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net/mlx5: DR, Add support for ConnectX-7 steering

Add support for a new SW format version that is implemented by ConnectX-7. Except for several differences, the STEv2 is identical to STEv1, so for most callbacks the STEv2 context struct will call STEv1 functions.

Yevgeny Kliteynik committed 4 years ago

Commit 6862c781 parent 638a07f11 files · +436 −110Browse files

Unified · Split

11 files
  1. drivers/net/ethernet/mellanox/mlx5/core/Makefile +1 −0
  2. drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c +1 −1
  3. drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c +4 −4
  4. drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +2 −0
  5. drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +1 −0
  6. drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c +99 −103
  7. drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.h +94 −0
  8. drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v2.c +231 −0
  9. drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c +1 −1
  10. drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h +1 −1
  11. include/linux/mlx5/mlx5_ifc.h +1 −0
drivers/net/ethernet/mellanox/mlx5/core/Makefile+1−0
@@ -103,6 +103,7 @@ mlx5_core-$(CONFIG_MLX5_SW_STEERING) += steering/dr_domain.o steering/dr_table.o · 102 unmodified lines
103 steering/dr_icm_pool.o steering/dr_buddy.o \103 steering/dr_icm_pool.o steering/dr_buddy.o \
104 steering/dr_ste.o steering/dr_send.o \104 steering/dr_ste.o steering/dr_send.o \
105 steering/dr_ste_v0.o steering/dr_ste_v1.o \105 steering/dr_ste_v0.o steering/dr_ste_v1.o \
106 steering/dr_ste_v2.o \
106 steering/dr_cmd.o steering/dr_fw.o \107 steering/dr_cmd.o steering/dr_fw.o \
107 steering/dr_action.o steering/fs_dr.o \108 steering/dr_action.o steering/fs_dr.o \
108 steering/dr_dbg.o109 steering/dr_dbg.o
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c+1−1
@@ -8,7 +8,7 @@ · 7 unmodified lines
8#define DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, dmn_type) \8#define DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, dmn_type) \
9 ((dmn)->info.caps.dmn_type##_sw_owner || \9 ((dmn)->info.caps.dmn_type##_sw_owner || \
10 ((dmn)->info.caps.dmn_type##_sw_owner_v2 && \10 ((dmn)->info.caps.dmn_type##_sw_owner_v2 && \
11 (dmn)->info.caps.sw_format_ver <= MLX5_STEERING_FORMAT_CONNECTX_6DX))11 (dmn)->info.caps.sw_format_ver <= MLX5_STEERING_FORMAT_CONNECTX_7))
12 12
13static void dr_domain_init_csum_recalc_fts(struct mlx5dr_domain *dmn)13static void dr_domain_init_csum_recalc_fts(struct mlx5dr_domain *dmn)
14{14{
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c+4−4
@@ -108,7 +108,7 @@ dr_mask_is_vxlan_gpe_set(struct mlx5dr_match_misc3 *misc3) · 107 unmodified lines
108static bool108static bool
109dr_matcher_supp_vxlan_gpe(struct mlx5dr_cmd_caps *caps)109dr_matcher_supp_vxlan_gpe(struct mlx5dr_cmd_caps *caps)
110{110{
111 return (caps->sw_format_ver == MLX5_STEERING_FORMAT_CONNECTX_6DX) ||111 return (caps->sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) ||
112 (caps->flex_protocols & MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED);112 (caps->flex_protocols & MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED);
113}113}
114 114
@@ -149,7 +149,7 @@ static bool dr_mask_is_tnl_geneve_tlv_opt_exist_set(struct mlx5dr_match_misc *mi · 34 unmodified lines
149static bool149static bool
150dr_matcher_supp_tnl_geneve(struct mlx5dr_cmd_caps *caps)150dr_matcher_supp_tnl_geneve(struct mlx5dr_cmd_caps *caps)
151{151{
152 return (caps->sw_format_ver == MLX5_STEERING_FORMAT_CONNECTX_6DX) ||152 return (caps->sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) ||
153 (caps->flex_protocols & MLX5_FLEX_PARSER_GENEVE_ENABLED);153 (caps->flex_protocols & MLX5_FLEX_PARSER_GENEVE_ENABLED);
154}154}
155 155
@@ -266,13 +266,13 @@ static bool dr_mask_is_tnl_gtpu_any(struct mlx5dr_match_param *mask, · 110 unmodified lines
266 266
267static int dr_matcher_supp_icmp_v4(struct mlx5dr_cmd_caps *caps)267static int dr_matcher_supp_icmp_v4(struct mlx5dr_cmd_caps *caps)
268{268{
269 return (caps->sw_format_ver == MLX5_STEERING_FORMAT_CONNECTX_6DX) ||269 return (caps->sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) ||
270 (caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V4_ENABLED);270 (caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V4_ENABLED);
271}271}
272 272
273static int dr_matcher_supp_icmp_v6(struct mlx5dr_cmd_caps *caps)273static int dr_matcher_supp_icmp_v6(struct mlx5dr_cmd_caps *caps)
274{274{
275 return (caps->sw_format_ver == MLX5_STEERING_FORMAT_CONNECTX_6DX) ||275 return (caps->sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) ||
276 (caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V6_ENABLED);276 (caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V6_ENABLED);
277}277}
278 278
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c+2−0
@@ -1367,6 +1367,8 @@ struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version) · 1366 unmodified lines
1367 return mlx5dr_ste_get_ctx_v0();1367 return mlx5dr_ste_get_ctx_v0();
1368 else if (version == MLX5_STEERING_FORMAT_CONNECTX_6DX)1368 else if (version == MLX5_STEERING_FORMAT_CONNECTX_6DX)
1369 return mlx5dr_ste_get_ctx_v1();1369 return mlx5dr_ste_get_ctx_v1();
1370 else if (version == MLX5_STEERING_FORMAT_CONNECTX_7)
1371 return mlx5dr_ste_get_ctx_v2();
1370 1372
1371 return NULL;1373 return NULL;
1372}1374}
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h+1−0
@@ -201,5 +201,6 @@ struct mlx5dr_ste_ctx { · 200 unmodified lines
201 201
202struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v0(void);202struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v0(void);
203struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v1(void);203struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v1(void);
204struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v2(void);
204 205
205#endif /* _DR_STE_ */206#endif /* _DR_STE_ */
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c+99−103
@@ -3,7 +3,7 @@ · 2 unmodified lines
3 3
4#include <linux/types.h>4#include <linux/types.h>
5#include "mlx5_ifc_dr_ste_v1.h"5#include "mlx5_ifc_dr_ste_v1.h"
6#include "dr_ste.h"6#include "dr_ste_v1.h"
7 7
8#define DR_STE_CALC_DFNR_TYPE(lookup_type, inner) \8#define DR_STE_CALC_DFNR_TYPE(lookup_type, inner) \
9 ((inner) ? DR_STE_V1_LU_TYPE_##lookup_type##_I : \9 ((inner) ? DR_STE_V1_LU_TYPE_##lookup_type##_I : \
@@ -262,7 +262,7 @@ static void dr_ste_v1_set_entry_type(u8 *hw_ste_p, u8 entry_type) · 252 unmodified lines
262 MLX5_SET(ste_match_bwc_v1, hw_ste_p, entry_format, entry_type);262 MLX5_SET(ste_match_bwc_v1, hw_ste_p, entry_format, entry_type);
263}263}
264 264
265static void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr)265void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr)
266{266{
267 u64 index = miss_addr >> 6;267 u64 index = miss_addr >> 6;
268 268
@@ -270,7 +270,7 @@ static void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr) · 1 unmodified line
270 MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6, index);270 MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6, index);
271}271}
272 272
273static u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p)273u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p)
274{274{
275 u64 index =275 u64 index =
276 ((u64)MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6) |276 ((u64)MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6) |
@@ -279,12 +279,12 @@ static u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p) · 2 unmodified lines
279 return index << 6;279 return index << 6;
280}280}
281 281
282static void dr_ste_v1_set_byte_mask(u8 *hw_ste_p, u16 byte_mask)282void dr_ste_v1_set_byte_mask(u8 *hw_ste_p, u16 byte_mask)
283{283{
284 MLX5_SET(ste_match_bwc_v1, hw_ste_p, byte_mask, byte_mask);284 MLX5_SET(ste_match_bwc_v1, hw_ste_p, byte_mask, byte_mask);
285}285}
286 286
287static u16 dr_ste_v1_get_byte_mask(u8 *hw_ste_p)287u16 dr_ste_v1_get_byte_mask(u8 *hw_ste_p)
288{288{
289 return MLX5_GET(ste_match_bwc_v1, hw_ste_p, byte_mask);289 return MLX5_GET(ste_match_bwc_v1, hw_ste_p, byte_mask);
290}290}
@@ -295,13 +295,13 @@ static void dr_ste_v1_set_lu_type(u8 *hw_ste_p, u16 lu_type) · 4 unmodified lines
295 MLX5_SET(ste_match_bwc_v1, hw_ste_p, match_definer_ctx_idx, lu_type & 0xFF);295 MLX5_SET(ste_match_bwc_v1, hw_ste_p, match_definer_ctx_idx, lu_type & 0xFF);
296}296}
297 297
298static void dr_ste_v1_set_next_lu_type(u8 *hw_ste_p, u16 lu_type)298void dr_ste_v1_set_next_lu_type(u8 *hw_ste_p, u16 lu_type)
299{299{
300 MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_entry_format, lu_type >> 8);300 MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_entry_format, lu_type >> 8);
301 MLX5_SET(ste_match_bwc_v1, hw_ste_p, hash_definer_ctx_idx, lu_type & 0xFF);301 MLX5_SET(ste_match_bwc_v1, hw_ste_p, hash_definer_ctx_idx, lu_type & 0xFF);
302}302}
303 303
304static u16 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p)304u16 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p)
305{305{
306 u8 mode = MLX5_GET(ste_match_bwc_v1, hw_ste_p, next_entry_format);306 u8 mode = MLX5_GET(ste_match_bwc_v1, hw_ste_p, next_entry_format);
307 u8 index = MLX5_GET(ste_match_bwc_v1, hw_ste_p, hash_definer_ctx_idx);307 u8 index = MLX5_GET(ste_match_bwc_v1, hw_ste_p, hash_definer_ctx_idx);
@@ -314,7 +314,7 @@ static void dr_ste_v1_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi) · 6 unmodified lines
314 MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_63_48, gvmi);314 MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_63_48, gvmi);
315}315}
316 316
317static void dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size)317void dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size)
318{318{
319 u64 index = (icm_addr >> 5) | ht_size;319 u64 index = (icm_addr >> 5) | ht_size;
320 320
@@ -322,8 +322,7 @@ static void dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size) · 1 unmodified line
322 MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_31_5_size, index);322 MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_31_5_size, index);
323}323}
324 324
325static void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type,325void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type, bool is_rx, u16 gvmi)
326 bool is_rx, u16 gvmi)
327{326{
328 dr_ste_v1_set_lu_type(hw_ste_p, lu_type);327 dr_ste_v1_set_lu_type(hw_ste_p, lu_type);
329 dr_ste_v1_set_next_lu_type(hw_ste_p, MLX5DR_STE_LU_TYPE_DONT_CARE);328 dr_ste_v1_set_next_lu_type(hw_ste_p, MLX5DR_STE_LU_TYPE_DONT_CARE);
@@ -333,8 +332,7 @@ static void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type, · 3 unmodified lines
333 MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_63_48, gvmi);332 MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_63_48, gvmi);
334}333}
335 334
336static void dr_ste_v1_prepare_for_postsend(u8 *hw_ste_p,335void dr_ste_v1_prepare_for_postsend(u8 *hw_ste_p, u32 ste_size)
337 u32 ste_size)
338{336{
339 u8 *tag = hw_ste_p + DR_STE_SIZE_CTRL;337 u8 *tag = hw_ste_p + DR_STE_SIZE_CTRL;
340 u8 *mask = tag + DR_STE_SIZE_TAG;338 u8 *mask = tag + DR_STE_SIZE_TAG;
@@ -511,12 +509,12 @@ static void dr_ste_v1_arr_init_next_match(u8 **last_ste, · 170 unmodified lines
511 memset(action, 0, MLX5_FLD_SZ_BYTES(ste_mask_and_match_v1, action));509 memset(action, 0, MLX5_FLD_SZ_BYTES(ste_mask_and_match_v1, action));
512}510}
513 511
514static void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn,512void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn,
515 u8 *action_type_set,513 u8 *action_type_set,
516 u32 actions_caps,514 u32 actions_caps,
517 u8 *last_ste,515 u8 *last_ste,
518 struct mlx5dr_ste_actions_attr *attr,516 struct mlx5dr_ste_actions_attr *attr,
519 u32 *added_stes)517 u32 *added_stes)
520{518{
521 u8 *action = MLX5_ADDR_OF(ste_match_bwc_v1, last_ste, action);519 u8 *action = MLX5_ADDR_OF(ste_match_bwc_v1, last_ste, action);
522 u8 action_sz = DR_STE_ACTION_DOUBLE_SZ;520 u8 action_sz = DR_STE_ACTION_DOUBLE_SZ;
@@ -635,12 +633,12 @@ static void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn, · 112 unmodified lines
635 dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);633 dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);
636}634}
637 635
638static void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn,636void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn,
639 u8 *action_type_set,637 u8 *action_type_set,
640 u32 actions_caps,638 u32 actions_caps,
641 u8 *last_ste,639 u8 *last_ste,
642 struct mlx5dr_ste_actions_attr *attr,640 struct mlx5dr_ste_actions_attr *attr,
643 u32 *added_stes)641 u32 *added_stes)
644{642{
645 u8 *action = MLX5_ADDR_OF(ste_match_bwc_v1, last_ste, action);643 u8 *action = MLX5_ADDR_OF(ste_match_bwc_v1, last_ste, action);
646 u8 action_sz = DR_STE_ACTION_DOUBLE_SZ;644 u8 action_sz = DR_STE_ACTION_DOUBLE_SZ;
@@ -808,11 +806,11 @@ static void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn, · 161 unmodified lines
808 dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);806 dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);
809}807}
810 808
811static void dr_ste_v1_set_action_set(u8 *d_action,809void dr_ste_v1_set_action_set(u8 *d_action,
812 u8 hw_field,810 u8 hw_field,
813 u8 shifter,811 u8 shifter,
814 u8 length,812 u8 length,
815 u32 data)813 u32 data)
816{814{
817 shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;815 shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
818 MLX5_SET(ste_double_action_set_v1, d_action, action_id, DR_STE_V1_ACTION_ID_SET);816 MLX5_SET(ste_double_action_set_v1, d_action, action_id, DR_STE_V1_ACTION_ID_SET);
@@ -822,11 +820,11 @@ static void dr_ste_v1_set_action_set(u8 *d_action, · 3 unmodified lines
822 MLX5_SET(ste_double_action_set_v1, d_action, inline_data, data);820 MLX5_SET(ste_double_action_set_v1, d_action, inline_data, data);
823}821}
824 822
825static void dr_ste_v1_set_action_add(u8 *d_action,823void dr_ste_v1_set_action_add(u8 *d_action,
826 u8 hw_field,824 u8 hw_field,
827 u8 shifter,825 u8 shifter,
828 u8 length,826 u8 length,
829 u32 data)827 u32 data)
830{828{
831 shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;829 shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
832 MLX5_SET(ste_double_action_add_v1, d_action, action_id, DR_STE_V1_ACTION_ID_ADD);830 MLX5_SET(ste_double_action_add_v1, d_action, action_id, DR_STE_V1_ACTION_ID_ADD);
@@ -836,12 +834,12 @@ static void dr_ste_v1_set_action_add(u8 *d_action, · 3 unmodified lines
836 MLX5_SET(ste_double_action_add_v1, d_action, add_value, data);834 MLX5_SET(ste_double_action_add_v1, d_action, add_value, data);
837}835}
838 836
839static void dr_ste_v1_set_action_copy(u8 *d_action,837void dr_ste_v1_set_action_copy(u8 *d_action,
840 u8 dst_hw_field,838 u8 dst_hw_field,
841 u8 dst_shifter,839 u8 dst_shifter,
842 u8 dst_len,840 u8 dst_len,
843 u8 src_hw_field,841 u8 src_hw_field,
844 u8 src_shifter)842 u8 src_shifter)
845{843{
846 dst_shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;844 dst_shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
847 src_shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;845 src_shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
@@ -856,11 +854,11 @@ static void dr_ste_v1_set_action_copy(u8 *d_action, · 8 unmodified lines
856#define DR_STE_DECAP_L3_ACTION_NUM 8854#define DR_STE_DECAP_L3_ACTION_NUM 8
857#define DR_STE_L2_HDR_MAX_SZ 20855#define DR_STE_L2_HDR_MAX_SZ 20
858 856
859static int dr_ste_v1_set_action_decap_l3_list(void *data,857int dr_ste_v1_set_action_decap_l3_list(void *data,
860 u32 data_sz,858 u32 data_sz,
861 u8 *hw_action,859 u8 *hw_action,
862 u32 hw_action_sz,860 u32 hw_action_sz,
863 u16 *used_hw_action_num)861 u16 *used_hw_action_num)
864{862{
865 u8 padded_data[DR_STE_L2_HDR_MAX_SZ] = {};863 u8 padded_data[DR_STE_L2_HDR_MAX_SZ] = {};
866 void *data_ptr = padded_data;864 void *data_ptr = padded_data;
@@ -985,8 +983,8 @@ static int dr_ste_v1_build_eth_l2_src_dst_tag(struct mlx5dr_match_param *value, · 118 unmodified lines
985 return 0;983 return 0;
986}984}
987 985
988static void dr_ste_v1_build_eth_l2_src_dst_init(struct mlx5dr_ste_build *sb,986void dr_ste_v1_build_eth_l2_src_dst_init(struct mlx5dr_ste_build *sb,
989 struct mlx5dr_match_param *mask)987 struct mlx5dr_match_param *mask)
990{988{
991 dr_ste_v1_build_eth_l2_src_dst_bit_mask(mask, sb->inner, sb->bit_mask);989 dr_ste_v1_build_eth_l2_src_dst_bit_mask(mask, sb->inner, sb->bit_mask);
992 990
@@ -1009,8 +1007,8 @@ static int dr_ste_v1_build_eth_l3_ipv6_dst_tag(struct mlx5dr_match_param *value, · 16 unmodified lines
1009 return 0;1007 return 0;
1010}1008}
1011 1009
1012static void dr_ste_v1_build_eth_l3_ipv6_dst_init(struct mlx5dr_ste_build *sb,1010void dr_ste_v1_build_eth_l3_ipv6_dst_init(struct mlx5dr_ste_build *sb,
1013 struct mlx5dr_match_param *mask)1011 struct mlx5dr_match_param *mask)
1014{1012{
1015 dr_ste_v1_build_eth_l3_ipv6_dst_tag(mask, sb, sb->bit_mask);1013 dr_ste_v1_build_eth_l3_ipv6_dst_tag(mask, sb, sb->bit_mask);
1016 1014
@@ -1033,8 +1031,8 @@ static int dr_ste_v1_build_eth_l3_ipv6_src_tag(struct mlx5dr_match_param *value, · 16 unmodified lines
1033 return 0;1031 return 0;
1034}1032}
1035 1033
1036static void dr_ste_v1_build_eth_l3_ipv6_src_init(struct mlx5dr_ste_build *sb,1034void dr_ste_v1_build_eth_l3_ipv6_src_init(struct mlx5dr_ste_build *sb,
1037 struct mlx5dr_match_param *mask)1035 struct mlx5dr_match_param *mask)
1038{1036{
1039 dr_ste_v1_build_eth_l3_ipv6_src_tag(mask, sb, sb->bit_mask);1037 dr_ste_v1_build_eth_l3_ipv6_src_tag(mask, sb, sb->bit_mask);
1040 1038
@@ -1068,8 +1066,8 @@ static int dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag(struct mlx5dr_match_param *va · 27 unmodified lines
1068 return 0;1066 return 0;
1069}1067}
1070 1068
1071static void dr_ste_v1_build_eth_l3_ipv4_5_tuple_init(struct mlx5dr_ste_build *sb,1069void dr_ste_v1_build_eth_l3_ipv4_5_tuple_init(struct mlx5dr_ste_build *sb,
1072 struct mlx5dr_match_param *mask)1070 struct mlx5dr_match_param *mask)
1073{1071{
1074 dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag(mask, sb, sb->bit_mask);1072 dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag(mask, sb, sb->bit_mask);
1075 1073
@@ -1209,8 +1207,8 @@ static int dr_ste_v1_build_eth_l2_src_tag(struct mlx5dr_match_param *value, · 133 unmodified lines
1209 return dr_ste_v1_build_eth_l2_src_or_dst_tag(value, sb->inner, tag);1207 return dr_ste_v1_build_eth_l2_src_or_dst_tag(value, sb->inner, tag);
1210}1208}
1211 1209
1212static void dr_ste_v1_build_eth_l2_src_init(struct mlx5dr_ste_build *sb,1210void dr_ste_v1_build_eth_l2_src_init(struct mlx5dr_ste_build *sb,
1213 struct mlx5dr_match_param *mask)1211 struct mlx5dr_match_param *mask)
1214{1212{
1215 dr_ste_v1_build_eth_l2_src_bit_mask(mask, sb->inner, sb->bit_mask);1213 dr_ste_v1_build_eth_l2_src_bit_mask(mask, sb->inner, sb->bit_mask);
1216 1214
@@ -1242,8 +1240,8 @@ static int dr_ste_v1_build_eth_l2_dst_tag(struct mlx5dr_match_param *value, · 25 unmodified lines
1242 return dr_ste_v1_build_eth_l2_src_or_dst_tag(value, sb->inner, tag);1240 return dr_ste_v1_build_eth_l2_src_or_dst_tag(value, sb->inner, tag);
1243}1241}
1244 1242
1245static void dr_ste_v1_build_eth_l2_dst_init(struct mlx5dr_ste_build *sb,1243void dr_ste_v1_build_eth_l2_dst_init(struct mlx5dr_ste_build *sb,
1246 struct mlx5dr_match_param *mask)1244 struct mlx5dr_match_param *mask)
1247{1245{
1248 dr_ste_v1_build_eth_l2_dst_bit_mask(mask, sb->inner, sb->bit_mask);1246 dr_ste_v1_build_eth_l2_dst_bit_mask(mask, sb->inner, sb->bit_mask);
1249 1247
@@ -1322,8 +1320,8 @@ static int dr_ste_v1_build_eth_l2_tnl_tag(struct mlx5dr_match_param *value, · 72 unmodified lines
1322 return 0;1320 return 0;
1323}1321}
1324 1322
1325static void dr_ste_v1_build_eth_l2_tnl_init(struct mlx5dr_ste_build *sb,1323void dr_ste_v1_build_eth_l2_tnl_init(struct mlx5dr_ste_build *sb,
1326 struct mlx5dr_match_param *mask)1324 struct mlx5dr_match_param *mask)
1327{1325{
1328 dr_ste_v1_build_eth_l2_tnl_bit_mask(mask, sb->inner, sb->bit_mask);1326 dr_ste_v1_build_eth_l2_tnl_bit_mask(mask, sb->inner, sb->bit_mask);
1329 1327
@@ -1344,8 +1342,8 @@ static int dr_ste_v1_build_eth_l3_ipv4_misc_tag(struct mlx5dr_match_param *value · 14 unmodified lines
1344 return 0;1342 return 0;
1345}1343}
1346 1344
1347static void dr_ste_v1_build_eth_l3_ipv4_misc_init(struct mlx5dr_ste_build *sb,1345void dr_ste_v1_build_eth_l3_ipv4_misc_init(struct mlx5dr_ste_build *sb,
1348 struct mlx5dr_match_param *mask)1346 struct mlx5dr_match_param *mask)
1349{1347{
1350 dr_ste_v1_build_eth_l3_ipv4_misc_tag(mask, sb, sb->bit_mask);1348 dr_ste_v1_build_eth_l3_ipv4_misc_tag(mask, sb, sb->bit_mask);
1351 1349
@@ -1384,8 +1382,8 @@ static int dr_ste_v1_build_eth_ipv6_l3_l4_tag(struct mlx5dr_match_param *value, · 32 unmodified lines
1384 return 0;1382 return 0;
1385}1383}
1386 1384
1387static void dr_ste_v1_build_eth_ipv6_l3_l4_init(struct mlx5dr_ste_build *sb,1385void dr_ste_v1_build_eth_ipv6_l3_l4_init(struct mlx5dr_ste_build *sb,
1388 struct mlx5dr_match_param *mask)1386 struct mlx5dr_match_param *mask)
1389{1387{
1390 dr_ste_v1_build_eth_ipv6_l3_l4_tag(mask, sb, sb->bit_mask);1388 dr_ste_v1_build_eth_ipv6_l3_l4_tag(mask, sb, sb->bit_mask);
1391 1389
@@ -1408,8 +1406,8 @@ static int dr_ste_v1_build_mpls_tag(struct mlx5dr_match_param *value, · 16 unmodified lines
1408 return 0;1406 return 0;
1409}1407}
1410 1408
1411static void dr_ste_v1_build_mpls_init(struct mlx5dr_ste_build *sb,1409void dr_ste_v1_build_mpls_init(struct mlx5dr_ste_build *sb,
1412 struct mlx5dr_match_param *mask)1410 struct mlx5dr_match_param *mask)
1413{1411{
1414 dr_ste_v1_build_mpls_tag(mask, sb, sb->bit_mask);1412 dr_ste_v1_build_mpls_tag(mask, sb, sb->bit_mask);
1415 1413
@@ -1435,8 +1433,8 @@ static int dr_ste_v1_build_tnl_gre_tag(struct mlx5dr_match_param *value, · 19 unmodified lines
1435 return 0;1433 return 0;
1436}1434}
1437 1435
1438static void dr_ste_v1_build_tnl_gre_init(struct mlx5dr_ste_build *sb,1436void dr_ste_v1_build_tnl_gre_init(struct mlx5dr_ste_build *sb,
1439 struct mlx5dr_match_param *mask)1437 struct mlx5dr_match_param *mask)
1440{1438{
1441 dr_ste_v1_build_tnl_gre_tag(mask, sb, sb->bit_mask);1439 dr_ste_v1_build_tnl_gre_tag(mask, sb, sb->bit_mask);
1442 1440
@@ -1480,8 +1478,8 @@ static int dr_ste_v1_build_tnl_mpls_tag(struct mlx5dr_match_param *value, · 37 unmodified lines
1480 return 0;1478 return 0;
1481}1479}
1482 1480
1483static void dr_ste_v1_build_tnl_mpls_init(struct mlx5dr_ste_build *sb,1481void dr_ste_v1_build_tnl_mpls_init(struct mlx5dr_ste_build *sb,
1484 struct mlx5dr_match_param *mask)1482 struct mlx5dr_match_param *mask)
1485{1483{
1486 dr_ste_v1_build_tnl_mpls_tag(mask, sb, sb->bit_mask);1484 dr_ste_v1_build_tnl_mpls_tag(mask, sb, sb->bit_mask);
1487 1485
@@ -1515,8 +1513,8 @@ static int dr_ste_v1_build_tnl_mpls_over_udp_tag(struct mlx5dr_match_param *valu · 27 unmodified lines
1515 return 0;1513 return 0;
1516}1514}
1517 1515
1518static void dr_ste_v1_build_tnl_mpls_over_udp_init(struct mlx5dr_ste_build *sb,1516void dr_ste_v1_build_tnl_mpls_over_udp_init(struct mlx5dr_ste_build *sb,
1519 struct mlx5dr_match_param *mask)1517 struct mlx5dr_match_param *mask)
1520{1518{
1521 dr_ste_v1_build_tnl_mpls_over_udp_tag(mask, sb, sb->bit_mask);1519 dr_ste_v1_build_tnl_mpls_over_udp_tag(mask, sb, sb->bit_mask);
1522 1520
@@ -1556,8 +1554,8 @@ static int dr_ste_v1_build_tnl_mpls_over_gre_tag(struct mlx5dr_match_param *valu · 33 unmodified lines
1556 return 0;1554 return 0;
1557}1555}
1558 1556
1559static void dr_ste_v1_build_tnl_mpls_over_gre_init(struct mlx5dr_ste_build *sb,1557void dr_ste_v1_build_tnl_mpls_over_gre_init(struct mlx5dr_ste_build *sb,
1560 struct mlx5dr_match_param *mask)1558 struct mlx5dr_match_param *mask)
1561{1559{
1562 dr_ste_v1_build_tnl_mpls_over_gre_tag(mask, sb, sb->bit_mask);1560 dr_ste_v1_build_tnl_mpls_over_gre_tag(mask, sb, sb->bit_mask);
1563 1561
@@ -1603,8 +1601,8 @@ static int dr_ste_v1_build_icmp_tag(struct mlx5dr_match_param *value, · 39 unmodified lines
1603 return 0;1601 return 0;
1604}1602}
1605 1603
1606static void dr_ste_v1_build_icmp_init(struct mlx5dr_ste_build *sb,1604void dr_ste_v1_build_icmp_init(struct mlx5dr_ste_build *sb,
1607 struct mlx5dr_match_param *mask)1605 struct mlx5dr_match_param *mask)
1608{1606{
1609 dr_ste_v1_build_icmp_tag(mask, sb, sb->bit_mask);1607 dr_ste_v1_build_icmp_tag(mask, sb, sb->bit_mask);
1610 1608
@@ -1625,8 +1623,8 @@ static int dr_ste_v1_build_general_purpose_tag(struct mlx5dr_match_param *value, · 14 unmodified lines
1625 return 0;1623 return 0;
1626}1624}
1627 1625
1628static void dr_ste_v1_build_general_purpose_init(struct mlx5dr_ste_build *sb,1626void dr_ste_v1_build_general_purpose_init(struct mlx5dr_ste_build *sb,
1629 struct mlx5dr_match_param *mask)1627 struct mlx5dr_match_param *mask)
1630{1628{
1631 dr_ste_v1_build_general_purpose_tag(mask, sb, sb->bit_mask);1629 dr_ste_v1_build_general_purpose_tag(mask, sb, sb->bit_mask);
1632 1630
@@ -1652,8 +1650,8 @@ static int dr_ste_v1_build_eth_l4_misc_tag(struct mlx5dr_match_param *value, · 19 unmodified lines
1652 return 0;1650 return 0;
1653}1651}
1654 1652
1655static void dr_ste_v1_build_eth_l4_misc_init(struct mlx5dr_ste_build *sb,1653void dr_ste_v1_build_eth_l4_misc_init(struct mlx5dr_ste_build *sb,
1656 struct mlx5dr_match_param *mask)1654 struct mlx5dr_match_param *mask)
1657{1655{
1658 dr_ste_v1_build_eth_l4_misc_tag(mask, sb, sb->bit_mask);1656 dr_ste_v1_build_eth_l4_misc_tag(mask, sb, sb->bit_mask);
1659 1657
@@ -1682,9 +1680,8 @@ dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag(struct mlx5dr_match_param *value, · 22 unmodified lines
1682 return 0;1680 return 0;
1683}1681}
1684 1682
1685static void1683void dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init(struct mlx5dr_ste_build *sb,
1686dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init(struct mlx5dr_ste_build *sb,1684 struct mlx5dr_match_param *mask)
1687 struct mlx5dr_match_param *mask)
1688{1685{
1689 dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag(mask, sb, sb->bit_mask);1686 dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag(mask, sb, sb->bit_mask);
1690 1687
@@ -1712,9 +1709,8 @@ dr_ste_v1_build_flex_parser_tnl_geneve_tag(struct mlx5dr_match_param *value, · 21 unmodified lines
1712 return 0;1709 return 0;
1713}1710}
1714 1711
1715static void1712void dr_ste_v1_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb,
1716dr_ste_v1_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb,1713 struct mlx5dr_match_param *mask)
1717 struct mlx5dr_match_param *mask)
1718{1714{
1719 dr_ste_v1_build_flex_parser_tnl_geneve_tag(mask, sb, sb->bit_mask);1715 dr_ste_v1_build_flex_parser_tnl_geneve_tag(mask, sb, sb->bit_mask);
1720 1716
@@ -1735,8 +1731,8 @@ static int dr_ste_v1_build_tnl_header_0_1_tag(struct mlx5dr_match_param *value, · 14 unmodified lines
1735 return 0;1731 return 0;
1736}1732}
1737 1733
1738static void dr_ste_v1_build_tnl_header_0_1_init(struct mlx5dr_ste_build *sb,1734void dr_ste_v1_build_tnl_header_0_1_init(struct mlx5dr_ste_build *sb,
1739 struct mlx5dr_match_param *mask)1735 struct mlx5dr_match_param *mask)
1740{1736{
1741 sb->lu_type = DR_STE_V1_LU_TYPE_FLEX_PARSER_TNL_HEADER;1737 sb->lu_type = DR_STE_V1_LU_TYPE_FLEX_PARSER_TNL_HEADER;
1742 dr_ste_v1_build_tnl_header_0_1_tag(mask, sb, sb->bit_mask);1738 dr_ste_v1_build_tnl_header_0_1_tag(mask, sb, sb->bit_mask);
@@ -1758,8 +1754,8 @@ static int dr_ste_v1_build_register_0_tag(struct mlx5dr_match_param *value, · 15 unmodified lines
1758 return 0;1754 return 0;
1759}1755}
1760 1756
1761static void dr_ste_v1_build_register_0_init(struct mlx5dr_ste_build *sb,1757void dr_ste_v1_build_register_0_init(struct mlx5dr_ste_build *sb,
1762 struct mlx5dr_match_param *mask)1758 struct mlx5dr_match_param *mask)
1763{1759{
1764 dr_ste_v1_build_register_0_tag(mask, sb, sb->bit_mask);1760 dr_ste_v1_build_register_0_tag(mask, sb, sb->bit_mask);
1765 1761
@@ -1782,8 +1778,8 @@ static int dr_ste_v1_build_register_1_tag(struct mlx5dr_match_param *value, · 16 unmodified lines
1782 return 0;1778 return 0;
1783}1779}
1784 1780
1785static void dr_ste_v1_build_register_1_init(struct mlx5dr_ste_build *sb,1781void dr_ste_v1_build_register_1_init(struct mlx5dr_ste_build *sb,
1786 struct mlx5dr_match_param *mask)1782 struct mlx5dr_match_param *mask)
1787{1783{
1788 dr_ste_v1_build_register_1_tag(mask, sb, sb->bit_mask);1784 dr_ste_v1_build_register_1_tag(mask, sb, sb->bit_mask);
1789 1785
@@ -1846,8 +1842,8 @@ static int dr_ste_v1_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value, · 56 unmodified lines
1846 return 0;1842 return 0;
1847}1843}
1848 1844
1849static void dr_ste_v1_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb,1845void dr_ste_v1_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb,
1850 struct mlx5dr_match_param *mask)1846 struct mlx5dr_match_param *mask)
1851{1847{
1852 dr_ste_v1_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask);1848 dr_ste_v1_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask);
1853 1849
@@ -1901,8 +1897,8 @@ static int dr_ste_v1_build_felx_parser_tag(struct mlx5dr_match_param *value, · 47 unmodified lines
1901 return 0;1897 return 0;
1902}1898}
1903 1899
1904static void dr_ste_v1_build_flex_parser_0_init(struct mlx5dr_ste_build *sb,1900void dr_ste_v1_build_flex_parser_0_init(struct mlx5dr_ste_build *sb,
1905 struct mlx5dr_match_param *mask)1901 struct mlx5dr_match_param *mask)
1906{1902{
1907 sb->lu_type = DR_STE_V1_LU_TYPE_FLEX_PARSER_0;1903 sb->lu_type = DR_STE_V1_LU_TYPE_FLEX_PARSER_0;
1908 dr_ste_v1_build_felx_parser_tag(mask, sb, sb->bit_mask);1904 dr_ste_v1_build_felx_parser_tag(mask, sb, sb->bit_mask);
@@ -1910,8 +1906,8 @@ static void dr_ste_v1_build_flex_parser_0_init(struct mlx5dr_ste_build *sb, · 1 unmodified line
1910 sb->ste_build_tag_func = &dr_ste_v1_build_felx_parser_tag;1906 sb->ste_build_tag_func = &dr_ste_v1_build_felx_parser_tag;
1911}1907}
1912 1908
1913static void dr_ste_v1_build_flex_parser_1_init(struct mlx5dr_ste_build *sb,1909void dr_ste_v1_build_flex_parser_1_init(struct mlx5dr_ste_build *sb,
1914 struct mlx5dr_match_param *mask)1910 struct mlx5dr_match_param *mask)
1915{1911{
1916 sb->lu_type = DR_STE_V1_LU_TYPE_FLEX_PARSER_1;1912 sb->lu_type = DR_STE_V1_LU_TYPE_FLEX_PARSER_1;
1917 dr_ste_v1_build_felx_parser_tag(mask, sb, sb->bit_mask);1913 dr_ste_v1_build_felx_parser_tag(mask, sb, sb->bit_mask);
@@ -1935,7 +1931,7 @@ dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_tag(struct mlx5dr_match_param *va · 17 unmodified lines
1935 return 0;1931 return 0;
1936}1932}
1937 1933
1938static void1934void
1939dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init(struct mlx5dr_ste_build *sb,1935dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init(struct mlx5dr_ste_build *sb,
1940 struct mlx5dr_match_param *mask)1936 struct mlx5dr_match_param *mask)
1941{1937{
@@ -1968,7 +1964,7 @@ dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_tag(struct mlx5dr_match_par · 26 unmodified lines
1968 return 0;1964 return 0;
1969}1965}
1970 1966
1971static void1967void
1972dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init(struct mlx5dr_ste_build *sb,1968dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init(struct mlx5dr_ste_build *sb,
1973 struct mlx5dr_match_param *mask)1969 struct mlx5dr_match_param *mask)
1974{1970{
@@ -1991,8 +1987,8 @@ static int dr_ste_v1_build_flex_parser_tnl_gtpu_tag(struct mlx5dr_match_param *v · 16 unmodified lines
1991 return 0;1987 return 0;
1992}1988}
1993 1989
1994static void dr_ste_v1_build_flex_parser_tnl_gtpu_init(struct mlx5dr_ste_build *sb,1990void dr_ste_v1_build_flex_parser_tnl_gtpu_init(struct mlx5dr_ste_build *sb,
1995 struct mlx5dr_match_param *mask)1991 struct mlx5dr_match_param *mask)
1996{1992{
1997 dr_ste_v1_build_flex_parser_tnl_gtpu_tag(mask, sb, sb->bit_mask);1993 dr_ste_v1_build_flex_parser_tnl_gtpu_tag(mask, sb, sb->bit_mask);
1998 1994
@@ -2017,7 +2013,7 @@ dr_ste_v1_build_tnl_gtpu_flex_parser_0_tag(struct mlx5dr_match_param *value, · 18 unmodified lines
2017 return 0;2013 return 0;
2018}2014}
2019 2015
2020static void2016void
2021dr_ste_v1_build_tnl_gtpu_flex_parser_0_init(struct mlx5dr_ste_build *sb,2017dr_ste_v1_build_tnl_gtpu_flex_parser_0_init(struct mlx5dr_ste_build *sb,
2022 struct mlx5dr_match_param *mask)2018 struct mlx5dr_match_param *mask)
2023{2019{
@@ -2044,7 +2040,7 @@ dr_ste_v1_build_tnl_gtpu_flex_parser_1_tag(struct mlx5dr_match_param *value, · 20 unmodified lines
2044 return 0;2040 return 0;
2045}2041}
2046 2042
2047static void2043void
2048dr_ste_v1_build_tnl_gtpu_flex_parser_1_init(struct mlx5dr_ste_build *sb,2044dr_ste_v1_build_tnl_gtpu_flex_parser_1_init(struct mlx5dr_ste_build *sb,
2049 struct mlx5dr_match_param *mask)2045 struct mlx5dr_match_param *mask)
2050{2046{
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.h+94−0
@@ -0,0 +1,94 @@
1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2/* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
3
4#ifndef _DR_STE_V1_
5#define _DR_STE_V1_
6
7#include "dr_types.h"
8#include "dr_ste.h"
9
10void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr);
11u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p);
12void dr_ste_v1_set_byte_mask(u8 *hw_ste_p, u16 byte_mask);
13u16 dr_ste_v1_get_byte_mask(u8 *hw_ste_p);
14void dr_ste_v1_set_next_lu_type(u8 *hw_ste_p, u16 lu_type);
15u16 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p);
16void dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size);
17void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type, bool is_rx, u16 gvmi);
18void dr_ste_v1_prepare_for_postsend(u8 *hw_ste_p, u32 ste_size);
19void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn, u8 *action_type_set,
20 u32 actions_caps, u8 *last_ste,
21 struct mlx5dr_ste_actions_attr *attr, u32 *added_stes);
22void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn, u8 *action_type_set,
23 u32 actions_caps, u8 *last_ste,
24 struct mlx5dr_ste_actions_attr *attr, u32 *added_stes);
25void dr_ste_v1_set_action_set(u8 *d_action, u8 hw_field, u8 shifter,
26 u8 length, u32 data);
27void dr_ste_v1_set_action_add(u8 *d_action, u8 hw_field, u8 shifter,
28 u8 length, u32 data);
29void dr_ste_v1_set_action_copy(u8 *d_action, u8 dst_hw_field, u8 dst_shifter,
30 u8 dst_len, u8 src_hw_field, u8 src_shifter);
31int dr_ste_v1_set_action_decap_l3_list(void *data, u32 data_sz, u8 *hw_action,
32 u32 hw_action_sz, u16 *used_hw_action_num);
33void dr_ste_v1_build_eth_l2_src_dst_init(struct mlx5dr_ste_build *sb,
34 struct mlx5dr_match_param *mask);
35void dr_ste_v1_build_eth_l3_ipv6_dst_init(struct mlx5dr_ste_build *sb,
36 struct mlx5dr_match_param *mask);
37void dr_ste_v1_build_eth_l3_ipv6_src_init(struct mlx5dr_ste_build *sb,
38 struct mlx5dr_match_param *mask);
39void dr_ste_v1_build_eth_l3_ipv4_5_tuple_init(struct mlx5dr_ste_build *sb,
40 struct mlx5dr_match_param *mask);
41void dr_ste_v1_build_eth_l2_src_init(struct mlx5dr_ste_build *sb,
42 struct mlx5dr_match_param *mask);
43void dr_ste_v1_build_eth_l2_dst_init(struct mlx5dr_ste_build *sb,
44 struct mlx5dr_match_param *mask);
45void dr_ste_v1_build_eth_l2_tnl_init(struct mlx5dr_ste_build *sb,
46 struct mlx5dr_match_param *mask);
47void dr_ste_v1_build_eth_l3_ipv4_misc_init(struct mlx5dr_ste_build *sb,
48 struct mlx5dr_match_param *mask);
49void dr_ste_v1_build_eth_ipv6_l3_l4_init(struct mlx5dr_ste_build *sb,
50 struct mlx5dr_match_param *mask);
51void dr_ste_v1_build_mpls_init(struct mlx5dr_ste_build *sb,
52 struct mlx5dr_match_param *mask);
53void dr_ste_v1_build_tnl_gre_init(struct mlx5dr_ste_build *sb,
54 struct mlx5dr_match_param *mask);
55void dr_ste_v1_build_tnl_mpls_init(struct mlx5dr_ste_build *sb,
56 struct mlx5dr_match_param *mask);
57void dr_ste_v1_build_tnl_mpls_over_udp_init(struct mlx5dr_ste_build *sb,
58 struct mlx5dr_match_param *mask);
59void dr_ste_v1_build_tnl_mpls_over_gre_init(struct mlx5dr_ste_build *sb,
60 struct mlx5dr_match_param *mask);
61void dr_ste_v1_build_icmp_init(struct mlx5dr_ste_build *sb,
62 struct mlx5dr_match_param *mask);
63void dr_ste_v1_build_general_purpose_init(struct mlx5dr_ste_build *sb,
64 struct mlx5dr_match_param *mask);
65void dr_ste_v1_build_eth_l4_misc_init(struct mlx5dr_ste_build *sb,
66 struct mlx5dr_match_param *mask);
67void dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init(struct mlx5dr_ste_build *sb,
68 struct mlx5dr_match_param *mask);
69void dr_ste_v1_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb,
70 struct mlx5dr_match_param *mask);
71void dr_ste_v1_build_tnl_header_0_1_init(struct mlx5dr_ste_build *sb,
72 struct mlx5dr_match_param *mask);
73void dr_ste_v1_build_register_0_init(struct mlx5dr_ste_build *sb,
74 struct mlx5dr_match_param *mask);
75void dr_ste_v1_build_register_1_init(struct mlx5dr_ste_build *sb,
76 struct mlx5dr_match_param *mask);
77void dr_ste_v1_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb,
78 struct mlx5dr_match_param *mask);
79void dr_ste_v1_build_flex_parser_0_init(struct mlx5dr_ste_build *sb,
80 struct mlx5dr_match_param *mask);
81void dr_ste_v1_build_flex_parser_1_init(struct mlx5dr_ste_build *sb,
82 struct mlx5dr_match_param *mask);
83void dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init(struct mlx5dr_ste_build *sb,
84 struct mlx5dr_match_param *mask);
85void dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init(struct mlx5dr_ste_build *sb,
86 struct mlx5dr_match_param *mask);
87void dr_ste_v1_build_flex_parser_tnl_gtpu_init(struct mlx5dr_ste_build *sb,
88 struct mlx5dr_match_param *mask);
89void dr_ste_v1_build_tnl_gtpu_flex_parser_0_init(struct mlx5dr_ste_build *sb,
90 struct mlx5dr_match_param *mask);
91void dr_ste_v1_build_tnl_gtpu_flex_parser_1_init(struct mlx5dr_ste_build *sb,
92 struct mlx5dr_match_param *mask);
93
94#endif /* _DR_STE_V1_ */
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v2.c+231−0
@@ -0,0 +1,231 @@
1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2/* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
3
4#include "dr_ste_v1.h"
5
6enum {
7 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_0 = 0x00,
8 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1 = 0x01,
9 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_2 = 0x02,
10 DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_0 = 0x08,
11 DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_1 = 0x09,
12 DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0 = 0x0e,
13 DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0 = 0x18,
14 DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_1 = 0x19,
15 DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_0 = 0x40,
16 DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_1 = 0x41,
17 DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_0 = 0x44,
18 DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_1 = 0x45,
19 DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_2 = 0x46,
20 DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_3 = 0x47,
21 DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_0 = 0x4c,
22 DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_1 = 0x4d,
23 DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_2 = 0x4e,
24 DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_3 = 0x4f,
25 DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_0 = 0x5e,
26 DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_1 = 0x5f,
27 DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_0 = 0x6f,
28 DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_1 = 0x70,
29 DR_STE_V2_ACTION_MDFY_FLD_METADATA_2_CQE = 0x7b,
30 DR_STE_V2_ACTION_MDFY_FLD_GNRL_PURPOSE = 0x7c,
31 DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_0 = 0x90,
32 DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_1 = 0x91,
33 DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_0 = 0x92,
34 DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_1 = 0x93,
35 DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_0 = 0x94,
36 DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_1 = 0x95,
37};
38
39static const struct mlx5dr_ste_action_modify_field dr_ste_v2_action_modify_field_arr[] = {
40 [MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16] = {
41 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_0, .start = 0, .end = 31,
42 },
43 [MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0] = {
44 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_1, .start = 16, .end = 31,
45 },
46 [MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE] = {
47 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1, .start = 0, .end = 15,
48 },
49 [MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16] = {
50 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_0, .start = 0, .end = 31,
51 },
52 [MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0] = {
53 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1, .start = 16, .end = 31,
54 },
55 [MLX5_ACTION_IN_FIELD_OUT_IP_DSCP] = {
56 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0, .start = 18, .end = 23,
57 },
58 [MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS] = {
59 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_1, .start = 16, .end = 24,
60 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
61 },
62 [MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT] = {
63 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 16, .end = 31,
64 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
65 },
66 [MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT] = {
67 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 0, .end = 15,
68 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
69 },
70 [MLX5_ACTION_IN_FIELD_OUT_IP_TTL] = {
71 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0, .start = 8, .end = 15,
72 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
73 },
74 [MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT] = {
75 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0, .start = 8, .end = 15,
76 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
77 },
78 [MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT] = {
79 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 16, .end = 31,
80 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_UDP,
81 },
82 [MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT] = {
83 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 0, .end = 15,
84 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_UDP,
85 },
86 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96] = {
87 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_0, .start = 0, .end = 31,
88 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
89 },
90 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64] = {
91 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_1, .start = 0, .end = 31,
92 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
93 },
94 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32] = {
95 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_2, .start = 0, .end = 31,
96 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
97 },
98 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0] = {
99 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_3, .start = 0, .end = 31,
100 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
101 },
102 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96] = {
103 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_0, .start = 0, .end = 31,
104 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
105 },
106 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64] = {
107 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_1, .start = 0, .end = 31,
108 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
109 },
110 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32] = {
111 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_2, .start = 0, .end = 31,
112 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
113 },
114 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0] = {
115 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_3, .start = 0, .end = 31,
116 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
117 },
118 [MLX5_ACTION_IN_FIELD_OUT_SIPV4] = {
119 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_0, .start = 0, .end = 31,
120 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
121 },
122 [MLX5_ACTION_IN_FIELD_OUT_DIPV4] = {
123 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_1, .start = 0, .end = 31,
124 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
125 },
126 [MLX5_ACTION_IN_FIELD_METADATA_REG_A] = {
127 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_GNRL_PURPOSE, .start = 0, .end = 31,
128 },
129 [MLX5_ACTION_IN_FIELD_METADATA_REG_B] = {
130 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_METADATA_2_CQE, .start = 0, .end = 31,
131 },
132 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_0] = {
133 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_0, .start = 0, .end = 31,
134 },
135 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_1] = {
136 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_1, .start = 0, .end = 31,
137 },
138 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_2] = {
139 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_0, .start = 0, .end = 31,
140 },
141 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_3] = {
142 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_1, .start = 0, .end = 31,
143 },
144 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_4] = {
145 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_0, .start = 0, .end = 31,
146 },
147 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_5] = {
148 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_1, .start = 0, .end = 31,
149 },
150 [MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM] = {
151 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_0, .start = 0, .end = 31,
152 },
153 [MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM] = {
154 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_1, .start = 0, .end = 31,
155 },
156 [MLX5_ACTION_IN_FIELD_OUT_FIRST_VID] = {
157 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_2, .start = 0, .end = 15,
158 },
159 [MLX5_ACTION_IN_FIELD_OUT_EMD_31_0] = {
160 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_1, .start = 0, .end = 31,
161 },
162 [MLX5_ACTION_IN_FIELD_OUT_EMD_47_32] = {
163 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_0, .start = 0, .end = 15,
164 },
165};
166
167static struct mlx5dr_ste_ctx ste_ctx_v2 = {
168 /* Builders */
169 .build_eth_l2_src_dst_init = &dr_ste_v1_build_eth_l2_src_dst_init,
170 .build_eth_l3_ipv6_src_init = &dr_ste_v1_build_eth_l3_ipv6_src_init,
171 .build_eth_l3_ipv6_dst_init = &dr_ste_v1_build_eth_l3_ipv6_dst_init,
172 .build_eth_l3_ipv4_5_tuple_init = &dr_ste_v1_build_eth_l3_ipv4_5_tuple_init,
173 .build_eth_l2_src_init = &dr_ste_v1_build_eth_l2_src_init,
174 .build_eth_l2_dst_init = &dr_ste_v1_build_eth_l2_dst_init,
175 .build_eth_l2_tnl_init = &dr_ste_v1_build_eth_l2_tnl_init,
176 .build_eth_l3_ipv4_misc_init = &dr_ste_v1_build_eth_l3_ipv4_misc_init,
177 .build_eth_ipv6_l3_l4_init = &dr_ste_v1_build_eth_ipv6_l3_l4_init,
178 .build_mpls_init = &dr_ste_v1_build_mpls_init,
179 .build_tnl_gre_init = &dr_ste_v1_build_tnl_gre_init,
180 .build_tnl_mpls_init = &dr_ste_v1_build_tnl_mpls_init,
181 .build_tnl_mpls_over_udp_init = &dr_ste_v1_build_tnl_mpls_over_udp_init,
182 .build_tnl_mpls_over_gre_init = &dr_ste_v1_build_tnl_mpls_over_gre_init,
183 .build_icmp_init = &dr_ste_v1_build_icmp_init,
184 .build_general_purpose_init = &dr_ste_v1_build_general_purpose_init,
185 .build_eth_l4_misc_init = &dr_ste_v1_build_eth_l4_misc_init,
186 .build_tnl_vxlan_gpe_init = &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init,
187 .build_tnl_geneve_init = &dr_ste_v1_build_flex_parser_tnl_geneve_init,
188 .build_tnl_geneve_tlv_opt_init = &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init,
189 .build_tnl_geneve_tlv_opt_exist_init =
190 &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init,
191 .build_register_0_init = &dr_ste_v1_build_register_0_init,
192 .build_register_1_init = &dr_ste_v1_build_register_1_init,
193 .build_src_gvmi_qpn_init = &dr_ste_v1_build_src_gvmi_qpn_init,
194 .build_flex_parser_0_init = &dr_ste_v1_build_flex_parser_0_init,
195 .build_flex_parser_1_init = &dr_ste_v1_build_flex_parser_1_init,
196 .build_tnl_gtpu_init = &dr_ste_v1_build_flex_parser_tnl_gtpu_init,
197 .build_tnl_header_0_1_init = &dr_ste_v1_build_tnl_header_0_1_init,
198 .build_tnl_gtpu_flex_parser_0_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_0_init,
199 .build_tnl_gtpu_flex_parser_1_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_1_init,
200
201 /* Getters and Setters */
202 .ste_init = &dr_ste_v1_init,
203 .set_next_lu_type = &dr_ste_v1_set_next_lu_type,
204 .get_next_lu_type = &dr_ste_v1_get_next_lu_type,
205 .set_miss_addr = &dr_ste_v1_set_miss_addr,
206 .get_miss_addr = &dr_ste_v1_get_miss_addr,
207 .set_hit_addr = &dr_ste_v1_set_hit_addr,
208 .set_byte_mask = &dr_ste_v1_set_byte_mask,
209 .get_byte_mask = &dr_ste_v1_get_byte_mask,
210
211 /* Actions */
212 .actions_caps = DR_STE_CTX_ACTION_CAP_TX_POP |
213 DR_STE_CTX_ACTION_CAP_RX_PUSH |
214 DR_STE_CTX_ACTION_CAP_RX_ENCAP,
215 .set_actions_rx = &dr_ste_v1_set_actions_rx,
216 .set_actions_tx = &dr_ste_v1_set_actions_tx,
217 .modify_field_arr_sz = ARRAY_SIZE(dr_ste_v2_action_modify_field_arr),
218 .modify_field_arr = dr_ste_v2_action_modify_field_arr,
219 .set_action_set = &dr_ste_v1_set_action_set,
220 .set_action_add = &dr_ste_v1_set_action_add,
221 .set_action_copy = &dr_ste_v1_set_action_copy,
222 .set_action_decap_l3_list = &dr_ste_v1_set_action_decap_l3_list,
223
224 /* Send */
225 .prepare_for_postsend = &dr_ste_v1_prepare_for_postsend,
226};
227
228struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v2(void)
229{
230 return &ste_ctx_v2;
231}
drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c+1−1
@@ -758,7 +758,7 @@ static u32 mlx5_cmd_dr_get_capabilities(struct mlx5_flow_root_namespace *ns, · 757 unmodified lines
758 enum fs_flow_table_type ft_type)758 enum fs_flow_table_type ft_type)
759{759{
760 if (ft_type != FS_FT_FDB ||760 if (ft_type != FS_FT_FDB ||
761 MLX5_CAP_GEN(ns->dev, steering_format_version) != MLX5_STEERING_FORMAT_CONNECTX_6DX)761 MLX5_CAP_GEN(ns->dev, steering_format_version) == MLX5_STEERING_FORMAT_CONNECTX_5)
762 return 0;762 return 0;
763 763
764 return MLX5_FLOW_STEERING_CAP_VLAN_PUSH_ON_RX | MLX5_FLOW_STEERING_CAP_VLAN_POP_ON_TX;764 return MLX5_FLOW_STEERING_CAP_VLAN_PUSH_ON_RX | MLX5_FLOW_STEERING_CAP_VLAN_POP_ON_TX;
drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h+1−1
@@ -136,7 +136,7 @@ mlx5dr_is_supported(struct mlx5_core_dev *dev) · 135 unmodified lines
136 (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner) ||136 (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner) ||
137 (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner_v2) &&137 (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner_v2) &&
138 (MLX5_CAP_GEN(dev, steering_format_version) <=138 (MLX5_CAP_GEN(dev, steering_format_version) <=
139 MLX5_STEERING_FORMAT_CONNECTX_6DX)));139 MLX5_STEERING_FORMAT_CONNECTX_7)));
140}140}
141 141
142/* buddy functions & structure */142/* buddy functions & structure */
include/linux/mlx5/mlx5_ifc.h+1−0
@@ -1346,6 +1346,7 @@ enum mlx5_fc_bulk_alloc_bitmask { · 1345 unmodified lines
1346enum {1346enum {
1347 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,1347 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1348 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,1348 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1349 MLX5_STEERING_FORMAT_CONNECTX_7 = 2,
1349};1350};
1350 1351
1351struct mlx5_ifc_cmd_hca_cap_bits {1352struct mlx5_ifc_cmd_hca_cap_bits {

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