There is no more hard limit of 80 characters for long lines, so join a few of them for better readability.
Unified · Split
| @@ -111,8 +111,7 @@ static inline int to_reg(int gpio, enum ctrl_register reg_type) · 110 unmodified lines | ||
| 111 | 111 | return reg + gpio % 8; |
| 112 | 112 | } |
| 113 | 113 | |
| 114 | −static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, | |
| 115 | − int gpio) | |
| 114 | +static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio) | |
| 116 | 115 | { |
| 117 | 116 | u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0; |
| 118 | 117 | int mask = BIT(gpio % 8); |
| @@ -141,8 +140,7 @@ static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) · 22 unmodified lines | ||
| 141 | 140 | return regmap_write(cg->regmap, reg, CTLO_INPUT_SET); |
| 142 | 141 | } |
| 143 | 142 | |
| 144 | −static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, | |
| 145 | − int value) | |
| 143 | +static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value) | |
| 146 | 144 | { |
| 147 | 145 | struct crystalcove_gpio *cg = gpiochip_get_data(chip); |
| 148 | 146 | int reg = to_reg(gpio, CTRL_OUT); |
| @@ -169,8 +167,7 @@ static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) · 20 unmodified lines | ||
| 169 | 167 | return val & 0x1; |
| 170 | 168 | } |
| 171 | 169 | |
| 172 | −static void crystalcove_gpio_set(struct gpio_chip *chip, | |
| 173 | − unsigned int gpio, int value) | |
| 170 | +static void crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) | |
| 174 | 171 | { |
| 175 | 172 | struct crystalcove_gpio *cg = gpiochip_get_data(chip); |
| 176 | 173 | int reg = to_reg(gpio, CTRL_OUT); |
| @@ -186,8 +183,7 @@ static void crystalcove_gpio_set(struct gpio_chip *chip, · 9 unmodified lines | ||
| 186 | 183 | |
| 187 | 184 | static int crystalcove_irq_type(struct irq_data *data, unsigned int type) |
| 188 | 185 | { |
| 189 | − struct crystalcove_gpio *cg = | |
| 190 | − gpiochip_get_data(irq_data_get_irq_chip_data(data)); | |
| 186 | + struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data)); | |
| 191 | 187 | irq_hw_number_t hwirq = irqd_to_hwirq(data); |
| 192 | 188 | |
| 193 | 189 | if (hwirq >= CRYSTALCOVE_GPIO_NUM) |
| @@ -217,16 +213,14 @@ static int crystalcove_irq_type(struct irq_data *data, unsigned int type) · 23 unmodified lines | ||
| 217 | 213 | |
| 218 | 214 | static void crystalcove_bus_lock(struct irq_data *data) |
| 219 | 215 | { |
| 220 | − struct crystalcove_gpio *cg = | |
| 221 | − gpiochip_get_data(irq_data_get_irq_chip_data(data)); | |
| 216 | + struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data)); | |
| 222 | 217 | |
| 223 | 218 | mutex_lock(&cg->buslock); |
| 224 | 219 | } |
| 225 | 220 | |
| 226 | 221 | static void crystalcove_bus_sync_unlock(struct irq_data *data) |
| 227 | 222 | { |
| 228 | − struct crystalcove_gpio *cg = | |
| 229 | − gpiochip_get_data(irq_data_get_irq_chip_data(data)); | |
| 223 | + struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data)); | |
| 230 | 224 | irq_hw_number_t hwirq = irqd_to_hwirq(data); |
| 231 | 225 | |
| 232 | 226 | if (cg->update & UPDATE_IRQ_TYPE) |
| @@ -304,8 +298,7 @@ static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data) · 71 unmodified lines | ||
| 304 | 298 | return IRQ_HANDLED; |
| 305 | 299 | } |
| 306 | 300 | |
| 307 | −static void crystalcove_gpio_dbg_show(struct seq_file *s, | |
| 308 | − struct gpio_chip *chip) | |
| 301 | +static void crystalcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
| 309 | 302 | { |
| 310 | 303 | struct crystalcove_gpio *cg = gpiochip_get_data(chip); |
| 311 | 304 | int gpio, offset; |