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drm/amd/pp: Remove unneeded void * casts for Vega10

Removes unneeded void * casts for the following pointers: hwmgr->backend hwmgr->smu_backend

Rex Zhu committed 8 years ago

Commit 690dc621 parent 25380904 files · +87 −138Browse files

Unified · Split

4 files
  1. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +70 −114
  2. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +6 −9
  3. drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +7 −7
  4. drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +4 −8
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c+70−114
@@ -107,8 +107,7 @@ const struct vega10_power_state *cast_const_phw_vega10_power_state( · 106 unmodified lines
107 107
108static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)108static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
109{109{
110 struct vega10_hwmgr *data =110 struct vega10_hwmgr *data = hwmgr->backend;
111 (struct vega10_hwmgr *)(hwmgr->backend);
112 111
113 data->registry_data.sclk_dpm_key_disabled =112 data->registry_data.sclk_dpm_key_disabled =
114 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;113 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
@@ -185,8 +184,7 @@ static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) · 70 unmodified lines
185 184
186static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)185static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
187{186{
188 struct vega10_hwmgr *data =187 struct vega10_hwmgr *data = hwmgr->backend;
189 (struct vega10_hwmgr *)(hwmgr->backend);
190 struct phm_ppt_v2_information *table_info =188 struct phm_ppt_v2_information *table_info =
191 (struct phm_ppt_v2_information *)hwmgr->pptable;189 (struct phm_ppt_v2_information *)hwmgr->pptable;
192 struct amdgpu_device *adev = hwmgr->adev;190 struct amdgpu_device *adev = hwmgr->adev;
@@ -296,7 +294,7 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) · 103 unmodified lines
296 294
297static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)295static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
298{296{
299 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);297 struct vega10_hwmgr *data = hwmgr->backend;
300 int i;298 int i;
301 uint32_t sub_vendor_id, hw_revision;299 uint32_t sub_vendor_id, hw_revision;
302 struct amdgpu_device *adev = hwmgr->adev;300 struct amdgpu_device *adev = hwmgr->adev;
@@ -484,7 +482,7 @@ static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, · 181 unmodified lines
484*/482*/
485static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)483static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
486{484{
487 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);485 struct vega10_hwmgr *data = hwmgr->backend;
488 uint16_t vv_id;486 uint16_t vv_id;
489 uint32_t vddc = 0;487 uint32_t vddc = 0;
490 uint16_t i, j;488 uint16_t i, j;
@@ -675,7 +673,7 @@ static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr) · 184 unmodified lines
675 struct phm_ppt_v2_information *table_info =673 struct phm_ppt_v2_information *table_info =
676 (struct phm_ppt_v2_information *)(hwmgr->pptable);674 (struct phm_ppt_v2_information *)(hwmgr->pptable);
677#ifdef PPLIB_VEGA10_EVV_SUPPORT675#ifdef PPLIB_VEGA10_EVV_SUPPORT
678 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);676 struct vega10_hwmgr *data = hwmgr->backend;
679 677
680 tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,678 tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
681 table_info->vddc_lookup_table, &(data->vddc_leakage));679 table_info->vddc_lookup_table, &(data->vddc_leakage));
@@ -878,8 +876,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) · 196 unmodified lines
878 876
879static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)877static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
880{878{
881 struct vega10_hwmgr *data =879 struct vega10_hwmgr *data = hwmgr->backend;
882 (struct vega10_hwmgr *)(hwmgr->backend);
883 880
884 data->low_sclk_interrupt_threshold = 0;881 data->low_sclk_interrupt_threshold = 0;
885 882
@@ -888,8 +885,7 @@ static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr) · 2 unmodified lines
888 885
889static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)886static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
890{887{
891 struct vega10_hwmgr *data =888 struct vega10_hwmgr *data = hwmgr->backend;
892 (struct vega10_hwmgr *)(hwmgr->backend);
893 PPTable_t *pp_table = &(data->smc_state_table.pp_table);889 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
894 890
895 struct pp_atomfwctrl_voltage_table table;891 struct pp_atomfwctrl_voltage_table table;
@@ -1092,7 +1088,7 @@ static void vega10_trim_voltage_table_to_fit_state_table( · 196 unmodified lines
1092*/1088*/
1093static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)1089static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1094{1090{
1095 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);1091 struct vega10_hwmgr *data = hwmgr->backend;
1096 struct phm_ppt_v2_information *table_info =1092 struct phm_ppt_v2_information *table_info =
1097 (struct phm_ppt_v2_information *)hwmgr->pptable;1093 (struct phm_ppt_v2_information *)hwmgr->pptable;
1098 int result;1094 int result;
@@ -1180,8 +1176,7 @@ static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, · 81 unmodified lines
1180}1176}
1181static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)1177static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1182{1178{
1183 struct vega10_hwmgr *data =1179 struct vega10_hwmgr *data = hwmgr->backend;
1184 (struct vega10_hwmgr *)(hwmgr->backend);
1185 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);1180 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1186 struct phm_ppt_v2_information *table_info =1181 struct phm_ppt_v2_information *table_info =
1187 (struct phm_ppt_v2_information *)(hwmgr->pptable);1182 (struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -1230,8 +1225,7 @@ static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) · 42 unmodified lines
1230 */1225 */
1231static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)1226static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1232{1227{
1233 struct vega10_hwmgr *data =1228 struct vega10_hwmgr *data = hwmgr->backend;
1234 (struct vega10_hwmgr *)(hwmgr->backend);
1235 struct phm_ppt_v2_information *table_info =1229 struct phm_ppt_v2_information *table_info =
1236 (struct phm_ppt_v2_information *)(hwmgr->pptable);1230 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1237 struct vega10_single_dpm_table *dpm_table;1231 struct vega10_single_dpm_table *dpm_table;
@@ -1431,8 +1425,7 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) · 193 unmodified lines
1431 */1425 */
1432static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)1426static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1433{1427{
1434 struct vega10_hwmgr *data =1428 struct vega10_hwmgr *data = hwmgr->backend;
1435 (struct vega10_hwmgr *)(hwmgr->backend);
1436 struct phm_ppt_v2_information *table_info =1429 struct phm_ppt_v2_information *table_info =
1437 (struct phm_ppt_v2_information *)(hwmgr->pptable);1430 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1438 1431
@@ -1473,8 +1466,7 @@ static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr, · 34 unmodified lines
1473static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)1466static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1474{1467{
1475 int result = -1;1468 int result = -1;
1476 struct vega10_hwmgr *data =1469 struct vega10_hwmgr *data = hwmgr->backend;
1477 (struct vega10_hwmgr *)(hwmgr->backend);
1478 PPTable_t *pp_table = &(data->smc_state_table.pp_table);1470 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1479 struct vega10_pcie_table *pcie_table =1471 struct vega10_pcie_table *pcie_table =
1480 &(data->dpm_table.pcie_table);1472 &(data->dpm_table.pcie_table);
@@ -1525,8 +1517,7 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, · 44 unmodified lines
1525 (struct phm_ppt_v2_information *)(hwmgr->pptable);1517 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1526 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk =1518 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk =
1527 table_info->vdd_dep_on_sclk;1519 table_info->vdd_dep_on_sclk;
1528 struct vega10_hwmgr *data =1520 struct vega10_hwmgr *data = hwmgr->backend;
1529 (struct vega10_hwmgr *)(hwmgr->backend);
1530 struct pp_atomfwctrl_clock_dividers_soc15 dividers;1521 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1531 uint32_t gfx_max_clock =1522 uint32_t gfx_max_clock =
1532 hwmgr->platform_descriptor.overdriveLimit.engineClock;1523 hwmgr->platform_descriptor.overdriveLimit.engineClock;
@@ -1638,8 +1629,7 @@ uint16_t vega10_locate_vddc_given_clock(struct pp_hwmgr *hwmgr, · 105 unmodified lines
1638*/1629*/
1639static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)1630static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1640{1631{
1641 struct vega10_hwmgr *data =1632 struct vega10_hwmgr *data = hwmgr->backend;
1642 (struct vega10_hwmgr *)(hwmgr->backend);
1643 struct phm_ppt_v2_information *table_info =1633 struct phm_ppt_v2_information *table_info =
1644 (struct phm_ppt_v2_information *)(hwmgr->pptable);1634 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1645 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =1635 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
@@ -1713,8 +1703,7 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, · 67 unmodified lines
1713 uint32_t mem_clock, uint8_t *current_mem_vid,1703 uint32_t mem_clock, uint8_t *current_mem_vid,
1714 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)1704 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1715{1705{
1716 struct vega10_hwmgr *data =1706 struct vega10_hwmgr *data = hwmgr->backend;
1717 (struct vega10_hwmgr *)(hwmgr->backend);
1718 struct phm_ppt_v2_information *table_info =1707 struct phm_ppt_v2_information *table_info =
1719 (struct phm_ppt_v2_information *)(hwmgr->pptable);1708 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1720 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk =1709 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk =
@@ -1772,8 +1761,7 @@ static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, · 51 unmodified lines
1772 */1761 */
1773static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)1762static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1774{1763{
1775 struct vega10_hwmgr *data =1764 struct vega10_hwmgr *data = hwmgr->backend;
1776 (struct vega10_hwmgr *)(hwmgr->backend);
1777 PPTable_t *pp_table = &(data->smc_state_table.pp_table);1765 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1778 struct vega10_single_dpm_table *dpm_table =1766 struct vega10_single_dpm_table *dpm_table =
1779 &(data->dpm_table.mem_table);1767 &(data->dpm_table.mem_table);
@@ -1816,8 +1804,7 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) · 36 unmodified lines
1816static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,1804static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1817 DSPCLK_e disp_clock)1805 DSPCLK_e disp_clock)
1818{1806{
1819 struct vega10_hwmgr *data =1807 struct vega10_hwmgr *data = hwmgr->backend;
1820 (struct vega10_hwmgr *)(hwmgr->backend);
1821 PPTable_t *pp_table = &(data->smc_state_table.pp_table);1808 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1822 struct phm_ppt_v2_information *table_info =1809 struct phm_ppt_v2_information *table_info =
1823 (struct phm_ppt_v2_information *)1810 (struct phm_ppt_v2_information *)
@@ -1912,8 +1899,7 @@ static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr, · 88 unmodified lines
1912 1899
1913static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)1900static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
1914{1901{
1915 struct vega10_hwmgr *data =1902 struct vega10_hwmgr *data = hwmgr->backend;
1916 (struct vega10_hwmgr *)(hwmgr->backend);
1917 PPTable_t *pp_table = &(data->smc_state_table.pp_table);1903 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1918 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);1904 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
1919 int result = -EINVAL;1905 int result = -EINVAL;
@@ -1976,8 +1962,7 @@ static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr, · 56 unmodified lines
1976 1962
1977static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)1963static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
1978{1964{
1979 struct vega10_hwmgr *data =1965 struct vega10_hwmgr *data = hwmgr->backend;
1980 (struct vega10_hwmgr *)(hwmgr->backend);
1981 PPTable_t *pp_table = &(data->smc_state_table.pp_table);1966 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1982 struct vega10_single_dpm_table *vclk_dpm_table =1967 struct vega10_single_dpm_table *vclk_dpm_table =
1983 &(data->dpm_table.vclk_table);1968 &(data->dpm_table.vclk_table);
@@ -2048,8 +2033,7 @@ static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr) · 64 unmodified lines
2048 2033
2049static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)2034static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2050{2035{
2051 struct vega10_hwmgr *data =2036 struct vega10_hwmgr *data = hwmgr->backend;
2052 (struct vega10_hwmgr *)(hwmgr->backend);
2053 PPTable_t *pp_table = &(data->smc_state_table.pp_table);2037 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2054 struct phm_ppt_v2_information *table_info =2038 struct phm_ppt_v2_information *table_info =
2055 (struct phm_ppt_v2_information *)(hwmgr->pptable);2039 (struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -2068,8 +2052,7 @@ static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr) · 12 unmodified lines
2068 2052
2069static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)2053static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2070{2054{
2071 struct vega10_hwmgr *data =2055 struct vega10_hwmgr *data = hwmgr->backend;
2072 (struct vega10_hwmgr *)(hwmgr->backend);
2073 PPTable_t *pp_table = &(data->smc_state_table.pp_table);2056 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2074 struct phm_ppt_v2_information *table_info =2057 struct phm_ppt_v2_information *table_info =
2075 (struct phm_ppt_v2_information *)(hwmgr->pptable);2058 (struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -2260,8 +2243,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) · 184 unmodified lines
2260 2243
2261static int vega10_acg_enable(struct pp_hwmgr *hwmgr)2244static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2262{2245{
2263 struct vega10_hwmgr *data =2246 struct vega10_hwmgr *data = hwmgr->backend;
2264 (struct vega10_hwmgr *)(hwmgr->backend);
2265 uint32_t agc_btc_response;2247 uint32_t agc_btc_response;
2266 2248
2267 if (data->smu_features[GNLD_ACG].supported) {2249 if (data->smu_features[GNLD_ACG].supported) {
@@ -2293,8 +2275,7 @@ static int vega10_acg_enable(struct pp_hwmgr *hwmgr) · 25 unmodified lines
2293 2275
2294static int vega10_acg_disable(struct pp_hwmgr *hwmgr)2276static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2295{2277{
2296 struct vega10_hwmgr *data =2278 struct vega10_hwmgr *data = hwmgr->backend;
2297 (struct vega10_hwmgr *)(hwmgr->backend);
2298 2279
2299 if (data->smu_features[GNLD_ACG].supported && 2280 if (data->smu_features[GNLD_ACG].supported &&
2300 data->smu_features[GNLD_ACG].enabled)2281 data->smu_features[GNLD_ACG].enabled)
@@ -2307,8 +2288,7 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr) · 6 unmodified lines
2307 2288
2308static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)2289static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2309{2290{
2310 struct vega10_hwmgr *data =2291 struct vega10_hwmgr *data = hwmgr->backend;
2311 (struct vega10_hwmgr *)(hwmgr->backend);
2312 PPTable_t *pp_table = &(data->smc_state_table.pp_table);2292 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2313 struct pp_atomfwctrl_gpio_parameters gpio_params = {0};2293 struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2314 int result;2294 int result;
@@ -2343,8 +2323,7 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) · 28 unmodified lines
2343 2323
2344static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)2324static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2345{2325{
2346 struct vega10_hwmgr *data =2326 struct vega10_hwmgr *data = hwmgr->backend;
2347 (struct vega10_hwmgr *)(hwmgr->backend);
2348 2327
2349 if (data->smu_features[GNLD_AVFS].supported) {2328 if (data->smu_features[GNLD_AVFS].supported) {
2350 if (enable) {2329 if (enable) {
@@ -2375,7 +2354,7 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) · 24 unmodified lines
2375 uint32_t top32, bottom32;2354 uint32_t top32, bottom32;
2376 struct phm_fuses_default fuse;2355 struct phm_fuses_default fuse;
2377 2356
2378 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);2357 struct vega10_hwmgr *data = hwmgr->backend;
2379 AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);2358 AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2380 2359
2381 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);2360 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
@@ -2416,8 +2395,7 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) · 34 unmodified lines
2416static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)2395static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2417{2396{
2418 int result;2397 int result;
2419 struct vega10_hwmgr *data =2398 struct vega10_hwmgr *data = hwmgr->backend;
2420 (struct vega10_hwmgr *)(hwmgr->backend);
2421 struct phm_ppt_v2_information *table_info =2399 struct phm_ppt_v2_information *table_info =
2422 (struct phm_ppt_v2_information *)(hwmgr->pptable);2400 (struct phm_ppt_v2_information *)(hwmgr->pptable);
2423 PPTable_t *pp_table = &(data->smc_state_table.pp_table);2401 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
@@ -2555,7 +2533,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) · 131 unmodified lines
2555 2533
2556static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)2534static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2557{2535{
2558 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);2536 struct vega10_hwmgr *data = hwmgr->backend;
2559 2537
2560 if (data->smu_features[GNLD_THERMAL].supported) {2538 if (data->smu_features[GNLD_THERMAL].supported) {
2561 if (data->smu_features[GNLD_THERMAL].enabled)2539 if (data->smu_features[GNLD_THERMAL].enabled)
@@ -2575,7 +2553,7 @@ static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) · 13 unmodified lines
2575 2553
2576static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)2554static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2577{2555{
2578 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);2556 struct vega10_hwmgr *data = hwmgr->backend;
2579 2557
2580 if (data->smu_features[GNLD_THERMAL].supported) {2558 if (data->smu_features[GNLD_THERMAL].supported) {
2581 if (!data->smu_features[GNLD_THERMAL].enabled)2559 if (!data->smu_features[GNLD_THERMAL].enabled)
@@ -2595,8 +2573,7 @@ static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) · 13 unmodified lines
2595 2573
2596static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)2574static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2597{2575{
2598 struct vega10_hwmgr *data =2576 struct vega10_hwmgr *data = hwmgr->backend;
2599 (struct vega10_hwmgr *)(hwmgr->backend);
2600 2577
2601 if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {2578 if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2602 if (data->smu_features[GNLD_VR0HOT].supported) {2579 if (data->smu_features[GNLD_VR0HOT].supported) {
@@ -2624,8 +2601,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) · 21 unmodified lines
2624 2601
2625static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)2602static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2626{2603{
2627 struct vega10_hwmgr *data =2604 struct vega10_hwmgr *data = hwmgr->backend;
2628 (struct vega10_hwmgr *)(hwmgr->backend);
2629 2605
2630 if (data->registry_data.ulv_support) {2606 if (data->registry_data.ulv_support) {
2631 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,2607 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2640,8 +2616,7 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) · 8 unmodified lines
2640 2616
2641static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)2617static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2642{2618{
2643 struct vega10_hwmgr *data =2619 struct vega10_hwmgr *data = hwmgr->backend;
2644 (struct vega10_hwmgr *)(hwmgr->backend);
2645 2620
2646 if (data->registry_data.ulv_support) {2621 if (data->registry_data.ulv_support) {
2647 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,2622 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2656,8 +2631,7 @@ static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) · 8 unmodified lines
2656 2631
2657static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)2632static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2658{2633{
2659 struct vega10_hwmgr *data =2634 struct vega10_hwmgr *data = hwmgr->backend;
2660 (struct vega10_hwmgr *)(hwmgr->backend);
2661 2635
2662 if (data->smu_features[GNLD_DS_GFXCLK].supported) {2636 if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2663 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,2637 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2696,8 +2670,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) · 32 unmodified lines
2696 2670
2697static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)2671static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2698{2672{
2699 struct vega10_hwmgr *data =2673 struct vega10_hwmgr *data = hwmgr->backend;
2700 (struct vega10_hwmgr *)(hwmgr->backend);
2701 2674
2702 if (data->smu_features[GNLD_DS_GFXCLK].supported) {2675 if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2703 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,2676 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -2736,8 +2709,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) · 32 unmodified lines
2736 2709
2737static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)2710static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2738{2711{
2739 struct vega10_hwmgr *data =2712 struct vega10_hwmgr *data = hwmgr->backend;
2740 (struct vega10_hwmgr *)(hwmgr->backend);
2741 uint32_t i, feature_mask = 0;2713 uint32_t i, feature_mask = 0;
2742 2714
2743 2715
@@ -2774,8 +2746,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) · 30 unmodified lines
2774 */2746 */
2775static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)2747static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2776{2748{
2777 struct vega10_hwmgr *data =2749 struct vega10_hwmgr *data = hwmgr->backend;
2778 (struct vega10_hwmgr *)(hwmgr->backend);
2779 uint32_t i, feature_mask = 0;2750 uint32_t i, feature_mask = 0;
2780 2751
2781 for (i = 0; i < GNLD_DPM_MAX; i++) {2752 for (i = 0; i < GNLD_DPM_MAX; i++) {
@@ -2827,8 +2798,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) · 45 unmodified lines
2827 2798
2828static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)2799static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
2829{2800{
2830 struct vega10_hwmgr *data =2801 struct vega10_hwmgr *data = hwmgr->backend;
2831 (struct vega10_hwmgr *)(hwmgr->backend);
2832 2802
2833 if (data->smu_features[GNLD_PCC_LIMIT].supported) {2803 if (data->smu_features[GNLD_PCC_LIMIT].supported) {
2834 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)2804 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
@@ -2845,8 +2815,7 @@ static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool · 10 unmodified lines
2845 2815
2846static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)2816static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2847{2817{
2848 struct vega10_hwmgr *data =2818 struct vega10_hwmgr *data = hwmgr->backend;
2849 (struct vega10_hwmgr *)(hwmgr->backend);
2850 int tmp_result, result = 0;2819 int tmp_result, result = 0;
2851 2820
2852 vega10_enable_disable_PCC_limit_feature(hwmgr, true);2821 vega10_enable_disable_PCC_limit_feature(hwmgr, true);
@@ -3063,7 +3032,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, · 210 unmodified lines
3063 struct cgs_display_info info = {0};3032 struct cgs_display_info info = {0};
3064 const struct phm_clock_and_voltage_limits *max_limits;3033 const struct phm_clock_and_voltage_limits *max_limits;
3065 uint32_t i;3034 uint32_t i;
3066 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);3035 struct vega10_hwmgr *data = hwmgr->backend;
3067 struct phm_ppt_v2_information *table_info =3036 struct phm_ppt_v2_information *table_info =
3068 (struct phm_ppt_v2_information *)(hwmgr->pptable);3037 (struct phm_ppt_v2_information *)(hwmgr->pptable);
3069 int32_t count;3038 int32_t count;
@@ -3207,8 +3176,7 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co · 137 unmodified lines
3207 (const struct phm_set_power_state_input *)input;3176 (const struct phm_set_power_state_input *)input;
3208 const struct vega10_power_state *vega10_ps =3177 const struct vega10_power_state *vega10_ps =
3209 cast_const_phw_vega10_power_state(states->pnew_state);3178 cast_const_phw_vega10_power_state(states->pnew_state);
3210 struct vega10_hwmgr *data =3179 struct vega10_hwmgr *data = hwmgr->backend;
3211 (struct vega10_hwmgr *)(hwmgr->backend);
3212 struct vega10_single_dpm_table *sclk_table =3180 struct vega10_single_dpm_table *sclk_table =
3213 &(data->dpm_table.gfx_table);3181 &(data->dpm_table.gfx_table);
3214 uint32_t sclk = vega10_ps->performance_levels3182 uint32_t sclk = vega10_ps->performance_levels
@@ -3296,8 +3264,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( · 81 unmodified lines
3296 (const struct phm_set_power_state_input *)input;3264 (const struct phm_set_power_state_input *)input;
3297 const struct vega10_power_state *vega10_ps =3265 const struct vega10_power_state *vega10_ps =
3298 cast_const_phw_vega10_power_state(states->pnew_state);3266 cast_const_phw_vega10_power_state(states->pnew_state);
3299 struct vega10_hwmgr *data =3267 struct vega10_hwmgr *data = hwmgr->backend;
3300 (struct vega10_hwmgr *)(hwmgr->backend);
3301 uint32_t sclk = vega10_ps->performance_levels3268 uint32_t sclk = vega10_ps->performance_levels
3302 [vega10_ps->performance_level_count - 1].gfx_clock;3269 [vega10_ps->performance_level_count - 1].gfx_clock;
3303 uint32_t mclk = vega10_ps->performance_levels3270 uint32_t mclk = vega10_ps->performance_levels
@@ -3522,8 +3489,7 @@ static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, · 218 unmodified lines
3522static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,3489static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3523 const struct vega10_power_state *vega10_ps)3490 const struct vega10_power_state *vega10_ps)
3524{3491{
3525 struct vega10_hwmgr *data =3492 struct vega10_hwmgr *data = hwmgr->backend;
3526 (struct vega10_hwmgr *)(hwmgr->backend);
3527 uint32_t high_limit_count;3493 uint32_t high_limit_count;
3528 3494
3529 PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),3495 PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
@@ -3601,8 +3567,7 @@ static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr) · 71 unmodified lines
3601 3567
3602static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)3568static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3603{3569{
3604 struct vega10_hwmgr *data =3570 struct vega10_hwmgr *data = hwmgr->backend;
3605 (struct vega10_hwmgr *)(hwmgr->backend);
3606 uint32_t socclk_idx;3571 uint32_t socclk_idx;
3607 3572
3608 vega10_apply_dal_minimum_voltage_request(hwmgr);3573 vega10_apply_dal_minimum_voltage_request(hwmgr);
@@ -3641,8 +3606,7 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) · 32 unmodified lines
3641 3606
3642static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)3607static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3643{3608{
3644 struct vega10_hwmgr *data =3609 struct vega10_hwmgr *data = hwmgr->backend;
3645 (struct vega10_hwmgr *)(hwmgr->backend);
3646 3610
3647 vega10_apply_dal_minimum_voltage_request(hwmgr);3611 vega10_apply_dal_minimum_voltage_request(hwmgr);
3648 3612
@@ -3674,8 +3638,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) · 25 unmodified lines
3674static int vega10_generate_dpm_level_enable_mask(3638static int vega10_generate_dpm_level_enable_mask(
3675 struct pp_hwmgr *hwmgr, const void *input)3639 struct pp_hwmgr *hwmgr, const void *input)
3676{3640{
3677 struct vega10_hwmgr *data =3641 struct vega10_hwmgr *data = hwmgr->backend;
3678 (struct vega10_hwmgr *)(hwmgr->backend);
3679 const struct phm_set_power_state_input *states =3642 const struct phm_set_power_state_input *states =
3680 (const struct phm_set_power_state_input *)input;3643 (const struct phm_set_power_state_input *)input;
3681 const struct vega10_power_state *vega10_ps =3644 const struct vega10_power_state *vega10_ps =
@@ -3713,8 +3676,7 @@ static int vega10_generate_dpm_level_enable_mask( · 31 unmodified lines
3713 3676
3714int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)3677int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3715{3678{
3716 struct vega10_hwmgr *data =3679 struct vega10_hwmgr *data = hwmgr->backend;
3717 (struct vega10_hwmgr *)(hwmgr->backend);
3718 3680
3719 if (data->smu_features[GNLD_DPM_VCE].supported) {3681 if (data->smu_features[GNLD_DPM_VCE].supported) {
3720 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,3682 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -3730,8 +3692,7 @@ int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) · 9 unmodified lines
3730 3692
3731static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)3693static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3732{3694{
3733 struct vega10_hwmgr *data =3695 struct vega10_hwmgr *data = hwmgr->backend;
3734 (struct vega10_hwmgr *)(hwmgr->backend);
3735 uint32_t low_sclk_interrupt_threshold = 0;3696 uint32_t low_sclk_interrupt_threshold = 0;
3736 3697
3737 if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&3698 if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
@@ -3755,8 +3716,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, · 17 unmodified lines
3755 const void *input)3716 const void *input)
3756{3717{
3757 int tmp_result, result = 0;3718 int tmp_result, result = 0;
3758 struct vega10_hwmgr *data =3719 struct vega10_hwmgr *data = hwmgr->backend;
3759 (struct vega10_hwmgr *)(hwmgr->backend);
3760 PPTable_t *pp_table = &(data->smc_state_table.pp_table);3720 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3761 3721
3762 tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);3722 tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
@@ -3852,7 +3812,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, · 89 unmodified lines
3852 void *value, int *size)3812 void *value, int *size)
3853{3813{
3854 uint32_t sclk_idx, mclk_idx, activity_percent = 0;3814 uint32_t sclk_idx, mclk_idx, activity_percent = 0;
3855 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);3815 struct vega10_hwmgr *data = hwmgr->backend;
3856 struct vega10_dpm_table *dpm_table = &data->dpm_table;3816 struct vega10_dpm_table *dpm_table = &data->dpm_table;
3857 int ret = 0;3817 int ret = 0;
3858 uint32_t reg, val_vid;3818 uint32_t reg, val_vid;
@@ -3990,8 +3950,7 @@ static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, · 131 unmodified lines
3990static int vega10_notify_smc_display_config_after_ps_adjustment(3950static int vega10_notify_smc_display_config_after_ps_adjustment(
3991 struct pp_hwmgr *hwmgr)3951 struct pp_hwmgr *hwmgr)
3992{3952{
3993 struct vega10_hwmgr *data =3953 struct vega10_hwmgr *data = hwmgr->backend;
3994 (struct vega10_hwmgr *)(hwmgr->backend);
3995 struct vega10_single_dpm_table *dpm_table =3954 struct vega10_single_dpm_table *dpm_table =
3996 &data->dpm_table.dcef_table;3955 &data->dpm_table.dcef_table;
3997 struct phm_ppt_v2_information *table_info =3956 struct phm_ppt_v2_information *table_info =
@@ -4049,8 +4008,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( · 51 unmodified lines
4049 4008
4050static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)4009static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
4051{4010{
4052 struct vega10_hwmgr *data =4011 struct vega10_hwmgr *data = hwmgr->backend;
4053 (struct vega10_hwmgr *)(hwmgr->backend);
4054 4012
4055 data->smc_state_table.gfx_boot_level =4013 data->smc_state_table.gfx_boot_level =
4056 data->smc_state_table.gfx_max_level =4014 data->smc_state_table.gfx_max_level =
@@ -4072,8 +4030,7 @@ static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr) · 15 unmodified lines
4072 4030
4073static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)4031static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
4074{4032{
4075 struct vega10_hwmgr *data =4033 struct vega10_hwmgr *data = hwmgr->backend;
4076 (struct vega10_hwmgr *)(hwmgr->backend);
4077 4034
4078 data->smc_state_table.gfx_boot_level =4035 data->smc_state_table.gfx_boot_level =
4079 data->smc_state_table.gfx_max_level =4036 data->smc_state_table.gfx_max_level =
@@ -4096,7 +4053,7 @@ static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr) · 16 unmodified lines
4096 4053
4097static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)4054static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
4098{4055{
4099 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4056 struct vega10_hwmgr *data = hwmgr->backend;
4100 4057
4101 data->smc_state_table.gfx_boot_level =4058 data->smc_state_table.gfx_boot_level =
4102 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));4059 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
@@ -4213,7 +4170,7 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 110 unmodified lines
4213 4170
4214static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)4171static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4215{4172{
4216 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4173 struct vega10_hwmgr *data = hwmgr->backend;
4217 4174
4218 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)4175 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
4219 return AMD_FAN_CTRL_MANUAL;4176 return AMD_FAN_CTRL_MANUAL;
@@ -4273,7 +4230,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr, · 53 unmodified lines
4273 (struct phm_ppt_v2_information *)hwmgr->pptable;4230 (struct phm_ppt_v2_information *)hwmgr->pptable;
4274 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =4231 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4275 table_info->vdd_dep_on_mclk;4232 table_info->vdd_dep_on_mclk;
4276 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4233 struct vega10_hwmgr *data = hwmgr->backend;
4277 uint32_t i;4234 uint32_t i;
4278 4235
4279 clocks->num_levels = 0;4236 clocks->num_levels = 0;
@@ -4397,7 +4354,7 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, · 117 unmodified lines
4397static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,4354static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4398 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)4355 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
4399{4356{
4400 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4357 struct vega10_hwmgr *data = hwmgr->backend;
4401 Watermarks_t *table = &(data->smc_state_table.water_marks_table);4358 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4402 int result = 0;4359 int result = 0;
4403 uint32_t i;4360 uint32_t i;
@@ -4453,7 +4410,7 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, · 49 unmodified lines
4453static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,4410static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
4454 enum pp_clock_type type, uint32_t mask)4411 enum pp_clock_type type, uint32_t mask)
4455{4412{
4456 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4413 struct vega10_hwmgr *data = hwmgr->backend;
4457 4414
4458 switch (type) {4415 switch (type) {
4459 case PP_SCLK:4416 case PP_SCLK:
@@ -4494,7 +4451,7 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, · 34 unmodified lines
4494static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,4451static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4495 enum pp_clock_type type, char *buf)4452 enum pp_clock_type type, char *buf)
4496{4453{
4497 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4454 struct vega10_hwmgr *data = hwmgr->backend;
4498 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);4455 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4499 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);4456 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4500 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);4457 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
@@ -4544,7 +4501,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, · 43 unmodified lines
4544 4501
4545static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)4502static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4546{4503{
4547 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4504 struct vega10_hwmgr *data = hwmgr->backend;
4548 int result = 0;4505 int result = 0;
4549 uint32_t num_turned_on_displays = 1;4506 uint32_t num_turned_on_displays = 1;
4550 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);4507 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
@@ -4569,8 +4526,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) · 18 unmodified lines
4569 4526
4570int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)4527int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4571{4528{
4572 struct vega10_hwmgr *data =4529 struct vega10_hwmgr *data = hwmgr->backend;
4573 (struct vega10_hwmgr *)(hwmgr->backend);
4574 4530
4575 if (data->smu_features[GNLD_DPM_UVD].supported) {4531 if (data->smu_features[GNLD_DPM_UVD].supported) {
4576 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,4532 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
@@ -4585,7 +4541,7 @@ int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) · 8 unmodified lines
4585 4541
4586static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)4542static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4587{4543{
4588 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4544 struct vega10_hwmgr *data = hwmgr->backend;
4589 4545
4590 data->vce_power_gated = bgate;4546 data->vce_power_gated = bgate;
4591 vega10_enable_disable_vce_dpm(hwmgr, !bgate);4547 vega10_enable_disable_vce_dpm(hwmgr, !bgate);
@@ -4593,7 +4549,7 @@ static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) · 1 unmodified line
4593 4549
4594static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)4550static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4595{4551{
4596 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4552 struct vega10_hwmgr *data = hwmgr->backend;
4597 4553
4598 data->uvd_power_gated = bgate;4554 data->uvd_power_gated = bgate;
4599 vega10_enable_disable_uvd_dpm(hwmgr, !bgate);4555 vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
@@ -4646,7 +4602,7 @@ static int vega10_check_states_equal(struct pp_hwmgr *hwmgr, · 46 unmodified lines
4646static bool4602static bool
4647vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)4603vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4648{4604{
4649 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4605 struct vega10_hwmgr *data = hwmgr->backend;
4650 bool is_update_required = false;4606 bool is_update_required = false;
4651 struct cgs_display_info info = {0, 0, NULL};4607 struct cgs_display_info info = {0, 0, NULL};
4652 4608
@@ -4704,7 +4660,7 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) · 51 unmodified lines
4704 4660
4705static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)4661static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
4706{4662{
4707 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4663 struct vega10_hwmgr *data = hwmgr->backend;
4708 int result;4664 int result;
4709 4665
4710 result = vega10_disable_dpm_tasks(hwmgr);4666 result = vega10_disable_dpm_tasks(hwmgr);
@@ -4718,7 +4674,7 @@ static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) · 7 unmodified lines
4718 4674
4719static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)4675static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
4720{4676{
4721 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4677 struct vega10_hwmgr *data = hwmgr->backend;
4722 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);4678 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4723 struct vega10_single_dpm_table *golden_sclk_table =4679 struct vega10_single_dpm_table *golden_sclk_table =
4724 &(data->golden_dpm_table.gfx_table);4680 &(data->golden_dpm_table.gfx_table);
@@ -4736,7 +4692,7 @@ static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) · 11 unmodified lines
4736 4692
4737static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)4693static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4738{4694{
4739 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4695 struct vega10_hwmgr *data = hwmgr->backend;
4740 struct vega10_single_dpm_table *golden_sclk_table =4696 struct vega10_single_dpm_table *golden_sclk_table =
4741 &(data->golden_dpm_table.gfx_table);4697 &(data->golden_dpm_table.gfx_table);
4742 struct pp_power_state *ps;4698 struct pp_power_state *ps;
@@ -4769,7 +4725,7 @@ static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) · 26 unmodified lines
4769 4725
4770static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)4726static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
4771{4727{
4772 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4728 struct vega10_hwmgr *data = hwmgr->backend;
4773 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);4729 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4774 struct vega10_single_dpm_table *golden_mclk_table =4730 struct vega10_single_dpm_table *golden_mclk_table =
4775 &(data->golden_dpm_table.mem_table);4731 &(data->golden_dpm_table.mem_table);
@@ -4788,7 +4744,7 @@ static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) · 12 unmodified lines
4788 4744
4789static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)4745static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4790{4746{
4791 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4747 struct vega10_hwmgr *data = hwmgr->backend;
4792 struct vega10_single_dpm_table *golden_mclk_table =4748 struct vega10_single_dpm_table *golden_mclk_table =
4793 &(data->golden_dpm_table.mem_table);4749 &(data->golden_dpm_table.mem_table);
4794 struct pp_power_state *ps;4750 struct pp_power_state *ps;
@@ -4894,7 +4850,7 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr, · 99 unmodified lines
4894 4850
4895static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)4851static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4896{4852{
4897 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4853 struct vega10_hwmgr *data = hwmgr->backend;
4898 uint32_t i, size = 0;4854 uint32_t i, size = 0;
4899 static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},4855 static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
4900 {90, 60, 0, 0,},4856 {90, 60, 0, 0,},
@@ -4935,7 +4891,7 @@ static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) · 34 unmodified lines
4935 4891
4936static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)4892static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4937{4893{
4938 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);4894 struct vega10_hwmgr *data = hwmgr->backend;
4939 uint8_t busy_set_point;4895 uint8_t busy_set_point;
4940 uint8_t FPS;4896 uint8_t FPS;
4941 uint8_t use_rlc_busy;4897 uint8_t use_rlc_busy;
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c+6−9
@@ -1193,7 +1193,7 @@ static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) · 1192 unmodified lines
1193int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)1193int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
1194{1194{
1195 int result = 0;1195 int result = 0;
1196 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);1196 struct vega10_hwmgr *data = hwmgr->backend;
1197 1197
1198 if (data->smu_features[GNLD_DIDT].supported) {1198 if (data->smu_features[GNLD_DIDT].supported) {
1199 if (data->smu_features[GNLD_DIDT].enabled)1199 if (data->smu_features[GNLD_DIDT].enabled)
@@ -1240,7 +1240,7 @@ int vega10_enable_didt_config(struct pp_hwmgr *hwmgr) · 40 unmodified lines
1240int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)1240int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
1241{1241{
1242 int result = 0;1242 int result = 0;
1243 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);1243 struct vega10_hwmgr *data = hwmgr->backend;
1244 1244
1245 if (data->smu_features[GNLD_DIDT].supported) {1245 if (data->smu_features[GNLD_DIDT].supported) {
1246 if (!data->smu_features[GNLD_DIDT].enabled)1246 if (!data->smu_features[GNLD_DIDT].enabled)
@@ -1286,7 +1286,7 @@ int vega10_disable_didt_config(struct pp_hwmgr *hwmgr) · 39 unmodified lines
1286 1286
1287void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)1287void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1288{1288{
1289 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);1289 struct vega10_hwmgr *data = hwmgr->backend;
1290 struct phm_ppt_v2_information *table_info =1290 struct phm_ppt_v2_information *table_info =
1291 (struct phm_ppt_v2_information *)(hwmgr->pptable);1291 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1292 struct phm_tdp_table *tdp_table = table_info->tdp_table;1292 struct phm_tdp_table *tdp_table = table_info->tdp_table;
@@ -1325,8 +1325,7 @@ void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) · 32 unmodified lines
1325 1325
1326int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)1326int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
1327{1327{
1328 struct vega10_hwmgr *data =1328 struct vega10_hwmgr *data = hwmgr->backend;
1329 (struct vega10_hwmgr *)(hwmgr->backend);
1330 1329
1331 if (data->registry_data.enable_pkg_pwr_tracking_feature)1330 if (data->registry_data.enable_pkg_pwr_tracking_feature)
1332 smum_send_msg_to_smc_with_parameter(hwmgr,1331 smum_send_msg_to_smc_with_parameter(hwmgr,
@@ -1337,8 +1336,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) · 4 unmodified lines
1337 1336
1338int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)1337int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
1339{1338{
1340 struct vega10_hwmgr *data =1339 struct vega10_hwmgr *data = hwmgr->backend;
1341 (struct vega10_hwmgr *)(hwmgr->backend);
1342 struct phm_ppt_v2_information *table_info =1340 struct phm_ppt_v2_information *table_info =
1343 (struct phm_ppt_v2_information *)(hwmgr->pptable);1341 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1344 struct phm_tdp_table *tdp_table = table_info->tdp_table;1342 struct phm_tdp_table *tdp_table = table_info->tdp_table;
@@ -1371,8 +1369,7 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) · 26 unmodified lines
1371 1369
1372int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)1370int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
1373{1371{
1374 struct vega10_hwmgr *data =1372 struct vega10_hwmgr *data = hwmgr->backend;
1375 (struct vega10_hwmgr *)(hwmgr->backend);
1376 1373
1377 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {1374 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1378 if (data->smu_features[GNLD_PPT].supported)1375 if (data->smu_features[GNLD_PPT].supported)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c+7−7
@@ -89,7 +89,7 @@ int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, · 88 unmodified lines
89 89
90int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)90int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
91{91{
92 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);92 struct vega10_hwmgr *data = hwmgr->backend;
93 uint32_t tach_period;93 uint32_t tach_period;
94 uint32_t crystal_clock_freq;94 uint32_t crystal_clock_freq;
95 int result = 0;95 int result = 0;
@@ -188,7 +188,7 @@ int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) · 92 unmodified lines
188 */188 */
189static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)189static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
190{190{
191 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);191 struct vega10_hwmgr *data = hwmgr->backend;
192 192
193 if (data->smu_features[GNLD_FAN_CONTROL].supported) {193 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
194 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(194 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
@@ -205,7 +205,7 @@ static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr) · 10 unmodified lines
205 205
206static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)206static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
207{207{
208 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);208 struct vega10_hwmgr *data = hwmgr->backend;
209 209
210 if (data->smu_features[GNLD_FAN_CONTROL].supported) {210 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
211 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(211 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
@@ -235,7 +235,7 @@ int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) · 23 unmodified lines
235 235
236int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)236int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
237{237{
238 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);238 struct vega10_hwmgr *data = hwmgr->backend;
239 239
240 if (hwmgr->thermal_controller.fanInfo.bNoFan)240 if (hwmgr->thermal_controller.fanInfo.bNoFan)
241 return -1;241 return -1;
@@ -445,7 +445,7 @@ static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) · 203 unmodified lines
445*/445*/
446static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)446static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
447{447{
448 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);448 struct vega10_hwmgr *data = hwmgr->backend;
449 uint32_t val = 0;449 uint32_t val = 0;
450 uint32_t reg;450 uint32_t reg;
451 451
@@ -477,7 +477,7 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr) · 25 unmodified lines
477*/477*/
478int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)478int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
479{479{
480 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);480 struct vega10_hwmgr *data = hwmgr->backend;
481 uint32_t reg;481 uint32_t reg;
482 482
483 if (data->smu_features[GNLD_FW_CTF].supported) {483 if (data->smu_features[GNLD_FW_CTF].supported) {
@@ -526,7 +526,7 @@ int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) · 42 unmodified lines
526int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)526int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
527{527{
528 int ret;528 int ret;
529 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);529 struct vega10_hwmgr *data = hwmgr->backend;
530 PPTable_t *table = &(data->smc_state_table.pp_table);530 PPTable_t *table = &(data->smc_state_table.pp_table);
531 531
532 if (!data->smu_features[GNLD_FAN_CONTROL].supported)532 if (!data->smu_features[GNLD_FAN_CONTROL].supported)
drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c+4−8
@@ -185,8 +185,7 @@ static int vega10_get_argument(struct pp_hwmgr *hwmgr) · 184 unmodified lines
185static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,185static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
186 uint8_t *table, int16_t table_id)186 uint8_t *table, int16_t table_id)
187{187{
188 struct vega10_smumgr *priv =188 struct vega10_smumgr *priv = hwmgr->smu_backend;
189 (struct vega10_smumgr *)(hwmgr->smu_backend);
190 189
191 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,190 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
192 "Invalid SMU Table ID!", return -EINVAL);191 "Invalid SMU Table ID!", return -EINVAL);
@@ -213,8 +212,7 @@ static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, · 20 unmodified lines
213static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,212static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
214 uint8_t *table, int16_t table_id)213 uint8_t *table, int16_t table_id)
215{214{
216 struct vega10_smumgr *priv =215 struct vega10_smumgr *priv = hwmgr->smu_backend;
217 (struct vega10_smumgr *)(hwmgr->smu_backend);
218 216
219 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,217 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
220 "Invalid SMU Table ID!", return -EINVAL);218 "Invalid SMU Table ID!", return -EINVAL);
@@ -265,8 +263,7 @@ static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr) · 44 unmodified lines
265 263
266static int vega10_set_tools_address(struct pp_hwmgr *hwmgr)264static int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
267{265{
268 struct vega10_smumgr *priv =266 struct vega10_smumgr *priv = hwmgr->smu_backend;
269 (struct vega10_smumgr *)(hwmgr->smu_backend);
270 267
271 if (priv->smu_tables.entry[TOOLSTABLE].mc_addr) {268 if (priv->smu_tables.entry[TOOLSTABLE].mc_addr) {
272 vega10_send_msg_to_smc_with_parameter(hwmgr,269 vega10_send_msg_to_smc_with_parameter(hwmgr,
@@ -435,8 +432,7 @@ free_backend: · 162 unmodified lines
435 432
436static int vega10_smu_fini(struct pp_hwmgr *hwmgr)433static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
437{434{
438 struct vega10_smumgr *priv =435 struct vega10_smumgr *priv = hwmgr->smu_backend;
439 (struct vega10_smumgr *)(hwmgr->smu_backend);
440 436
441 if (priv) {437 if (priv) {
442 amdgpu_bo_free_kernel(&priv->smu_tables.entry[PPTABLE].handle,438 amdgpu_bo_free_kernel(&priv->smu_tables.entry[PPTABLE].handle,

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