Add binding documentation of apmixedsys for MT8516 SoC.
Unified · Split
| @@ -15,6 +15,7 @@ Required Properties: · 14 unmodified lines | ||
| 15 | 15 | - "mediatek,mt8135-apmixedsys" |
| 16 | 16 | - "mediatek,mt8173-apmixedsys" |
| 17 | 17 | - "mediatek,mt8183-apmixedsys", "syscon" |
| 18 | + - "mediatek,mt8516-apmixedsys" | |
| 18 | 19 | - #clock-cells: Must be 1 |
| 19 | 20 | |
| 20 | 21 | The apmixedsys controller uses the common clk binding from |
| @@ -8,6 +8,16 @@ · 7 unmodified lines | ||
| 8 | 8 | #ifndef _DT_BINDINGS_CLK_MT8516_H |
| 9 | 9 | #define _DT_BINDINGS_CLK_MT8516_H |
| 10 | 10 | |
| 11 | +/* APMIXEDSYS */ | |
| 12 | + | |
| 13 | +#define CLK_APMIXED_ARMPLL 0 | |
| 14 | +#define CLK_APMIXED_MAINPLL 1 | |
| 15 | +#define CLK_APMIXED_UNIVPLL 2 | |
| 16 | +#define CLK_APMIXED_MMPLL 3 | |
| 17 | +#define CLK_APMIXED_APLL1 4 | |
| 18 | +#define CLK_APMIXED_APLL2 5 | |
| 19 | +#define CLK_APMIXED_NR_CLK 6 | |
| 20 | + | |
| 11 | 21 | /* INFRACFG */ |
| 12 | 22 | |
| 13 | 23 | #define CLK_IFR_MUX1_SEL 0 |