History

Merge tag 'drm-fixes-2020-03-20' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie: "Hope you are well hiding out above the garage. A few amdgpu changes but nothing too major. I've had a wisdom tooth out this week so haven't been to on top of things, but all seems good. core: - fix lease warning i915: - Track active elements during dequeue - Fix failure to handle all MCR ranges - Revert unnecessary workaround amdgpu: - Pageflip fix - VCN clockgating fixes - GPR debugfs fix for umr - GPU reset fix - eDP fix for MBP - DCN2.x fix dw-hdmi: - fix AVI frame colorimetry komeda: - fix compiler warning bochs: - downgrade a binding failure to a warning" * tag 'drm-fixes-2020-03-20' of git://anongit.freedesktop.org/drm/drm: drm/amd/display: Fix pageflip event race condition for DCN. drm/amdgpu: fix typo for vcn2.5/jpeg2.5 idle check drm/amdgpu: fix typo for vcn2/jpeg2 idle check drm/amdgpu: fix typo for vcn1 idle check drm/lease: fix WARNING in idr_destroy drm/i915: Handle all MCR ranges Revert "drm/i915/tgl: Add extra hdc flush workaround" drm/i915/execlists: Track active elements during dequeue drm/bochs: downgrade pci_request_region failure from error to warning drm/amd/display: Add link_rate quirk for Apple 15" MBP 2017 drm/amdgpu: add fbdev suspend/resume on gpu reset drm/amd/amdgpu: Fix GPR read from debugfs (v2) drm/amd/display: fix typos for dcn20_funcs and dcn21_funcs struct drm/komeda: mark PM functions as __maybe_unused drm/bridge: dw-hdmi: fix AVI frame colorimetry

Linus Torvalds committed 6 years ago

Commit 69d3e5a2 parents 6c90b86 5366b9617 files · +104 −83Browse files

Unified · Split

17 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +3 −3
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +4 −0
  3. drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +1 −1
  4. drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +1 −1
  5. drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +1 −1
  6. drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +1 −1
  7. drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +1 −1
  8. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +15 −3
  9. drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +11 −0
  10. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c +0 −1
  11. drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c +0 −1
  12. drivers/gpu/drm/arm/display/komeda/komeda_drv.c +2 −2
  13. drivers/gpu/drm/bochs/bochs_hw.c +2 −4
  14. drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +26 −20
  15. drivers/gpu/drm/drm_lease.c +2 −1
  16. drivers/gpu/drm/i915/gt/intel_lrc.c +12 −40
  17. drivers/gpu/drm/i915/gt/intel_workarounds.c +22 −3
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c+3−3
@@ -781,11 +781,11 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, · 780 unmodified lines
781 ssize_t result = 0;781 ssize_t result = 0;
782 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;782 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
783 783
784 if (size & 3 || *pos & 3)784 if (size > 4096 || size & 3 || *pos & 3)
785 return -EINVAL;785 return -EINVAL;
786 786
787 /* decode offset */787 /* decode offset */
788 offset = *pos & GENMASK_ULL(11, 0);788 offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
789 se = (*pos & GENMASK_ULL(19, 12)) >> 12;789 se = (*pos & GENMASK_ULL(19, 12)) >> 12;
790 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;790 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
791 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;791 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
@@ -823,7 +823,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, · 31 unmodified lines
823 while (size) {823 while (size) {
824 uint32_t value;824 uint32_t value;
825 825
826 value = data[offset++];826 value = data[result >> 2];
827 r = put_user(value, (uint32_t *)buf);827 r = put_user(value, (uint32_t *)buf);
828 if (r) {828 if (r) {
829 result = r;829 result = r;
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+4−0
@@ -3913,6 +3913,8 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, · 3912 unmodified lines
3913 if (r)3913 if (r)
3914 goto out;3914 goto out;
3915 3915
3916 amdgpu_fbdev_set_suspend(tmp_adev, 0);
3917
3916 /* must succeed. */3918 /* must succeed. */
3917 amdgpu_ras_resume(tmp_adev);3919 amdgpu_ras_resume(tmp_adev);
3918 3920
@@ -4086,6 +4088,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 167 unmodified lines
4086 */4088 */
4087 amdgpu_unregister_gpu_instance(tmp_adev);4089 amdgpu_unregister_gpu_instance(tmp_adev);
4088 4090
4091 amdgpu_fbdev_set_suspend(adev, 1);
4092
4089 /* disable ras on ALL IPs */4093 /* disable ras on ALL IPs */
4090 if (!(in_ras_intr && !use_baco) &&4094 if (!(in_ras_intr && !use_baco) &&
4091 amdgpu_device_ip_need_full_reset(tmp_adev))4095 amdgpu_device_ip_need_full_reset(tmp_adev))
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c+1−1
@@ -693,7 +693,7 @@ static int jpeg_v2_0_set_clockgating_state(void *handle, · 692 unmodified lines
693 bool enable = (state == AMD_CG_STATE_GATE);693 bool enable = (state == AMD_CG_STATE_GATE);
694 694
695 if (enable) {695 if (enable) {
696 if (jpeg_v2_0_is_idle(handle))696 if (!jpeg_v2_0_is_idle(handle))
697 return -EBUSY;697 return -EBUSY;
698 jpeg_v2_0_enable_clock_gating(adev);698 jpeg_v2_0_enable_clock_gating(adev);
699 } else {699 } else {
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c+1−1
@@ -477,7 +477,7 @@ static int jpeg_v2_5_set_clockgating_state(void *handle, · 476 unmodified lines
477 continue;477 continue;
478 478
479 if (enable) {479 if (enable) {
480 if (jpeg_v2_5_is_idle(handle))480 if (!jpeg_v2_5_is_idle(handle))
481 return -EBUSY;481 return -EBUSY;
482 jpeg_v2_5_enable_clock_gating(adev, i);482 jpeg_v2_5_enable_clock_gating(adev, i);
483 } else {483 } else {
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c+1−1
@@ -1352,7 +1352,7 @@ static int vcn_v1_0_set_clockgating_state(void *handle, · 1351 unmodified lines
1352 1352
1353 if (enable) {1353 if (enable) {
1354 /* wait for STATUS to clear */1354 /* wait for STATUS to clear */
1355 if (vcn_v1_0_is_idle(handle))1355 if (!vcn_v1_0_is_idle(handle))
1356 return -EBUSY;1356 return -EBUSY;
1357 vcn_v1_0_enable_clock_gating(adev);1357 vcn_v1_0_enable_clock_gating(adev);
1358 } else {1358 } else {
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c+1−1
@@ -1217,7 +1217,7 @@ static int vcn_v2_0_set_clockgating_state(void *handle, · 1216 unmodified lines
1217 1217
1218 if (enable) {1218 if (enable) {
1219 /* wait for STATUS to clear */1219 /* wait for STATUS to clear */
1220 if (vcn_v2_0_is_idle(handle))1220 if (!vcn_v2_0_is_idle(handle))
1221 return -EBUSY;1221 return -EBUSY;
1222 vcn_v2_0_enable_clock_gating(adev);1222 vcn_v2_0_enable_clock_gating(adev);
1223 } else {1223 } else {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c+1−1
@@ -1672,7 +1672,7 @@ static int vcn_v2_5_set_clockgating_state(void *handle, · 1671 unmodified lines
1672 return 0;1672 return 0;
1673 1673
1674 if (enable) {1674 if (enable) {
1675 if (vcn_v2_5_is_idle(handle))1675 if (!vcn_v2_5_is_idle(handle))
1676 return -EBUSY;1676 return -EBUSY;
1677 vcn_v2_5_enable_clock_gating(adev);1677 vcn_v2_5_enable_clock_gating(adev);
1678 } else {1678 } else {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+15−3
@@ -522,8 +522,9 @@ static void dm_dcn_crtc_high_irq(void *interrupt_params) · 521 unmodified lines
522 522
523 acrtc_state = to_dm_crtc_state(acrtc->base.state);523 acrtc_state = to_dm_crtc_state(acrtc->base.state);
524 524
525 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,525 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
526 amdgpu_dm_vrr_active(acrtc_state));526 amdgpu_dm_vrr_active(acrtc_state),
527 acrtc_state->active_planes);
527 528
528 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);529 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
529 drm_crtc_handle_vblank(&acrtc->base);530 drm_crtc_handle_vblank(&acrtc->base);
@@ -543,7 +544,18 @@ static void dm_dcn_crtc_high_irq(void *interrupt_params) · 13 unmodified lines
543 &acrtc_state->vrr_params.adjust);544 &acrtc_state->vrr_params.adjust);
544 }545 }
545 546
546 if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {547 /*
548 * If there aren't any active_planes then DCH HUBP may be clock-gated.
549 * In that case, pageflip completion interrupts won't fire and pageflip
550 * completion events won't get delivered. Prevent this by sending
551 * pending pageflip events from here if a flip is still pending.
552 *
553 * If any planes are enabled, use dm_pflip_high_irq() instead, to
554 * avoid race conditions between flip programming and completion,
555 * which could cause too early flip completion events.
556 */
557 if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
558 acrtc_state->active_planes == 0) {
547 if (acrtc->event) {559 if (acrtc->event) {
548 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);560 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
549 acrtc->event = NULL;561 acrtc->event = NULL;
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+11−0
@@ -3401,6 +3401,17 @@ static bool retrieve_link_cap(struct dc_link *link) · 3400 unmodified lines
3401 sink_id.ieee_device_id,3401 sink_id.ieee_device_id,
3402 sizeof(sink_id.ieee_device_id));3402 sizeof(sink_id.ieee_device_id));
3403 3403
3404 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3405 {
3406 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3407
3408 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3409 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3410 sizeof(str_mbp_2017))) {
3411 link->reported_link_cap.link_rate = 0x0c;
3412 }
3413 }
3414
3404 core_link_read_dpcd(3415 core_link_read_dpcd(
3405 link,3416 link,
3406 DP_SINK_HW_REVISION_START,3417 DP_SINK_HW_REVISION_START,
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c+0−1
@@ -108,7 +108,6 @@ static const struct hwseq_private_funcs dcn20_private_funcs = { · 107 unmodified lines
108 .enable_power_gating_plane = dcn20_enable_power_gating_plane,108 .enable_power_gating_plane = dcn20_enable_power_gating_plane,
109 .dpp_pg_control = dcn20_dpp_pg_control,109 .dpp_pg_control = dcn20_dpp_pg_control,
110 .hubp_pg_control = dcn20_hubp_pg_control,110 .hubp_pg_control = dcn20_hubp_pg_control,
111 .dsc_pg_control = NULL,
112 .update_odm = dcn20_update_odm,111 .update_odm = dcn20_update_odm,
113 .dsc_pg_control = dcn20_dsc_pg_control,112 .dsc_pg_control = dcn20_dsc_pg_control,
114 .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,113 .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c+0−1
@@ -116,7 +116,6 @@ static const struct hwseq_private_funcs dcn21_private_funcs = { · 115 unmodified lines
116 .enable_power_gating_plane = dcn20_enable_power_gating_plane,116 .enable_power_gating_plane = dcn20_enable_power_gating_plane,
117 .dpp_pg_control = dcn20_dpp_pg_control,117 .dpp_pg_control = dcn20_dpp_pg_control,
118 .hubp_pg_control = dcn20_hubp_pg_control,118 .hubp_pg_control = dcn20_hubp_pg_control,
119 .dsc_pg_control = NULL,
120 .update_odm = dcn20_update_odm,119 .update_odm = dcn20_update_odm,
121 .dsc_pg_control = dcn20_dsc_pg_control,120 .dsc_pg_control = dcn20_dsc_pg_control,
122 .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,121 .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
drivers/gpu/drm/arm/display/komeda/komeda_drv.c+2−2
@@ -146,14 +146,14 @@ static const struct of_device_id komeda_of_match[] = { · 145 unmodified lines
146 146
147MODULE_DEVICE_TABLE(of, komeda_of_match);147MODULE_DEVICE_TABLE(of, komeda_of_match);
148 148
149static int komeda_rt_pm_suspend(struct device *dev)149static int __maybe_unused komeda_rt_pm_suspend(struct device *dev)
150{150{
151 struct komeda_drv *mdrv = dev_get_drvdata(dev);151 struct komeda_drv *mdrv = dev_get_drvdata(dev);
152 152
153 return komeda_dev_suspend(mdrv->mdev);153 return komeda_dev_suspend(mdrv->mdev);
154}154}
155 155
156static int komeda_rt_pm_resume(struct device *dev)156static int __maybe_unused komeda_rt_pm_resume(struct device *dev)
157{157{
158 struct komeda_drv *mdrv = dev_get_drvdata(dev);158 struct komeda_drv *mdrv = dev_get_drvdata(dev);
159 159
drivers/gpu/drm/bochs/bochs_hw.c+2−4
@@ -156,10 +156,8 @@ int bochs_hw_init(struct drm_device *dev) · 155 unmodified lines
156 size = min(size, mem);156 size = min(size, mem);
157 }157 }
158 158
159 if (pci_request_region(pdev, 0, "bochs-drm") != 0) {159 if (pci_request_region(pdev, 0, "bochs-drm") != 0)
160 DRM_ERROR("Cannot request framebuffer\n");160 DRM_WARN("Cannot request framebuffer, boot fb still active?\n");
161 return -EBUSY;
162 }
163 161
164 bochs->fb_map = ioremap(addr, size);162 bochs->fb_map = ioremap(addr, size);
165 if (bochs->fb_map == NULL) {163 if (bochs->fb_map == NULL) {
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c+26−20
@@ -1624,28 +1624,34 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) · 1623 unmodified lines
1624 frame.colorspace = HDMI_COLORSPACE_RGB;1624 frame.colorspace = HDMI_COLORSPACE_RGB;
1625 1625
1626 /* Set up colorimetry */1626 /* Set up colorimetry */
1627 switch (hdmi->hdmi_data.enc_out_encoding) {1627 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1628 case V4L2_YCBCR_ENC_601:1628 switch (hdmi->hdmi_data.enc_out_encoding) {
1629 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)1629 case V4L2_YCBCR_ENC_601:
1630 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;1630 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1631 else1631 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1632 else
1633 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1634 frame.extended_colorimetry =
1635 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1636 break;
1637 case V4L2_YCBCR_ENC_709:
1638 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1639 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1640 else
1641 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1642 frame.extended_colorimetry =
1643 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1644 break;
1645 default: /* Carries no data */
1632 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;1646 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1647 frame.extended_colorimetry =
1648 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1649 break;
1650 }
1651 } else {
1652 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1633 frame.extended_colorimetry =1653 frame.extended_colorimetry =
1634 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;1654 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1635 break;
1636 case V4L2_YCBCR_ENC_709:
1637 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1638 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1639 else
1640 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1641 frame.extended_colorimetry =
1642 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1643 break;
1644 default: /* Carries no data */
1645 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1646 frame.extended_colorimetry =
1647 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1648 break;
1649 }1655 }
1650 1656
1651 frame.scan_mode = HDMI_SCAN_MODE_NONE;1657 frame.scan_mode = HDMI_SCAN_MODE_NONE;
drivers/gpu/drm/drm_lease.c+2−1
@@ -542,10 +542,12 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev, · 541 unmodified lines
542 }542 }
543 543
544 DRM_DEBUG_LEASE("Creating lease\n");544 DRM_DEBUG_LEASE("Creating lease\n");
545 /* lessee will take the ownership of leases */
545 lessee = drm_lease_create(lessor, &leases);546 lessee = drm_lease_create(lessor, &leases);
546 547
547 if (IS_ERR(lessee)) {548 if (IS_ERR(lessee)) {
548 ret = PTR_ERR(lessee);549 ret = PTR_ERR(lessee);
550 idr_destroy(&leases);
549 goto out_leases;551 goto out_leases;
550 }552 }
551 553
@@ -580,7 +582,6 @@ out_lessee: · 28 unmodified lines
580 582
581out_leases:583out_leases:
582 put_unused_fd(fd);584 put_unused_fd(fd);
583 idr_destroy(&leases);
584 585
585 DRM_DEBUG_LEASE("drm_mode_create_lease_ioctl failed: %d\n", ret);586 DRM_DEBUG_LEASE("drm_mode_create_lease_ioctl failed: %d\n", ret);
586 return ret;587 return ret;
drivers/gpu/drm/i915/gt/intel_lrc.c+12−40
@@ -1600,17 +1600,6 @@ static void virtual_xfer_breadcrumbs(struct virtual_engine *ve, · 1599 unmodified lines
1600 spin_unlock(&old->breadcrumbs.irq_lock);1600 spin_unlock(&old->breadcrumbs.irq_lock);
1601}1601}
1602 1602
1603static struct i915_request *
1604last_active(const struct intel_engine_execlists *execlists)
1605{
1606 struct i915_request * const *last = READ_ONCE(execlists->active);
1607
1608 while (*last && i915_request_completed(*last))
1609 last++;
1610
1611 return *last;
1612}
1613
1614#define for_each_waiter(p__, rq__) \1603#define for_each_waiter(p__, rq__) \
1615 list_for_each_entry_lockless(p__, \1604 list_for_each_entry_lockless(p__, \
1616 &(rq__)->sched.waiters_list, \1605 &(rq__)->sched.waiters_list, \
@@ -1740,11 +1729,9 @@ static void record_preemption(struct intel_engine_execlists *execlists) · 123 unmodified lines
1740 (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);1729 (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
1741}1730}
1742 1731
1743static unsigned long active_preempt_timeout(struct intel_engine_cs *engine)1732static unsigned long active_preempt_timeout(struct intel_engine_cs *engine,
1733 const struct i915_request *rq)
1744{1734{
1745 struct i915_request *rq;
1746
1747 rq = last_active(&engine->execlists);
1748 if (!rq)1735 if (!rq)
1749 return 0;1736 return 0;
1750 1737
@@ -1755,13 +1742,14 @@ static unsigned long active_preempt_timeout(struct intel_engine_cs *engine) · 4 unmodified lines
1755 return READ_ONCE(engine->props.preempt_timeout_ms);1742 return READ_ONCE(engine->props.preempt_timeout_ms);
1756}1743}
1757 1744
1758static void set_preempt_timeout(struct intel_engine_cs *engine)1745static void set_preempt_timeout(struct intel_engine_cs *engine,
1746 const struct i915_request *rq)
1759{1747{
1760 if (!intel_engine_has_preempt_reset(engine))1748 if (!intel_engine_has_preempt_reset(engine))
1761 return;1749 return;
1762 1750
1763 set_timer_ms(&engine->execlists.preempt,1751 set_timer_ms(&engine->execlists.preempt,
1764 active_preempt_timeout(engine));1752 active_preempt_timeout(engine, rq));
1765}1753}
1766 1754
1767static inline void clear_ports(struct i915_request **ports, int count)1755static inline void clear_ports(struct i915_request **ports, int count)
@@ -1774,6 +1762,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 6 unmodified lines
1774 struct intel_engine_execlists * const execlists = &engine->execlists;1762 struct intel_engine_execlists * const execlists = &engine->execlists;
1775 struct i915_request **port = execlists->pending;1763 struct i915_request **port = execlists->pending;
1776 struct i915_request ** const last_port = port + execlists->port_mask;1764 struct i915_request ** const last_port = port + execlists->port_mask;
1765 struct i915_request * const *active;
1777 struct i915_request *last;1766 struct i915_request *last;
1778 struct rb_node *rb;1767 struct rb_node *rb;
1779 bool submit = false;1768 bool submit = false;
@@ -1828,7 +1817,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 48 unmodified lines
1828 * i.e. we will retrigger preemption following the ack in case1817 * i.e. we will retrigger preemption following the ack in case
1829 * of trouble.1818 * of trouble.
1830 */1819 */
1831 last = last_active(execlists);1820 active = READ_ONCE(execlists->active);
1821 while ((last = *active) && i915_request_completed(last))
1822 active++;
1823
1832 if (last) {1824 if (last) {
1833 if (need_preempt(engine, last, rb)) {1825 if (need_preempt(engine, last, rb)) {
1834 ENGINE_TRACE(engine,1826 ENGINE_TRACE(engine,
@@ -2110,7 +2102,7 @@ done: · 275 unmodified lines
2110 * Skip if we ended up with exactly the same set of requests,2102 * Skip if we ended up with exactly the same set of requests,
2111 * e.g. trying to timeslice a pair of ordered contexts2103 * e.g. trying to timeslice a pair of ordered contexts
2112 */2104 */
2113 if (!memcmp(execlists->active, execlists->pending,2105 if (!memcmp(active, execlists->pending,
2114 (port - execlists->pending + 1) * sizeof(*port))) {2106 (port - execlists->pending + 1) * sizeof(*port))) {
2115 do2107 do
2116 execlists_schedule_out(fetch_and_zero(port));2108 execlists_schedule_out(fetch_and_zero(port));
@@ -2121,7 +2113,7 @@ done: · 4 unmodified lines
2121 clear_ports(port + 1, last_port - port);2113 clear_ports(port + 1, last_port - port);
2122 2114
2123 execlists_submit_ports(engine);2115 execlists_submit_ports(engine);
2124 set_preempt_timeout(engine);2116 set_preempt_timeout(engine, *active);
2125 } else {2117 } else {
2126skip_submit:2118skip_submit:
2127 ring_set_paused(engine, 0);2119 ring_set_paused(engine, 0);
@@ -4008,26 +4000,6 @@ static int gen12_emit_flush_render(struct i915_request *request, · 1880 unmodified lines
4008 4000
4009 *cs++ = preparser_disable(false);4001 *cs++ = preparser_disable(false);
4010 intel_ring_advance(request, cs);4002 intel_ring_advance(request, cs);
4011
4012 /*
4013 * Wa_1604544889:tgl
4014 */
4015 if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
4016 flags = 0;
4017 flags |= PIPE_CONTROL_CS_STALL;
4018 flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
4019
4020 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
4021 flags |= PIPE_CONTROL_QW_WRITE;
4022
4023 cs = intel_ring_begin(request, 6);
4024 if (IS_ERR(cs))
4025 return PTR_ERR(cs);
4026
4027 cs = gen8_emit_pipe_control(cs, flags,
4028 LRC_PPHWSP_SCRATCH_ADDR);
4029 intel_ring_advance(request, cs);
4030 }
4031 }4003 }
4032 4004
4033 return 0;4005 return 0;
drivers/gpu/drm/i915/gt/intel_workarounds.c+22−3
@@ -1529,15 +1529,34 @@ err_obj: · 1528 unmodified lines
1529 return ERR_PTR(err);1529 return ERR_PTR(err);
1530}1530}
1531 1531
1532static const struct {
1533 u32 start;
1534 u32 end;
1535} mcr_ranges_gen8[] = {
1536 { .start = 0x5500, .end = 0x55ff },
1537 { .start = 0x7000, .end = 0x7fff },
1538 { .start = 0x9400, .end = 0x97ff },
1539 { .start = 0xb000, .end = 0xb3ff },
1540 { .start = 0xe000, .end = 0xe7ff },
1541 {},
1542};
1543
1532static bool mcr_range(struct drm_i915_private *i915, u32 offset)1544static bool mcr_range(struct drm_i915_private *i915, u32 offset)
1533{1545{
1546 int i;
1547
1548 if (INTEL_GEN(i915) < 8)
1549 return false;
1550
1534 /*1551 /*
1535 * Registers in this range are affected by the MCR selector1552 * Registers in these ranges are affected by the MCR selector
1536 * which only controls CPU initiated MMIO. Routing does not1553 * which only controls CPU initiated MMIO. Routing does not
1537 * work for CS access so we cannot verify them on this path.1554 * work for CS access so we cannot verify them on this path.
1538 */1555 */
1539 if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff))1556 for (i = 0; mcr_ranges_gen8[i].start; i++)
1540 return true;1557 if (offset >= mcr_ranges_gen8[i].start &&
1558 offset <= mcr_ranges_gen8[i].end)
1559 return true;
1541 1560
1542 return false;1561 return false;
1543}1562}

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