History

Merge tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes, nothing too exciting about this. Some changes hit arch/sh and arch/arm but are well isolated and acknowledged by the respective arch maintainers. Core changes: - Dropped the chained IRQ setup callback into GPIOLIB as we got rid of the last users of that in this changeset. New drivers: - New driver for Ingenic X1830. - New driver for Freescale i.MX8MP. Driver enhancements: - Fix all remaining Intel drivers to pass their IRQ chips along with the GPIO chips. - Intel Baytrail allocates its irqchip dynamically. - Intel Lynxpoint is thoroughly rewritten and modernized. - Aspeed AST2600 pin muxing and configuration is much improved. - Qualcomm SC7180 functions are updated and wakeup interrupt map is provided. - A whole slew of Renesas SH-PFC cleanups and improvements. - Fix up the Intel DT bindings to use the generic YAML DT bindings schema (a first user of this)" * tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: madera: Remove extra blank line pinctrl: qcom: Don't lock around irq_set_irq_wake() pinctrl: mvebu: armada-37xx: use use platform api gpio: Drop the chained IRQ handler assign function pinctrl: freescale: Add i.MX8MP pinctrl driver support dt-bindings: imx: Add pinctrl binding doc for i.MX8MP pinctrl: tigerlake: Tiger Lake uses _HID enumeration pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID pinctrl: iproc: Use platform_get_irq_optional() to avoid error message pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema pinctrl: intel: Pass irqchip when adding gpiochip pinctrl: intel: Add GPIO <-> pin mapping ranges via callback pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins pinctrl: sunrisepoint: Add missing Interrupt Status register offset pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers pinctrl: artpec6: fix __iomem on reg in set pinctrl: ingenic: Use devm_platform_ioremap_resource() pinctrl: ingenic: Factorize irq_set_type function pinctrl: ingenic: Remove duplicated ingenic_chip_info structures ...

Linus Torvalds committed 6 years ago

Commit 6ba3d702 parents fa889d8 122ce2272 files · +3353 −1784Browse files

Unified · Split

72 files
  1. Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +5 −4
  2. Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml +69 −0
  3. Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt +5 −3
  4. Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml +75 −0
  5. Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml +0 −116
  6. Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml +1 −1
  7. Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt +3 −2
  8. Documentation/driver-api/gpio/driver.rst +0 −5
  9. MAINTAINERS +0 −1
  10. arch/arm/mach-u300/core.c +1 −1
  11. arch/sh/include/cpu-sh2a/cpu/sh7264.h +0 −6
  12. arch/sh/include/cpu-sh2a/cpu/sh7269.h +9 −8
  13. drivers/gpio/Kconfig +0 −8
  14. drivers/gpio/Makefile +0 −1
  15. drivers/gpio/gpio-lynxpoint.c +0 −471
  16. drivers/gpio/gpio-mt7621.c +1 −2
  17. drivers/gpio/gpio-xgs-iproc.c +1 −2
  18. drivers/gpio/gpiolib.c +1 −24
  19. drivers/pinctrl/actions/pinctrl-s700.c +0 −1
  20. drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +90 −80
  21. drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +111 −101
  22. drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +386 −1
  23. drivers/pinctrl/aspeed/pinctrl-aspeed.c +11 −39
  24. drivers/pinctrl/aspeed/pinctrl-aspeed.h +36 −2
  25. drivers/pinctrl/aspeed/pinmux-aspeed.h +1 −0
  26. drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +8 −2
  27. drivers/pinctrl/cirrus/pinctrl-madera-core.c +0 −1
  28. drivers/pinctrl/core.c +16 −25
  29. drivers/pinctrl/core.h +0 −4
  30. drivers/pinctrl/devicetree.c +2 −2
  31. drivers/pinctrl/freescale/Kconfig +7 −0
  32. drivers/pinctrl/freescale/Makefile +1 −0
  33. drivers/pinctrl/freescale/pinctrl-imx8mp.c +345 −0
  34. drivers/pinctrl/intel/Kconfig +13 −0
  35. drivers/pinctrl/intel/Makefile +1 −0
  36. drivers/pinctrl/intel/pinctrl-baytrail.c +150 −161
  37. drivers/pinctrl/intel/pinctrl-cherryview.c +4 −1
  38. drivers/pinctrl/intel/pinctrl-intel.c +40 −61
  39. drivers/pinctrl/intel/pinctrl-intel.h +44 −0
  40. drivers/pinctrl/intel/pinctrl-lynxpoint.c +975 −0
  41. drivers/pinctrl/intel/pinctrl-sunrisepoint.c +1 −0
  42. drivers/pinctrl/intel/pinctrl-tigerlake.c +250 −297
  43. drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h +1 −1
  44. drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h +1 −1
  45. drivers/pinctrl/meson/pinctrl-meson8b.c +6 −1
  46. drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +11 −5
  47. drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +1 −1
  48. drivers/pinctrl/pinctrl-artpec6.c +1 −1
  49. drivers/pinctrl/pinctrl-ingenic.c +442 −195
  50. drivers/pinctrl/pinctrl-rza1.c +2 −2
  51. drivers/pinctrl/qcom/pinctrl-msm.c +0 −5
  52. drivers/pinctrl/qcom/pinctrl-msm8976.c +1 −1
  53. drivers/pinctrl/qcom/pinctrl-sc7180.c +58 −20
  54. drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +1 −1
  55. drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +1 −1
  56. drivers/pinctrl/samsung/Kconfig +10 −6
  57. drivers/pinctrl/sh-pfc/Kconfig +8 −4
  58. drivers/pinctrl/sh-pfc/Makefile +2 −2
  59. drivers/pinctrl/sh-pfc/core.c +44 −13
  60. drivers/pinctrl/sh-pfc/gpio.c +5 −6
  61. drivers/pinctrl/sh-pfc/pfc-r8a7778.c +2 −2
  62. drivers/pinctrl/sh-pfc/pfc-r8a77950.c +13 −13
  63. drivers/pinctrl/sh-pfc/pfc-r8a77951.c +13 −26
  64. drivers/pinctrl/sh-pfc/pfc-r8a77965.c +3 −3
  65. drivers/pinctrl/sh-pfc/pfc-sh7264.c +16 −17
  66. drivers/pinctrl/sh-pfc/pfc-sh7269.c +27 −12
  67. drivers/pinctrl/sh-pfc/sh_pfc.h +2 −2
  68. drivers/pinctrl/stm32/pinctrl-stm32.h +1 −1
  69. drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c +11 −2
  70. drivers/pinctrl/tegra/pinctrl-tegra.c +2 −2
  71. include/linux/gpio/driver.h +0 −5
  72. include/linux/pinctrl/machine.h +5 −0
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml+5−4
@@ -54,8 +54,9 @@ patternProperties: · 53 unmodified lines
54 TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,54 TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
55 TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,55 TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
56 THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,56 THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,
57 UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,57 UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
58 WDTRST3, WDTRST4, ]58 USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
59 WDTRST4, ]
59 groups:60 groups:
60 allOf:61 allOf:
61 - $ref: "/schemas/types.yaml#/definitions/string"62 - $ref: "/schemas/types.yaml#/definitions/string"
@@ -85,8 +86,8 @@ patternProperties: · 23 unmodified lines
85 TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,86 TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
86 TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,87 TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
87 THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,88 THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,
88 UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB,89 UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, USBA,
89 VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]90 USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]
90 91
91required:92required:
92 - compatible93 - compatible
Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml+69−0
@@ -0,0 +1,69 @@
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale IMX8MP IOMUX Controller
8
9maintainers:
10 - Anson Huang <Anson.Huang@nxp.com>
11
12description:
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
14 for common binding part and usage.
15
16properties:
17 compatible:
18 const: fsl,imx8mp-iomuxc
19
20 reg:
21 maxItems: 1
22
23# Client device subnode's properties
24patternProperties:
25 'grp$':
26 type: object
27 description:
28 Pinctrl node's client devices use subnodes for desired pin configuration.
29 Client device subnodes use below standard properties.
30
31 properties:
32 fsl,pins:
33 allOf:
34 - $ref: /schemas/types.yaml#/definitions/uint32-array
35 description:
36 each entry consists of 6 integers and represents the mux and config
37 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
38 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
39 be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
40 integer CONFIG is the pad setting value like pull-up on this pin. Please
41 refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
42
43 required:
44 - fsl,pins
45
46 additionalProperties: false
47
48required:
49 - compatible
50 - reg
51
52additionalProperties: false
53
54examples:
55 # Pinmux controller node
56 - |
57 iomuxc: pinctrl@30330000 {
58 compatible = "fsl,imx8mp-iomuxc";
59 reg = <0x30330000 0x10000>;
60
61 pinctrl_uart2: uart2grp {
62 fsl,pins = <
63 0x228 0x488 0x5F0 0x0 0x6 0x49
64 0x228 0x488 0x000 0x0 0x0 0x49
65 >;
66 };
67 };
68
69...
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt+5−3
@@ -10,9 +10,9 @@ GPIO port configuration registers and it is typical to refer to pins using the · 9 unmodified lines
10naming scheme "PxN" where x is a character identifying the GPIO port with10naming scheme "PxN" where x is a character identifying the GPIO port with
11which the pin is associated and N is an integer from 0 to 31 identifying the11which the pin is associated and N is an integer from 0 to 31 identifying the
12pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and12pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
13PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO13PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
14ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz478014contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
15contains 6 GPIO ports, PA to PF, for a total of 192 pins.15jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
16 16
17 17
18Required properties:18Required properties:
@@ -28,6 +28,7 @@ Required properties: · 9 unmodified lines
28 - "ingenic,x1000-pinctrl"28 - "ingenic,x1000-pinctrl"
29 - "ingenic,x1000e-pinctrl"29 - "ingenic,x1000e-pinctrl"
30 - "ingenic,x1500-pinctrl"30 - "ingenic,x1500-pinctrl"
31 - "ingenic,x1830-pinctrl"
31 - reg: Address range of the pinctrl registers.32 - reg: Address range of the pinctrl registers.
32 33
33 34
@@ -40,6 +41,7 @@ Required properties for sub-nodes (GPIO chips): · 6 unmodified lines
40 - "ingenic,jz4770-gpio"41 - "ingenic,jz4770-gpio"
41 - "ingenic,jz4780-gpio"42 - "ingenic,jz4780-gpio"
42 - "ingenic,x1000-gpio"43 - "ingenic,x1000-gpio"
44 - "ingenic,x1830-gpio"
43 - reg: The GPIO bank number.45 - reg: The GPIO bank number.
44 - interrupt-controller: Marks the device node as an interrupt controller.46 - interrupt-controller: Marks the device node as an interrupt controller.
45 - interrupts: Interrupt specifier for the controllers interrupt.47 - interrupts: Interrupt specifier for the controllers interrupt.
Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml+75−0
@@ -0,0 +1,75 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
8
9maintainers:
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
11
12description: |
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
14 GPIO function selection & GPIO attributes configuration.
15
16properties:
17 compatible:
18 const: intel,lgm-io
19
20 reg:
21 maxItems: 1
22
23# Client device subnode's properties
24patternProperties:
25 '-pins$':
26 type: object
27 allOf:
28 - $ref: pincfg-node.yaml#
29 - $ref: pinmux-node.yaml#
30 description:
31 Pinctrl node's client devices use subnodes for desired pin configuration.
32 Client device subnodes use below standard properties.
33
34 properties:
35 function: true
36 groups: true
37 pins: true
38 pinmux: true
39 bias-pull-up: true
40 bias-pull-down: true
41 drive-strength: true
42 slew-rate: true
43 drive-open-drain: true
44 output-enable: true
45
46 required:
47 - function
48 - groups
49
50 additionalProperties: false
51
52required:
53 - compatible
54 - reg
55
56additionalProperties: false
57
58examples:
59 # Pinmux controller node
60 - |
61 pinctrl: pinctrl@e2880000 {
62 compatible = "intel,lgm-io";
63 reg = <0xe2880000 0x100000>;
64
65 uart0-pins {
66 pins = <64>, /* UART_RX0 */
67 <65>; /* UART_TX0 */
68 function = "CONSOLE_UART0";
69 pinmux = <1>,
70 <1>;
71 groups = "CONSOLE_UART0";
72 };
73 };
74
75...
Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml+0−116
@@ -1,116 +0,0 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
8
9maintainers:
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
11
12description: |
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
14 GPIO function selection & GPIO attributes configuration.
15
16 Please refer to [1] for details of the common pinctrl bindings used by the
17 client devices.
18
19 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
20
21properties:
22 compatible:
23 const: intel,lgm-io
24
25 reg:
26 maxItems: 1
27
28# Client device subnode's properties
29patternProperties:
30 '-pins$':
31 type: object
32 description:
33 Pinctrl node's client devices use subnodes for desired pin configuration.
34 Client device subnodes use below standard properties.
35
36 properties:
37 function:
38 $ref: /schemas/types.yaml#/definitions/string
39 description:
40 A string containing the name of the function to mux to the group.
41
42 groups:
43 $ref: /schemas/types.yaml#/definitions/string-array
44 description:
45 An array of strings identifying the list of groups.
46
47 pins:
48 $ref: /schemas/types.yaml#/definitions/uint32-array
49 description:
50 List of pins to select with this function.
51
52 pinmux:
53 description: The applicable mux group.
54 allOf:
55 - $ref: "/schemas/types.yaml#/definitions/uint32-array"
56
57 bias-pull-up:
58 type: boolean
59
60 bias-pull-down:
61 type: boolean
62
63 drive-strength:
64 description: |
65 Selects the drive strength for the specified pins in mA.
66 0: 2 mA
67 1: 4 mA
68 2: 8 mA
69 3: 12 mA
70 allOf:
71 - $ref: /schemas/types.yaml#/definitions/uint32
72 - enum: [0, 1, 2, 3]
73
74 slew-rate:
75 type: boolean
76 description: |
77 Sets slew rate for specified pins.
78 0: slow slew
79 1: fast slew
80
81 drive-open-drain:
82 type: boolean
83
84 output-enable:
85 type: boolean
86
87 required:
88 - function
89 - groups
90
91 additionalProperties: false
92
93required:
94 - compatible
95 - reg
96
97additionalProperties: false
98
99examples:
100 # Pinmux controller node
101 - |
102 pinctrl: pinctrl@e2880000 {
103 compatible = "intel,lgm-pinctrl";
104 reg = <0xe2880000 0x100000>;
105
106 uart0-pins {
107 pins = <64>, /* UART_RX0 */
108 <65>; /* UART_TX0 */
109 function = "CONSOLE_UART0";
110 pinmux = <1>,
111 <1>;
112 groups = "CONSOLE_UART0";
113 };
114 };
115
116...
Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml+1−1
@@ -114,7 +114,7 @@ properties: · 113 unmodified lines
114 specific binding for the hardware defines whether the entries are integers114 specific binding for the hardware defines whether the entries are integers
115 or strings, and their meaning.115 or strings, and their meaning.
116 116
117 group:117 groups:
118 $ref: /schemas/types.yaml#/definitions/string-array118 $ref: /schemas/types.yaml#/definitions/string-array
119 description:119 description:
120 the group to apply the properties to, if the driver supports120 the group to apply the properties to, if the driver supports
Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt+3−2
@@ -125,8 +125,9 @@ to specify in a pin configuration subnode: · 124 unmodified lines
125 mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag,125 mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag,
126 PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss,126 PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss,
127 qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs,127 qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs,
128 qspi_data, qup00, qup01, qup02, qup03, qup04, qup05,128 qspi_data, qup00, qup01, qup02_i2c, qup02_uart, qup03,
129 qup10, qup11, qup12, qup13, qup14, qup15, sdc1_tb,129 qup04_i2c, qup04_uart, qup05, qup10, qup11_i2c, qup11_uart,
130 qup12, qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb,
130 sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2,131 sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2,
131 tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt,132 tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt,
132 usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT,133 usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT,
Documentation/driver-api/gpio/driver.rst+0−5
@@ -507,11 +507,6 @@ available but we try to move away from this: · 506 unmodified lines
507 cascaded irq has to be handled by a threaded interrupt handler.507 cascaded irq has to be handled by a threaded interrupt handler.
508 Apart from that it works exactly like the chained irqchip.508 Apart from that it works exactly like the chained irqchip.
509 509
510- DEPRECATED: gpiochip_set_chained_irqchip(): sets up a chained cascaded irq
511 handler for a gpio_chip from a parent IRQ and passes the struct gpio_chip*
512 as handler data. Notice that we pass is as the handler data, since the
513 irqchip data is likely used by the parent irqchip.
514
515- gpiochip_set_nested_irqchip(): sets up a nested cascaded irq handler for a510- gpiochip_set_nested_irqchip(): sets up a nested cascaded irq handler for a
516 gpio_chip from a parent IRQ. As the parent IRQ has usually been511 gpio_chip from a parent IRQ. As the parent IRQ has usually been
517 explicitly requested by the driver, this does very little more than512 explicitly requested by the driver, this does very little more than
MAINTAINERS+0−1
@@ -8383,7 +8383,6 @@ S: Maintained · 8382 unmodified lines
8383T: git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git8383T: git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git
8384F: drivers/gpio/gpio-ich.c8384F: drivers/gpio/gpio-ich.c
8385F: drivers/gpio/gpio-intel-mid.c8385F: drivers/gpio/gpio-intel-mid.c
8386F: drivers/gpio/gpio-lynxpoint.c
8387F: drivers/gpio/gpio-merrifield.c8386F: drivers/gpio/gpio-merrifield.c
8388F: drivers/gpio/gpio-ml-ioh.c8387F: drivers/gpio/gpio-ml-ioh.c
8389F: drivers/gpio/gpio-pch.c8388F: drivers/gpio/gpio-pch.c
arch/arm/mach-u300/core.c+1−1
@@ -201,7 +201,7 @@ static unsigned long pin_highz_conf[] = { · 200 unmodified lines
201};201};
202 202
203/* Pin control settings */203/* Pin control settings */
204static struct pinctrl_map __initdata u300_pinmux_map[] = {204static const struct pinctrl_map u300_pinmux_map[] = {
205 /* anonymous maps for chip power and EMIFs */205 /* anonymous maps for chip power and EMIFs */
206 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),206 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
207 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),207 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
arch/sh/include/cpu-sh2a/cpu/sh7264.h+0−6
@@ -112,12 +112,6 @@ enum { · 111 unmodified lines
112 GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,112 GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
113 GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,113 GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
114 114
115 /* SSU */
116 GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
117 GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
118 GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
119 GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
120
121 /* SCIF */115 /* SCIF */
122 GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3,116 GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3,
123 GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3,117 GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3,
arch/sh/include/cpu-sh2a/cpu/sh7269.h+9−8
@@ -78,8 +78,15 @@ enum { · 77 unmodified lines
78 GPIO_FN_WDTOVF,78 GPIO_FN_WDTOVF,
79 79
80 /* CAN */80 /* CAN */
81 GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,81 GPIO_FN_CTX2, GPIO_FN_CRX2,
82 GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2,82 GPIO_FN_CTX1, GPIO_FN_CRX1,
83 GPIO_FN_CTX0, GPIO_FN_CRX0,
84 GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0_CRX1,
85 GPIO_FN_CTX0_CTX1_CTX2, GPIO_FN_CRX0_CRX1_CRX2,
86 GPIO_FN_CTX2_PJ21, GPIO_FN_CRX2_PJ20,
87 GPIO_FN_CTX1_PJ23, GPIO_FN_CRX1_PJ22,
88 GPIO_FN_CTX0_CTX1_PJ23, GPIO_FN_CRX0_CRX1_PJ22,
89 GPIO_FN_CTX0_CTX1_CTX2_PJ21, GPIO_FN_CRX0_CRX1_CRX2_PJ20,
83 90
84 /* DMAC */91 /* DMAC */
85 GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,92 GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
@@ -119,12 +126,6 @@ enum { · 33 unmodified lines
119 GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,126 GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
120 GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,127 GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
121 128
122 /* SSU */
123 GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
124 GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
125 GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
126 GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
127
128 /* SCIF */129 /* SCIF */
129 GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0,130 GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0,
130 GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1,131 GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1,
drivers/gpio/Kconfig+0−8
@@ -341,14 +341,6 @@ config GPIO_LPC32XX · 340 unmodified lines
341 Select this option to enable GPIO driver for341 Select this option to enable GPIO driver for
342 NXP LPC32XX devices.342 NXP LPC32XX devices.
343 343
344config GPIO_LYNXPOINT
345 tristate "Intel Lynxpoint GPIO support"
346 depends on ACPI && X86
347 select GPIOLIB_IRQCHIP
348 help
349 driver for GPIO functionality on Intel Lynxpoint PCH chipset
350 Requires ACPI device enumeration code to set up a platform device.
351
352config GPIO_MB86S7X344config GPIO_MB86S7X
353 tristate "GPIO support for Fujitsu MB86S7x Platforms"345 tristate "GPIO support for Fujitsu MB86S7x Platforms"
354 help346 help
drivers/gpio/Makefile+0−1
@@ -77,7 +77,6 @@ obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o · 76 unmodified lines
77obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o77obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
78obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o78obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
79obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o79obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
80obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
81obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o80obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
82obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o81obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
83obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o82obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
drivers/gpio/gpio-lynxpoint.c+0−471
@@ -1,471 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * GPIO controller driver for Intel Lynxpoint PCH chipset>
4 * Copyright (c) 2012, Intel Corporation.
5 *
6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 */
8
9#include <linux/acpi.h>
10#include <linux/bitops.h>
11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/slab.h>
19#include <linux/types.h>
20
21/* LynxPoint chipset has support for 94 gpio pins */
22
23#define LP_NUM_GPIO 94
24
25/* Bitmapped register offsets */
26#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
27#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
28#define LP_INT_STAT 0x80
29#define LP_INT_ENABLE 0x90
30
31/* Each pin has two 32 bit config registers, starting at 0x100 */
32#define LP_CONFIG1 0x100
33#define LP_CONFIG2 0x104
34
35/* LP_CONFIG1 reg bits */
36#define OUT_LVL_BIT BIT(31)
37#define IN_LVL_BIT BIT(30)
38#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
39#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
40#define DIR_BIT BIT(2) /* 0: Output, 1: Input */
41#define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */
42
43/* LP_CONFIG2 reg bits */
44#define GPINDIS_BIT BIT(2) /* disable input sensing */
45#define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */
46
47struct lp_gpio {
48 struct gpio_chip chip;
49 struct platform_device *pdev;
50 spinlock_t lock;
51 unsigned long reg_base;
52};
53
54/*
55 * Lynxpoint gpios are controlled through both bitmapped registers and
56 * per gpio specific registers. The bitmapped registers are in chunks of
57 * 3 x 32bit registers to cover all 94 gpios
58 *
59 * per gpio specific registers consist of two 32bit registers per gpio
60 * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
61 * 188 config registers.
62 *
63 * A simplified view of the register layout look like this:
64 *
65 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
66 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
67 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
68 * ...
69 * LP_INT_ENABLE[31:0] ...
70 * LP_INT_ENABLE[63:31] ...
71 * LP_INT_ENABLE[94:64] ...
72 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
73 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
74 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
75 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
76 * LP2_CONFIG1 (gpio 2) ...
77 * LP2_CONFIG2 (gpio 2) ...
78 * ...
79 * LP94_CONFIG1 (gpio 94) ...
80 * LP94_CONFIG2 (gpio 94) ...
81 */
82
83static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
84 int reg)
85{
86 struct lp_gpio *lg = gpiochip_get_data(chip);
87 int reg_offset;
88
89 if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
90 /* per gpio specific config registers */
91 reg_offset = offset * 8;
92 else
93 /* bitmapped registers */
94 reg_offset = (offset / 32) * 4;
95
96 return lg->reg_base + reg + reg_offset;
97}
98
99static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
100{
101 struct lp_gpio *lg = gpiochip_get_data(chip);
102 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
103 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
104 unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
105
106 pm_runtime_get(&lg->pdev->dev); /* should we put if failed */
107
108 /* Fail if BIOS reserved pin for ACPI use */
109 if (!(inl(acpi_use) & BIT(offset % 32))) {
110 dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
111 return -EBUSY;
112 }
113 /* Fail if pin is in alternate function mode (not GPIO mode) */
114 if (!(inl(reg) & USE_SEL_BIT))
115 return -ENODEV;
116
117 /* enable input sensing */
118 outl(inl(conf2) & ~GPINDIS_BIT, conf2);
119
120
121 return 0;
122}
123
124static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
125{
126 struct lp_gpio *lg = gpiochip_get_data(chip);
127 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
128
129 /* disable input sensing */
130 outl(inl(conf2) | GPINDIS_BIT, conf2);
131
132 pm_runtime_put(&lg->pdev->dev);
133}
134
135static int lp_irq_type(struct irq_data *d, unsigned type)
136{
137 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
138 struct lp_gpio *lg = gpiochip_get_data(gc);
139 u32 hwirq = irqd_to_hwirq(d);
140 unsigned long flags;
141 u32 value;
142 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
143
144 if (hwirq >= lg->chip.ngpio)
145 return -EINVAL;
146
147 spin_lock_irqsave(&lg->lock, flags);
148 value = inl(reg);
149
150 /* set both TRIG_SEL and INV bits to 0 for rising edge */
151 if (type & IRQ_TYPE_EDGE_RISING)
152 value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
153
154 /* TRIG_SEL bit 0, INV bit 1 for falling edge */
155 if (type & IRQ_TYPE_EDGE_FALLING)
156 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
157
158 /* TRIG_SEL bit 1, INV bit 0 for level low */
159 if (type & IRQ_TYPE_LEVEL_LOW)
160 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
161
162 /* TRIG_SEL bit 1, INV bit 1 for level high */
163 if (type & IRQ_TYPE_LEVEL_HIGH)
164 value |= TRIG_SEL_BIT | INT_INV_BIT;
165
166 outl(value, reg);
167
168 if (type & IRQ_TYPE_EDGE_BOTH)
169 irq_set_handler_locked(d, handle_edge_irq);
170 else if (type & IRQ_TYPE_LEVEL_MASK)
171 irq_set_handler_locked(d, handle_level_irq);
172
173 spin_unlock_irqrestore(&lg->lock, flags);
174
175 return 0;
176}
177
178static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
179{
180 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
181 return !!(inl(reg) & IN_LVL_BIT);
182}
183
184static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
185{
186 struct lp_gpio *lg = gpiochip_get_data(chip);
187 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
188 unsigned long flags;
189
190 spin_lock_irqsave(&lg->lock, flags);
191
192 if (value)
193 outl(inl(reg) | OUT_LVL_BIT, reg);
194 else
195 outl(inl(reg) & ~OUT_LVL_BIT, reg);
196
197 spin_unlock_irqrestore(&lg->lock, flags);
198}
199
200static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
201{
202 struct lp_gpio *lg = gpiochip_get_data(chip);
203 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
204 unsigned long flags;
205
206 spin_lock_irqsave(&lg->lock, flags);
207 outl(inl(reg) | DIR_BIT, reg);
208 spin_unlock_irqrestore(&lg->lock, flags);
209
210 return 0;
211}
212
213static int lp_gpio_direction_output(struct gpio_chip *chip,
214 unsigned offset, int value)
215{
216 struct lp_gpio *lg = gpiochip_get_data(chip);
217 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
218 unsigned long flags;
219
220 lp_gpio_set(chip, offset, value);
221
222 spin_lock_irqsave(&lg->lock, flags);
223 outl(inl(reg) & ~DIR_BIT, reg);
224 spin_unlock_irqrestore(&lg->lock, flags);
225
226 return 0;
227}
228
229static void lp_gpio_irq_handler(struct irq_desc *desc)
230{
231 struct irq_data *data = irq_desc_get_irq_data(desc);
232 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
233 struct lp_gpio *lg = gpiochip_get_data(gc);
234 struct irq_chip *chip = irq_data_get_irq_chip(data);
235 unsigned long reg, ena, pending;
236 u32 base, pin;
237
238 /* check from GPIO controller which pin triggered the interrupt */
239 for (base = 0; base < lg->chip.ngpio; base += 32) {
240 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
241 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
242
243 /* Only interrupts that are enabled */
244 pending = inl(reg) & inl(ena);
245
246 for_each_set_bit(pin, &pending, 32) {
247 unsigned irq;
248
249 /* Clear before handling so we don't lose an edge */
250 outl(BIT(pin), reg);
251
252 irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
253 generic_handle_irq(irq);
254 }
255 }
256 chip->irq_eoi(data);
257}
258
259static void lp_irq_unmask(struct irq_data *d)
260{
261}
262
263static void lp_irq_mask(struct irq_data *d)
264{
265}
266
267static void lp_irq_enable(struct irq_data *d)
268{
269 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
270 struct lp_gpio *lg = gpiochip_get_data(gc);
271 u32 hwirq = irqd_to_hwirq(d);
272 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
273 unsigned long flags;
274
275 spin_lock_irqsave(&lg->lock, flags);
276 outl(inl(reg) | BIT(hwirq % 32), reg);
277 spin_unlock_irqrestore(&lg->lock, flags);
278}
279
280static void lp_irq_disable(struct irq_data *d)
281{
282 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
283 struct lp_gpio *lg = gpiochip_get_data(gc);
284 u32 hwirq = irqd_to_hwirq(d);
285 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
286 unsigned long flags;
287
288 spin_lock_irqsave(&lg->lock, flags);
289 outl(inl(reg) & ~BIT(hwirq % 32), reg);
290 spin_unlock_irqrestore(&lg->lock, flags);
291}
292
293static struct irq_chip lp_irqchip = {
294 .name = "LP-GPIO",
295 .irq_mask = lp_irq_mask,
296 .irq_unmask = lp_irq_unmask,
297 .irq_enable = lp_irq_enable,
298 .irq_disable = lp_irq_disable,
299 .irq_set_type = lp_irq_type,
300 .flags = IRQCHIP_SKIP_SET_WAKE,
301};
302
303static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
304{
305 struct lp_gpio *lg = gpiochip_get_data(chip);
306 unsigned long reg;
307 unsigned base;
308
309 for (base = 0; base < lg->chip.ngpio; base += 32) {
310 /* disable gpio pin interrupts */
311 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
312 outl(0, reg);
313 /* Clear interrupt status register */
314 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
315 outl(0xffffffff, reg);
316 }
317
318 return 0;
319}
320
321static int lp_gpio_probe(struct platform_device *pdev)
322{
323 struct lp_gpio *lg;
324 struct gpio_chip *gc;
325 struct resource *io_rc, *irq_rc;
326 struct device *dev = &pdev->dev;
327 unsigned long reg_len;
328 int ret = -ENODEV;
329
330 lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
331 if (!lg)
332 return -ENOMEM;
333
334 lg->pdev = pdev;
335 platform_set_drvdata(pdev, lg);
336
337 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
338 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
339
340 if (!io_rc) {
341 dev_err(dev, "missing IO resources\n");
342 return -EINVAL;
343 }
344
345 lg->reg_base = io_rc->start;
346 reg_len = resource_size(io_rc);
347
348 if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
349 dev_err(dev, "failed requesting IO region 0x%x\n",
350 (unsigned int)lg->reg_base);
351 return -EBUSY;
352 }
353
354 spin_lock_init(&lg->lock);
355
356 gc = &lg->chip;
357 gc->label = dev_name(dev);
358 gc->owner = THIS_MODULE;
359 gc->request = lp_gpio_request;
360 gc->free = lp_gpio_free;
361 gc->direction_input = lp_gpio_direction_input;
362 gc->direction_output = lp_gpio_direction_output;
363 gc->get = lp_gpio_get;
364 gc->set = lp_gpio_set;
365 gc->base = -1;
366 gc->ngpio = LP_NUM_GPIO;
367 gc->can_sleep = false;
368 gc->parent = dev;
369
370 /* set up interrupts */
371 if (irq_rc && irq_rc->start) {
372 struct gpio_irq_chip *girq;
373
374 girq = &gc->irq;
375 girq->chip = &lp_irqchip;
376 girq->init_hw = lp_gpio_irq_init_hw;
377 girq->parent_handler = lp_gpio_irq_handler;
378 girq->num_parents = 1;
379 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
380 sizeof(*girq->parents),
381 GFP_KERNEL);
382 if (!girq->parents)
383 return -ENOMEM;
384 girq->parents[0] = (unsigned)irq_rc->start;
385 girq->default_type = IRQ_TYPE_NONE;
386 girq->handler = handle_bad_irq;
387 }
388
389 ret = devm_gpiochip_add_data(dev, gc, lg);
390 if (ret) {
391 dev_err(dev, "failed adding lp-gpio chip\n");
392 return ret;
393 }
394
395 pm_runtime_enable(dev);
396
397 return 0;
398}
399
400static int lp_gpio_runtime_suspend(struct device *dev)
401{
402 return 0;
403}
404
405static int lp_gpio_runtime_resume(struct device *dev)
406{
407 return 0;
408}
409
410static int lp_gpio_resume(struct device *dev)
411{
412 struct lp_gpio *lg = dev_get_drvdata(dev);
413 unsigned long reg;
414 int i;
415
416 /* on some hardware suspend clears input sensing, re-enable it here */
417 for (i = 0; i < lg->chip.ngpio; i++) {
418 if (gpiochip_is_requested(&lg->chip, i) != NULL) {
419 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
420 outl(inl(reg) & ~GPINDIS_BIT, reg);
421 }
422 }
423 return 0;
424}
425
426static const struct dev_pm_ops lp_gpio_pm_ops = {
427 .runtime_suspend = lp_gpio_runtime_suspend,
428 .runtime_resume = lp_gpio_runtime_resume,
429 .resume = lp_gpio_resume,
430};
431
432static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
433 { "INT33C7", 0 },
434 { "INT3437", 0 },
435 { }
436};
437MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
438
439static int lp_gpio_remove(struct platform_device *pdev)
440{
441 pm_runtime_disable(&pdev->dev);
442 return 0;
443}
444
445static struct platform_driver lp_gpio_driver = {
446 .probe = lp_gpio_probe,
447 .remove = lp_gpio_remove,
448 .driver = {
449 .name = "lp_gpio",
450 .pm = &lp_gpio_pm_ops,
451 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
452 },
453};
454
455static int __init lp_gpio_init(void)
456{
457 return platform_driver_register(&lp_gpio_driver);
458}
459
460static void __exit lp_gpio_exit(void)
461{
462 platform_driver_unregister(&lp_gpio_driver);
463}
464
465subsys_initcall(lp_gpio_init);
466module_exit(lp_gpio_exit);
467
468MODULE_AUTHOR("Mathias Nyman (Intel)");
469MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint");
470MODULE_LICENSE("GPL v2");
471MODULE_ALIAS("platform:lp_gpio");
drivers/gpio/gpio-mt7621.c+1−2
@@ -253,8 +253,7 @@ mediatek_gpio_bank_probe(struct device *dev, · 252 unmodified lines
253 253
254 /*254 /*
255 * Directly request the irq here instead of passing255 * Directly request the irq here instead of passing
256 * a flow-handler to gpiochip_set_chained_irqchip,256 * a flow-handler because the irq is shared.
257 * because the irq is shared.
258 */257 */
259 ret = devm_request_irq(dev, mtk->gpio_irq,258 ret = devm_request_irq(dev, mtk->gpio_irq,
260 mediatek_gpio_irq_handler, IRQF_SHARED,259 mediatek_gpio_irq_handler, IRQF_SHARED,
drivers/gpio/gpio-xgs-iproc.c+1−2
@@ -251,8 +251,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) · 250 unmodified lines
251 251
252 /*252 /*
253 * Directly request the irq here instead of passing253 * Directly request the irq here instead of passing
254 * a flow-handler to gpiochip_set_chained_irqchip,254 * a flow-handler because the irq is shared.
255 * because the irq is shared.
256 */255 */
257 ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler,256 ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler,
258 IRQF_SHARED, chip->gc.label, &chip->gc);257 IRQF_SHARED, chip->gc.label, &chip->gc);
drivers/gpio/gpiolib.c+1−24
@@ -1800,7 +1800,7 @@ EXPORT_SYMBOL_GPL(gpiochip_irqchip_irq_valid); · 1799 unmodified lines
1800 * gpiochip_set_cascaded_irqchip() - connects a cascaded irqchip to a gpiochip1800 * gpiochip_set_cascaded_irqchip() - connects a cascaded irqchip to a gpiochip
1801 * @gc: the gpiochip to set the irqchip chain to1801 * @gc: the gpiochip to set the irqchip chain to
1802 * @parent_irq: the irq number corresponding to the parent IRQ for this1802 * @parent_irq: the irq number corresponding to the parent IRQ for this
1803 * chained irqchip1803 * cascaded irqchip
1804 * @parent_handler: the parent interrupt handler for the accumulated IRQ1804 * @parent_handler: the parent interrupt handler for the accumulated IRQ
1805 * coming out of the gpiochip. If the interrupt is nested rather than1805 * coming out of the gpiochip. If the interrupt is nested rather than
1806 * cascaded, pass NULL in this handler argument1806 * cascaded, pass NULL in this handler argument
@@ -1842,29 +1842,6 @@ static void gpiochip_set_cascaded_irqchip(struct gpio_chip *gc, · 35 unmodified lines
1842 }1842 }
1843}1843}
1844 1844
1845/**
1846 * gpiochip_set_chained_irqchip() - connects a chained irqchip to a gpiochip
1847 * @gpiochip: the gpiochip to set the irqchip chain to
1848 * @irqchip: the irqchip to chain to the gpiochip
1849 * @parent_irq: the irq number corresponding to the parent IRQ for this
1850 * chained irqchip
1851 * @parent_handler: the parent interrupt handler for the accumulated IRQ
1852 * coming out of the gpiochip.
1853 */
1854void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
1855 struct irq_chip *irqchip,
1856 unsigned int parent_irq,
1857 irq_flow_handler_t parent_handler)
1858{
1859 if (gpiochip->irq.threaded) {
1860 chip_err(gpiochip, "tried to chain a threaded gpiochip\n");
1861 return;
1862 }
1863
1864 gpiochip_set_cascaded_irqchip(gpiochip, parent_irq, parent_handler);
1865}
1866EXPORT_SYMBOL_GPL(gpiochip_set_chained_irqchip);
1867
1868/**1845/**
1869 * gpiochip_set_nested_irqchip() - connects a nested irqchip to a gpiochip1846 * gpiochip_set_nested_irqchip() - connects a nested irqchip to a gpiochip
1870 * @gpiochip: the gpiochip to set the irqchip nested handler to1847 * @gpiochip: the gpiochip to set the irqchip nested handler to
drivers/pinctrl/actions/pinctrl-s700.c+0−1
@@ -1583,7 +1583,6 @@ static const struct owl_pinmux_func s700_functions[] = { · 1582 unmodified lines
1583 [S700_MUX_USB30] = FUNCTION(usb30),1583 [S700_MUX_USB30] = FUNCTION(usb30),
1584 [S700_MUX_CLKO_25M] = FUNCTION(clko_25m),1584 [S700_MUX_CLKO_25M] = FUNCTION(clko_25m),
1585 [S700_MUX_MIPI_CSI] = FUNCTION(mipi_csi),1585 [S700_MUX_MIPI_CSI] = FUNCTION(mipi_csi),
1586 [S700_MUX_DSI] = FUNCTION(dsi),
1587 [S700_MUX_NAND] = FUNCTION(nand),1586 [S700_MUX_NAND] = FUNCTION(nand),
1588 [S700_MUX_SPDIF] = FUNCTION(spdif),1587 [S700_MUX_SPDIF] = FUNCTION(spdif),
1589 [S700_MUX_SIRQ0] = FUNCTION(sirq0),1588 [S700_MUX_SIRQ0] = FUNCTION(sirq0),
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c+90−80
@@ -2439,88 +2439,88 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { · 2438 unmodified lines
2439 2439
2440static const struct aspeed_pin_config aspeed_g4_configs[] = {2440static const struct aspeed_pin_config aspeed_g4_configs[] = {
2441 /* GPIO banks ranges [A, B], [D, J], [M, R] */2441 /* GPIO banks ranges [A, B], [D, J], [M, R] */
2442 { PIN_CONFIG_BIAS_PULL_DOWN, { D6, D5 }, SCU8C, 16 },2442 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16),
2443 { PIN_CONFIG_BIAS_DISABLE, { D6, D5 }, SCU8C, 16 },2443 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16),
2444 { PIN_CONFIG_BIAS_PULL_DOWN, { J21, E18 }, SCU8C, 17 },2444 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J21, E18, SCU8C, 17),
2445 { PIN_CONFIG_BIAS_DISABLE, { J21, E18 }, SCU8C, 17 },2445 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J21, E18, SCU8C, 17),
2446 { PIN_CONFIG_BIAS_PULL_DOWN, { A18, E15 }, SCU8C, 19 },2446 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, E15, SCU8C, 19),
2447 { PIN_CONFIG_BIAS_DISABLE, { A18, E15 }, SCU8C, 19 },2447 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, E15, SCU8C, 19),
2448 { PIN_CONFIG_BIAS_PULL_DOWN, { D15, B14 }, SCU8C, 20 },2448 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20),
2449 { PIN_CONFIG_BIAS_DISABLE, { D15, B14 }, SCU8C, 20 },2449 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20),
2450 { PIN_CONFIG_BIAS_PULL_DOWN, { D18, C17 }, SCU8C, 21 },2450 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D18, C17, SCU8C, 21),
2451 { PIN_CONFIG_BIAS_DISABLE, { D18, C17 }, SCU8C, 21 },2451 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D18, C17, SCU8C, 21),
2452 { PIN_CONFIG_BIAS_PULL_DOWN, { A14, U18 }, SCU8C, 22 },2452 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A14, U18, SCU8C, 22),
2453 { PIN_CONFIG_BIAS_DISABLE, { A14, U18 }, SCU8C, 22 },2453 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A14, U18, SCU8C, 22),
2454 { PIN_CONFIG_BIAS_PULL_DOWN, { A8, E7 }, SCU8C, 23 },2454 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23),
2455 { PIN_CONFIG_BIAS_DISABLE, { A8, E7 }, SCU8C, 23 },2455 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23),
2456 { PIN_CONFIG_BIAS_PULL_DOWN, { C22, E20 }, SCU8C, 24 },2456 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C22, E20, SCU8C, 24),
2457 { PIN_CONFIG_BIAS_DISABLE, { C22, E20 }, SCU8C, 24 },2457 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C22, E20, SCU8C, 24),
2458 { PIN_CONFIG_BIAS_PULL_DOWN, { J5, T1 }, SCU8C, 25 },2458 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25),
2459 { PIN_CONFIG_BIAS_DISABLE, { J5, T1 }, SCU8C, 25 },2459 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25),
2460 { PIN_CONFIG_BIAS_PULL_DOWN, { U1, U5 }, SCU8C, 26 },2460 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U1, U5, SCU8C, 26),
2461 { PIN_CONFIG_BIAS_DISABLE, { U1, U5 }, SCU8C, 26 },2461 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U1, U5, SCU8C, 26),
2462 { PIN_CONFIG_BIAS_PULL_DOWN, { V3, V5 }, SCU8C, 27 },2462 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V3, V5, SCU8C, 27),
2463 { PIN_CONFIG_BIAS_DISABLE, { V3, V5 }, SCU8C, 27 },2463 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V3, V5, SCU8C, 27),
2464 { PIN_CONFIG_BIAS_PULL_DOWN, { W4, AB2 }, SCU8C, 28 },2464 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, W4, AB2, SCU8C, 28),
2465 { PIN_CONFIG_BIAS_DISABLE, { W4, AB2 }, SCU8C, 28 },2465 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, W4, AB2, SCU8C, 28),
2466 { PIN_CONFIG_BIAS_PULL_DOWN, { V6, V7 }, SCU8C, 29 },2466 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V6, V7, SCU8C, 29),
2467 { PIN_CONFIG_BIAS_DISABLE, { V6, V7 }, SCU8C, 29 },2467 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V6, V7, SCU8C, 29),
2468 { PIN_CONFIG_BIAS_PULL_DOWN, { Y6, AB7 }, SCU8C, 30 },2468 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y6, AB7, SCU8C, 30),
2469 { PIN_CONFIG_BIAS_DISABLE, { Y6, AB7 }, SCU8C, 30 },2469 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y6, AB7, SCU8C, 30),
2470 { PIN_CONFIG_BIAS_PULL_DOWN, { V20, A5 }, SCU8C, 31 },2470 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, A5, SCU8C, 31),
2471 { PIN_CONFIG_BIAS_DISABLE, { V20, A5 }, SCU8C, 31 },2471 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, A5, SCU8C, 31),
2472 2472
2473 /* GPIOs T[0-5] (RGMII1 Tx pins) */2473 /* GPIOs T[0-5] (RGMII1 Tx pins) */
2474 { PIN_CONFIG_DRIVE_STRENGTH, { A12, A13 }, SCU90, 9 },2474 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9),
2475 { PIN_CONFIG_BIAS_PULL_DOWN, { A12, A13 }, SCU90, 12 },2475 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12),
2476 { PIN_CONFIG_BIAS_DISABLE, { A12, A13 }, SCU90, 12 },2476 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A12, A13, SCU90, 12),
2477 2477
2478 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */2478 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
2479 { PIN_CONFIG_DRIVE_STRENGTH, { D9, D10 }, SCU90, 11 },2479 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, D9, D10, SCU90, 11),
2480 { PIN_CONFIG_BIAS_PULL_DOWN, { D9, D10 }, SCU90, 14 },2480 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D9, D10, SCU90, 14),
2481 { PIN_CONFIG_BIAS_DISABLE, { D9, D10 }, SCU90, 14 },2481 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D9, D10, SCU90, 14),
2482 2482
2483 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */2483 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2484 { PIN_CONFIG_BIAS_PULL_DOWN, { E11, E10 }, SCU90, 13 },2484 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13),
2485 { PIN_CONFIG_BIAS_DISABLE, { E11, E10 }, SCU90, 13 },2485 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13),
2486 2486
2487 /* GPIOs V[2-7] (RGMII2 Rx pins) */2487 /* GPIOs V[2-7] (RGMII2 Rx pins) */
2488 { PIN_CONFIG_BIAS_PULL_DOWN, { C9, C8 }, SCU90, 15 },2488 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15),
2489 { PIN_CONFIG_BIAS_DISABLE, { C9, C8 }, SCU90, 15 },2489 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15),
2490 2490
2491 /* ADC pull-downs (SCUA8[19:4]) */2491 /* ADC pull-downs (SCUA8[19:4]) */
2492 { PIN_CONFIG_BIAS_PULL_DOWN, { L5, L5 }, SCUA8, 4 },2492 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L5, L5, SCUA8, 4),
2493 { PIN_CONFIG_BIAS_DISABLE, { L5, L5 }, SCUA8, 4 },2493 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L5, L5, SCUA8, 4),
2494 { PIN_CONFIG_BIAS_PULL_DOWN, { L4, L4 }, SCUA8, 5 },2494 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L4, L4, SCUA8, 5),
2495 { PIN_CONFIG_BIAS_DISABLE, { L4, L4 }, SCUA8, 5 },2495 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L4, L4, SCUA8, 5),
2496 { PIN_CONFIG_BIAS_PULL_DOWN, { L3, L3 }, SCUA8, 6 },2496 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, L3, SCUA8, 6),
2497 { PIN_CONFIG_BIAS_DISABLE, { L3, L3 }, SCUA8, 6 },2497 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, L3, SCUA8, 6),
2498 { PIN_CONFIG_BIAS_PULL_DOWN, { L2, L2 }, SCUA8, 7 },2498 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7),
2499 { PIN_CONFIG_BIAS_DISABLE, { L2, L2 }, SCUA8, 7 },2499 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7),
2500 { PIN_CONFIG_BIAS_PULL_DOWN, { L1, L1 }, SCUA8, 8 },2500 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8),
2501 { PIN_CONFIG_BIAS_DISABLE, { L1, L1 }, SCUA8, 8 },2501 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8),
2502 { PIN_CONFIG_BIAS_PULL_DOWN, { M5, M5 }, SCUA8, 9 },2502 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M5, M5, SCUA8, 9),
2503 { PIN_CONFIG_BIAS_DISABLE, { M5, M5 }, SCUA8, 9 },2503 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M5, M5, SCUA8, 9),
2504 { PIN_CONFIG_BIAS_PULL_DOWN, { M4, M4 }, SCUA8, 10 },2504 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M4, M4, SCUA8, 10),
2505 { PIN_CONFIG_BIAS_DISABLE, { M4, M4 }, SCUA8, 10 },2505 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M4, M4, SCUA8, 10),
2506 { PIN_CONFIG_BIAS_PULL_DOWN, { M3, M3 }, SCUA8, 11 },2506 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M3, M3, SCUA8, 11),
2507 { PIN_CONFIG_BIAS_DISABLE, { M3, M3 }, SCUA8, 11 },2507 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M3, M3, SCUA8, 11),
2508 { PIN_CONFIG_BIAS_PULL_DOWN, { M2, M2 }, SCUA8, 12 },2508 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12),
2509 { PIN_CONFIG_BIAS_DISABLE, { M2, M2 }, SCUA8, 12 },2509 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12),
2510 { PIN_CONFIG_BIAS_PULL_DOWN, { M1, M1 }, SCUA8, 13 },2510 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13),
2511 { PIN_CONFIG_BIAS_DISABLE, { M1, M1 }, SCUA8, 13 },2511 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13),
2512 { PIN_CONFIG_BIAS_PULL_DOWN, { N5, N5 }, SCUA8, 14 },2512 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N5, N5, SCUA8, 14),
2513 { PIN_CONFIG_BIAS_DISABLE, { N5, N5 }, SCUA8, 14 },2513 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N5, N5, SCUA8, 14),
2514 { PIN_CONFIG_BIAS_PULL_DOWN, { N4, N4 }, SCUA8, 15 },2514 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15),
2515 { PIN_CONFIG_BIAS_DISABLE, { N4, N4 }, SCUA8, 15 },2515 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15),
2516 { PIN_CONFIG_BIAS_PULL_DOWN, { N3, N3 }, SCUA8, 16 },2516 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N3, N3, SCUA8, 16),
2517 { PIN_CONFIG_BIAS_DISABLE, { N3, N3 }, SCUA8, 16 },2517 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N3, N3, SCUA8, 16),
2518 { PIN_CONFIG_BIAS_PULL_DOWN, { N2, N2 }, SCUA8, 17 },2518 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17),
2519 { PIN_CONFIG_BIAS_DISABLE, { N2, N2 }, SCUA8, 17 },2519 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17),
2520 { PIN_CONFIG_BIAS_PULL_DOWN, { N1, N1 }, SCUA8, 18 },2520 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18),
2521 { PIN_CONFIG_BIAS_DISABLE, { N1, N1 }, SCUA8, 18 },2521 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18),
2522 { PIN_CONFIG_BIAS_PULL_DOWN, { P5, P5 }, SCUA8, 19 },2522 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, P5, P5, SCUA8, 19),
2523 { PIN_CONFIG_BIAS_DISABLE, { P5, P5 }, SCUA8, 19 },2523 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, P5, P5, SCUA8, 19),
2524 2524
2525 /*2525 /*
2526 * Debounce settings for GPIOs D and E passthrough mode are in2526 * Debounce settings for GPIOs D and E passthrough mode are in
@@ -2531,14 +2531,14 @@ static const struct aspeed_pin_config aspeed_g4_configs[] = { · 4 unmodified lines
2531 * controller. Due to this tangle between GPIO and pinctrl we don't yet2531 * controller. Due to this tangle between GPIO and pinctrl we don't yet
2532 * fully support pass-through debounce.2532 * fully support pass-through debounce.
2533 */2533 */
2534 { PIN_CONFIG_INPUT_DEBOUNCE, { A18, D16 }, SCUA8, 20 },2534 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A18, D16, SCUA8, 20),
2535 { PIN_CONFIG_INPUT_DEBOUNCE, { B17, A17 }, SCUA8, 21 },2535 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B17, A17, SCUA8, 21),
2536 { PIN_CONFIG_INPUT_DEBOUNCE, { C16, B16 }, SCUA8, 22 },2536 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C16, B16, SCUA8, 22),
2537 { PIN_CONFIG_INPUT_DEBOUNCE, { A16, E15 }, SCUA8, 23 },2537 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A16, E15, SCUA8, 23),
2538 { PIN_CONFIG_INPUT_DEBOUNCE, { D15, C15 }, SCUA8, 24 },2538 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24),
2539 { PIN_CONFIG_INPUT_DEBOUNCE, { B15, A15 }, SCUA8, 25 },2539 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25),
2540 { PIN_CONFIG_INPUT_DEBOUNCE, { E14, D14 }, SCUA8, 26 },2540 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E14, D14, SCUA8, 26),
2541 { PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 },2541 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C14, B14, SCUA8, 27),
2542};2542};
2543 2543
2544static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,2544static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
@@ -2594,6 +2594,14 @@ static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, · 49 unmodified lines
2594 return 0;2594 return 0;
2595}2595}
2596 2596
2597static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = {
2598 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
2599 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2600 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2601 { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
2602 { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
2603};
2604
2597static const struct aspeed_pinmux_ops aspeed_g4_ops = {2605static const struct aspeed_pinmux_ops aspeed_g4_ops = {
2598 .set = aspeed_g4_sig_expr_set,2606 .set = aspeed_g4_sig_expr_set,
2599};2607};
@@ -2610,6 +2618,8 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { · 10 unmodified lines
2610 },2618 },
2611 .configs = aspeed_g4_configs,2619 .configs = aspeed_g4_configs,
2612 .nconfigs = ARRAY_SIZE(aspeed_g4_configs),2620 .nconfigs = ARRAY_SIZE(aspeed_g4_configs),
2621 .confmaps = aspeed_g4_pin_config_map,
2622 .nconfmaps = ARRAY_SIZE(aspeed_g4_pin_config_map),
2613};2623};
2614 2624
2615static const struct pinmux_ops aspeed_g4_pinmux_ops = {2625static const struct pinmux_ops aspeed_g4_pinmux_ops = {
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c+111−101
@@ -2476,124 +2476,124 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { · 2475 unmodified lines
2476 2476
2477static struct aspeed_pin_config aspeed_g5_configs[] = {2477static struct aspeed_pin_config aspeed_g5_configs[] = {
2478 /* GPIOA, GPIOQ */2478 /* GPIOA, GPIOQ */
2479 { PIN_CONFIG_BIAS_PULL_DOWN, { B14, B13 }, SCU8C, 16 },2479 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B14, B13, SCU8C, 16),
2480 { PIN_CONFIG_BIAS_DISABLE, { B14, B13 }, SCU8C, 16 },2480 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B14, B13, SCU8C, 16),
2481 { PIN_CONFIG_BIAS_PULL_DOWN, { A11, N20 }, SCU8C, 16 },2481 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A11, N20, SCU8C, 16),
2482 { PIN_CONFIG_BIAS_DISABLE, { A11, N20 }, SCU8C, 16 },2482 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A11, N20, SCU8C, 16),
2483 2483
2484 /* GPIOB, GPIOR */2484 /* GPIOB, GPIOR */
2485 { PIN_CONFIG_BIAS_PULL_DOWN, { K19, H20 }, SCU8C, 17 },2485 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, K19, H20, SCU8C, 17),
2486 { PIN_CONFIG_BIAS_DISABLE, { K19, H20 }, SCU8C, 17 },2486 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, K19, H20, SCU8C, 17),
2487 { PIN_CONFIG_BIAS_PULL_DOWN, { AA19, E10 }, SCU8C, 17 },2487 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17),
2488 { PIN_CONFIG_BIAS_DISABLE, { AA19, E10 }, SCU8C, 17 },2488 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17),
2489 2489
2490 /* GPIOC, GPIOS*/2490 /* GPIOC, GPIOS*/
2491 { PIN_CONFIG_BIAS_PULL_DOWN, { C12, B11 }, SCU8C, 18 },2491 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18),
2492 { PIN_CONFIG_BIAS_DISABLE, { C12, B11 }, SCU8C, 18 },2492 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18),
2493 { PIN_CONFIG_BIAS_PULL_DOWN, { V20, AA20 }, SCU8C, 18 },2493 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, AA20, SCU8C, 18),
2494 { PIN_CONFIG_BIAS_DISABLE, { V20, AA20 }, SCU8C, 18 },2494 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, AA20, SCU8C, 18),
2495 2495
2496 /* GPIOD, GPIOY */2496 /* GPIOD, GPIOY */
2497 { PIN_CONFIG_BIAS_PULL_DOWN, { F19, C21 }, SCU8C, 19 },2497 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F19, C21, SCU8C, 19),
2498 { PIN_CONFIG_BIAS_DISABLE, { F19, C21 }, SCU8C, 19 },2498 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F19, C21, SCU8C, 19),
2499 { PIN_CONFIG_BIAS_PULL_DOWN, { R22, P20 }, SCU8C, 19 },2499 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R22, P20, SCU8C, 19),
2500 { PIN_CONFIG_BIAS_DISABLE, { R22, P20 }, SCU8C, 19 },2500 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R22, P20, SCU8C, 19),
2501 2501
2502 /* GPIOE, GPIOZ */2502 /* GPIOE, GPIOZ */
2503 { PIN_CONFIG_BIAS_PULL_DOWN, { B20, B19 }, SCU8C, 20 },2503 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B20, B19, SCU8C, 20),
2504 { PIN_CONFIG_BIAS_DISABLE, { B20, B19 }, SCU8C, 20 },2504 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B20, B19, SCU8C, 20),
2505 { PIN_CONFIG_BIAS_PULL_DOWN, { Y20, W21 }, SCU8C, 20 },2505 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y20, W21, SCU8C, 20),
2506 { PIN_CONFIG_BIAS_DISABLE, { Y20, W21 }, SCU8C, 20 },2506 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y20, W21, SCU8C, 20),
2507 2507
2508 /* GPIOF, GPIOAA */2508 /* GPIOF, GPIOAA */
2509 { PIN_CONFIG_BIAS_PULL_DOWN, { J19, H18 }, SCU8C, 21 },2509 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J19, H18, SCU8C, 21),
2510 { PIN_CONFIG_BIAS_DISABLE, { J19, H18 }, SCU8C, 21 },2510 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J19, H18, SCU8C, 21),
2511 { PIN_CONFIG_BIAS_PULL_DOWN, { Y21, P19 }, SCU8C, 21 },2511 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y21, P19, SCU8C, 21),
2512 { PIN_CONFIG_BIAS_DISABLE, { Y21, P19 }, SCU8C, 21 },2512 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y21, P19, SCU8C, 21),
2513 2513
2514 /* GPIOG, GPIOAB */2514 /* GPIOG, GPIOAB */
2515 { PIN_CONFIG_BIAS_PULL_DOWN, { A19, E14 }, SCU8C, 22 },2515 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A19, E14, SCU8C, 22),
2516 { PIN_CONFIG_BIAS_DISABLE, { A19, E14 }, SCU8C, 22 },2516 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A19, E14, SCU8C, 22),
2517 { PIN_CONFIG_BIAS_PULL_DOWN, { N19, R20 }, SCU8C, 22 },2517 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N19, R20, SCU8C, 22),
2518 { PIN_CONFIG_BIAS_DISABLE, { N19, R20 }, SCU8C, 22 },2518 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N19, R20, SCU8C, 22),
2519 2519
2520 /* GPIOH, GPIOAC */2520 /* GPIOH, GPIOAC */
2521 { PIN_CONFIG_BIAS_PULL_DOWN, { A18, D18 }, SCU8C, 23 },2521 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, D18, SCU8C, 23),
2522 { PIN_CONFIG_BIAS_DISABLE, { A18, D18 }, SCU8C, 23 },2522 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, D18, SCU8C, 23),
2523 { PIN_CONFIG_BIAS_PULL_DOWN, { G21, G22 }, SCU8C, 23 },2523 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G21, G22, SCU8C, 23),
2524 { PIN_CONFIG_BIAS_DISABLE, { G21, G22 }, SCU8C, 23 },2524 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G21, G22, SCU8C, 23),
2525 2525
2526 /* GPIOs [I, P] */2526 /* GPIOs [I, P] */
2527 { PIN_CONFIG_BIAS_PULL_DOWN, { C18, A15 }, SCU8C, 24 },2527 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24),
2528 { PIN_CONFIG_BIAS_DISABLE, { C18, A15 }, SCU8C, 24 },2528 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C18, A15, SCU8C, 24),
2529 { PIN_CONFIG_BIAS_PULL_DOWN, { R2, T3 }, SCU8C, 25 },2529 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R2, T3, SCU8C, 25),
2530 { PIN_CONFIG_BIAS_DISABLE, { R2, T3 }, SCU8C, 25 },2530 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R2, T3, SCU8C, 25),
2531 { PIN_CONFIG_BIAS_PULL_DOWN, { L3, R1 }, SCU8C, 26 },2531 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, R1, SCU8C, 26),
2532 { PIN_CONFIG_BIAS_DISABLE, { L3, R1 }, SCU8C, 26 },2532 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, R1, SCU8C, 26),
2533 { PIN_CONFIG_BIAS_PULL_DOWN, { T2, W1 }, SCU8C, 27 },2533 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, T2, W1, SCU8C, 27),
2534 { PIN_CONFIG_BIAS_DISABLE, { T2, W1 }, SCU8C, 27 },2534 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, T2, W1, SCU8C, 27),
2535 { PIN_CONFIG_BIAS_PULL_DOWN, { Y1, T5 }, SCU8C, 28 },2535 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28),
2536 { PIN_CONFIG_BIAS_DISABLE, { Y1, T5 }, SCU8C, 28 },2536 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28),
2537 { PIN_CONFIG_BIAS_PULL_DOWN, { V2, T4 }, SCU8C, 29 },2537 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29),
2538 { PIN_CONFIG_BIAS_DISABLE, { V2, T4 }, SCU8C, 29 },2538 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29),
2539 { PIN_CONFIG_BIAS_PULL_DOWN, { U5, W4 }, SCU8C, 30 },2539 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U5, W4, SCU8C, 30),
2540 { PIN_CONFIG_BIAS_DISABLE, { U5, W4 }, SCU8C, 30 },2540 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U5, W4, SCU8C, 30),
2541 { PIN_CONFIG_BIAS_PULL_DOWN, { V4, V6 }, SCU8C, 31 },2541 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V4, V6, SCU8C, 31),
2542 { PIN_CONFIG_BIAS_DISABLE, { V4, V6 }, SCU8C, 31 },2542 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V4, V6, SCU8C, 31),
2543 2543
2544 /* GPIOs T[0-5] (RGMII1 Tx pins) */2544 /* GPIOs T[0-5] (RGMII1 Tx pins) */
2545 { PIN_CONFIG_DRIVE_STRENGTH, { B5, B5 }, SCU90, 8 },2545 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B5, B5, SCU90, 8),
2546 { PIN_CONFIG_DRIVE_STRENGTH, { E9, A5 }, SCU90, 9 },2546 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, E9, A5, SCU90, 9),
2547 { PIN_CONFIG_BIAS_PULL_DOWN, { B5, D7 }, SCU90, 12 },2547 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B5, D7, SCU90, 12),
2548 { PIN_CONFIG_BIAS_DISABLE, { B5, D7 }, SCU90, 12 },2548 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B5, D7, SCU90, 12),
2549 2549
2550 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */2550 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
2551 { PIN_CONFIG_DRIVE_STRENGTH, { B2, B2 }, SCU90, 10 },2551 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10),
2552 { PIN_CONFIG_DRIVE_STRENGTH, { B1, B3 }, SCU90, 11 },2552 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B1, B3, SCU90, 11),
2553 { PIN_CONFIG_BIAS_PULL_DOWN, { B2, D4 }, SCU90, 14 },2553 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14),
2554 { PIN_CONFIG_BIAS_DISABLE, { B2, D4 }, SCU90, 14 },2554 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14),
2555 2555
2556 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */2556 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2557 { PIN_CONFIG_BIAS_PULL_DOWN, { B4, C4 }, SCU90, 13 },2557 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13),
2558 { PIN_CONFIG_BIAS_DISABLE, { B4, C4 }, SCU90, 13 },2558 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13),
2559 2559
2560 /* GPIOs V[2-7] (RGMII2 Rx pins) */2560 /* GPIOs V[2-7] (RGMII2 Rx pins) */
2561 { PIN_CONFIG_BIAS_PULL_DOWN, { C2, E6 }, SCU90, 15 },2561 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15),
2562 { PIN_CONFIG_BIAS_DISABLE, { C2, E6 }, SCU90, 15 },2562 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15),
2563 2563
2564 /* ADC pull-downs (SCUA8[19:4]) */2564 /* ADC pull-downs (SCUA8[19:4]) */
2565 { PIN_CONFIG_BIAS_PULL_DOWN, { F4, F4 }, SCUA8, 4 },2565 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4),
2566 { PIN_CONFIG_BIAS_DISABLE, { F4, F4 }, SCUA8, 4 },2566 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4),
2567 { PIN_CONFIG_BIAS_PULL_DOWN, { F5, F5 }, SCUA8, 5 },2567 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F5, F5, SCUA8, 5),
2568 { PIN_CONFIG_BIAS_DISABLE, { F5, F5 }, SCUA8, 5 },2568 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F5, F5, SCUA8, 5),
2569 { PIN_CONFIG_BIAS_PULL_DOWN, { E2, E2 }, SCUA8, 6 },2569 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E2, E2, SCUA8, 6),
2570 { PIN_CONFIG_BIAS_DISABLE, { E2, E2 }, SCUA8, 6 },2570 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E2, E2, SCUA8, 6),
2571 { PIN_CONFIG_BIAS_PULL_DOWN, { E1, E1 }, SCUA8, 7 },2571 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA8, 7),
2572 { PIN_CONFIG_BIAS_DISABLE, { E1, E1 }, SCUA8, 7 },2572 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E1, E1, SCUA8, 7),
2573 { PIN_CONFIG_BIAS_PULL_DOWN, { F3, F3 }, SCUA8, 8 },2573 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8),
2574 { PIN_CONFIG_BIAS_DISABLE, { F3, F3 }, SCUA8, 8 },2574 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8),
2575 { PIN_CONFIG_BIAS_PULL_DOWN, { E3, E3 }, SCUA8, 9 },2575 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA8, 9),
2576 { PIN_CONFIG_BIAS_DISABLE, { E3, E3 }, SCUA8, 9 },2576 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E3, E3, SCUA8, 9),
2577 { PIN_CONFIG_BIAS_PULL_DOWN, { G5, G5 }, SCUA8, 10 },2577 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G5, G5, SCUA8, 10),
2578 { PIN_CONFIG_BIAS_DISABLE, { G5, G5 }, SCUA8, 10 },2578 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G5, G5, SCUA8, 10),
2579 { PIN_CONFIG_BIAS_PULL_DOWN, { G4, G4 }, SCUA8, 11 },2579 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G4, G4, SCUA8, 11),
2580 { PIN_CONFIG_BIAS_DISABLE, { G4, G4 }, SCUA8, 11 },2580 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G4, G4, SCUA8, 11),
2581 { PIN_CONFIG_BIAS_PULL_DOWN, { F2, F2 }, SCUA8, 12 },2581 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F2, F2, SCUA8, 12),
2582 { PIN_CONFIG_BIAS_DISABLE, { F2, F2 }, SCUA8, 12 },2582 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F2, F2, SCUA8, 12),
2583 { PIN_CONFIG_BIAS_PULL_DOWN, { G3, G3 }, SCUA8, 13 },2583 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13),
2584 { PIN_CONFIG_BIAS_DISABLE, { G3, G3 }, SCUA8, 13 },2584 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13),
2585 { PIN_CONFIG_BIAS_PULL_DOWN, { G2, G2 }, SCUA8, 14 },2585 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G2, G2, SCUA8, 14),
2586 { PIN_CONFIG_BIAS_DISABLE, { G2, G2 }, SCUA8, 14 },2586 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G2, G2, SCUA8, 14),
2587 { PIN_CONFIG_BIAS_PULL_DOWN, { F1, F1 }, SCUA8, 15 },2587 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F1, F1, SCUA8, 15),
2588 { PIN_CONFIG_BIAS_DISABLE, { F1, F1 }, SCUA8, 15 },2588 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F1, F1, SCUA8, 15),
2589 { PIN_CONFIG_BIAS_PULL_DOWN, { H5, H5 }, SCUA8, 16 },2589 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H5, H5, SCUA8, 16),
2590 { PIN_CONFIG_BIAS_DISABLE, { H5, H5 }, SCUA8, 16 },2590 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H5, H5, SCUA8, 16),
2591 { PIN_CONFIG_BIAS_PULL_DOWN, { G1, G1 }, SCUA8, 17 },2591 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G1, G1, SCUA8, 17),
2592 { PIN_CONFIG_BIAS_DISABLE, { G1, G1 }, SCUA8, 17 },2592 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G1, G1, SCUA8, 17),
2593 { PIN_CONFIG_BIAS_PULL_DOWN, { H3, H3 }, SCUA8, 18 },2593 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H3, H3, SCUA8, 18),
2594 { PIN_CONFIG_BIAS_DISABLE, { H3, H3 }, SCUA8, 18 },2594 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H3, H3, SCUA8, 18),
2595 { PIN_CONFIG_BIAS_PULL_DOWN, { H4, H4 }, SCUA8, 19 },2595 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H4, H4, SCUA8, 19),
2596 { PIN_CONFIG_BIAS_DISABLE, { H4, H4 }, SCUA8, 19 },2596 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H4, H4, SCUA8, 19),
2597 2597
2598 /*2598 /*
2599 * Debounce settings for GPIOs D and E passthrough mode are in2599 * Debounce settings for GPIOs D and E passthrough mode are in
@@ -2604,14 +2604,14 @@ static struct aspeed_pin_config aspeed_g5_configs[] = { · 4 unmodified lines
2604 * controller. Due to this tangle between GPIO and pinctrl we don't yet2604 * controller. Due to this tangle between GPIO and pinctrl we don't yet
2605 * fully support pass-through debounce.2605 * fully support pass-through debounce.
2606 */2606 */
2607 { PIN_CONFIG_INPUT_DEBOUNCE, { F19, E21 }, SCUA8, 20 },2607 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F19, E21, SCUA8, 20),
2608 { PIN_CONFIG_INPUT_DEBOUNCE, { F20, D20 }, SCUA8, 21 },2608 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F20, D20, SCUA8, 21),
2609 { PIN_CONFIG_INPUT_DEBOUNCE, { D21, E20 }, SCUA8, 22 },2609 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D21, E20, SCUA8, 22),
2610 { PIN_CONFIG_INPUT_DEBOUNCE, { G18, C21 }, SCUA8, 23 },2610 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, G18, C21, SCUA8, 23),
2611 { PIN_CONFIG_INPUT_DEBOUNCE, { B20, C20 }, SCUA8, 24 },2611 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B20, C20, SCUA8, 24),
2612 { PIN_CONFIG_INPUT_DEBOUNCE, { F18, F17 }, SCUA8, 25 },2612 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F18, F17, SCUA8, 25),
2613 { PIN_CONFIG_INPUT_DEBOUNCE, { E18, D19 }, SCUA8, 26 },2613 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E18, D19, SCUA8, 26),
2614 { PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 },2614 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A20, B19, SCUA8, 27),
2615};2615};
2616 2616
2617static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,2617static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
@@ -2780,6 +2780,14 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx, · 162 unmodified lines
2780 return 0;2780 return 0;
2781}2781}
2782 2782
2783static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = {
2784 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
2785 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2786 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2787 { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
2788 { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
2789};
2790
2783static const struct aspeed_pinmux_ops aspeed_g5_ops = {2791static const struct aspeed_pinmux_ops aspeed_g5_ops = {
2784 .eval = aspeed_g5_sig_expr_eval,2792 .eval = aspeed_g5_sig_expr_eval,
2785 .set = aspeed_g5_sig_expr_set,2793 .set = aspeed_g5_sig_expr_set,
@@ -2797,6 +2805,8 @@ static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { · 11 unmodified lines
2797 },2805 },
2798 .configs = aspeed_g5_configs,2806 .configs = aspeed_g5_configs,
2799 .nconfigs = ARRAY_SIZE(aspeed_g5_configs),2807 .nconfigs = ARRAY_SIZE(aspeed_g5_configs),
2808 .confmaps = aspeed_g5_pin_config_map,
2809 .nconfmaps = ARRAY_SIZE(aspeed_g5_pin_config_map),
2800};2810};
2801 2811
2802static const struct pinmux_ops aspeed_g5_pinmux_ops = {2812static const struct pinmux_ops aspeed_g5_pinmux_ops = {
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c+386−1
@@ -26,7 +26,10 @@ · 25 unmodified lines
26#define SCU430 0x430 /* Multi-function Pin Control #8 */26#define SCU430 0x430 /* Multi-function Pin Control #8 */
27#define SCU434 0x434 /* Multi-function Pin Control #9 */27#define SCU434 0x434 /* Multi-function Pin Control #9 */
28#define SCU438 0x438 /* Multi-function Pin Control #10 */28#define SCU438 0x438 /* Multi-function Pin Control #10 */
29#define SCU440 0x440 /* USB Multi-function Pin Control #12 */
29#define SCU450 0x450 /* Multi-function Pin Control #14 */30#define SCU450 0x450 /* Multi-function Pin Control #14 */
31#define SCU454 0x454 /* Multi-function Pin Control #15 */
32#define SCU458 0x458 /* Multi-function Pin Control #16 */
30#define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */33#define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */
31#define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */34#define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */
32#define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */35#define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */
@@ -35,9 +38,17 @@ · 2 unmodified lines
35#define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */38#define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */
36#define SCU500 0x500 /* Hardware Strap 1 */39#define SCU500 0x500 /* Hardware Strap 1 */
37#define SCU510 0x510 /* Hardware Strap 2 */40#define SCU510 0x510 /* Hardware Strap 2 */
41#define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */
42#define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
43#define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */
44#define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */
45#define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */
46#define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */
47#define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */
38#define SCU694 0x694 /* Multi-function Pin Control #25 */48#define SCU694 0x694 /* Multi-function Pin Control #25 */
49#define SCUC20 0xC20 /* PCIE configuration Setting Control */
39 50
40#define ASPEED_G6_NR_PINS 24851#define ASPEED_G6_NR_PINS 256
41 52
42#define M24 053#define M24 0
43SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0));54SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0));
@@ -1534,6 +1545,78 @@ GROUP_DECL(I3C4, AE25, AF24); · 1490 unmodified lines
1534FUNC_DECL_2(I3C4, HVI3C4, I3C4);1545FUNC_DECL_2(I3C4, HVI3C4, I3C4);
1535FUNC_GROUP_DECL(FSI2, AE25, AF24);1546FUNC_GROUP_DECL(FSI2, AE25, AF24);
1536 1547
1548#define AF23 248
1549SIG_EXPR_LIST_DECL_SESG(AF23, I3C1SCL, I3C1, SIG_DESC_SET(SCU438, 16));
1550PIN_DECL_(AF23, SIG_EXPR_LIST_PTR(AF23, I3C1SCL));
1551
1552#define AE24 249
1553SIG_EXPR_LIST_DECL_SESG(AE24, I3C1SDA, I3C1, SIG_DESC_SET(SCU438, 17));
1554PIN_DECL_(AE24, SIG_EXPR_LIST_PTR(AE24, I3C1SDA));
1555
1556FUNC_GROUP_DECL(I3C1, AF23, AE24);
1557
1558#define AF22 250
1559SIG_EXPR_LIST_DECL_SESG(AF22, I3C2SCL, I3C2, SIG_DESC_SET(SCU438, 18));
1560PIN_DECL_(AF22, SIG_EXPR_LIST_PTR(AF22, I3C2SCL));
1561
1562#define AE22 251
1563SIG_EXPR_LIST_DECL_SESG(AE22, I3C2SDA, I3C2, SIG_DESC_SET(SCU438, 19));
1564PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA));
1565
1566FUNC_GROUP_DECL(I3C2, AF22, AE22);
1567
1568#define USB2ADP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 0, 0 }
1569#define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 }
1570#define USB2AH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 2, 0 }
1571#define USB2AHP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 3, 0 }
1572#define USB11BHID_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 0, 0 }
1573#define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 }
1574#define USB2BH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 2, 0 }
1575
1576#define A4 252
1577SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC,
1578 SIG_DESC_SET(SCUC20, 16));
1579SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC);
1580SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC);
1581SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC);
1582PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP),
1583 SIG_EXPR_LIST_PTR(A4, USB2AHDP));
1584
1585#define B4 253
1586SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC);
1587SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC);
1588SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC);
1589SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC);
1590PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN),
1591 SIG_EXPR_LIST_PTR(B4, USB2AHDN));
1592
1593GROUP_DECL(USBA, A4, B4);
1594
1595FUNC_DECL_1(USB2ADP, USBA);
1596FUNC_DECL_1(USB2AD, USBA);
1597FUNC_DECL_1(USB2AH, USBA);
1598FUNC_DECL_1(USB2AHP, USBA);
1599
1600#define A6 254
1601SIG_EXPR_LIST_DECL_SEMG(A6, USB11BDP, USBB, USB11BHID, USB11BHID_DESC);
1602SIG_EXPR_LIST_DECL_SEMG(A6, USB2BDDP, USBB, USB2BD, USB2BD_DESC);
1603SIG_EXPR_LIST_DECL_SEMG(A6, USB2BHDP, USBB, USB2BH, USB2BH_DESC);
1604PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDP), SIG_EXPR_LIST_PTR(A6, USB2BDDP),
1605 SIG_EXPR_LIST_PTR(A6, USB2BHDP));
1606
1607#define B6 255
1608SIG_EXPR_LIST_DECL_SEMG(B6, USB11BDN, USBB, USB11BHID, USB11BHID_DESC);
1609SIG_EXPR_LIST_DECL_SEMG(B6, USB2BDDN, USBB, USB2BD, USB2BD_DESC);
1610SIG_EXPR_LIST_DECL_SEMG(B6, USB2BHDN, USBB, USB2BH, USB2BH_DESC);
1611PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDN), SIG_EXPR_LIST_PTR(B6, USB2BDDN),
1612 SIG_EXPR_LIST_PTR(B6, USB2BHDN));
1613
1614GROUP_DECL(USBB, A6, B6);
1615
1616FUNC_DECL_1(USB11BHID, USBB);
1617FUNC_DECL_1(USB2BD, USBB);
1618FUNC_DECL_1(USB2BH, USBB);
1619
1537/* Pins, groups and functions are sort(1):ed alphabetically for sanity */1620/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
1538 1621
1539static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {1622static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
@@ -1554,6 +1637,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { · 14 unmodified lines
1554 ASPEED_PINCTRL_PIN(A24),1637 ASPEED_PINCTRL_PIN(A24),
1555 ASPEED_PINCTRL_PIN(A25),1638 ASPEED_PINCTRL_PIN(A25),
1556 ASPEED_PINCTRL_PIN(A3),1639 ASPEED_PINCTRL_PIN(A3),
1640 ASPEED_PINCTRL_PIN(A4),
1641 ASPEED_PINCTRL_PIN(A6),
1557 ASPEED_PINCTRL_PIN(AA11),1642 ASPEED_PINCTRL_PIN(AA11),
1558 ASPEED_PINCTRL_PIN(AA12),1643 ASPEED_PINCTRL_PIN(AA12),
1559 ASPEED_PINCTRL_PIN(AA16),1644 ASPEED_PINCTRL_PIN(AA16),
@@ -1625,6 +1710,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { · 65 unmodified lines
1625 ASPEED_PINCTRL_PIN(AE16),1710 ASPEED_PINCTRL_PIN(AE16),
1626 ASPEED_PINCTRL_PIN(AE18),1711 ASPEED_PINCTRL_PIN(AE18),
1627 ASPEED_PINCTRL_PIN(AE19),1712 ASPEED_PINCTRL_PIN(AE19),
1713 ASPEED_PINCTRL_PIN(AE22),
1714 ASPEED_PINCTRL_PIN(AE24),
1628 ASPEED_PINCTRL_PIN(AE25),1715 ASPEED_PINCTRL_PIN(AE25),
1629 ASPEED_PINCTRL_PIN(AE26),1716 ASPEED_PINCTRL_PIN(AE26),
1630 ASPEED_PINCTRL_PIN(AE7),1717 ASPEED_PINCTRL_PIN(AE7),
@@ -1634,6 +1721,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { · 3 unmodified lines
1634 ASPEED_PINCTRL_PIN(AF12),1721 ASPEED_PINCTRL_PIN(AF12),
1635 ASPEED_PINCTRL_PIN(AF14),1722 ASPEED_PINCTRL_PIN(AF14),
1636 ASPEED_PINCTRL_PIN(AF15),1723 ASPEED_PINCTRL_PIN(AF15),
1724 ASPEED_PINCTRL_PIN(AF22),
1725 ASPEED_PINCTRL_PIN(AF23),
1637 ASPEED_PINCTRL_PIN(AF24),1726 ASPEED_PINCTRL_PIN(AF24),
1638 ASPEED_PINCTRL_PIN(AF25),1727 ASPEED_PINCTRL_PIN(AF25),
1639 ASPEED_PINCTRL_PIN(AF7),1728 ASPEED_PINCTRL_PIN(AF7),
@@ -1654,6 +1743,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { · 14 unmodified lines
1654 ASPEED_PINCTRL_PIN(B25),1743 ASPEED_PINCTRL_PIN(B25),
1655 ASPEED_PINCTRL_PIN(B26),1744 ASPEED_PINCTRL_PIN(B26),
1656 ASPEED_PINCTRL_PIN(B3),1745 ASPEED_PINCTRL_PIN(B3),
1746 ASPEED_PINCTRL_PIN(B4),
1747 ASPEED_PINCTRL_PIN(B6),
1657 ASPEED_PINCTRL_PIN(C1),1748 ASPEED_PINCTRL_PIN(C1),
1658 ASPEED_PINCTRL_PIN(C11),1749 ASPEED_PINCTRL_PIN(C11),
1659 ASPEED_PINCTRL_PIN(C12),1750 ASPEED_PINCTRL_PIN(C12),
@@ -1847,6 +1938,8 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { · 187 unmodified lines
1847 ASPEED_PINCTRL_GROUP(I2C7),1938 ASPEED_PINCTRL_GROUP(I2C7),
1848 ASPEED_PINCTRL_GROUP(I2C8),1939 ASPEED_PINCTRL_GROUP(I2C8),
1849 ASPEED_PINCTRL_GROUP(I2C9),1940 ASPEED_PINCTRL_GROUP(I2C9),
1941 ASPEED_PINCTRL_GROUP(I3C1),
1942 ASPEED_PINCTRL_GROUP(I3C2),
1850 ASPEED_PINCTRL_GROUP(I3C3),1943 ASPEED_PINCTRL_GROUP(I3C3),
1851 ASPEED_PINCTRL_GROUP(I3C4),1944 ASPEED_PINCTRL_GROUP(I3C4),
1852 ASPEED_PINCTRL_GROUP(I3C5),1945 ASPEED_PINCTRL_GROUP(I3C5),
@@ -2012,6 +2105,8 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { · 159 unmodified lines
2012 ASPEED_PINCTRL_GROUP(UART7),2105 ASPEED_PINCTRL_GROUP(UART7),
2013 ASPEED_PINCTRL_GROUP(UART8),2106 ASPEED_PINCTRL_GROUP(UART8),
2014 ASPEED_PINCTRL_GROUP(UART9),2107 ASPEED_PINCTRL_GROUP(UART9),
2108 ASPEED_PINCTRL_GROUP(USBA),
2109 ASPEED_PINCTRL_GROUP(USBB),
2015 ASPEED_PINCTRL_GROUP(VB),2110 ASPEED_PINCTRL_GROUP(VB),
2016 ASPEED_PINCTRL_GROUP(VGAHS),2111 ASPEED_PINCTRL_GROUP(VGAHS),
2017 ASPEED_PINCTRL_GROUP(VGAVS),2112 ASPEED_PINCTRL_GROUP(VGAVS),
@@ -2079,6 +2174,8 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { · 61 unmodified lines
2079 ASPEED_PINCTRL_FUNC(I2C7),2174 ASPEED_PINCTRL_FUNC(I2C7),
2080 ASPEED_PINCTRL_FUNC(I2C8),2175 ASPEED_PINCTRL_FUNC(I2C8),
2081 ASPEED_PINCTRL_FUNC(I2C9),2176 ASPEED_PINCTRL_FUNC(I2C9),
2177 ASPEED_PINCTRL_FUNC(I3C1),
2178 ASPEED_PINCTRL_FUNC(I3C2),
2082 ASPEED_PINCTRL_FUNC(I3C3),2179 ASPEED_PINCTRL_FUNC(I3C3),
2083 ASPEED_PINCTRL_FUNC(I3C4),2180 ASPEED_PINCTRL_FUNC(I3C4),
2084 ASPEED_PINCTRL_FUNC(I3C5),2181 ASPEED_PINCTRL_FUNC(I3C5),
@@ -2221,6 +2318,13 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { · 136 unmodified lines
2221 ASPEED_PINCTRL_FUNC(UART7),2318 ASPEED_PINCTRL_FUNC(UART7),
2222 ASPEED_PINCTRL_FUNC(UART8),2319 ASPEED_PINCTRL_FUNC(UART8),
2223 ASPEED_PINCTRL_FUNC(UART9),2320 ASPEED_PINCTRL_FUNC(UART9),
2321 ASPEED_PINCTRL_FUNC(USB11BHID),
2322 ASPEED_PINCTRL_FUNC(USB2AD),
2323 ASPEED_PINCTRL_FUNC(USB2ADP),
2324 ASPEED_PINCTRL_FUNC(USB2AH),
2325 ASPEED_PINCTRL_FUNC(USB2AHP),
2326 ASPEED_PINCTRL_FUNC(USB2BD),
2327 ASPEED_PINCTRL_FUNC(USB2BH),
2224 ASPEED_PINCTRL_FUNC(VB),2328 ASPEED_PINCTRL_FUNC(VB),
2225 ASPEED_PINCTRL_FUNC(VGAHS),2329 ASPEED_PINCTRL_FUNC(VGAHS),
2226 ASPEED_PINCTRL_FUNC(VGAVS),2330 ASPEED_PINCTRL_FUNC(VGAVS),
@@ -2230,6 +2334,260 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { · 3 unmodified lines
2230 ASPEED_PINCTRL_FUNC(WDTRST4),2334 ASPEED_PINCTRL_FUNC(WDTRST4),
2231};2335};
2232 2336
2337static struct aspeed_pin_config aspeed_g6_configs[] = {
2338 /* GPIOB7 */
2339 ASPEED_PULL_DOWN_PINCONF(J24, SCU610, 15),
2340 /* GPIOB6 */
2341 ASPEED_PULL_DOWN_PINCONF(H25, SCU610, 14),
2342 /* GPIOB5 */
2343 ASPEED_PULL_DOWN_PINCONF(G26, SCU610, 13),
2344 /* GPIOB4 */
2345 ASPEED_PULL_DOWN_PINCONF(J23, SCU610, 12),
2346 /* GPIOB3 */
2347 ASPEED_PULL_DOWN_PINCONF(J25, SCU610, 11),
2348 /* GPIOB2 */
2349 ASPEED_PULL_DOWN_PINCONF(H26, SCU610, 10),
2350 /* GPIOB1 */
2351 ASPEED_PULL_DOWN_PINCONF(K23, SCU610, 9),
2352 /* GPIOB0 */
2353 ASPEED_PULL_DOWN_PINCONF(J26, SCU610, 8),
2354
2355 /* GPIOH3 */
2356 ASPEED_PULL_DOWN_PINCONF(A17, SCU614, 27),
2357 /* GPIOH2 */
2358 ASPEED_PULL_DOWN_PINCONF(C18, SCU614, 26),
2359 /* GPIOH1 */
2360 ASPEED_PULL_DOWN_PINCONF(B18, SCU614, 25),
2361 /* GPIOH0 */
2362 ASPEED_PULL_DOWN_PINCONF(A18, SCU614, 24),
2363
2364 /* GPIOL7 */
2365 ASPEED_PULL_DOWN_PINCONF(C14, SCU618, 31),
2366 /* GPIOL6 */
2367 ASPEED_PULL_DOWN_PINCONF(B14, SCU618, 30),
2368 /* GPIOL5 */
2369 ASPEED_PULL_DOWN_PINCONF(F15, SCU618, 29),
2370 /* GPIOL4 */
2371 ASPEED_PULL_DOWN_PINCONF(C15, SCU618, 28),
2372
2373 /* GPIOJ7 */
2374 ASPEED_PULL_UP_PINCONF(D19, SCU618, 15),
2375 /* GPIOJ6 */
2376 ASPEED_PULL_UP_PINCONF(C20, SCU618, 14),
2377 /* GPIOJ5 */
2378 ASPEED_PULL_UP_PINCONF(A19, SCU618, 13),
2379 /* GPIOJ4 */
2380 ASPEED_PULL_UP_PINCONF(C19, SCU618, 12),
2381 /* GPIOJ3 */
2382 ASPEED_PULL_UP_PINCONF(D20, SCU618, 11),
2383 /* GPIOJ2 */
2384 ASPEED_PULL_UP_PINCONF(E19, SCU618, 10),
2385 /* GPIOJ1 */
2386 ASPEED_PULL_UP_PINCONF(A20, SCU618, 9),
2387 /* GPIOJ0 */
2388 ASPEED_PULL_UP_PINCONF(B20, SCU618, 8),
2389
2390 /* GPIOI7 */
2391 ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7),
2392 /* GPIOI6 */
2393 ASPEED_PULL_DOWN_PINCONF(B16, SCU618, 6),
2394 /* GPIOI5 */
2395 ASPEED_PULL_DOWN_PINCONF(E16, SCU618, 5),
2396 /* GPIOI4 */
2397 ASPEED_PULL_DOWN_PINCONF(C16, SCU618, 4),
2398 /* GPIOI3 */
2399 ASPEED_PULL_DOWN_PINCONF(D16, SCU618, 3),
2400 /* GPIOI2 */
2401 ASPEED_PULL_DOWN_PINCONF(E17, SCU618, 2),
2402 /* GPIOI1 */
2403 ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1),
2404 /* GPIOI0 */
2405 ASPEED_PULL_DOWN_PINCONF(D17, SCU618, 0),
2406
2407 /* GPIOP7 */
2408 ASPEED_PULL_DOWN_PINCONF(Y23, SCU61C, 31),
2409 /* GPIOP6 */
2410 ASPEED_PULL_DOWN_PINCONF(AB24, SCU61C, 30),
2411 /* GPIOP5 */
2412 ASPEED_PULL_DOWN_PINCONF(AB23, SCU61C, 29),
2413 /* GPIOP4 */
2414 ASPEED_PULL_DOWN_PINCONF(W23, SCU61C, 28),
2415 /* GPIOP3 */
2416 ASPEED_PULL_DOWN_PINCONF(AA24, SCU61C, 27),
2417 /* GPIOP2 */
2418 ASPEED_PULL_DOWN_PINCONF(AA23, SCU61C, 26),
2419 /* GPIOP1 */
2420 ASPEED_PULL_DOWN_PINCONF(W24, SCU61C, 25),
2421 /* GPIOP0 */
2422 ASPEED_PULL_DOWN_PINCONF(AB22, SCU61C, 24),
2423
2424 /* GPIOO7 */
2425 ASPEED_PULL_DOWN_PINCONF(AC23, SCU61C, 23),
2426 /* GPIOO6 */
2427 ASPEED_PULL_DOWN_PINCONF(AC24, SCU61C, 22),
2428 /* GPIOO5 */
2429 ASPEED_PULL_DOWN_PINCONF(AC22, SCU61C, 21),
2430 /* GPIOO4 */
2431 ASPEED_PULL_DOWN_PINCONF(AD25, SCU61C, 20),
2432 /* GPIOO3 */
2433 ASPEED_PULL_DOWN_PINCONF(AD24, SCU61C, 19),
2434 /* GPIOO2 */
2435 ASPEED_PULL_DOWN_PINCONF(AD23, SCU61C, 18),
2436 /* GPIOO1 */
2437 ASPEED_PULL_DOWN_PINCONF(AD22, SCU61C, 17),
2438 /* GPIOO0 */
2439 ASPEED_PULL_DOWN_PINCONF(AD26, SCU61C, 16),
2440
2441 /* GPION7 */
2442 ASPEED_PULL_DOWN_PINCONF(M26, SCU61C, 15),
2443 /* GPION6 */
2444 ASPEED_PULL_DOWN_PINCONF(N26, SCU61C, 14),
2445 /* GPION5 */
2446 ASPEED_PULL_DOWN_PINCONF(M23, SCU61C, 13),
2447 /* GPION4 */
2448 ASPEED_PULL_DOWN_PINCONF(P26, SCU61C, 12),
2449 /* GPION3 */
2450 ASPEED_PULL_DOWN_PINCONF(N24, SCU61C, 11),
2451 /* GPION2 */
2452 ASPEED_PULL_DOWN_PINCONF(N25, SCU61C, 10),
2453 /* GPION1 */
2454 ASPEED_PULL_DOWN_PINCONF(N23, SCU61C, 9),
2455 /* GPION0 */
2456 ASPEED_PULL_DOWN_PINCONF(P25, SCU61C, 8),
2457
2458 /* GPIOM7 */
2459 ASPEED_PULL_DOWN_PINCONF(D13, SCU61C, 7),
2460 /* GPIOM6 */
2461 ASPEED_PULL_DOWN_PINCONF(C13, SCU61C, 6),
2462 /* GPIOM5 */
2463 ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5),
2464 /* GPIOM4 */
2465 ASPEED_PULL_DOWN_PINCONF(B12, SCU61C, 4),
2466 /* GPIOM3 */
2467 ASPEED_PULL_DOWN_PINCONF(E14, SCU61C, 3),
2468 /* GPIOM2 */
2469 ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2),
2470 /* GPIOM1 */
2471 ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1),
2472 /* GPIOM0 */
2473 ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0),
2474
2475 /* GPIOS7 */
2476 ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23),
2477 /* GPIOS6 */
2478 ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22),
2479 /* GPIOS5 */
2480 ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21),
2481 /* GPIOS4 */
2482 ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20),
2483 /* GPIOS3*/
2484 ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19),
2485 /* GPIOS2 */
2486 ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18),
2487 /* GPIOS1 */
2488 ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17),
2489 /* GPIOS0 */
2490 ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16),
2491
2492 /* GPIOR7 */
2493 ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15),
2494 /* GPIOR6 */
2495 ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14),
2496 /* GPIOR5 */
2497 ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13),
2498 /* GPIOR4 */
2499 ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12),
2500 /* GPIOR3*/
2501 ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11),
2502 /* GPIOR2 */
2503 ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10),
2504 /* GPIOR1 */
2505 ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9),
2506 /* GPIOR0 */
2507 ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8),
2508
2509 /* GPIOX7 */
2510 ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31),
2511 /* GPIOX6 */
2512 ASPEED_PULL_DOWN_PINCONF(AF9, SCU634, 30),
2513 /* GPIOX5 */
2514 ASPEED_PULL_DOWN_PINCONF(AD9, SCU634, 29),
2515 /* GPIOX4 */
2516 ASPEED_PULL_DOWN_PINCONF(AB9, SCU634, 28),
2517 /* GPIOX3*/
2518 ASPEED_PULL_DOWN_PINCONF(AF8, SCU634, 27),
2519 /* GPIOX2 */
2520 ASPEED_PULL_DOWN_PINCONF(AC9, SCU634, 26),
2521 /* GPIOX1 */
2522 ASPEED_PULL_DOWN_PINCONF(AA9, SCU634, 25),
2523 /* GPIOX0 */
2524 ASPEED_PULL_DOWN_PINCONF(AE8, SCU634, 24),
2525
2526 /* GPIOV7 */
2527 ASPEED_PULL_DOWN_PINCONF(AF15, SCU634, 15),
2528 /* GPIOV6 */
2529 ASPEED_PULL_DOWN_PINCONF(AD15, SCU634, 14),
2530 /* GPIOV5 */
2531 ASPEED_PULL_DOWN_PINCONF(AE14, SCU634, 13),
2532 /* GPIOV4 */
2533 ASPEED_PULL_DOWN_PINCONF(AE15, SCU634, 12),
2534 /* GPIOV3*/
2535 ASPEED_PULL_DOWN_PINCONF(AC15, SCU634, 11),
2536 /* GPIOV2 */
2537 ASPEED_PULL_DOWN_PINCONF(AD14, SCU634, 10),
2538 /* GPIOV1 */
2539 ASPEED_PULL_DOWN_PINCONF(AF14, SCU634, 9),
2540 /* GPIOV0 */
2541 ASPEED_PULL_DOWN_PINCONF(AB15, SCU634, 8),
2542
2543 /* GPIOZ7 */
2544 ASPEED_PULL_DOWN_PINCONF(AF10, SCU638, 15),
2545 /* GPIOZ6 */
2546 ASPEED_PULL_DOWN_PINCONF(AD11, SCU638, 14),
2547 /* GPIOZ5 */
2548 ASPEED_PULL_DOWN_PINCONF(AA11, SCU638, 13),
2549 /* GPIOZ4 */
2550 ASPEED_PULL_DOWN_PINCONF(AC11, SCU638, 12),
2551 /* GPIOZ3*/
2552 ASPEED_PULL_DOWN_PINCONF(AB11, SCU638, 11),
2553
2554 /* GPIOZ1 */
2555 ASPEED_PULL_DOWN_PINCONF(AD10, SCU638, 9),
2556 /* GPIOZ0 */
2557 ASPEED_PULL_DOWN_PINCONF(AC10, SCU638, 8),
2558
2559 /* GPIOY6 */
2560 ASPEED_PULL_DOWN_PINCONF(AC12, SCU638, 6),
2561 /* GPIOY5 */
2562 ASPEED_PULL_DOWN_PINCONF(AF12, SCU638, 5),
2563 /* GPIOY4 */
2564 ASPEED_PULL_DOWN_PINCONF(AE12, SCU638, 4),
2565 /* GPIOY3 */
2566 ASPEED_PULL_DOWN_PINCONF(AA12, SCU638, 3),
2567 /* GPIOY2 */
2568 ASPEED_PULL_DOWN_PINCONF(AE11, SCU638, 2),
2569 /* GPIOY1 */
2570 ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1),
2571 /* GPIOY0 */
2572 ASPEED_PULL_DOWN_PINCONF(AF11, SCU638, 0),
2573
2574 /* LAD3 */
2575 { PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)},
2576 /* LAD2 */
2577 { PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)},
2578 /* LAD1 */
2579 { PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)},
2580 /* LAD0 */
2581 { PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)},
2582
2583 /* MAC3 */
2584 { PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)},
2585 { PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)},
2586 /* MAC4 */
2587 { PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)},
2588 { PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},
2589};
2590
2233/**2591/**
2234 * Configure a pin's signal by applying an expression's descriptor state for2592 * Configure a pin's signal by applying an expression's descriptor state for
2235 * all descriptors in the expression.2593 * all descriptors in the expression.
@@ -2297,6 +2655,20 @@ static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx, · 61 unmodified lines
2297 return 0;2655 return 0;
2298}2656}
2299 2657
2658static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = {
2659 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
2660 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2661 { PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)},
2662 { PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)},
2663 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2664 { PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)},
2665 { PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)},
2666 { PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)},
2667 { PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)},
2668 { PIN_CONFIG_POWER_SOURCE, 3300, 0, BIT_MASK(0)},
2669 { PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)},
2670};
2671
2300static const struct aspeed_pinmux_ops aspeed_g5_ops = {2672static const struct aspeed_pinmux_ops aspeed_g5_ops = {
2301 .set = aspeed_g6_sig_expr_set,2673 .set = aspeed_g6_sig_expr_set,
2302};2674};
@@ -2311,6 +2683,10 @@ static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = { · 8 unmodified lines
2311 .functions = aspeed_g6_functions,2683 .functions = aspeed_g6_functions,
2312 .nfunctions = ARRAY_SIZE(aspeed_g6_functions),2684 .nfunctions = ARRAY_SIZE(aspeed_g6_functions),
2313 },2685 },
2686 .configs = aspeed_g6_configs,
2687 .nconfigs = ARRAY_SIZE(aspeed_g6_configs),
2688 .confmaps = aspeed_g6_pin_config_map,
2689 .nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map),
2314};2690};
2315 2691
2316static const struct pinmux_ops aspeed_g6_pinmux_ops = {2692static const struct pinmux_ops aspeed_g6_pinmux_ops = {
@@ -2331,12 +2707,21 @@ static const struct pinctrl_ops aspeed_g6_pinctrl_ops = { · 14 unmodified lines
2331 .dt_free_map = pinctrl_utils_free_map,2707 .dt_free_map = pinctrl_utils_free_map,
2332};2708};
2333 2709
2710static const struct pinconf_ops aspeed_g6_conf_ops = {
2711 .is_generic = true,
2712 .pin_config_get = aspeed_pin_config_get,
2713 .pin_config_set = aspeed_pin_config_set,
2714 .pin_config_group_get = aspeed_pin_config_group_get,
2715 .pin_config_group_set = aspeed_pin_config_group_set,
2716};
2717
2334static struct pinctrl_desc aspeed_g6_pinctrl_desc = {2718static struct pinctrl_desc aspeed_g6_pinctrl_desc = {
2335 .name = "aspeed-g6-pinctrl",2719 .name = "aspeed-g6-pinctrl",
2336 .pins = aspeed_g6_pins,2720 .pins = aspeed_g6_pins,
2337 .npins = ARRAY_SIZE(aspeed_g6_pins),2721 .npins = ARRAY_SIZE(aspeed_g6_pins),
2338 .pctlops = &aspeed_g6_pinctrl_ops,2722 .pctlops = &aspeed_g6_pinctrl_ops,
2339 .pmxops = &aspeed_g6_pinmux_ops,2723 .pmxops = &aspeed_g6_pinmux_ops,
2724 .confops = &aspeed_g6_conf_ops,
2340};2725};
2341 2726
2342static int aspeed_g6_pinctrl_probe(struct platform_device *pdev)2727static int aspeed_g6_pinctrl_probe(struct platform_device *pdev)
drivers/pinctrl/aspeed/pinctrl-aspeed.c+11−39
@@ -411,49 +411,21 @@ static inline const struct aspeed_pin_config *find_pinconf_config( · 410 unmodified lines
411 return NULL;411 return NULL;
412}412}
413 413
414/*
415 * Aspeed pin configuration description.
416 *
417 * @param: pinconf configuration parameter
418 * @arg: The supported argument for @param, or -1 if any value is supported
419 * @val: The register value to write to configure @arg for @param
420 *
421 * The map is to be used in conjunction with the configuration array supplied
422 * by the driver implementation.
423 */
424struct aspeed_pin_config_map {
425 enum pin_config_param param;
426 s32 arg;
427 u32 val;
428};
429
430enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL };414enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL };
431 415
432/* Aspeed consistently both:
433 *
434 * 1. Defines "disable bits" for internal pull-downs
435 * 2. Uses 8mA or 16mA drive strengths
436 */
437static const struct aspeed_pin_config_map pin_config_map[] = {
438 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1 },
439 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0 },
440 { PIN_CONFIG_BIAS_DISABLE, -1, 1 },
441 { PIN_CONFIG_DRIVE_STRENGTH, 8, 0 },
442 { PIN_CONFIG_DRIVE_STRENGTH, 16, 1 },
443};
444
445static const struct aspeed_pin_config_map *find_pinconf_map(416static const struct aspeed_pin_config_map *find_pinconf_map(
417 const struct aspeed_pinctrl_data *pdata,
446 enum pin_config_param param,418 enum pin_config_param param,
447 enum aspeed_pin_config_map_type type,419 enum aspeed_pin_config_map_type type,
448 s64 value)420 s64 value)
449{421{
450 int i;422 int i;
451 423
452 for (i = 0; i < ARRAY_SIZE(pin_config_map); i++) {424 for (i = 0; i < pdata->nconfmaps; i++) {
453 const struct aspeed_pin_config_map *elem;425 const struct aspeed_pin_config_map *elem;
454 bool match;426 bool match;
455 427
456 elem = &pin_config_map[i];428 elem = &pdata->confmaps[i];
457 429
458 switch (type) {430 switch (type) {
459 case MAP_TYPE_ARG:431 case MAP_TYPE_ARG:
@@ -491,8 +463,8 @@ int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset, · 31 unmodified lines
491 if (rc < 0)463 if (rc < 0)
492 return rc;464 return rc;
493 465
494 pmap = find_pinconf_map(param, MAP_TYPE_VAL,466 pmap = find_pinconf_map(pdata, param, MAP_TYPE_VAL,
495 (val & BIT(pconf->bit)) >> pconf->bit);467 (val & pconf->mask) >> __ffs(pconf->mask));
496 468
497 if (!pmap)469 if (!pmap)
498 return -EINVAL;470 return -EINVAL;
@@ -535,22 +507,22 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, · 36 unmodified lines
535 if (!pconf)507 if (!pconf)
536 return -ENOTSUPP;508 return -ENOTSUPP;
537 509
538 pmap = find_pinconf_map(param, MAP_TYPE_ARG, arg);510 pmap = find_pinconf_map(pdata, param, MAP_TYPE_ARG, arg);
539 511
540 if (WARN_ON(!pmap))512 if (WARN_ON(!pmap))
541 return -EINVAL;513 return -EINVAL;
542 514
543 val = pmap->val << pconf->bit;515 val = pmap->val << __ffs(pconf->mask);
544 516
545 rc = regmap_update_bits(pdata->scu, pconf->reg,517 rc = regmap_update_bits(pdata->scu, pconf->reg,
546 BIT(pconf->bit), val);518 pmap->mask, val);
547 519
548 if (rc < 0)520 if (rc < 0)
549 return rc;521 return rc;
550 522
551 pr_debug("%s: Set SCU%02X[%d]=%d for param %d(=%d) on pin %d\n",523 pr_debug("%s: Set SCU%02X[%lu]=%d for param %d(=%d) on pin %d\n",
552 __func__, pconf->reg, pconf->bit, pmap->val,524 __func__, pconf->reg, __ffs(pconf->mask),
553 param, arg, offset);525 pmap->val, param, arg, offset);
554 }526 }
555 527
556 return 0;528 return 0;
drivers/pinctrl/aspeed/pinctrl-aspeed.h+36−2
@@ -24,8 +24,7 @@ struct aspeed_pin_config { · 23 unmodified lines
24 enum pin_config_param param;24 enum pin_config_param param;
25 unsigned int pins[2];25 unsigned int pins[2];
26 unsigned int reg;26 unsigned int reg;
27 u8 bit;27 u32 mask;
28 u8 value;
29};28};
30 29
31#define ASPEED_PINCTRL_PIN(name_) \30#define ASPEED_PINCTRL_PIN(name_) \
@@ -35,6 +34,38 @@ struct aspeed_pin_config { · 3 unmodified lines
35 .drv_data = (void *) &(PIN_SYM(name_)) \34 .drv_data = (void *) &(PIN_SYM(name_)) \
36 }35 }
37 36
37#define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \
38 .param = param_, \
39 .pins = {pin0_, pin1_}, \
40 .reg = reg_, \
41 .mask = BIT_MASK(bit_) \
42}
43
44#define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \
45 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \
46 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
47
48#define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \
49 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \
50 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
51/*
52 * Aspeed pin configuration description.
53 *
54 * @param: pinconf configuration parameter
55 * @arg: The supported argument for @param, or -1 if any value is supported
56 * @val: The register value to write to configure @arg for @param
57 * @mask: The bitfield mask for @val
58 *
59 * The map is to be used in conjunction with the configuration array supplied
60 * by the driver implementation.
61 */
62struct aspeed_pin_config_map {
63 enum pin_config_param param;
64 s32 arg;
65 u32 val;
66 u32 mask;
67};
68
38struct aspeed_pinctrl_data {69struct aspeed_pinctrl_data {
39 struct regmap *scu;70 struct regmap *scu;
40 71
@@ -45,6 +76,9 @@ struct aspeed_pinctrl_data { · 4 unmodified lines
45 const unsigned int nconfigs;76 const unsigned int nconfigs;
46 77
47 struct aspeed_pinmux_data pinmux;78 struct aspeed_pinmux_data pinmux;
79
80 const struct aspeed_pin_config_map *confmaps;
81 const unsigned int nconfmaps;
48};82};
49 83
50/* Aspeed pinctrl helpers */84/* Aspeed pinctrl helpers */
drivers/pinctrl/aspeed/pinmux-aspeed.h+1−0
@@ -737,6 +737,7 @@ struct aspeed_pin_desc { · 736 unmodified lines
737#define FUNC_DECL_(func, ...) \737#define FUNC_DECL_(func, ...) \
738 static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }738 static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }
739 739
740#define FUNC_DECL_1(func, group) FUNC_DECL_(func, #group)
740#define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)741#define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)
741#define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three)742#define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three)
742 743
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c+8−2
@@ -286,6 +286,12 @@ static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) · 285 unmodified lines
286 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);286 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
287 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,287 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
288 rising_or_high);288 rising_or_high);
289
290 if (type & IRQ_TYPE_EDGE_BOTH)
291 irq_set_handler_locked(d, handle_edge_irq);
292 else
293 irq_set_handler_locked(d, handle_level_irq);
294
289 raw_spin_unlock_irqrestore(&chip->lock, flags);295 raw_spin_unlock_irqrestore(&chip->lock, flags);
290 296
291 dev_dbg(chip->dev,297 dev_dbg(chip->dev,
@@ -843,7 +849,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) · 551 unmodified lines
843 "gpio-ranges");849 "gpio-ranges");
844 850
845 /* optional GPIO interrupt support */851 /* optional GPIO interrupt support */
846 irq = platform_get_irq(pdev, 0);852 irq = platform_get_irq_optional(pdev, 0);
847 if (irq > 0) {853 if (irq > 0) {
848 struct irq_chip *irqc;854 struct irq_chip *irqc;
849 struct gpio_irq_chip *girq;855 struct gpio_irq_chip *girq;
@@ -868,7 +874,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) · 18 unmodified lines
868 return -ENOMEM;874 return -ENOMEM;
869 girq->parents[0] = irq;875 girq->parents[0] = irq;
870 girq->default_type = IRQ_TYPE_NONE;876 girq->default_type = IRQ_TYPE_NONE;
871 girq->handler = handle_simple_irq;877 girq->handler = handle_bad_irq;
872 }878 }
873 879
874 ret = gpiochip_add_data(gc, chip);880 ret = gpiochip_add_data(gc, chip);
drivers/pinctrl/cirrus/pinctrl-madera-core.c+0−1
@@ -560,7 +560,6 @@ static void __maybe_unused madera_pin_dbg_show(struct pinctrl_dev *pctldev, · 559 unmodified lines
560 seq_puts(s, " SCHMITT");560 seq_puts(s, " SCHMITT");
561}561}
562 562
563
564static const struct pinctrl_ops madera_pin_group_ops = {563static const struct pinctrl_ops madera_pin_group_ops = {
565 .get_groups_count = madera_get_groups_count,564 .get_groups_count = madera_get_groups_count,
566 .get_group_name = madera_get_group_name,565 .get_group_name = madera_get_group_name,
drivers/pinctrl/core.c+16−25
@@ -1376,8 +1376,15 @@ void devm_pinctrl_put(struct pinctrl *p) · 1375 unmodified lines
1376}1376}
1377EXPORT_SYMBOL_GPL(devm_pinctrl_put);1377EXPORT_SYMBOL_GPL(devm_pinctrl_put);
1378 1378
1379int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps,1379/**
1380 bool dup)1380 * pinctrl_register_mappings() - register a set of pin controller mappings
1381 * @maps: the pincontrol mappings table to register. Note the pinctrl-core
1382 * keeps a reference to the passed in maps, so they should _not_ be
1383 * marked with __initdata.
1384 * @num_maps: the number of maps in the mapping table
1385 */
1386int pinctrl_register_mappings(const struct pinctrl_map *maps,
1387 unsigned num_maps)
1381{1388{
1382 int i, ret;1389 int i, ret;
1383 struct pinctrl_maps *maps_node;1390 struct pinctrl_maps *maps_node;
@@ -1430,17 +1437,8 @@ int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps, · 46 unmodified lines
1430 if (!maps_node)1437 if (!maps_node)
1431 return -ENOMEM;1438 return -ENOMEM;
1432 1439
1440 maps_node->maps = maps;
1433 maps_node->num_maps = num_maps;1441 maps_node->num_maps = num_maps;
1434 if (dup) {
1435 maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
1436 GFP_KERNEL);
1437 if (!maps_node->maps) {
1438 kfree(maps_node);
1439 return -ENOMEM;
1440 }
1441 } else {
1442 maps_node->maps = maps;
1443 }
1444 1442
1445 mutex_lock(&pinctrl_maps_mutex);1443 mutex_lock(&pinctrl_maps_mutex);
1446 list_add_tail(&maps_node->node, &pinctrl_maps);1444 list_add_tail(&maps_node->node, &pinctrl_maps);
@@ -1448,22 +1446,14 @@ int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps, · 1 unmodified line
1448 1446
1449 return 0;1447 return 0;
1450}1448}
1449EXPORT_SYMBOL_GPL(pinctrl_register_mappings);
1451 1450
1452/**1451/**
1453 * pinctrl_register_mappings() - register a set of pin controller mappings1452 * pinctrl_unregister_mappings() - unregister a set of pin controller mappings
1454 * @maps: the pincontrol mappings table to register. This should probably be1453 * @maps: the pincontrol mappings table passed to pinctrl_register_mappings()
1455 * marked with __initdata so it can be discarded after boot. This1454 * when registering the mappings.
1456 * function will perform a shallow copy for the mapping entries.
1457 * @num_maps: the number of maps in the mapping table
1458 */1455 */
1459int pinctrl_register_mappings(const struct pinctrl_map *maps,1456void pinctrl_unregister_mappings(const struct pinctrl_map *map)
1460 unsigned num_maps)
1461{
1462 return pinctrl_register_map(maps, num_maps, true);
1463}
1464EXPORT_SYMBOL_GPL(pinctrl_register_mappings);
1465
1466void pinctrl_unregister_map(const struct pinctrl_map *map)
1467{1457{
1468 struct pinctrl_maps *maps_node;1458 struct pinctrl_maps *maps_node;
1469 1459
@@ -1478,6 +1468,7 @@ void pinctrl_unregister_map(const struct pinctrl_map *map) · 8 unmodified lines
1478 }1468 }
1479 mutex_unlock(&pinctrl_maps_mutex);1469 mutex_unlock(&pinctrl_maps_mutex);
1480}1470}
1471EXPORT_SYMBOL_GPL(pinctrl_unregister_mappings);
1481 1472
1482/**1473/**
1483 * pinctrl_force_sleep() - turn a given controller device into sleep state1474 * pinctrl_force_sleep() - turn a given controller device into sleep state
drivers/pinctrl/core.h+0−4
@@ -236,10 +236,6 @@ extern struct pinctrl_gpio_range * · 235 unmodified lines
236pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,236pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
237 unsigned int pin);237 unsigned int pin);
238 238
239int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps,
240 bool dup);
241void pinctrl_unregister_map(const struct pinctrl_map *map);
242
243extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);239extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);
244extern int pinctrl_force_default(struct pinctrl_dev *pctldev);240extern int pinctrl_force_default(struct pinctrl_dev *pctldev);
245 241
drivers/pinctrl/devicetree.c+2−2
@@ -51,7 +51,7 @@ void pinctrl_dt_free_maps(struct pinctrl *p) · 50 unmodified lines
51 struct pinctrl_dt_map *dt_map, *n1;51 struct pinctrl_dt_map *dt_map, *n1;
52 52
53 list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {53 list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
54 pinctrl_unregister_map(dt_map->map);54 pinctrl_unregister_mappings(dt_map->map);
55 list_del(&dt_map->node);55 list_del(&dt_map->node);
56 dt_free_map(dt_map->pctldev, dt_map->map,56 dt_free_map(dt_map->pctldev, dt_map->map,
57 dt_map->num_maps);57 dt_map->num_maps);
@@ -92,7 +92,7 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, · 34 unmodified lines
92 dt_map->num_maps = num_maps;92 dt_map->num_maps = num_maps;
93 list_add_tail(&dt_map->node, &p->dt_maps);93 list_add_tail(&dt_map->node, &p->dt_maps);
94 94
95 return pinctrl_register_map(map, num_maps, false);95 return pinctrl_register_mappings(map, num_maps);
96 96
97err_free_map:97err_free_map:
98 dt_free_map(pctldev, map, num_maps);98 dt_free_map(pctldev, map, num_maps);
drivers/pinctrl/freescale/Kconfig+7−0
@@ -137,6 +137,13 @@ config PINCTRL_IMX8MN · 136 unmodified lines
137 help137 help
138 Say Y here to enable the imx8mn pinctrl driver138 Say Y here to enable the imx8mn pinctrl driver
139 139
140config PINCTRL_IMX8MP
141 bool "IMX8MP pinctrl driver"
142 depends on ARCH_MXC && ARM64
143 select PINCTRL_IMX
144 help
145 Say Y here to enable the imx8mp pinctrl driver
146
140config PINCTRL_IMX8MQ147config PINCTRL_IMX8MQ
141 bool "IMX8MQ pinctrl driver"148 bool "IMX8MQ pinctrl driver"
142 depends on ARCH_MXC && ARM64149 depends on ARCH_MXC && ARM64
drivers/pinctrl/freescale/Makefile+1−0
@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o · 19 unmodified lines
20obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o20obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
21obj-$(CONFIG_PINCTRL_IMX8MM) += pinctrl-imx8mm.o21obj-$(CONFIG_PINCTRL_IMX8MM) += pinctrl-imx8mm.o
22obj-$(CONFIG_PINCTRL_IMX8MN) += pinctrl-imx8mn.o22obj-$(CONFIG_PINCTRL_IMX8MN) += pinctrl-imx8mn.o
23obj-$(CONFIG_PINCTRL_IMX8MP) += pinctrl-imx8mp.o
23obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o24obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
24obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o25obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
25obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o26obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
drivers/pinctrl/freescale/pinctrl-imx8mp.c+345−0
@@ -0,0 +1,345 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <linux/err.h>
7#include <linux/init.h>
8#include <linux/of.h>
9#include <linux/pinctrl/pinctrl.h>
10#include <linux/platform_device.h>
11
12#include "pinctrl-imx.h"
13
14enum imx8mp_pads {
15 MX8MP_IOMUXC_RESERVE0 = 0,
16 MX8MP_IOMUXC_RESERVE1 = 1,
17 MX8MP_IOMUXC_RESERVE2 = 2,
18 MX8MP_IOMUXC_RESERVE3 = 3,
19 MX8MP_IOMUXC_RESERVE4 = 4,
20 MX8MP_IOMUXC_GPIO1_IO00 = 5,
21 MX8MP_IOMUXC_GPIO1_IO01 = 6,
22 MX8MP_IOMUXC_GPIO1_IO02 = 7,
23 MX8MP_IOMUXC_GPIO1_IO03 = 8,
24 MX8MP_IOMUXC_GPIO1_IO04 = 9,
25 MX8MP_IOMUXC_GPIO1_IO05 = 10,
26 MX8MP_IOMUXC_GPIO1_IO06 = 11,
27 MX8MP_IOMUXC_GPIO1_IO07 = 12,
28 MX8MP_IOMUXC_GPIO1_IO08 = 13,
29 MX8MP_IOMUXC_GPIO1_IO09 = 14,
30 MX8MP_IOMUXC_GPIO1_IO10 = 15,
31 MX8MP_IOMUXC_GPIO1_IO11 = 16,
32 MX8MP_IOMUXC_GPIO1_IO12 = 17,
33 MX8MP_IOMUXC_GPIO1_IO13 = 18,
34 MX8MP_IOMUXC_GPIO1_IO14 = 19,
35 MX8MP_IOMUXC_GPIO1_IO15 = 20,
36 MX8MP_IOMUXC_ENET_MDC = 21,
37 MX8MP_IOMUXC_ENET_MDIO = 22,
38 MX8MP_IOMUXC_ENET_TD3 = 23,
39 MX8MP_IOMUXC_ENET_TD2 = 24,
40 MX8MP_IOMUXC_ENET_TD1 = 25,
41 MX8MP_IOMUXC_ENET_TD0 = 26,
42 MX8MP_IOMUXC_ENET_TX_CTL = 27,
43 MX8MP_IOMUXC_ENET_TXC = 28,
44 MX8MP_IOMUXC_ENET_RX_CTL = 29,
45 MX8MP_IOMUXC_ENET_RXC = 30,
46 MX8MP_IOMUXC_ENET_RD0 = 31,
47 MX8MP_IOMUXC_ENET_RD1 = 32,
48 MX8MP_IOMUXC_ENET_RD2 = 33,
49 MX8MP_IOMUXC_ENET_RD3 = 34,
50 MX8MP_IOMUXC_SD1_CLK = 35,
51 MX8MP_IOMUXC_SD1_CMD = 36,
52 MX8MP_IOMUXC_SD1_DATA0 = 37,
53 MX8MP_IOMUXC_SD1_DATA1 = 38,
54 MX8MP_IOMUXC_SD1_DATA2 = 39,
55 MX8MP_IOMUXC_SD1_DATA3 = 40,
56 MX8MP_IOMUXC_SD1_DATA4 = 41,
57 MX8MP_IOMUXC_SD1_DATA5 = 42,
58 MX8MP_IOMUXC_SD1_DATA6 = 43,
59 MX8MP_IOMUXC_SD1_DATA7 = 44,
60 MX8MP_IOMUXC_SD1_RESET_B = 45,
61 MX8MP_IOMUXC_SD1_STROBE = 46,
62 MX8MP_IOMUXC_SD2_CD_B = 47,
63 MX8MP_IOMUXC_SD2_CLK = 48,
64 MX8MP_IOMUXC_SD2_CMD = 49,
65 MX8MP_IOMUXC_SD2_DATA0 = 50,
66 MX8MP_IOMUXC_SD2_DATA1 = 51,
67 MX8MP_IOMUXC_SD2_DATA2 = 52,
68 MX8MP_IOMUXC_SD2_DATA3 = 53,
69 MX8MP_IOMUXC_SD2_RESET_B = 54,
70 MX8MP_IOMUXC_SD2_WP = 55,
71 MX8MP_IOMUXC_NAND_ALE = 56,
72 MX8MP_IOMUXC_NAND_CE0_B = 57,
73 MX8MP_IOMUXC_NAND_CE1_B = 58,
74 MX8MP_IOMUXC_NAND_CE2_B = 59,
75 MX8MP_IOMUXC_NAND_CE3_B = 60,
76 MX8MP_IOMUXC_NAND_CLE = 61,
77 MX8MP_IOMUXC_NAND_DATA00 = 62,
78 MX8MP_IOMUXC_NAND_DATA01 = 63,
79 MX8MP_IOMUXC_NAND_DATA02 = 64,
80 MX8MP_IOMUXC_NAND_DATA03 = 65,
81 MX8MP_IOMUXC_NAND_DATA04 = 66,
82 MX8MP_IOMUXC_NAND_DATA05 = 67,
83 MX8MP_IOMUXC_NAND_DATA06 = 68,
84 MX8MP_IOMUXC_NAND_DATA07 = 69,
85 MX8MP_IOMUXC_NAND_DQS = 70,
86 MX8MP_IOMUXC_NAND_RE_B = 71,
87 MX8MP_IOMUXC_NAND_READY_B = 72,
88 MX8MP_IOMUXC_NAND_WE_B = 73,
89 MX8MP_IOMUXC_NAND_WP_B = 74,
90 MX8MP_IOMUXC_SAI5_RXFS = 75,
91 MX8MP_IOMUXC_SAI5_RXC = 76,
92 MX8MP_IOMUXC_SAI5_RXD0 = 77,
93 MX8MP_IOMUXC_SAI5_RXD1 = 78,
94 MX8MP_IOMUXC_SAI5_RXD2 = 79,
95 MX8MP_IOMUXC_SAI5_RXD3 = 80,
96 MX8MP_IOMUXC_SAI5_MCLK = 81,
97 MX8MP_IOMUXC_SAI1_RXFS = 82,
98 MX8MP_IOMUXC_SAI1_RXC = 83,
99 MX8MP_IOMUXC_SAI1_RXD0 = 84,
100 MX8MP_IOMUXC_SAI1_RXD1 = 85,
101 MX8MP_IOMUXC_SAI1_RXD2 = 86,
102 MX8MP_IOMUXC_SAI1_RXD3 = 87,
103 MX8MP_IOMUXC_SAI1_RXD4 = 88,
104 MX8MP_IOMUXC_SAI1_RXD5 = 89,
105 MX8MP_IOMUXC_SAI1_RXD6 = 90,
106 MX8MP_IOMUXC_SAI1_RXD7 = 91,
107 MX8MP_IOMUXC_SAI1_TXFS = 92,
108 MX8MP_IOMUXC_SAI1_TXC = 93,
109 MX8MP_IOMUXC_SAI1_TXD0 = 94,
110 MX8MP_IOMUXC_SAI1_TXD1 = 95,
111 MX8MP_IOMUXC_SAI1_TXD2 = 96,
112 MX8MP_IOMUXC_SAI1_TXD3 = 97,
113 MX8MP_IOMUXC_SAI1_TXD4 = 98,
114 MX8MP_IOMUXC_SAI1_TXD5 = 99,
115 MX8MP_IOMUXC_SAI1_TXD6 = 100,
116 MX8MP_IOMUXC_SAI1_TXD7 = 101,
117 MX8MP_IOMUXC_SAI1_MCLK = 102,
118 MX8MP_IOMUXC_SAI2_RXFS = 103,
119 MX8MP_IOMUXC_SAI2_RXC = 104,
120 MX8MP_IOMUXC_SAI2_RXD0 = 105,
121 MX8MP_IOMUXC_SAI2_TXFS = 106,
122 MX8MP_IOMUXC_SAI2_TXC = 107,
123 MX8MP_IOMUXC_SAI2_TXD0 = 108,
124 MX8MP_IOMUXC_SAI2_MCLK = 109,
125 MX8MP_IOMUXC_SAI3_RXFS = 110,
126 MX8MP_IOMUXC_SAI3_RXC = 111,
127 MX8MP_IOMUXC_SAI3_RXD = 112,
128 MX8MP_IOMUXC_SAI3_TXFS = 113,
129 MX8MP_IOMUXC_SAI3_TXC = 114,
130 MX8MP_IOMUXC_SAI3_TXD = 115,
131 MX8MP_IOMUXC_SAI3_MCLK = 116,
132 MX8MP_IOMUXC_SPDIF_TX = 117,
133 MX8MP_IOMUXC_SPDIF_RX = 118,
134 MX8MP_IOMUXC_SPDIF_EXT_CLK = 119,
135 MX8MP_IOMUXC_ECSPI1_SCLK = 120,
136 MX8MP_IOMUXC_ECSPI1_MOSI = 121,
137 MX8MP_IOMUXC_ECSPI1_MISO = 122,
138 MX8MP_IOMUXC_ECSPI1_SS0 = 123,
139 MX8MP_IOMUXC_ECSPI2_SCLK = 124,
140 MX8MP_IOMUXC_ECSPI2_MOSI = 125,
141 MX8MP_IOMUXC_ECSPI2_MISO = 126,
142 MX8MP_IOMUXC_ECSPI2_SS0 = 127,
143 MX8MP_IOMUXC_I2C1_SCL = 128,
144 MX8MP_IOMUXC_I2C1_SDA = 129,
145 MX8MP_IOMUXC_I2C2_SCL = 130,
146 MX8MP_IOMUXC_I2C2_SDA = 131,
147 MX8MP_IOMUXC_I2C3_SCL = 132,
148 MX8MP_IOMUXC_I2C3_SDA = 133,
149 MX8MP_IOMUXC_I2C4_SCL = 134,
150 MX8MP_IOMUXC_I2C4_SDA = 135,
151 MX8MP_IOMUXC_UART1_RXD = 136,
152 MX8MP_IOMUXC_UART1_TXD = 137,
153 MX8MP_IOMUXC_UART2_RXD = 138,
154 MX8MP_IOMUXC_UART2_TXD = 139,
155 MX8MP_IOMUXC_UART3_RXD = 140,
156 MX8MP_IOMUXC_UART3_TXD = 141,
157 MX8MP_IOMUXC_UART4_RXD = 142,
158 MX8MP_IOMUXC_UART4_TXD = 143,
159 MX8MP_IOMUXC_HDMI_DDC_SCL = 144,
160 MX8MP_IOMUXC_HDMI_DDC_SDA = 145,
161 MX8MP_IOMUXC_HDMI_CEC = 146,
162 MX8MP_IOMUXC_HDMI_HPD = 147,
163};
164
165/* Pad names for the pinmux subsystem */
166static const struct pinctrl_pin_desc imx8mp_pinctrl_pads[] = {
167 IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE0),
168 IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE1),
169 IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE2),
170 IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE3),
171 IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE4),
172 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO00),
173 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO01),
174 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO02),
175 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO03),
176 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO04),
177 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO05),
178 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO06),
179 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO07),
180 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO08),
181 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO09),
182 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO10),
183 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO11),
184 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO12),
185 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO13),
186 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO14),
187 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO15),
188 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDC),
189 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDIO),
190 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD3),
191 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD2),
192 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD1),
193 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD0),
194 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TX_CTL),
195 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TXC),
196 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RX_CTL),
197 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RXC),
198 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD0),
199 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD1),
200 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD2),
201 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD3),
202 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CLK),
203 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CMD),
204 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA0),
205 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA1),
206 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA2),
207 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA3),
208 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA4),
209 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA5),
210 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA6),
211 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA7),
212 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_RESET_B),
213 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_STROBE),
214 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CD_B),
215 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CLK),
216 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CMD),
217 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA0),
218 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA1),
219 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA2),
220 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA3),
221 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_RESET_B),
222 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_WP),
223 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_ALE),
224 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE0_B),
225 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE1_B),
226 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE2_B),
227 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE3_B),
228 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CLE),
229 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA00),
230 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA01),
231 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA02),
232 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA03),
233 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA04),
234 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA05),
235 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA06),
236 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA07),
237 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DQS),
238 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_RE_B),
239 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_READY_B),
240 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WE_B),
241 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WP_B),
242 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXFS),
243 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXC),
244 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD0),
245 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD1),
246 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD2),
247 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD3),
248 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_MCLK),
249 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXFS),
250 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXC),
251 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD0),
252 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD1),
253 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD2),
254 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD3),
255 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD4),
256 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD5),
257 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD6),
258 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD7),
259 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXFS),
260 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXC),
261 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD0),
262 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD1),
263 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD2),
264 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD3),
265 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD4),
266 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD5),
267 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD6),
268 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD7),
269 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_MCLK),
270 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXFS),
271 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXC),
272 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXD0),
273 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXFS),
274 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXC),
275 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXD0),
276 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_MCLK),
277 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXFS),
278 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXC),
279 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXD),
280 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXFS),
281 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXC),
282 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXD),
283 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_MCLK),
284 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_TX),
285 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_RX),
286 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_EXT_CLK),
287 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SCLK),
288 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MOSI),
289 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MISO),
290 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SS0),
291 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SCLK),
292 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MOSI),
293 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MISO),
294 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SS0),
295 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SCL),
296 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SDA),
297 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SCL),
298 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SDA),
299 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SCL),
300 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SDA),
301 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SCL),
302 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SDA),
303 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_RXD),
304 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_TXD),
305 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_RXD),
306 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_TXD),
307 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_RXD),
308 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_TXD),
309 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_RXD),
310 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_TXD),
311 IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SCL),
312 IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SDA),
313 IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_CEC),
314 IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_HPD),
315};
316
317static const struct imx_pinctrl_soc_info imx8mp_pinctrl_info = {
318 .pins = imx8mp_pinctrl_pads,
319 .npins = ARRAY_SIZE(imx8mp_pinctrl_pads),
320 .gpr_compatible = "fsl,imx8mp-iomuxc-gpr",
321};
322
323static const struct of_device_id imx8mp_pinctrl_of_match[] = {
324 { .compatible = "fsl,imx8mp-iomuxc", .data = &imx8mp_pinctrl_info, },
325 { /* sentinel */ }
326};
327
328static int imx8mp_pinctrl_probe(struct platform_device *pdev)
329{
330 return imx_pinctrl_probe(pdev, &imx8mp_pinctrl_info);
331}
332
333static struct platform_driver imx8mp_pinctrl_driver = {
334 .driver = {
335 .name = "imx8mp-pinctrl",
336 .of_match_table = of_match_ptr(imx8mp_pinctrl_of_match),
337 },
338 .probe = imx8mp_pinctrl_probe,
339};
340
341static int __init imx8mp_pinctrl_init(void)
342{
343 return platform_driver_register(&imx8mp_pinctrl_driver);
344}
345arch_initcall(imx8mp_pinctrl_init);
drivers/pinctrl/intel/Kconfig+13−0
@@ -31,6 +31,19 @@ config PINCTRL_CHERRYVIEW · 30 unmodified lines
31 Cherryview/Braswell pinctrl driver provides an interface that31 Cherryview/Braswell pinctrl driver provides an interface that
32 allows configuring of SoC pins and using them as GPIOs.32 allows configuring of SoC pins and using them as GPIOs.
33 33
34config PINCTRL_LYNXPOINT
35 tristate "Intel Lynxpoint pinctrl and GPIO driver"
36 depends on ACPI
37 select PINMUX
38 select PINCONF
39 select GENERIC_PINCONF
40 select GPIOLIB
41 select GPIOLIB_IRQCHIP
42 help
43 Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
44 provides an interface that allows configuring of PCH pins and
45 using them as GPIOs.
46
34config PINCTRL_MERRIFIELD47config PINCTRL_MERRIFIELD
35 tristate "Intel Merrifield pinctrl driver"48 tristate "Intel Merrifield pinctrl driver"
36 depends on X86_INTEL_MID49 depends on X86_INTEL_MID
drivers/pinctrl/intel/Makefile+1−0
@@ -3,6 +3,7 @@ · 2 unmodified lines
3 3
4obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o4obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
5obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o5obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
6obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o
6obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o7obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
7obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o8obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
8obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o9obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
drivers/pinctrl/intel/pinctrl-baytrail.c+150−161
@@ -93,7 +93,7 @@ · 92 unmodified lines
93#define BYT_DEFAULT_GPIO_MUX 093#define BYT_DEFAULT_GPIO_MUX 0
94#define BYT_ALTER_GPIO_MUX 194#define BYT_ALTER_GPIO_MUX 1
95 95
96struct byt_gpio_pin_context {96struct intel_pad_context {
97 u32 conf0;97 u32 conf0;
98 u32 val;98 u32 val;
99};99};
@@ -105,16 +105,6 @@ struct byt_gpio_pin_context { · 5 unmodified lines
105 .pad_map = (map),\105 .pad_map = (map),\
106 }106 }
107 107
108struct byt_gpio {
109 struct gpio_chip chip;
110 struct platform_device *pdev;
111 struct pinctrl_dev *pctl_dev;
112 struct pinctrl_desc pctl_desc;
113 const struct intel_pinctrl_soc_data *soc_data;
114 struct intel_community *communities_copy;
115 struct byt_gpio_pin_context *saved_context;
116};
117
118/* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */108/* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
119static const struct pinctrl_pin_desc byt_score_pins[] = {109static const struct pinctrl_pin_desc byt_score_pins[] = {
120 PINCTRL_PIN(0, "SATA_GP0"),110 PINCTRL_PIN(0, "SATA_GP0"),
@@ -550,14 +540,14 @@ static const struct intel_pinctrl_soc_data *byt_soc_data[] = { · 429 unmodified lines
550 540
551static DEFINE_RAW_SPINLOCK(byt_lock);541static DEFINE_RAW_SPINLOCK(byt_lock);
552 542
553static struct intel_community *byt_get_community(struct byt_gpio *vg,543static struct intel_community *byt_get_community(struct intel_pinctrl *vg,
554 unsigned int pin)544 unsigned int pin)
555{545{
556 struct intel_community *comm;546 struct intel_community *comm;
557 int i;547 int i;
558 548
559 for (i = 0; i < vg->soc_data->ncommunities; i++) {549 for (i = 0; i < vg->ncommunities; i++) {
560 comm = vg->communities_copy + i;550 comm = vg->communities + i;
561 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)551 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
562 return comm;552 return comm;
563 }553 }
@@ -565,7 +555,7 @@ static struct intel_community *byt_get_community(struct byt_gpio *vg, · 1 unmodified line
565 return NULL;555 return NULL;
566}556}
567 557
568static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,558static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
569 int reg)559 int reg)
570{560{
571 struct intel_community *comm = byt_get_community(vg, offset);561 struct intel_community *comm = byt_get_community(vg, offset);
@@ -592,17 +582,17 @@ static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset, · 20 unmodified lines
592 582
593static int byt_get_groups_count(struct pinctrl_dev *pctldev)583static int byt_get_groups_count(struct pinctrl_dev *pctldev)
594{584{
595 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);585 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
596 586
597 return vg->soc_data->ngroups;587 return vg->soc->ngroups;
598}588}
599 589
600static const char *byt_get_group_name(struct pinctrl_dev *pctldev,590static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
601 unsigned int selector)591 unsigned int selector)
602{592{
603 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);593 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
604 594
605 return vg->soc_data->groups[selector].name;595 return vg->soc->groups[selector].name;
606}596}
607 597
608static int byt_get_group_pins(struct pinctrl_dev *pctldev,598static int byt_get_group_pins(struct pinctrl_dev *pctldev,
@@ -610,10 +600,10 @@ static int byt_get_group_pins(struct pinctrl_dev *pctldev, · 1 unmodified line
610 const unsigned int **pins,600 const unsigned int **pins,
611 unsigned int *num_pins)601 unsigned int *num_pins)
612{602{
613 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);603 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
614 604
615 *pins = vg->soc_data->groups[selector].pins;605 *pins = vg->soc->groups[selector].pins;
616 *num_pins = vg->soc_data->groups[selector].npins;606 *num_pins = vg->soc->groups[selector].npins;
617 607
618 return 0;608 return 0;
619}609}
@@ -626,17 +616,17 @@ static const struct pinctrl_ops byt_pinctrl_ops = { · 6 unmodified lines
626 616
627static int byt_get_functions_count(struct pinctrl_dev *pctldev)617static int byt_get_functions_count(struct pinctrl_dev *pctldev)
628{618{
629 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);619 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
630 620
631 return vg->soc_data->nfunctions;621 return vg->soc->nfunctions;
632}622}
633 623
634static const char *byt_get_function_name(struct pinctrl_dev *pctldev,624static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
635 unsigned int selector)625 unsigned int selector)
636{626{
637 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);627 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
638 628
639 return vg->soc_data->functions[selector].name;629 return vg->soc->functions[selector].name;
640}630}
641 631
642static int byt_get_function_groups(struct pinctrl_dev *pctldev,632static int byt_get_function_groups(struct pinctrl_dev *pctldev,
@@ -644,15 +634,15 @@ static int byt_get_function_groups(struct pinctrl_dev *pctldev, · 1 unmodified line
644 const char * const **groups,634 const char * const **groups,
645 unsigned int *num_groups)635 unsigned int *num_groups)
646{636{
647 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);637 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
648 638
649 *groups = vg->soc_data->functions[selector].groups;639 *groups = vg->soc->functions[selector].groups;
650 *num_groups = vg->soc_data->functions[selector].ngroups;640 *num_groups = vg->soc->functions[selector].ngroups;
651 641
652 return 0;642 return 0;
653}643}
654 644
655static void byt_set_group_simple_mux(struct byt_gpio *vg,645static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
656 const struct intel_pingroup group,646 const struct intel_pingroup group,
657 unsigned int func)647 unsigned int func)
658{648{
@@ -667,7 +657,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg, · 8 unmodified lines
667 657
668 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);658 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
669 if (!padcfg0) {659 if (!padcfg0) {
670 dev_warn(&vg->pdev->dev,660 dev_warn(vg->dev,
671 "Group %s, pin %i not muxed (no padcfg0)\n",661 "Group %s, pin %i not muxed (no padcfg0)\n",
672 group.name, i);662 group.name, i);
673 continue;663 continue;
@@ -682,7 +672,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg, · 8 unmodified lines
682 raw_spin_unlock_irqrestore(&byt_lock, flags);672 raw_spin_unlock_irqrestore(&byt_lock, flags);
683}673}
684 674
685static void byt_set_group_mixed_mux(struct byt_gpio *vg,675static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
686 const struct intel_pingroup group,676 const struct intel_pingroup group,
687 const unsigned int *func)677 const unsigned int *func)
688{678{
@@ -697,7 +687,7 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg, · 8 unmodified lines
697 687
698 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);688 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
699 if (!padcfg0) {689 if (!padcfg0) {
700 dev_warn(&vg->pdev->dev,690 dev_warn(vg->dev,
701 "Group %s, pin %i not muxed (no padcfg0)\n",691 "Group %s, pin %i not muxed (no padcfg0)\n",
702 group.name, i);692 group.name, i);
703 continue;693 continue;
@@ -715,9 +705,9 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg, · 11 unmodified lines
715static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,705static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
716 unsigned int group_selector)706 unsigned int group_selector)
717{707{
718 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);708 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
719 const struct intel_function func = vg->soc_data->functions[func_selector];709 const struct intel_function func = vg->soc->functions[func_selector];
720 const struct intel_pingroup group = vg->soc_data->groups[group_selector];710 const struct intel_pingroup group = vg->soc->groups[group_selector];
721 711
722 if (group.modes)712 if (group.modes)
723 byt_set_group_mixed_mux(vg, group, group.modes);713 byt_set_group_mixed_mux(vg, group, group.modes);
@@ -729,22 +719,22 @@ static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, · 5 unmodified lines
729 return 0;719 return 0;
730}720}
731 721
732static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset)722static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
733{723{
734 /* SCORE pin 92-93 */724 /* SCORE pin 92-93 */
735 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&725 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
736 offset >= 92 && offset <= 93)726 offset >= 92 && offset <= 93)
737 return BYT_ALTER_GPIO_MUX;727 return BYT_ALTER_GPIO_MUX;
738 728
739 /* SUS pin 11-21 */729 /* SUS pin 11-21 */
740 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&730 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
741 offset >= 11 && offset <= 21)731 offset >= 11 && offset <= 21)
742 return BYT_ALTER_GPIO_MUX;732 return BYT_ALTER_GPIO_MUX;
743 733
744 return BYT_DEFAULT_GPIO_MUX;734 return BYT_DEFAULT_GPIO_MUX;
745}735}
746 736
747static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)737static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
748{738{
749 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);739 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
750 unsigned long flags;740 unsigned long flags;
@@ -752,7 +742,13 @@ static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset) · 1 unmodified line
752 742
753 raw_spin_lock_irqsave(&byt_lock, flags);743 raw_spin_lock_irqsave(&byt_lock, flags);
754 value = readl(reg);744 value = readl(reg);
755 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);745
746 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
747 if (value & BYT_DIRECT_IRQ_EN)
748 /* nothing to do */ ;
749 else
750 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
751
756 writel(value, reg);752 writel(value, reg);
757 raw_spin_unlock_irqrestore(&byt_lock, flags);753 raw_spin_unlock_irqrestore(&byt_lock, flags);
758}754}
@@ -761,7 +757,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, · 2 unmodified lines
761 struct pinctrl_gpio_range *range,757 struct pinctrl_gpio_range *range,
762 unsigned int offset)758 unsigned int offset)
763{759{
764 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);760 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
765 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);761 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
766 u32 value, gpio_mux;762 u32 value, gpio_mux;
767 unsigned long flags;763 unsigned long flags;
@@ -784,13 +780,12 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, · 16 unmodified lines
784 value |= gpio_mux;780 value |= gpio_mux;
785 writel(value, reg);781 writel(value, reg);
786 782
787 dev_warn(&vg->pdev->dev, FW_BUG783 dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
788 "pin %u forcibly re-configured as GPIO\n", offset);
789 }784 }
790 785
791 raw_spin_unlock_irqrestore(&byt_lock, flags);786 raw_spin_unlock_irqrestore(&byt_lock, flags);
792 787
793 pm_runtime_get(&vg->pdev->dev);788 pm_runtime_get(vg->dev);
794 789
795 return 0;790 return 0;
796}791}
@@ -799,10 +794,10 @@ static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, · 2 unmodified lines
799 struct pinctrl_gpio_range *range,794 struct pinctrl_gpio_range *range,
800 unsigned int offset)795 unsigned int offset)
801{796{
802 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);797 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
803 798
804 byt_gpio_clear_triggering(vg, offset);799 byt_gpio_clear_triggering(vg, offset);
805 pm_runtime_put(&vg->pdev->dev);800 pm_runtime_put(vg->dev);
806}801}
807 802
808static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,803static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
@@ -810,7 +805,7 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, · 1 unmodified line
810 unsigned int offset,805 unsigned int offset,
811 bool input)806 bool input)
812{807{
813 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);808 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
814 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);809 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
815 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);810 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
816 unsigned long flags;811 unsigned long flags;
@@ -822,15 +817,15 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, · 5 unmodified lines
822 value &= ~BYT_DIR_MASK;817 value &= ~BYT_DIR_MASK;
823 if (input)818 if (input)
824 value |= BYT_OUTPUT_EN;819 value |= BYT_OUTPUT_EN;
825 else820 else if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
826 /*821 /*
827 * Before making any direction modifications, do a check if gpio822 * Before making any direction modifications, do a check if gpio
828 * is set for direct IRQ. On baytrail, setting GPIO to output823 * is set for direct IRQ. On baytrail, setting GPIO to output
829 * does not make sense, so let's at least warn the caller before824 * does not make sense, so let's at least inform the caller before
830 * they shoot themselves in the foot.825 * they shoot themselves in the foot.
831 */826 */
832 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,827 dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
833 "Potential Error: Setting GPIO with direct_irq_en to output");828
834 writel(value, val_reg);829 writel(value, val_reg);
835 830
836 raw_spin_unlock_irqrestore(&byt_lock, flags);831 raw_spin_unlock_irqrestore(&byt_lock, flags);
@@ -893,7 +888,7 @@ static int byt_set_pull_strength(u32 *reg, u16 strength) · 56 unmodified lines
893static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,888static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
894 unsigned long *config)889 unsigned long *config)
895{890{
896 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);891 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
897 enum pin_config_param param = pinconf_to_config_param(*config);892 enum pin_config_param param = pinconf_to_config_param(*config);
898 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);893 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
899 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);894 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
@@ -978,7 +973,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, · 78 unmodified lines
978 unsigned long *configs,973 unsigned long *configs,
979 unsigned int num_configs)974 unsigned int num_configs)
980{975{
981 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);976 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
982 unsigned int param, arg;977 unsigned int param, arg;
983 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);978 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
984 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);979 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
@@ -1012,7 +1007,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, · 27 unmodified lines
1012 if (val & BYT_INPUT_EN) {1007 if (val & BYT_INPUT_EN) {
1013 val &= ~BYT_INPUT_EN;1008 val &= ~BYT_INPUT_EN;
1014 writel(val, val_reg);1009 writel(val, val_reg);
1015 dev_warn(&vg->pdev->dev,1010 dev_warn(vg->dev,
1016 "pin %u forcibly set to input mode\n",1011 "pin %u forcibly set to input mode\n",
1017 offset);1012 offset);
1018 }1013 }
@@ -1034,7 +1029,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, · 15 unmodified lines
1034 if (val & BYT_INPUT_EN) {1029 if (val & BYT_INPUT_EN) {
1035 val &= ~BYT_INPUT_EN;1030 val &= ~BYT_INPUT_EN;
1036 writel(val, val_reg);1031 writel(val, val_reg);
1037 dev_warn(&vg->pdev->dev,1032 dev_warn(vg->dev,
1038 "pin %u forcibly set to input mode\n",1033 "pin %u forcibly set to input mode\n",
1039 offset);1034 offset);
1040 }1035 }
@@ -1115,7 +1110,7 @@ static const struct pinctrl_desc byt_pinctrl_desc = { · 74 unmodified lines
1115 1110
1116static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)1111static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1117{1112{
1118 struct byt_gpio *vg = gpiochip_get_data(chip);1113 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1119 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);1114 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1120 unsigned long flags;1115 unsigned long flags;
1121 u32 val;1116 u32 val;
@@ -1129,7 +1124,7 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) · 7 unmodified lines
1129 1124
1130static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)1125static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1131{1126{
1132 struct byt_gpio *vg = gpiochip_get_data(chip);1127 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1133 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);1128 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1134 unsigned long flags;1129 unsigned long flags;
1135 u32 old_val;1130 u32 old_val;
@@ -1148,7 +1143,7 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) · 12 unmodified lines
1148 1143
1149static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)1144static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1150{1145{
1151 struct byt_gpio *vg = gpiochip_get_data(chip);1146 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1152 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);1147 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1153 unsigned long flags;1148 unsigned long flags;
1154 u32 value;1149 u32 value;
@@ -1161,9 +1156,9 @@ static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) · 6 unmodified lines
1161 raw_spin_unlock_irqrestore(&byt_lock, flags);1156 raw_spin_unlock_irqrestore(&byt_lock, flags);
1162 1157
1163 if (!(value & BYT_OUTPUT_EN))1158 if (!(value & BYT_OUTPUT_EN))
1164 return 0;1159 return GPIO_LINE_DIRECTION_OUT;
1165 if (!(value & BYT_INPUT_EN))1160 if (!(value & BYT_INPUT_EN))
1166 return 1;1161 return GPIO_LINE_DIRECTION_IN;
1167 1162
1168 return -EINVAL;1163 return -EINVAL;
1169}1164}
@@ -1188,11 +1183,11 @@ static int byt_gpio_direction_output(struct gpio_chip *chip, · 18 unmodified lines
1188 1183
1189static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)1184static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1190{1185{
1191 struct byt_gpio *vg = gpiochip_get_data(chip);1186 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1192 int i;1187 int i;
1193 u32 conf0, val;1188 u32 conf0, val;
1194 1189
1195 for (i = 0; i < vg->soc_data->npins; i++) {1190 for (i = 0; i < vg->soc->npins; i++) {
1196 const struct intel_community *comm;1191 const struct intel_community *comm;
1197 const char *pull_str = NULL;1192 const char *pull_str = NULL;
1198 const char *pull = NULL;1193 const char *pull = NULL;
@@ -1202,7 +1197,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) · 3 unmodified lines
1202 unsigned int pin;1197 unsigned int pin;
1203 1198
1204 raw_spin_lock_irqsave(&byt_lock, flags);1199 raw_spin_lock_irqsave(&byt_lock, flags);
1205 pin = vg->soc_data->pins[i].number;1200 pin = vg->soc->pins[i].number;
1206 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);1201 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1207 if (!reg) {1202 if (!reg) {
1208 seq_printf(s,1203 seq_printf(s,
@@ -1297,7 +1292,7 @@ static const struct gpio_chip byt_gpio_chip = { · 88 unmodified lines
1297static void byt_irq_ack(struct irq_data *d)1292static void byt_irq_ack(struct irq_data *d)
1298{1293{
1299 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);1294 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1300 struct byt_gpio *vg = gpiochip_get_data(gc);1295 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1301 unsigned int offset = irqd_to_hwirq(d);1296 unsigned int offset = irqd_to_hwirq(d);
1302 void __iomem *reg;1297 void __iomem *reg;
1303 1298
@@ -1313,7 +1308,7 @@ static void byt_irq_ack(struct irq_data *d) · 9 unmodified lines
1313static void byt_irq_mask(struct irq_data *d)1308static void byt_irq_mask(struct irq_data *d)
1314{1309{
1315 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);1310 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1316 struct byt_gpio *vg = gpiochip_get_data(gc);1311 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1317 1312
1318 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));1313 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1319}1314}
@@ -1321,7 +1316,7 @@ static void byt_irq_mask(struct irq_data *d) · 1 unmodified line
1321static void byt_irq_unmask(struct irq_data *d)1316static void byt_irq_unmask(struct irq_data *d)
1322{1317{
1323 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);1318 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1324 struct byt_gpio *vg = gpiochip_get_data(gc);1319 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1325 unsigned int offset = irqd_to_hwirq(d);1320 unsigned int offset = irqd_to_hwirq(d);
1326 unsigned long flags;1321 unsigned long flags;
1327 void __iomem *reg;1322 void __iomem *reg;
@@ -1359,7 +1354,7 @@ static void byt_irq_unmask(struct irq_data *d) · 31 unmodified lines
1359 1354
1360static int byt_irq_type(struct irq_data *d, unsigned int type)1355static int byt_irq_type(struct irq_data *d, unsigned int type)
1361{1356{
1362 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));1357 struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1363 u32 offset = irqd_to_hwirq(d);1358 u32 offset = irqd_to_hwirq(d);
1364 u32 value;1359 u32 value;
1365 unsigned long flags;1360 unsigned long flags;
@@ -1395,20 +1390,10 @@ static int byt_irq_type(struct irq_data *d, unsigned int type) · 29 unmodified lines
1395 return 0;1390 return 0;
1396}1391}
1397 1392
1398static struct irq_chip byt_irqchip = {
1399 .name = "BYT-GPIO",
1400 .irq_ack = byt_irq_ack,
1401 .irq_mask = byt_irq_mask,
1402 .irq_unmask = byt_irq_unmask,
1403 .irq_set_type = byt_irq_type,
1404 .flags = IRQCHIP_SKIP_SET_WAKE,
1405};
1406
1407static void byt_gpio_irq_handler(struct irq_desc *desc)1393static void byt_gpio_irq_handler(struct irq_desc *desc)
1408{1394{
1409 struct irq_data *data = irq_desc_get_irq_data(desc);1395 struct irq_data *data = irq_desc_get_irq_data(desc);
1410 struct byt_gpio *vg = gpiochip_get_data(1396 struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1411 irq_desc_get_handler_data(desc));
1412 struct irq_chip *chip = irq_data_get_irq_chip(data);1397 struct irq_chip *chip = irq_data_get_irq_chip(data);
1413 u32 base, pin;1398 u32 base, pin;
1414 void __iomem *reg;1399 void __iomem *reg;
@@ -1420,7 +1405,7 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) · 5 unmodified lines
1420 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);1405 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1421 1406
1422 if (!reg) {1407 if (!reg) {
1423 dev_warn(&vg->pdev->dev,1408 dev_warn(vg->dev,
1424 "Pin %i: could not retrieve interrupt status register\n",1409 "Pin %i: could not retrieve interrupt status register\n",
1425 base);1410 base);
1426 continue;1411 continue;
@@ -1441,22 +1426,9 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, · 14 unmodified lines
1441 unsigned long *valid_mask,1426 unsigned long *valid_mask,
1442 unsigned int ngpios)1427 unsigned int ngpios)
1443{1428{
1444 /*1429 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1445 * FIXME: currently the valid_mask is filled in as part of
1446 * initializing the irq_chip below in byt_gpio_irq_init_hw().
1447 * when converting this driver to the new way of passing the
1448 * gpio_irq_chip along when adding the gpio_chip, move the
1449 * mask initialization into this callback instead. Right now
1450 * this callback is here to make sure the mask gets allocated.
1451 */
1452}
1453
1454static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1455{
1456 struct byt_gpio *vg = gpiochip_get_data(chip);
1457 struct device *dev = &vg->pdev->dev;
1458 void __iomem *reg;1430 void __iomem *reg;
1459 u32 base, value;1431 u32 value;
1460 int i;1432 int i;
1461 1433
1462 /*1434 /*
@@ -1464,12 +1436,12 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip) · 1 unmodified line
1464 * do not use direct IRQ mode. This will prevent spurious1436 * do not use direct IRQ mode. This will prevent spurious
1465 * interrupts from misconfigured pins.1437 * interrupts from misconfigured pins.
1466 */1438 */
1467 for (i = 0; i < vg->soc_data->npins; i++) {1439 for (i = 0; i < vg->soc->npins; i++) {
1468 unsigned int pin = vg->soc_data->pins[i].number;1440 unsigned int pin = vg->soc->pins[i].number;
1469 1441
1470 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);1442 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1471 if (!reg) {1443 if (!reg) {
1472 dev_warn(&vg->pdev->dev,1444 dev_warn(vg->dev,
1473 "Pin %i: could not retrieve conf0 register\n",1445 "Pin %i: could not retrieve conf0 register\n",
1474 i);1446 i);
1475 continue;1447 continue;
@@ -1477,20 +1449,27 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip) · 1 unmodified line
1477 1449
1478 value = readl(reg);1450 value = readl(reg);
1479 if (value & BYT_DIRECT_IRQ_EN) {1451 if (value & BYT_DIRECT_IRQ_EN) {
1480 clear_bit(i, chip->irq.valid_mask);1452 clear_bit(i, valid_mask);
1481 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);1453 dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);
1482 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {1454 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1483 byt_gpio_clear_triggering(vg, i);1455 byt_gpio_clear_triggering(vg, i);
1484 dev_dbg(dev, "disabling GPIO %d\n", i);1456 dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1485 }1457 }
1486 }1458 }
1459}
1460
1461static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1462{
1463 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1464 void __iomem *reg;
1465 u32 base, value;
1487 1466
1488 /* clear interrupt status trigger registers */1467 /* clear interrupt status trigger registers */
1489 for (base = 0; base < vg->soc_data->npins; base += 32) {1468 for (base = 0; base < vg->soc->npins; base += 32) {
1490 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);1469 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1491 1470
1492 if (!reg) {1471 if (!reg) {
1493 dev_warn(&vg->pdev->dev,1472 dev_warn(vg->dev,
1494 "Pin %i: could not retrieve irq status reg\n",1473 "Pin %i: could not retrieve irq status reg\n",
1495 base);1474 base);
1496 continue;1475 continue;
@@ -1501,7 +1480,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip) · 4 unmodified lines
1501 might be misconfigured in bios */1480 might be misconfigured in bios */
1502 value = readl(reg);1481 value = readl(reg);
1503 if (value)1482 if (value)
1504 dev_err(&vg->pdev->dev,1483 dev_err(vg->dev,
1505 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",1484 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1506 base / 32, value);1485 base / 32, value);
1507 }1486 }
@@ -1511,19 +1490,20 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip) · 3 unmodified lines
1511 1490
1512static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)1491static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1513{1492{
1514 struct byt_gpio *vg = gpiochip_get_data(chip);1493 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1515 struct device *dev = &vg->pdev->dev;1494 struct device *dev = vg->dev;
1516 int ret;1495 int ret;
1517 1496
1518 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc_data->npins);1497 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1519 if (ret)1498 if (ret)
1520 dev_err(dev, "failed to add GPIO pin range\n");1499 dev_err(dev, "failed to add GPIO pin range\n");
1521 1500
1522 return ret;1501 return ret;
1523}1502}
1524 1503
1525static int byt_gpio_probe(struct byt_gpio *vg)1504static int byt_gpio_probe(struct intel_pinctrl *vg)
1526{1505{
1506 struct platform_device *pdev = to_platform_device(vg->dev);
1527 struct gpio_chip *gc;1507 struct gpio_chip *gc;
1528 struct resource *irq_rc;1508 struct resource *irq_rc;
1529 int ret;1509 int ret;
@@ -1531,32 +1511,39 @@ static int byt_gpio_probe(struct byt_gpio *vg) · 1 unmodified line
1531 /* Set up gpio chip */1511 /* Set up gpio chip */
1532 vg->chip = byt_gpio_chip;1512 vg->chip = byt_gpio_chip;
1533 gc = &vg->chip;1513 gc = &vg->chip;
1534 gc->label = dev_name(&vg->pdev->dev);1514 gc->label = dev_name(vg->dev);
1535 gc->base = -1;1515 gc->base = -1;
1536 gc->can_sleep = false;1516 gc->can_sleep = false;
1537 gc->add_pin_ranges = byt_gpio_add_pin_ranges;1517 gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1538 gc->parent = &vg->pdev->dev;1518 gc->parent = vg->dev;
1539 gc->ngpio = vg->soc_data->npins;1519 gc->ngpio = vg->soc->npins;
1540 gc->irq.init_valid_mask = byt_init_irq_valid_mask;
1541 1520
1542#ifdef CONFIG_PM_SLEEP1521#ifdef CONFIG_PM_SLEEP
1543 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,1522 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1544 sizeof(*vg->saved_context), GFP_KERNEL);1523 GFP_KERNEL);
1545 if (!vg->saved_context)1524 if (!vg->context.pads)
1546 return -ENOMEM;1525 return -ENOMEM;
1547#endif1526#endif
1548 1527
1549 /* set up interrupts */1528 /* set up interrupts */
1550 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);1529 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1551 if (irq_rc && irq_rc->start) {1530 if (irq_rc && irq_rc->start) {
1552 struct gpio_irq_chip *girq;1531 struct gpio_irq_chip *girq;
1553 1532
1533 vg->irqchip.name = "BYT-GPIO",
1534 vg->irqchip.irq_ack = byt_irq_ack,
1535 vg->irqchip.irq_mask = byt_irq_mask,
1536 vg->irqchip.irq_unmask = byt_irq_unmask,
1537 vg->irqchip.irq_set_type = byt_irq_type,
1538 vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE,
1539
1554 girq = &gc->irq;1540 girq = &gc->irq;
1555 girq->chip = &byt_irqchip;1541 girq->chip = &vg->irqchip;
1556 girq->init_hw = byt_gpio_irq_init_hw;1542 girq->init_hw = byt_gpio_irq_init_hw;
1543 girq->init_valid_mask = byt_init_irq_valid_mask;
1557 girq->parent_handler = byt_gpio_irq_handler;1544 girq->parent_handler = byt_gpio_irq_handler;
1558 girq->num_parents = 1;1545 girq->num_parents = 1;
1559 girq->parents = devm_kcalloc(&vg->pdev->dev, girq->num_parents,1546 girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1560 sizeof(*girq->parents), GFP_KERNEL);1547 sizeof(*girq->parents), GFP_KERNEL);
1561 if (!girq->parents)1548 if (!girq->parents)
1562 return -ENOMEM;1549 return -ENOMEM;
@@ -1565,34 +1552,35 @@ static int byt_gpio_probe(struct byt_gpio *vg) · 2 unmodified lines
1565 girq->handler = handle_bad_irq;1552 girq->handler = handle_bad_irq;
1566 }1553 }
1567 1554
1568 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);1555 ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1569 if (ret) {1556 if (ret) {
1570 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");1557 dev_err(vg->dev, "failed adding byt-gpio chip\n");
1571 return ret;1558 return ret;
1572 }1559 }
1573 1560
1574 return ret;1561 return ret;
1575}1562}
1576 1563
1577static int byt_set_soc_data(struct byt_gpio *vg,1564static int byt_set_soc_data(struct intel_pinctrl *vg,
1578 const struct intel_pinctrl_soc_data *soc_data)1565 const struct intel_pinctrl_soc_data *soc)
1579{1566{
1567 struct platform_device *pdev = to_platform_device(vg->dev);
1580 int i;1568 int i;
1581 1569
1582 vg->soc_data = soc_data;1570 vg->soc = soc;
1583 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,1571
1584 soc_data->ncommunities,1572 vg->ncommunities = vg->soc->ncommunities;
1585 sizeof(*vg->communities_copy),1573 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1586 GFP_KERNEL);1574 sizeof(*vg->communities), GFP_KERNEL);
1587 if (!vg->communities_copy)1575 if (!vg->communities)
1588 return -ENOMEM;1576 return -ENOMEM;
1589 1577
1590 for (i = 0; i < soc_data->ncommunities; i++) {1578 for (i = 0; i < vg->soc->ncommunities; i++) {
1591 struct intel_community *comm = vg->communities_copy + i;1579 struct intel_community *comm = vg->communities + i;
1592 1580
1593 *comm = vg->soc_data->communities[i];1581 *comm = vg->soc->communities[i];
1594 1582
1595 comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0);1583 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
1596 if (IS_ERR(comm->pad_regs))1584 if (IS_ERR(comm->pad_regs))
1597 return PTR_ERR(comm->pad_regs);1585 return PTR_ERR(comm->pad_regs);
1598 }1586 }
@@ -1610,15 +1598,16 @@ static int byt_pinctrl_probe(struct platform_device *pdev) · 11 unmodified lines
1610{1598{
1611 const struct intel_pinctrl_soc_data *soc_data = NULL;1599 const struct intel_pinctrl_soc_data *soc_data = NULL;
1612 const struct intel_pinctrl_soc_data **soc_table;1600 const struct intel_pinctrl_soc_data **soc_table;
1601 struct device *dev = &pdev->dev;
1613 struct acpi_device *acpi_dev;1602 struct acpi_device *acpi_dev;
1614 struct byt_gpio *vg;1603 struct intel_pinctrl *vg;
1615 int i, ret;1604 int i, ret;
1616 1605
1617 acpi_dev = ACPI_COMPANION(&pdev->dev);1606 acpi_dev = ACPI_COMPANION(dev);
1618 if (!acpi_dev)1607 if (!acpi_dev)
1619 return -ENODEV;1608 return -ENODEV;
1620 1609
1621 soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev);1610 soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
1622 1611
1623 for (i = 0; soc_table[i]; i++) {1612 for (i = 0; soc_table[i]; i++) {
1624 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {1613 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
@@ -1630,26 +1619,26 @@ static int byt_pinctrl_probe(struct platform_device *pdev) · 5 unmodified lines
1630 if (!soc_data)1619 if (!soc_data)
1631 return -ENODEV;1620 return -ENODEV;
1632 1621
1633 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);1622 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1634 if (!vg)1623 if (!vg)
1635 return -ENOMEM;1624 return -ENOMEM;
1636 1625
1637 vg->pdev = pdev;1626 vg->dev = dev;
1638 ret = byt_set_soc_data(vg, soc_data);1627 ret = byt_set_soc_data(vg, soc_data);
1639 if (ret) {1628 if (ret) {
1640 dev_err(&pdev->dev, "failed to set soc data\n");1629 dev_err(dev, "failed to set soc data\n");
1641 return ret;1630 return ret;
1642 }1631 }
1643 1632
1644 vg->pctl_desc = byt_pinctrl_desc;1633 vg->pctldesc = byt_pinctrl_desc;
1645 vg->pctl_desc.name = dev_name(&pdev->dev);1634 vg->pctldesc.name = dev_name(dev);
1646 vg->pctl_desc.pins = vg->soc_data->pins;1635 vg->pctldesc.pins = vg->soc->pins;
1647 vg->pctl_desc.npins = vg->soc_data->npins;1636 vg->pctldesc.npins = vg->soc->npins;
1648 1637
1649 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg);1638 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1650 if (IS_ERR(vg->pctl_dev)) {1639 if (IS_ERR(vg->pctldev)) {
1651 dev_err(&pdev->dev, "failed to register pinctrl driver\n");1640 dev_err(dev, "failed to register pinctrl driver\n");
1652 return PTR_ERR(vg->pctl_dev);1641 return PTR_ERR(vg->pctldev);
1653 }1642 }
1654 1643
1655 ret = byt_gpio_probe(vg);1644 ret = byt_gpio_probe(vg);
@@ -1657,7 +1646,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev) · 1 unmodified line
1657 return ret;1646 return ret;
1658 1647
1659 platform_set_drvdata(pdev, vg);1648 platform_set_drvdata(pdev, vg);
1660 pm_runtime_enable(&pdev->dev);1649 pm_runtime_enable(dev);
1661 1650
1662 return 0;1651 return 0;
1663}1652}
@@ -1665,30 +1654,30 @@ static int byt_pinctrl_probe(struct platform_device *pdev) · 1 unmodified line
1665#ifdef CONFIG_PM_SLEEP1654#ifdef CONFIG_PM_SLEEP
1666static int byt_gpio_suspend(struct device *dev)1655static int byt_gpio_suspend(struct device *dev)
1667{1656{
1668 struct byt_gpio *vg = dev_get_drvdata(dev);1657 struct intel_pinctrl *vg = dev_get_drvdata(dev);
1669 unsigned long flags;1658 unsigned long flags;
1670 int i;1659 int i;
1671 1660
1672 raw_spin_lock_irqsave(&byt_lock, flags);1661 raw_spin_lock_irqsave(&byt_lock, flags);
1673 1662
1674 for (i = 0; i < vg->soc_data->npins; i++) {1663 for (i = 0; i < vg->soc->npins; i++) {
1675 void __iomem *reg;1664 void __iomem *reg;
1676 u32 value;1665 u32 value;
1677 unsigned int pin = vg->soc_data->pins[i].number;1666 unsigned int pin = vg->soc->pins[i].number;
1678 1667
1679 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);1668 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1680 if (!reg) {1669 if (!reg) {
1681 dev_warn(&vg->pdev->dev,1670 dev_warn(vg->dev,
1682 "Pin %i: could not retrieve conf0 register\n",1671 "Pin %i: could not retrieve conf0 register\n",
1683 i);1672 i);
1684 continue;1673 continue;
1685 }1674 }
1686 value = readl(reg) & BYT_CONF0_RESTORE_MASK;1675 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1687 vg->saved_context[i].conf0 = value;1676 vg->context.pads[i].conf0 = value;
1688 1677
1689 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);1678 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1690 value = readl(reg) & BYT_VAL_RESTORE_MASK;1679 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1691 vg->saved_context[i].val = value;1680 vg->context.pads[i].val = value;
1692 }1681 }
1693 1682
1694 raw_spin_unlock_irqrestore(&byt_lock, flags);1683 raw_spin_unlock_irqrestore(&byt_lock, flags);
@@ -1697,29 +1686,29 @@ static int byt_gpio_suspend(struct device *dev) · 2 unmodified lines
1697 1686
1698static int byt_gpio_resume(struct device *dev)1687static int byt_gpio_resume(struct device *dev)
1699{1688{
1700 struct byt_gpio *vg = dev_get_drvdata(dev);1689 struct intel_pinctrl *vg = dev_get_drvdata(dev);
1701 unsigned long flags;1690 unsigned long flags;
1702 int i;1691 int i;
1703 1692
1704 raw_spin_lock_irqsave(&byt_lock, flags);1693 raw_spin_lock_irqsave(&byt_lock, flags);
1705 1694
1706 for (i = 0; i < vg->soc_data->npins; i++) {1695 for (i = 0; i < vg->soc->npins; i++) {
1707 void __iomem *reg;1696 void __iomem *reg;
1708 u32 value;1697 u32 value;
1709 unsigned int pin = vg->soc_data->pins[i].number;1698 unsigned int pin = vg->soc->pins[i].number;
1710 1699
1711 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);1700 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1712 if (!reg) {1701 if (!reg) {
1713 dev_warn(&vg->pdev->dev,1702 dev_warn(vg->dev,
1714 "Pin %i: could not retrieve conf0 register\n",1703 "Pin %i: could not retrieve conf0 register\n",
1715 i);1704 i);
1716 continue;1705 continue;
1717 }1706 }
1718 value = readl(reg);1707 value = readl(reg);
1719 if ((value & BYT_CONF0_RESTORE_MASK) !=1708 if ((value & BYT_CONF0_RESTORE_MASK) !=
1720 vg->saved_context[i].conf0) {1709 vg->context.pads[i].conf0) {
1721 value &= ~BYT_CONF0_RESTORE_MASK;1710 value &= ~BYT_CONF0_RESTORE_MASK;
1722 value |= vg->saved_context[i].conf0;1711 value |= vg->context.pads[i].conf0;
1723 writel(value, reg);1712 writel(value, reg);
1724 dev_info(dev, "restored pin %d conf0 %#08x", i, value);1713 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1725 }1714 }
@@ -1727,11 +1716,11 @@ static int byt_gpio_resume(struct device *dev) · 1 unmodified line
1727 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);1716 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1728 value = readl(reg);1717 value = readl(reg);
1729 if ((value & BYT_VAL_RESTORE_MASK) !=1718 if ((value & BYT_VAL_RESTORE_MASK) !=
1730 vg->saved_context[i].val) {1719 vg->context.pads[i].val) {
1731 u32 v;1720 u32 v;
1732 1721
1733 v = value & ~BYT_VAL_RESTORE_MASK;1722 v = value & ~BYT_VAL_RESTORE_MASK;
1734 v |= vg->saved_context[i].val;1723 v |= vg->context.pads[i].val;
1735 if (v != value) {1724 if (v != value) {
1736 writel(v, reg);1725 writel(v, reg);
1737 dev_dbg(dev, "restored pin %d val %#08x\n",1726 dev_dbg(dev, "restored pin %d val %#08x\n",
drivers/pinctrl/intel/pinctrl-cherryview.c+4−1
@@ -1289,7 +1289,10 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) · 1288 unmodified lines
1289 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;1289 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1290 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;1290 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1291 1291
1292 return direction != CHV_PADCTRL0_GPIOCFG_GPO;1292 if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1293 return GPIO_LINE_DIRECTION_OUT;
1294
1295 return GPIO_LINE_DIRECTION_IN;
1293}1296}
1294 1297
1295static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)1298static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
drivers/pinctrl/intel/pinctrl-intel.c+40−61
@@ -8,8 +8,8 @@ · 7 unmodified lines
8 */8 */
9 9
10#include <linux/acpi.h>10#include <linux/acpi.h>
11#include <linux/interrupt.h>
12#include <linux/gpio/driver.h>11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/log2.h>13#include <linux/log2.h>
14#include <linux/module.h>14#include <linux/module.h>
15#include <linux/platform_device.h>15#include <linux/platform_device.h>
@@ -85,39 +85,6 @@ struct intel_community_context { · 69 unmodified lines
85 u32 *hostown;85 u32 *hostown;
86};86};
87 87
88struct intel_pinctrl_context {
89 struct intel_pad_context *pads;
90 struct intel_community_context *communities;
91};
92
93/**
94 * struct intel_pinctrl - Intel pinctrl private structure
95 * @dev: Pointer to the device structure
96 * @lock: Lock to serialize register access
97 * @pctldesc: Pin controller description
98 * @pctldev: Pointer to the pin controller device
99 * @chip: GPIO chip in this pin controller
100 * @irqchip: IRQ chip in this pin controller
101 * @soc: SoC/PCH specific pin configuration data
102 * @communities: All communities in this pin controller
103 * @ncommunities: Number of communities in this pin controller
104 * @context: Configuration saved over system sleep
105 * @irq: pinctrl/GPIO chip irq number
106 */
107struct intel_pinctrl {
108 struct device *dev;
109 raw_spinlock_t lock;
110 struct pinctrl_desc pctldesc;
111 struct pinctrl_dev *pctldev;
112 struct gpio_chip chip;
113 struct irq_chip irqchip;
114 const struct intel_pinctrl_soc_data *soc;
115 struct intel_community *communities;
116 size_t ncommunities;
117 struct intel_pinctrl_context context;
118 int irq;
119};
120
121#define pin_to_padno(c, p) ((p) - (c)->pin_base)88#define pin_to_padno(c, p) ((p) - (c)->pin_base)
122#define padgroup_offset(g, p) ((p) - (g)->base)89#define padgroup_offset(g, p) ((p) - (g)->base)
123 90
@@ -944,7 +911,10 @@ static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) · 820 unmodified lines
944 if (padcfg0 & PADCFG0_PMODE_MASK)911 if (padcfg0 & PADCFG0_PMODE_MASK)
945 return -EINVAL;912 return -EINVAL;
946 913
947 return !!(padcfg0 & PADCFG0_GPIOTXDIS);914 if (padcfg0 & PADCFG0_GPIOTXDIS)
915 return GPIO_LINE_DIRECTION_IN;
916
917 return GPIO_LINE_DIRECTION_OUT;
948}918}
949 919
950static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)920static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
@@ -1160,8 +1130,8 @@ static irqreturn_t intel_gpio_irq(int irq, void *data) · 209 unmodified lines
1160 return ret;1130 return ret;
1161}1131}
1162 1132
1163static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,1133static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1164 const struct intel_community *community)1134 const struct intel_community *community)
1165{1135{
1166 int ret = 0, i;1136 int ret = 0, i;
1167 1137
@@ -1181,6 +1151,24 @@ static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, · 13 unmodified lines
1181 return ret;1151 return ret;
1182}1152}
1183 1153
1154static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1155{
1156 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1157 int ret, i;
1158
1159 for (i = 0; i < pctrl->ncommunities; i++) {
1160 struct intel_community *community = &pctrl->communities[i];
1161
1162 ret = intel_gpio_add_community_ranges(pctrl, community);
1163 if (ret) {
1164 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1165 return ret;
1166 }
1167 }
1168
1169 return 0;
1170}
1171
1184static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)1172static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1185{1173{
1186 const struct intel_community *community;1174 const struct intel_community *community;
@@ -1205,7 +1193,8 @@ static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) · 18 unmodified lines
1205 1193
1206static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)1194static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1207{1195{
1208 int ret, i;1196 int ret;
1197 struct gpio_irq_chip *girq;
1209 1198
1210 pctrl->chip = intel_gpio_chip;1199 pctrl->chip = intel_gpio_chip;
1211 1200
@@ -1214,6 +1203,7 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) · 2 unmodified lines
1214 pctrl->chip.label = dev_name(pctrl->dev);1203 pctrl->chip.label = dev_name(pctrl->dev);
1215 pctrl->chip.parent = pctrl->dev;1204 pctrl->chip.parent = pctrl->dev;
1216 pctrl->chip.base = -1;1205 pctrl->chip.base = -1;
1206 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1217 pctrl->irq = irq;1207 pctrl->irq = irq;
1218 1208
1219 /* Setup IRQ chip */1209 /* Setup IRQ chip */
@@ -1225,26 +1215,9 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) · 5 unmodified lines
1225 pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;1215 pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
1226 pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;1216 pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
1227 1217
1228 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1229 if (ret) {
1230 dev_err(pctrl->dev, "failed to register gpiochip\n");
1231 return ret;
1232 }
1233
1234 for (i = 0; i < pctrl->ncommunities; i++) {
1235 struct intel_community *community = &pctrl->communities[i];
1236
1237 ret = intel_gpio_add_pin_ranges(pctrl, community);
1238 if (ret) {
1239 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1240 return ret;
1241 }
1242 }
1243
1244 /*1218 /*
1245 * We need to request the interrupt here (instead of providing chip1219 * On some platforms several GPIO controllers share the same interrupt
1246 * to the irq directly) because on some platforms several GPIO1220 * line.
1247 * controllers share the same interrupt line.
1248 */1221 */
1249 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,1222 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1250 IRQF_SHARED | IRQF_NO_THREAD,1223 IRQF_SHARED | IRQF_NO_THREAD,
@@ -1254,14 +1227,20 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) · 3 unmodified lines
1254 return ret;1227 return ret;
1255 }1228 }
1256 1229
1257 ret = gpiochip_irqchip_add(&pctrl->chip, &pctrl->irqchip, 0,1230 girq = &pctrl->chip.irq;
1258 handle_bad_irq, IRQ_TYPE_NONE);1231 girq->chip = &pctrl->irqchip;
1232 /* This will let us handle the IRQ in the driver */
1233 girq->parent_handler = NULL;
1234 girq->num_parents = 0;
1235 girq->default_type = IRQ_TYPE_NONE;
1236 girq->handler = handle_bad_irq;
1237
1238 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1259 if (ret) {1239 if (ret) {
1260 dev_err(pctrl->dev, "failed to add irqchip\n");1240 dev_err(pctrl->dev, "failed to register gpiochip\n");
1261 return ret;1241 return ret;
1262 }1242 }
1263 1243
1264 gpiochip_set_chained_irqchip(&pctrl->chip, &pctrl->irqchip, irq, NULL);
1265 return 0;1244 return 0;
1266}1245}
1267 1246
drivers/pinctrl/intel/pinctrl-intel.h+44−0
@@ -10,7 +10,10 @@ · 9 unmodified lines
10#ifndef PINCTRL_INTEL_H10#ifndef PINCTRL_INTEL_H
11#define PINCTRL_INTEL_H11#define PINCTRL_INTEL_H
12 12
13#include <linux/gpio/driver.h>
14#include <linux/irq.h>
13#include <linux/pm.h>15#include <linux/pm.h>
16#include <linux/spinlock_types.h>
14 17
15struct pinctrl_pin_desc;18struct pinctrl_pin_desc;
16struct platform_device;19struct platform_device;
@@ -174,6 +177,47 @@ struct intel_pinctrl_soc_data { · 157 unmodified lines
174 size_t ncommunities;177 size_t ncommunities;
175};178};
176 179
180struct intel_pad_context;
181struct intel_community_context;
182
183/**
184 * struct intel_pinctrl_context - context to be saved during suspend-resume
185 * @pads: Opaque context per pad (driver dependent)
186 * @communities: Opaque context per community (driver dependent)
187 */
188struct intel_pinctrl_context {
189 struct intel_pad_context *pads;
190 struct intel_community_context *communities;
191};
192
193/**
194 * struct intel_pinctrl - Intel pinctrl private structure
195 * @dev: Pointer to the device structure
196 * @lock: Lock to serialize register access
197 * @pctldesc: Pin controller description
198 * @pctldev: Pointer to the pin controller device
199 * @chip: GPIO chip in this pin controller
200 * @irqchip: IRQ chip in this pin controller
201 * @soc: SoC/PCH specific pin configuration data
202 * @communities: All communities in this pin controller
203 * @ncommunities: Number of communities in this pin controller
204 * @context: Configuration saved over system sleep
205 * @irq: pinctrl/GPIO chip irq number
206 */
207struct intel_pinctrl {
208 struct device *dev;
209 raw_spinlock_t lock;
210 struct pinctrl_desc pctldesc;
211 struct pinctrl_dev *pctldev;
212 struct gpio_chip chip;
213 struct irq_chip irqchip;
214 const struct intel_pinctrl_soc_data *soc;
215 struct intel_community *communities;
216 size_t ncommunities;
217 struct intel_pinctrl_context context;
218 int irq;
219};
220
177int intel_pinctrl_probe_by_hid(struct platform_device *pdev);221int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
178int intel_pinctrl_probe_by_uid(struct platform_device *pdev);222int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
179 223
drivers/pinctrl/intel/pinctrl-lynxpoint.c+975−0
@@ -0,0 +1,975 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Lynxpoint PCH pinctrl/GPIO driver
4 *
5 * Copyright (c) 2012, 2019, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Andy Shevchenko <andriy.shevchenko@linux.intel.com>
8 */
9
10#include <linux/acpi.h>
11#include <linux/bitops.h>
12#include <linux/gpio/driver.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/slab.h>
20#include <linux/types.h>
21
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinconf-generic.h>
26
27#include "pinctrl-intel.h"
28
29#define COMMUNITY(p, n) \
30 { \
31 .pin_base = (p), \
32 .npins = (n), \
33 }
34
35static const struct pinctrl_pin_desc lptlp_pins[] = {
36 PINCTRL_PIN(0, "GP0_UART1_RXD"),
37 PINCTRL_PIN(1, "GP1_UART1_TXD"),
38 PINCTRL_PIN(2, "GP2_UART1_RTSB"),
39 PINCTRL_PIN(3, "GP3_UART1_CTSB"),
40 PINCTRL_PIN(4, "GP4_I2C0_SDA"),
41 PINCTRL_PIN(5, "GP5_I2C0_SCL"),
42 PINCTRL_PIN(6, "GP6_I2C1_SDA"),
43 PINCTRL_PIN(7, "GP7_I2C1_SCL"),
44 PINCTRL_PIN(8, "GP8"),
45 PINCTRL_PIN(9, "GP9"),
46 PINCTRL_PIN(10, "GP10"),
47 PINCTRL_PIN(11, "GP11_SMBALERTB"),
48 PINCTRL_PIN(12, "GP12_LANPHYPC"),
49 PINCTRL_PIN(13, "GP13"),
50 PINCTRL_PIN(14, "GP14"),
51 PINCTRL_PIN(15, "GP15"),
52 PINCTRL_PIN(16, "GP16_MGPIO9"),
53 PINCTRL_PIN(17, "GP17_MGPIO10"),
54 PINCTRL_PIN(18, "GP18_SRC0CLKRQB"),
55 PINCTRL_PIN(19, "GP19_SRC1CLKRQB"),
56 PINCTRL_PIN(20, "GP20_SRC2CLKRQB"),
57 PINCTRL_PIN(21, "GP21_SRC3CLKRQB"),
58 PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"),
59 PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"),
60 PINCTRL_PIN(24, "GP24_MGPIO0"),
61 PINCTRL_PIN(25, "GP25_USBWAKEOUTB"),
62 PINCTRL_PIN(26, "GP26_MGPIO5"),
63 PINCTRL_PIN(27, "GP27_MGPIO6"),
64 PINCTRL_PIN(28, "GP28_MGPIO7"),
65 PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"),
66 PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"),
67 PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"),
68 PINCTRL_PIN(32, "GP32_CLKRUNB"),
69 PINCTRL_PIN(33, "GP33_DEVSLP0"),
70 PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"),
71 PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"),
72 PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"),
73 PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"),
74 PINCTRL_PIN(38, "GP38_DEVSLP1"),
75 PINCTRL_PIN(39, "GP39_DEVSLP2"),
76 PINCTRL_PIN(40, "GP40_OC0B"),
77 PINCTRL_PIN(41, "GP41_OC1B"),
78 PINCTRL_PIN(42, "GP42_OC2B"),
79 PINCTRL_PIN(43, "GP43_OC3B"),
80 PINCTRL_PIN(44, "GP44"),
81 PINCTRL_PIN(45, "GP45_TMS2"),
82 PINCTRL_PIN(46, "GP46_TDO2"),
83 PINCTRL_PIN(47, "GP47"),
84 PINCTRL_PIN(48, "GP48"),
85 PINCTRL_PIN(49, "GP49"),
86 PINCTRL_PIN(50, "GP50"),
87 PINCTRL_PIN(51, "GP51_GSXDOUT"),
88 PINCTRL_PIN(52, "GP52_GSXSLOAD"),
89 PINCTRL_PIN(53, "GP53_GSXDIN"),
90 PINCTRL_PIN(54, "GP54_GSXSRESETB"),
91 PINCTRL_PIN(55, "GP55_GSXCLK"),
92 PINCTRL_PIN(56, "GP56"),
93 PINCTRL_PIN(57, "GP57"),
94 PINCTRL_PIN(58, "GP58"),
95 PINCTRL_PIN(59, "GP59"),
96 PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"),
97 PINCTRL_PIN(61, "GP61_SUS_STATB"),
98 PINCTRL_PIN(62, "GP62_SUSCLK"),
99 PINCTRL_PIN(63, "GP63_SLP_S5B"),
100 PINCTRL_PIN(64, "GP64_SDIO_CLK"),
101 PINCTRL_PIN(65, "GP65_SDIO_CMD"),
102 PINCTRL_PIN(66, "GP66_SDIO_D0"),
103 PINCTRL_PIN(67, "GP67_SDIO_D1"),
104 PINCTRL_PIN(68, "GP68_SDIO_D2"),
105 PINCTRL_PIN(69, "GP69_SDIO_D3"),
106 PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"),
107 PINCTRL_PIN(71, "GP71_MPHYPC"),
108 PINCTRL_PIN(72, "GP72_BATLOWB"),
109 PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"),
110 PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"),
111 PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"),
112 PINCTRL_PIN(76, "GP76_BMBUSYB"),
113 PINCTRL_PIN(77, "GP77_PIRQAB"),
114 PINCTRL_PIN(78, "GP78_PIRQBB"),
115 PINCTRL_PIN(79, "GP79_PIRQCB"),
116 PINCTRL_PIN(80, "GP80_PIRQDB"),
117 PINCTRL_PIN(81, "GP81_SPKR"),
118 PINCTRL_PIN(82, "GP82_RCINB"),
119 PINCTRL_PIN(83, "GP83_GSPI0_CSB"),
120 PINCTRL_PIN(84, "GP84_GSPI0_CLK"),
121 PINCTRL_PIN(85, "GP85_GSPI0_MISO"),
122 PINCTRL_PIN(86, "GP86_GSPI0_MOSI"),
123 PINCTRL_PIN(87, "GP87_GSPI1_CSB"),
124 PINCTRL_PIN(88, "GP88_GSPI1_CLK"),
125 PINCTRL_PIN(89, "GP89_GSPI1_MISO"),
126 PINCTRL_PIN(90, "GP90_GSPI1_MOSI"),
127 PINCTRL_PIN(91, "GP91_UART0_RXD"),
128 PINCTRL_PIN(92, "GP92_UART0_TXD"),
129 PINCTRL_PIN(93, "GP93_UART0_RTSB"),
130 PINCTRL_PIN(94, "GP94_UART0_CTSB"),
131};
132
133static const struct intel_community lptlp_communities[] = {
134 COMMUNITY(0, 95),
135};
136
137static const struct intel_pinctrl_soc_data lptlp_soc_data = {
138 .pins = lptlp_pins,
139 .npins = ARRAY_SIZE(lptlp_pins),
140 .communities = lptlp_communities,
141 .ncommunities = ARRAY_SIZE(lptlp_communities),
142};
143
144/* LynxPoint chipset has support for 95 GPIO pins */
145
146#define LP_NUM_GPIO 95
147
148/* Bitmapped register offsets */
149#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
150#define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */
151#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
152#define LP_INT_STAT 0x80
153#define LP_INT_ENABLE 0x90
154
155/* Each pin has two 32 bit config registers, starting at 0x100 */
156#define LP_CONFIG1 0x100
157#define LP_CONFIG2 0x104
158
159/* LP_CONFIG1 reg bits */
160#define OUT_LVL_BIT BIT(31)
161#define IN_LVL_BIT BIT(30)
162#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
163#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
164#define DIR_BIT BIT(2) /* 0: Output, 1: Input */
165#define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */
166#define USE_SEL_NATIVE (0 << 0)
167#define USE_SEL_GPIO (1 << 0)
168
169/* LP_CONFIG2 reg bits */
170#define GPINDIS_BIT BIT(2) /* disable input sensing */
171#define GPIWP_MASK GENMASK(1, 0) /* weak pull options */
172#define GPIWP_NONE 0 /* none */
173#define GPIWP_DOWN 1 /* weak pull down */
174#define GPIWP_UP 2 /* weak pull up */
175
176/*
177 * Lynxpoint gpios are controlled through both bitmapped registers and
178 * per gpio specific registers. The bitmapped registers are in chunks of
179 * 3 x 32bit registers to cover all 95 GPIOs
180 *
181 * per gpio specific registers consist of two 32bit registers per gpio
182 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of
183 * 190 config registers.
184 *
185 * A simplified view of the register layout look like this:
186 *
187 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
188 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
189 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
190 * ...
191 * LP_INT_ENABLE[31:0] ...
192 * LP_INT_ENABLE[63:32] ...
193 * LP_INT_ENABLE[94:64] ...
194 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
195 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
196 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
197 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
198 * LP2_CONFIG1 (gpio 2) ...
199 * LP2_CONFIG2 (gpio 2) ...
200 * ...
201 * LP94_CONFIG1 (gpio 94) ...
202 * LP94_CONFIG2 (gpio 94) ...
203 *
204 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
205 */
206
207static struct intel_community *lp_get_community(struct intel_pinctrl *lg,
208 unsigned int pin)
209{
210 struct intel_community *comm;
211 int i;
212
213 for (i = 0; i < lg->ncommunities; i++) {
214 comm = &lg->communities[i];
215 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
216 return comm;
217 }
218
219 return NULL;
220}
221
222static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset,
223 int reg)
224{
225 struct intel_pinctrl *lg = gpiochip_get_data(chip);
226 struct intel_community *comm;
227 int reg_offset;
228
229 comm = lp_get_community(lg, offset);
230 if (!comm)
231 return NULL;
232
233 offset -= comm->pin_base;
234
235 if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
236 /* per gpio specific config registers */
237 reg_offset = offset * 8;
238 else
239 /* bitmapped registers */
240 reg_offset = (offset / 32) * 4;
241
242 return comm->regs + reg_offset + reg;
243}
244
245static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin)
246{
247 void __iomem *acpi_use;
248
249 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED);
250 if (!acpi_use)
251 return true;
252
253 return !(ioread32(acpi_use) & BIT(pin % 32));
254}
255
256static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset)
257{
258 void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC);
259 u32 value;
260
261 value = ioread32(ioxapic_use);
262
263 if (offset >= 8 && offset <= 10)
264 return !!(value & BIT(offset - 8 + 0));
265 if (offset >= 13 && offset <= 14)
266 return !!(value & BIT(offset - 13 + 3));
267 if (offset >= 45 && offset <= 55)
268 return !!(value & BIT(offset - 45 + 5));
269
270 return false;
271}
272
273static int lp_get_groups_count(struct pinctrl_dev *pctldev)
274{
275 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
276
277 return lg->soc->ngroups;
278}
279
280static const char *lp_get_group_name(struct pinctrl_dev *pctldev,
281 unsigned int selector)
282{
283 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
284
285 return lg->soc->groups[selector].name;
286}
287
288static int lp_get_group_pins(struct pinctrl_dev *pctldev,
289 unsigned int selector,
290 const unsigned int **pins,
291 unsigned int *num_pins)
292{
293 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
294
295 *pins = lg->soc->groups[selector].pins;
296 *num_pins = lg->soc->groups[selector].npins;
297
298 return 0;
299}
300
301static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
302 unsigned int pin)
303{
304 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
305 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
306 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
307 u32 value, mode;
308
309 value = ioread32(reg);
310
311 mode = value & USE_SEL_MASK;
312 if (mode == USE_SEL_GPIO)
313 seq_puts(s, "GPIO ");
314 else
315 seq_printf(s, "mode %d ", mode);
316
317 seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2));
318
319 if (lp_gpio_acpi_use(lg, pin))
320 seq_puts(s, " [ACPI]");
321}
322
323static const struct pinctrl_ops lptlp_pinctrl_ops = {
324 .get_groups_count = lp_get_groups_count,
325 .get_group_name = lp_get_group_name,
326 .get_group_pins = lp_get_group_pins,
327 .pin_dbg_show = lp_pin_dbg_show,
328};
329
330static int lp_get_functions_count(struct pinctrl_dev *pctldev)
331{
332 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
333
334 return lg->soc->nfunctions;
335}
336
337static const char *lp_get_function_name(struct pinctrl_dev *pctldev,
338 unsigned int selector)
339{
340 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
341
342 return lg->soc->functions[selector].name;
343}
344
345static int lp_get_function_groups(struct pinctrl_dev *pctldev,
346 unsigned int selector,
347 const char * const **groups,
348 unsigned int *num_groups)
349{
350 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
351
352 *groups = lg->soc->functions[selector].groups;
353 *num_groups = lg->soc->functions[selector].ngroups;
354
355 return 0;
356}
357
358static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
359 unsigned int function, unsigned int group)
360{
361 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
362 const struct intel_pingroup *grp = &lg->soc->groups[group];
363 unsigned long flags;
364 int i;
365
366 raw_spin_lock_irqsave(&lg->lock, flags);
367
368 /* Now enable the mux setting for each pin in the group */
369 for (i = 0; i < grp->npins; i++) {
370 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1);
371 u32 value;
372
373 value = ioread32(reg);
374
375 value &= ~USE_SEL_MASK;
376 if (grp->modes)
377 value |= grp->modes[i];
378 else
379 value |= grp->mode;
380
381 iowrite32(value, reg);
382 }
383
384 raw_spin_unlock_irqrestore(&lg->lock, flags);
385
386 return 0;
387}
388
389static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
390 struct pinctrl_gpio_range *range,
391 unsigned int pin)
392{
393 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
394 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
395 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
396 unsigned long flags;
397 u32 value;
398
399 pm_runtime_get(lg->dev);
400
401 raw_spin_lock_irqsave(&lg->lock, flags);
402
403 /*
404 * Reconfigure pin to GPIO mode if needed and issue a warning,
405 * since we expect firmware to configure it properly.
406 */
407 value = ioread32(reg);
408 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) {
409 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg);
410 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin);
411 }
412
413 /* Enable input sensing */
414 iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2);
415
416 raw_spin_unlock_irqrestore(&lg->lock, flags);
417
418 return 0;
419}
420
421static void lp_gpio_disable_free(struct pinctrl_dev *pctldev,
422 struct pinctrl_gpio_range *range,
423 unsigned int pin)
424{
425 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
426 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
427 unsigned long flags;
428
429 raw_spin_lock_irqsave(&lg->lock, flags);
430
431 /* Disable input sensing */
432 iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2);
433
434 raw_spin_unlock_irqrestore(&lg->lock, flags);
435
436 pm_runtime_put(lg->dev);
437}
438
439static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
440 struct pinctrl_gpio_range *range,
441 unsigned int pin, bool input)
442{
443 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
444 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
445 unsigned long flags;
446 u32 value;
447
448 raw_spin_lock_irqsave(&lg->lock, flags);
449
450 value = ioread32(reg);
451 value &= ~DIR_BIT;
452 if (input) {
453 value |= DIR_BIT;
454 } else {
455 /*
456 * Before making any direction modifications, do a check if GPIO
457 * is set for direct IRQ. On Lynxpoint, setting GPIO to output
458 * does not make sense, so let's at least warn the caller before
459 * they shoot themselves in the foot.
460 */
461 WARN(lp_gpio_ioxapic_use(&lg->chip, pin),
462 "Potential Error: Setting GPIO to output with IOxAPIC redirection");
463 }
464 iowrite32(value, reg);
465
466 raw_spin_unlock_irqrestore(&lg->lock, flags);
467
468 return 0;
469}
470
471static const struct pinmux_ops lptlp_pinmux_ops = {
472 .get_functions_count = lp_get_functions_count,
473 .get_function_name = lp_get_function_name,
474 .get_function_groups = lp_get_function_groups,
475 .set_mux = lp_pinmux_set_mux,
476 .gpio_request_enable = lp_gpio_request_enable,
477 .gpio_disable_free = lp_gpio_disable_free,
478 .gpio_set_direction = lp_gpio_set_direction,
479};
480
481static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
482 unsigned long *config)
483{
484 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
485 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
486 enum pin_config_param param = pinconf_to_config_param(*config);
487 unsigned long flags;
488 u32 value, pull;
489 u16 arg = 0;
490
491 raw_spin_lock_irqsave(&lg->lock, flags);
492 value = ioread32(conf2);
493 raw_spin_unlock_irqrestore(&lg->lock, flags);
494
495 pull = value & GPIWP_MASK;
496
497 switch (param) {
498 case PIN_CONFIG_BIAS_DISABLE:
499 if (pull)
500 return -EINVAL;
501 break;
502 case PIN_CONFIG_BIAS_PULL_DOWN:
503 if (pull != GPIWP_DOWN)
504 return -EINVAL;
505
506 arg = 1;
507 break;
508 case PIN_CONFIG_BIAS_PULL_UP:
509 if (pull != GPIWP_UP)
510 return -EINVAL;
511
512 arg = 1;
513 break;
514 default:
515 return -ENOTSUPP;
516 }
517
518 *config = pinconf_to_config_packed(param, arg);
519
520 return 0;
521}
522
523static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
524 unsigned long *configs, unsigned int num_configs)
525{
526 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
527 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
528 enum pin_config_param param;
529 unsigned long flags;
530 int i, ret = 0;
531 u32 value;
532
533 raw_spin_lock_irqsave(&lg->lock, flags);
534
535 value = ioread32(conf2);
536
537 for (i = 0; i < num_configs; i++) {
538 param = pinconf_to_config_param(configs[i]);
539
540 switch (param) {
541 case PIN_CONFIG_BIAS_DISABLE:
542 value &= ~GPIWP_MASK;
543 break;
544 case PIN_CONFIG_BIAS_PULL_DOWN:
545 value &= ~GPIWP_MASK;
546 value |= GPIWP_DOWN;
547 break;
548 case PIN_CONFIG_BIAS_PULL_UP:
549 value &= ~GPIWP_MASK;
550 value |= GPIWP_UP;
551 break;
552 default:
553 ret = -ENOTSUPP;
554 }
555
556 if (ret)
557 break;
558 }
559
560 if (!ret)
561 iowrite32(value, conf2);
562
563 raw_spin_unlock_irqrestore(&lg->lock, flags);
564
565 return ret;
566}
567
568static const struct pinconf_ops lptlp_pinconf_ops = {
569 .is_generic = true,
570 .pin_config_get = lp_pin_config_get,
571 .pin_config_set = lp_pin_config_set,
572};
573
574static const struct pinctrl_desc lptlp_pinctrl_desc = {
575 .pctlops = &lptlp_pinctrl_ops,
576 .pmxops = &lptlp_pinmux_ops,
577 .confops = &lptlp_pinconf_ops,
578 .owner = THIS_MODULE,
579};
580
581static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset)
582{
583 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
584 return !!(ioread32(reg) & IN_LVL_BIT);
585}
586
587static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
588{
589 struct intel_pinctrl *lg = gpiochip_get_data(chip);
590 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
591 unsigned long flags;
592
593 raw_spin_lock_irqsave(&lg->lock, flags);
594
595 if (value)
596 iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
597 else
598 iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
599
600 raw_spin_unlock_irqrestore(&lg->lock, flags);
601}
602
603static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
604{
605 return pinctrl_gpio_direction_input(chip->base + offset);
606}
607
608static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
609 int value)
610{
611 lp_gpio_set(chip, offset, value);
612
613 return pinctrl_gpio_direction_output(chip->base + offset);
614}
615
616static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
617{
618 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
619
620 if (ioread32(reg) & DIR_BIT)
621 return GPIO_LINE_DIRECTION_IN;
622
623 return GPIO_LINE_DIRECTION_OUT;
624}
625
626static void lp_gpio_irq_handler(struct irq_desc *desc)
627{
628 struct irq_data *data = irq_desc_get_irq_data(desc);
629 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
630 struct intel_pinctrl *lg = gpiochip_get_data(gc);
631 struct irq_chip *chip = irq_data_get_irq_chip(data);
632 void __iomem *reg, *ena;
633 unsigned long pending;
634 u32 base, pin;
635
636 /* check from GPIO controller which pin triggered the interrupt */
637 for (base = 0; base < lg->chip.ngpio; base += 32) {
638 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
639 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
640
641 /* Only interrupts that are enabled */
642 pending = ioread32(reg) & ioread32(ena);
643
644 for_each_set_bit(pin, &pending, 32) {
645 unsigned int irq;
646
647 irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
648 generic_handle_irq(irq);
649 }
650 }
651 chip->irq_eoi(data);
652}
653
654static void lp_irq_ack(struct irq_data *d)
655{
656 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
657 struct intel_pinctrl *lg = gpiochip_get_data(gc);
658 u32 hwirq = irqd_to_hwirq(d);
659 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
660 unsigned long flags;
661
662 raw_spin_lock_irqsave(&lg->lock, flags);
663 iowrite32(BIT(hwirq % 32), reg);
664 raw_spin_unlock_irqrestore(&lg->lock, flags);
665}
666
667static void lp_irq_unmask(struct irq_data *d)
668{
669}
670
671static void lp_irq_mask(struct irq_data *d)
672{
673}
674
675static void lp_irq_enable(struct irq_data *d)
676{
677 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
678 struct intel_pinctrl *lg = gpiochip_get_data(gc);
679 u32 hwirq = irqd_to_hwirq(d);
680 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
681 unsigned long flags;
682
683 raw_spin_lock_irqsave(&lg->lock, flags);
684 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
685 raw_spin_unlock_irqrestore(&lg->lock, flags);
686}
687
688static void lp_irq_disable(struct irq_data *d)
689{
690 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
691 struct intel_pinctrl *lg = gpiochip_get_data(gc);
692 u32 hwirq = irqd_to_hwirq(d);
693 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
694 unsigned long flags;
695
696 raw_spin_lock_irqsave(&lg->lock, flags);
697 iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
698 raw_spin_unlock_irqrestore(&lg->lock, flags);
699}
700
701static int lp_irq_set_type(struct irq_data *d, unsigned int type)
702{
703 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
704 struct intel_pinctrl *lg = gpiochip_get_data(gc);
705 u32 hwirq = irqd_to_hwirq(d);
706 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
707 unsigned long flags;
708 u32 value;
709
710 if (hwirq >= lg->chip.ngpio)
711 return -EINVAL;
712
713 /* Fail if BIOS reserved pin for ACPI use */
714 if (lp_gpio_acpi_use(lg, hwirq)) {
715 dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq);
716 return -EBUSY;
717 }
718
719 raw_spin_lock_irqsave(&lg->lock, flags);
720 value = ioread32(reg);
721
722 /* set both TRIG_SEL and INV bits to 0 for rising edge */
723 if (type & IRQ_TYPE_EDGE_RISING)
724 value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
725
726 /* TRIG_SEL bit 0, INV bit 1 for falling edge */
727 if (type & IRQ_TYPE_EDGE_FALLING)
728 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
729
730 /* TRIG_SEL bit 1, INV bit 0 for level low */
731 if (type & IRQ_TYPE_LEVEL_LOW)
732 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
733
734 /* TRIG_SEL bit 1, INV bit 1 for level high */
735 if (type & IRQ_TYPE_LEVEL_HIGH)
736 value |= TRIG_SEL_BIT | INT_INV_BIT;
737
738 iowrite32(value, reg);
739
740 if (type & IRQ_TYPE_EDGE_BOTH)
741 irq_set_handler_locked(d, handle_edge_irq);
742 else if (type & IRQ_TYPE_LEVEL_MASK)
743 irq_set_handler_locked(d, handle_level_irq);
744
745 raw_spin_unlock_irqrestore(&lg->lock, flags);
746
747 return 0;
748}
749
750static struct irq_chip lp_irqchip = {
751 .name = "LP-GPIO",
752 .irq_ack = lp_irq_ack,
753 .irq_mask = lp_irq_mask,
754 .irq_unmask = lp_irq_unmask,
755 .irq_enable = lp_irq_enable,
756 .irq_disable = lp_irq_disable,
757 .irq_set_type = lp_irq_set_type,
758 .flags = IRQCHIP_SKIP_SET_WAKE,
759};
760
761static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
762{
763 struct intel_pinctrl *lg = gpiochip_get_data(chip);
764 void __iomem *reg;
765 unsigned int base;
766
767 for (base = 0; base < lg->chip.ngpio; base += 32) {
768 /* disable gpio pin interrupts */
769 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
770 iowrite32(0, reg);
771 /* Clear interrupt status register */
772 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
773 iowrite32(0xffffffff, reg);
774 }
775
776 return 0;
777}
778
779static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
780{
781 struct intel_pinctrl *lg = gpiochip_get_data(chip);
782 struct device *dev = lg->dev;
783 int ret;
784
785 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
786 if (ret)
787 dev_err(dev, "failed to add GPIO pin range\n");
788
789 return ret;
790}
791
792static int lp_gpio_probe(struct platform_device *pdev)
793{
794 const struct intel_pinctrl_soc_data *soc;
795 struct intel_pinctrl *lg;
796 struct gpio_chip *gc;
797 struct resource *io_rc, *irq_rc;
798 struct device *dev = &pdev->dev;
799 void __iomem *regs;
800 unsigned int i;
801 int ret;
802
803 soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev);
804 if (!soc)
805 return -ENODEV;
806
807 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL);
808 if (!lg)
809 return -ENOMEM;
810
811 lg->dev = dev;
812 lg->soc = soc;
813
814 lg->ncommunities = lg->soc->ncommunities;
815 lg->communities = devm_kcalloc(dev, lg->ncommunities,
816 sizeof(*lg->communities), GFP_KERNEL);
817 if (!lg->communities)
818 return -ENOMEM;
819
820 lg->pctldesc = lptlp_pinctrl_desc;
821 lg->pctldesc.name = dev_name(dev);
822 lg->pctldesc.pins = lg->soc->pins;
823 lg->pctldesc.npins = lg->soc->npins;
824
825 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg);
826 if (IS_ERR(lg->pctldev)) {
827 dev_err(dev, "failed to register pinctrl driver\n");
828 return PTR_ERR(lg->pctldev);
829 }
830
831 platform_set_drvdata(pdev, lg);
832
833 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
834 if (!io_rc) {
835 dev_err(dev, "missing IO resources\n");
836 return -EINVAL;
837 }
838
839 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc));
840 if (!regs) {
841 dev_err(dev, "failed mapping IO region %pR\n", &io_rc);
842 return -EBUSY;
843 }
844
845 for (i = 0; i < lg->soc->ncommunities; i++) {
846 struct intel_community *comm = &lg->communities[i];
847
848 *comm = lg->soc->communities[i];
849
850 comm->regs = regs;
851 comm->pad_regs = regs + 0x100;
852 }
853
854 raw_spin_lock_init(&lg->lock);
855
856 gc = &lg->chip;
857 gc->label = dev_name(dev);
858 gc->owner = THIS_MODULE;
859 gc->request = gpiochip_generic_request;
860 gc->free = gpiochip_generic_free;
861 gc->direction_input = lp_gpio_direction_input;
862 gc->direction_output = lp_gpio_direction_output;
863 gc->get = lp_gpio_get;
864 gc->set = lp_gpio_set;
865 gc->get_direction = lp_gpio_get_direction;
866 gc->base = -1;
867 gc->ngpio = LP_NUM_GPIO;
868 gc->can_sleep = false;
869 gc->add_pin_ranges = lp_gpio_add_pin_ranges;
870 gc->parent = dev;
871
872 /* set up interrupts */
873 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
874 if (irq_rc && irq_rc->start) {
875 struct gpio_irq_chip *girq;
876
877 girq = &gc->irq;
878 girq->chip = &lp_irqchip;
879 girq->init_hw = lp_gpio_irq_init_hw;
880 girq->parent_handler = lp_gpio_irq_handler;
881 girq->num_parents = 1;
882 girq->parents = devm_kcalloc(dev, girq->num_parents,
883 sizeof(*girq->parents),
884 GFP_KERNEL);
885 if (!girq->parents)
886 return -ENOMEM;
887 girq->parents[0] = (unsigned int)irq_rc->start;
888 girq->default_type = IRQ_TYPE_NONE;
889 girq->handler = handle_bad_irq;
890 }
891
892 ret = devm_gpiochip_add_data(dev, gc, lg);
893 if (ret) {
894 dev_err(dev, "failed adding lp-gpio chip\n");
895 return ret;
896 }
897
898 pm_runtime_enable(dev);
899
900 return 0;
901}
902
903static int lp_gpio_remove(struct platform_device *pdev)
904{
905 pm_runtime_disable(&pdev->dev);
906 return 0;
907}
908
909static int lp_gpio_runtime_suspend(struct device *dev)
910{
911 return 0;
912}
913
914static int lp_gpio_runtime_resume(struct device *dev)
915{
916 return 0;
917}
918
919static int lp_gpio_resume(struct device *dev)
920{
921 struct intel_pinctrl *lg = dev_get_drvdata(dev);
922 void __iomem *reg;
923 int i;
924
925 /* on some hardware suspend clears input sensing, re-enable it here */
926 for (i = 0; i < lg->chip.ngpio; i++) {
927 if (gpiochip_is_requested(&lg->chip, i) != NULL) {
928 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
929 iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg);
930 }
931 }
932 return 0;
933}
934
935static const struct dev_pm_ops lp_gpio_pm_ops = {
936 .runtime_suspend = lp_gpio_runtime_suspend,
937 .runtime_resume = lp_gpio_runtime_resume,
938 .resume = lp_gpio_resume,
939};
940
941static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
942 { "INT33C7", (kernel_ulong_t)&lptlp_soc_data },
943 { "INT3437", (kernel_ulong_t)&lptlp_soc_data },
944 { }
945};
946MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
947
948static struct platform_driver lp_gpio_driver = {
949 .probe = lp_gpio_probe,
950 .remove = lp_gpio_remove,
951 .driver = {
952 .name = "lp_gpio",
953 .pm = &lp_gpio_pm_ops,
954 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
955 },
956};
957
958static int __init lp_gpio_init(void)
959{
960 return platform_driver_register(&lp_gpio_driver);
961}
962
963static void __exit lp_gpio_exit(void)
964{
965 platform_driver_unregister(&lp_gpio_driver);
966}
967
968subsys_initcall(lp_gpio_init);
969module_exit(lp_gpio_exit);
970
971MODULE_AUTHOR("Mathias Nyman (Intel)");
972MODULE_AUTHOR("Andy Shevchenko (Intel)");
973MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver");
974MODULE_LICENSE("GPL v2");
975MODULE_ALIAS("platform:lp_gpio");
drivers/pinctrl/intel/pinctrl-sunrisepoint.c+1−0
@@ -589,6 +589,7 @@ static const struct intel_pinctrl_soc_data spth_soc_data = { · 588 unmodified lines
589 589
590static const struct acpi_device_id spt_pinctrl_acpi_match[] = {590static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
591 { "INT344B", (kernel_ulong_t)&sptlp_soc_data },591 { "INT344B", (kernel_ulong_t)&sptlp_soc_data },
592 { "INT3451", (kernel_ulong_t)&spth_soc_data },
592 { "INT345D", (kernel_ulong_t)&spth_soc_data },593 { "INT345D", (kernel_ulong_t)&spth_soc_data },
593 { }594 { }
594};595};
drivers/pinctrl/intel/pinctrl-tigerlake.c+250−297
@@ -2,7 +2,7 @@ · 1 unmodified line
2/*2/*
3 * Intel Tiger Lake PCH pinctrl/GPIO driver3 * Intel Tiger Lake PCH pinctrl/GPIO driver
4 *4 *
5 * Copyright (C) 2019, Intel Corporation5 * Copyright (C) 2019 - 2020, Intel Corporation
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 */8 */
@@ -21,15 +21,19 @@ · 12 unmodified lines
21#define TGL_GPI_IS 0x10021#define TGL_GPI_IS 0x100
22#define TGL_GPI_IE 0x12022#define TGL_GPI_IE 0x120
23 23
24#define TGL_GPP(r, s, e) \24#define TGL_NO_GPIO -1
25
26#define TGL_GPP(r, s, e, g) \
25 { \27 { \
26 .reg_num = (r), \28 .reg_num = (r), \
27 .base = (s), \29 .base = (s), \
28 .size = ((e) - (s) + 1), \30 .size = ((e) - (s) + 1), \
31 .gpio_base = (g), \
29 }32 }
30 33
31#define TGL_COMMUNITY(s, e, g) \34#define TGL_COMMUNITY(b, s, e, g) \
32 { \35 { \
36 .barno = (b), \
33 .padown_offset = TGL_PAD_OWN, \37 .padown_offset = TGL_PAD_OWN, \
34 .padcfglock_offset = TGL_PADCFGLOCK, \38 .padcfglock_offset = TGL_PADCFGLOCK, \
35 .hostown_offset = TGL_HOSTSW_OWN, \39 .hostown_offset = TGL_HOSTSW_OWN, \
@@ -42,7 +46,7 @@ · 6 unmodified lines
42 }46 }
43 47
44/* Tiger Lake-LP */48/* Tiger Lake-LP */
45static const struct pinctrl_pin_desc tgllp_community0_pins[] = {49static const struct pinctrl_pin_desc tgllp_pins[] = {
46 /* GPP_B */50 /* GPP_B */
47 PINCTRL_PIN(0, "CORE_VID_0"),51 PINCTRL_PIN(0, "CORE_VID_0"),
48 PINCTRL_PIN(1, "CORE_VID_1"),52 PINCTRL_PIN(1, "CORE_VID_1"),
@@ -113,324 +117,273 @@ static const struct pinctrl_pin_desc tgllp_community0_pins[] = { · 64 unmodified lines
113 PINCTRL_PIN(64, "GPPC_A_22"),117 PINCTRL_PIN(64, "GPPC_A_22"),
114 PINCTRL_PIN(65, "I2S1_SCLK"),118 PINCTRL_PIN(65, "I2S1_SCLK"),
115 PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),119 PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
116};
117
118static const struct intel_padgroup tgllp_community0_gpps[] = {
119 TGL_GPP(0, 0, 25), /* GPP_B */
120 TGL_GPP(1, 26, 41), /* GPP_T */
121 TGL_GPP(2, 42, 66), /* GPP_A */
122};
123
124static const struct intel_community tgllp_community0[] = {
125 TGL_COMMUNITY(0, 66, tgllp_community0_gpps),
126};
127
128static const struct intel_pinctrl_soc_data tgllp_community0_soc_data = {
129 .uid = "0",
130 .pins = tgllp_community0_pins,
131 .npins = ARRAY_SIZE(tgllp_community0_pins),
132 .communities = tgllp_community0,
133 .ncommunities = ARRAY_SIZE(tgllp_community0),
134};
135
136static const struct pinctrl_pin_desc tgllp_community1_pins[] = {
137 /* GPP_S */120 /* GPP_S */
138 PINCTRL_PIN(0, "SNDW0_CLK"),121 PINCTRL_PIN(67, "SNDW0_CLK"),
139 PINCTRL_PIN(1, "SNDW0_DATA"),122 PINCTRL_PIN(68, "SNDW0_DATA"),
140 PINCTRL_PIN(2, "SNDW1_CLK"),123 PINCTRL_PIN(69, "SNDW1_CLK"),
141 PINCTRL_PIN(3, "SNDW1_DATA"),124 PINCTRL_PIN(70, "SNDW1_DATA"),
142 PINCTRL_PIN(4, "SNDW2_CLK"),125 PINCTRL_PIN(71, "SNDW2_CLK"),
143 PINCTRL_PIN(5, "SNDW2_DATA"),126 PINCTRL_PIN(72, "SNDW2_DATA"),
144 PINCTRL_PIN(6, "SNDW3_CLK"),127 PINCTRL_PIN(73, "SNDW3_CLK"),
145 PINCTRL_PIN(7, "SNDW3_DATA"),128 PINCTRL_PIN(74, "SNDW3_DATA"),
146 /* GPP_H */129 /* GPP_H */
147 PINCTRL_PIN(8, "GPPC_H_0"),130 PINCTRL_PIN(75, "GPPC_H_0"),
148 PINCTRL_PIN(9, "GPPC_H_1"),131 PINCTRL_PIN(76, "GPPC_H_1"),
149 PINCTRL_PIN(10, "GPPC_H_2"),132 PINCTRL_PIN(77, "GPPC_H_2"),
150 PINCTRL_PIN(11, "SX_EXIT_HOLDOFFB"),133 PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"),
151 PINCTRL_PIN(12, "I2C2_SDA"),134 PINCTRL_PIN(79, "I2C2_SDA"),
152 PINCTRL_PIN(13, "I2C2_SCL"),135 PINCTRL_PIN(80, "I2C2_SCL"),
153 PINCTRL_PIN(14, "I2C3_SDA"),136 PINCTRL_PIN(81, "I2C3_SDA"),
154 PINCTRL_PIN(15, "I2C3_SCL"),137 PINCTRL_PIN(82, "I2C3_SCL"),
155 PINCTRL_PIN(16, "I2C4_SDA"),138 PINCTRL_PIN(83, "I2C4_SDA"),
156 PINCTRL_PIN(17, "I2C4_SCL"),139 PINCTRL_PIN(84, "I2C4_SCL"),
157 PINCTRL_PIN(18, "SRCCLKREQB_4"),140 PINCTRL_PIN(85, "SRCCLKREQB_4"),
158 PINCTRL_PIN(19, "SRCCLKREQB_5"),141 PINCTRL_PIN(86, "SRCCLKREQB_5"),
159 PINCTRL_PIN(20, "M2_SKT2_CFG_0"),142 PINCTRL_PIN(87, "M2_SKT2_CFG_0"),
160 PINCTRL_PIN(21, "M2_SKT2_CFG_1"),143 PINCTRL_PIN(88, "M2_SKT2_CFG_1"),
161 PINCTRL_PIN(22, "M2_SKT2_CFG_2"),144 PINCTRL_PIN(89, "M2_SKT2_CFG_2"),
162 PINCTRL_PIN(23, "M2_SKT2_CFG_3"),145 PINCTRL_PIN(90, "M2_SKT2_CFG_3"),
163 PINCTRL_PIN(24, "DDPB_CTRLCLK"),146 PINCTRL_PIN(91, "DDPB_CTRLCLK"),
164 PINCTRL_PIN(25, "DDPB_CTRLDATA"),147 PINCTRL_PIN(92, "DDPB_CTRLDATA"),
165 PINCTRL_PIN(26, "CPU_C10_GATEB"),148 PINCTRL_PIN(93, "CPU_C10_GATEB"),
166 PINCTRL_PIN(27, "TIME_SYNC_0"),149 PINCTRL_PIN(94, "TIME_SYNC_0"),
167 PINCTRL_PIN(28, "IMGCLKOUT_1"),150 PINCTRL_PIN(95, "IMGCLKOUT_1"),
168 PINCTRL_PIN(29, "IMGCLKOUT_2"),151 PINCTRL_PIN(96, "IMGCLKOUT_2"),
169 PINCTRL_PIN(30, "IMGCLKOUT_3"),152 PINCTRL_PIN(97, "IMGCLKOUT_3"),
170 PINCTRL_PIN(31, "IMGCLKOUT_4"),153 PINCTRL_PIN(98, "IMGCLKOUT_4"),
171 /* GPP_D */154 /* GPP_D */
172 PINCTRL_PIN(32, "ISH_GP_0"),155 PINCTRL_PIN(99, "ISH_GP_0"),
173 PINCTRL_PIN(33, "ISH_GP_1"),156 PINCTRL_PIN(100, "ISH_GP_1"),
174 PINCTRL_PIN(34, "ISH_GP_2"),157 PINCTRL_PIN(101, "ISH_GP_2"),
175 PINCTRL_PIN(35, "ISH_GP_3"),158 PINCTRL_PIN(102, "ISH_GP_3"),
176 PINCTRL_PIN(36, "IMGCLKOUT_0"),159 PINCTRL_PIN(103, "IMGCLKOUT_0"),
177 PINCTRL_PIN(37, "SRCCLKREQB_0"),160 PINCTRL_PIN(104, "SRCCLKREQB_0"),
178 PINCTRL_PIN(38, "SRCCLKREQB_1"),161 PINCTRL_PIN(105, "SRCCLKREQB_1"),
179 PINCTRL_PIN(39, "SRCCLKREQB_2"),162 PINCTRL_PIN(106, "SRCCLKREQB_2"),
180 PINCTRL_PIN(40, "SRCCLKREQB_3"),163 PINCTRL_PIN(107, "SRCCLKREQB_3"),
181 PINCTRL_PIN(41, "ISH_SPI_CSB"),164 PINCTRL_PIN(108, "ISH_SPI_CSB"),
182 PINCTRL_PIN(42, "ISH_SPI_CLK"),165 PINCTRL_PIN(109, "ISH_SPI_CLK"),
183 PINCTRL_PIN(43, "ISH_SPI_MISO"),166 PINCTRL_PIN(110, "ISH_SPI_MISO"),
184 PINCTRL_PIN(44, "ISH_SPI_MOSI"),167 PINCTRL_PIN(111, "ISH_SPI_MOSI"),
185 PINCTRL_PIN(45, "ISH_UART0_RXD"),168 PINCTRL_PIN(112, "ISH_UART0_RXD"),
186 PINCTRL_PIN(46, "ISH_UART0_TXD"),169 PINCTRL_PIN(113, "ISH_UART0_TXD"),
187 PINCTRL_PIN(47, "ISH_UART0_RTSB"),170 PINCTRL_PIN(114, "ISH_UART0_RTSB"),
188 PINCTRL_PIN(48, "ISH_UART0_CTSB"),171 PINCTRL_PIN(115, "ISH_UART0_CTSB"),
189 PINCTRL_PIN(49, "ISH_GP_4"),172 PINCTRL_PIN(116, "ISH_GP_4"),
190 PINCTRL_PIN(50, "ISH_GP_5"),173 PINCTRL_PIN(117, "ISH_GP_5"),
191 PINCTRL_PIN(51, "I2S_MCLK1_OUT"),174 PINCTRL_PIN(118, "I2S_MCLK1_OUT"),
192 PINCTRL_PIN(52, "GSPI2_CLK_LOOPBK"),175 PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"),
193 /* GPP_U */176 /* GPP_U */
194 PINCTRL_PIN(53, "UART3_RXD"),177 PINCTRL_PIN(120, "UART3_RXD"),
195 PINCTRL_PIN(54, "UART3_TXD"),178 PINCTRL_PIN(121, "UART3_TXD"),
196 PINCTRL_PIN(55, "UART3_RTSB"),179 PINCTRL_PIN(122, "UART3_RTSB"),
197 PINCTRL_PIN(56, "UART3_CTSB"),180 PINCTRL_PIN(123, "UART3_CTSB"),
198 PINCTRL_PIN(57, "GSPI3_CS0B"),181 PINCTRL_PIN(124, "GSPI3_CS0B"),
199 PINCTRL_PIN(58, "GSPI3_CLK"),182 PINCTRL_PIN(125, "GSPI3_CLK"),
200 PINCTRL_PIN(59, "GSPI3_MISO"),183 PINCTRL_PIN(126, "GSPI3_MISO"),
201 PINCTRL_PIN(60, "GSPI3_MOSI"),184 PINCTRL_PIN(127, "GSPI3_MOSI"),
202 PINCTRL_PIN(61, "GSPI4_CS0B"),185 PINCTRL_PIN(128, "GSPI4_CS0B"),
203 PINCTRL_PIN(62, "GSPI4_CLK"),186 PINCTRL_PIN(129, "GSPI4_CLK"),
204 PINCTRL_PIN(63, "GSPI4_MISO"),187 PINCTRL_PIN(130, "GSPI4_MISO"),
205 PINCTRL_PIN(64, "GSPI4_MOSI"),188 PINCTRL_PIN(131, "GSPI4_MOSI"),
206 PINCTRL_PIN(65, "GSPI5_CS0B"),189 PINCTRL_PIN(132, "GSPI5_CS0B"),
207 PINCTRL_PIN(66, "GSPI5_CLK"),190 PINCTRL_PIN(133, "GSPI5_CLK"),
208 PINCTRL_PIN(67, "GSPI5_MISO"),191 PINCTRL_PIN(134, "GSPI5_MISO"),
209 PINCTRL_PIN(68, "GSPI5_MOSI"),192 PINCTRL_PIN(135, "GSPI5_MOSI"),
210 PINCTRL_PIN(69, "GSPI6_CS0B"),193 PINCTRL_PIN(136, "GSPI6_CS0B"),
211 PINCTRL_PIN(70, "GSPI6_CLK"),194 PINCTRL_PIN(137, "GSPI6_CLK"),
212 PINCTRL_PIN(71, "GSPI6_MISO"),195 PINCTRL_PIN(138, "GSPI6_MISO"),
213 PINCTRL_PIN(72, "GSPI6_MOSI"),196 PINCTRL_PIN(139, "GSPI6_MOSI"),
214 PINCTRL_PIN(73, "GSPI3_CLK_LOOPBK"),197 PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"),
215 PINCTRL_PIN(74, "GSPI4_CLK_LOOPBK"),198 PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"),
216 PINCTRL_PIN(75, "GSPI5_CLK_LOOPBK"),199 PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"),
217 PINCTRL_PIN(76, "GSPI6_CLK_LOOPBK"),200 PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"),
218 /* vGPIO */201 /* vGPIO */
219 PINCTRL_PIN(77, "CNV_BTEN"),202 PINCTRL_PIN(144, "CNV_BTEN"),
220 PINCTRL_PIN(78, "CNV_BT_HOST_WAKEB"),203 PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
221 PINCTRL_PIN(79, "CNV_BT_IF_SELECT"),204 PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
222 PINCTRL_PIN(80, "vCNV_BT_UART_TXD"),205 PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
223 PINCTRL_PIN(81, "vCNV_BT_UART_RXD"),206 PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
224 PINCTRL_PIN(82, "vCNV_BT_UART_CTS_B"),207 PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
225 PINCTRL_PIN(83, "vCNV_BT_UART_RTS_B"),208 PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
226 PINCTRL_PIN(84, "vCNV_MFUART1_TXD"),209 PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
227 PINCTRL_PIN(85, "vCNV_MFUART1_RXD"),210 PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
228 PINCTRL_PIN(86, "vCNV_MFUART1_CTS_B"),211 PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
229 PINCTRL_PIN(87, "vCNV_MFUART1_RTS_B"),212 PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
230 PINCTRL_PIN(88, "vUART0_TXD"),213 PINCTRL_PIN(155, "vUART0_TXD"),
231 PINCTRL_PIN(89, "vUART0_RXD"),214 PINCTRL_PIN(156, "vUART0_RXD"),
232 PINCTRL_PIN(90, "vUART0_CTS_B"),215 PINCTRL_PIN(157, "vUART0_CTS_B"),
233 PINCTRL_PIN(91, "vUART0_RTS_B"),216 PINCTRL_PIN(158, "vUART0_RTS_B"),
234 PINCTRL_PIN(92, "vISH_UART0_TXD"),217 PINCTRL_PIN(159, "vISH_UART0_TXD"),
235 PINCTRL_PIN(93, "vISH_UART0_RXD"),218 PINCTRL_PIN(160, "vISH_UART0_RXD"),
236 PINCTRL_PIN(94, "vISH_UART0_CTS_B"),219 PINCTRL_PIN(161, "vISH_UART0_CTS_B"),
237 PINCTRL_PIN(95, "vISH_UART0_RTS_B"),220 PINCTRL_PIN(162, "vISH_UART0_RTS_B"),
238 PINCTRL_PIN(96, "vCNV_BT_I2S_BCLK"),221 PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"),
239 PINCTRL_PIN(97, "vCNV_BT_I2S_WS_SYNC"),222 PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"),
240 PINCTRL_PIN(98, "vCNV_BT_I2S_SDO"),223 PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"),
241 PINCTRL_PIN(99, "vCNV_BT_I2S_SDI"),224 PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"),
242 PINCTRL_PIN(100, "vI2S2_SCLK"),225 PINCTRL_PIN(167, "vI2S2_SCLK"),
243 PINCTRL_PIN(101, "vI2S2_SFRM"),226 PINCTRL_PIN(168, "vI2S2_SFRM"),
244 PINCTRL_PIN(102, "vI2S2_TXD"),227 PINCTRL_PIN(169, "vI2S2_TXD"),
245 PINCTRL_PIN(103, "vI2S2_RXD"),228 PINCTRL_PIN(170, "vI2S2_RXD"),
246};
247
248static const struct intel_padgroup tgllp_community1_gpps[] = {
249 TGL_GPP(0, 0, 7), /* GPP_S */
250 TGL_GPP(1, 8, 31), /* GPP_H */
251 TGL_GPP(2, 32, 52), /* GPP_D */
252 TGL_GPP(3, 53, 76), /* GPP_U */
253 TGL_GPP(4, 77, 103), /* vGPIO */
254};
255
256static const struct intel_community tgllp_community1[] = {
257 TGL_COMMUNITY(0, 103, tgllp_community1_gpps),
258};
259
260static const struct intel_pinctrl_soc_data tgllp_community1_soc_data = {
261 .uid = "1",
262 .pins = tgllp_community1_pins,
263 .npins = ARRAY_SIZE(tgllp_community1_pins),
264 .communities = tgllp_community1,
265 .ncommunities = ARRAY_SIZE(tgllp_community1),
266};
267
268static const struct pinctrl_pin_desc tgllp_community4_pins[] = {
269 /* GPP_C */229 /* GPP_C */
270 PINCTRL_PIN(0, "SMBCLK"),230 PINCTRL_PIN(171, "SMBCLK"),
271 PINCTRL_PIN(1, "SMBDATA"),231 PINCTRL_PIN(172, "SMBDATA"),
272 PINCTRL_PIN(2, "SMBALERTB"),232 PINCTRL_PIN(173, "SMBALERTB"),
273 PINCTRL_PIN(3, "SML0CLK"),233 PINCTRL_PIN(174, "SML0CLK"),
274 PINCTRL_PIN(4, "SML0DATA"),234 PINCTRL_PIN(175, "SML0DATA"),
275 PINCTRL_PIN(5, "SML0ALERTB"),235 PINCTRL_PIN(176, "SML0ALERTB"),
276 PINCTRL_PIN(6, "SML1CLK"),236 PINCTRL_PIN(177, "SML1CLK"),
277 PINCTRL_PIN(7, "SML1DATA"),237 PINCTRL_PIN(178, "SML1DATA"),
278 PINCTRL_PIN(8, "UART0_RXD"),238 PINCTRL_PIN(179, "UART0_RXD"),
279 PINCTRL_PIN(9, "UART0_TXD"),239 PINCTRL_PIN(180, "UART0_TXD"),
280 PINCTRL_PIN(10, "UART0_RTSB"),240 PINCTRL_PIN(181, "UART0_RTSB"),
281 PINCTRL_PIN(11, "UART0_CTSB"),241 PINCTRL_PIN(182, "UART0_CTSB"),
282 PINCTRL_PIN(12, "UART1_RXD"),242 PINCTRL_PIN(183, "UART1_RXD"),
283 PINCTRL_PIN(13, "UART1_TXD"),243 PINCTRL_PIN(184, "UART1_TXD"),
284 PINCTRL_PIN(14, "UART1_RTSB"),244 PINCTRL_PIN(185, "UART1_RTSB"),
285 PINCTRL_PIN(15, "UART1_CTSB"),245 PINCTRL_PIN(186, "UART1_CTSB"),
286 PINCTRL_PIN(16, "I2C0_SDA"),246 PINCTRL_PIN(187, "I2C0_SDA"),
287 PINCTRL_PIN(17, "I2C0_SCL"),247 PINCTRL_PIN(188, "I2C0_SCL"),
288 PINCTRL_PIN(18, "I2C1_SDA"),248 PINCTRL_PIN(189, "I2C1_SDA"),
289 PINCTRL_PIN(19, "I2C1_SCL"),249 PINCTRL_PIN(190, "I2C1_SCL"),
290 PINCTRL_PIN(20, "UART2_RXD"),250 PINCTRL_PIN(191, "UART2_RXD"),
291 PINCTRL_PIN(21, "UART2_TXD"),251 PINCTRL_PIN(192, "UART2_TXD"),
292 PINCTRL_PIN(22, "UART2_RTSB"),252 PINCTRL_PIN(193, "UART2_RTSB"),
293 PINCTRL_PIN(23, "UART2_CTSB"),253 PINCTRL_PIN(194, "UART2_CTSB"),
294 /* GPP_F */254 /* GPP_F */
295 PINCTRL_PIN(24, "CNV_BRI_DT"),255 PINCTRL_PIN(195, "CNV_BRI_DT"),
296 PINCTRL_PIN(25, "CNV_BRI_RSP"),256 PINCTRL_PIN(196, "CNV_BRI_RSP"),
297 PINCTRL_PIN(26, "CNV_RGI_DT"),257 PINCTRL_PIN(197, "CNV_RGI_DT"),
298 PINCTRL_PIN(27, "CNV_RGI_RSP"),258 PINCTRL_PIN(198, "CNV_RGI_RSP"),
299 PINCTRL_PIN(28, "CNV_RF_RESET_B"),259 PINCTRL_PIN(199, "CNV_RF_RESET_B"),
300 PINCTRL_PIN(29, "GPPC_F_5"),260 PINCTRL_PIN(200, "GPPC_F_5"),
301 PINCTRL_PIN(30, "CNV_PA_BLANKING"),261 PINCTRL_PIN(201, "CNV_PA_BLANKING"),
302 PINCTRL_PIN(31, "GPPC_F_7"),262 PINCTRL_PIN(202, "GPPC_F_7"),
303 PINCTRL_PIN(32, "I2S_MCLK2_INOUT"),263 PINCTRL_PIN(203, "I2S_MCLK2_INOUT"),
304 PINCTRL_PIN(33, "BOOTMPC"),264 PINCTRL_PIN(204, "BOOTMPC"),
305 PINCTRL_PIN(34, "GPPC_F_10"),265 PINCTRL_PIN(205, "GPPC_F_10"),
306 PINCTRL_PIN(35, "GPPC_F_11"),266 PINCTRL_PIN(206, "GPPC_F_11"),
307 PINCTRL_PIN(36, "GSXDOUT"),267 PINCTRL_PIN(207, "GSXDOUT"),
308 PINCTRL_PIN(37, "GSXSLOAD"),268 PINCTRL_PIN(208, "GSXSLOAD"),
309 PINCTRL_PIN(38, "GSXDIN"),269 PINCTRL_PIN(209, "GSXDIN"),
310 PINCTRL_PIN(39, "GSXSRESETB"),270 PINCTRL_PIN(210, "GSXSRESETB"),
311 PINCTRL_PIN(40, "GSXCLK"),271 PINCTRL_PIN(211, "GSXCLK"),
312 PINCTRL_PIN(41, "GMII_MDC"),272 PINCTRL_PIN(212, "GMII_MDC"),
313 PINCTRL_PIN(42, "GMII_MDIO"),273 PINCTRL_PIN(213, "GMII_MDIO"),
314 PINCTRL_PIN(43, "SRCCLKREQB_6"),274 PINCTRL_PIN(214, "SRCCLKREQB_6"),
315 PINCTRL_PIN(44, "EXT_PWR_GATEB"),275 PINCTRL_PIN(215, "EXT_PWR_GATEB"),
316 PINCTRL_PIN(45, "EXT_PWR_GATE2B"),276 PINCTRL_PIN(216, "EXT_PWR_GATE2B"),
317 PINCTRL_PIN(46, "VNN_CTRL"),277 PINCTRL_PIN(217, "VNN_CTRL"),
318 PINCTRL_PIN(47, "V1P05_CTRL"),278 PINCTRL_PIN(218, "V1P05_CTRL"),
319 PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"),279 PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"),
320 /* HVCMOS */280 /* HVCMOS */
321 PINCTRL_PIN(49, "L_BKLTEN"),281 PINCTRL_PIN(220, "L_BKLTEN"),
322 PINCTRL_PIN(50, "L_BKLTCTL"),282 PINCTRL_PIN(221, "L_BKLTCTL"),
323 PINCTRL_PIN(51, "L_VDDEN"),283 PINCTRL_PIN(222, "L_VDDEN"),
324 PINCTRL_PIN(52, "SYS_PWROK"),284 PINCTRL_PIN(223, "SYS_PWROK"),
325 PINCTRL_PIN(53, "SYS_RESETB"),285 PINCTRL_PIN(224, "SYS_RESETB"),
326 PINCTRL_PIN(54, "MLK_RSTB"),286 PINCTRL_PIN(225, "MLK_RSTB"),
327 /* GPP_E */287 /* GPP_E */
328 PINCTRL_PIN(55, "SATAXPCIE_0"),288 PINCTRL_PIN(226, "SATAXPCIE_0"),
329 PINCTRL_PIN(56, "SPI1_IO_2"),289 PINCTRL_PIN(227, "SPI1_IO_2"),
330 PINCTRL_PIN(57, "SPI1_IO_3"),290 PINCTRL_PIN(228, "SPI1_IO_3"),
331 PINCTRL_PIN(58, "CPU_GP_0"),291 PINCTRL_PIN(229, "CPU_GP_0"),
332 PINCTRL_PIN(59, "SATA_DEVSLP_0"),292 PINCTRL_PIN(230, "SATA_DEVSLP_0"),
333 PINCTRL_PIN(60, "SATA_DEVSLP_1"),293 PINCTRL_PIN(231, "SATA_DEVSLP_1"),
334 PINCTRL_PIN(61, "GPPC_E_6"),294 PINCTRL_PIN(232, "GPPC_E_6"),
335 PINCTRL_PIN(62, "CPU_GP_1"),295 PINCTRL_PIN(233, "CPU_GP_1"),
336 PINCTRL_PIN(63, "SPI1_CS1B"),296 PINCTRL_PIN(234, "SPI1_CS1B"),
337 PINCTRL_PIN(64, "USB2_OCB_0"),297 PINCTRL_PIN(235, "USB2_OCB_0"),
338 PINCTRL_PIN(65, "SPI1_CSB"),298 PINCTRL_PIN(236, "SPI1_CSB"),
339 PINCTRL_PIN(66, "SPI1_CLK"),299 PINCTRL_PIN(237, "SPI1_CLK"),
340 PINCTRL_PIN(67, "SPI1_MISO_IO_1"),300 PINCTRL_PIN(238, "SPI1_MISO_IO_1"),
341 PINCTRL_PIN(68, "SPI1_MOSI_IO_0"),301 PINCTRL_PIN(239, "SPI1_MOSI_IO_0"),
342 PINCTRL_PIN(69, "DDSP_HPD_A"),302 PINCTRL_PIN(240, "DDSP_HPD_A"),
343 PINCTRL_PIN(70, "ISH_GP_6"),303 PINCTRL_PIN(241, "ISH_GP_6"),
344 PINCTRL_PIN(71, "ISH_GP_7"),304 PINCTRL_PIN(242, "ISH_GP_7"),
345 PINCTRL_PIN(72, "GPPC_E_17"),305 PINCTRL_PIN(243, "GPPC_E_17"),
346 PINCTRL_PIN(73, "DDP1_CTRLCLK"),306 PINCTRL_PIN(244, "DDP1_CTRLCLK"),
347 PINCTRL_PIN(74, "DDP1_CTRLDATA"),307 PINCTRL_PIN(245, "DDP1_CTRLDATA"),
348 PINCTRL_PIN(75, "DDP2_CTRLCLK"),308 PINCTRL_PIN(246, "DDP2_CTRLCLK"),
349 PINCTRL_PIN(76, "DDP2_CTRLDATA"),309 PINCTRL_PIN(247, "DDP2_CTRLDATA"),
350 PINCTRL_PIN(77, "DDPA_CTRLCLK"),310 PINCTRL_PIN(248, "DDPA_CTRLCLK"),
351 PINCTRL_PIN(78, "DDPA_CTRLDATA"),311 PINCTRL_PIN(249, "DDPA_CTRLDATA"),
352 PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"),312 PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"),
353 /* JTAG */313 /* JTAG */
354 PINCTRL_PIN(80, "JTAG_TDO"),314 PINCTRL_PIN(251, "JTAG_TDO"),
355 PINCTRL_PIN(81, "JTAGX"),315 PINCTRL_PIN(252, "JTAGX"),
356 PINCTRL_PIN(82, "PRDYB"),316 PINCTRL_PIN(253, "PRDYB"),
357 PINCTRL_PIN(83, "PREQB"),317 PINCTRL_PIN(254, "PREQB"),
358 PINCTRL_PIN(84, "CPU_TRSTB"),318 PINCTRL_PIN(255, "CPU_TRSTB"),
359 PINCTRL_PIN(85, "JTAG_TDI"),319 PINCTRL_PIN(256, "JTAG_TDI"),
360 PINCTRL_PIN(86, "JTAG_TMS"),320 PINCTRL_PIN(257, "JTAG_TMS"),
361 PINCTRL_PIN(87, "JTAG_TCK"),321 PINCTRL_PIN(258, "JTAG_TCK"),
362 PINCTRL_PIN(88, "DBG_PMODE"),322 PINCTRL_PIN(259, "DBG_PMODE"),
363};323 /* GPP_R */
364 324 PINCTRL_PIN(260, "HDA_BCLK"),
365static const struct intel_padgroup tgllp_community4_gpps[] = {325 PINCTRL_PIN(261, "HDA_SYNC"),
366 TGL_GPP(0, 0, 23), /* GPP_C */326 PINCTRL_PIN(262, "HDA_SDO"),
367 TGL_GPP(1, 24, 48), /* GPP_F */327 PINCTRL_PIN(263, "HDA_SDI_0"),
368 TGL_GPP(2, 49, 54), /* HVCMOS */328 PINCTRL_PIN(264, "HDA_RSTB"),
369 TGL_GPP(3, 55, 79), /* GPP_E */329 PINCTRL_PIN(265, "HDA_SDI_1"),
370 TGL_GPP(4, 80, 88), /* JTAG */330 PINCTRL_PIN(266, "GPP_R_6"),
331 PINCTRL_PIN(267, "GPP_R_7"),
332 /* SPI */
333 PINCTRL_PIN(268, "SPI0_IO_2"),
334 PINCTRL_PIN(269, "SPI0_IO_3"),
335 PINCTRL_PIN(270, "SPI0_MOSI_IO_0"),
336 PINCTRL_PIN(271, "SPI0_MISO_IO_1"),
337 PINCTRL_PIN(272, "SPI0_TPM_CSB"),
338 PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"),
339 PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"),
340 PINCTRL_PIN(275, "SPI0_CLK"),
341 PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"),
371};342};
372 343
373static const struct intel_community tgllp_community4[] = {344static const struct intel_padgroup tgllp_community0_gpps[] = {
374 TGL_COMMUNITY(0, 88, tgllp_community4_gpps),345 TGL_GPP(0, 0, 25, 0), /* GPP_B */
346 TGL_GPP(1, 26, 41, 32), /* GPP_T */
347 TGL_GPP(2, 42, 66, 64), /* GPP_A */
375};348};
376 349
377static const struct intel_pinctrl_soc_data tgllp_community4_soc_data = {350static const struct intel_padgroup tgllp_community1_gpps[] = {
378 .uid = "4",351 TGL_GPP(0, 67, 74, 96), /* GPP_S */
379 .pins = tgllp_community4_pins,352 TGL_GPP(1, 75, 98, 128), /* GPP_H */
380 .npins = ARRAY_SIZE(tgllp_community4_pins),353 TGL_GPP(2, 99, 119, 160), /* GPP_D */
381 .communities = tgllp_community4,354 TGL_GPP(3, 120, 143, 192), /* GPP_U */
382 .ncommunities = ARRAY_SIZE(tgllp_community4),355 TGL_GPP(4, 144, 170, 224), /* vGPIO */
383};356};
384 357
385static const struct pinctrl_pin_desc tgllp_community5_pins[] = {358static const struct intel_padgroup tgllp_community4_gpps[] = {
386 /* GPP_R */359 TGL_GPP(0, 171, 194, 256), /* GPP_C */
387 PINCTRL_PIN(0, "HDA_BCLK"),360 TGL_GPP(1, 195, 219, 288), /* GPP_F */
388 PINCTRL_PIN(1, "HDA_SYNC"),361 TGL_GPP(2, 220, 225, TGL_NO_GPIO), /* HVCMOS */
389 PINCTRL_PIN(2, "HDA_SDO"),362 TGL_GPP(3, 226, 250, 320), /* GPP_E */
390 PINCTRL_PIN(3, "HDA_SDI_0"),363 TGL_GPP(4, 251, 259, TGL_NO_GPIO), /* JTAG */
391 PINCTRL_PIN(4, "HDA_RSTB"),
392 PINCTRL_PIN(5, "HDA_SDI_1"),
393 PINCTRL_PIN(6, "GPP_R_6"),
394 PINCTRL_PIN(7, "GPP_R_7"),
395 /* SPI */
396 PINCTRL_PIN(8, "SPI0_IO_2"),
397 PINCTRL_PIN(9, "SPI0_IO_3"),
398 PINCTRL_PIN(10, "SPI0_MOSI_IO_0"),
399 PINCTRL_PIN(11, "SPI0_MISO_IO_1"),
400 PINCTRL_PIN(12, "SPI0_TPM_CSB"),
401 PINCTRL_PIN(13, "SPI0_FLASH_0_CSB"),
402 PINCTRL_PIN(14, "SPI0_FLASH_1_CSB"),
403 PINCTRL_PIN(15, "SPI0_CLK"),
404 PINCTRL_PIN(16, "SPI0_CLK_LOOPBK"),
405};364};
406 365
407static const struct intel_padgroup tgllp_community5_gpps[] = {366static const struct intel_padgroup tgllp_community5_gpps[] = {
408 TGL_GPP(0, 0, 7), /* GPP_R */367 TGL_GPP(0, 260, 267, 352), /* GPP_R */
409 TGL_GPP(1, 8, 16), /* SPI */368 TGL_GPP(1, 268, 276, TGL_NO_GPIO), /* SPI */
410};
411
412static const struct intel_community tgllp_community5[] = {
413 TGL_COMMUNITY(0, 16, tgllp_community5_gpps),
414};369};
415 370
416static const struct intel_pinctrl_soc_data tgllp_community5_soc_data = {371static const struct intel_community tgllp_communities[] = {
417 .uid = "5",372 TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps),
418 .pins = tgllp_community5_pins,373 TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps),
419 .npins = ARRAY_SIZE(tgllp_community5_pins),374 TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
420 .communities = tgllp_community5,375 TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps),
421 .ncommunities = ARRAY_SIZE(tgllp_community5),
422};376};
423 377
424static const struct intel_pinctrl_soc_data *tgllp_soc_data_array[] = {378static const struct intel_pinctrl_soc_data tgllp_soc_data = {
425 &tgllp_community0_soc_data,379 .pins = tgllp_pins,
426 &tgllp_community1_soc_data,380 .npins = ARRAY_SIZE(tgllp_pins),
427 &tgllp_community4_soc_data,381 .communities = tgllp_communities,
428 &tgllp_community5_soc_data,382 .ncommunities = ARRAY_SIZE(tgllp_communities),
429 NULL
430};383};
431 384
432static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {385static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
433 { "INT34C5", (kernel_ulong_t)tgllp_soc_data_array },386 { "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
434 { }387 { }
435};388};
436MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);389MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
@@ -438,7 +391,7 @@ MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); · 1 unmodified line
438static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);391static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);
439 392
440static struct platform_driver tgl_pinctrl_driver = {393static struct platform_driver tgl_pinctrl_driver = {
441 .probe = intel_pinctrl_probe_by_uid,394 .probe = intel_pinctrl_probe_by_hid,
442 .driver = {395 .driver = {
443 .name = "tigerlake-pinctrl",396 .name = "tigerlake-pinctrl",
444 .acpi_match_table = tgl_pinctrl_acpi_match,397 .acpi_match_table = tgl_pinctrl_acpi_match,
drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h+1−1
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.01/* SPDX-License-Identifier: GPL-2.0 */
2/*2/*
3 * Copyright (C) 2018 MediaTek Inc.3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>4 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h+1−1
@@ -1,3 +1,4 @@
1/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
1/*2/*
2 * Copyright (c) 2017 Baylibre SAS.3 * Copyright (c) 2017 Baylibre SAS.
3 * Author: Jerome Brunet <jbrunet@baylibre.com>4 * Author: Jerome Brunet <jbrunet@baylibre.com>
@@ -5,7 +6,6 @@ · 1 unmodified line
5 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.6 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
6 * Author: Xingyu Chen <xingyu.chen@amlogic.com>7 * Author: Xingyu Chen <xingyu.chen@amlogic.com>
7 *8 *
8 * SPDX-License-Identifier: (GPL-2.0+ or MIT)
9 */9 */
10 10
11struct meson_pmx_bank {11struct meson_pmx_bank {
drivers/pinctrl/meson/pinctrl-meson8b.c+6−1
@@ -233,6 +233,8 @@ static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; · 232 unmodified lines
233static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 };233static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 };
234static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 };234static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 };
235static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 };235static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 };
236static const unsigned int eth_rxd3_h_pins[] = { GPIOH_5 };
237static const unsigned int eth_rxd2_h_pins[] = { GPIOH_6 };
236static const unsigned int clk_24m_out_pins[] = { GPIOH_9 };238static const unsigned int clk_24m_out_pins[] = { GPIOH_9 };
237 239
238static const unsigned int spi_ss1_pins[] = { GPIOH_0 };240static const unsigned int spi_ss1_pins[] = { GPIOH_0 };
@@ -535,6 +537,8 @@ static struct meson_pmx_group meson8b_cbus_groups[] = { · 296 unmodified lines
535 GROUP(spi_miso_1, 9, 12),537 GROUP(spi_miso_1, 9, 12),
536 GROUP(spi_mosi_1, 9, 11),538 GROUP(spi_mosi_1, 9, 11),
537 GROUP(spi_sclk_1, 9, 10),539 GROUP(spi_sclk_1, 9, 10),
540 GROUP(eth_rxd3_h, 6, 15),
541 GROUP(eth_rxd2_h, 6, 14),
538 GROUP(eth_txd3, 6, 13),542 GROUP(eth_txd3, 6, 13),
539 GROUP(eth_txd2, 6, 12),543 GROUP(eth_txd2, 6, 12),
540 GROUP(eth_tx_clk, 6, 11),544 GROUP(eth_tx_clk, 6, 11),
@@ -746,7 +750,8 @@ static const char * const ethernet_groups[] = { · 205 unmodified lines
746 "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1",750 "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1",
747 "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv",751 "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv",
748 "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk",752 "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk",
749 "eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2"753 "eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2",
754 "eth_rxd3_h", "eth_rxd2_h"
750};755};
751 756
752static const char * const i2c_a_groups[] = {757static const char * const i2c_a_groups[] = {
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c+11−5
@@ -15,7 +15,6 @@ · 14 unmodified lines
15#include <linux/of.h>15#include <linux/of.h>
16#include <linux/of_address.h>16#include <linux/of_address.h>
17#include <linux/of_device.h>17#include <linux/of_device.h>
18#include <linux/of_irq.h>
19#include <linux/pinctrl/pinconf-generic.h>18#include <linux/pinctrl/pinconf-generic.h>
20#include <linux/pinctrl/pinconf.h>19#include <linux/pinctrl/pinconf.h>
21#include <linux/pinctrl/pinctrl.h>20#include <linux/pinctrl/pinctrl.h>
@@ -733,13 +732,20 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, · 711 unmodified lines
733 ret = 0;732 ret = 0;
734 break;733 break;
735 }734 }
736 };735 }
737 if (ret) {736 if (ret) {
738 dev_err(dev, "no gpio-controller child node\n");737 dev_err(dev, "no gpio-controller child node\n");
739 return ret;738 return ret;
740 }739 }
741 740
742 nr_irq_parent = of_irq_count(np);741 nr_irq_parent = platform_irq_count(pdev);
742 if (nr_irq_parent < 0) {
743 if (nr_irq_parent != -EPROBE_DEFER)
744 dev_err(dev, "Couldn't determine irq count: %pe\n",
745 ERR_PTR(nr_irq_parent));
746 return nr_irq_parent;
747 }
748
743 spin_lock_init(&info->irq_lock);749 spin_lock_init(&info->irq_lock);
744 750
745 if (!nr_irq_parent) {751 if (!nr_irq_parent) {
@@ -776,7 +782,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, · 30 unmodified lines
776 if (!girq->parents)782 if (!girq->parents)
777 return -ENOMEM;783 return -ENOMEM;
778 for (i = 0; i < nr_irq_parent; i++) {784 for (i = 0; i < nr_irq_parent; i++) {
779 int irq = irq_of_parse_and_map(np, i);785 int irq = platform_get_irq(pdev, i);
780 786
781 if (irq < 0)787 if (irq < 0)
782 continue;788 continue;
@@ -800,7 +806,7 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev, · 17 unmodified lines
800 ret = 0;806 ret = 0;
801 break;807 break;
802 }808 }
803 };809 }
804 if (ret)810 if (ret)
805 return ret;811 return ret;
806 812
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c+1−1
@@ -331,7 +331,7 @@ static unsigned int npcmgpio_irq_startup(struct irq_data *d) · 330 unmodified lines
331 return 0;331 return 0;
332}332}
333 333
334static struct irq_chip npcmgpio_irqchip = {334static const struct irq_chip npcmgpio_irqchip = {
335 .name = "NPCM7XX-GPIO-IRQ",335 .name = "NPCM7XX-GPIO-IRQ",
336 .irq_ack = npcmgpio_irq_ack,336 .irq_ack = npcmgpio_irq_ack,
337 .irq_unmask = npcmgpio_irq_unmask,337 .irq_unmask = npcmgpio_irq_unmask,
drivers/pinctrl/pinctrl-artpec6.c+1−1
@@ -798,7 +798,7 @@ static int artpec6_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 797 unmodified lines
798 enum pin_config_param param;798 enum pin_config_param param;
799 unsigned int arg;799 unsigned int arg;
800 unsigned int regval;800 unsigned int regval;
801 unsigned int *reg;801 void __iomem *reg;
802 int i;802 int i;
803 803
804 /* Check for valid pin */804 /* Check for valid pin */
drivers/pinctrl/pinctrl-ingenic.c+442−195
@@ -3,7 +3,7 @@ · 2 unmodified lines
3 * Ingenic SoCs pinctrl driver3 * Ingenic SoCs pinctrl driver
4 *4 *
5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
6 * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
7 */7 */
8 8
9#include <linux/compiler.h>9#include <linux/compiler.h>
@@ -42,28 +42,36 @@ · 32 unmodified lines
42#define JZ4760_GPIO_FLAG 0x5042#define JZ4760_GPIO_FLAG 0x50
43#define JZ4760_GPIO_PEN 0x7043#define JZ4760_GPIO_PEN 0x70
44 44
45#define X1000_GPIO_PZ_BASE 0x70045#define X1830_GPIO_PEL 0x110
46#define X1000_GPIO_PZ_GID2LD 0x7f046#define X1830_GPIO_PEH 0x120
47 47
48#define REG_SET(x) ((x) + 0x4)48#define REG_SET(x) ((x) + 0x4)
49#define REG_CLEAR(x) ((x) + 0x8)49#define REG_CLEAR(x) ((x) + 0x8)
50 50
51#define REG_PZ_BASE(x) ((x) * 7)
52#define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
53
54#define GPIO_PULL_DIS 0
55#define GPIO_PULL_UP 1
56#define GPIO_PULL_DOWN 2
57
51#define PINS_PER_GPIO_CHIP 3258#define PINS_PER_GPIO_CHIP 32
52 59
53enum jz_version {60enum jz_version {
54 ID_JZ4740,61 ID_JZ4740,
55 ID_JZ4725B,62 ID_JZ4725B,
56 ID_JZ4760,63 ID_JZ4760,
57 ID_JZ4760B,
58 ID_JZ4770,64 ID_JZ4770,
59 ID_JZ4780,65 ID_JZ4780,
60 ID_X1000,66 ID_X1000,
61 ID_X1000E,
62 ID_X1500,67 ID_X1500,
68 ID_X1830,
63};69};
64 70
65struct ingenic_chip_info {71struct ingenic_chip_info {
66 unsigned int num_chips;72 unsigned int num_chips;
73 unsigned int reg_offset;
74 enum jz_version version;
67 75
68 const struct group_desc *groups;76 const struct group_desc *groups;
69 unsigned int num_groups;77 unsigned int num_groups;
@@ -79,7 +87,6 @@ struct ingenic_pinctrl { · 9 unmodified lines
79 struct regmap *map;87 struct regmap *map;
80 struct pinctrl_dev *pctl;88 struct pinctrl_dev *pctl;
81 struct pinctrl_pin_desc *pdesc;89 struct pinctrl_pin_desc *pdesc;
82 enum jz_version version;
83 90
84 const struct ingenic_chip_info *info;91 const struct ingenic_chip_info *info;
85};92};
@@ -216,6 +223,8 @@ static const struct function_desc jz4740_functions[] = { · 130 unmodified lines
216 223
217static const struct ingenic_chip_info jz4740_chip_info = {224static const struct ingenic_chip_info jz4740_chip_info = {
218 .num_chips = 4,225 .num_chips = 4,
226 .reg_offset = 0x100,
227 .version = ID_JZ4740,
219 .groups = jz4740_groups,228 .groups = jz4740_groups,
220 .num_groups = ARRAY_SIZE(jz4740_groups),229 .num_groups = ARRAY_SIZE(jz4740_groups),
221 .functions = jz4740_functions,230 .functions = jz4740_functions,
@@ -339,6 +348,8 @@ static const struct function_desc jz4725b_functions[] = { · 117 unmodified lines
339 348
340static const struct ingenic_chip_info jz4725b_chip_info = {349static const struct ingenic_chip_info jz4725b_chip_info = {
341 .num_chips = 4,350 .num_chips = 4,
351 .reg_offset = 0x100,
352 .version = ID_JZ4725B,
342 .groups = jz4725b_groups,353 .groups = jz4725b_groups,
343 .num_groups = ARRAY_SIZE(jz4725b_groups),354 .num_groups = ARRAY_SIZE(jz4725b_groups),
344 .functions = jz4725b_functions,355 .functions = jz4725b_functions,
@@ -592,16 +603,8 @@ static const struct function_desc jz4760_functions[] = { · 247 unmodified lines
592 603
593static const struct ingenic_chip_info jz4760_chip_info = {604static const struct ingenic_chip_info jz4760_chip_info = {
594 .num_chips = 6,605 .num_chips = 6,
595 .groups = jz4760_groups,606 .reg_offset = 0x100,
596 .num_groups = ARRAY_SIZE(jz4760_groups),607 .version = ID_JZ4760,
597 .functions = jz4760_functions,
598 .num_functions = ARRAY_SIZE(jz4760_functions),
599 .pull_ups = jz4760_pull_ups,
600 .pull_downs = jz4760_pull_downs,
601};
602
603static const struct ingenic_chip_info jz4760b_chip_info = {
604 .num_chips = 6,
605 .groups = jz4760_groups,608 .groups = jz4760_groups,
606 .num_groups = ARRAY_SIZE(jz4760_groups),609 .num_groups = ARRAY_SIZE(jz4760_groups),
607 .functions = jz4760_functions,610 .functions = jz4760_functions,
@@ -880,6 +883,8 @@ static const struct function_desc jz4770_functions[] = { · 272 unmodified lines
880 883
881static const struct ingenic_chip_info jz4770_chip_info = {884static const struct ingenic_chip_info jz4770_chip_info = {
882 .num_chips = 6,885 .num_chips = 6,
886 .reg_offset = 0x100,
887 .version = ID_JZ4770,
883 .groups = jz4770_groups,888 .groups = jz4770_groups,
884 .num_groups = ARRAY_SIZE(jz4770_groups),889 .num_groups = ARRAY_SIZE(jz4770_groups),
885 .functions = jz4770_functions,890 .functions = jz4770_functions,
@@ -1013,6 +1018,8 @@ static const struct function_desc jz4780_functions[] = { · 127 unmodified lines
1013 1018
1014static const struct ingenic_chip_info jz4780_chip_info = {1019static const struct ingenic_chip_info jz4780_chip_info = {
1015 .num_chips = 6,1020 .num_chips = 6,
1021 .reg_offset = 0x100,
1022 .version = ID_JZ4780,
1016 .groups = jz4780_groups,1023 .groups = jz4780_groups,
1017 .num_groups = ARRAY_SIZE(jz4780_groups),1024 .num_groups = ARRAY_SIZE(jz4780_groups),
1018 .functions = jz4780_functions,1025 .functions = jz4780_functions,
@@ -1022,7 +1029,7 @@ static const struct ingenic_chip_info jz4780_chip_info = { · 3 unmodified lines
1022};1029};
1023 1030
1024static const u32 x1000_pull_ups[4] = {1031static const u32 x1000_pull_ups[4] = {
1025 0xffffffff, 0x8dffffff, 0x7d3fffff, 0xffffffff,1032 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
1026};1033};
1027 1034
1028static const u32 x1000_pull_downs[4] = {1035static const u32 x1000_pull_downs[4] = {
@@ -1033,28 +1040,45 @@ static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; · 4 unmodified lines
1033static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };1040static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1034static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };1041static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
1035static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };1042static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
1036static int x1000_uart1_hwflow_d_pins[] = { 0x64, 0x65, };1043static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
1037static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };1044static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
1038static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };1045static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
1046static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, };
1047static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
1048static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
1049static int x1000_ssi_dt_d_pins[] = { 0x62, };
1050static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
1051static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
1052static int x1000_ssi_dr_d_pins[] = { 0x63, };
1053static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
1054static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
1055static int x1000_ssi_clk_d_pins[] = { 0x60, };
1056static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
1057static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
1058static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
1059static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
1060static int x1000_ssi_ce0_d_pins[] = { 0x61, };
1061static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
1062static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
1039static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };1063static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
1040static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };1064static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
1041static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };1065static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
1042static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };1066static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
1043static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };1067static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
1044static int x1000_nemc_8bit_data_pins[] = {1068static int x1000_emc_8bit_data_pins[] = {
1045 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,1069 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1046};1070};
1047static int x1000_nemc_16bit_data_pins[] = {1071static int x1000_emc_16bit_data_pins[] = {
1048 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,1072 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1049};1073};
1050static int x1000_nemc_addr_pins[] = {1074static int x1000_emc_addr_pins[] = {
1051 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,1075 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
1052 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,1076 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
1053};1077};
1054static int x1000_nemc_rd_we_pins[] = { 0x30, 0x31, };1078static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
1055static int x1000_nemc_wait_pins[] = { 0x34, };1079static int x1000_emc_wait_pins[] = { 0x34, };
1056static int x1000_nemc_cs1_pins[] = { 0x32, };1080static int x1000_emc_cs1_pins[] = { 0x32, };
1057static int x1000_nemc_cs2_pins[] = { 0x33, };1081static int x1000_emc_cs2_pins[] = { 0x33, };
1058static int x1000_i2c0_pins[] = { 0x38, 0x37, };1082static int x1000_i2c0_pins[] = { 0x38, 0x37, };
1059static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };1083static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
1060static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };1084static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
@@ -1083,23 +1107,40 @@ static int x1000_uart0_data_funcs[] = { 0, 0, }; · 22 unmodified lines
1083static int x1000_uart0_hwflow_funcs[] = { 0, 0, };1107static int x1000_uart0_hwflow_funcs[] = { 0, 0, };
1084static int x1000_uart1_data_a_funcs[] = { 2, 2, };1108static int x1000_uart1_data_a_funcs[] = { 2, 2, };
1085static int x1000_uart1_data_d_funcs[] = { 1, 1, };1109static int x1000_uart1_data_d_funcs[] = { 1, 1, };
1086static int x1000_uart1_hwflow_d_funcs[] = { 1, 1, };1110static int x1000_uart1_hwflow_funcs[] = { 1, 1, };
1087static int x1000_uart2_data_a_funcs[] = { 2, 2, };1111static int x1000_uart2_data_a_funcs[] = { 2, 2, };
1088static int x1000_uart2_data_d_funcs[] = { 0, 0, };1112static int x1000_uart2_data_d_funcs[] = { 0, 0, };
1113static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
1114static int x1000_ssi_dt_a_22_funcs[] = { 2, };
1115static int x1000_ssi_dt_a_29_funcs[] = { 2, };
1116static int x1000_ssi_dt_d_funcs[] = { 0, };
1117static int x1000_ssi_dr_a_23_funcs[] = { 2, };
1118static int x1000_ssi_dr_a_28_funcs[] = { 2, };
1119static int x1000_ssi_dr_d_funcs[] = { 0, };
1120static int x1000_ssi_clk_a_24_funcs[] = { 2, };
1121static int x1000_ssi_clk_a_26_funcs[] = { 2, };
1122static int x1000_ssi_clk_d_funcs[] = { 0, };
1123static int x1000_ssi_gpc_a_20_funcs[] = { 2, };
1124static int x1000_ssi_gpc_a_31_funcs[] = { 2, };
1125static int x1000_ssi_ce0_a_25_funcs[] = { 2, };
1126static int x1000_ssi_ce0_a_27_funcs[] = { 2, };
1127static int x1000_ssi_ce0_d_funcs[] = { 0, };
1128static int x1000_ssi_ce1_a_21_funcs[] = { 2, };
1129static int x1000_ssi_ce1_a_30_funcs[] = { 2, };
1089static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };1130static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };
1090static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };1131static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };
1091static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };1132static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };
1092static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };1133static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };
1093static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };1134static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };
1094static int x1000_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };1135static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1095static int x1000_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };1136static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1096static int x1000_nemc_addr_funcs[] = {1137static int x1000_emc_addr_funcs[] = {
1097 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,1138 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1098};1139};
1099static int x1000_nemc_rd_we_funcs[] = { 0, 0, };1140static int x1000_emc_rd_we_funcs[] = { 0, 0, };
1100static int x1000_nemc_wait_funcs[] = { 0, };1141static int x1000_emc_wait_funcs[] = { 0, };
1101static int x1000_nemc_cs1_funcs[] = { 0, };1142static int x1000_emc_cs1_funcs[] = { 0, };
1102static int x1000_nemc_cs2_funcs[] = { 0, };1143static int x1000_emc_cs2_funcs[] = { 0, };
1103static int x1000_i2c0_funcs[] = { 0, 0, };1144static int x1000_i2c0_funcs[] = { 0, 0, };
1104static int x1000_i2c1_a_funcs[] = { 2, 2, };1145static int x1000_i2c1_a_funcs[] = { 2, 2, };
1105static int x1000_i2c1_c_funcs[] = { 0, 0, };1146static int x1000_i2c1_c_funcs[] = { 0, 0, };
@@ -1121,21 +1162,38 @@ static const struct group_desc x1000_groups[] = { · 15 unmodified lines
1121 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),1162 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
1122 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),1163 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
1123 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),1164 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
1124 INGENIC_PIN_GROUP("uart1-hwflow-d", x1000_uart1_hwflow_d),1165 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow),
1125 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),1166 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
1126 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),1167 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
1168 INGENIC_PIN_GROUP("sfc", x1000_sfc),
1169 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22),
1170 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29),
1171 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d),
1172 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23),
1173 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28),
1174 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d),
1175 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24),
1176 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26),
1177 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d),
1178 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20),
1179 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31),
1180 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25),
1181 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27),
1182 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d),
1183 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21),
1184 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30),
1127 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),1185 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
1128 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),1186 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
1129 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),1187 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
1130 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),1188 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
1131 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),1189 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
1132 INGENIC_PIN_GROUP("nemc-8bit-data", x1000_nemc_8bit_data),1190 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data),
1133 INGENIC_PIN_GROUP("nemc-16bit-data", x1000_nemc_16bit_data),1191 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data),
1134 INGENIC_PIN_GROUP("nemc-addr", x1000_nemc_addr),1192 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr),
1135 INGENIC_PIN_GROUP("nemc-rd-we", x1000_nemc_rd_we),1193 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we),
1136 INGENIC_PIN_GROUP("nemc-wait", x1000_nemc_wait),1194 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait),
1137 INGENIC_PIN_GROUP("nemc-cs1", x1000_nemc_cs1),1195 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1),
1138 INGENIC_PIN_GROUP("nemc-cs2", x1000_nemc_cs2),1196 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2),
1139 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),1197 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
1140 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),1198 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
1141 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),1199 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
@@ -1154,21 +1212,30 @@ static const struct group_desc x1000_groups[] = { · 12 unmodified lines
1154 1212
1155static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };1213static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1156static const char *x1000_uart1_groups[] = {1214static const char *x1000_uart1_groups[] = {
1157 "uart1-data-a", "uart1-data-d", "uart1-hwflow-d",1215 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
1158};1216};
1159static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };1217static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
1218static const char *x1000_sfc_groups[] = { "sfc", };
1219static const char *x1000_ssi_groups[] = {
1220 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
1221 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
1222 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
1223 "ssi-gpc-a-20", "ssi-gpc-a-31",
1224 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
1225 "ssi-ce1-a-21", "ssi-ce1-a-30",
1226};
1160static const char *x1000_mmc0_groups[] = {1227static const char *x1000_mmc0_groups[] = {
1161 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",1228 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
1162};1229};
1163static const char *x1000_mmc1_groups[] = {1230static const char *x1000_mmc1_groups[] = {
1164 "mmc1-1bit-e", "mmc1-4bit-e",1231 "mmc1-1bit", "mmc1-4bit",
1165};1232};
1166static const char *x1000_nemc_groups[] = {1233static const char *x1000_emc_groups[] = {
1167 "nemc-8bit-data", "nemc-16bit-data",1234 "emc-8bit-data", "emc-16bit-data",
1168 "nemc-addr", "nemc-rd-we", "nemc-wait",1235 "emc-addr", "emc-rd-we", "emc-wait",
1169};1236};
1170static const char *x1000_cs1_groups[] = { "nemc-cs1", };1237static const char *x1000_cs1_groups[] = { "emc-cs1", };
1171static const char *x1000_cs2_groups[] = { "nemc-cs2", };1238static const char *x1000_cs2_groups[] = { "emc-cs2", };
1172static const char *x1000_i2c0_groups[] = { "i2c0-data", };1239static const char *x1000_i2c0_groups[] = { "i2c0-data", };
1173static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };1240static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1174static const char *x1000_i2c2_groups[] = { "i2c2-data", };1241static const char *x1000_i2c2_groups[] = { "i2c2-data", };
@@ -1187,11 +1254,13 @@ static const struct function_desc x1000_functions[] = { · 12 unmodified lines
1187 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },1254 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
1188 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },1255 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
1189 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },1256 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
1257 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
1258 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
1190 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },1259 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
1191 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },1260 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
1192 { "nemc", x1000_nemc_groups, ARRAY_SIZE(x1000_nemc_groups), },1261 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
1193 { "nemc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },1262 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
1194 { "nemc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },1263 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
1195 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },1264 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
1196 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },1265 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
1197 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },1266 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
@@ -1207,16 +1276,8 @@ static const struct function_desc x1000_functions[] = { · 9 unmodified lines
1207 1276
1208static const struct ingenic_chip_info x1000_chip_info = {1277static const struct ingenic_chip_info x1000_chip_info = {
1209 .num_chips = 4,1278 .num_chips = 4,
1210 .groups = x1000_groups,1279 .reg_offset = 0x100,
1211 .num_groups = ARRAY_SIZE(x1000_groups),1280 .version = ID_X1000,
1212 .functions = x1000_functions,
1213 .num_functions = ARRAY_SIZE(x1000_functions),
1214 .pull_ups = x1000_pull_ups,
1215 .pull_downs = x1000_pull_downs,
1216};
1217
1218static const struct ingenic_chip_info x1000e_chip_info = {
1219 .num_chips = 4,
1220 .groups = x1000_groups,1281 .groups = x1000_groups,
1221 .num_groups = ARRAY_SIZE(x1000_groups),1282 .num_groups = ARRAY_SIZE(x1000_groups),
1222 .functions = x1000_functions,1283 .functions = x1000_functions,
@@ -1229,11 +1290,11 @@ static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; · 6 unmodified lines
1229static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };1290static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1230static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };1291static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
1231static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };1292static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
1232static int x1500_uart1_hwflow_d_pins[] = { 0x64, 0x65, };1293static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
1233static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };1294static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
1234static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };1295static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
1235static int x1500_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };1296static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
1236static int x1500_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };1297static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
1237static int x1500_i2c0_pins[] = { 0x38, 0x37, };1298static int x1500_i2c0_pins[] = { 0x38, 0x37, };
1238static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };1299static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
1239static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };1300static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
@@ -1252,11 +1313,11 @@ static int x1500_uart0_data_funcs[] = { 0, 0, }; · 12 unmodified lines
1252static int x1500_uart0_hwflow_funcs[] = { 0, 0, };1313static int x1500_uart0_hwflow_funcs[] = { 0, 0, };
1253static int x1500_uart1_data_a_funcs[] = { 2, 2, };1314static int x1500_uart1_data_a_funcs[] = { 2, 2, };
1254static int x1500_uart1_data_d_funcs[] = { 1, 1, };1315static int x1500_uart1_data_d_funcs[] = { 1, 1, };
1255static int x1500_uart1_hwflow_d_funcs[] = { 1, 1, };1316static int x1500_uart1_hwflow_funcs[] = { 1, 1, };
1256static int x1500_uart2_data_a_funcs[] = { 2, 2, };1317static int x1500_uart2_data_a_funcs[] = { 2, 2, };
1257static int x1500_uart2_data_d_funcs[] = { 0, 0, };1318static int x1500_uart2_data_d_funcs[] = { 0, 0, };
1258static int x1500_mmc0_1bit_funcs[] = { 1, 1, 1, };1319static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, };
1259static int x1500_mmc0_4bit_funcs[] = { 1, 1, 1, };1320static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, };
1260static int x1500_i2c0_funcs[] = { 0, 0, };1321static int x1500_i2c0_funcs[] = { 0, 0, };
1261static int x1500_i2c1_a_funcs[] = { 2, 2, };1322static int x1500_i2c1_a_funcs[] = { 2, 2, };
1262static int x1500_i2c1_c_funcs[] = { 0, 0, };1323static int x1500_i2c1_c_funcs[] = { 0, 0, };
@@ -1273,11 +1334,12 @@ static const struct group_desc x1500_groups[] = { · 10 unmodified lines
1273 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),1334 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),
1274 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),1335 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),
1275 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),1336 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),
1276 INGENIC_PIN_GROUP("uart1-hwflow-d", x1500_uart1_hwflow_d),1337 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow),
1277 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),1338 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),
1278 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),1339 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),
1279 INGENIC_PIN_GROUP("mmc0-1bit", x1500_mmc0_1bit),1340 INGENIC_PIN_GROUP("sfc", x1000_sfc),
1280 INGENIC_PIN_GROUP("mmc0-4bit", x1500_mmc0_4bit),1341 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit),
1342 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit),
1281 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),1343 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),
1282 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),1344 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
1283 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),1345 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
@@ -1293,10 +1355,10 @@ static const struct group_desc x1500_groups[] = { · 9 unmodified lines
1293 1355
1294static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };1356static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1295static const char *x1500_uart1_groups[] = {1357static const char *x1500_uart1_groups[] = {
1296 "uart1-data-a", "uart1-data-d", "uart1-hwflow-d",1358 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
1297};1359};
1298static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };1360static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
1299static const char *x1500_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };1361static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
1300static const char *x1500_i2c0_groups[] = { "i2c0-data", };1362static const char *x1500_i2c0_groups[] = { "i2c0-data", };
1301static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };1363static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1302static const char *x1500_i2c2_groups[] = { "i2c2-data", };1364static const char *x1500_i2c2_groups[] = { "i2c2-data", };
@@ -1312,7 +1374,8 @@ static const struct function_desc x1500_functions[] = { · 9 unmodified lines
1312 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },1374 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
1313 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },1375 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
1314 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },1376 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
1315 { "mmc0", x1500_mmc0_groups, ARRAY_SIZE(x1500_mmc0_groups), },1377 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
1378 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
1316 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },1379 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
1317 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },1380 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
1318 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },1381 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
@@ -1327,6 +1390,8 @@ static const struct function_desc x1500_functions[] = { · 8 unmodified lines
1327 1390
1328static const struct ingenic_chip_info x1500_chip_info = {1391static const struct ingenic_chip_info x1500_chip_info = {
1329 .num_chips = 4,1392 .num_chips = 4,
1393 .reg_offset = 0x100,
1394 .version = ID_X1500,
1330 .groups = x1500_groups,1395 .groups = x1500_groups,
1331 .num_groups = ARRAY_SIZE(x1500_groups),1396 .num_groups = ARRAY_SIZE(x1500_groups),
1332 .functions = x1500_functions,1397 .functions = x1500_functions,
@@ -1335,6 +1400,222 @@ static const struct ingenic_chip_info x1500_chip_info = { · 2 unmodified lines
1335 .pull_downs = x1000_pull_downs,1400 .pull_downs = x1000_pull_downs,
1336};1401};
1337 1402
1403static const u32 x1830_pull_ups[4] = {
1404 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1405};
1406
1407static const u32 x1830_pull_downs[4] = {
1408 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1409};
1410
1411static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
1412static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
1413static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
1414static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, };
1415static int x1830_ssi0_dt_pins[] = { 0x4c, };
1416static int x1830_ssi0_dr_pins[] = { 0x4b, };
1417static int x1830_ssi0_clk_pins[] = { 0x4f, };
1418static int x1830_ssi0_gpc_pins[] = { 0x4d, };
1419static int x1830_ssi0_ce0_pins[] = { 0x50, };
1420static int x1830_ssi0_ce1_pins[] = { 0x4e, };
1421static int x1830_ssi1_dt_c_pins[] = { 0x53, };
1422static int x1830_ssi1_dr_c_pins[] = { 0x54, };
1423static int x1830_ssi1_clk_c_pins[] = { 0x57, };
1424static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
1425static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
1426static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
1427static int x1830_ssi1_dt_d_pins[] = { 0x62, };
1428static int x1830_ssi1_dr_d_pins[] = { 0x63, };
1429static int x1830_ssi1_clk_d_pins[] = { 0x66, };
1430static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
1431static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
1432static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
1433static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
1434static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
1435static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
1436static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
1437static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
1438static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
1439static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
1440static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
1441static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
1442static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
1443static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
1444static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
1445static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
1446static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
1447static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
1448static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
1449static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
1450static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
1451static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
1452static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
1453static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
1454static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
1455static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
1456static int x1830_mac_pins[] = {
1457 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
1458};
1459
1460static int x1830_uart0_data_funcs[] = { 0, 0, };
1461static int x1830_uart0_hwflow_funcs[] = { 0, 0, };
1462static int x1830_uart1_data_funcs[] = { 0, 0, };
1463static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
1464static int x1830_ssi0_dt_funcs[] = { 0, };
1465static int x1830_ssi0_dr_funcs[] = { 0, };
1466static int x1830_ssi0_clk_funcs[] = { 0, };
1467static int x1830_ssi0_gpc_funcs[] = { 0, };
1468static int x1830_ssi0_ce0_funcs[] = { 0, };
1469static int x1830_ssi0_ce1_funcs[] = { 0, };
1470static int x1830_ssi1_dt_c_funcs[] = { 1, };
1471static int x1830_ssi1_dr_c_funcs[] = { 1, };
1472static int x1830_ssi1_clk_c_funcs[] = { 1, };
1473static int x1830_ssi1_gpc_c_funcs[] = { 1, };
1474static int x1830_ssi1_ce0_c_funcs[] = { 1, };
1475static int x1830_ssi1_ce1_c_funcs[] = { 1, };
1476static int x1830_ssi1_dt_d_funcs[] = { 2, };
1477static int x1830_ssi1_dr_d_funcs[] = { 2, };
1478static int x1830_ssi1_clk_d_funcs[] = { 2, };
1479static int x1830_ssi1_gpc_d_funcs[] = { 2, };
1480static int x1830_ssi1_ce0_d_funcs[] = { 2, };
1481static int x1830_ssi1_ce1_d_funcs[] = { 2, };
1482static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, };
1483static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, };
1484static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, };
1485static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, };
1486static int x1830_i2c0_funcs[] = { 1, 1, };
1487static int x1830_i2c1_funcs[] = { 0, 0, };
1488static int x1830_i2c2_funcs[] = { 1, 1, };
1489static int x1830_pwm_pwm0_b_funcs[] = { 0, };
1490static int x1830_pwm_pwm0_c_funcs[] = { 1, };
1491static int x1830_pwm_pwm1_b_funcs[] = { 0, };
1492static int x1830_pwm_pwm1_c_funcs[] = { 1, };
1493static int x1830_pwm_pwm2_c_8_funcs[] = { 0, };
1494static int x1830_pwm_pwm2_c_13_funcs[] = { 1, };
1495static int x1830_pwm_pwm3_c_9_funcs[] = { 0, };
1496static int x1830_pwm_pwm3_c_14_funcs[] = { 1, };
1497static int x1830_pwm_pwm4_c_15_funcs[] = { 1, };
1498static int x1830_pwm_pwm4_c_25_funcs[] = { 0, };
1499static int x1830_pwm_pwm5_c_16_funcs[] = { 1, };
1500static int x1830_pwm_pwm5_c_26_funcs[] = { 0, };
1501static int x1830_pwm_pwm6_c_17_funcs[] = { 1, };
1502static int x1830_pwm_pwm6_c_27_funcs[] = { 0, };
1503static int x1830_pwm_pwm7_c_18_funcs[] = { 1, };
1504static int x1830_pwm_pwm7_c_28_funcs[] = { 0, };
1505static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1506
1507static const struct group_desc x1830_groups[] = {
1508 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data),
1509 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow),
1510 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data),
1511 INGENIC_PIN_GROUP("sfc", x1830_sfc),
1512 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt),
1513 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr),
1514 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk),
1515 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc),
1516 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0),
1517 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1),
1518 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c),
1519 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c),
1520 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c),
1521 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c),
1522 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c),
1523 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c),
1524 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d),
1525 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d),
1526 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d),
1527 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d),
1528 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d),
1529 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d),
1530 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit),
1531 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit),
1532 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit),
1533 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit),
1534 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0),
1535 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1),
1536 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2),
1537 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b),
1538 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c),
1539 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b),
1540 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c),
1541 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8),
1542 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13),
1543 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9),
1544 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14),
1545 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15),
1546 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25),
1547 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16),
1548 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26),
1549 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17),
1550 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27),
1551 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18),
1552 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28),
1553 INGENIC_PIN_GROUP("mac", x1830_mac),
1554};
1555
1556static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1557static const char *x1830_uart1_groups[] = { "uart1-data", };
1558static const char *x1830_sfc_groups[] = { "sfc", };
1559static const char *x1830_ssi0_groups[] = {
1560 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
1561};
1562static const char *x1830_ssi1_groups[] = {
1563 "ssi1-dt-c", "ssi1-dt-d",
1564 "ssi1-dr-c", "ssi1-dr-d",
1565 "ssi1-clk-c", "ssi1-clk-d",
1566 "ssi1-gpc-c", "ssi1-gpc-d",
1567 "ssi1-ce0-c", "ssi1-ce0-d",
1568 "ssi1-ce1-c", "ssi1-ce1-d",
1569};
1570static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
1571static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
1572static const char *x1830_i2c0_groups[] = { "i2c0-data", };
1573static const char *x1830_i2c1_groups[] = { "i2c1-data", };
1574static const char *x1830_i2c2_groups[] = { "i2c2-data", };
1575static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
1576static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
1577static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
1578static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
1579static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
1580static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
1581static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
1582static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
1583static const char *x1830_mac_groups[] = { "mac", };
1584
1585static const struct function_desc x1830_functions[] = {
1586 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
1587 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
1588 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
1589 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
1590 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
1591 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
1592 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
1593 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
1594 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
1595 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
1596 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
1597 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
1598 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
1599 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
1600 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1601 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1602 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1603 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1604 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
1605};
1606
1607static const struct ingenic_chip_info x1830_chip_info = {
1608 .num_chips = 4,
1609 .reg_offset = 0x1000,
1610 .version = ID_X1830,
1611 .groups = x1830_groups,
1612 .num_groups = ARRAY_SIZE(x1830_groups),
1613 .functions = x1830_functions,
1614 .num_functions = ARRAY_SIZE(x1830_functions),
1615 .pull_ups = x1830_pull_ups,
1616 .pull_downs = x1830_pull_downs,
1617};
1618
1338static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)1619static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
1339{1620{
1340 unsigned int val;1621 unsigned int val;
@@ -1363,12 +1644,14 @@ static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, · 22 unmodified lines
1363 else1644 else
1364 reg = REG_CLEAR(reg);1645 reg = REG_CLEAR(reg);
1365 1646
1366 regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset));1647 regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
1648 jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
1367}1649}
1368 1650
1369static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)1651static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
1370{1652{
1371 regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_GID2LD,1653 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
1654 jzgc->jzpc->info->reg_offset),
1372 jzgc->gc.base / PINS_PER_GPIO_CHIP);1655 jzgc->gc.base / PINS_PER_GPIO_CHIP);
1373}1656}
1374 1657
@@ -1383,7 +1666,7 @@ static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, · 8 unmodified lines
1383static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,1666static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
1384 u8 offset, int value)1667 u8 offset, int value)
1385{1668{
1386 if (jzgc->jzpc->version >= ID_JZ4760)1669 if (jzgc->jzpc->info->version >= ID_JZ4760)
1387 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value);1670 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value);
1388 else1671 else
1389 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);1672 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
@@ -1393,58 +1676,42 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, · 3 unmodified lines
1393 u8 offset, unsigned int type)1676 u8 offset, unsigned int type)
1394{1677{
1395 u8 reg1, reg2;1678 u8 reg1, reg2;
1396 1679 bool val1, val2;
1397 if (jzgc->jzpc->version >= ID_JZ4760) {
1398 reg1 = JZ4760_GPIO_PAT1;
1399 reg2 = JZ4760_GPIO_PAT0;
1400 } else {
1401 reg1 = JZ4740_GPIO_TRIG;
1402 reg2 = JZ4740_GPIO_DIR;
1403 }
1404 1680
1405 switch (type) {1681 switch (type) {
1406 case IRQ_TYPE_EDGE_RISING:1682 case IRQ_TYPE_EDGE_RISING:
1407 if (jzgc->jzpc->version >= ID_X1000) {1683 val1 = val2 = true;
1408 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);
1409 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);
1410 ingenic_gpio_shadow_set_bit_load(jzgc);
1411 } else {
1412 ingenic_gpio_set_bit(jzgc, reg2, offset, true);
1413 ingenic_gpio_set_bit(jzgc, reg1, offset, true);
1414 }
1415 break;1684 break;
1416 case IRQ_TYPE_EDGE_FALLING:1685 case IRQ_TYPE_EDGE_FALLING:
1417 if (jzgc->jzpc->version >= ID_X1000) {1686 val1 = false;
1418 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);1687 val2 = true;
1419 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);
1420 ingenic_gpio_shadow_set_bit_load(jzgc);
1421 } else {
1422 ingenic_gpio_set_bit(jzgc, reg2, offset, false);
1423 ingenic_gpio_set_bit(jzgc, reg1, offset, true);
1424 }
1425 break;1688 break;
1426 case IRQ_TYPE_LEVEL_HIGH:1689 case IRQ_TYPE_LEVEL_HIGH:
1427 if (jzgc->jzpc->version >= ID_X1000) {1690 val1 = true;
1428 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);1691 val2 = false;
1429 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);
1430 ingenic_gpio_shadow_set_bit_load(jzgc);
1431 } else {
1432 ingenic_gpio_set_bit(jzgc, reg2, offset, true);
1433 ingenic_gpio_set_bit(jzgc, reg1, offset, false);
1434 }
1435 break;1692 break;
1436 case IRQ_TYPE_LEVEL_LOW:1693 case IRQ_TYPE_LEVEL_LOW:
1437 default:1694 default:
1438 if (jzgc->jzpc->version >= ID_X1000) {1695 val1 = val2 = false;
1439 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);
1440 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);
1441 ingenic_gpio_shadow_set_bit_load(jzgc);
1442 } else {
1443 ingenic_gpio_set_bit(jzgc, reg2, offset, false);
1444 ingenic_gpio_set_bit(jzgc, reg1, offset, false);
1445 }
1446 break;1696 break;
1447 }1697 }
1698
1699 if (jzgc->jzpc->info->version >= ID_JZ4760) {
1700 reg1 = JZ4760_GPIO_PAT1;
1701 reg2 = JZ4760_GPIO_PAT0;
1702 } else {
1703 reg1 = JZ4740_GPIO_TRIG;
1704 reg2 = JZ4740_GPIO_DIR;
1705 }
1706
1707 if (jzgc->jzpc->info->version >= ID_X1000) {
1708 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
1709 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
1710 ingenic_gpio_shadow_set_bit_load(jzgc);
1711 } else {
1712 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
1713 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
1714 }
1448}1715}
1449 1716
1450static void ingenic_gpio_irq_mask(struct irq_data *irqd)1717static void ingenic_gpio_irq_mask(struct irq_data *irqd)
@@ -1469,7 +1736,7 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd) · 18 unmodified lines
1469 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);1736 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1470 int irq = irqd->hwirq;1737 int irq = irqd->hwirq;
1471 1738
1472 if (jzgc->jzpc->version >= ID_JZ4760)1739 if (jzgc->jzpc->info->version >= ID_JZ4760)
1473 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true);1740 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true);
1474 else1741 else
1475 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);1742 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
@@ -1485,7 +1752,7 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd) · 9 unmodified lines
1485 1752
1486 ingenic_gpio_irq_mask(irqd);1753 ingenic_gpio_irq_mask(irqd);
1487 1754
1488 if (jzgc->jzpc->version >= ID_JZ4760)1755 if (jzgc->jzpc->info->version >= ID_JZ4760)
1489 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false);1756 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false);
1490 else1757 else
1491 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);1758 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
@@ -1510,7 +1777,7 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd) · 18 unmodified lines
1510 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);1777 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
1511 }1778 }
1512 1779
1513 if (jzgc->jzpc->version >= ID_JZ4760)1780 if (jzgc->jzpc->info->version >= ID_JZ4760)
1514 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false);1781 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false);
1515 else1782 else
1516 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);1783 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
@@ -1567,7 +1834,7 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc) · 50 unmodified lines
1567 1834
1568 chained_irq_enter(irq_chip, desc);1835 chained_irq_enter(irq_chip, desc);
1569 1836
1570 if (jzgc->jzpc->version >= ID_JZ4760)1837 if (jzgc->jzpc->info->version >= ID_JZ4760)
1571 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG);1838 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG);
1572 else1839 else
1573 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);1840 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
@@ -1611,7 +1878,7 @@ static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, · 37 unmodified lines
1611 unsigned int idx = pin % PINS_PER_GPIO_CHIP;1878 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1612 unsigned int offt = pin / PINS_PER_GPIO_CHIP;1879 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1613 1880
1614 regmap_write(jzpc->map, offt * 0x100 +1881 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
1615 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));1882 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1616}1883}
1617 1884
@@ -1620,14 +1887,15 @@ static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, · 2 unmodified lines
1620{1887{
1621 unsigned int idx = pin % PINS_PER_GPIO_CHIP;1888 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1622 1889
1623 regmap_write(jzpc->map, X1000_GPIO_PZ_BASE +1890 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
1624 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));1891 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1625}1892}
1626 1893
1627static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,1894static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
1628 unsigned int pin)1895 unsigned int pin)
1629{1896{
1630 regmap_write(jzpc->map, X1000_GPIO_PZ_GID2LD, pin / PINS_PER_GPIO_CHIP);1897 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
1898 pin / PINS_PER_GPIO_CHIP);
1631}1899}
1632 1900
1633static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,1901static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
@@ -1637,7 +1905,7 @@ static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, · 3 unmodified lines
1637 unsigned int offt = pin / PINS_PER_GPIO_CHIP;1905 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1638 unsigned int val;1906 unsigned int val;
1639 1907
1640 regmap_read(jzpc->map, offt * 0x100 + reg, &val);1908 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
1641 1909
1642 return val & BIT(idx);1910 return val & BIT(idx);
1643}1911}
@@ -1648,7 +1916,7 @@ static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) · 4 unmodified lines
1648 struct ingenic_pinctrl *jzpc = jzgc->jzpc;1916 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
1649 unsigned int pin = gc->base + offset;1917 unsigned int pin = gc->base + offset;
1650 1918
1651 if (jzpc->version >= ID_JZ4760)1919 if (jzpc->info->version >= ID_JZ4760)
1652 return ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1);1920 return ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1);
1653 1921
1654 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))1922 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
@@ -1674,13 +1942,13 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, · 19 unmodified lines
1674 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",1942 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
1675 'A' + offt, idx, func);1943 'A' + offt, idx, func);
1676 1944
1677 if (jzpc->version >= ID_X1000) {1945 if (jzpc->info->version >= ID_X1000) {
1678 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);1946 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
1679 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);1947 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
1680 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);1948 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
1681 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);1949 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
1682 ingenic_shadow_config_pin_load(jzpc, pin);1950 ingenic_shadow_config_pin_load(jzpc, pin);
1683 } else if (jzpc->version >= ID_JZ4760) {1951 } else if (jzpc->info->version >= ID_JZ4760) {
1684 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);1952 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
1685 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);1953 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
1686 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);1954 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
@@ -1733,12 +2001,12 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, · 46 unmodified lines
1733 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",2001 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
1734 'A' + offt, idx, input ? "in" : "out");2002 'A' + offt, idx, input ? "in" : "out");
1735 2003
1736 if (jzpc->version >= ID_X1000) {2004 if (jzpc->info->version >= ID_X1000) {
1737 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);2005 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
1738 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);2006 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
1739 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);2007 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
1740 ingenic_shadow_config_pin_load(jzpc, pin);2008 ingenic_shadow_config_pin_load(jzpc, pin);
1741 } else if (jzpc->version >= ID_JZ4760) {2009 } else if (jzpc->info->version >= ID_JZ4760) {
1742 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);2010 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
1743 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);2011 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
1744 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);2012 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
@@ -1768,7 +2036,7 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, · 23 unmodified lines
1768 unsigned int offt = pin / PINS_PER_GPIO_CHIP;2036 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1769 bool pull;2037 bool pull;
1770 2038
1771 if (jzpc->version >= ID_JZ4760)2039 if (jzpc->info->version >= ID_JZ4760)
1772 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN);2040 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN);
1773 else2041 else
1774 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);2042 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
@@ -1798,18 +2066,37 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, · 23 unmodified lines
1798}2066}
1799 2067
1800static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,2068static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
1801 unsigned int pin, bool enabled)2069 unsigned int pin, unsigned int bias)
1802{2070{
1803 if (jzpc->version >= ID_JZ4760)2071 if (jzpc->info->version >= ID_X1830) {
1804 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !enabled);2072 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1805 else2073 unsigned int half = PINS_PER_GPIO_CHIP / 2;
1806 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled);2074 unsigned int idxh = pin % half * 2;
2075 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2076
2077 if (idx < half) {
2078 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2079 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
2080 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2081 REG_SET(X1830_GPIO_PEL), bias << idxh);
2082 } else {
2083 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2084 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
2085 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2086 REG_SET(X1830_GPIO_PEH), bias << idxh);
2087 }
2088
2089 } else if (jzpc->info->version >= ID_JZ4760) {
2090 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias);
2091 } else {
2092 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
2093 }
1807}2094}
1808 2095
1809static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,2096static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
1810 unsigned int pin, bool high)2097 unsigned int pin, bool high)
1811{2098{
1812 if (jzpc->version >= ID_JZ4760)2099 if (jzpc->info->version >= ID_JZ4760)
1813 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high);2100 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high);
1814 else2101 else
1815 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);2102 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
@@ -1843,7 +2130,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 27 unmodified lines
1843 case PIN_CONFIG_BIAS_DISABLE:2130 case PIN_CONFIG_BIAS_DISABLE:
1844 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",2131 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
1845 'A' + offt, idx);2132 'A' + offt, idx);
1846 ingenic_set_bias(jzpc, pin, false);2133 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
1847 break;2134 break;
1848 2135
1849 case PIN_CONFIG_BIAS_PULL_UP:2136 case PIN_CONFIG_BIAS_PULL_UP:
@@ -1851,7 +2138,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 1 unmodified line
1851 return -EINVAL;2138 return -EINVAL;
1852 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",2139 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
1853 'A' + offt, idx);2140 'A' + offt, idx);
1854 ingenic_set_bias(jzpc, pin, true);2141 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
1855 break;2142 break;
1856 2143
1857 case PIN_CONFIG_BIAS_PULL_DOWN:2144 case PIN_CONFIG_BIAS_PULL_DOWN:
@@ -1859,7 +2146,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 1 unmodified line
1859 return -EINVAL;2146 return -EINVAL;
1860 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",2147 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
1861 'A' + offt, idx);2148 'A' + offt, idx);
1862 ingenic_set_bias(jzpc, pin, true);2149 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
1863 break;2150 break;
1864 2151
1865 case PIN_CONFIG_OUTPUT:2152 case PIN_CONFIG_OUTPUT:
@@ -1939,25 +2226,13 @@ static const struct regmap_config ingenic_pinctrl_regmap_config = { · 73 unmodified lines
1939 .reg_stride = 4,2226 .reg_stride = 4,
1940};2227};
1941 2228
1942static const struct of_device_id ingenic_pinctrl_of_match[] = {
1943 { .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 },
1944 { .compatible = "ingenic,jz4725b-pinctrl", .data = (void *)ID_JZ4725B },
1945 { .compatible = "ingenic,jz4760-pinctrl", .data = (void *) ID_JZ4760 },
1946 { .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B },
1947 { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 },
1948 { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 },
1949 { .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 },
1950 { .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E },
1951 { .compatible = "ingenic,x1500-pinctrl", .data = (void *) ID_X1500 },
1952 {},
1953};
1954
1955static const struct of_device_id ingenic_gpio_of_match[] __initconst = {2229static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
1956 { .compatible = "ingenic,jz4740-gpio", },2230 { .compatible = "ingenic,jz4740-gpio", },
1957 { .compatible = "ingenic,jz4760-gpio", },2231 { .compatible = "ingenic,jz4760-gpio", },
1958 { .compatible = "ingenic,jz4770-gpio", },2232 { .compatible = "ingenic,jz4770-gpio", },
1959 { .compatible = "ingenic,jz4780-gpio", },2233 { .compatible = "ingenic,jz4780-gpio", },
1960 { .compatible = "ingenic,x1000-gpio", },2234 { .compatible = "ingenic,x1000-gpio", },
2235 { .compatible = "ingenic,x1830-gpio", },
1961 {},2236 {},
1962};2237};
1963 2238
@@ -1981,7 +2256,7 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, · 17 unmodified lines
1981 return -ENOMEM;2256 return -ENOMEM;
1982 2257
1983 jzgc->jzpc = jzpc;2258 jzgc->jzpc = jzpc;
1984 jzgc->reg_base = bank * 0x100;2259 jzgc->reg_base = bank * jzpc->info->reg_offset;
1985 2260
1986 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);2261 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
1987 if (!jzgc->gc.label)2262 if (!jzgc->gc.label)
@@ -2048,9 +2323,6 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) · 60 unmodified lines
2048 struct ingenic_pinctrl *jzpc;2323 struct ingenic_pinctrl *jzpc;
2049 struct pinctrl_desc *pctl_desc;2324 struct pinctrl_desc *pctl_desc;
2050 void __iomem *base;2325 void __iomem *base;
2051 const struct platform_device_id *id = platform_get_device_id(pdev);
2052 const struct of_device_id *of_id = of_match_device(
2053 ingenic_pinctrl_of_match, dev);
2054 const struct ingenic_chip_info *chip_info;2326 const struct ingenic_chip_info *chip_info;
2055 struct device_node *node;2327 struct device_node *node;
2056 unsigned int i;2328 unsigned int i;
@@ -2060,8 +2332,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) · 3 unmodified lines
2060 if (!jzpc)2332 if (!jzpc)
2061 return -ENOMEM;2333 return -ENOMEM;
2062 2334
2063 base = devm_ioremap_resource(dev,2335 base = devm_platform_ioremap_resource(pdev, 0);
2064 platform_get_resource(pdev, IORESOURCE_MEM, 0));
2065 if (IS_ERR(base))2336 if (IS_ERR(base))
2066 return PTR_ERR(base);2337 return PTR_ERR(base);
2067 2338
@@ -2073,31 +2344,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) · 5 unmodified lines
2073 }2344 }
2074 2345
2075 jzpc->dev = dev;2346 jzpc->dev = dev;
2076 2347 jzpc->info = chip_info = of_device_get_match_data(dev);
2077 if (of_id)
2078 jzpc->version = (enum jz_version)of_id->data;
2079 else
2080 jzpc->version = (enum jz_version)id->driver_data;
2081
2082 if (jzpc->version >= ID_X1500)
2083 chip_info = &x1500_chip_info;
2084 else if (jzpc->version >= ID_X1000E)
2085 chip_info = &x1000e_chip_info;
2086 else if (jzpc->version >= ID_X1000)
2087 chip_info = &x1000_chip_info;
2088 else if (jzpc->version >= ID_JZ4780)
2089 chip_info = &jz4780_chip_info;
2090 else if (jzpc->version >= ID_JZ4770)
2091 chip_info = &jz4770_chip_info;
2092 else if (jzpc->version >= ID_JZ4760B)
2093 chip_info = &jz4760b_chip_info;
2094 else if (jzpc->version >= ID_JZ4760)
2095 chip_info = &jz4760_chip_info;
2096 else if (jzpc->version >= ID_JZ4725B)
2097 chip_info = &jz4725b_chip_info;
2098 else
2099 chip_info = &jz4740_chip_info;
2100 jzpc->info = chip_info;
2101 2348
2102 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);2349 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
2103 if (!pctl_desc)2350 if (!pctl_desc)
@@ -2166,25 +2413,25 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) · 62 unmodified lines
2166 return 0;2413 return 0;
2167}2414}
2168 2415
2169static const struct platform_device_id ingenic_pinctrl_ids[] = {2416static const struct of_device_id ingenic_pinctrl_of_match[] = {
2170 { "jz4740-pinctrl", ID_JZ4740 },2417 { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info },
2171 { "jz4725b-pinctrl", ID_JZ4725B },2418 { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info },
2172 { "jz4760-pinctrl", ID_JZ4760 },2419 { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info },
2173 { "jz4760b-pinctrl", ID_JZ4760B },2420 { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info },
2174 { "jz4770-pinctrl", ID_JZ4770 },2421 { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info },
2175 { "jz4780-pinctrl", ID_JZ4780 },2422 { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info },
2176 { "x1000-pinctrl", ID_X1000 },2423 { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info },
2177 { "x1000e-pinctrl", ID_X1000E },2424 { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info },
2178 { "x1500-pinctrl", ID_X1500 },2425 { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info },
2426 { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info },
2179 {},2427 {},
2180};2428};
2181 2429
2182static struct platform_driver ingenic_pinctrl_driver = {2430static struct platform_driver ingenic_pinctrl_driver = {
2183 .driver = {2431 .driver = {
2184 .name = "pinctrl-ingenic",2432 .name = "pinctrl-ingenic",
2185 .of_match_table = of_match_ptr(ingenic_pinctrl_of_match),2433 .of_match_table = ingenic_pinctrl_of_match,
2186 },2434 },
2187 .id_table = ingenic_pinctrl_ids,
2188};2435};
2189 2436
2190static int __init ingenic_pinctrl_drv_register(void)2437static int __init ingenic_pinctrl_drv_register(void)
drivers/pinctrl/pinctrl-rza1.c+2−2
@@ -1229,8 +1229,8 @@ static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl, · 1228 unmodified lines
1229 1229
1230 pinctrl_add_gpio_range(rza1_pctl->pctl, range);1230 pinctrl_add_gpio_range(rza1_pctl->pctl, range);
1231 1231
1232 dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",1232 dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
1233 chip->label, chip->ngpio);1233 chip->label, chip->ngpio);
1234 1234
1235 return 0;1235 return 0;
1236}1236}
drivers/pinctrl/qcom/pinctrl-msm.c+0−5
@@ -960,7 +960,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) · 959 unmodified lines
960{960{
961 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);961 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
962 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);962 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
963 unsigned long flags;
964 963
965 /*964 /*
966 * While they may not wake up when the TLMM is powered off,965 * While they may not wake up when the TLMM is powered off,
@@ -971,12 +970,8 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) · 4 unmodified lines
971 if (d->parent_data)970 if (d->parent_data)
972 irq_chip_set_wake_parent(d, on);971 irq_chip_set_wake_parent(d, on);
973 972
974 raw_spin_lock_irqsave(&pctrl->lock, flags);
975
976 irq_set_irq_wake(pctrl->irq, on);973 irq_set_irq_wake(pctrl->irq, on);
977 974
978 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
979
980 return 0;975 return 0;
981}976}
982 977
drivers/pinctrl/qcom/pinctrl-msm8976.c+1−1
@@ -589,7 +589,7 @@ static const char * const blsp_uart5_groups[] = { · 588 unmodified lines
589static const char * const qdss_traceclk_a_groups[] = {589static const char * const qdss_traceclk_a_groups[] = {
590 "gpio46",590 "gpio46",
591};591};
592const char * const m_voc_groups[] = {592static const char * const m_voc_groups[] = {
593 "gpio123", "gpio124",593 "gpio123", "gpio124",
594};594};
595static const char * const blsp_i2c5_groups[] = {595static const char * const blsp_i2c5_groups[] = {
drivers/pinctrl/qcom/pinctrl-sc7180.c+58−20
@@ -456,14 +456,18 @@ enum sc7180_functions { · 455 unmodified lines
456 msm_mux_qspi_data,456 msm_mux_qspi_data,
457 msm_mux_qup00,457 msm_mux_qup00,
458 msm_mux_qup01,458 msm_mux_qup01,
459 msm_mux_qup02,459 msm_mux_qup02_i2c,
460 msm_mux_qup02_uart,
460 msm_mux_qup03,461 msm_mux_qup03,
461 msm_mux_qup04,462 msm_mux_qup04_i2c,
463 msm_mux_qup04_uart,
462 msm_mux_qup05,464 msm_mux_qup05,
463 msm_mux_qup10,465 msm_mux_qup10,
464 msm_mux_qup11,466 msm_mux_qup11_i2c,
467 msm_mux_qup11_uart,
465 msm_mux_qup12,468 msm_mux_qup12,
466 msm_mux_qup13,469 msm_mux_qup13_i2c,
470 msm_mux_qup13_uart,
467 msm_mux_qup14,471 msm_mux_qup14,
468 msm_mux_qup15,472 msm_mux_qup15,
469 msm_mux_sdc1_tb,473 msm_mux_sdc1_tb,
@@ -543,7 +547,10 @@ static const char * const sdc1_tb_groups[] = { · 73 unmodified lines
543static const char * const sdc2_tb_groups[] = {547static const char * const sdc2_tb_groups[] = {
544 "gpio5",548 "gpio5",
545};549};
546static const char * const qup11_groups[] = {550static const char * const qup11_i2c_groups[] = {
551 "gpio6", "gpio7",
552};
553static const char * const qup11_uart_groups[] = {
547 "gpio6", "gpio7",554 "gpio6", "gpio7",
548};555};
549static const char * const ddr_bist_groups[] = {556static const char * const ddr_bist_groups[] = {
@@ -593,7 +600,10 @@ static const char * const qdss_groups[] = { · 43 unmodified lines
593static const char * const pll_reset_groups[] = {600static const char * const pll_reset_groups[] = {
594 "gpio14",601 "gpio14",
595};602};
596static const char * const qup02_groups[] = {603static const char * const qup02_i2c_groups[] = {
604 "gpio15", "gpio16",
605};
606static const char * const qup02_uart_groups[] = {
597 "gpio15", "gpio16",607 "gpio15", "gpio16",
598};608};
599static const char * const cci_i2c_groups[] = {609static const char * const cci_i2c_groups[] = {
@@ -698,7 +708,10 @@ static const char * const wlan1_adc1_groups[] = { · 98 unmodified lines
698static const char * const atest_usb13_groups[] = {708static const char * const atest_usb13_groups[] = {
699 "gpio44",709 "gpio44",
700};710};
701static const char * const qup13_groups[] = {711static const char * const qup13_i2c_groups[] = {
712 "gpio46", "gpio47",
713};
714static const char * const qup13_uart_groups[] = {
702 "gpio46", "gpio47",715 "gpio46", "gpio47",
703};716};
704static const char * const gcc_gp1_groups[] = {717static const char * const gcc_gp1_groups[] = {
@@ -848,7 +861,10 @@ static const char * const usb_phy_groups[] = { · 143 unmodified lines
848static const char * const mss_lte_groups[] = {861static const char * const mss_lte_groups[] = {
849 "gpio108", "gpio109",862 "gpio108", "gpio109",
850};863};
851static const char * const qup04_groups[] = {864static const char * const qup04_i2c_groups[] = {
865 "gpio115", "gpio116",
866};
867static const char * const qup04_uart_groups[] = {
852 "gpio115", "gpio116",868 "gpio115", "gpio116",
853};869};
854 870
@@ -929,14 +945,18 @@ static const struct msm_function sc7180_functions[] = { · 74 unmodified lines
929 FUNCTION(qspi_data),945 FUNCTION(qspi_data),
930 FUNCTION(qup00),946 FUNCTION(qup00),
931 FUNCTION(qup01),947 FUNCTION(qup01),
932 FUNCTION(qup02),948 FUNCTION(qup02_i2c),
949 FUNCTION(qup02_uart),
933 FUNCTION(qup03),950 FUNCTION(qup03),
934 FUNCTION(qup04),951 FUNCTION(qup04_i2c),
952 FUNCTION(qup04_uart),
935 FUNCTION(qup05),953 FUNCTION(qup05),
936 FUNCTION(qup10),954 FUNCTION(qup10),
937 FUNCTION(qup11),955 FUNCTION(qup11_i2c),
956 FUNCTION(qup11_uart),
938 FUNCTION(qup12),957 FUNCTION(qup12),
939 FUNCTION(qup13),958 FUNCTION(qup13_i2c),
959 FUNCTION(qup13_uart),
940 FUNCTION(qup14),960 FUNCTION(qup14),
941 FUNCTION(qup15),961 FUNCTION(qup15),
942 FUNCTION(sdc1_tb),962 FUNCTION(sdc1_tb),
@@ -976,8 +996,8 @@ static const struct msm_pingroup sc7180_groups[] = { · 33 unmodified lines
976 [3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, _, _, _, _, _),996 [3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, _, _, _, _, _),
977 [4] = PINGROUP(4, NORTH, sdc1_tb, _, qdss_cti, _, _, _, _, _, _),997 [4] = PINGROUP(4, NORTH, sdc1_tb, _, qdss_cti, _, _, _, _, _, _),
978 [5] = PINGROUP(5, NORTH, sdc2_tb, _, _, _, _, _, _, _, _),998 [5] = PINGROUP(5, NORTH, sdc2_tb, _, _, _, _, _, _, _, _),
979 [6] = PINGROUP(6, NORTH, qup11, qup11, _, _, _, _, _, _, _),999 [6] = PINGROUP(6, NORTH, qup11_i2c, qup11_uart, _, _, _, _, _, _, _),
980 [7] = PINGROUP(7, NORTH, qup11, qup11, ddr_bist, _, _, _, _, _, _),1000 [7] = PINGROUP(7, NORTH, qup11_i2c, qup11_uart, ddr_bist, _, _, _, _, _, _),
981 [8] = PINGROUP(8, NORTH, gp_pdm1, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _),1001 [8] = PINGROUP(8, NORTH, gp_pdm1, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _),
982 [9] = PINGROUP(9, NORTH, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _, _),1002 [9] = PINGROUP(9, NORTH, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _, _),
983 [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, _, _, _, _, _, _),1003 [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, _, _, _, _, _, _),
@@ -985,8 +1005,8 @@ static const struct msm_pingroup sc7180_groups[] = { · 1 unmodified line
985 [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, wlan2_adc0, atest_usb10, ddr_pxi3, _),1005 [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, wlan2_adc0, atest_usb10, ddr_pxi3, _),
986 [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _),1006 [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _),
987 [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),1007 [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
988 [15] = PINGROUP(15, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _),1008 [15] = PINGROUP(15, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _),
989 [16] = PINGROUP(16, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _),1009 [16] = PINGROUP(16, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _),
990 [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, wlan1_adc0, atest_usb12, ddr_pxi1, atest_char),1010 [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, wlan1_adc0, atest_usb12, ddr_pxi1, atest_char),
991 [18] = PINGROUP(18, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, vsense_trigger, ddr_pxi0, atest_char3, _),1011 [18] = PINGROUP(18, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, vsense_trigger, ddr_pxi0, atest_char3, _),
992 [19] = PINGROUP(19, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char2, _, _, _, _),1012 [19] = PINGROUP(19, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char2, _, _, _, _),
@@ -1016,8 +1036,8 @@ static const struct msm_pingroup sc7180_groups[] = { · 23 unmodified lines
1016 [43] = PINGROUP(43, NORTH, qup12, _, _, _, _, _, _, _, _),1036 [43] = PINGROUP(43, NORTH, qup12, _, _, _, _, _, _, _, _),
1017 [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),1037 [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
1018 [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _),1038 [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _),
1019 [46] = PINGROUP(46, NORTH, qup13, qup13, _, _, _, _, _, _, _),1039 [46] = PINGROUP(46, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _),
1020 [47] = PINGROUP(47, NORTH, qup13, qup13, _, _, _, _, _, _, _),1040 [47] = PINGROUP(47, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _),
1021 [48] = PINGROUP(48, NORTH, gcc_gp1, _, _, _, _, _, _, _, _),1041 [48] = PINGROUP(48, NORTH, gcc_gp1, _, _, _, _, _, _, _, _),
1022 [49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, _, _, _, _, _, _, _),1042 [49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, _, _, _, _, _, _, _),
1023 [50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, gp_pdm1, _, _, _, _, _, _),1043 [50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, gp_pdm1, _, _, _, _, _, _),
@@ -1085,8 +1105,8 @@ static const struct msm_pingroup sc7180_groups[] = { · 61 unmodified lines
1085 [112] = PINGROUP(112, NORTH, _, _, _, _, _, _, _, _, _),1105 [112] = PINGROUP(112, NORTH, _, _, _, _, _, _, _, _, _),
1086 [113] = PINGROUP(113, NORTH, _, _, _, _, _, _, _, _, _),1106 [113] = PINGROUP(113, NORTH, _, _, _, _, _, _, _, _, _),
1087 [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _),1107 [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _),
1088 [115] = PINGROUP(115, WEST, qup04, qup04, _, _, _, _, _, _, _),1108 [115] = PINGROUP(115, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _),
1089 [116] = PINGROUP(116, WEST, qup04, qup04, _, _, _, _, _, _, _),1109 [116] = PINGROUP(116, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _),
1090 [117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _),1110 [117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _),
1091 [118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _),1111 [118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _),
1092 [119] = UFS_RESET(ufs_reset, 0x7f000),1112 [119] = UFS_RESET(ufs_reset, 0x7f000),
@@ -1099,6 +1119,22 @@ static const struct msm_pingroup sc7180_groups[] = { · 6 unmodified lines
1099 [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x7b000, 9, 0),1119 [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x7b000, 9, 0),
1100};1120};
1101 1121
1122static const struct msm_gpio_wakeirq_map sc7180_pdc_map[] = {
1123 {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 35},
1124 {10, 80}, {11, 51}, {16, 20}, {21, 55}, {22, 90}, {23, 21},
1125 {24, 61}, {26, 52}, {28, 36}, {30, 100}, {31, 33}, {32, 81},
1126 {33, 62}, {34, 43}, {36, 91}, {37, 53}, {38, 63}, {39, 72},
1127 {41, 101}, {42, 7}, {43, 34}, {45, 73}, {47, 82}, {49, 17},
1128 {52, 109}, {53, 102}, {55, 92}, {56, 56}, {57, 57}, {58, 83},
1129 {59, 37}, {62, 110}, {63, 111}, {64, 74}, {65, 44}, {66, 93},
1130 {67, 58}, {68, 112}, {69, 32}, {70, 54}, {72, 59}, {73, 64},
1131 {74, 71}, {78, 31}, {82, 30}, {85, 103}, {86, 38}, {87, 39},
1132 {88, 45}, {89, 46}, {90, 47}, {91, 48}, {92, 60}, {93, 49},
1133 {94, 84}, {95, 94}, {98, 65}, {101, 66}, {104, 67}, {109, 104},
1134 {110, 68}, {113, 69}, {114, 113}, {115, 108}, {116, 121},
1135 {117, 114}, {118, 119},
1136};
1137
1102static const struct msm_pinctrl_soc_data sc7180_pinctrl = {1138static const struct msm_pinctrl_soc_data sc7180_pinctrl = {
1103 .pins = sc7180_pins,1139 .pins = sc7180_pins,
1104 .npins = ARRAY_SIZE(sc7180_pins),1140 .npins = ARRAY_SIZE(sc7180_pins),
@@ -1109,6 +1145,8 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = { · 4 unmodified lines
1109 .ngpios = 120,1145 .ngpios = 120,
1110 .tiles = sc7180_tiles,1146 .tiles = sc7180_tiles,
1111 .ntiles = ARRAY_SIZE(sc7180_tiles),1147 .ntiles = ARRAY_SIZE(sc7180_tiles),
1148 .wakeirq_map = sc7180_pdc_map,
1149 .nwakeirq_map = ARRAY_SIZE(sc7180_pdc_map),
1112};1150};
1113 1151
1114static int sc7180_pinctrl_probe(struct platform_device *pdev)1152static int sc7180_pinctrl_probe(struct platform_device *pdev)
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c+1−1
@@ -439,7 +439,7 @@ static const struct pinconf_ops pm8xxx_pinconf_ops = { · 438 unmodified lines
439 .pin_config_group_set = pm8xxx_pin_config_set,439 .pin_config_group_set = pm8xxx_pin_config_set,
440};440};
441 441
442static struct pinctrl_desc pm8xxx_pinctrl_desc = {442static const struct pinctrl_desc pm8xxx_pinctrl_desc = {
443 .name = "pm8xxx_gpio",443 .name = "pm8xxx_gpio",
444 .pctlops = &pm8xxx_pinctrl_ops,444 .pctlops = &pm8xxx_pinctrl_ops,
445 .pmxops = &pm8xxx_pinmux_ops,445 .pmxops = &pm8xxx_pinmux_ops,
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c+1−1
@@ -430,7 +430,7 @@ static const struct pinconf_ops pm8xxx_pinconf_ops = { · 429 unmodified lines
430 .pin_config_group_set = pm8xxx_pin_config_set,430 .pin_config_group_set = pm8xxx_pin_config_set,
431};431};
432 432
433static struct pinctrl_desc pm8xxx_pinctrl_desc = {433static const struct pinctrl_desc pm8xxx_pinctrl_desc = {
434 .name = "pm8xxx_mpp",434 .name = "pm8xxx_mpp",
435 .pctlops = &pm8xxx_pinctrl_ops,435 .pctlops = &pm8xxx_pinctrl_ops,
436 .pmxops = &pm8xxx_pinmux_ops,436 .pmxops = &pm8xxx_pinmux_ops,
drivers/pinctrl/samsung/Kconfig+10−6
@@ -4,30 +4,34 @@ · 3 unmodified lines
4#4#
5config PINCTRL_SAMSUNG5config PINCTRL_SAMSUNG
6 bool6 bool
7 depends on OF_GPIO
7 select PINMUX8 select PINMUX
8 select PINCONF9 select PINCONF
9 10
10config PINCTRL_EXYNOS11config PINCTRL_EXYNOS
11 bool "Pinctrl driver data for Samsung EXYNOS SoCs"12 bool "Pinctrl common driver part for Samsung Exynos SoCs"
12 depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)13 depends on OF_GPIO
14 depends on ARCH_EXYNOS || ARCH_S5PV210 || COMPILE_TEST
13 select PINCTRL_SAMSUNG15 select PINCTRL_SAMSUNG
14 select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210)16 select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210)
15 select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS17 select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS
16 18
17config PINCTRL_EXYNOS_ARM19config PINCTRL_EXYNOS_ARM
18 bool "ARMv7-specific pinctrl driver data for Exynos" if COMPILE_TEST20 bool "ARMv7-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST
19 depends on PINCTRL_EXYNOS21 depends on PINCTRL_EXYNOS
20 22
21config PINCTRL_EXYNOS_ARM6423config PINCTRL_EXYNOS_ARM64
22 bool "ARMv8-specific pinctrl driver data for Exynos" if COMPILE_TEST24 bool "ARMv8-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST
23 depends on PINCTRL_EXYNOS25 depends on PINCTRL_EXYNOS
24 26
25config PINCTRL_S3C24XX27config PINCTRL_S3C24XX
26 bool "Samsung S3C24XX SoC pinctrl driver"28 bool "Samsung S3C24XX SoC pinctrl driver"
27 depends on ARCH_S3C24XX && OF29 depends on OF_GPIO
30 depends on ARCH_S3C24XX || COMPILE_TEST
28 select PINCTRL_SAMSUNG31 select PINCTRL_SAMSUNG
29 32
30config PINCTRL_S3C64XX33config PINCTRL_S3C64XX
31 bool "Samsung S3C64XX SoC pinctrl driver"34 bool "Samsung S3C64XX SoC pinctrl driver"
32 depends on ARCH_S3C64XX35 depends on OF_GPIO
36 depends on ARCH_S3C64XX || COMPILE_TEST
33 select PINCTRL_SAMSUNG37 select PINCTRL_SAMSUNG
drivers/pinctrl/sh-pfc/Kconfig+8−4
@@ -26,8 +26,9 @@ config PINCTRL_SH_PFC · 25 unmodified lines
26 select PINCTRL_PFC_R8A7792 if ARCH_R8A779226 select PINCTRL_PFC_R8A7792 if ARCH_R8A7792
27 select PINCTRL_PFC_R8A7793 if ARCH_R8A779327 select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
28 select PINCTRL_PFC_R8A7794 if ARCH_R8A779428 select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
29 select PINCTRL_PFC_R8A7795 if ARCH_R8A779529 select PINCTRL_PFC_R8A77950 if ARCH_R8A77950 || ARCH_R8A7795
30 select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 || ARCH_R8A779630 select PINCTRL_PFC_R8A77951 if ARCH_R8A77951 || ARCH_R8A7795
31 select PINCTRL_PFC_R8A77960 if ARCH_R8A77960
31 select PINCTRL_PFC_R8A77961 if ARCH_R8A7796132 select PINCTRL_PFC_R8A77961 if ARCH_R8A77961
32 select PINCTRL_PFC_R8A77965 if ARCH_R8A7796533 select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
33 select PINCTRL_PFC_R8A77970 if ARCH_R8A7797034 select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
@@ -115,8 +116,11 @@ config PINCTRL_PFC_R8A7793 · 81 unmodified lines
115config PINCTRL_PFC_R8A7794116config PINCTRL_PFC_R8A7794
116 bool "R-Car E2 pin control support" if COMPILE_TEST117 bool "R-Car E2 pin control support" if COMPILE_TEST
117 118
118config PINCTRL_PFC_R8A7795119config PINCTRL_PFC_R8A77950
119 bool "R-Car H3 pin control support" if COMPILE_TEST120 bool "R-Car H3 ES1.x pin control support" if COMPILE_TEST
121
122config PINCTRL_PFC_R8A77951
123 bool "R-Car H3 ES2.0+ pin control support" if COMPILE_TEST
120 124
121config PINCTRL_PFC_R8A77960125config PINCTRL_PFC_R8A77960
122 bool "R-Car M3-W pin control support" if COMPILE_TEST126 bool "R-Car M3-W pin control support" if COMPILE_TEST
drivers/pinctrl/sh-pfc/Makefile+2−2
@@ -18,8 +18,8 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o · 17 unmodified lines
18obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o18obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
19obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o19obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
20obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o20obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
21obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o21obj-$(CONFIG_PINCTRL_PFC_R8A77950) += pfc-r8a77950.o
22obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o22obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a77951.o
23obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o23obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
24obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o24obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
25obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o25obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
drivers/pinctrl/sh-pfc/core.c+44−13
@@ -23,6 +23,7 @@ · 22 unmodified lines
23#include <linux/platform_device.h>23#include <linux/platform_device.h>
24#include <linux/psci.h>24#include <linux/psci.h>
25#include <linux/slab.h>25#include <linux/slab.h>
26#include <linux/sys_soc.h>
26 27
27#include "core.h"28#include "core.h"
28 29
@@ -568,18 +569,18 @@ static const struct of_device_id sh_pfc_of_table[] = { · 539 unmodified lines
568 .data = &r8a7794_pinmux_info,569 .data = &r8a7794_pinmux_info,
569 },570 },
570#endif571#endif
571#ifdef CONFIG_PINCTRL_PFC_R8A7795572/* Both r8a7795 entries must be present to make sanity checks work */
573#ifdef CONFIG_PINCTRL_PFC_R8A77950
572 {574 {
573 .compatible = "renesas,pfc-r8a7795",575 .compatible = "renesas,pfc-r8a7795",
574 .data = &r8a7795_pinmux_info,576 .data = &r8a77950_pinmux_info,
575 },577 },
576#ifdef DEBUG578#endif
579#ifdef CONFIG_PINCTRL_PFC_R8A77951
577 {580 {
578 /* For sanity checks only (nothing matches against this) */581 .compatible = "renesas,pfc-r8a7795",
579 .compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */582 .data = &r8a77951_pinmux_info,
580 .data = &r8a7795es1_pinmux_info,
581 },583 },
582#endif /* DEBUG */
583#endif584#endif
584#ifdef CONFIG_PINCTRL_PFC_R8A77960585#ifdef CONFIG_PINCTRL_PFC_R8A77960
585 {586 {
@@ -886,19 +887,49 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv) · 300 unmodified lines
886static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}887static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
887#endif /* !DEBUG */888#endif /* !DEBUG */
888 889
890#ifdef CONFIG_OF
891static const void *sh_pfc_quirk_match(void)
892{
893#if defined(CONFIG_PINCTRL_PFC_R8A77950) || \
894 defined(CONFIG_PINCTRL_PFC_R8A77951)
895 const struct soc_device_attribute *match;
896 static const struct soc_device_attribute quirks[] = {
897 {
898 .soc_id = "r8a7795", .revision = "ES1.*",
899 .data = &r8a77950_pinmux_info,
900 },
901 {
902 .soc_id = "r8a7795",
903 .data = &r8a77951_pinmux_info,
904 },
905
906 { /* sentinel */ }
907 };
908
909 match = soc_device_match(quirks);
910 if (match)
911 return match->data ?: ERR_PTR(-ENODEV);
912#endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */
913
914 return NULL;
915}
916#endif /* CONFIG_OF */
917
889static int sh_pfc_probe(struct platform_device *pdev)918static int sh_pfc_probe(struct platform_device *pdev)
890{919{
891#ifdef CONFIG_OF
892 struct device_node *np = pdev->dev.of_node;
893#endif
894 const struct sh_pfc_soc_info *info;920 const struct sh_pfc_soc_info *info;
895 struct sh_pfc *pfc;921 struct sh_pfc *pfc;
896 int ret;922 int ret;
897 923
898#ifdef CONFIG_OF924#ifdef CONFIG_OF
899 if (np)925 if (pdev->dev.of_node) {
900 info = of_device_get_match_data(&pdev->dev);926 info = sh_pfc_quirk_match();
901 else927 if (IS_ERR(info))
928 return PTR_ERR(info);
929
930 if (!info)
931 info = of_device_get_match_data(&pdev->dev);
932 } else
902#endif933#endif
903 info = (const void *)platform_get_device_id(pdev)->driver_data;934 info = (const void *)platform_get_device_id(pdev)->driver_data;
904 935
drivers/pinctrl/sh-pfc/gpio.c+5−6
@@ -386,12 +386,11 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) · 385 unmodified lines
386 }386 }
387 387
388 /* Register the function GPIOs chip. */388 /* Register the function GPIOs chip. */
389 if (pfc->info->nr_func_gpios == 0)389 if (pfc->info->nr_func_gpios) {
390 return 0;390 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
391 391 if (IS_ERR(chip))
392 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);392 return PTR_ERR(chip);
393 if (IS_ERR(chip))393 }
394 return PTR_ERR(chip);
395#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */394#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
396 395
397 return 0;396 return 0;
drivers/pinctrl/sh-pfc/pfc-r8a7778.c+2−2
@@ -2305,7 +2305,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 2304 unmodified lines
2305 FN_ATAG0_A, 0, FN_REMOCON_B, 0,2305 FN_ATAG0_A, 0, FN_REMOCON_B, 0,
2306 /* IP0_11_8 [4] */2306 /* IP0_11_8 [4] */
2307 FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS,2307 FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS,
2308 FN_ATADIR0_A, 0, FN_SDSELF_B, 0,2308 FN_ATADIR0_A, 0, FN_SDSELF_A, 0,
2309 FN_PWM4_B, 0, 0, 0,2309 FN_PWM4_B, 0, 0, 0,
2310 0, 0, 0, 0,2310 0, 0, 0, 0,
2311 /* IP0_7_5 [3] */2311 /* IP0_7_5 [3] */
@@ -2349,7 +2349,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 37 unmodified lines
2349 FN_TS_SDAT0_A, 0, 0, 0,2349 FN_TS_SDAT0_A, 0, 0, 0,
2350 0, 0, 0, 0,2350 0, 0, 0, 0,
2351 /* IP1_10_8 [3] */2351 /* IP1_10_8 [3] */
2352 FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24,2352 FN_SD1_CD_A, FN_MMC_D6, 0, FN_A24,
2353 FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A,2353 FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A,
2354 /* IP1_7_5 [3] */2354 /* IP1_7_5 [3] */
2355 FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,2355 FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
drivers/pinctrl/sh-pfc/pfc-r8a77950.crenamed from drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c+13−13
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.01// SPDX-License-Identifier: GPL-2.0
2/*2/*
3 * R8A7795 ES1.x processor support - PFC hardware block.3 * R8A77950 processor support - PFC hardware block.
4 *4 *
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
6 */6 */
@@ -5562,8 +5562,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { · 5555 unmodified lines
5562 { /* sentinel */ },5562 { /* sentinel */ },
5563};5563};
5564 5564
5565static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,5565static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5566 u32 *pocctrl)5566 u32 *pocctrl)
5567{5567{
5568 int bit = -EINVAL;5568 int bit = -EINVAL;
5569 5569
@@ -5820,8 +5820,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 250 unmodified lines
5820 { /* sentinel */ },5820 { /* sentinel */ },
5821};5821};
5822 5822
5823static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,5823static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc,
5824 unsigned int pin)5824 unsigned int pin)
5825{5825{
5826 const struct pinmux_bias_reg *reg;5826 const struct pinmux_bias_reg *reg;
5827 unsigned int bit;5827 unsigned int bit;
@@ -5838,8 +5838,8 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, · 10 unmodified lines
5838 return PIN_CONFIG_BIAS_PULL_DOWN;5838 return PIN_CONFIG_BIAS_PULL_DOWN;
5839}5839}
5840 5840
5841static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,5841static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5842 unsigned int bias)5842 unsigned int bias)
5843{5843{
5844 const struct pinmux_bias_reg *reg;5844 const struct pinmux_bias_reg *reg;
5845 u32 enable, updown;5845 u32 enable, updown;
@@ -5861,15 +5861,15 @@ static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, · 15 unmodified lines
5861 sh_pfc_write(pfc, reg->puen, enable);5861 sh_pfc_write(pfc, reg->puen, enable);
5862}5862}
5863 5863
5864static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {5864static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
5865 .pin_to_pocctrl = r8a7795es1_pin_to_pocctrl,5865 .pin_to_pocctrl = r8a77950_pin_to_pocctrl,
5866 .get_bias = r8a7795es1_pinmux_get_bias,5866 .get_bias = r8a77950_pinmux_get_bias,
5867 .set_bias = r8a7795es1_pinmux_set_bias,5867 .set_bias = r8a77950_pinmux_set_bias,
5868};5868};
5869 5869
5870const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {5870const struct sh_pfc_soc_info r8a77950_pinmux_info = {
5871 .name = "r8a77950_pfc",5871 .name = "r8a77950_pfc",
5872 .ops = &r8a7795es1_pinmux_ops,5872 .ops = &r8a77950_pinmux_ops,
5873 .unlock_reg = 0xe6060000, /* PMMR */5873 .unlock_reg = 0xe6060000, /* PMMR */
5874 5874
5875 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },5875 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/sh-pfc/pfc-r8a77951.crenamed from drivers/pinctrl/sh-pfc/pfc-r8a7795.c+13−26
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.01// SPDX-License-Identifier: GPL-2.0
2/*2/*
3 * R8A7795 ES2.0+ processor support - PFC hardware block.3 * R8A77951 processor support - PFC hardware block.
4 *4 *
5 * Copyright (C) 2015-2019 Renesas Electronics Corporation5 * Copyright (C) 2015-2019 Renesas Electronics Corporation
6 */6 */
@@ -5915,7 +5915,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { · 5908 unmodified lines
5915 { /* sentinel */ },5915 { /* sentinel */ },
5916};5916};
5917 5917
5918static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)5918static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
5919 unsigned int pin, u32 *pocctrl)
5919{5920{
5920 int bit = -EINVAL;5921 int bit = -EINVAL;
5921 5922
@@ -6172,8 +6173,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 250 unmodified lines
6172 { /* sentinel */ },6173 { /* sentinel */ },
6173};6174};
6174 6175
6175static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,6176static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc,
6176 unsigned int pin)6177 unsigned int pin)
6177{6178{
6178 const struct pinmux_bias_reg *reg;6179 const struct pinmux_bias_reg *reg;
6179 unsigned int bit;6180 unsigned int bit;
@@ -6190,8 +6191,8 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, · 10 unmodified lines
6190 return PIN_CONFIG_BIAS_PULL_DOWN;6191 return PIN_CONFIG_BIAS_PULL_DOWN;
6191}6192}
6192 6193
6193static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,6194static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6194 unsigned int bias)6195 unsigned int bias)
6195{6196{
6196 const struct pinmux_bias_reg *reg;6197 const struct pinmux_bias_reg *reg;
6197 u32 enable, updown;6198 u32 enable, updown;
@@ -6213,29 +6214,15 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, · 15 unmodified lines
6213 sh_pfc_write(pfc, reg->puen, enable);6214 sh_pfc_write(pfc, reg->puen, enable);
6214}6215}
6215 6216
6216static const struct soc_device_attribute r8a7795es1[] = {6217static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
6217 { .soc_id = "r8a7795", .revision = "ES1.*" },6218 .pin_to_pocctrl = r8a77951_pin_to_pocctrl,
6218 { /* sentinel */ }6219 .get_bias = r8a77951_pinmux_get_bias,
6220 .set_bias = r8a77951_pinmux_set_bias,
6219};6221};
6220 6222
6221static int r8a7795_pinmux_init(struct sh_pfc *pfc)6223const struct sh_pfc_soc_info r8a77951_pinmux_info = {
6222{
6223 if (soc_device_match(r8a7795es1))
6224 pfc->info = &r8a7795es1_pinmux_info;
6225
6226 return 0;
6227}
6228
6229static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
6230 .init = r8a7795_pinmux_init,
6231 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
6232 .get_bias = r8a7795_pinmux_get_bias,
6233 .set_bias = r8a7795_pinmux_set_bias,
6234};
6235
6236const struct sh_pfc_soc_info r8a7795_pinmux_info = {
6237 .name = "r8a77951_pfc",6224 .name = "r8a77951_pfc",
6238 .ops = &r8a7795_pinmux_ops,6225 .ops = &r8a77951_pinmux_ops,
6239 .unlock_reg = 0xe6060000, /* PMMR */6226 .unlock_reg = 0xe6060000, /* PMMR */
6240 6227
6241 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },6228 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
drivers/pinctrl/sh-pfc/pfc-r8a77965.c+3−3
@@ -5998,7 +5998,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { · 5997 unmodified lines
5998 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */5998 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
5999 } },5999 } },
6000 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {6000 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
6001 { PIN_DU_DOTCLKIN3, 28, 2 }, /* DU_DOTCLKIN3 */6001 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
6002 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */6002 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
6003 { PIN_TMS, 4, 2 }, /* TMS */6003 { PIN_TMS, 4, 2 }, /* TMS */
6004 } },6004 } },
@@ -6254,8 +6254,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { · 249 unmodified lines
6254 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */6254 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
6255 } },6255 } },
6256 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {6256 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6257 [ 0] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */6257 [ 0] = SH_PFC_PIN_NONE,
6258 [ 1] = SH_PFC_PIN_NONE,6258 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6259 [ 2] = PIN_FSCLKST, /* FSCLKST */6259 [ 2] = PIN_FSCLKST, /* FSCLKST */
6260 [ 3] = PIN_EXTALR, /* EXTALR*/6260 [ 3] = PIN_EXTALR, /* EXTALR*/
6261 [ 4] = PIN_TRST_N, /* TRST# */6261 [ 4] = PIN_TRST_N, /* TRST# */
drivers/pinctrl/sh-pfc/pfc-sh7264.c+16−17
@@ -497,17 +497,15 @@ enum { · 496 unmodified lines
497 SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK,497 SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK,
498 CRX0_MARK, CRX1_MARK,498 CRX0_MARK, CRX1_MARK,
499 CTX0_MARK, CTX1_MARK,499 CTX0_MARK, CTX1_MARK,
500 CRX0_CRX1_MARK, CTX0_CTX1_MARK,
500 501
501 PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,502 PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
502 PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,503 PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
503 PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,504 PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
504 PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,505 PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
505 IERXD_MARK, IETXD_MARK,506 IERXD_MARK, IETXD_MARK,
506 CRX0_CRX1_MARK,
507 WDTOVF_MARK,507 WDTOVF_MARK,
508 508
509 CRX0X1_MARK,
510
511 /* DMAC */509 /* DMAC */
512 TEND0_MARK, DACK0_MARK, DREQ0_MARK,510 TEND0_MARK, DACK0_MARK, DREQ0_MARK,
513 TEND1_MARK, DACK1_MARK, DREQ1_MARK,511 TEND1_MARK, DACK1_MARK, DREQ1_MARK,
@@ -995,12 +993,12 @@ static const u16 pinmux_data[] = { · 481 unmodified lines
995 993
996 PINMUX_DATA(PJ3_DATA, PJ3MD_00),994 PINMUX_DATA(PJ3_DATA, PJ3MD_00),
997 PINMUX_DATA(CRX1_MARK, PJ3MD_01),995 PINMUX_DATA(CRX1_MARK, PJ3MD_01),
998 PINMUX_DATA(CRX0X1_MARK, PJ3MD_10),996 PINMUX_DATA(CRX0_CRX1_MARK, PJ3MD_10),
999 PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11),997 PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11),
1000 998
1001 PINMUX_DATA(PJ2_DATA, PJ2MD_000),999 PINMUX_DATA(PJ2_DATA, PJ2MD_000),
1002 PINMUX_DATA(CTX1_MARK, PJ2MD_001),1000 PINMUX_DATA(CTX1_MARK, PJ2MD_001),
1003 PINMUX_DATA(CRX0_CRX1_MARK, PJ2MD_010),1001 PINMUX_DATA(CTX0_CTX1_MARK, PJ2MD_010),
1004 PINMUX_DATA(CS2_MARK, PJ2MD_011),1002 PINMUX_DATA(CS2_MARK, PJ2MD_011),
1005 PINMUX_DATA(SCK0_MARK, PJ2MD_100),1003 PINMUX_DATA(SCK0_MARK, PJ2MD_100),
1006 PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101),1004 PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101),
@@ -1245,6 +1243,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { · 238 unmodified lines
1245 GPIO_FN(CTX1),1243 GPIO_FN(CTX1),
1246 GPIO_FN(CRX1),1244 GPIO_FN(CRX1),
1247 GPIO_FN(CTX0),1245 GPIO_FN(CTX0),
1246 GPIO_FN(CTX0_CTX1),
1248 GPIO_FN(CRX0),1247 GPIO_FN(CRX0),
1249 GPIO_FN(CRX0_CRX1),1248 GPIO_FN(CRX0_CRX1),
1250 1249
@@ -2020,18 +2019,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 769 unmodified lines
2020 2019
2021 { PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1, GROUP(2020 { PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1, GROUP(
2022 0, 0, 0, 0, 0, 0, 0, 0,2021 0, 0, 0, 0, 0, 0, 0, 0,
2023 PJ11_IN, PJ11_OUT,2022 PK11_IN, PK11_OUT,
2024 PJ10_IN, PJ10_OUT,2023 PK10_IN, PK10_OUT,
2025 PJ9_IN, PJ9_OUT,2024 PK9_IN, PK9_OUT,
2026 PJ8_IN, PJ8_OUT,2025 PK8_IN, PK8_OUT,
2027 PJ7_IN, PJ7_OUT,2026 PK7_IN, PK7_OUT,
2028 PJ6_IN, PJ6_OUT,2027 PK6_IN, PK6_OUT,
2029 PJ5_IN, PJ5_OUT,2028 PK5_IN, PK5_OUT,
2030 PJ4_IN, PJ4_OUT,2029 PK4_IN, PK4_OUT,
2031 PJ3_IN, PJ3_OUT,2030 PK3_IN, PK3_OUT,
2032 PJ2_IN, PJ2_OUT,2031 PK2_IN, PK2_OUT,
2033 PJ1_IN, PJ1_OUT,2032 PK1_IN, PK1_OUT,
2034 PJ0_IN, PJ0_OUT ))2033 PK0_IN, PK0_OUT ))
2035 },2034 },
2036 {}2035 {}
2037};2036};
drivers/pinctrl/sh-pfc/pfc-sh7269.c+27−12
@@ -737,13 +737,12 @@ enum { · 736 unmodified lines
737 CRX0_MARK, CTX0_MARK,737 CRX0_MARK, CTX0_MARK,
738 CRX1_MARK, CTX1_MARK,738 CRX1_MARK, CTX1_MARK,
739 CRX2_MARK, CTX2_MARK,739 CRX2_MARK, CTX2_MARK,
740 CRX0_CRX1_MARK,740 CRX0_CRX1_MARK, CTX0_CTX1_MARK,
741 CRX0_CRX1_CRX2_MARK,741 CRX0_CRX1_CRX2_MARK, CTX0_CTX1_CTX2_MARK,
742 CTX0CTX1CTX2_MARK,
743 CRX1_PJ22_MARK, CTX1_PJ23_MARK,742 CRX1_PJ22_MARK, CTX1_PJ23_MARK,
744 CRX2_PJ20_MARK, CTX2_PJ21_MARK,743 CRX2_PJ20_MARK, CTX2_PJ21_MARK,
745 CRX0CRX1_PJ22_MARK,744 CRX0_CRX1_PJ22_MARK, CTX0_CTX1_PJ23_MARK,
746 CRX0CRX1CRX2_PJ20_MARK,745 CRX0_CRX1_CRX2_PJ20_MARK, CTX0_CTX1_CTX2_PJ21_MARK,
747 746
748 /* VDC */747 /* VDC */
749 DV_CLK_MARK,748 DV_CLK_MARK,
@@ -821,6 +820,7 @@ static const u16 pinmux_data[] = { · 71 unmodified lines
821 PINMUX_DATA(CS3_MARK, PC8MD_001),820 PINMUX_DATA(CS3_MARK, PC8MD_001),
822 PINMUX_DATA(TXD7_MARK, PC8MD_010),821 PINMUX_DATA(TXD7_MARK, PC8MD_010),
823 PINMUX_DATA(CTX1_MARK, PC8MD_011),822 PINMUX_DATA(CTX1_MARK, PC8MD_011),
823 PINMUX_DATA(CTX0_CTX1_MARK, PC8MD_100),
824 824
825 PINMUX_DATA(PC7_DATA, PC7MD_000),825 PINMUX_DATA(PC7_DATA, PC7MD_000),
826 PINMUX_DATA(CKE_MARK, PC7MD_001),826 PINMUX_DATA(CKE_MARK, PC7MD_001),
@@ -833,11 +833,12 @@ static const u16 pinmux_data[] = { · 6 unmodified lines
833 PINMUX_DATA(CAS_MARK, PC6MD_001),833 PINMUX_DATA(CAS_MARK, PC6MD_001),
834 PINMUX_DATA(SCK7_MARK, PC6MD_010),834 PINMUX_DATA(SCK7_MARK, PC6MD_010),
835 PINMUX_DATA(CTX0_MARK, PC6MD_011),835 PINMUX_DATA(CTX0_MARK, PC6MD_011),
836 PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC6MD_100),
836 837
837 PINMUX_DATA(PC5_DATA, PC5MD_000),838 PINMUX_DATA(PC5_DATA, PC5MD_000),
838 PINMUX_DATA(RAS_MARK, PC5MD_001),839 PINMUX_DATA(RAS_MARK, PC5MD_001),
839 PINMUX_DATA(CRX0_MARK, PC5MD_011),840 PINMUX_DATA(CRX0_MARK, PC5MD_011),
840 PINMUX_DATA(CTX0CTX1CTX2_MARK, PC5MD_100),841 PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC5MD_100),
841 PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101),842 PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101),
842 843
843 PINMUX_DATA(PC4_DATA, PC4MD_00),844 PINMUX_DATA(PC4_DATA, PC4MD_00),
@@ -1289,30 +1290,32 @@ static const u16 pinmux_data[] = { · 445 unmodified lines
1289 PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010),1290 PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010),
1290 PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011),1291 PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011),
1291 PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100),1292 PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100),
1292 PINMUX_DATA(CTX1_MARK, PJ23MD_101),1293 PINMUX_DATA(CTX1_PJ23_MARK, PJ23MD_101),
1294 PINMUX_DATA(CTX0_CTX1_PJ23_MARK, PJ23MD_110),
1293 1295
1294 PINMUX_DATA(PJ22_DATA, PJ22MD_000),1296 PINMUX_DATA(PJ22_DATA, PJ22MD_000),
1295 PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001),1297 PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001),
1296 PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010),1298 PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010),
1297 PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011),1299 PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011),
1298 PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100),1300 PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100),
1299 PINMUX_DATA(CRX1_MARK, PJ22MD_101),1301 PINMUX_DATA(CRX1_PJ22_MARK, PJ22MD_101),
1300 PINMUX_DATA(CRX0_CRX1_MARK, PJ22MD_110),1302 PINMUX_DATA(CRX0_CRX1_PJ22_MARK, PJ22MD_110),
1301 1303
1302 PINMUX_DATA(PJ21_DATA, PJ21MD_000),1304 PINMUX_DATA(PJ21_DATA, PJ21MD_000),
1303 PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001),1305 PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001),
1304 PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010),1306 PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010),
1305 PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011),1307 PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011),
1306 PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100),1308 PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100),
1307 PINMUX_DATA(CTX2_MARK, PJ21MD_101),1309 PINMUX_DATA(CTX2_PJ21_MARK, PJ21MD_101),
1310 PINMUX_DATA(CTX0_CTX1_CTX2_PJ21_MARK, PJ21MD_110),
1308 1311
1309 PINMUX_DATA(PJ20_DATA, PJ20MD_000),1312 PINMUX_DATA(PJ20_DATA, PJ20MD_000),
1310 PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001),1313 PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001),
1311 PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010),1314 PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010),
1312 PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011),1315 PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011),
1313 PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100),1316 PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100),
1314 PINMUX_DATA(CRX2_MARK, PJ20MD_101),1317 PINMUX_DATA(CRX2_PJ20_MARK, PJ20MD_101),
1315 PINMUX_DATA(CRX0CRX1CRX2_PJ20_MARK, PJ20MD_110),1318 PINMUX_DATA(CRX0_CRX1_CRX2_PJ20_MARK, PJ20MD_110),
1316 1319
1317 PINMUX_DATA(PJ19_DATA, PJ19MD_000),1320 PINMUX_DATA(PJ19_DATA, PJ19MD_000),
1318 PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001),1321 PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001),
@@ -1663,12 +1666,24 @@ static const struct pinmux_func pinmux_func_gpios[] = { · 344 unmodified lines
1663 GPIO_FN(WDTOVF),1666 GPIO_FN(WDTOVF),
1664 1667
1665 /* CAN */1668 /* CAN */
1669 GPIO_FN(CTX2),
1670 GPIO_FN(CRX2),
1666 GPIO_FN(CTX1),1671 GPIO_FN(CTX1),
1667 GPIO_FN(CRX1),1672 GPIO_FN(CRX1),
1668 GPIO_FN(CTX0),1673 GPIO_FN(CTX0),
1669 GPIO_FN(CRX0),1674 GPIO_FN(CRX0),
1675 GPIO_FN(CTX0_CTX1),
1670 GPIO_FN(CRX0_CRX1),1676 GPIO_FN(CRX0_CRX1),
1677 GPIO_FN(CTX0_CTX1_CTX2),
1671 GPIO_FN(CRX0_CRX1_CRX2),1678 GPIO_FN(CRX0_CRX1_CRX2),
1679 GPIO_FN(CTX2_PJ21),
1680 GPIO_FN(CRX2_PJ20),
1681 GPIO_FN(CTX1_PJ23),
1682 GPIO_FN(CRX1_PJ22),
1683 GPIO_FN(CTX0_CTX1_PJ23),
1684 GPIO_FN(CRX0_CRX1_PJ22),
1685 GPIO_FN(CTX0_CTX1_CTX2_PJ21),
1686 GPIO_FN(CRX0_CRX1_CRX2_PJ20),
1672 1687
1673 /* DMAC */1688 /* DMAC */
1674 GPIO_FN(TEND0),1689 GPIO_FN(TEND0),
drivers/pinctrl/sh-pfc/sh_pfc.h+2−2
@@ -318,8 +318,8 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info; · 317 unmodified lines
318extern const struct sh_pfc_soc_info r8a7792_pinmux_info;318extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
319extern const struct sh_pfc_soc_info r8a7793_pinmux_info;319extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
320extern const struct sh_pfc_soc_info r8a7794_pinmux_info;320extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
321extern const struct sh_pfc_soc_info r8a7795_pinmux_info;321extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak;
322extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;322extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak;
323extern const struct sh_pfc_soc_info r8a77960_pinmux_info;323extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
324extern const struct sh_pfc_soc_info r8a77961_pinmux_info;324extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
325extern const struct sh_pfc_soc_info r8a77965_pinmux_info;325extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
drivers/pinctrl/stm32/pinctrl-stm32.h+1−1
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.01/* SPDX-License-Identifier: GPL-2.0 */
2/*2/*
3 * Copyright (C) Maxime Coquelin 20153 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 20174 * Copyright (C) STMicroelectronics 2017
drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c+11−2
@@ -19,7 +19,6 @@ · 18 unmodified lines
19#include <linux/platform_device.h>19#include <linux/platform_device.h>
20#include <linux/of.h>20#include <linux/of.h>
21#include <linux/of_device.h>21#include <linux/of_device.h>
22#include <linux/of_irq.h>
23#include <linux/pinctrl/pinctrl.h>22#include <linux/pinctrl/pinctrl.h>
24 23
25#include "pinctrl-sunxi.h"24#include "pinctrl-sunxi.h"
@@ -549,7 +548,17 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { · 523 unmodified lines
549 548
550static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)549static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
551{550{
552 switch (of_irq_count(pdev->dev.of_node)) {551 int ret;
552
553 ret = platform_irq_count(pdev);
554 if (ret < 0) {
555 if (ret != -EPROBE_DEFER)
556 dev_err(&pdev->dev, "Couldn't determine irq count: %pe\n",
557 ERR_PTR(ret));
558 return ret;
559 }
560
561 switch (ret) {
553 case 2:562 case 2:
554 dev_warn(&pdev->dev,563 dev_warn(&pdev->dev,
555 "Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n");564 "Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n");
drivers/pinctrl/tegra/pinctrl-tegra.c+2−2
@@ -648,7 +648,7 @@ static int tegra_pinctrl_suspend(struct device *dev) · 647 unmodified lines
648{648{
649 struct tegra_pmx *pmx = dev_get_drvdata(dev);649 struct tegra_pmx *pmx = dev_get_drvdata(dev);
650 u32 *backup_regs = pmx->backup_regs;650 u32 *backup_regs = pmx->backup_regs;
651 u32 *regs;651 u32 __iomem *regs;
652 size_t bank_size;652 size_t bank_size;
653 unsigned int i, k;653 unsigned int i, k;
654 654
@@ -666,7 +666,7 @@ static int tegra_pinctrl_resume(struct device *dev) · 11 unmodified lines
666{666{
667 struct tegra_pmx *pmx = dev_get_drvdata(dev);667 struct tegra_pmx *pmx = dev_get_drvdata(dev);
668 u32 *backup_regs = pmx->backup_regs;668 u32 *backup_regs = pmx->backup_regs;
669 u32 *regs;669 u32 __iomem *regs;
670 size_t bank_size;670 size_t bank_size;
671 unsigned int i, k;671 unsigned int i, k;
672 672
include/linux/gpio/driver.h+0−5
@@ -582,11 +582,6 @@ int gpiochip_irq_domain_activate(struct irq_domain *domain, · 581 unmodified lines
582void gpiochip_irq_domain_deactivate(struct irq_domain *domain,582void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
583 struct irq_data *data);583 struct irq_data *data);
584 584
585void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
586 struct irq_chip *irqchip,
587 unsigned int parent_irq,
588 irq_flow_handler_t parent_handler);
589
590void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,585void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
591 struct irq_chip *irqchip,586 struct irq_chip *irqchip,
592 unsigned int parent_irq);587 unsigned int parent_irq);
include/linux/pinctrl/machine.h+5−0
@@ -153,6 +153,7 @@ struct pinctrl_map { · 152 unmodified lines
153 153
154extern int pinctrl_register_mappings(const struct pinctrl_map *map,154extern int pinctrl_register_mappings(const struct pinctrl_map *map,
155 unsigned num_maps);155 unsigned num_maps);
156extern void pinctrl_unregister_mappings(const struct pinctrl_map *map);
156extern void pinctrl_provide_dummies(void);157extern void pinctrl_provide_dummies(void);
157#else158#else
158 159
@@ -162,6 +163,10 @@ static inline int pinctrl_register_mappings(const struct pinctrl_map *map, · 3 unmodified lines
162 return 0;163 return 0;
163}164}
164 165
166static inline void pinctrl_unregister_mappings(const struct pinctrl_map *map)
167{
168}
169
165static inline void pinctrl_provide_dummies(void)170static inline void pinctrl_provide_dummies(void)
166{171{
167}172}