lael-labs/linux

Documentation/gpu/drm-mm.rst+23−6

 requested size and store it into the struct :c:type:`struct
 drm_gem_object <drm_gem_object>` filp field. The memory is
 used as either main storage for the object when the graphics hardware
-uses system memory directly or as a backing store otherwise.
+uses system memory directly or as a backing store otherwise. Drivers
+can call drm_gem_huge_mnt_create() to create, mount and use a huge
+shmem mountpoint instead of the default one ('shm_mnt'). For builds
+with CONFIG_TRANSPARENT_HUGEPAGE enabled, further calls to
+drm_gem_object_init() will let shmem allocate huge pages when
+possible.
 Drivers are responsible for the actual physical pages allocation by
 calling shmem_read_mapping_page_gfp() for each page.
 count. Drivers can use the drm_gem_vm_open() and drm_gem_vm_close() helper
 functions directly as open and close handlers.
-The fault operation handler is responsible for mapping individual pages
+The fault operation handler is responsible for mapping pages to
-to userspace when a page fault occurs. Depending on the memory
+userspace when a page fault occurs. Depending on the memory allocation
-allocation scheme, drivers can allocate pages at fault time, or can
+scheme, drivers can allocate pages at fault time, or can decide to
-decide to allocate memory for the GEM object at the time the object is
+allocate memory for the GEM object at the time the object is created.
-created.
 Drivers that want to map the GEM object upfront instead of handling page
 faults can implement their own mmap file operation handler.
+In order to reduce page table overhead, if the internal shmem mountpoint
+"shm_mnt" is configured to use transparent huge pages (for builds with
+CONFIG_TRANSPARENT_HUGEPAGE enabled) and if the shmem backing store
+managed to allocate a huge page for a faulty address, the fault handler
+will first attempt to insert that huge page into the VMA before falling
+back to individual page insertion. mmap() user address alignment for GEM
+objects is handled by providing a custom get_unmapped_area file
+operation which forwards to the shmem backing store. For most drivers,
+which don't create a huge mountpoint by default or through a module
+parameter, transparent huge pages can be enabled by either setting the
+"transparent_hugepage_shmem" kernel parameter or the
+"/sys/kernel/mm/transparent_hugepage/shmem_enabled" sysfs knob.
 For platforms without MMU the GEM core provides a helper method
 drm_gem_dma_get_unmapped_area(). The mmap() routines will call this to get a
 proposed address for the mapping.

Documentation/gpu/todo.rst+45−0

@@ -878,6 +878,51 @@ Contact: Christian König · 877 unmodified lines
878		878
879	Level: Starter	879	Level: Starter
880		880
		881	DRM GPU Scheduler
		882	=================
		883
		884	Provide a universal successor for drm_sched_resubmit_jobs()
		885	-----------------------------------------------------------
		886
		887	drm_sched_resubmit_jobs() is deprecated. Main reason being that it leads to
		888	reinitializing dma_fences. See that function's docu for details. The better
		889	approach for valid resubmissions by amdgpu and Xe is (apparently) to figure out
		890	which job (and, through association: which entity) caused the hang. Then, the
		891	job's buffer data, together with all other jobs' buffer data currently in the
		892	same hardware ring, must be invalidated. This can for example be done by
		893	overwriting it. amdgpu currently determines which jobs are in the ring and need
		894	to be overwritten by keeping copies of the job. Xe obtains that information by
		895	directly accessing drm_sched's pending_list.
		896
		897	Tasks:
		898
		899	1. implement scheduler functionality through which the driver can obtain the
		900	information which broken jobs are currently in the hardware ring.
		901	2. Such infrastructure would then typically be used in
		902	drm_sched_backend_ops.timedout_job(). Document that.
		903	3. Port a driver as first user.
		904	4. Document the new alternative in the docu of deprecated
		905	drm_sched_resubmit_jobs().
		906
		907	Contact: Christian König <christian.koenig@amd.com>
		908	Philipp Stanner <phasta@kernel.org>
		909
		910	Level: Advanced
		911
		912	Add locking for runqueues
		913	-------------------------
		914
		915	There is an old FIXME by Sima in include/drm/gpu_scheduler.h. It details that
		916	struct drm_sched_rq is read at many places without any locks, not even with a
		917	READ_ONCE. At XDC 2025 no one could really tell why that is the case, whether
		918	locks are needed and whether they could be added. (But for real, that should
		919	probably be locked!). Check whether it's possible to add locks everywhere, and
		920	do so if yes.
		921
		922	Contact: Philipp Stanner <phasta@kernel.org>
		923
		924	Level: Intermediate
		925
881	Outside DRM	926	Outside DRM
882	===========	927	===========
883		928

Documentation/process/debugging/kgdb.rst+0−28

@@ -889,34 +889,6 @@ in the virtual console layer. On resuming kernel execution, the kernel · 888 unmodified lines
889	debugger calls kgdboc_post_exp_handler() which in turn calls	889	debugger calls kgdboc_post_exp_handler() which in turn calls
890	con_debug_leave().	890	con_debug_leave().
891		891
892	Any video driver that wants to be compatible with the kernel debugger
893	and the atomic kms callbacks must implement the ``mode_set_base_atomic``,
894	``fb_debug_enter`` and ``fb_debug_leave operations``. For the
895	``fb_debug_enter`` and ``fb_debug_leave`` the option exists to use the
896	generic drm fb helper functions or implement something custom for the
897	hardware. The following example shows the initialization of the
898	.mode_set_base_atomic operation in
899	drivers/gpu/drm/i915/intel_display.c::
900
901
902	static const struct drm_crtc_helper_funcs intel_helper_funcs = {
903	[...]
904	.mode_set_base_atomic = intel_pipe_set_base_atomic,
905	[...]
906	};
907
908
909	Here is an example of how the i915 driver initializes the
910	fb_debug_enter and fb_debug_leave functions to use the generic drm
911	helpers in ``drivers/gpu/drm/i915/intel_fb.c``::
912
913
914	static struct fb_ops intelfb_ops = {
915	[...]
916	.fb_debug_enter = drm_fb_helper_debug_enter,
917	.fb_debug_leave = drm_fb_helper_debug_leave,
918	[...]
919	};
920		892
921		893
922	Credits	894	Credits

drivers/accel/amdxdna/aie2_message.c+12−6

 	if (!ndev->mgmt_chann)
 		return -ENODEV;
-	drm_WARN_ON(&xdna->ddev, xdna->rpm_on && !mutex_is_locked(&xdna->dev_lock));
 	ret = xdna_send_msg_wait(xdna, ndev->mgmt_chann, msg);
 	if (ret == -ETIME) {
 		xdna_mailbox_stop_channel(ndev->mgmt_chann);
 int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev)
 {
 	DECLARE_AIE2_MSG(suspend, MSG_OP_SUSPEND);
+	int ret;
-	return aie2_send_mgmt_msg_wait(ndev, &msg);
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Failed to suspend fw, ret %d", ret);
+		return ret;
+	}
+	return aie2_psp_waitmode_poll(ndev->psp_hdl);
 }
 int aie2_resume_fw(struct amdxdna_dev_hdl *ndev)
 	u32 cmd_len;
 	void *cmd;
+	memset(npu_slot, 0, sizeof(*npu_slot));
 	cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
 	if (*size < sizeof(*npu_slot) + cmd_len)
 		return -EINVAL;
 	if (npu_slot->cu_idx == INVALID_CU_IDX)
 		return -EINVAL;
-	memset(npu_slot, 0, sizeof(*npu_slot));
 	npu_slot->type = EXEC_NPU_TYPE_NON_ELF;
 	npu_slot->arg_cnt = cmd_len / sizeof(u32);
 	memcpy(npu_slot->args, cmd, cmd_len);
 	u32 cmd_len;
 	u32 arg_sz;
+	memset(npu_slot, 0, sizeof(*npu_slot));
 	sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
 	arg_sz = cmd_len - sizeof(*sn);
 	if (cmd_len < sizeof(*sn) || arg_sz > MAX_NPU_ARGS_SIZE)
 	if (npu_slot->cu_idx == INVALID_CU_IDX)
 		return -EINVAL;
-	memset(npu_slot, 0, sizeof(*npu_slot));
 	npu_slot->type = EXEC_NPU_TYPE_PARTIAL_ELF;
 	npu_slot->inst_buf_addr = sn->buffer;
 	npu_slot->inst_size = sn->buffer_size;
 	u32 cmd_len;
 	u32 arg_sz;
+	memset(npu_slot, 0, sizeof(*npu_slot));
 	pd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
 	arg_sz = cmd_len - sizeof(*pd);
 	if (cmd_len < sizeof(*pd) || arg_sz > MAX_NPU_ARGS_SIZE)
 	if (npu_slot->cu_idx == INVALID_CU_IDX)
 		return -EINVAL;
-	memset(npu_slot, 0, sizeof(*npu_slot));
 	npu_slot->type = EXEC_NPU_TYPE_PREEMPT;
 	npu_slot->inst_buf_addr = pd->inst_buf;
 	npu_slot->save_buf_addr = pd->save_buf;
 	u32 cmd_len;
 	u32 arg_sz;
+	memset(npu_slot, 0, sizeof(*npu_slot));
 	pd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
 	arg_sz = cmd_len - sizeof(*pd);
 	if (cmd_len < sizeof(*pd) || arg_sz > MAX_NPU_ARGS_SIZE)
 	if (*size < sizeof(*npu_slot) + arg_sz)
 		return -EINVAL;
-	memset(npu_slot, 0, sizeof(*npu_slot));
 	npu_slot->type = EXEC_NPU_TYPE_ELF;
 	npu_slot->inst_buf_addr = pd->inst_buf;
 	npu_slot->save_buf_addr = pd->save_buf;

drivers/accel/amdxdna/aie2_pci.c+1−1

@@ -322,7 +322,7 @@ static int aie2_xrs_set_dft_dpm_level(struct drm_device *ddev, u32 dpm_level) · 321 unmodified lines
322	if (ndev->pw_mode != POWER_MODE_DEFAULT \|\| ndev->dpm_level == dpm_level)	322	if (ndev->pw_mode != POWER_MODE_DEFAULT \|\| ndev->dpm_level == dpm_level)
323	return 0;	323	return 0;
324		324
325	return ndev->priv->hw_ops.set_dpm(ndev, dpm_level);	325	return aie2_pm_set_dpm(ndev, dpm_level);
326	}	326	}
327		327
328	static struct xrs_action_ops aie2_xrs_actions = {	328	static struct xrs_action_ops aie2_xrs_actions = {

drivers/accel/amdxdna/aie2_pci.h+3−0

 	PSP_INTR_REG = PSP_NUM_IN_REGS,
 	PSP_STATUS_REG,
 	PSP_RESP_REG,
+	PSP_PWAITMODE_REG,
 	PSP_MAX_REGS /* Keep this at the end */
 };
 /* aie2_pm.c */
 int aie2_pm_init(struct amdxdna_dev_hdl *ndev);
 int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type target);
+int aie2_pm_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
 /* aie2_psp.c */
 struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config *conf);
 int aie2_psp_start(struct psp_device *psp);
 void aie2_psp_stop(struct psp_device *psp);
+int aie2_psp_waitmode_poll(struct psp_device *psp);
 /* aie2_error.c */
 int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev);

drivers/accel/amdxdna/aie2_pm.c+16−1

 #include "aie2_pci.h"
 #include "amdxdna_pci_drv.h"
+#include "amdxdna_pm.h"
 #define AIE2_CLK_GATING_ENABLE	1
 #define AIE2_CLK_GATING_DISABLE	0
 	return 0;
 }
+int aie2_pm_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
+{
+	int ret;
+	ret = amdxdna_pm_resume_get(ndev->xdna);
+	if (ret)
+		return ret;
+	ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level);
+	amdxdna_pm_suspend_put(ndev->xdna);
+	return ret;
+}
 int aie2_pm_init(struct amdxdna_dev_hdl *ndev)
 {
 	int ret;
 		return -EOPNOTSUPP;
 	}
-	ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level);
+	ret = aie2_pm_set_dpm(ndev, dpm_level);
 	if (ret)
 		return ret;

drivers/accel/amdxdna/aie2_psp.c+15−0

@@ -76,6 +76,21 @@ static int psp_exec(struct psp_device psp, u32 reg_vals) · 75 unmodified lines
76	return 0;	76	return 0;
77	}	77	}
78		78
		79	int aie2_psp_waitmode_poll(struct psp_device *psp)
		80	{
		81	struct amdxdna_dev *xdna = to_xdna_dev(psp->ddev);
		82	u32 mode_reg;
		83	int ret;
		84
		85	ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_PWAITMODE_REG), mode_reg,
		86	(mode_reg & 0x1) == 1,
		87	PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT);
		88	if (ret)
		89	XDNA_ERR(xdna, "fw waitmode reg error, ret %d", ret);
		90
		91	return ret;
		92	}
		93
79	void aie2_psp_stop(struct psp_device *psp)	94	void aie2_psp_stop(struct psp_device *psp)
80	{	95	{
81	u32 reg_vals[PSP_NUM_IN_REGS] = { PSP_RELEASE_TMR, };	96	u32 reg_vals[PSP_NUM_IN_REGS] = { PSP_RELEASE_TMR, };

drivers/accel/amdxdna/aie2_smu.c+4−23

 #include "aie2_pci.h"
 #include "amdxdna_pci_drv.h"
-#include "amdxdna_pm.h"
 #define SMU_RESULT_OK		1
 	u32 freq;
 	int ret;
-	ret = amdxdna_pm_resume_get(ndev->xdna);
-	if (ret)
-		return ret;
 	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_MPNPUCLK_FREQ,
 			    ndev->priv->dpm_clk_tbl[dpm_level].npuclk, &freq);
 	if (ret) {
 		XDNA_ERR(ndev->xdna, "Set npu clock to %d failed, ret %d\n",
 			 ndev->priv->dpm_clk_tbl[dpm_level].npuclk, ret);
-		goto suspend_put;
+		return ret;
 	}
 	ndev->npuclk_freq = freq;
 	if (ret) {
 		XDNA_ERR(ndev->xdna, "Set h clock to %d failed, ret %d\n",
 			 ndev->priv->dpm_clk_tbl[dpm_level].hclk, ret);
-		goto suspend_put;
+		return ret;
 	}
-	amdxdna_pm_suspend_put(ndev->xdna);
 	ndev->hclk_freq = freq;
 	ndev->dpm_level = dpm_level;
 	ndev->max_tops = 2 * ndev->total_col;
 		 ndev->npuclk_freq, ndev->hclk_freq);
 	return 0;
-suspend_put:
-	amdxdna_pm_suspend_put(ndev->xdna);
-	return ret;
 }
 int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
 {
 	int ret;
-	ret = amdxdna_pm_resume_get(ndev->xdna);
-	if (ret)
-		return ret;
 	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_HARD_DPMLEVEL, dpm_level, NULL);
 	if (ret) {
 		XDNA_ERR(ndev->xdna, "Set hard dpm level %d failed, ret %d ",
 			 dpm_level, ret);
-		goto suspend_put;
+		return ret;
 	}
 	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_SOFT_DPMLEVEL, dpm_level, NULL);
 	if (ret) {
 		XDNA_ERR(ndev->xdna, "Set soft dpm level %d failed, ret %d",
 			 dpm_level, ret);
-		goto suspend_put;
+		return ret;
 	}
-	amdxdna_pm_suspend_put(ndev->xdna);
 	ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
 	ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
 	ndev->dpm_level = dpm_level;
 		 ndev->npuclk_freq, ndev->hclk_freq);
 	return 0;
-suspend_put:
-	amdxdna_pm_suspend_put(ndev->xdna);
-	return ret;
 }
 int aie2_smu_init(struct amdxdna_dev_hdl *ndev)

drivers/accel/amdxdna/amdxdna_mailbox.c+1−18

@@ -112,22 +112,6 @@ static u32 mailbox_reg_read(struct mailbox_channel *mb_chann, u32 mbox_reg) · 111 unmodified lines
112	return readl(ringbuf_addr);	112	return readl(ringbuf_addr);
113	}	113	}
114		114
115	static int mailbox_reg_read_non_zero(struct mailbox_channel mb_chann, u32 mbox_reg, u32 val)
116	{
117	struct xdna_mailbox_res *mb_res = &mb_chann->mb->res;
118	void __iomem *ringbuf_addr = mb_res->mbox_base + mbox_reg;
119	int ret, value;
120
121	/* Poll till value is not zero */
122	ret = readx_poll_timeout(readl, ringbuf_addr, value,
123	value, 1 /* us */, 100);
124	if (ret < 0)
125	return ret;
126
127	*val = value;
128	return 0;
129	}
130
131	static inline void	115	static inline void
132	mailbox_set_headptr(struct mailbox_channel *mb_chann, u32 headptr_val)	116	mailbox_set_headptr(struct mailbox_channel *mb_chann, u32 headptr_val)
133	{	117	{
@@ -286,8 +270,7 @@ static int mailbox_get_msg(struct mailbox_channel *mb_chann) · 152 unmodified lines
286	u32 start_addr;	270	u32 start_addr;
287	int ret;	271	int ret;
288		272
289	if (mailbox_reg_read_non_zero(mb_chann, mb_chann->res[CHAN_RES_I2X].mb_tail_ptr_reg, &tail))	273	tail = mailbox_get_tailptr(mb_chann, CHAN_RES_I2X);
290	return -EINVAL;
291	head = mb_chann->i2x_head;	274	head = mb_chann->i2x_head;
292	ringbuf_size = mailbox_get_ringbuf_size(mb_chann, CHAN_RES_I2X);	275	ringbuf_size = mailbox_get_ringbuf_size(mb_chann, CHAN_RES_I2X);
293	start_addr = mb_chann->res[CHAN_RES_I2X].rb_start_addr;	276	start_addr = mb_chann->res[CHAN_RES_I2X].rb_start_addr;

drivers/accel/amdxdna/amdxdna_pci_drv.h+0−1

@@ -101,7 +101,6 @@ struct amdxdna_dev { · 100 unmodified lines
101	struct amdxdna_fw_ver fw_ver;	101	struct amdxdna_fw_ver fw_ver;
102	struct rw_semaphore notifier_lock; /* for mmu notifier*/	102	struct rw_semaphore notifier_lock; /* for mmu notifier*/
103	struct workqueue_struct *notifier_wq;	103	struct workqueue_struct *notifier_wq;
104	bool rpm_on;
105	};	104	};
106		105
107	/*	106	/*

drivers/accel/amdxdna/amdxdna_pm.c+2−20

 {
 	struct amdxdna_dev *xdna = to_xdna_dev(dev_get_drvdata(dev));
 	int ret = -EOPNOTSUPP;
-	bool rpm;
-	if (xdna->dev_info->ops->suspend) {
+	if (xdna->dev_info->ops->suspend)
-		rpm = xdna->rpm_on;
-		xdna->rpm_on = false;
 		ret = xdna->dev_info->ops->suspend(xdna);
-		xdna->rpm_on = rpm;
-	}
 	XDNA_DBG(xdna, "Suspend done ret %d", ret);
 	return ret;
 {
 	struct amdxdna_dev *xdna = to_xdna_dev(dev_get_drvdata(dev));
 	int ret = -EOPNOTSUPP;
-	bool rpm;
-	if (xdna->dev_info->ops->resume) {
+	if (xdna->dev_info->ops->resume)
-		rpm = xdna->rpm_on;
-		xdna->rpm_on = false;
 		ret = xdna->dev_info->ops->resume(xdna);
-		xdna->rpm_on = rpm;
-	}
 	XDNA_DBG(xdna, "Resume done ret %d", ret);
 	return ret;
 	struct device *dev = xdna->ddev.dev;
 	int ret;
-	if (!xdna->rpm_on)
-		return 0;
 	ret = pm_runtime_resume_and_get(dev);
 	if (ret) {
 		XDNA_ERR(xdna, "Resume failed: %d", ret);
 {
 	struct device *dev = xdna->ddev.dev;
-	if (!xdna->rpm_on)
-		return;
 	pm_runtime_put_autosuspend(dev);
 }
 	pm_runtime_use_autosuspend(dev);
 	pm_runtime_allow(dev);
 	pm_runtime_put_autosuspend(dev);
-	xdna->rpm_on = true;
 }
 void amdxdna_pm_fini(struct amdxdna_dev *xdna)
 {
 	struct device *dev = xdna->ddev.dev;
-	xdna->rpm_on = false;
 	pm_runtime_get_noresume(dev);
 	pm_runtime_forbid(dev);
 }

drivers/accel/amdxdna/npu1_regs.c+2−0

 #include "amdxdna_pci_drv.h"
 /* Address definition from NPU1 docs */
+#define MPNPU_PWAITMODE			0x3010034
 #define MPNPU_PUB_SEC_INTR		0x3010090
 #define MPNPU_PUB_PWRMGMT_INTR		0x3010094
 #define MPNPU_PUB_SCRATCH2		0x30100A0
 		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU1_PSP, MPNPU_PUB_SEC_INTR),
 		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU1_PSP, MPNPU_PUB_SCRATCH2),
 		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH3),
+		DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU1_PSP, MPNPU_PWAITMODE),
 	},
 	.smu_regs_off   = {
 		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH5),

drivers/accel/amdxdna/npu2_regs.c+2−0

 #include "amdxdna_pci_drv.h"
 /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
+#define MPNPU_PWAITMODE                0x301003C
 #define MPNPU_PUB_SEC_INTR             0x3010060
 #define MPNPU_PUB_PWRMGMT_INTR         0x3010064
 #define MPNPU_PUB_SCRATCH0             0x301006C
 		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU2_PSP, MP0_C2PMSG_73),
 		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU2_PSP, MP0_C2PMSG_123),
 		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU2_REG, MPNPU_PUB_SCRATCH3),
+		DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU2_REG, MPNPU_PWAITMODE),
 	},
 	.smu_regs_off   = {
 		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU2_SMU, MP1_C2PMSG_0),

drivers/accel/amdxdna/npu4_regs.c+2−0

 #include "amdxdna_pci_drv.h"
 /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
+#define MPNPU_PWAITMODE                0x301003C
 #define MPNPU_PUB_SEC_INTR             0x3010060
 #define MPNPU_PUB_PWRMGMT_INTR         0x3010064
 #define MPNPU_PUB_SCRATCH0             0x301006C
 		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU4_PSP, MP0_C2PMSG_73),
 		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU4_PSP, MP0_C2PMSG_123),
 		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU4_REG, MPNPU_PUB_SCRATCH3),
+		DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU4_REG, MPNPU_PWAITMODE),
 	},
 	.smu_regs_off   = {
 		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU4_SMU, MP1_C2PMSG_0),

drivers/accel/amdxdna/npu5_regs.c+2−0

 #include "amdxdna_pci_drv.h"
 /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
+#define MPNPU_PWAITMODE                0x301003C
 #define MPNPU_PUB_SEC_INTR             0x3010060
 #define MPNPU_PUB_PWRMGMT_INTR         0x3010064
 #define MPNPU_PUB_SCRATCH0             0x301006C
 		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU5_PSP, MP0_C2PMSG_73),
 		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU5_PSP, MP0_C2PMSG_123),
 		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU5_REG, MPNPU_PUB_SCRATCH3),
+		DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU5_REG, MPNPU_PWAITMODE),
 	},
 	.smu_regs_off   = {
 		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU5_SMU, MP1_C2PMSG_0),

drivers/accel/amdxdna/npu6_regs.c+2−0

 #include "amdxdna_pci_drv.h"
 /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
+#define MPNPU_PWAITMODE                0x301003C
 #define MPNPU_PUB_SEC_INTR             0x3010060
 #define MPNPU_PUB_PWRMGMT_INTR         0x3010064
 #define MPNPU_PUB_SCRATCH0             0x301006C
 		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU6_PSP, MP0_C2PMSG_73),
 		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123),
 		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU6_REG, MPNPU_PUB_SCRATCH3),
+		DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU6_REG, MPNPU_PWAITMODE),
 	},
 	.smu_regs_off   = {
 		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU6_SMU, MP1_C2PMSG_0),

drivers/dma-buf/Kconfig+1−1

@@ -55,7 +55,7 @@ config DMABUF_MOVE_NOTIFY · 54 unmodified lines
55	config DMABUF_DEBUG	55	config DMABUF_DEBUG
56	bool "DMA-BUF debug checks"	56	bool "DMA-BUF debug checks"
57	depends on DMA_SHARED_BUFFER	57	depends on DMA_SHARED_BUFFER
58	default y if DMA_API_DEBUG	58	default y if DEBUG
59	help	59	help
60	This option enables additional checks for DMA-BUF importers and	60	This option enables additional checks for DMA-BUF importers and
61	exporters. Specifically it validates that importers do not peek at the	61	exporters. Specifically it validates that importers do not peek at the

drivers/dma-buf/dma-buf.c+62−17

@@ -35,6 +35,12 @@ · 34 unmodified lines
35		35
36	#include "dma-buf-sysfs-stats.h"	36	#include "dma-buf-sysfs-stats.h"
37		37
		38	/* Wrapper to hide the sg_table page link from the importer */
		39	struct dma_buf_sg_table_wrapper {
		40	struct sg_table *original;
		41	struct sg_table wrapper;
		42	};
		43
38	static inline int is_dma_buf_file(struct file *);	44	static inline int is_dma_buf_file(struct file *);
39		45
40	static DEFINE_MUTEX(dmabuf_list_mutex);	46	static DEFINE_MUTEX(dmabuf_list_mutex);
@@ -820,21 +826,59 @@ void dma_buf_put(struct dma_buf *dmabuf) · 779 unmodified lines
820	}	826	}
821	EXPORT_SYMBOL_NS_GPL(dma_buf_put, "DMA_BUF");	827	EXPORT_SYMBOL_NS_GPL(dma_buf_put, "DMA_BUF");
822		828
823	static void mangle_sg_table(struct sg_table *sg_table)	829	static int dma_buf_wrap_sg_table(struct sg_table **sg_table)
824	{	830	{
825	#ifdef CONFIG_DMABUF_DEBUG	831	struct scatterlist to_sg, from_sg;
826	int i;	832	struct sg_table from = sg_table;
827	struct scatterlist *sg;	833	struct dma_buf_sg_table_wrapper *to;
828		834	int i, ret;
829	/* To catch abuse of the underlying struct page by importers mix	835
830	* up the bits, but take care to preserve the low SG_ bits to	836	if (!IS_ENABLED(CONFIG_DMABUF_DEBUG))
831	* not corrupt the sgt. The mixing is undone on unmap	837	return 0;
832	* before passing the sgt back to the exporter.	838
		839	/*
		840	* To catch abuse of the underlying struct page by importers copy the
		841	* sg_table without copying the page_link and give only the copy back to
		842	* the importer.
833	*/	843	*/
834	for_each_sgtable_sg(sg_table, sg, i)	844	to = kzalloc(sizeof(*to), GFP_KERNEL);
835	sg->page_link ^= ~0xffUL;	845	if (!to)
836	#endif	846	return -ENOMEM;
		847
		848	ret = sg_alloc_table(&to->wrapper, from->nents, GFP_KERNEL);
		849	if (ret)
		850	goto free_to;
		851
		852	to_sg = to->wrapper.sgl;
		853	for_each_sgtable_dma_sg(from, from_sg, i) {
		854	to_sg->offset = 0;
		855	to_sg->length = 0;
		856	sg_assign_page(to_sg, NULL);
		857	sg_dma_address(to_sg) = sg_dma_address(from_sg);
		858	sg_dma_len(to_sg) = sg_dma_len(from_sg);
		859	to_sg = sg_next(to_sg);
		860	}
837		861
		862	to->original = from;
		863	*sg_table = &to->wrapper;
		864	return 0;
		865
		866	free_to:
		867	kfree(to);
		868	return ret;
		869	}
		870
		871	static void dma_buf_unwrap_sg_table(struct sg_table **sg_table)
		872	{
		873	struct dma_buf_sg_table_wrapper *copy;
		874
		875	if (!IS_ENABLED(CONFIG_DMABUF_DEBUG))
		876	return;
		877
		878	copy = container_of(sg_table, typeof(copy), wrapper);
		879	*sg_table = copy->original;
		880	sg_free_table(&copy->wrapper);
		881	kfree(copy);
838	}	882	}
839		883
840	static inline bool	884	static inline bool
@@ -1131,10 +1175,11 @@ struct sg_table dma_buf_map_attachment(struct dma_buf_attachment attach, · 290 unmodified lines
1131	if (ret < 0)	1175	if (ret < 0)
1132	goto error_unmap;	1176	goto error_unmap;
1133	}	1177	}
1134	mangle_sg_table(sg_table);	1178	ret = dma_buf_wrap_sg_table(&sg_table);
		1179	if (ret)
		1180	goto error_unmap;
1135		1181
1136	#ifdef CONFIG_DMA_API_DEBUG	1182	if (IS_ENABLED(CONFIG_DMA_API_DEBUG)) {
1137	{
1138	struct scatterlist *sg;	1183	struct scatterlist *sg;
1139	u64 addr;	1184	u64 addr;
1140	int len;	1185	int len;
@@ -1146,10 +1191,10 @@ struct sg_table dma_buf_map_attachment(struct dma_buf_attachment attach, · 5 unmodified lines
1146	if (!PAGE_ALIGNED(addr) \|\| !PAGE_ALIGNED(len)) {	1191	if (!PAGE_ALIGNED(addr) \|\| !PAGE_ALIGNED(len)) {
1147	pr_debug("%s: addr %llx or len %x is not page aligned!\n",	1192	pr_debug("%s: addr %llx or len %x is not page aligned!\n",
1148	__func__, addr, len);	1193	__func__, addr, len);
		1194	break;
1149	}	1195	}
1150	}	1196	}
1151	}	1197	}
1152	#endif /* CONFIG_DMA_API_DEBUG */
1153	return sg_table;	1198	return sg_table;
1154		1199
1155	error_unmap:	1200	error_unmap:
@@ -1213,7 +1258,7 @@ void dma_buf_unmap_attachment(struct dma_buf_attachment *attach, · 57 unmodified lines
1213		1258
1214	dma_resv_assert_held(attach->dmabuf->resv);	1259	dma_resv_assert_held(attach->dmabuf->resv);
1215		1260
1216	mangle_sg_table(sg_table);	1261	dma_buf_unwrap_sg_table(&sg_table);
1217	attach->dmabuf->ops->unmap_dma_buf(attach, sg_table, direction);	1262	attach->dmabuf->ops->unmap_dma_buf(attach, sg_table, direction);
1218		1263
1219	if (dma_buf_pin_on_map(attach))	1264	if (dma_buf_pin_on_map(attach))

drivers/dma-buf/dma-fence.c+62−38

  *
  * Unlike dma_fence_signal_timestamp(), this function must be called with
  * &dma_fence.lock held.
- *
- * Returns 0 on success and a negative error value when @fence has been
- * signalled already.
  */
-int dma_fence_signal_timestamp_locked(struct dma_fence *fence,
+void dma_fence_signal_timestamp_locked(struct dma_fence *fence,
 				      ktime_t timestamp)
 {
 	struct dma_fence_cb *cur, *tmp;
 	if (unlikely(test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
 				      &fence->flags)))
-		return -EINVAL;
+		return;
 	/* Stash the cb_list before replacing it with the timestamp */
 	list_replace(&fence->cb_list, &cb_list);
 		INIT_LIST_HEAD(&cur->node);
 		cur->func(fence, cur);
 	}
-	return 0;
 }
 EXPORT_SYMBOL(dma_fence_signal_timestamp_locked);
  * can only go from the unsignaled to the signaled state and not back, it will
  * only be effective the first time. Set the timestamp provided as the fence
  * signal timestamp.
- *
- * Returns 0 on success and a negative error value when @fence has been
- * signalled already.
  */
-int dma_fence_signal_timestamp(struct dma_fence *fence, ktime_t timestamp)
+void dma_fence_signal_timestamp(struct dma_fence *fence, ktime_t timestamp)
 {
 	unsigned long flags;
-	int ret;
 	if (WARN_ON(!fence))
-		return -EINVAL;
+		return;
 	spin_lock_irqsave(fence->lock, flags);
-	ret = dma_fence_signal_timestamp_locked(fence, timestamp);
+	dma_fence_signal_timestamp_locked(fence, timestamp);
 	spin_unlock_irqrestore(fence->lock, flags);
-	return ret;
 }
 EXPORT_SYMBOL(dma_fence_signal_timestamp);
  *
  * Unlike dma_fence_signal(), this function must be called with &dma_fence.lock
  * held.
- *
- * Returns 0 on success and a negative error value when @fence has been
- * signalled already.
  */
-int dma_fence_signal_locked(struct dma_fence *fence)
+void dma_fence_signal_locked(struct dma_fence *fence)
 {
-	return dma_fence_signal_timestamp_locked(fence, ktime_get());
+	dma_fence_signal_timestamp_locked(fence, ktime_get());
 }
 EXPORT_SYMBOL(dma_fence_signal_locked);
+/**
+ * dma_fence_check_and_signal_locked - signal the fence if it's not yet signaled
+ * @fence: the fence to check and signal
+ *
+ * Checks whether a fence was signaled and signals it if it was not yet signaled.
+ *
+ * Unlike dma_fence_check_and_signal(), this function must be called with
+ * &struct dma_fence.lock being held.
+ *
+ * Return: true if fence has been signaled already, false otherwise.
+ */
+bool dma_fence_check_and_signal_locked(struct dma_fence *fence)
+{
+	bool ret;
+	ret = dma_fence_test_signaled_flag(fence);
+	dma_fence_signal_locked(fence);
+	return ret;
+}
+EXPORT_SYMBOL(dma_fence_check_and_signal_locked);
+/**
+ * dma_fence_check_and_signal - signal the fence if it's not yet signaled
+ * @fence: the fence to check and signal
+ *
+ * Checks whether a fence was signaled and signals it if it was not yet signaled.
+ * All this is done in a race-free manner.
+ *
+ * Return: true if fence has been signaled already, false otherwise.
+ */
+bool dma_fence_check_and_signal(struct dma_fence *fence)
+{
+	unsigned long flags;
+	bool ret;
+	spin_lock_irqsave(fence->lock, flags);
+	ret = dma_fence_check_and_signal_locked(fence);
+	spin_unlock_irqrestore(fence->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(dma_fence_check_and_signal);
 /**
  * dma_fence_signal - signal completion of a fence
  * @fence: the fence to signal
  * dma_fence_add_callback(). Can be called multiple times, but since a fence
  * can only go from the unsignaled to the signaled state and not back, it will
  * only be effective the first time.
- *
- * Returns 0 on success and a negative error value when @fence has been
- * signalled already.
  */
-int dma_fence_signal(struct dma_fence *fence)
+void dma_fence_signal(struct dma_fence *fence)
 {
 	unsigned long flags;
-	int ret;
 	bool tmp;
 	if (WARN_ON(!fence))
-		return -EINVAL;
+		return;
 	tmp = dma_fence_begin_signalling();
 	spin_lock_irqsave(fence->lock, flags);
-	ret = dma_fence_signal_timestamp_locked(fence, ktime_get());
+	dma_fence_signal_timestamp_locked(fence, ktime_get());
 	spin_unlock_irqrestore(fence->lock, flags);
 	dma_fence_end_signalling(tmp);
-	return ret;
 }
 EXPORT_SYMBOL(dma_fence_signal);
 	trace_dma_fence_destroy(fence);
 	if (!list_empty(&fence->cb_list) &&
-	    !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
+	    !dma_fence_test_signaled_flag(fence)) {
 		const char __rcu *timeline;
 		const char __rcu *driver;
 		unsigned long flags;
 	was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
 				   &fence->flags);
-	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
+	if (dma_fence_test_signaled_flag(fence))
 		return false;
 	if (!was_set && fence->ops->enable_signaling) {
 	if (WARN_ON(!fence || !func))
 		return -EINVAL;
-	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
+	if (dma_fence_test_signaled_flag(fence)) {
 		INIT_LIST_HEAD(&cb->node);
 		return -ENOENT;
 	}
 	spin_lock_irqsave(fence->lock, flags);
-	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
+	if (dma_fence_test_signaled_flag(fence))
 		goto out;
 	if (intr && signal_pending(current)) {
 	cb.task = current;
 	list_add(&cb.base.node, &fence->cb_list);
-	while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) {
+	while (!dma_fence_test_signaled_flag(fence) && ret > 0) {
 		if (intr)
 			__set_current_state(TASK_INTERRUPTIBLE);
 		else
 	for (i = 0; i < count; ++i) {
 		struct dma_fence *fence = fences[i];
-		if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
+		if (dma_fence_test_signaled_flag(fence)) {
 			if (idx)
 				*idx = i;
 			return true;
 	RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
 			 "RCU protection is required for safe access to returned string");
-	if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
+	if (!dma_fence_test_signaled_flag(fence))
 		return fence->ops->get_driver_name(fence);
 	else
 		return "detached-driver";
 	RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
 			 "RCU protection is required for safe access to returned string");
-	if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
+	if (!dma_fence_test_signaled_flag(fence))
 		return fence->ops->get_timeline_name(fence);
 	else
 		return "signaled-timeline";

drivers/dma-buf/st-dma-fence.c+2−2

@@ -126,7 +126,7 @@ static int test_signaling(void *arg) · 125 unmodified lines
126	goto err_free;	126	goto err_free;
127	}	127	}
128		128
129	if (dma_fence_signal(f)) {	129	if (dma_fence_check_and_signal(f)) {
130	pr_err("Fence reported being already signaled\n");	130	pr_err("Fence reported being already signaled\n");
131	goto err_free;	131	goto err_free;
132	}	132	}
@@ -136,7 +136,7 @@ static int test_signaling(void *arg) · 3 unmodified lines
136	goto err_free;	136	goto err_free;
137	}	137	}
138		138
139	if (!dma_fence_signal(f)) {	139	if (!dma_fence_test_signaled_flag(f)) {
140	pr_err("Fence reported not being already signaled\n");	140	pr_err("Fence reported not being already signaled\n");
141	goto err_free;	141	goto err_free;
142	}	142	}

drivers/gpu/drm/Kconfig+59−140

@@ -265,164 +265,83 @@ config DRM_SCHED · 264 unmodified lines
265	tristate	265	tristate
266	depends on DRM	266	depends on DRM
267		267
268	source "drivers/gpu/drm/sysfb/Kconfig"	268	# Separate option as not all DRM drivers use it
		269	config DRM_PANEL_BACKLIGHT_QUIRKS
		270	tristate
269		271
270	source "drivers/gpu/drm/arm/Kconfig"	272	config DRM_LIB_RANDOM
		273	bool
		274	default n
271		275
272	source "drivers/gpu/drm/radeon/Kconfig"	276	config DRM_PRIVACY_SCREEN
		277	bool
		278	default n
273		279
		280	# DRM driver Kconfig files, sorted
		281	source "drivers/gpu/drm/adp/Kconfig"
274	source "drivers/gpu/drm/amd/amdgpu/Kconfig"	282	source "drivers/gpu/drm/amd/amdgpu/Kconfig"
275		283	source "drivers/gpu/drm/arm/Kconfig"
276	source "drivers/gpu/drm/nouveau/Kconfig"
277
278	source "drivers/gpu/drm/nova/Kconfig"
279
280	source "drivers/gpu/drm/i915/Kconfig"
281
282	source "drivers/gpu/drm/xe/Kconfig"
283
284	source "drivers/gpu/drm/kmb/Kconfig"
285
286	config DRM_VGEM
287	tristate "Virtual GEM provider"
288	depends on DRM && MMU
289	select DRM_GEM_SHMEM_HELPER
290	help
291	Choose this option to get a virtual graphics memory manager,
292	as used by Mesa's software renderer for enhanced performance.
293	If M is selected the module will be called vgem.
294
295	source "drivers/gpu/drm/vkms/Kconfig"
296
297	source "drivers/gpu/drm/exynos/Kconfig"
298
299	source "drivers/gpu/drm/rockchip/Kconfig"
300
301	source "drivers/gpu/drm/vmwgfx/Kconfig"
302
303	source "drivers/gpu/drm/gma500/Kconfig"
304
305	source "drivers/gpu/drm/udl/Kconfig"
306
307	source "drivers/gpu/drm/ast/Kconfig"
308
309	source "drivers/gpu/drm/mgag200/Kconfig"
310
311	source "drivers/gpu/drm/armada/Kconfig"	284	source "drivers/gpu/drm/armada/Kconfig"
312		285	source "drivers/gpu/drm/aspeed/Kconfig"
		286	source "drivers/gpu/drm/ast/Kconfig"
313	source "drivers/gpu/drm/atmel-hlcdc/Kconfig"	287	source "drivers/gpu/drm/atmel-hlcdc/Kconfig"
314
315	source "drivers/gpu/drm/renesas/Kconfig"
316
317	source "drivers/gpu/drm/sun4i/Kconfig"
318
319	source "drivers/gpu/drm/omapdrm/Kconfig"
320
321	source "drivers/gpu/drm/tilcdc/Kconfig"
322
323	source "drivers/gpu/drm/qxl/Kconfig"
324
325	source "drivers/gpu/drm/virtio/Kconfig"
326
327	source "drivers/gpu/drm/msm/Kconfig"
328
329	source "drivers/gpu/drm/fsl-dcu/Kconfig"
330
331	source "drivers/gpu/drm/tegra/Kconfig"
332
333	source "drivers/gpu/drm/stm/Kconfig"
334
335	source "drivers/gpu/drm/panel/Kconfig"
336
337	source "drivers/gpu/drm/bridge/Kconfig"	288	source "drivers/gpu/drm/bridge/Kconfig"
338
339	source "drivers/gpu/drm/sti/Kconfig"
340
341	source "drivers/gpu/drm/imx/Kconfig"
342
343	source "drivers/gpu/drm/ingenic/Kconfig"
344
345	source "drivers/gpu/drm/v3d/Kconfig"
346
347	source "drivers/gpu/drm/vc4/Kconfig"
348
349	source "drivers/gpu/drm/loongson/Kconfig"
350
351	source "drivers/gpu/drm/etnaviv/Kconfig"	289	source "drivers/gpu/drm/etnaviv/Kconfig"
352		290	source "drivers/gpu/drm/exynos/Kconfig"
		291	source "drivers/gpu/drm/fsl-dcu/Kconfig"
		292	source "drivers/gpu/drm/gma500/Kconfig"
		293	source "drivers/gpu/drm/gud/Kconfig"
353	source "drivers/gpu/drm/hisilicon/Kconfig"	294	source "drivers/gpu/drm/hisilicon/Kconfig"
354		295	source "drivers/gpu/drm/hyperv/Kconfig"
		296	source "drivers/gpu/drm/i915/Kconfig"
		297	source "drivers/gpu/drm/imagination/Kconfig"
		298	source "drivers/gpu/drm/imx/Kconfig"
		299	source "drivers/gpu/drm/ingenic/Kconfig"
		300	source "drivers/gpu/drm/kmb/Kconfig"
		301	source "drivers/gpu/drm/lima/Kconfig"
355	source "drivers/gpu/drm/logicvc/Kconfig"	302	source "drivers/gpu/drm/logicvc/Kconfig"
356		303	source "drivers/gpu/drm/loongson/Kconfig"
		304	source "drivers/gpu/drm/mcde/Kconfig"
357	source "drivers/gpu/drm/mediatek/Kconfig"	305	source "drivers/gpu/drm/mediatek/Kconfig"
358
359	source "drivers/gpu/drm/mxsfb/Kconfig"
360
361	source "drivers/gpu/drm/meson/Kconfig"	306	source "drivers/gpu/drm/meson/Kconfig"
362		307	source "drivers/gpu/drm/mgag200/Kconfig"
363	source "drivers/gpu/drm/tiny/Kconfig"	308	source "drivers/gpu/drm/msm/Kconfig"
364		309	source "drivers/gpu/drm/mxsfb/Kconfig"
365	source "drivers/gpu/drm/pl111/Kconfig"	310	source "drivers/gpu/drm/nouveau/Kconfig"
366		311	source "drivers/gpu/drm/nova/Kconfig"
367	source "drivers/gpu/drm/tve200/Kconfig"	312	source "drivers/gpu/drm/omapdrm/Kconfig"
368		313	source "drivers/gpu/drm/panel/Kconfig"
369	source "drivers/gpu/drm/xen/Kconfig"
370
371	source "drivers/gpu/drm/vboxvideo/Kconfig"
372
373	source "drivers/gpu/drm/lima/Kconfig"
374
375	source "drivers/gpu/drm/panfrost/Kconfig"	314	source "drivers/gpu/drm/panfrost/Kconfig"
376
377	source "drivers/gpu/drm/panthor/Kconfig"	315	source "drivers/gpu/drm/panthor/Kconfig"
378		316	source "drivers/gpu/drm/pl111/Kconfig"
379	source "drivers/gpu/drm/aspeed/Kconfig"	317	source "drivers/gpu/drm/qxl/Kconfig"
380		318	source "drivers/gpu/drm/radeon/Kconfig"
381	source "drivers/gpu/drm/mcde/Kconfig"	319	source "drivers/gpu/drm/renesas/Kconfig"
382		320	source "drivers/gpu/drm/rockchip/Kconfig"
383	source "drivers/gpu/drm/tidss/Kconfig"
384
385	source "drivers/gpu/drm/adp/Kconfig"
386
387	source "drivers/gpu/drm/xlnx/Kconfig"
388
389	source "drivers/gpu/drm/gud/Kconfig"
390
391	source "drivers/gpu/drm/sitronix/Kconfig"	321	source "drivers/gpu/drm/sitronix/Kconfig"
392
393	source "drivers/gpu/drm/solomon/Kconfig"	322	source "drivers/gpu/drm/solomon/Kconfig"
394
395	source "drivers/gpu/drm/sprd/Kconfig"	323	source "drivers/gpu/drm/sprd/Kconfig"
396		324	source "drivers/gpu/drm/sti/Kconfig"
397	source "drivers/gpu/drm/imagination/Kconfig"	325	source "drivers/gpu/drm/stm/Kconfig"
398		326	source "drivers/gpu/drm/sun4i/Kconfig"
		327	source "drivers/gpu/drm/sysfb/Kconfig"
		328	source "drivers/gpu/drm/tegra/Kconfig"
		329	source "drivers/gpu/drm/tidss/Kconfig"
		330	source "drivers/gpu/drm/tilcdc/Kconfig"
		331	source "drivers/gpu/drm/tiny/Kconfig"
		332	source "drivers/gpu/drm/tve200/Kconfig"
399	source "drivers/gpu/drm/tyr/Kconfig"	333	source "drivers/gpu/drm/tyr/Kconfig"
400		334	source "drivers/gpu/drm/udl/Kconfig"
401	config DRM_HYPERV	335	source "drivers/gpu/drm/v3d/Kconfig"
402	tristate "DRM Support for Hyper-V synthetic video device"	336	source "drivers/gpu/drm/vboxvideo/Kconfig"
403	depends on DRM && PCI && HYPERV_VMBUS	337	source "drivers/gpu/drm/vc4/Kconfig"
404	select DRM_CLIENT_SELECTION	338	source "drivers/gpu/drm/vgem/Kconfig"
405	select DRM_KMS_HELPER	339	source "drivers/gpu/drm/virtio/Kconfig"
406	select DRM_GEM_SHMEM_HELPER	340	source "drivers/gpu/drm/vkms/Kconfig"
407	help	341	source "drivers/gpu/drm/vmwgfx/Kconfig"
408	This is a KMS driver for Hyper-V synthetic video device. Choose this	342	source "drivers/gpu/drm/xe/Kconfig"
409	option if you would like to enable drm driver for Hyper-V virtual	343	source "drivers/gpu/drm/xen/Kconfig"
410	machine. Unselect Hyper-V framebuffer driver (CONFIG_FB_HYPERV) so	344	source "drivers/gpu/drm/xlnx/Kconfig"
411	that DRM driver is used by default.
412
413	If M is selected the module will be called hyperv_drm.
414
415	# Separate option as not all DRM drivers use it
416	config DRM_PANEL_BACKLIGHT_QUIRKS
417	tristate
418
419	config DRM_LIB_RANDOM
420	bool
421	default n
422
423	config DRM_PRIVACY_SCREEN
424	bool
425	default n
426		345
427	endif	346	endif
428		347

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c+11−24

 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
 				     struct drm_framebuffer *fb,
-				     int x, int y, int atomic)
+				     int x, int y)
 {
 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	bool bypass_lut = false;
 	/* no fb bound */
-	if (!atomic && !crtc->primary->fb) {
+	if (!crtc->primary->fb) {
 		DRM_DEBUG_KMS("No FB bound\n");
 		return 0;
 	}
-	if (atomic)
+	target_fb = crtc->primary->fb;
-		target_fb = fb;
-	else
-		target_fb = crtc->primary->fb;
 	/* If atomic, assume fb object is pinned & idle & fenced and
 	 * just update base pointers
 	if (unlikely(r != 0))
 		return r;
-	if (!atomic) {
+	abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-		abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+	r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
-		r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
+	if (unlikely(r != 0)) {
-		if (unlikely(r != 0)) {
+		amdgpu_bo_unreserve(abo);
-			amdgpu_bo_unreserve(abo);
+		return -EINVAL;
-			return -EINVAL;
-		}
 	}
 	fb_location = amdgpu_bo_gpu_offset(abo);
 	/* set pageflip to happen anywhere in vblank interval */
 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
-	if (!atomic && fb && fb != crtc->primary->fb) {
+	if (fb && fb != crtc->primary->fb) {
 		abo = gem_to_amdgpu_bo(fb->obj[0]);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r != 0))
 	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
 	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
-	dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
+	dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y);
 	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
 	amdgpu_atombios_crtc_scaler_setup(crtc);
 	dce_v10_0_cursor_reset(crtc);
 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 				  struct drm_framebuffer *old_fb)
 {
-	return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
+	return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y);
-}
-static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
-					 struct drm_framebuffer *fb,
-					 int x, int y, enum mode_set_atomic state)
-{
-	return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
 }
 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
 	.mode_fixup = dce_v10_0_crtc_mode_fixup,
 	.mode_set = dce_v10_0_crtc_mode_set,
 	.mode_set_base = dce_v10_0_crtc_set_base,
-	.mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
 	.prepare = dce_v10_0_crtc_prepare,
 	.commit = dce_v10_0_crtc_commit,
 	.disable = dce_v10_0_crtc_disable,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c+11−24

 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
 				     struct drm_framebuffer *fb,
-				     int x, int y, int atomic)
+				     int x, int y)
 {
 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	bool bypass_lut = false;
 	/* no fb bound */
-	if (!atomic && !crtc->primary->fb) {
+	if (!crtc->primary->fb) {
 		DRM_DEBUG_KMS("No FB bound\n");
 		return 0;
 	}
-	if (atomic)
+	target_fb = crtc->primary->fb;
-		target_fb = fb;
-	else
-		target_fb = crtc->primary->fb;
 	/* If atomic, assume fb object is pinned & idle & fenced and
 	 * just update base pointers
 	if (unlikely(r != 0))
 		return r;
-	if (!atomic) {
+	abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-		abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+	r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
-		r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
+	if (unlikely(r != 0)) {
-		if (unlikely(r != 0)) {
+		amdgpu_bo_unreserve(abo);
-			amdgpu_bo_unreserve(abo);
+		return -EINVAL;
-			return -EINVAL;
-		}
 	}
 	fb_location = amdgpu_bo_gpu_offset(abo);
 	/* set pageflip to happen anywhere in vblank interval */
 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
-	if (!atomic && fb && fb != crtc->primary->fb) {
+	if (fb && fb != crtc->primary->fb) {
 		abo = gem_to_amdgpu_bo(fb->obj[0]);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r != 0))
 	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
 	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
-	dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
+	dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y);
 	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
 	amdgpu_atombios_crtc_scaler_setup(crtc);
 	dce_v6_0_cursor_reset(crtc);
 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 				  struct drm_framebuffer *old_fb)
 {
-	return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
+	return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y);
-}
-static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
-					 struct drm_framebuffer *fb,
-					 int x, int y, enum mode_set_atomic state)
-{
-	return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
 }
 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
 	.mode_fixup = dce_v6_0_crtc_mode_fixup,
 	.mode_set = dce_v6_0_crtc_mode_set,
 	.mode_set_base = dce_v6_0_crtc_set_base,
-	.mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
 	.prepare = dce_v6_0_crtc_prepare,
 	.commit = dce_v6_0_crtc_commit,
 	.disable = dce_v6_0_crtc_disable,

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c+11−24

 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
 				     struct drm_framebuffer *fb,
-				     int x, int y, int atomic)
+				     int x, int y)
 {
 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	bool bypass_lut = false;
 	/* no fb bound */
-	if (!atomic && !crtc->primary->fb) {
+	if (!crtc->primary->fb) {
 		DRM_DEBUG_KMS("No FB bound\n");
 		return 0;
 	}
-	if (atomic)
+	target_fb = crtc->primary->fb;
-		target_fb = fb;
-	else
-		target_fb = crtc->primary->fb;
 	/* If atomic, assume fb object is pinned & idle & fenced and
 	 * just update base pointers
 	if (unlikely(r != 0))
 		return r;
-	if (!atomic) {
+	abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-		abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+	r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
-		r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
+	if (unlikely(r != 0)) {
-		if (unlikely(r != 0)) {
+		amdgpu_bo_unreserve(abo);
-			amdgpu_bo_unreserve(abo);
+		return -EINVAL;
-			return -EINVAL;
-		}
 	}
 	fb_location = amdgpu_bo_gpu_offset(abo);
 	/* set pageflip to happen anywhere in vblank interval */
 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
-	if (!atomic && fb && fb != crtc->primary->fb) {
+	if (fb && fb != crtc->primary->fb) {
 		abo = gem_to_amdgpu_bo(fb->obj[0]);
 		r = amdgpu_bo_reserve(abo, true);
 		if (unlikely(r != 0))
 	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
 	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
-	dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
+	dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y);
 	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
 	amdgpu_atombios_crtc_scaler_setup(crtc);
 	dce_v8_0_cursor_reset(crtc);
 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 				  struct drm_framebuffer *old_fb)
 {
-	return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
+	return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y);
-}
-static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
-					 struct drm_framebuffer *fb,
-					 int x, int y, enum mode_set_atomic state)
-{
-	return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
 }
 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
 	.mode_fixup = dce_v8_0_crtc_mode_fixup,
 	.mode_set = dce_v8_0_crtc_mode_set,
 	.mode_set_base = dce_v8_0_crtc_set_base,
-	.mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
 	.prepare = dce_v8_0_crtc_prepare,
 	.commit = dce_v8_0_crtc_commit,
 	.disable = dce_v8_0_crtc_disable,

drivers/gpu/drm/amd/amdkfd/kfd_process.c+3−3

@@ -1987,10 +1987,10 @@ kfd_process_gpuid_from_node(struct kfd_process p, struct kfd_node node, · 1986 unmodified lines
1987	return -EINVAL;	1987	return -EINVAL;
1988	}	1988	}
1989		1989
1990	static int signal_eviction_fence(struct kfd_process *p)	1990	static bool signal_eviction_fence(struct kfd_process *p)
1991	{	1991	{
1992	struct dma_fence *ef;	1992	struct dma_fence *ef;
1993	int ret;	1993	bool ret;
1994		1994
1995	rcu_read_lock();	1995	rcu_read_lock();
1996	ef = dma_fence_get_rcu_safe(&p->ef);	1996	ef = dma_fence_get_rcu_safe(&p->ef);
@@ -1998,7 +1998,7 @@ static int signal_eviction_fence(struct kfd_process *p) · 1 unmodified line
1998	if (!ef)	1998	if (!ef)
1999	return -EINVAL;	1999	return -EINVAL;
2000		2000
2001	ret = dma_fence_signal(ef);	2001	ret = dma_fence_check_and_signal(ef);
2002	dma_fence_put(ef);	2002	dma_fence_put(ef);
2003		2003
2004	return ret;	2004	return ret;

drivers/gpu/drm/ast/ast_cursor.c+62−21

@@ -28,6 +28,7 @@ · 27 unmodified lines
28	#include <drm/drm_damage_helper.h>	28	#include <drm/drm_damage_helper.h>
29	#include <drm/drm_format_helper.h>	29	#include <drm/drm_format_helper.h>
30	#include <drm/drm_gem_atomic_helper.h>	30	#include <drm/drm_gem_atomic_helper.h>
		31	#include <drm/drm_gem_framebuffer_helper.h>
31	#include <drm/drm_print.h>	32	#include <drm/drm_print.h>
32		33
33	#include "ast_drv.h"	34	#include "ast_drv.h"
@@ -181,6 +182,62 @@ static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, · 147 unmodified lines
181	return 0;	182	return 0;
182	}	183	}
183		184
		185	static const u8 ast_cursor_plane_get_argb4444(struct ast_cursor_plane ast_cursor_plane,
		186	struct drm_shadow_plane_state *shadow_plane_state,
		187	const struct drm_rect *clip)
		188	{
		189	struct drm_plane_state *plane_state = &shadow_plane_state->base;
		190	struct drm_framebuffer *fb = plane_state->fb;
		191	u8 *argb4444 = NULL;
		192
		193	if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE) == 0) {
		194	switch (fb->format->format) {
		195	case DRM_FORMAT_ARGB4444:
		196	if (shadow_plane_state->data[0].is_iomem) {
		197	struct iosys_map argb4444_dst[DRM_FORMAT_MAX_PLANES] = {
		198	IOSYS_MAP_INIT_VADDR(ast_cursor_plane->argb4444),
		199	};
		200	unsigned int argb4444_dst_pitch[DRM_FORMAT_MAX_PLANES] = {
		201	AST_HWC_PITCH,
		202	};
		203
		204	drm_fb_memcpy(argb4444_dst, argb4444_dst_pitch,
		205	shadow_plane_state->data, fb, clip);
		206	argb4444 = argb4444_dst[0].vaddr;
		207	} else {
		208	argb4444 = shadow_plane_state->data[0].vaddr;
		209	}
		210	break;
		211	case DRM_FORMAT_ARGB8888:
		212	{
		213	struct iosys_map argb4444_dst[DRM_FORMAT_MAX_PLANES] = {
		214	IOSYS_MAP_INIT_VADDR(ast_cursor_plane->argb4444),
		215	};
		216	unsigned int argb4444_dst_pitch[DRM_FORMAT_MAX_PLANES] = {
		217	AST_HWC_PITCH,
		218	};
		219
		220	drm_fb_argb8888_to_argb4444(argb4444_dst, argb4444_dst_pitch,
		221	shadow_plane_state->data, fb, clip,
		222	&shadow_plane_state->fmtcnv_state);
		223	argb4444 = argb4444_dst[0].vaddr;
		224	}
		225	break;
		226	}
		227
		228	drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
		229	} else {
		230	/*
		231	* Fall back to white square if GEM object is not ready. Gives
		232	* the user an indication where the cursor is located.
		233	*/
		234	memset(ast_cursor_plane->argb4444, 0xff, sizeof(ast_cursor_plane->argb4444));
		235	argb4444 = ast_cursor_plane->argb4444;
		236	}
		237
		238	return argb4444;
		239	}
		240
184	static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,	241	static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,
185	struct drm_atomic_state *state)	242	struct drm_atomic_state *state)
186	{	243	{
@@ -205,29 +262,13 @@ static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, · 18 unmodified lines
205	*/	262	*/
206		263
207	if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &damage)) {	264	if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &damage)) {
208	u8 *argb4444;	265	const u8 *argb4444 = ast_cursor_plane_get_argb4444(ast_cursor_plane,
		266	shadow_plane_state,
		267	&damage);
209		268
210	switch (fb->format->format) {	269	if (argb4444)
211	case DRM_FORMAT_ARGB4444:	270	ast_set_cursor_image(ast, argb4444, fb->width, fb->height);
212	argb4444 = shadow_plane_state->data[0].vaddr;
213	break;
214	default:
215	argb4444 = ast_cursor_plane->argb4444;
216	{
217	struct iosys_map argb4444_dst[DRM_FORMAT_MAX_PLANES] = {
218	IOSYS_MAP_INIT_VADDR(argb4444),
219	};
220	unsigned int argb4444_dst_pitch[DRM_FORMAT_MAX_PLANES] = {
221	AST_HWC_PITCH,
222	};
223		271
224	drm_fb_argb8888_to_argb4444(argb4444_dst, argb4444_dst_pitch,
225	shadow_plane_state->data, fb, &damage,
226	&shadow_plane_state->fmtcnv_state);
227	}
228	break;
229	}
230	ast_set_cursor_image(ast, argb4444, fb->width, fb->height);
231	ast_set_cursor_base(ast, dst_off);	272	ast_set_cursor_base(ast, dst_off);
232	}	273	}
233		274

drivers/gpu/drm/bridge/ti-sn65dsi83.c+66−20

 {
 	struct sn65dsi83 *ctx = container_of(ws, struct sn65dsi83, reset_work);
 	int ret;
+	int idx;
+	if (!drm_bridge_enter(&ctx->bridge, &idx))
+		return;
 	/* Reset the pipe */
 	ret = sn65dsi83_reset_pipe(ctx);
 	}
 	if (ctx->irq)
 		enable_irq(ctx->irq);
+	drm_bridge_exit(idx);
 }
 static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx)
 {
 	unsigned int irq_stat;
 	int ret;
+	int idx;
+	if (!drm_bridge_enter(&ctx->bridge, &idx))
+		return;
 	/*
 	 * Schedule a reset in case of:
 		schedule_work(&ctx->reset_work);
 	}
+	drm_bridge_exit(idx);
 }
 static void sn65dsi83_monitor_work(struct work_struct *work)
 	cancel_delayed_work_sync(&ctx->monitor_work);
 }
+/*
+ * Release resources taken by sn65dsi83_atomic_pre_enable().
+ *
+ * Invoked by sn65dsi83_atomic_disable() normally, or by devres after
+ * sn65dsi83_remove() in case this happens befora atomic_disable.
+ */
+static void sn65dsi83_release_resources(void *data)
+{
+	struct sn65dsi83 *ctx = (struct sn65dsi83 *)data;
+	int ret;
+	if (ctx->irq) {
+		/* Disable irq */
+		regmap_write(ctx->regmap, REG_IRQ_EN, 0x0);
+		regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0);
+	} else {
+		/* Stop the polling task */
+		sn65dsi83_monitor_stop(ctx);
+	}
+	/* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
+	gpiod_set_value_cansleep(ctx->enable_gpio, 0);
+	usleep_range(10000, 11000);
+	ret = regulator_disable(ctx->vcc);
+	if (ret)
+		dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret);
+	regcache_mark_dirty(ctx->regmap);
+}
 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
 					struct drm_atomic_state *state)
 {
 	__le16 le16val;
 	u16 val;
 	int ret;
+	int idx;
+	if (!drm_bridge_enter(bridge, &idx))
+		return;
 	ret = regulator_enable(ctx->vcc);
 	if (ret) {
 		dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret);
-		return;
+		goto err_exit;
 	}
 	/* Deassert reset */
 		dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
 		/* On failure, disable PLL again and exit. */
 		regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
-		return;
+		goto err_add_action;
 	}
 	/* Trigger reset after CSR register update. */
 	/* Wait for 10ms after soft reset as specified in datasheet */
 	usleep_range(10000, 12000);
+err_add_action:
+	devm_add_action(ctx->dev, sn65dsi83_release_resources, ctx);
+err_exit:
+	drm_bridge_exit(idx);
 }
 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
 {
 	struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
 	unsigned int pval;
+	int idx;
+	if (!drm_bridge_enter(bridge, &idx))
+		return;
 	/* Clear all errors that got asserted during initialization. */
 	regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
 		/* Use the polling task */
 		sn65dsi83_monitor_start(ctx);
 	}
+	drm_bridge_exit(idx);
 }
 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge,
 				     struct drm_atomic_state *state)
 {
 	struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
-	int ret;
+	int idx;
-	if (ctx->irq) {
+	if (!drm_bridge_enter(bridge, &idx))
-		/* Disable irq */
+		return;
-		regmap_write(ctx->regmap, REG_IRQ_EN, 0x0);
-		regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0);
-	} else {
-		/* Stop the polling task */
-		sn65dsi83_monitor_stop(ctx);
-	}
-	/* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
-	gpiod_set_value_cansleep(ctx->enable_gpio, 0);
-	usleep_range(10000, 11000);
-	ret = regulator_disable(ctx->vcc);
+	devm_release_action(ctx->dev, sn65dsi83_release_resources, ctx);
-	if (ret)
-		dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret);
-	regcache_mark_dirty(ctx->regmap);
+	drm_bridge_exit(idx);
 }
 static enum drm_mode_status
 {
 	struct sn65dsi83 *ctx = i2c_get_clientdata(client);
-	drm_bridge_remove(&ctx->bridge);
+	drm_bridge_unplug(&ctx->bridge);
 }
 static const struct i2c_device_id sn65dsi83_id[] = {

drivers/gpu/drm/display/drm_dp_mst_topology.c+2−1

@@ -4572,7 +4572,8 @@ int drm_dp_atomic_release_time_slots(struct drm_atomic_state *state, · 4571 unmodified lines
4572	if (!payload->delete) {	4572	if (!payload->delete) {
4573	payload->pbn = 0;	4573	payload->pbn = 0;
4574	payload->delete = true;	4574	payload->delete = true;
4575	topology_state->payload_mask &= ~BIT(payload->vcpi - 1);	4575	if (payload->vcpi > 0)
		4576	topology_state->payload_mask &= ~BIT(payload->vcpi - 1);
4576	}	4577	}
4577		4578
4578	return 0;	4579	return 0;

drivers/gpu/drm/drm_atomic.c+1−0

@@ -906,6 +906,7 @@ drm_atomic_private_obj_init(struct drm_device *dev, · 905 unmodified lines
906		906
907	drm_modeset_lock_init(&obj->lock);	907	drm_modeset_lock_init(&obj->lock);
908		908
		909	obj->dev = dev;
909	obj->state = state;	910	obj->state = state;
910	obj->funcs = funcs;	911	obj->funcs = funcs;
911	list_add_tail(&obj->head, &dev->mode_config.privobj_list);	912	list_add_tail(&obj->head, &dev->mode_config.privobj_list);

drivers/gpu/drm/drm_bridge.c+62−0

@@ -27,6 +27,7 @@ · 26 unmodified lines
27	#include <linux/media-bus-format.h>	27	#include <linux/media-bus-format.h>
28	#include <linux/module.h>	28	#include <linux/module.h>
29	#include <linux/mutex.h>	29	#include <linux/mutex.h>
		30	#include <linux/srcu.h>
30		31
31	#include <drm/drm_atomic_state_helper.h>	32	#include <drm/drm_atomic_state_helper.h>
32	#include <drm/drm_bridge.h>	33	#include <drm/drm_bridge.h>
@@ -202,6 +203,67 @@ static DEFINE_MUTEX(bridge_lock); · 169 unmodified lines
202	static LIST_HEAD(bridge_list);	203	static LIST_HEAD(bridge_list);
203	static LIST_HEAD(bridge_lingering_list);	204	static LIST_HEAD(bridge_lingering_list);
204		205
		206	DEFINE_STATIC_SRCU(drm_bridge_unplug_srcu);
		207
		208	/**
		209	* drm_bridge_enter - Enter DRM bridge critical section
		210	* @bridge: DRM bridge
		211	* @idx: Pointer to index that will be passed to the matching drm_bridge_exit()
		212	*
		213	* This function marks and protects the beginning of a section that should not
		214	* be entered after the bridge has been unplugged. The section end is marked
		215	* with drm_bridge_exit(). Calls to this function can be nested.
		216	*
		217	* Returns:
		218	* True if it is OK to enter the section, false otherwise.
		219	*/
		220	bool drm_bridge_enter(struct drm_bridge bridge, int idx)
		221	{
		222	*idx = srcu_read_lock(&drm_bridge_unplug_srcu);
		223
		224	if (bridge->unplugged) {
		225	srcu_read_unlock(&drm_bridge_unplug_srcu, *idx);
		226	return false;
		227	}
		228
		229	return true;
		230	}
		231	EXPORT_SYMBOL(drm_bridge_enter);
		232
		233	/**
		234	* drm_bridge_exit - Exit DRM bridge critical section
		235	* @idx: index returned by drm_bridge_enter()
		236	*
		237	* This function marks the end of a section that should not be entered after
		238	* the bridge has been unplugged.
		239	*/
		240	void drm_bridge_exit(int idx)
		241	{
		242	srcu_read_unlock(&drm_bridge_unplug_srcu, idx);
		243	}
		244	EXPORT_SYMBOL(drm_bridge_exit);
		245
		246	/**
		247	* drm_bridge_unplug - declare a DRM bridge was unplugged and remove it
		248	* @bridge: DRM bridge
		249	*
		250	* This tells the bridge has been physically unplugged and no operations on
		251	* device resources must be done anymore. Entry-points can use
		252	* drm_bridge_enter() and drm_bridge_exit() to protect device resources in
		253	* a race free manner.
		254	*
		255	* Also unregisters the bridge.
		256	*/
		257	void drm_bridge_unplug(struct drm_bridge *bridge)
		258	{
		259	bridge->unplugged = true;
		260
		261	synchronize_srcu(&drm_bridge_unplug_srcu);
		262
		263	drm_bridge_remove(bridge);
		264	}
		265	EXPORT_SYMBOL(drm_bridge_unplug);
		266
205	static void __drm_bridge_free(struct kref *kref)	267	static void __drm_bridge_free(struct kref *kref)
206	{	268	{
207	struct drm_bridge *bridge = container_of(kref, struct drm_bridge, refcount);	269	struct drm_bridge *bridge = container_of(kref, struct drm_bridge, refcount);

drivers/gpu/drm/drm_fb_helper.c+0−108

@@ -75,9 +75,6 @@ MODULE_PARM_DESC(drm_leak_fbdev_smem, · 74 unmodified lines
75	"Allow unsafe leaking fbdev physical smem address [default=false]");	75	"Allow unsafe leaking fbdev physical smem address [default=false]");
76	#endif	76	#endif
77		77
78	static LIST_HEAD(kernel_fb_helper_list);
79	static DEFINE_MUTEX(kernel_fb_helper_lock);
80
81	/**	78	/**
82	* DOC: fbdev helpers	79	* DOC: fbdev helpers
83	*	80	*
@@ -115,101 +112,6 @@ static DEFINE_MUTEX(kernel_fb_helper_lock); · 31 unmodified lines
115	* mmap page writes.	112	* mmap page writes.
116	*/	113	*/
117		114
118	static void drm_fb_helper_restore_lut_atomic(struct drm_crtc *crtc)
119	{
120	uint16_t r_base, g_base, *b_base;
121
122	if (crtc->funcs->gamma_set == NULL)
123	return;
124
125	r_base = crtc->gamma_store;
126	g_base = r_base + crtc->gamma_size;
127	b_base = g_base + crtc->gamma_size;
128
129	crtc->funcs->gamma_set(crtc, r_base, g_base, b_base,
130	crtc->gamma_size, NULL);
131	}
132
133	/**
134	* drm_fb_helper_debug_enter - implementation for &fb_ops.fb_debug_enter
135	* @info: fbdev registered by the helper
136	*/
137	int drm_fb_helper_debug_enter(struct fb_info *info)
138	{
139	struct drm_fb_helper *helper = info->par;
140	const struct drm_crtc_helper_funcs *funcs;
141	struct drm_mode_set *mode_set;
142
143	list_for_each_entry(helper, &kernel_fb_helper_list, kernel_fb_list) {
144	mutex_lock(&helper->client.modeset_mutex);
145	drm_client_for_each_modeset(mode_set, &helper->client) {
146	if (!mode_set->crtc->enabled)
147	continue;
148
149	funcs = mode_set->crtc->helper_private;
150	if (funcs->mode_set_base_atomic == NULL)
151	continue;
152
153	if (drm_drv_uses_atomic_modeset(mode_set->crtc->dev))
154	continue;
155
156	funcs->mode_set_base_atomic(mode_set->crtc,
157	mode_set->fb,
158	mode_set->x,
159	mode_set->y,
160	ENTER_ATOMIC_MODE_SET);
161	}
162	mutex_unlock(&helper->client.modeset_mutex);
163	}
164
165	return 0;
166	}
167	EXPORT_SYMBOL(drm_fb_helper_debug_enter);
168
169	/**
170	* drm_fb_helper_debug_leave - implementation for &fb_ops.fb_debug_leave
171	* @info: fbdev registered by the helper
172	*/
173	int drm_fb_helper_debug_leave(struct fb_info *info)
174	{
175	struct drm_fb_helper *helper = info->par;
176	struct drm_client_dev *client = &helper->client;
177	struct drm_device *dev = helper->dev;
178	struct drm_crtc *crtc;
179	const struct drm_crtc_helper_funcs *funcs;
180	struct drm_mode_set *mode_set;
181	struct drm_framebuffer *fb;
182
183	mutex_lock(&client->modeset_mutex);
184	drm_client_for_each_modeset(mode_set, client) {
185	crtc = mode_set->crtc;
186	if (drm_drv_uses_atomic_modeset(crtc->dev))
187	continue;
188
189	funcs = crtc->helper_private;
190	fb = crtc->primary->fb;
191
192	if (!crtc->enabled)
193	continue;
194
195	if (!fb) {
196	drm_err(dev, "no fb to restore?\n");
197	continue;
198	}
199
200	if (funcs->mode_set_base_atomic == NULL)
201	continue;
202
203	drm_fb_helper_restore_lut_atomic(mode_set->crtc);
204	funcs->mode_set_base_atomic(mode_set->crtc, fb, crtc->x,
205	crtc->y, LEAVE_ATOMIC_MODE_SET);
206	}
207	mutex_unlock(&client->modeset_mutex);
208
209	return 0;
210	}
211	EXPORT_SYMBOL(drm_fb_helper_debug_leave);
212
213	static int	115	static int
214	__drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper,	116	__drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper,
215	bool force)	117	bool force)
@@ -397,7 +299,6 @@ void drm_fb_helper_prepare(struct drm_device dev, struct drm_fb_helper helper, · 181 unmodified lines
397	if (!preferred_bpp)	299	if (!preferred_bpp)
398	preferred_bpp = 32;	300	preferred_bpp = 32;
399		301
400	INIT_LIST_HEAD(&helper->kernel_fb_list);
401	spin_lock_init(&helper->damage_lock);	302	spin_lock_init(&helper->damage_lock);
402	INIT_WORK(&helper->resume_work, drm_fb_helper_resume_worker);	303	INIT_WORK(&helper->resume_work, drm_fb_helper_resume_worker);
403	INIT_WORK(&helper->damage_work, drm_fb_helper_damage_work);	304	INIT_WORK(&helper->damage_work, drm_fb_helper_damage_work);
@@ -534,11 +435,6 @@ void drm_fb_helper_fini(struct drm_fb_helper *fb_helper) · 130 unmodified lines
534		435
535	drm_fb_helper_release_info(fb_helper);	436	drm_fb_helper_release_info(fb_helper);
536		437
537	mutex_lock(&kernel_fb_helper_lock);
538	if (!list_empty(&fb_helper->kernel_fb_list))
539	list_del(&fb_helper->kernel_fb_list);
540	mutex_unlock(&kernel_fb_helper_lock);
541
542	if (!fb_helper->client.funcs)	438	if (!fb_helper->client.funcs)
543	drm_client_release(&fb_helper->client);	439	drm_client_release(&fb_helper->client);
544	}	440	}
@@ -1766,10 +1662,6 @@ __drm_fb_helper_initial_config_and_unlock(struct drm_fb_helper *fb_helper) · 1221 unmodified lines
1766	drm_info(dev, "fb%d: %s frame buffer device\n",	1662	drm_info(dev, "fb%d: %s frame buffer device\n",
1767	info->node, info->fix.id);	1663	info->node, info->fix.id);
1768		1664
1769	mutex_lock(&kernel_fb_helper_lock);
1770	list_add(&fb_helper->kernel_fb_list, &kernel_fb_helper_list);
1771	mutex_unlock(&kernel_fb_helper_lock);
1772
1773	return 0;	1665	return 0;
1774		1666
1775	err_drm_fb_helper_release_info:	1667	err_drm_fb_helper_release_info:

drivers/gpu/drm/drm_gem.c+155−49

@@ -29,6 +29,9 @@ · 28 unmodified lines
29	#include <linux/export.h>	29	#include <linux/export.h>
30	#include <linux/file.h>	30	#include <linux/file.h>
31	#include <linux/fs.h>	31	#include <linux/fs.h>
		32	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		33	#include <linux/fs_context.h>
		34	#endif
32	#include <linux/iosys-map.h>	35	#include <linux/iosys-map.h>
33	#include <linux/mem_encrypt.h>	36	#include <linux/mem_encrypt.h>
34	#include <linux/mm.h>	37	#include <linux/mm.h>
@@ -36,6 +39,7 @@ · 1 unmodified line
36	#include <linux/module.h>	39	#include <linux/module.h>
37	#include <linux/pagemap.h>	40	#include <linux/pagemap.h>
38	#include <linux/pagevec.h>	41	#include <linux/pagevec.h>
		42	#include <linux/sched/mm.h>
39	#include <linux/shmem_fs.h>	43	#include <linux/shmem_fs.h>
40	#include <linux/slab.h>	44	#include <linux/slab.h>
41	#include <linux/string_helpers.h>	45	#include <linux/string_helpers.h>
@@ -81,6 +85,60 @@ · 39 unmodified lines
81	* up at a later date, and as our interface with shmfs for memory allocation.	85	* up at a later date, and as our interface with shmfs for memory allocation.
82	*/	86	*/
83		87
		88	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		89	static void drm_gem_huge_mnt_free(struct drm_device dev, void data)
		90	{
		91	kern_unmount(dev->huge_mnt);
		92	}
		93
		94	/**
		95	* drm_gem_huge_mnt_create - Create, mount and use a huge tmpfs mountpoint
		96	* @dev: DRM device that will use the huge tmpfs mountpoint
		97	* @value: huge tmpfs mount option value
		98	*
		99	* This function creates and mounts a dedicated huge tmpfs mountpoint for the
		100	* lifetime of the DRM device @dev which is used at GEM object initialization
		101	* with drm_gem_object_init().
		102	*
		103	* The most common option for @value is "within_size" which only allocates huge
		104	* pages if the page will be fully within the GEM object size. "always",
		105	* "advise" and "never" are supported too but the latter would just create a
		106	* mountpoint similar to the default one (`shm_mnt`). See shmemfs and
		107	* Transparent Hugepage for more information.
		108	*
		109	* Returns:
		110	* 0 on success or a negative error code on failure.
		111	*/
		112	int drm_gem_huge_mnt_create(struct drm_device dev, const char value)
		113	{
		114	struct file_system_type *type;
		115	struct fs_context *fc;
		116	int ret;
		117
		118	if (unlikely(drm_gem_get_huge_mnt(dev)))
		119	return 0;
		120
		121	type = get_fs_type("tmpfs");
		122	if (unlikely(!type))
		123	return -EOPNOTSUPP;
		124	fc = fs_context_for_mount(type, SB_KERNMOUNT);
		125	if (IS_ERR(fc))
		126	return PTR_ERR(fc);
		127	ret = vfs_parse_fs_string(fc, "source", "tmpfs");
		128	if (unlikely(ret))
		129	return -ENOPARAM;
		130	ret = vfs_parse_fs_string(fc, "huge", value);
		131	if (unlikely(ret))
		132	return -ENOPARAM;
		133
		134	dev->huge_mnt = fc_mount_longterm(fc);
		135	put_fs_context(fc);
		136
		137	return drmm_add_action_or_reset(dev, drm_gem_huge_mnt_free, NULL);
		138	}
		139	EXPORT_SYMBOL_GPL(drm_gem_huge_mnt_create);
		140	#endif
		141
84	static void	142	static void
85	drm_gem_init_release(struct drm_device dev, void ptr)	143	drm_gem_init_release(struct drm_device dev, void ptr)
86	{	144	{
@@ -113,29 +171,28 @@ drm_gem_init(struct drm_device *dev) · 26 unmodified lines
113	}	171	}
114		172
115	/**	173	/**
116	* drm_gem_object_init_with_mnt - initialize an allocated shmem-backed GEM	174	* drm_gem_object_init - initialize an allocated shmem-backed GEM object
117	* object in a given shmfs mountpoint
118	*	175	*
119	* @dev: drm_device the object should be initialized for	176	* @dev: drm_device the object should be initialized for
120	* @obj: drm_gem_object to initialize	177	* @obj: drm_gem_object to initialize
121	* @size: object size	178	* @size: object size
122	* @gemfs: tmpfs mount where the GEM object will be created. If NULL, use
123	* the usual tmpfs mountpoint (`shm_mnt`).
124	*	179	*
125	* Initialize an already allocated GEM object of the specified size with	180	* Initialize an already allocated GEM object of the specified size with
126	* shmfs backing store.	181	* shmfs backing store. A huge mountpoint can be used by calling
		182	* drm_gem_huge_mnt_create() beforehand.
127	*/	183	*/
128	int drm_gem_object_init_with_mnt(struct drm_device *dev,	184	int drm_gem_object_init(struct drm_device dev, struct drm_gem_object obj,
129	struct drm_gem_object *obj, size_t size,	185	size_t size)
130	struct vfsmount *gemfs)
131	{	186	{
		187	struct vfsmount *huge_mnt;
132	struct file *filp;	188	struct file *filp;
133		189
134	drm_gem_private_object_init(dev, obj, size);	190	drm_gem_private_object_init(dev, obj, size);
135		191
136	if (gemfs)	192	huge_mnt = drm_gem_get_huge_mnt(dev);
137	filp = shmem_file_setup_with_mnt(gemfs, "drm mm object", size,	193	if (huge_mnt)
138	VM_NORESERVE);	194	filp = shmem_file_setup_with_mnt(huge_mnt, "drm mm object",
		195	size, VM_NORESERVE);
139	else	196	else
140	filp = shmem_file_setup("drm mm object", size, VM_NORESERVE);	197	filp = shmem_file_setup("drm mm object", size, VM_NORESERVE);
141		198
@@ -146,22 +203,6 @@ int drm_gem_object_init_with_mnt(struct drm_device *dev, · 4 unmodified lines
146		203
147	return 0;	204	return 0;
148	}	205	}
149	EXPORT_SYMBOL(drm_gem_object_init_with_mnt);
150
151	/**
152	* drm_gem_object_init - initialize an allocated shmem-backed GEM object
153	* @dev: drm_device the object should be initialized for
154	* @obj: drm_gem_object to initialize
155	* @size: object size
156	*
157	* Initialize an already allocated GEM object of the specified size with
158	* shmfs backing store.
159	*/
160	int drm_gem_object_init(struct drm_device dev, struct drm_gem_object obj,
161	size_t size)
162	{
163	return drm_gem_object_init_with_mnt(dev, obj, size, NULL);
164	}
165	EXPORT_SYMBOL(drm_gem_object_init);	206	EXPORT_SYMBOL(drm_gem_object_init);
166		207
167	/**	208	/**
@@ -1181,36 +1222,27 @@ err_drm_gem_object_put: · 1013 unmodified lines
1181	}	1222	}
1182	EXPORT_SYMBOL(drm_gem_mmap_obj);	1223	EXPORT_SYMBOL(drm_gem_mmap_obj);
1183		1224
1184	/**	1225	/*
1185	* drm_gem_mmap - memory map routine for GEM objects	1226	* Look up a GEM object in offset space based on the exact start address. The
1186	* @filp: DRM file pointer	1227	* caller must be granted access to the object. Returns a GEM object on success
1187	* @vma: VMA for the area to be mapped	1228	* or a negative error code on failure. The returned GEM object needs to be
1188	*	1229	* released with drm_gem_object_put().
1189	* If a driver supports GEM object mapping, mmap calls on the DRM file
1190	* descriptor will end up here.
1191	*
1192	* Look up the GEM object based on the offset passed in (vma->vm_pgoff will
1193	* contain the fake offset we created when the GTT map ioctl was called on
1194	* the object) and map it with a call to drm_gem_mmap_obj().
1195	*
1196	* If the caller is not granted access to the buffer object, the mmap will fail
1197	* with EACCES. Please see the vma manager for more information.
1198	*/	1230	*/
1199	int drm_gem_mmap(struct file filp, struct vm_area_struct vma)	1231	static struct drm_gem_object *
		1232	drm_gem_object_lookup_at_offset(struct file *filp, unsigned long start,
		1233	unsigned long pages)
1200	{	1234	{
1201	struct drm_file *priv = filp->private_data;	1235	struct drm_file *priv = filp->private_data;
1202	struct drm_device *dev = priv->minor->dev;	1236	struct drm_device *dev = priv->minor->dev;
1203	struct drm_gem_object *obj = NULL;	1237	struct drm_gem_object *obj = NULL;
1204	struct drm_vma_offset_node *node;	1238	struct drm_vma_offset_node *node;
1205	int ret;
1206		1239
1207	if (drm_dev_is_unplugged(dev))	1240	if (drm_dev_is_unplugged(dev))
1208	return -ENODEV;	1241	return ERR_PTR(-ENODEV);
1209		1242
1210	drm_vma_offset_lock_lookup(dev->vma_offset_manager);	1243	drm_vma_offset_lock_lookup(dev->vma_offset_manager);
1211	node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,	1244	node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
1212	vma->vm_pgoff,	1245	start, pages);
1213	vma_pages(vma));
1214	if (likely(node)) {	1246	if (likely(node)) {
1215	obj = container_of(node, struct drm_gem_object, vma_node);	1247	obj = container_of(node, struct drm_gem_object, vma_node);
1216	/*	1248	/*
@@ -1229,14 +1261,88 @@ int drm_gem_mmap(struct file filp, struct vm_area_struct vma) · 12 unmodified lines
1229	drm_vma_offset_unlock_lookup(dev->vma_offset_manager);	1261	drm_vma_offset_unlock_lookup(dev->vma_offset_manager);
1230		1262
1231	if (!obj)	1263	if (!obj)
1232	return -EINVAL;	1264	return ERR_PTR(-EINVAL);
1233		1265
1234	if (!drm_vma_node_is_allowed(node, priv)) {	1266	if (!drm_vma_node_is_allowed(node, priv)) {
1235	drm_gem_object_put(obj);	1267	drm_gem_object_put(obj);
1236	return -EACCES;	1268	return ERR_PTR(-EACCES);
1237	}	1269	}
1238		1270
1239	ret = drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT,	1271	return obj;
		1272	}
		1273
		1274	#ifdef CONFIG_MMU
		1275	/**
		1276	* drm_gem_get_unmapped_area - get memory mapping region routine for GEM objects
		1277	* @filp: DRM file pointer
		1278	* @uaddr: User address hint
		1279	* @len: Mapping length
		1280	* @pgoff: Offset (in pages)
		1281	* @flags: Mapping flags
		1282	*
		1283	* If a driver supports GEM object mapping, before ending up in drm_gem_mmap(),
		1284	* mmap calls on the DRM file descriptor will first try to find a free linear
		1285	* address space large enough for a mapping. Since GEM objects are backed by
		1286	* shmem buffers, this should preferably be handled by the shmem virtual memory
		1287	* filesystem which can appropriately align addresses to huge page sizes when
		1288	* needed.
		1289	*
		1290	* Look up the GEM object based on the offset passed in (vma->vm_pgoff will
		1291	* contain the fake offset we created) and call shmem_get_unmapped_area() with
		1292	* the right file pointer.
		1293	*
		1294	* If a GEM object is not available at the given offset or if the caller is not
		1295	* granted access to it, fall back to mm_get_unmapped_area().
		1296	*/
		1297	unsigned long drm_gem_get_unmapped_area(struct file *filp, unsigned long uaddr,
		1298	unsigned long len, unsigned long pgoff,
		1299	unsigned long flags)
		1300	{
		1301	struct drm_gem_object *obj;
		1302	unsigned long ret;
		1303
		1304	obj = drm_gem_object_lookup_at_offset(filp, pgoff, len >> PAGE_SHIFT);
		1305	if (IS_ERR(obj) \|\| !obj->filp \|\| !obj->filp->f_op->get_unmapped_area)
		1306	return mm_get_unmapped_area(filp, uaddr, len, 0,
		1307	flags);
		1308
		1309	ret = obj->filp->f_op->get_unmapped_area(obj->filp, uaddr, len, 0,
		1310	flags);
		1311
		1312	drm_gem_object_put(obj);
		1313
		1314	return ret;
		1315	}
		1316	EXPORT_SYMBOL_GPL(drm_gem_get_unmapped_area);
		1317	#endif
		1318
		1319	/**
		1320	* drm_gem_mmap - memory map routine for GEM objects
		1321	* @filp: DRM file pointer
		1322	* @vma: VMA for the area to be mapped
		1323	*
		1324	* If a driver supports GEM object mapping, mmap calls on the DRM file
		1325	* descriptor will end up here.
		1326	*
		1327	* Look up the GEM object based on the offset passed in (vma->vm_pgoff will
		1328	* contain the fake offset we created) and map it with a call to
		1329	* drm_gem_mmap_obj().
		1330	*
		1331	* If the caller is not granted access to the buffer object, the mmap will fail
		1332	* with EACCES. Please see the vma manager for more information.
		1333	*/
		1334	int drm_gem_mmap(struct file filp, struct vm_area_struct vma)
		1335	{
		1336	struct drm_gem_object *obj;
		1337	int ret;
		1338
		1339	obj = drm_gem_object_lookup_at_offset(filp, vma->vm_pgoff,
		1340	vma_pages(vma));
		1341	if (IS_ERR(obj))
		1342	return PTR_ERR(obj);
		1343
		1344	ret = drm_gem_mmap_obj(obj,
		1345	drm_vma_node_size(&obj->vma_node) << PAGE_SHIFT,
1240	vma);	1346	vma);
1241		1347
1242	drm_gem_object_put(obj);	1348	drm_gem_object_put(obj);

drivers/gpu/drm/drm_gem_shmem_helper.c+41−36

 };
 static int __drm_gem_shmem_init(struct drm_device *dev, struct drm_gem_shmem_object *shmem,
-				size_t size, bool private, struct vfsmount *gemfs)
+				size_t size, bool private)
 {
 	struct drm_gem_object *obj = &shmem->base;
 	int ret = 0;
 		drm_gem_private_object_init(dev, obj, size);
 		shmem->map_wc = false; /* dma-buf mappings use always writecombine */
 	} else {
-		ret = drm_gem_object_init_with_mnt(dev, obj, size, gemfs);
+		ret = drm_gem_object_init(dev, obj, size);
 	}
 	if (ret) {
 		drm_gem_private_object_fini(obj);
  */
 int drm_gem_shmem_init(struct drm_device *dev, struct drm_gem_shmem_object *shmem, size_t size)
 {
-	return __drm_gem_shmem_init(dev, shmem, size, false, NULL);
+	return __drm_gem_shmem_init(dev, shmem, size, false);
 }
 EXPORT_SYMBOL_GPL(drm_gem_shmem_init);
 static struct drm_gem_shmem_object *
-__drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private,
+__drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private)
-		       struct vfsmount *gemfs)
 {
 	struct drm_gem_shmem_object *shmem;
 	struct drm_gem_object *obj;
 		obj = &shmem->base;
 	}
-	ret = __drm_gem_shmem_init(dev, shmem, size, private, gemfs);
+	ret = __drm_gem_shmem_init(dev, shmem, size, private);
 	if (ret) {
 		kfree(obj);
 		return ERR_PTR(ret);
  */
 struct drm_gem_shmem_object *drm_gem_shmem_create(struct drm_device *dev, size_t size)
 {
-	return __drm_gem_shmem_create(dev, size, false, NULL);
+	return __drm_gem_shmem_create(dev, size, false);
 }
 EXPORT_SYMBOL_GPL(drm_gem_shmem_create);
-/**
- * drm_gem_shmem_create_with_mnt - Allocate an object with the given size in a
- * given mountpoint
- * @dev: DRM device
- * @size: Size of the object to allocate
- * @gemfs: tmpfs mount where the GEM object will be created
- *
- * This function creates a shmem GEM object in a given tmpfs mountpoint.
- *
- * Returns:
- * A struct drm_gem_shmem_object * on success or an ERR_PTR()-encoded negative
- * error code on failure.
- */
-struct drm_gem_shmem_object *drm_gem_shmem_create_with_mnt(struct drm_device *dev,
-							   size_t size,
-							   struct vfsmount *gemfs)
-{
-	return __drm_gem_shmem_create(dev, size, false, gemfs);
-}
-EXPORT_SYMBOL_GPL(drm_gem_shmem_create_with_mnt);
 /**
  * drm_gem_shmem_release - Release resources associated with a shmem GEM object.
  * @shmem: shmem GEM object
 }
 EXPORT_SYMBOL_GPL(drm_gem_shmem_dumb_create);
+static bool drm_gem_shmem_try_map_pmd(struct vm_fault *vmf, unsigned long addr,
+				      struct page *page)
+{
+#ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP
+	unsigned long pfn = page_to_pfn(page);
+	unsigned long paddr = pfn << PAGE_SHIFT;
+	bool aligned = (addr & ~PMD_MASK) == (paddr & ~PMD_MASK);
+	if (aligned &&
+	    pmd_none(*vmf->pmd) &&
+	    folio_test_pmd_mappable(page_folio(page))) {
+		pfn &= PMD_MASK >> PAGE_SHIFT;
+		if (vmf_insert_pfn_pmd(vmf, pfn, false) == VM_FAULT_NOPAGE)
+			return true;
+	}
+#endif
+	return false;
+}
 static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf)
 {
 	struct vm_area_struct *vma = vmf->vma;
 	struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
 	loff_t num_pages = obj->size >> PAGE_SHIFT;
 	vm_fault_t ret;
-	struct page *page;
+	struct page **pages = shmem->pages;
 	pgoff_t page_offset;
+	unsigned long pfn;
-	/* We don't use vmf->pgoff since that has the fake offset */
+	/* Offset to faulty address in the VMA. */
-	page_offset = (vmf->address - vma->vm_start) >> PAGE_SHIFT;
+	page_offset = vmf->pgoff - vma->vm_pgoff;
 	dma_resv_lock(shmem->base.resv, NULL);
 	    drm_WARN_ON_ONCE(obj->dev, !shmem->pages) ||
 	    shmem->madv < 0) {
 		ret = VM_FAULT_SIGBUS;
-	} else {
+		goto out;
-		page = shmem->pages[page_offset];
+	}
-		ret = vmf_insert_pfn(vma, vmf->address, page_to_pfn(page));
+	if (drm_gem_shmem_try_map_pmd(vmf, vmf->address, pages[page_offset])) {
+		ret = VM_FAULT_NOPAGE;
+		goto out;
 	}
+	pfn = page_to_pfn(pages[page_offset]);
+	ret = vmf_insert_pfn(vma, vmf->address, pfn);
+ out:
 	dma_resv_unlock(shmem->base.resv);
 	return ret;
 	size_t size = PAGE_ALIGN(attach->dmabuf->size);
 	struct drm_gem_shmem_object *shmem;
-	shmem = __drm_gem_shmem_create(dev, size, true, NULL);
+	shmem = __drm_gem_shmem_create(dev, size, true);
 	if (IS_ERR(shmem))
 		return ERR_CAST(shmem);
 	size = PAGE_ALIGN(attach->dmabuf->size);
-	shmem = __drm_gem_shmem_create(dev, size, true, NULL);
+	shmem = __drm_gem_shmem_create(dev, size, true);
 	if (IS_ERR(shmem)) {
 		ret = PTR_ERR(shmem);
 		goto fail_detach;

drivers/gpu/drm/drm_panic.c+62−13

@@ -39,12 +39,6 @@ MODULE_AUTHOR("Jocelyn Falempe"); · 38 unmodified lines
39	MODULE_DESCRIPTION("DRM panic handler");	39	MODULE_DESCRIPTION("DRM panic handler");
40	MODULE_LICENSE("GPL");	40	MODULE_LICENSE("GPL");
41		41
42	static char drm_panic_screen[16] = CONFIG_DRM_PANIC_SCREEN;
43	module_param_string(panic_screen, drm_panic_screen, sizeof(drm_panic_screen), 0644);
44	MODULE_PARM_DESC(panic_screen,
45	"Choose what will be displayed by drm_panic, 'user' or 'kmsg' [default="
46	CONFIG_DRM_PANIC_SCREEN "]");
47
48	/**	42	/**
49	* DOC: overview	43	* DOC: overview
50	*	44	*
@@ -813,14 +807,59 @@ static void draw_panic_static_qr_code(struct drm_scanout_buffer *sb) · 762 unmodified lines
813	draw_panic_static_user(sb);	807	draw_panic_static_user(sb);
814	}	808	}
815	#else	809	#else
816	static void draw_panic_static_qr_code(struct drm_scanout_buffer *sb)	810	static void drm_panic_qr_init(void) {};
		811	static void drm_panic_qr_exit(void) {};
		812	#endif
		813
		814	enum drm_panic_type {
		815	DRM_PANIC_TYPE_KMSG,
		816	DRM_PANIC_TYPE_USER,
		817	DRM_PANIC_TYPE_QR,
		818	};
		819
		820	static enum drm_panic_type drm_panic_type = -1;
		821
		822	static const char *drm_panic_type_map[] = {
		823	[DRM_PANIC_TYPE_KMSG] = "kmsg",
		824	[DRM_PANIC_TYPE_USER] = "user",
		825	#if IS_ENABLED(CONFIG_DRM_PANIC_SCREEN_QR_CODE)
		826	[DRM_PANIC_TYPE_QR] = "qr",
		827	#endif
		828	};
		829
		830	static int drm_panic_type_set(const char val, const struct kernel_param kp)
817	{	831	{
818	draw_panic_static_user(sb);	832	unsigned int i;
		833
		834	for (i = 0; i < ARRAY_SIZE(drm_panic_type_map); i++) {
		835	if (!strcmp(val, drm_panic_type_map[i])) {
		836	drm_panic_type = i;
		837	return 0;
		838	}
		839	}
		840
		841	return -EINVAL;
819	}	842	}
820		843
821	static void drm_panic_qr_init(void) {};	844	static int drm_panic_type_get(char buffer, const struct kernel_param kp)
822	static void drm_panic_qr_exit(void) {};	845	{
		846	return scnprintf(buffer, PAGE_SIZE, "%s\n",
		847	drm_panic_type_map[drm_panic_type]);
		848	}
		849
		850	static const struct kernel_param_ops drm_panic_ops = {
		851	.set = drm_panic_type_set,
		852	.get = drm_panic_type_get,
		853	};
		854
		855	module_param_cb(panic_screen, &drm_panic_ops, NULL, 0644);
		856	MODULE_PARM_DESC(panic_screen,
		857	#if IS_ENABLED(CONFIG_DRM_PANIC_SCREEN_QR_CODE)
		858	"Choose what will be displayed by drm_panic, 'user', 'kmsg' or 'qr' [default="
		859	#else
		860	"Choose what will be displayed by drm_panic, 'user' or 'kmsg' [default="
823	#endif	861	#endif
		862	CONFIG_DRM_PANIC_SCREEN "]");
824		863
825	/*	864	/*
826	* drm_panic_is_format_supported()	865	* drm_panic_is_format_supported()
@@ -838,11 +877,19 @@ static bool drm_panic_is_format_supported(const struct drm_format_info *format) · 11 unmodified lines
838		877
839	static void draw_panic_dispatch(struct drm_scanout_buffer *sb)	878	static void draw_panic_dispatch(struct drm_scanout_buffer *sb)
840	{	879	{
841	if (!strcmp(drm_panic_screen, "kmsg")) {	880	switch (drm_panic_type) {
		881	case DRM_PANIC_TYPE_KMSG:
842	draw_panic_static_kmsg(sb);	882	draw_panic_static_kmsg(sb);
843	} else if (!strcmp(drm_panic_screen, "qr_code")) {	883	break;
		884
		885	#if IS_ENABLED(CONFIG_DRM_PANIC_SCREEN_QR_CODE)
		886	case DRM_PANIC_TYPE_QR:
844	draw_panic_static_qr_code(sb);	887	draw_panic_static_qr_code(sb);
845	} else {	888	break;
		889	#endif
		890
		891	case DRM_PANIC_TYPE_USER:
		892	default:
846	draw_panic_static_user(sb);	893	draw_panic_static_user(sb);
847	}	894	}
848	}	895	}
@@ -1025,6 +1072,8 @@ void drm_panic_unregister(struct drm_device *dev) · 176 unmodified lines
1025	*/	1072	*/
1026	void __init drm_panic_init(void)	1073	void __init drm_panic_init(void)
1027	{	1074	{
		1075	if (drm_panic_type == -1)
		1076	drm_panic_type_set(CONFIG_DRM_PANIC_SCREEN, NULL);
1028	drm_panic_qr_init();	1077	drm_panic_qr_init();
1029	}	1078	}
1030		1079

drivers/gpu/drm/drm_plane.c+2−2

@@ -1867,9 +1867,9 @@ int drm_plane_create_color_pipeline_property(struct drm_plane *plane, · 1866 unmodified lines
1867	prop = drm_property_create_enum(plane->dev, DRM_MODE_PROP_ATOMIC,	1867	prop = drm_property_create_enum(plane->dev, DRM_MODE_PROP_ATOMIC,
1868	"COLOR_PIPELINE",	1868	"COLOR_PIPELINE",
1869	all_pipelines, len);	1869	all_pipelines, len);
1870	if (IS_ERR(prop)) {	1870	if (!prop) {
1871	kfree(all_pipelines);	1871	kfree(all_pipelines);
1872	return PTR_ERR(prop);	1872	return -ENOMEM;
1873	}	1873	}
1874		1874
1875	drm_object_attach_property(&plane->base, prop, 0);	1875	drm_object_attach_property(&plane->base, prop, 0);

drivers/gpu/drm/drm_vblank.c+21−31

 	dev->num_crtcs = num_crtcs;
 	for (i = 0; i < num_crtcs; i++) {
-		struct drm_vblank_crtc *vblank = &dev->vblank[i];
+		struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, i);
 		vblank->dev = dev;
 		vblank->pipe = i;
  */
 wait_queue_head_t *drm_crtc_vblank_waitqueue(struct drm_crtc *crtc)
 {
-	return &crtc->dev->vblank[drm_crtc_index(crtc)].queue;
+	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
+	return &vblank->queue;
 }
 EXPORT_SYMBOL(drm_crtc_vblank_waitqueue);
 {
 	struct drm_device *dev = crtc->dev;
 	unsigned int pipe = crtc->index;
-	struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
 	struct timespec64 ts_etime, ts_vblank_time;
 	ktime_t stime, etime;
 	bool vbl_status;
 		return false;
 	}
-	if (drm_drv_uses_atomic_modeset(dev))
+	if (drm_drv_uses_atomic_modeset(dev)) {
+		struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
 		mode = &vblank->hwmode;
-	else
+	} else {
 		mode = &crtc->hwmode;
+	}
 	/* If mode timing undefined, just return as no-op:
 	 * Happens during initial modesetting of a crtc.
 EXPORT_SYMBOL(drm_crtc_vblank_put);
 /**
- * drm_wait_one_vblank - wait for one vblank
+ * drm_crtc_wait_one_vblank - wait for one vblank
- * @dev: DRM device
+ * @crtc: DRM crtc
- * @pipe: CRTC index
  *
- * This waits for one vblank to pass on @pipe, using the irq driver interfaces.
+ * This waits for one vblank to pass on @crtc, using the irq driver interfaces.
- * It is a failure to call this when the vblank irq for @pipe is disabled, e.g.
+ * It is a failure to call this when the vblank irq for @crtc is disabled, e.g.
  * due to lack of driver support or because the crtc is off.
  *
- * This is the legacy version of drm_crtc_wait_one_vblank().
+ * Returns: 0 on success, negative error on failures.
  */
-void drm_wait_one_vblank(struct drm_device *dev, unsigned int pipe)
+int drm_crtc_wait_one_vblank(struct drm_crtc *crtc)
 {
-	struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe);
+	struct drm_device *dev = crtc->dev;
+	int pipe = drm_crtc_index(crtc);
+	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
 	int ret;
 	u64 last;
-	if (drm_WARN_ON(dev, pipe >= dev->num_crtcs))
-		return;
 	ret = drm_vblank_get(dev, pipe);
 	if (drm_WARN(dev, ret, "vblank not available on crtc %i, ret=%i\n",
 		     pipe, ret))
-		return;
+		return ret;
 	last = drm_vblank_count(dev, pipe);
 	drm_WARN(dev, ret == 0, "vblank wait timed out on crtc %i\n", pipe);
 	drm_vblank_put(dev, pipe);
-}
-EXPORT_SYMBOL(drm_wait_one_vblank);
-/**
+	return ret ? 0 : -ETIMEDOUT;
- * drm_crtc_wait_one_vblank - wait for one vblank
- * @crtc: DRM crtc
- *
- * This waits for one vblank to pass on @crtc, using the irq driver interfaces.
- * It is a failure to call this when the vblank irq for @crtc is disabled, e.g.
- * due to lack of driver support or because the crtc is off.
- */
-void drm_crtc_wait_one_vblank(struct drm_crtc *crtc)
-{
-	drm_wait_one_vblank(crtc->dev, drm_crtc_index(crtc));
 }
 EXPORT_SYMBOL(drm_crtc_wait_one_vblank);
 	if (pipe >= dev->num_crtcs)
 		return -EINVAL;
-	vblank = &dev->vblank[pipe];
+	vblank = drm_vblank_crtc(dev, pipe);
 	/* If the counter is currently enabled and accurate, short-circuit
 	 * queries to return the cached timestamp of the last vblank.

drivers/gpu/drm/hyperv/Kconfig+14−0

@@ -0,0 +1,14 @@
	1	# SPDX-License-Identifier: GPL-2.0-only
	2	config DRM_HYPERV
	3	tristate "DRM Support for Hyper-V synthetic video device"
	4	depends on DRM && PCI && HYPERV_VMBUS
	5	select DRM_CLIENT_SELECTION
	6	select DRM_KMS_HELPER
	7	select DRM_GEM_SHMEM_HELPER
	8	help
	9	This is a KMS driver for Hyper-V synthetic video device. Choose this
	10	option if you would like to enable drm driver for Hyper-V virtual
	11	machine. Unselect Hyper-V framebuffer driver (CONFIG_FB_HYPERV) so
	12	that DRM driver is used by default.
	13
	14	If M is selected the module will be called hyperv_drm.

drivers/gpu/drm/i915/Makefile+1−2

 	gem/i915_gem_ttm_move.o \
 	gem/i915_gem_ttm_pm.o \
 	gem/i915_gem_userptr.o \
-	gem/i915_gem_wait.o \
+	gem/i915_gem_wait.o
-	gem/i915_gemfs.o
 i915-y += \
 	$(gem-y) \
 	i915_active.o \

drivers/gpu/drm/i915/gem/i915_gem_object_types.h+6−4

  */
 #define I915_BO_ALLOC_GPU_ONLY	  BIT(6)
 #define I915_BO_ALLOC_CCS_AUX	  BIT(7)
+#define I915_BO_ALLOC_NOTHP	  BIT(8)
 /*
  * Object is allowed to retain its initial data and will not be cleared on first
  * access if used along with I915_BO_ALLOC_USER. This is mainly to keep
  * preallocated framebuffer data intact while transitioning it to i915drmfb.
  */
-#define I915_BO_PREALLOC	  BIT(8)
+#define I915_BO_PREALLOC	  BIT(9)
 #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
 			     I915_BO_ALLOC_VOLATILE | \
 			     I915_BO_ALLOC_CPU_CLEAR | \
 			     I915_BO_ALLOC_PM_EARLY | \
 			     I915_BO_ALLOC_GPU_ONLY | \
 			     I915_BO_ALLOC_CCS_AUX | \
+			     I915_BO_ALLOC_NOTHP | \
 			     I915_BO_PREALLOC)
-#define I915_BO_READONLY          BIT(9)
+#define I915_BO_READONLY          BIT(10)
-#define I915_TILING_QUIRK_BIT     10 /* unknown swizzling; do not release! */
+#define I915_TILING_QUIRK_BIT     11 /* unknown swizzling; do not release! */
-#define I915_BO_PROTECTED         BIT(11)
+#define I915_BO_PROTECTED         BIT(12)
 	/**
 	 * @mem_flags - Mutable placement-related flags
 	 *

drivers/gpu/drm/i915/gem/i915_gem_shmem.c+41−17

@@ -9,14 +9,16 @@ · 8 unmodified lines
9	#include <linux/uio.h>	9	#include <linux/uio.h>
10		10
11	#include <drm/drm_cache.h>	11	#include <drm/drm_cache.h>
		12	#include <drm/drm_gem.h>
		13	#include <drm/drm_print.h>
12		14
13	#include "gem/i915_gem_region.h"	15	#include "gem/i915_gem_region.h"
14	#include "i915_drv.h"	16	#include "i915_drv.h"
15	#include "i915_gem_object.h"	17	#include "i915_gem_object.h"
16	#include "i915_gem_tiling.h"	18	#include "i915_gem_tiling.h"
17	#include "i915_gemfs.h"
18	#include "i915_scatterlist.h"	19	#include "i915_scatterlist.h"
19	#include "i915_trace.h"	20	#include "i915_trace.h"
		21	#include "i915_utils.h"
20		22
21	/*	23	/*
22	* Move folios to appropriate lru and release the batch, decrementing the	24	* Move folios to appropriate lru and release the batch, decrementing the
@@ -494,9 +496,11 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = { · 471 unmodified lines
494		496
495	static int __create_shmem(struct drm_i915_private *i915,	497	static int __create_shmem(struct drm_i915_private *i915,
496	struct drm_gem_object *obj,	498	struct drm_gem_object *obj,
497	resource_size_t size)	499	resource_size_t size,
		500	unsigned int flags)
498	{	501	{
499	unsigned long flags = VM_NORESERVE;	502	unsigned long shmem_flags = VM_NORESERVE;
		503	struct vfsmount *huge_mnt;
500	struct file *filp;	504	struct file *filp;
501		505
502	drm_gem_private_object_init(&i915->drm, obj, size);	506	drm_gem_private_object_init(&i915->drm, obj, size);
@@ -515,11 +519,12 @@ static int __create_shmem(struct drm_i915_private *i915, · 12 unmodified lines
515	if (BITS_PER_LONG == 64 && size > MAX_LFS_FILESIZE)	519	if (BITS_PER_LONG == 64 && size > MAX_LFS_FILESIZE)
516	return -E2BIG;	520	return -E2BIG;
517		521
518	if (i915->mm.gemfs)	522	huge_mnt = drm_gem_get_huge_mnt(&i915->drm);
519	filp = shmem_file_setup_with_mnt(i915->mm.gemfs, "i915", size,	523	if (!(flags & I915_BO_ALLOC_NOTHP) && huge_mnt)
520	flags);	524	filp = shmem_file_setup_with_mnt(huge_mnt, "i915", size,
		525	shmem_flags);
521	else	526	else
522	filp = shmem_file_setup("i915", size, flags);	527	filp = shmem_file_setup("i915", size, shmem_flags);
523	if (IS_ERR(filp))	528	if (IS_ERR(filp))
524	return PTR_ERR(filp);	529	return PTR_ERR(filp);
525		530
@@ -548,7 +553,7 @@ static int shmem_object_init(struct intel_memory_region *mem, · 22 unmodified lines
548	gfp_t mask;	553	gfp_t mask;
549	int ret;	554	int ret;
550		555
551	ret = __create_shmem(i915, &obj->base, size);	556	ret = __create_shmem(i915, &obj->base, size, flags);
552	if (ret)	557	if (ret)
553	return ret;	558	return ret;
554		559
@@ -644,21 +649,40 @@ fail: · 89 unmodified lines
644		649
645	static int init_shmem(struct intel_memory_region *mem)	650	static int init_shmem(struct intel_memory_region *mem)
646	{	651	{
647	i915_gemfs_init(mem->i915);	652	struct drm_i915_private *i915 = mem->i915;
648	intel_memory_region_set_name(mem, "system");
649		653
650	return 0; /* We have fallback to the kernel mnt if gemfs init failed. */	654	/*
651	}	655	* By creating our own shmemfs mountpoint, we can pass in
		656	* mount flags that better match our usecase.
		657	*
		658	* One example, although it is probably better with a per-file
		659	* control, is selecting huge page allocations ("huge=within_size").
		660	* However, we only do so on platforms which benefit from it, or to
		661	* offset the overhead of iommu lookups, where with latter it is a net
		662	* win even on platforms which would otherwise see some performance
		663	* regressions such a slow reads issue on Broadwell and Skylake.
		664	*/
652		665
653	static int release_shmem(struct intel_memory_region *mem)	666	if (GRAPHICS_VER(i915) < 11 && !i915_vtd_active(i915))
654	{	667	goto no_thp;
655	i915_gemfs_fini(mem->i915);	668
656	return 0;	669	drm_gem_huge_mnt_create(&i915->drm, "within_size");
		670	if (drm_gem_get_huge_mnt(&i915->drm))
		671	drm_info(&i915->drm, "Using Transparent Hugepages\n");
		672	else
		673	drm_notice(&i915->drm,
		674	"Transparent Hugepage support is recommended for optimal performance%s\n",
		675	GRAPHICS_VER(i915) >= 11 ? " on this platform!" :
		676	" when IOMMU is enabled!");
		677
		678	no_thp:
		679	intel_memory_region_set_name(mem, "system");
		680
		681	return 0; /* We have fallback to the kernel mnt if huge mnt failed. */
657	}	682	}
658		683
659	static const struct intel_memory_region_ops shmem_region_ops = {	684	static const struct intel_memory_region_ops shmem_region_ops = {
660	.init = init_shmem,	685	.init = init_shmem,
661	.release = release_shmem,
662	.init_object = shmem_object_init,	686	.init_object = shmem_object_init,
663	};	687	};
664		688

drivers/gpu/drm/i915/gem/i915_gemfs.c+0−71

@@ -1,71 +0,0 @@
1	// SPDX-License-Identifier: MIT
2	/*
3	* Copyright © 2017 Intel Corporation
4	*/
5
6	#include <linux/fs.h>
7	#include <linux/mount.h>
8	#include <linux/fs_context.h>
9
10	#include <drm/drm_print.h>
11
12	#include "i915_drv.h"
13	#include "i915_gemfs.h"
14	#include "i915_utils.h"
15
16	void i915_gemfs_init(struct drm_i915_private *i915)
17	{
18	struct file_system_type *type;
19	struct fs_context *fc;
20	struct vfsmount *gemfs;
21	int ret;
22
23	/*
24	* By creating our own shmemfs mountpoint, we can pass in
25	* mount flags that better match our usecase.
26	*
27	* One example, although it is probably better with a per-file
28	* control, is selecting huge page allocations ("huge=within_size").
29	* However, we only do so on platforms which benefit from it, or to
30	* offset the overhead of iommu lookups, where with latter it is a net
31	* win even on platforms which would otherwise see some performance
32	* regressions such a slow reads issue on Broadwell and Skylake.
33	*/
34
35	if (GRAPHICS_VER(i915) < 11 && !i915_vtd_active(i915))
36	return;
37
38	if (!IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE))
39	goto err;
40
41	type = get_fs_type("tmpfs");
42	if (!type)
43	goto err;
44
45	fc = fs_context_for_mount(type, SB_KERNMOUNT);
46	if (IS_ERR(fc))
47	goto err;
48	ret = vfs_parse_fs_string(fc, "source", "tmpfs");
49	if (!ret)
50	ret = vfs_parse_fs_string(fc, "huge", "within_size");
51	if (!ret)
52	gemfs = fc_mount_longterm(fc);
53	put_fs_context(fc);
54	if (ret)
55	goto err;
56
57	i915->mm.gemfs = gemfs;
58	drm_info(&i915->drm, "Using Transparent Hugepages\n");
59	return;
60
61	err:
62	drm_notice(&i915->drm,
63	"Transparent Hugepage support is recommended for optimal performance%s\n",
64	GRAPHICS_VER(i915) >= 11 ? " on this platform!" :
65	" when IOMMU is enabled!");
66	}
67
68	void i915_gemfs_fini(struct drm_i915_private *i915)
69	{
70	kern_unmount(i915->mm.gemfs);
71	}

drivers/gpu/drm/i915/gem/i915_gemfs.h+0−14

@@ -1,14 +0,0 @@
1	/* SPDX-License-Identifier: MIT */
2	/*
3	* Copyright © 2017 Intel Corporation
4	*/
5
6	#ifndef __I915_GEMFS_H__
7	#define __I915_GEMFS_H__
8
9	struct drm_i915_private;
10
11	void i915_gemfs_init(struct drm_i915_private *i915);
12	void i915_gemfs_fini(struct drm_i915_private *i915);
13
14	#endif

drivers/gpu/drm/i915/gem/selftests/huge_pages.c+3−12

 static inline bool igt_can_allocate_thp(struct drm_i915_private *i915)
 {
-	return i915->mm.gemfs && has_transparent_hugepage();
+	return !!drm_gem_get_huge_mnt(&i915->drm);
 }
 static struct drm_i915_gem_object *
 	struct drm_i915_private *i915 = arg;
 	struct i915_address_space *vm;
 	struct i915_gem_context *ctx;
-	struct vfsmount *gemfs = i915->mm.gemfs;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 	struct file *file;
 	}
 	vm = i915_gem_context_get_eb_vm(ctx);
-	/*
+	obj = i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_SMEM],
-	 * Make sure that we don't burst into a ball of flames upon falling back
+					    PAGE_SIZE, 0, I915_BO_ALLOC_NOTHP);
-	 * to tmpfs, which we rely on if on the off-chance we encounter a failure
-	 * when setting up gemfs.
-	 */
-	i915->mm.gemfs = NULL;
-	obj = i915_gem_object_create_shmem(i915, PAGE_SIZE);
 	if (IS_ERR(obj)) {
 		err = PTR_ERR(obj);
 		goto out_restore;
 out_put:
 	i915_gem_object_put(obj);
 out_restore:
-	i915->mm.gemfs = gemfs;
 	i915_vm_put(vm);
 out:

drivers/gpu/drm/i915/i915_drv.h+0−5

 	 */
 	atomic_t free_count;
-	/**
-	 * tmpfs instance used for shmem backed objects
-	 */
-	struct vfsmount *gemfs;
 	struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 	struct notifier_block oom_notifier;

drivers/gpu/drm/nouveau/dispnv04/crtc.c+4−20

 static int
 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
 			   struct drm_framebuffer *passed_fb,
-			   int x, int y, bool atomic)
+			   int x, int y)
 {
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	NV_DEBUG(drm, "index %d\n", nv_crtc->index);
 	/* no fb bound */
-	if (!atomic && !crtc->primary->fb) {
+	if (!crtc->primary->fb) {
 		NV_DEBUG(drm, "No FB bound\n");
 		return 0;
 	}
-	/* If atomic, we want to switch to the fb we were passed, so
+	drm_fb = crtc->primary->fb;
-	 * now we update pointers to do that.
-	 */
-	if (atomic) {
-		drm_fb = passed_fb;
-	} else {
-		drm_fb = crtc->primary->fb;
-	}
 	nvbo = nouveau_gem_object(drm_fb->obj[0]);
 	nv_crtc->fb.offset = nvbo->offset;
 	int ret = nv_crtc_swap_fbs(crtc, old_fb);
 	if (ret)
 		return ret;
-	return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
+	return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y);
-}
-static int
-nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
-			       struct drm_framebuffer *fb,
-			       int x, int y, enum mode_set_atomic state)
-{
-	return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
 }
 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
 	.commit = nv_crtc_commit,
 	.mode_set = nv_crtc_mode_set,
 	.mode_set_base = nv04_crtc_mode_set_base,
-	.mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
 	.disable = nv_crtc_disable,
 	.get_scanout_position = nouveau_display_scanoutpos,
 };

drivers/gpu/drm/panel/panel-edp.c+3−0

  */
 static const struct edp_panel_entry edp_panels[] = {
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x04a4, &delay_200_500_e50, "B122UAN01.0"),
+	EDP_PANEL_ENTRY('A', 'U', 'O', 0x0ba4, &delay_200_500_e50, "B140QAX01.H"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x105c, &delay_200_500_e50, "B116XTN01.0"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x1062, &delay_200_500_e50, "B120XAN01.0"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x125c, &delay_200_500_e50, "Unknown"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x615c, &delay_200_500_e50, "B116XAN06.1"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x635c, &delay_200_500_e50, "B116XAN06.3"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x639c, &delay_200_500_e50, "B140HAK02.7"),
+	EDP_PANEL_ENTRY('A', 'U', 'O', 0x643d, &delay_200_500_e50, "B140HAN06.4"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x723c, &delay_200_500_e50, "B140XTN07.2"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x73aa, &delay_200_500_e50, "B116XTN02.3"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x8594, &delay_200_500_e50, "B133UAN01.0"),
 	EDP_PANEL_ENTRY('C', 'S', 'W', 0x1462, &delay_200_500_e50, "MNE007QS5-2"),
 	EDP_PANEL_ENTRY('C', 'S', 'W', 0x1468, &delay_200_500_e50, "MNE007QB2-2"),
 	EDP_PANEL_ENTRY('C', 'S', 'W', 0x146e, &delay_80_500_e50_d50, "MNE007QB3-1"),
+	EDP_PANEL_ENTRY('C', 'S', 'W', 0x147c, &delay_200_500_e50_d100, "MNE007QB3-1"),
 	EDP_PANEL_ENTRY('C', 'S', 'W', 0x1519, &delay_200_500_e80_d50, "MNF601BS1-3"),
 	EDP_PANEL_ENTRY('E', 'T', 'C', 0x0000, &delay_50_500_e200_d200_po2e335, "LP079QX1-SP0V"),

drivers/gpu/drm/panfrost/panfrost_device.c+3−0

 #include "panfrost_device.h"
 #include "panfrost_devfreq.h"
 #include "panfrost_features.h"
+#include "panfrost_gem.h"
 #include "panfrost_issues.h"
 #include "panfrost_gpu.h"
 #include "panfrost_job.h"
 	if (err)
 		goto out_job;
+	panfrost_gem_init(pfdev);
 	return 0;
 out_job:
 	panfrost_jm_fini(pfdev);

drivers/gpu/drm/panfrost/panfrost_device.h+1−0

@@ -79,6 +79,7 @@ struct panfrost_features { · 78 unmodified lines
79	u32 thread_max_workgroup_sz;	79	u32 thread_max_workgroup_sz;
80	u32 thread_max_barrier_sz;	80	u32 thread_max_barrier_sz;
81	u32 coherency_features;	81	u32 coherency_features;
		82	u32 selected_coherency;
82	u32 afbc_features;	83	u32 afbc_features;
83	u32 texture_features[4];	84	u32 texture_features[4];
84	u32 js_features[16];	85	u32 js_features[16];

drivers/gpu/drm/panfrost/panfrost_drv.c+104−3

@@ -95,6 +95,7 @@ static int panfrost_ioctl_get_param(struct drm_device ddev, void data, struct · 94 unmodified lines
95	PANFROST_FEATURE_ARRAY(JS_FEATURES, js_features, 15);	95	PANFROST_FEATURE_ARRAY(JS_FEATURES, js_features, 15);
96	PANFROST_FEATURE(NR_CORE_GROUPS, nr_core_groups);	96	PANFROST_FEATURE(NR_CORE_GROUPS, nr_core_groups);
97	PANFROST_FEATURE(THREAD_TLS_ALLOC, thread_tls_alloc);	97	PANFROST_FEATURE(THREAD_TLS_ALLOC, thread_tls_alloc);
		98	PANFROST_FEATURE(SELECTED_COHERENCY, selected_coherency);
98		99
99	case DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP:	100	case DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP:
100	ret = panfrost_ioctl_query_timestamp(pfdev, &param->value);	101	ret = panfrost_ioctl_query_timestamp(pfdev, &param->value);
@@ -125,6 +126,10 @@ static int panfrost_ioctl_get_param(struct drm_device ddev, void data, struct · 24 unmodified lines
125	return 0;	126	return 0;
126	}	127	}
127		128
		129	#define PANFROST_BO_FLAGS (PANFROST_BO_NOEXEC \| \
		130	PANFROST_BO_HEAP \| \
		131	PANFROST_BO_WB_MMAP)
		132
128	static int panfrost_ioctl_create_bo(struct drm_device dev, void data,	133	static int panfrost_ioctl_create_bo(struct drm_device dev, void data,
129	struct drm_file *file)	134	struct drm_file *file)
130	{	135	{
@@ -134,8 +139,7 @@ static int panfrost_ioctl_create_bo(struct drm_device dev, void data, · 3 unmodified lines
134	struct panfrost_gem_mapping *mapping;	139	struct panfrost_gem_mapping *mapping;
135	int ret;	140	int ret;
136		141
137	if (!args->size \|\| args->pad \|\|	142	if (!args->size \|\| args->pad \|\| (args->flags & ~PANFROST_BO_FLAGS))
138	(args->flags & ~(PANFROST_BO_NOEXEC \| PANFROST_BO_HEAP)))
139	return -EINVAL;	143	return -EINVAL;
140		144
141	/* Heaps should never be executable */	145	/* Heaps should never be executable */
@@ -579,6 +583,91 @@ static int panfrost_ioctl_jm_ctx_destroy(struct drm_device dev, void data, · 437 unmodified lines
579	return panfrost_jm_ctx_destroy(file, args->handle);	583	return panfrost_jm_ctx_destroy(file, args->handle);
580	}	584	}
581		585
		586	static int panfrost_ioctl_sync_bo(struct drm_device ddev, void data,
		587	struct drm_file *file)
		588	{
		589	struct drm_panfrost_sync_bo *args = data;
		590	struct drm_panfrost_bo_sync_op *ops;
		591	struct drm_gem_object *obj;
		592	int ret;
		593	u32 i;
		594
		595	if (args->pad)
		596	return -EINVAL;
		597
		598	if (!args->op_count)
		599	return 0;
		600
		601	ops = kvmalloc_array(args->op_count, sizeof(*ops), GFP_KERNEL);
		602	if (!ops) {
		603	DRM_DEBUG("Failed to allocate incoming BO sync ops array\n");
		604	return -ENOMEM;
		605	}
		606
		607	if (copy_from_user(ops, (void __user *)(uintptr_t)args->ops,
		608	args->op_count * sizeof(*ops))) {
		609	DRM_DEBUG("Failed to copy in BO sync ops\n");
		610	ret = -EFAULT;
		611	goto err_ops;
		612	}
		613
		614	for (i = 0; i < args->op_count; i++) {
		615	obj = drm_gem_object_lookup(file, ops[i].handle);
		616	if (!obj) {
		617	ret = -ENOENT;
		618	goto err_ops;
		619	}
		620
		621	ret = panfrost_gem_sync(obj, ops[i].type,
		622	ops[i].offset, ops[i].size);
		623
		624	drm_gem_object_put(obj);
		625
		626	if (ret)
		627	goto err_ops;
		628	}
		629
		630	err_ops:
		631	kvfree(ops);
		632
		633	return ret;
		634	}
		635
		636	static int panfrost_ioctl_query_bo_info(struct drm_device dev, void data,
		637	struct drm_file *file_priv)
		638	{
		639	struct drm_panfrost_query_bo_info *args = data;
		640	struct drm_gem_object *gem_obj;
		641	struct panfrost_gem_object *bo;
		642
		643	gem_obj = drm_gem_object_lookup(file_priv, args->handle);
		644	if (!gem_obj) {
		645	DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
		646	return -ENOENT;
		647	}
		648
		649	bo = to_panfrost_bo(gem_obj);
		650	args->pad = 0;
		651	args->create_flags = 0;
		652	args->extra_flags = 0;
		653
		654	if (drm_gem_is_imported(gem_obj)) {
		655	args->extra_flags \|= DRM_PANFROST_BO_IS_IMPORTED;
		656	} else {
		657	if (bo->noexec)
		658	args->create_flags \|= PANFROST_BO_NOEXEC;
		659
		660	if (bo->is_heap)
		661	args->create_flags \|= PANFROST_BO_HEAP;
		662
		663	if (!bo->base.map_wc)
		664	args->create_flags \|= PANFROST_BO_WB_MMAP;
		665	}
		666
		667	drm_gem_object_put(gem_obj);
		668	return 0;
		669	}
		670
582	int panfrost_unstable_ioctl_check(void)	671	int panfrost_unstable_ioctl_check(void)
583	{	672	{
584	if (!unstable_ioctls)	673	if (!unstable_ioctls)
@@ -648,6 +737,8 @@ static const struct drm_ioctl_desc panfrost_drm_driver_ioctls[] = { · 63 unmodified lines
648	PANFROST_IOCTL(SET_LABEL_BO, set_label_bo, DRM_RENDER_ALLOW),	737	PANFROST_IOCTL(SET_LABEL_BO, set_label_bo, DRM_RENDER_ALLOW),
649	PANFROST_IOCTL(JM_CTX_CREATE, jm_ctx_create, DRM_RENDER_ALLOW),	738	PANFROST_IOCTL(JM_CTX_CREATE, jm_ctx_create, DRM_RENDER_ALLOW),
650	PANFROST_IOCTL(JM_CTX_DESTROY, jm_ctx_destroy, DRM_RENDER_ALLOW),	739	PANFROST_IOCTL(JM_CTX_DESTROY, jm_ctx_destroy, DRM_RENDER_ALLOW),
		740	PANFROST_IOCTL(SYNC_BO, sync_bo, DRM_RENDER_ALLOW),
		741	PANFROST_IOCTL(QUERY_BO_INFO, query_bo_info, DRM_RENDER_ALLOW),
651	};	742	};
652		743
653	static void panfrost_gpu_show_fdinfo(struct panfrost_device *pfdev,	744	static void panfrost_gpu_show_fdinfo(struct panfrost_device *pfdev,
@@ -837,6 +928,9 @@ static void panfrost_debugfs_init(struct drm_minor *minor) · 183 unmodified lines
837	* - 1.4 - adds SET_LABEL_BO	928	* - 1.4 - adds SET_LABEL_BO
838	* - 1.5 - adds JM_CTX_{CREATE,DESTROY} ioctls and extend SUBMIT to allow	929	* - 1.5 - adds JM_CTX_{CREATE,DESTROY} ioctls and extend SUBMIT to allow
839	* context creation with configurable priorities/affinity	930	* context creation with configurable priorities/affinity
		931	* - 1.6 - adds PANFROST_BO_MAP_WB, PANFROST_IOCTL_SYNC_BO,
		932	* PANFROST_IOCTL_QUERY_BO_INFO and
		933	* DRM_PANFROST_PARAM_SELECTED_COHERENCY
840	*/	934	*/
841	static const struct drm_driver panfrost_drm_driver = {	935	static const struct drm_driver panfrost_drm_driver = {
842	.driver_features = DRIVER_RENDER \| DRIVER_GEM \| DRIVER_SYNCOBJ,	936	.driver_features = DRIVER_RENDER \| DRIVER_GEM \| DRIVER_SYNCOBJ,
@@ -849,15 +943,22 @@ static const struct drm_driver panfrost_drm_driver = { · 6 unmodified lines
849	.name = "panfrost",	943	.name = "panfrost",
850	.desc = "panfrost DRM",	944	.desc = "panfrost DRM",
851	.major = 1,	945	.major = 1,
852	.minor = 5,	946	.minor = 6,
853		947
854	.gem_create_object = panfrost_gem_create_object,	948	.gem_create_object = panfrost_gem_create_object,
		949	.gem_prime_import = panfrost_gem_prime_import,
855	.gem_prime_import_sg_table = panfrost_gem_prime_import_sg_table,	950	.gem_prime_import_sg_table = panfrost_gem_prime_import_sg_table,
856	#ifdef CONFIG_DEBUG_FS	951	#ifdef CONFIG_DEBUG_FS
857	.debugfs_init = panfrost_debugfs_init,	952	.debugfs_init = panfrost_debugfs_init,
858	#endif	953	#endif
859	};	954	};
860		955
		956	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		957	bool panfrost_transparent_hugepage = true;
		958	module_param_named(transparent_hugepage, panfrost_transparent_hugepage, bool, 0400);
		959	MODULE_PARM_DESC(transparent_hugepage, "Use a dedicated tmpfs mount point with Transparent Hugepage enabled (true = default)");
		960	#endif
		961
861	static int panfrost_probe(struct platform_device *pdev)	962	static int panfrost_probe(struct platform_device *pdev)
862	{	963	{
863	struct panfrost_device *pfdev;	964	struct panfrost_device *pfdev;

drivers/gpu/drm/panfrost/panfrost_drv.h+9−0

@@ -0,0 +1,9 @@
	1	/* SPDX-License-Identifier: GPL-2.0 or MIT */
	2	/* Copyright 2025 Amazon.com, Inc. or its affiliates */
	3
	4	#ifndef __PANFROST_DRV_H__
	5	#define __PANFROST_DRV_H__
	6
	7	extern bool panfrost_transparent_hugepage;
	8
	9	#endif

drivers/gpu/drm/panfrost/panfrost_gem.c+257−0

@@ -1,5 +1,6 @@
1	// SPDX-License-Identifier: GPL-2.0	1	// SPDX-License-Identifier: GPL-2.0
2	/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */	2	/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
		3	/* Copyright 2025 Amazon.com, Inc. or its affiliates */
3		4
4	#include <linux/cleanup.h>	5	#include <linux/cleanup.h>
5	#include <linux/err.h>	6	#include <linux/err.h>
@@ -10,9 +11,26 @@ · 4 unmodified lines
10	#include <drm/panfrost_drm.h>	11	#include <drm/panfrost_drm.h>
11	#include <drm/drm_print.h>	12	#include <drm/drm_print.h>
12	#include "panfrost_device.h"	13	#include "panfrost_device.h"
		14	#include "panfrost_drv.h"
13	#include "panfrost_gem.h"	15	#include "panfrost_gem.h"
14	#include "panfrost_mmu.h"	16	#include "panfrost_mmu.h"
15		17
		18	void panfrost_gem_init(struct panfrost_device *pfdev)
		19	{
		20	int err;
		21
		22	if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) &&
		23	!panfrost_transparent_hugepage)
		24	return;
		25
		26	err = drm_gem_huge_mnt_create(&pfdev->base, "within_size");
		27	if (drm_gem_get_huge_mnt(&pfdev->base))
		28	drm_info(&pfdev->base, "Using Transparent Hugepage\n");
		29	else if (err)
		30	drm_warn(&pfdev->base, "Can't use Transparent Hugepage (%d)\n",
		31	err);
		32	}
		33
16	#ifdef CONFIG_DEBUG_FS	34	#ifdef CONFIG_DEBUG_FS
17	static void panfrost_gem_debugfs_bo_add(struct panfrost_device *pfdev,	35	static void panfrost_gem_debugfs_bo_add(struct panfrost_device *pfdev,
18	struct panfrost_gem_object *bo)	36	struct panfrost_gem_object *bo)
@@ -259,6 +277,128 @@ static size_t panfrost_gem_rss(struct drm_gem_object *obj) · 240 unmodified lines
259	return 0;	277	return 0;
260	}	278	}
261		279
		280	static struct sg_table *
		281	panfrost_gem_prime_map_dma_buf(struct dma_buf_attachment *attach,
		282	enum dma_data_direction dir)
		283	{
		284	struct sg_table *sgt = drm_gem_map_dma_buf(attach, dir);
		285
		286	if (!IS_ERR(sgt))
		287	attach->priv = sgt;
		288
		289	return sgt;
		290	}
		291
		292	static void
		293	panfrost_gem_prime_unmap_dma_buf(struct dma_buf_attachment *attach,
		294	struct sg_table *sgt,
		295	enum dma_data_direction dir)
		296	{
		297	attach->priv = NULL;
		298	drm_gem_unmap_dma_buf(attach, sgt, dir);
		299	}
		300
		301	static int
		302	panfrost_gem_prime_begin_cpu_access(struct dma_buf *dma_buf,
		303	enum dma_data_direction dir)
		304	{
		305	struct drm_gem_object *obj = dma_buf->priv;
		306	struct drm_device *dev = obj->dev;
		307	struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
		308	struct dma_buf_attachment *attach;
		309
		310	dma_resv_lock(obj->resv, NULL);
		311	if (shmem->sgt)
		312	dma_sync_sgtable_for_cpu(dev->dev, shmem->sgt, dir);
		313
		314	if (shmem->vaddr)
		315	invalidate_kernel_vmap_range(shmem->vaddr, shmem->base.size);
		316
		317	list_for_each_entry(attach, &dma_buf->attachments, node) {
		318	struct sg_table *sgt = attach->priv;
		319
		320	if (sgt)
		321	dma_sync_sgtable_for_cpu(attach->dev, sgt, dir);
		322	}
		323	dma_resv_unlock(obj->resv);
		324
		325	return 0;
		326	}
		327
		328	static int
		329	panfrost_gem_prime_end_cpu_access(struct dma_buf *dma_buf,
		330	enum dma_data_direction dir)
		331	{
		332	struct drm_gem_object *obj = dma_buf->priv;
		333	struct drm_device *dev = obj->dev;
		334	struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
		335	struct dma_buf_attachment *attach;
		336
		337	dma_resv_lock(obj->resv, NULL);
		338	list_for_each_entry(attach, &dma_buf->attachments, node) {
		339	struct sg_table *sgt = attach->priv;
		340
		341	if (sgt)
		342	dma_sync_sgtable_for_device(attach->dev, sgt, dir);
		343	}
		344
		345	if (shmem->vaddr)
		346	flush_kernel_vmap_range(shmem->vaddr, shmem->base.size);
		347
		348	if (shmem->sgt)
		349	dma_sync_sgtable_for_device(dev->dev, shmem->sgt, dir);
		350
		351	dma_resv_unlock(obj->resv);
		352	return 0;
		353	}
		354
		355	static const struct dma_buf_ops panfrost_dma_buf_ops = {
		356	.attach = drm_gem_map_attach,
		357	.detach = drm_gem_map_detach,
		358	.map_dma_buf = panfrost_gem_prime_map_dma_buf,
		359	.unmap_dma_buf = panfrost_gem_prime_unmap_dma_buf,
		360	.release = drm_gem_dmabuf_release,
		361	.mmap = drm_gem_dmabuf_mmap,
		362	.vmap = drm_gem_dmabuf_vmap,
		363	.vunmap = drm_gem_dmabuf_vunmap,
		364	.begin_cpu_access = panfrost_gem_prime_begin_cpu_access,
		365	.end_cpu_access = panfrost_gem_prime_end_cpu_access,
		366	};
		367
		368	static struct dma_buf *
		369	panfrost_gem_prime_export(struct drm_gem_object *obj, int flags)
		370	{
		371	struct drm_device *dev = obj->dev;
		372	struct dma_buf_export_info exp_info = {
		373	.exp_name = KBUILD_MODNAME,
		374	.owner = THIS_MODULE,
		375	.ops = &panfrost_dma_buf_ops,
		376	.size = obj->size,
		377	.flags = flags,
		378	.priv = obj,
		379	.resv = obj->resv,
		380	};
		381
		382	return drm_gem_dmabuf_export(dev, &exp_info);
		383	}
		384
		385	struct drm_gem_object *
		386	panfrost_gem_prime_import(struct drm_device *dev,
		387	struct dma_buf *dma_buf)
		388	{
		389	struct drm_gem_object *obj = dma_buf->priv;
		390
		391	if (dma_buf->ops == &panfrost_dma_buf_ops && obj->dev == dev) {
		392	/* Importing dmabuf exported from our own gem increases
		393	* refcount on gem itself instead of f_count of dmabuf.
		394	*/
		395	drm_gem_object_get(obj);
		396	return obj;
		397	}
		398
		399	return drm_gem_prime_import(dev, dma_buf);
		400	}
		401
262	static const struct drm_gem_object_funcs panfrost_gem_funcs = {	402	static const struct drm_gem_object_funcs panfrost_gem_funcs = {
263	.free = panfrost_gem_free_object,	403	.free = panfrost_gem_free_object,
264	.open = panfrost_gem_open,	404	.open = panfrost_gem_open,
@@ -267,6 +407,7 @@ static const struct drm_gem_object_funcs panfrost_gem_funcs = { · 2 unmodified lines
267	.pin = panfrost_gem_pin,	407	.pin = panfrost_gem_pin,
268	.unpin = drm_gem_shmem_object_unpin,	408	.unpin = drm_gem_shmem_object_unpin,
269	.get_sg_table = drm_gem_shmem_object_get_sg_table,	409	.get_sg_table = drm_gem_shmem_object_get_sg_table,
		410	.export = panfrost_gem_prime_export,
270	.vmap = drm_gem_shmem_object_vmap,	411	.vmap = drm_gem_shmem_object_vmap,
271	.vunmap = drm_gem_shmem_object_vunmap,	412	.vunmap = drm_gem_shmem_object_vunmap,
272	.mmap = drm_gem_shmem_object_mmap,	413	.mmap = drm_gem_shmem_object_mmap,
@@ -303,12 +444,42 @@ struct drm_gem_object panfrost_gem_create_object(struct drm_device dev, size_t · 30 unmodified lines
303	return &obj->base.base;	444	return &obj->base.base;
304	}	445	}
305		446
		447	static bool
		448	should_map_wc(struct panfrost_gem_object *bo)
		449	{
		450	struct panfrost_device *pfdev = to_panfrost_device(bo->base.base.dev);
		451
		452	/* We can't do uncached mappings if the device is coherent,
		453	* because the zeroing done by the shmem layer at page allocation
		454	* time happens on a cached mapping which isn't CPU-flushed (at least
		455	* not on Arm64 where the flush is deferred to PTE setup time, and
		456	* only done conditionally based on the mapping permissions). We can't
		457	* rely on dma_map_sgtable()/dma_sync_sgtable_for_xxx() either to flush
		458	* those, because they are NOPed if dma_dev_coherent() returns true.
		459	*/
		460	if (pfdev->coherent)
		461	return false;
		462
		463	/* Cached mappings are explicitly requested, so no write-combine. */
		464	if (bo->wb_mmap)
		465	return false;
		466
		467	/* The default is write-combine. */
		468	return true;
		469	}
		470
306	struct panfrost_gem_object *	471	struct panfrost_gem_object *
307	panfrost_gem_create(struct drm_device *dev, size_t size, u32 flags)	472	panfrost_gem_create(struct drm_device *dev, size_t size, u32 flags)
308	{	473	{
309	struct drm_gem_shmem_object *shmem;	474	struct drm_gem_shmem_object *shmem;
310	struct panfrost_gem_object *bo;	475	struct panfrost_gem_object *bo;
311		476
		477	/* The heap buffer is not supposed to be CPU-visible, so don't allow
		478	* WB_MMAP on those.
		479	*/
		480	if ((flags & PANFROST_BO_HEAP) && (flags & PANFROST_BO_WB_MMAP))
		481	return ERR_PTR(-EINVAL);
		482
312	/* Round up heap allocations to 2MB to keep fault handling simple */	483	/* Round up heap allocations to 2MB to keep fault handling simple */
313	if (flags & PANFROST_BO_HEAP)	484	if (flags & PANFROST_BO_HEAP)
314	size = roundup(size, SZ_2M);	485	size = roundup(size, SZ_2M);
@@ -320,6 +491,8 @@ panfrost_gem_create(struct drm_device *dev, size_t size, u32 flags) · 5 unmodified lines
320	bo = to_panfrost_bo(&shmem->base);	491	bo = to_panfrost_bo(&shmem->base);
321	bo->noexec = !!(flags & PANFROST_BO_NOEXEC);	492	bo->noexec = !!(flags & PANFROST_BO_NOEXEC);
322	bo->is_heap = !!(flags & PANFROST_BO_HEAP);	493	bo->is_heap = !!(flags & PANFROST_BO_HEAP);
		494	bo->wb_mmap = !!(flags & PANFROST_BO_WB_MMAP);
		495	bo->base.map_wc = should_map_wc(bo);
323		496
324	return bo;	497	return bo;
325	}	498	}
@@ -366,6 +539,90 @@ panfrost_gem_set_label(struct drm_gem_object obj, const char label) · 40 unmodified lines
366	kfree_const(old_label);	539	kfree_const(old_label);
367	}	540	}
368		541
		542	int
		543	panfrost_gem_sync(struct drm_gem_object *obj, u32 type, u32 offset, u32 size)
		544	{
		545	struct panfrost_gem_object *bo = to_panfrost_bo(obj);
		546	struct drm_gem_shmem_object *shmem = &bo->base;
		547	const struct drm_device *dev = shmem->base.dev;
		548	struct sg_table *sgt;
		549	struct scatterlist *sgl;
		550	unsigned int count;
		551
		552	/* Make sure the range is in bounds. */
		553	if (offset + size < offset \|\| offset + size > shmem->base.size)
		554	return -EINVAL;
		555
		556	/* Disallow CPU-cache maintenance on imported buffers. */
		557	if (drm_gem_is_imported(&shmem->base))
		558	return -EINVAL;
		559
		560	switch (type) {
		561	case PANFROST_BO_SYNC_CPU_CACHE_FLUSH:
		562	case PANFROST_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE:
		563	break;
		564
		565	default:
		566	return -EINVAL;
		567	}
		568
		569	/* Don't bother if it's WC-mapped */
		570	if (shmem->map_wc)
		571	return 0;
		572
		573	/* Nothing to do if the size is zero. */
		574	if (size == 0)
		575	return 0;
		576
		577	sgt = drm_gem_shmem_get_pages_sgt(shmem);
		578	if (IS_ERR(sgt))
		579	return PTR_ERR(sgt);
		580
		581	for_each_sgtable_dma_sg(sgt, sgl, count) {
		582	if (size == 0)
		583	break;
		584
		585	dma_addr_t paddr = sg_dma_address(sgl);
		586	size_t len = sg_dma_len(sgl);
		587
		588	if (len <= offset) {
		589	offset -= len;
		590	continue;
		591	}
		592
		593	paddr += offset;
		594	len -= offset;
		595	len = min_t(size_t, len, size);
		596	size -= len;
		597	offset = 0;
		598
		599	/* It's unclear whether dma_sync_xxx() is the right API to do CPU
		600	* cache maintenance given an IOMMU can register their own
		601	* implementation doing more than just CPU cache flushes/invalidation,
		602	* and what we really care about here is CPU caches only, but that's
		603	* the best we have that is both arch-agnostic and does at least the
		604	* CPU cache maintenance on a <page,offset,size> tuple.
		605	*
		606	* Also, I wish we could do a single
		607	*
		608	* dma_sync_single_for_device(BIDIR)
		609	*
		610	* and get a flush+invalidate, but that's not how it's implemented
		611	* in practice (at least on arm64), so we have to make it
		612	*
		613	* dma_sync_single_for_device(TO_DEVICE)
		614	* dma_sync_single_for_cpu(FROM_DEVICE)
		615	*
		616	* for the flush+invalidate case.
		617	*/
		618	dma_sync_single_for_device(dev->dev, paddr, len, DMA_TO_DEVICE);
		619	if (type == PANFROST_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE)
		620	dma_sync_single_for_cpu(dev->dev, paddr, len, DMA_FROM_DEVICE);
		621	}
		622
		623	return 0;
		624	}
		625
369	void	626	void
370	panfrost_gem_internal_set_label(struct drm_gem_object obj, const char label)	627	panfrost_gem_internal_set_label(struct drm_gem_object obj, const char label)
371	{	628	{

drivers/gpu/drm/panfrost/panfrost_gem.h+12−0

 	bool noexec		:1;
 	bool is_heap		:1;
+	/* On coherent devices, this reflects the creation flags, not the true
+	 * cacheability attribute of the mapping.
+	 */
+	bool wb_mmap		:1;
 #ifdef CONFIG_DEBUG_FS
 	struct panfrost_gem_debugfs debugfs;
 #endif
 	return container_of(node, struct panfrost_gem_mapping, mmnode);
 }
+void panfrost_gem_init(struct panfrost_device *pfdev);
 struct drm_gem_object *panfrost_gem_create_object(struct drm_device *dev, size_t size);
 struct drm_gem_object *
 panfrost_gem_prime_import_sg_table(struct drm_device *dev,
 				   struct dma_buf_attachment *attach,
 				   struct sg_table *sgt);
+struct drm_gem_object *
+panfrost_gem_prime_import(struct drm_device *dev,
+			  struct dma_buf *dma_buf);
 struct panfrost_gem_object *
 panfrost_gem_create(struct drm_device *dev, size_t size, u32 flags);
 void panfrost_gem_shrinker_cleanup(struct drm_device *dev);
 void panfrost_gem_set_label(struct drm_gem_object *obj, const char *label);
+int panfrost_gem_sync(struct drm_gem_object *obj, u32 type,
+		      u32 offset, u32 size);
 void panfrost_gem_internal_set_label(struct drm_gem_object *obj, const char *label);
 #ifdef CONFIG_DEBUG_FS

drivers/gpu/drm/panfrost/panfrost_gpu.c+23−3

@@ -159,8 +159,8 @@ static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev) · 158 unmodified lines
159	pfdev->features.revision >= 0x2000)	159	pfdev->features.revision >= 0x2000)
160	quirks \|= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT;	160	quirks \|= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT;
161	else if (panfrost_model_eq(pfdev, 0x6000) &&	161	else if (panfrost_model_eq(pfdev, 0x6000) &&
162	pfdev->features.coherency_features == COHERENCY_ACE)	162	pfdev->features.coherency_features == BIT(COHERENCY_ACE))
163	quirks \|= (COHERENCY_ACE_LITE \| COHERENCY_ACE) <<	163	quirks \|= (BIT(COHERENCY_ACE_LITE) \| BIT(COHERENCY_ACE)) <<
164	JM_FORCE_COHERENCY_FEATURES_SHIFT;	164	JM_FORCE_COHERENCY_FEATURES_SHIFT;
165		165
166	if (panfrost_has_hw_feature(pfdev, HW_FEATURE_IDVS_GROUP_SIZE))	166	if (panfrost_has_hw_feature(pfdev, HW_FEATURE_IDVS_GROUP_SIZE))
@@ -263,7 +263,27 @@ static int panfrost_gpu_init_features(struct panfrost_device *pfdev) · 96 unmodified lines
263	pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS);	263	pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS);
264	pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE);	264	pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE);
265	pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE);	265	pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE);
266	pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);	266
		267	if (panfrost_has_hw_feature(pfdev, HW_FEATURE_COHERENCY_REG))
		268	pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);
		269	else
		270	pfdev->features.coherency_features = BIT(COHERENCY_ACE_LITE);
		271
		272	BUILD_BUG_ON(COHERENCY_ACE_LITE != DRM_PANFROST_GPU_COHERENCY_ACE_LITE);
		273	BUILD_BUG_ON(COHERENCY_ACE != DRM_PANFROST_GPU_COHERENCY_ACE);
		274	BUILD_BUG_ON(COHERENCY_NONE != DRM_PANFROST_GPU_COHERENCY_NONE);
		275
		276	if (!pfdev->coherent) {
		277	pfdev->features.selected_coherency = COHERENCY_NONE;
		278	} else if (pfdev->features.coherency_features & BIT(COHERENCY_ACE)) {
		279	pfdev->features.selected_coherency = COHERENCY_ACE;
		280	} else if (pfdev->features.coherency_features & BIT(COHERENCY_ACE_LITE)) {
		281	pfdev->features.selected_coherency = COHERENCY_ACE_LITE;
		282	} else {
		283	drm_WARN(&pfdev->base, true, "No known coherency protocol supported");
		284	pfdev->features.selected_coherency = COHERENCY_NONE;
		285	}
		286
267	pfdev->features.afbc_features = gpu_read(pfdev, GPU_AFBC_FEATURES);	287	pfdev->features.afbc_features = gpu_read(pfdev, GPU_AFBC_FEATURES);
268	for (i = 0; i < 4; i++)	288	for (i = 0; i < 4; i++)
269	pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i));	289	pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i));

drivers/gpu/drm/panfrost/panfrost_regs.h+8−2

 #define GPU_L2_PRESENT_LO		0x120	/* (RO) Level 2 cache present bitmap, low word */
 #define GPU_L2_PRESENT_HI		0x124	/* (RO) Level 2 cache present bitmap, high word */
+/* GPU_COHERENCY_FEATURES is a bitmask of BIT(COHERENCY_xxx) values encoding the
+ * set of supported coherency protocols. GPU_COHERENCY_ENABLE is passed a
+ * COHERENCY_xxx value.
+ */
 #define GPU_COHERENCY_FEATURES		0x300	/* (RO) Coherency features present */
-#define   COHERENCY_ACE_LITE		BIT(0)
+#define GPU_COHERENCY_ENABLE		0x304	/* (RW) Coherency protocol selection */
-#define   COHERENCY_ACE			BIT(1)
+#define   COHERENCY_ACE_LITE		0
+#define   COHERENCY_ACE			1
+#define   COHERENCY_NONE		31
 #define GPU_STACK_PRESENT_LO		0xE00   /* (RO) Core stack present bitmap, low word */
 #define GPU_STACK_PRESENT_HI		0xE04   /* (RO) Core stack present bitmap, high word */

drivers/gpu/drm/panthor/panthor_device.c+12−1

 #include "panthor_devfreq.h"
 #include "panthor_device.h"
 #include "panthor_fw.h"
+#include "panthor_gem.h"
 #include "panthor_gpu.h"
 #include "panthor_hw.h"
 #include "panthor_mmu.h"
 static int panthor_gpu_coherency_init(struct panthor_device *ptdev)
 {
+	BUILD_BUG_ON(GPU_COHERENCY_NONE != DRM_PANTHOR_GPU_COHERENCY_NONE);
+	BUILD_BUG_ON(GPU_COHERENCY_ACE_LITE != DRM_PANTHOR_GPU_COHERENCY_ACE_LITE);
+	BUILD_BUG_ON(GPU_COHERENCY_ACE != DRM_PANTHOR_GPU_COHERENCY_ACE);
+	/* Start with no coherency, and update it if the device is flagged coherent. */
+	ptdev->gpu_info.selected_coherency = GPU_COHERENCY_NONE;
 	ptdev->coherent = device_get_dma_attr(ptdev->base.dev) == DEV_DMA_COHERENT;
 	if (!ptdev->coherent)
 	 * ACE protocol has never been supported for command stream frontend GPUs.
 	 */
 	if ((gpu_read(ptdev, GPU_COHERENCY_FEATURES) &
-		      GPU_COHERENCY_PROT_BIT(ACE_LITE)))
+		      GPU_COHERENCY_PROT_BIT(ACE_LITE))) {
+		ptdev->gpu_info.selected_coherency = GPU_COHERENCY_ACE_LITE;
 		return 0;
+	}
 	drm_err(&ptdev->base, "Coherency not supported by the device");
 	return -ENOTSUPP;
 	if (ret)
 		goto err_unplug_fw;
+	panthor_gem_init(ptdev);
 	/* ~3 frames */
 	pm_runtime_set_autosuspend_delay(ptdev->base.dev, 50);
 	pm_runtime_use_autosuspend(ptdev->base.dev);

drivers/gpu/drm/panthor/panthor_drv.c+84−3

@@ -177,7 +177,8 @@ panthor_get_uobj_array(const struct drm_panthor_obj_array *in, u32 min_stride, · 176 unmodified lines
177	PANTHOR_UOBJ_DECL(struct drm_panthor_sync_op, timeline_value), \	177	PANTHOR_UOBJ_DECL(struct drm_panthor_sync_op, timeline_value), \
178	PANTHOR_UOBJ_DECL(struct drm_panthor_queue_submit, syncs), \	178	PANTHOR_UOBJ_DECL(struct drm_panthor_queue_submit, syncs), \
179	PANTHOR_UOBJ_DECL(struct drm_panthor_queue_create, ringbuf_size), \	179	PANTHOR_UOBJ_DECL(struct drm_panthor_queue_create, ringbuf_size), \
180	PANTHOR_UOBJ_DECL(struct drm_panthor_vm_bind_op, syncs))	180	PANTHOR_UOBJ_DECL(struct drm_panthor_vm_bind_op, syncs), \
		181	PANTHOR_UOBJ_DECL(struct drm_panthor_bo_sync_op, size))
181		182
182	/**	183	/**
183	* PANTHOR_UOBJ_SET() - Copy a kernel object to a user object.	184	* PANTHOR_UOBJ_SET() - Copy a kernel object to a user object.
@@ -901,7 +902,8 @@ static int panthor_ioctl_vm_destroy(struct drm_device ddev, void data, · 717 unmodified lines
901	return panthor_vm_pool_destroy_vm(pfile->vms, args->id);	902	return panthor_vm_pool_destroy_vm(pfile->vms, args->id);
902	}	903	}
903		904
904	#define PANTHOR_BO_FLAGS DRM_PANTHOR_BO_NO_MMAP	905	#define PANTHOR_BO_FLAGS (DRM_PANTHOR_BO_NO_MMAP \| \
		906	DRM_PANTHOR_BO_WB_MMAP)
905		907
906	static int panthor_ioctl_bo_create(struct drm_device ddev, void data,	908	static int panthor_ioctl_bo_create(struct drm_device ddev, void data,
907	struct drm_file *file)	909	struct drm_file *file)
@@ -920,6 +922,10 @@ static int panthor_ioctl_bo_create(struct drm_device ddev, void data, · 12 unmodified lines
920	goto out_dev_exit;	922	goto out_dev_exit;
921	}	923	}
922		924
		925	if ((args->flags & DRM_PANTHOR_BO_NO_MMAP) &&
		926	(args->flags & DRM_PANTHOR_BO_WB_MMAP))
		927	return -EINVAL;
		928
923	if (args->exclusive_vm_id) {	929	if (args->exclusive_vm_id) {
924	vm = panthor_vm_pool_get_vm(pfile->vms, args->exclusive_vm_id);	930	vm = panthor_vm_pool_get_vm(pfile->vms, args->exclusive_vm_id);
925	if (!vm) {	931	if (!vm) {
@@ -1396,6 +1402,66 @@ static int panthor_ioctl_set_user_mmio_offset(struct drm_device *ddev, · 470 unmodified lines
1396	return 0;	1402	return 0;
1397	}	1403	}
1398		1404
		1405	static int panthor_ioctl_bo_sync(struct drm_device ddev, void data,
		1406	struct drm_file *file)
		1407	{
		1408	struct drm_panthor_bo_sync *args = data;
		1409	struct drm_panthor_bo_sync_op *ops;
		1410	struct drm_gem_object *obj;
		1411	int ret;
		1412
		1413	if (!args->ops.count)
		1414	return 0;
		1415
		1416	ret = PANTHOR_UOBJ_GET_ARRAY(ops, &args->ops);
		1417	if (ret)
		1418	return ret;
		1419
		1420	for (u32 i = 0; i < args->ops.count; i++) {
		1421	obj = drm_gem_object_lookup(file, ops[i].handle);
		1422	if (!obj) {
		1423	ret = -ENOENT;
		1424	goto err_ops;
		1425	}
		1426
		1427	ret = panthor_gem_sync(obj, ops[i].type, ops[i].offset,
		1428	ops[i].size);
		1429
		1430	drm_gem_object_put(obj);
		1431
		1432	if (ret)
		1433	goto err_ops;
		1434	}
		1435
		1436	err_ops:
		1437	kvfree(ops);
		1438
		1439	return ret;
		1440	}
		1441
		1442	static int panthor_ioctl_bo_query_info(struct drm_device ddev, void data,
		1443	struct drm_file *file)
		1444	{
		1445	struct drm_panthor_bo_query_info *args = data;
		1446	struct panthor_gem_object *bo;
		1447	struct drm_gem_object *obj;
		1448
		1449	obj = drm_gem_object_lookup(file, args->handle);
		1450	if (!obj)
		1451	return -ENOENT;
		1452
		1453	bo = to_panthor_bo(obj);
		1454	args->pad = 0;
		1455	args->create_flags = bo->flags;
		1456
		1457	args->extra_flags = 0;
		1458	if (drm_gem_is_imported(&bo->base.base))
		1459	args->extra_flags \|= DRM_PANTHOR_BO_IS_IMPORTED;
		1460
		1461	drm_gem_object_put(obj);
		1462	return 0;
		1463	}
		1464
1399	static int	1465	static int
1400	panthor_open(struct drm_device ddev, struct drm_file file)	1466	panthor_open(struct drm_device ddev, struct drm_file file)
1401	{	1467	{
@@ -1470,6 +1536,8 @@ static const struct drm_ioctl_desc panthor_drm_driver_ioctls[] = { · 68 unmodified lines
1470	PANTHOR_IOCTL(GROUP_SUBMIT, group_submit, DRM_RENDER_ALLOW),	1536	PANTHOR_IOCTL(GROUP_SUBMIT, group_submit, DRM_RENDER_ALLOW),
1471	PANTHOR_IOCTL(BO_SET_LABEL, bo_set_label, DRM_RENDER_ALLOW),	1537	PANTHOR_IOCTL(BO_SET_LABEL, bo_set_label, DRM_RENDER_ALLOW),
1472	PANTHOR_IOCTL(SET_USER_MMIO_OFFSET, set_user_mmio_offset, DRM_RENDER_ALLOW),	1538	PANTHOR_IOCTL(SET_USER_MMIO_OFFSET, set_user_mmio_offset, DRM_RENDER_ALLOW),
		1539	PANTHOR_IOCTL(BO_SYNC, bo_sync, DRM_RENDER_ALLOW),
		1540	PANTHOR_IOCTL(BO_QUERY_INFO, bo_query_info, DRM_RENDER_ALLOW),
1473	};	1541	};
1474		1542
1475	static int panthor_mmap(struct file filp, struct vm_area_struct vma)	1543	static int panthor_mmap(struct file filp, struct vm_area_struct vma)
@@ -1559,6 +1627,7 @@ static const struct file_operations panthor_drm_driver_fops = { · 83 unmodified lines
1559	.read = drm_read,	1627	.read = drm_read,
1560	.llseek = noop_llseek,	1628	.llseek = noop_llseek,
1561	.mmap = panthor_mmap,	1629	.mmap = panthor_mmap,
		1630	.get_unmapped_area = drm_gem_get_unmapped_area,
1562	.show_fdinfo = drm_show_fdinfo,	1631	.show_fdinfo = drm_show_fdinfo,
1563	.fop_flags = FOP_UNSIGNED_OFFSET,	1632	.fop_flags = FOP_UNSIGNED_OFFSET,
1564	};	1633	};
@@ -1604,6 +1673,11 @@ static void panthor_debugfs_init(struct drm_minor *minor) · 39 unmodified lines
1604	* - 1.3 - adds DRM_PANTHOR_GROUP_STATE_INNOCENT flag	1673	* - 1.3 - adds DRM_PANTHOR_GROUP_STATE_INNOCENT flag
1605	* - 1.4 - adds DRM_IOCTL_PANTHOR_BO_SET_LABEL ioctl	1674	* - 1.4 - adds DRM_IOCTL_PANTHOR_BO_SET_LABEL ioctl
1606	* - 1.5 - adds DRM_PANTHOR_SET_USER_MMIO_OFFSET ioctl	1675	* - 1.5 - adds DRM_PANTHOR_SET_USER_MMIO_OFFSET ioctl
		1676	* - 1.6 - enables GLB_COUNTER_EN
		1677	* - 1.7 - adds DRM_PANTHOR_BO_WB_MMAP flag
		1678	* - adds DRM_IOCTL_PANTHOR_BO_SYNC ioctl
		1679	* - adds DRM_IOCTL_PANTHOR_BO_QUERY_INFO ioctl
		1680	* - adds drm_panthor_gpu_info::selected_coherency
1607	*/	1681	*/
1608	static const struct drm_driver panthor_drm_driver = {	1682	static const struct drm_driver panthor_drm_driver = {
1609	.driver_features = DRIVER_RENDER \| DRIVER_GEM \| DRIVER_SYNCOBJ \|	1683	.driver_features = DRIVER_RENDER \| DRIVER_GEM \| DRIVER_SYNCOBJ \|
@@ -1617,15 +1691,22 @@ static const struct drm_driver panthor_drm_driver = { · 7 unmodified lines
1617	.name = "panthor",	1691	.name = "panthor",
1618	.desc = "Panthor DRM driver",	1692	.desc = "Panthor DRM driver",
1619	.major = 1,	1693	.major = 1,
1620	.minor = 5,	1694	.minor = 7,
1621		1695
1622	.gem_create_object = panthor_gem_create_object,	1696	.gem_create_object = panthor_gem_create_object,
1623	.gem_prime_import_sg_table = drm_gem_shmem_prime_import_sg_table,	1697	.gem_prime_import_sg_table = drm_gem_shmem_prime_import_sg_table,
		1698	.gem_prime_import = panthor_gem_prime_import,
1624	#ifdef CONFIG_DEBUG_FS	1699	#ifdef CONFIG_DEBUG_FS
1625	.debugfs_init = panthor_debugfs_init,	1700	.debugfs_init = panthor_debugfs_init,
1626	#endif	1701	#endif
1627	};	1702	};
1628		1703
		1704	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		1705	bool panthor_transparent_hugepage = true;
		1706	module_param_named(transparent_hugepage, panthor_transparent_hugepage, bool, 0400);
		1707	MODULE_PARM_DESC(transparent_hugepage, "Use a dedicated tmpfs mount point with Transparent Hugepage enabled (true = default)");
		1708	#endif
		1709
1629	static int panthor_probe(struct platform_device *pdev)	1710	static int panthor_probe(struct platform_device *pdev)
1630	{	1711	{
1631	struct panthor_device *ptdev;	1712	struct panthor_device *ptdev;

drivers/gpu/drm/panthor/panthor_drv.h+9−0

@@ -0,0 +1,9 @@
	1	/* SPDX-License-Identifier: GPL-2.0 or MIT */
	2	/* Copyright 2025 Amazon.com, Inc. or its affiliates */
	3
	4	#ifndef __PANTHOR_DRV_H__
	5	#define __PANTHOR_DRV_H__
	6
	7	extern bool panthor_transparent_hugepage;
	8
	9	#endif

drivers/gpu/drm/panthor/panthor_fw.c+2−2

 	if (panthor_fw_has_glb_state(ptdev))
 		glb_iface->input->ack_irq_mask |= GLB_STATE_MASK;
-	panthor_fw_update_reqs(glb_iface, req, GLB_IDLE_EN, GLB_IDLE_EN);
+	panthor_fw_update_reqs(glb_iface, req, GLB_IDLE_EN | GLB_COUNTER_EN,
+			       GLB_IDLE_EN | GLB_COUNTER_EN);
 	panthor_fw_toggle_reqs(glb_iface, req, ack,
 			       GLB_CFG_ALLOC_EN |
 			       GLB_CFG_POWEROFF_TIMER |
 		else
 			ptdev->reset.fast = true;
 	}
-	panthor_fw_stop(ptdev);
 	panthor_job_irq_suspend(&ptdev->fw->irq);
 	panthor_fw_stop(ptdev);

drivers/gpu/drm/panthor/panthor_gem.c+255−3

@@ -1,6 +1,7 @@
1	// SPDX-License-Identifier: GPL-2.0 or MIT	1	// SPDX-License-Identifier: GPL-2.0 or MIT
2	/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */	2	/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
3	/* Copyright 2023 Collabora ltd. */	3	/* Copyright 2023 Collabora ltd. */
		4	/* Copyright 2025 Amazon.com, Inc. or its affiliates */
4		5
5	#include <linux/cleanup.h>	6	#include <linux/cleanup.h>
6	#include <linux/dma-buf.h>	7	#include <linux/dma-buf.h>
@@ -12,10 +13,27 @@ · 5 unmodified lines
12	#include <drm/panthor_drm.h>	13	#include <drm/panthor_drm.h>
13		14
14	#include "panthor_device.h"	15	#include "panthor_device.h"
		16	#include "panthor_drv.h"
15	#include "panthor_fw.h"	17	#include "panthor_fw.h"
16	#include "panthor_gem.h"	18	#include "panthor_gem.h"
17	#include "panthor_mmu.h"	19	#include "panthor_mmu.h"
18		20
		21	void panthor_gem_init(struct panthor_device *ptdev)
		22	{
		23	int err;
		24
		25	if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) &&
		26	!panthor_transparent_hugepage)
		27	return;
		28
		29	err = drm_gem_huge_mnt_create(&ptdev->base, "within_size");
		30	if (drm_gem_get_huge_mnt(&ptdev->base))
		31	drm_info(&ptdev->base, "Using Transparent Hugepage\n");
		32	else if (err)
		33	drm_warn(&ptdev->base, "Can't use Transparent Hugepage (%d)\n",
		34	err);
		35	}
		36
19	#ifdef CONFIG_DEBUG_FS	37	#ifdef CONFIG_DEBUG_FS
20	static void panthor_gem_debugfs_bo_init(struct panthor_gem_object *bo)	38	static void panthor_gem_debugfs_bo_init(struct panthor_gem_object *bo)
21	{	39	{
@@ -59,6 +77,39 @@ static void panthor_gem_debugfs_set_usage_flags(struct panthor_gem_object *bo, u · 37 unmodified lines
59	static void panthor_gem_debugfs_bo_init(struct panthor_gem_object *bo) {}	77	static void panthor_gem_debugfs_bo_init(struct panthor_gem_object *bo) {}
60	#endif	78	#endif
61		79
		80	static bool
		81	should_map_wc(struct panthor_gem_object bo, struct panthor_vm exclusive_vm)
		82	{
		83	struct panthor_device *ptdev = container_of(bo->base.base.dev, struct panthor_device, base);
		84
		85	/* We can't do uncached mappings if the device is coherent,
		86	* because the zeroing done by the shmem layer at page allocation
		87	* time happens on a cached mapping which isn't CPU-flushed (at least
		88	* not on Arm64 where the flush is deferred to PTE setup time, and
		89	* only done conditionally based on the mapping permissions). We can't
		90	* rely on dma_map_sgtable()/dma_sync_sgtable_for_xxx() either to flush
		91	* those, because they are NOPed if dma_dev_coherent() returns true.
		92	*
		93	* FIXME: Note that this problem is going to pop up again when we
		94	* decide to support mapping buffers with the NO_MMAP flag as
		95	* non-shareable (AKA buffers accessed only by the GPU), because we
		96	* need the same CPU flush to happen after page allocation, otherwise
		97	* there's a risk of data leak or late corruption caused by a dirty
		98	* cacheline being evicted. At this point we'll need a way to force
		99	* CPU cache maintenance regardless of whether the device is coherent
		100	* or not.
		101	*/
		102	if (ptdev->coherent)
		103	return false;
		104
		105	/* Cached mappings are explicitly requested, so no write-combine. */
		106	if (bo->flags & DRM_PANTHOR_BO_WB_MMAP)
		107	return false;
		108
		109	/* The default is write-combine. */
		110	return true;
		111	}
		112
62	static void panthor_gem_free_object(struct drm_gem_object *obj)	113	static void panthor_gem_free_object(struct drm_gem_object *obj)
63	{	114	{
64	struct panthor_gem_object *bo = to_panthor_bo(obj);	115	struct panthor_gem_object *bo = to_panthor_bo(obj);
@@ -145,6 +196,7 @@ panthor_kernel_bo_create(struct panthor_device ptdev, struct panthor_vm vm, · 80 unmodified lines
145	bo = to_panthor_bo(&obj->base);	196	bo = to_panthor_bo(&obj->base);
146	kbo->obj = &obj->base;	197	kbo->obj = &obj->base;
147	bo->flags = bo_flags;	198	bo->flags = bo_flags;
		199	bo->base.map_wc = should_map_wc(bo, vm);
148	bo->exclusive_vm_root_gem = panthor_vm_root_gem(vm);	200	bo->exclusive_vm_root_gem = panthor_vm_root_gem(vm);
149	drm_gem_object_get(bo->exclusive_vm_root_gem);	201	drm_gem_object_get(bo->exclusive_vm_root_gem);
150	bo->base.base.resv = bo->exclusive_vm_root_gem->resv;	202	bo->base.base.resv = bo->exclusive_vm_root_gem->resv;
@@ -184,14 +236,130 @@ err_free_bo: · 33 unmodified lines
184	return ERR_PTR(ret);	236	return ERR_PTR(ret);
185	}	237	}
186		238
		239	static struct sg_table *
		240	panthor_gem_prime_map_dma_buf(struct dma_buf_attachment *attach,
		241	enum dma_data_direction dir)
		242	{
		243	struct sg_table *sgt = drm_gem_map_dma_buf(attach, dir);
		244
		245	if (!IS_ERR(sgt))
		246	attach->priv = sgt;
		247
		248	return sgt;
		249	}
		250
		251	static void
		252	panthor_gem_prime_unmap_dma_buf(struct dma_buf_attachment *attach,
		253	struct sg_table *sgt,
		254	enum dma_data_direction dir)
		255	{
		256	attach->priv = NULL;
		257	drm_gem_unmap_dma_buf(attach, sgt, dir);
		258	}
		259
		260	static int
		261	panthor_gem_prime_begin_cpu_access(struct dma_buf *dma_buf,
		262	enum dma_data_direction dir)
		263	{
		264	struct drm_gem_object *obj = dma_buf->priv;
		265	struct drm_device *dev = obj->dev;
		266	struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
		267	struct dma_buf_attachment *attach;
		268
		269	dma_resv_lock(obj->resv, NULL);
		270	if (shmem->sgt)
		271	dma_sync_sgtable_for_cpu(dev->dev, shmem->sgt, dir);
		272
		273	if (shmem->vaddr)
		274	invalidate_kernel_vmap_range(shmem->vaddr, shmem->base.size);
		275
		276	list_for_each_entry(attach, &dma_buf->attachments, node) {
		277	struct sg_table *sgt = attach->priv;
		278
		279	if (sgt)
		280	dma_sync_sgtable_for_cpu(attach->dev, sgt, dir);
		281	}
		282	dma_resv_unlock(obj->resv);
		283
		284	return 0;
		285	}
		286
		287	static int
		288	panthor_gem_prime_end_cpu_access(struct dma_buf *dma_buf,
		289	enum dma_data_direction dir)
		290	{
		291	struct drm_gem_object *obj = dma_buf->priv;
		292	struct drm_device *dev = obj->dev;
		293	struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
		294	struct dma_buf_attachment *attach;
		295
		296	dma_resv_lock(obj->resv, NULL);
		297	list_for_each_entry(attach, &dma_buf->attachments, node) {
		298	struct sg_table *sgt = attach->priv;
		299
		300	if (sgt)
		301	dma_sync_sgtable_for_device(attach->dev, sgt, dir);
		302	}
		303
		304	if (shmem->vaddr)
		305	flush_kernel_vmap_range(shmem->vaddr, shmem->base.size);
		306
		307	if (shmem->sgt)
		308	dma_sync_sgtable_for_device(dev->dev, shmem->sgt, dir);
		309
		310	dma_resv_unlock(obj->resv);
		311	return 0;
		312	}
		313
		314	static const struct dma_buf_ops panthor_dma_buf_ops = {
		315	.attach = drm_gem_map_attach,
		316	.detach = drm_gem_map_detach,
		317	.map_dma_buf = panthor_gem_prime_map_dma_buf,
		318	.unmap_dma_buf = panthor_gem_prime_unmap_dma_buf,
		319	.release = drm_gem_dmabuf_release,
		320	.mmap = drm_gem_dmabuf_mmap,
		321	.vmap = drm_gem_dmabuf_vmap,
		322	.vunmap = drm_gem_dmabuf_vunmap,
		323	.begin_cpu_access = panthor_gem_prime_begin_cpu_access,
		324	.end_cpu_access = panthor_gem_prime_end_cpu_access,
		325	};
		326
187	static struct dma_buf *	327	static struct dma_buf *
188	panthor_gem_prime_export(struct drm_gem_object *obj, int flags)	328	panthor_gem_prime_export(struct drm_gem_object *obj, int flags)
189	{	329	{
		330	struct drm_device *dev = obj->dev;
		331	struct dma_buf_export_info exp_info = {
		332	.exp_name = KBUILD_MODNAME,
		333	.owner = THIS_MODULE,
		334	.ops = &panthor_dma_buf_ops,
		335	.size = obj->size,
		336	.flags = flags,
		337	.priv = obj,
		338	.resv = obj->resv,
		339	};
		340
190	/* We can't export GEMs that have an exclusive VM. */	341	/* We can't export GEMs that have an exclusive VM. */
191	if (to_panthor_bo(obj)->exclusive_vm_root_gem)	342	if (to_panthor_bo(obj)->exclusive_vm_root_gem)
192	return ERR_PTR(-EINVAL);	343	return ERR_PTR(-EINVAL);
193		344
194	return drm_gem_prime_export(obj, flags);	345	return drm_gem_dmabuf_export(dev, &exp_info);
		346	}
		347
		348	struct drm_gem_object *
		349	panthor_gem_prime_import(struct drm_device *dev,
		350	struct dma_buf *dma_buf)
		351	{
		352	struct drm_gem_object *obj = dma_buf->priv;
		353
		354	if (dma_buf->ops == &panthor_dma_buf_ops && obj->dev == dev) {
		355	/* Importing dmabuf exported from our own gem increases
		356	* refcount on gem itself instead of f_count of dmabuf.
		357	*/
		358	drm_gem_object_get(obj);
		359	return obj;
		360	}
		361
		362	return drm_gem_prime_import(dev, dma_buf);
195	}	363	}
196		364
197	static enum drm_gem_object_status panthor_gem_status(struct drm_gem_object *obj)	365	static enum drm_gem_object_status panthor_gem_status(struct drm_gem_object *obj)
@@ -229,7 +397,6 @@ static const struct drm_gem_object_funcs panthor_gem_funcs = { · 31 unmodified lines
229	*/	397	*/
230	struct drm_gem_object panthor_gem_create_object(struct drm_device ddev, size_t size)	398	struct drm_gem_object panthor_gem_create_object(struct drm_device ddev, size_t size)
231	{	399	{
232	struct panthor_device *ptdev = container_of(ddev, struct panthor_device, base);
233	struct panthor_gem_object *obj;	400	struct panthor_gem_object *obj;
234		401
235	obj = kzalloc(sizeof(*obj), GFP_KERNEL);	402	obj = kzalloc(sizeof(*obj), GFP_KERNEL);
@@ -237,7 +404,6 @@ struct drm_gem_object panthor_gem_create_object(struct drm_device ddev, size_t · 1 unmodified line
237	return ERR_PTR(-ENOMEM);	404	return ERR_PTR(-ENOMEM);
238		405
239	obj->base.base.funcs = &panthor_gem_funcs;	406	obj->base.base.funcs = &panthor_gem_funcs;
240	obj->base.map_wc = !ptdev->coherent;
241	mutex_init(&obj->label.lock);	407	mutex_init(&obj->label.lock);
242		408
243	panthor_gem_debugfs_bo_init(obj);	409	panthor_gem_debugfs_bo_init(obj);
@@ -272,6 +438,7 @@ panthor_gem_create_with_handle(struct drm_file *file, · 28 unmodified lines
272		438
273	bo = to_panthor_bo(&shmem->base);	439	bo = to_panthor_bo(&shmem->base);
274	bo->flags = flags;	440	bo->flags = flags;
		441	bo->base.map_wc = should_map_wc(bo, exclusive_vm);
275		442
276	if (exclusive_vm) {	443	if (exclusive_vm) {
277	bo->exclusive_vm_root_gem = panthor_vm_root_gem(exclusive_vm);	444	bo->exclusive_vm_root_gem = panthor_vm_root_gem(exclusive_vm);
@@ -349,6 +516,91 @@ panthor_gem_kernel_bo_set_label(struct panthor_kernel_bo bo, const char label) · 71 unmodified lines
349	panthor_gem_bo_set_label(bo->obj, str);	516	panthor_gem_bo_set_label(bo->obj, str);
350	}	517	}
351		518
		519	int
		520	panthor_gem_sync(struct drm_gem_object *obj, u32 type,
		521	u64 offset, u64 size)
		522	{
		523	struct panthor_gem_object *bo = to_panthor_bo(obj);
		524	struct drm_gem_shmem_object *shmem = &bo->base;
		525	const struct drm_device *dev = shmem->base.dev;
		526	struct sg_table *sgt;
		527	struct scatterlist *sgl;
		528	unsigned int count;
		529
		530	/* Make sure the range is in bounds. */
		531	if (offset + size < offset \|\| offset + size > shmem->base.size)
		532	return -EINVAL;
		533
		534	/* Disallow CPU-cache maintenance on imported buffers. */
		535	if (drm_gem_is_imported(&shmem->base))
		536	return -EINVAL;
		537
		538	switch (type) {
		539	case DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH:
		540	case DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE:
		541	break;
		542
		543	default:
		544	return -EINVAL;
		545	}
		546
		547	/* Don't bother if it's WC-mapped */
		548	if (shmem->map_wc)
		549	return 0;
		550
		551	/* Nothing to do if the size is zero. */
		552	if (size == 0)
		553	return 0;
		554
		555	sgt = drm_gem_shmem_get_pages_sgt(shmem);
		556	if (IS_ERR(sgt))
		557	return PTR_ERR(sgt);
		558
		559	for_each_sgtable_dma_sg(sgt, sgl, count) {
		560	if (size == 0)
		561	break;
		562
		563	dma_addr_t paddr = sg_dma_address(sgl);
		564	size_t len = sg_dma_len(sgl);
		565
		566	if (len <= offset) {
		567	offset -= len;
		568	continue;
		569	}
		570
		571	paddr += offset;
		572	len -= offset;
		573	len = min_t(size_t, len, size);
		574	size -= len;
		575	offset = 0;
		576
		577	/* It's unclear whether dma_sync_xxx() is the right API to do CPU
		578	* cache maintenance given an IOMMU can register their own
		579	* implementation doing more than just CPU cache flushes/invalidation,
		580	* and what we really care about here is CPU caches only, but that's
		581	* the best we have that is both arch-agnostic and does at least the
		582	* CPU cache maintenance on a <page,offset,size> tuple.
		583	*
		584	* Also, I wish we could do a single
		585	*
		586	* dma_sync_single_for_device(BIDIR)
		587	*
		588	* and get a flush+invalidate, but that's not how it's implemented
		589	* in practice (at least on arm64), so we have to make it
		590	*
		591	* dma_sync_single_for_device(TO_DEVICE)
		592	* dma_sync_single_for_cpu(FROM_DEVICE)
		593	*
		594	* for the flush+invalidate case.
		595	*/
		596	dma_sync_single_for_device(dev->dev, paddr, len, DMA_TO_DEVICE);
		597	if (type == DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE)
		598	dma_sync_single_for_cpu(dev->dev, paddr, len, DMA_FROM_DEVICE);
		599	}
		600
		601	return 0;
		602	}
		603
352	#ifdef CONFIG_DEBUG_FS	604	#ifdef CONFIG_DEBUG_FS
353	struct gem_size_totals {	605	struct gem_size_totals {
354	size_t size;	606	size_t size;

drivers/gpu/drm/panthor/panthor_gem.h+8−0

 	return container_of(to_drm_gem_shmem_obj(obj), struct panthor_gem_object, base);
 }
+void panthor_gem_init(struct panthor_device *ptdev);
 struct drm_gem_object *panthor_gem_create_object(struct drm_device *ddev, size_t size);
 int
 void panthor_gem_bo_set_label(struct drm_gem_object *obj, const char *label);
 void panthor_gem_kernel_bo_set_label(struct panthor_kernel_bo *bo, const char *label);
+int panthor_gem_sync(struct drm_gem_object *obj,
+		     u32 type, u64 offset, u64 size);
+struct drm_gem_object *
+panthor_gem_prime_import(struct drm_device *dev,
+			 struct dma_buf *dma_buf);
 static inline u64
 panthor_kernel_bo_gpuva(struct panthor_kernel_bo *bo)

drivers/gpu/drm/panthor/panthor_gpu.c+13−8

 static void panthor_gpu_coherency_set(struct panthor_device *ptdev)
 {
 	gpu_write(ptdev, GPU_COHERENCY_PROTOCOL,
-		ptdev->coherent ? GPU_COHERENCY_PROT_BIT(ACE_LITE) : GPU_COHERENCY_NONE);
+		  ptdev->gpu_info.selected_coherency);
 }
 static void panthor_gpu_l2_config_set(struct panthor_device *ptdev)
 int panthor_gpu_flush_caches(struct panthor_device *ptdev,
 			     u32 l2, u32 lsc, u32 other)
 {
-	bool timedout = false;
 	unsigned long flags;
+	int ret = 0;
 	/* Serialize cache flush operations. */
 	guard(mutex)(&ptdev->gpu->cache_flush_lock);
 	spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
-	if (!drm_WARN_ON(&ptdev->base,
+	if (!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) {
-			 ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) {
 		ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED;
 		gpu_write(ptdev, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other));
+	} else {
+		ret = -EIO;
 	}
 	spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
+	if (ret)
+		return ret;
 	if (!wait_event_timeout(ptdev->gpu->reqs_acked,
 				!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED),
 				msecs_to_jiffies(100))) {
 		spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
 		if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 &&
 		    !(gpu_read(ptdev, GPU_INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
-			timedout = true;
+			ret = -ETIMEDOUT;
 		else
 			ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED;
 		spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
 	}
-	if (timedout) {
+	if (ret) {
+		panthor_device_schedule_reset(ptdev);
 		drm_err(&ptdev->base, "Flush caches timeout");
-		return -ETIMEDOUT;
 	}
-	return 0;
+	return ret;
 }
 /**
 		return -ETIMEDOUT;
 	}
+	ptdev->gpu->pending_reqs = 0;
 	return 0;
 }

drivers/gpu/drm/panthor/panthor_mmu.c+183−131

 	 * flagged as faulty as a result.
 	 */
 	bool unhandled_fault;
+	/** @locked_region: Information about the currently locked region currently. */
+	struct {
+		/** @locked_region.start: Start of the locked region. */
+		u64 start;
+		/** @locked_region.size: Size of the locked region. */
+		u64 size;
+	} locked_region;
 };
 /**
 	return ret;
 }
-static int write_cmd(struct panthor_device *ptdev, u32 as_nr, u32 cmd)
+static int as_send_cmd_and_wait(struct panthor_device *ptdev, u32 as_nr, u32 cmd)
 {
 	int status;
 	/* write AS_COMMAND when MMU is ready to accept another command */
 	status = wait_ready(ptdev, as_nr);
-	if (!status)
+	if (!status) {
 		gpu_write(ptdev, AS_COMMAND(as_nr), cmd);
+		status = wait_ready(ptdev, as_nr);
+	}
 	return status;
 }
-static void lock_region(struct panthor_device *ptdev, u32 as_nr,
+static u64 pack_region_range(struct panthor_device *ptdev, u64 region_start, u64 size)
-			u64 region_start, u64 size)
 {
 	u8 region_width;
-	u64 region;
 	u64 region_end = region_start + size;
-	if (!size)
+	if (drm_WARN_ON_ONCE(&ptdev->base, !size))
-		return;
+		return 0;
 	/*
 	 * The locked region is a naturally aligned power of 2 block encoded as
 	 */
 	region_start &= GENMASK_ULL(63, region_width);
-	region = region_width | region_start;
+	return region_width | region_start;
-	/* Lock the region that needs to be updated */
-	gpu_write64(ptdev, AS_LOCKADDR(as_nr), region);
-	write_cmd(ptdev, as_nr, AS_COMMAND_LOCK);
-}
-static int mmu_hw_do_operation_locked(struct panthor_device *ptdev, int as_nr,
-				      u64 iova, u64 size, u32 op)
-{
-	const u32 l2_flush_op = CACHE_CLEAN | CACHE_INV;
-	u32 lsc_flush_op;
-	int ret;
-	lockdep_assert_held(&ptdev->mmu->as.slots_lock);
-	switch (op) {
-	case AS_COMMAND_FLUSH_MEM:
-		lsc_flush_op = CACHE_CLEAN | CACHE_INV;
-		break;
-	case AS_COMMAND_FLUSH_PT:
-		lsc_flush_op = 0;
-		break;
-	default:
-		drm_WARN(&ptdev->base, 1, "Unexpected AS_COMMAND: %d", op);
-		return -EINVAL;
-	}
-	if (as_nr < 0)
-		return 0;
-	/*
-	 * If the AS number is greater than zero, then we can be sure
-	 * the device is up and running, so we don't need to explicitly
-	 * power it up
-	 */
-	lock_region(ptdev, as_nr, iova, size);
-	ret = wait_ready(ptdev, as_nr);
-	if (ret)
-		return ret;
-	ret = panthor_gpu_flush_caches(ptdev, l2_flush_op, lsc_flush_op, 0);
-	if (ret)
-		return ret;
-	/*
-	 * Explicitly unlock the region as the AS is not unlocked automatically
-	 * at the end of the GPU_CONTROL cache flush command, unlike
-	 * AS_COMMAND_FLUSH_MEM or AS_COMMAND_FLUSH_PT.
-	 */
-	write_cmd(ptdev, as_nr, AS_COMMAND_UNLOCK);
-	/* Wait for the unlock command to complete */
-	return wait_ready(ptdev, as_nr);
-}
-static int mmu_hw_do_operation(struct panthor_vm *vm,
-			       u64 iova, u64 size, u32 op)
-{
-	struct panthor_device *ptdev = vm->ptdev;
-	int ret;
-	mutex_lock(&ptdev->mmu->as.slots_lock);
-	ret = mmu_hw_do_operation_locked(ptdev, vm->as.id, iova, size, op);
-	mutex_unlock(&ptdev->mmu->as.slots_lock);
-	return ret;
 }
 static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr,
 				 u64 transtab, u64 transcfg, u64 memattr)
 {
-	int ret;
-	ret = mmu_hw_do_operation_locked(ptdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
-	if (ret)
-		return ret;
 	gpu_write64(ptdev, AS_TRANSTAB(as_nr), transtab);
 	gpu_write64(ptdev, AS_MEMATTR(as_nr), memattr);
 	gpu_write64(ptdev, AS_TRANSCFG(as_nr), transcfg);
-	return write_cmd(ptdev, as_nr, AS_COMMAND_UPDATE);
+	return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
 }
-static int panthor_mmu_as_disable(struct panthor_device *ptdev, u32 as_nr)
+static int panthor_mmu_as_disable(struct panthor_device *ptdev, u32 as_nr,
+				  bool recycle_slot)
 {
+	struct panthor_vm *vm = ptdev->mmu->as.slots[as_nr].vm;
 	int ret;
-	ret = mmu_hw_do_operation_locked(ptdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
+	lockdep_assert_held(&ptdev->mmu->as.slots_lock);
+	/* Flush+invalidate RW caches, invalidate RO ones. */
+	ret = panthor_gpu_flush_caches(ptdev, CACHE_CLEAN | CACHE_INV,
+				       CACHE_CLEAN | CACHE_INV, CACHE_INV);
 	if (ret)
 		return ret;
+	if (vm && vm->locked_region.size) {
+		/* Unlock the region if there's a lock pending. */
+		ret = as_send_cmd_and_wait(ptdev, vm->as.id, AS_COMMAND_UNLOCK);
+		if (ret)
+			return ret;
+	}
+	/* If the slot is going to be used immediately, don't bother changing
+	 * the config.
+	 */
+	if (recycle_slot)
+		return 0;
 	gpu_write64(ptdev, AS_TRANSTAB(as_nr), 0);
 	gpu_write64(ptdev, AS_MEMATTR(as_nr), 0);
 	gpu_write64(ptdev, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED);
-	return write_cmd(ptdev, as_nr, AS_COMMAND_UPDATE);
+	return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
 }
 static u32 panthor_mmu_fault_mask(struct panthor_device *ptdev, u32 value)
 	if (refcount_inc_not_zero(&vm->as.active_cnt))
 		goto out_dev_exit;
+	/* Make sure we don't race with lock/unlock_region() calls
+	 * happening around VM bind operations.
+	 */
+	mutex_lock(&vm->op_lock);
 	mutex_lock(&ptdev->mmu->as.slots_lock);
 	if (refcount_inc_not_zero(&vm->as.active_cnt))
 		drm_WARN_ON(&ptdev->base, refcount_read(&lru_vm->as.active_cnt));
 		as = lru_vm->as.id;
+		ret = panthor_mmu_as_disable(ptdev, as, true);
+		if (ret)
+			goto out_unlock;
 		panthor_vm_release_as_locked(lru_vm);
 	}
 		gpu_write(ptdev, MMU_INT_MASK, ~ptdev->mmu->as.faulty_mask);
 	}
+	/* The VM update is guarded by ::op_lock, which we take at the beginning
+	 * of this function, so we don't expect any locked region here.
+	 */
+	drm_WARN_ON(&vm->ptdev->base, vm->locked_region.size > 0);
 	ret = panthor_mmu_as_enable(vm->ptdev, vm->as.id, transtab, transcfg, vm->memattr);
 out_make_active:
 out_unlock:
 	mutex_unlock(&ptdev->mmu->as.slots_lock);
+	mutex_unlock(&vm->op_lock);
 out_dev_exit:
 	drm_dev_exit(cookie);
 	return SZ_2M;
 }
-static int panthor_vm_flush_range(struct panthor_vm *vm, u64 iova, u64 size)
+static void panthor_vm_declare_unusable(struct panthor_vm *vm)
 {
 	struct panthor_device *ptdev = vm->ptdev;
-	int ret = 0, cookie;
+	int cookie;
-	if (vm->as.id < 0)
-		return 0;
-	/* If the device is unplugged, we just silently skip the flush. */
+	if (vm->unusable)
-	if (!drm_dev_enter(&ptdev->base, &cookie))
+		return;
-		return 0;
-	ret = mmu_hw_do_operation(vm, iova, size, AS_COMMAND_FLUSH_PT);
-	drm_dev_exit(cookie);
+	vm->unusable = true;
-	return ret;
+	mutex_lock(&ptdev->mmu->as.slots_lock);
+	if (vm->as.id >= 0 && drm_dev_enter(&ptdev->base, &cookie)) {
+		panthor_mmu_as_disable(ptdev, vm->as.id, false);
+		drm_dev_exit(cookie);
+	}
+	mutex_unlock(&ptdev->mmu->as.slots_lock);
 }
-static int panthor_vm_unmap_pages(struct panthor_vm *vm, u64 iova, u64 size)
+static void panthor_vm_unmap_pages(struct panthor_vm *vm, u64 iova, u64 size)
 {
 	struct panthor_device *ptdev = vm->ptdev;
 	struct io_pgtable_ops *ops = vm->pgtbl_ops;
 	u64 start_iova = iova;
 	u64 offset = 0;
+	if (!size)
+		return;
+	drm_WARN_ON(&ptdev->base,
+		    (iova < vm->locked_region.start) ||
+		    (iova + size > vm->locked_region.start + vm->locked_region.size));
 	while (offset < size) {
 		size_t unmapped_sz = 0, pgcount;
 		size_t pgsize = get_pgsize(iova + offset, size - offset, &pgcount);
 		unmapped_sz = ops->unmap_pages(ops, iova + offset, pgsize, pgcount, NULL);
+		if (drm_WARN_ON_ONCE(&ptdev->base, unmapped_sz != pgsize * pgcount)) {
+			/* Gracefully handle sparsely unmapped regions to avoid leaving
+			 * page table pages behind when the drm_gpuvm and VM page table
+			 * are out-of-sync. This is not supposed to happen, hence the
+			 * above WARN_ON().
+			 */
+			while (!ops->iova_to_phys(ops, iova + unmapped_sz) &&
+			       unmapped_sz < pgsize * pgcount)
+				unmapped_sz += SZ_4K;
+			/* We're passed the point where we can try to fix things,
+			 * so flag the VM unusable to make sure it's not going
+			 * to be used anymore.
+			 */
+			panthor_vm_declare_unusable(vm);
-		if (drm_WARN_ON(&ptdev->base, unmapped_sz != pgsize * pgcount)) {
+			/* If we don't make progress, we're screwed. That also means
-			drm_err(&ptdev->base, "failed to unmap range %llx-%llx (requested range %llx-%llx)\n",
+			 * something else prevents us from unmapping the region, but
-				iova + offset + unmapped_sz,
+			 * there's not much we can do here: time for debugging.
-				iova + offset + pgsize * pgcount,
+			 */
-				iova, iova + size);
+			if (drm_WARN_ON_ONCE(&ptdev->base, !unmapped_sz))
-			panthor_vm_flush_range(vm, iova, offset + unmapped_sz);
+				return;
-			return  -EINVAL;
 		}
 		drm_dbg(&ptdev->base,
 		offset += unmapped_sz;
 	}
-	return panthor_vm_flush_range(vm, iova, size);
 }
 static int
 	if (!size)
 		return 0;
+	drm_WARN_ON(&ptdev->base,
+		    (iova < vm->locked_region.start) ||
+		    (iova + size > vm->locked_region.start + vm->locked_region.size));
 	for_each_sgtable_dma_sg(sgt, sgl, count) {
 		dma_addr_t paddr = sg_dma_address(sgl);
 		size_t len = sg_dma_len(sgl);
 			paddr += mapped;
 			len -= mapped;
-			if (drm_WARN_ON(&ptdev->base, !ret && !mapped))
+			/* If nothing was mapped, consider it an ENOMEM. */
+			if (!ret && !mapped)
 				ret = -ENOMEM;
-			if (ret) {
+			/* If something fails, we stop there, and flag the VM unusable. */
-				/* If something failed, unmap what we've already mapped before
+			if (drm_WARN_ON_ONCE(&ptdev->base, ret)) {
-				 * returning. The unmap call is not supposed to fail.
+				/* Unmap what we've already mapped to avoid leaving page
+				 * table pages behind.
 				 */
-				drm_WARN_ON(&ptdev->base,
+				panthor_vm_unmap_pages(vm, start_iova, iova - start_iova);
-					    panthor_vm_unmap_pages(vm, start_iova,
+				panthor_vm_declare_unusable(vm);
-								   iova - start_iova));
 				return ret;
 			}
 		}
 		offset = 0;
 	}
-	return panthor_vm_flush_range(vm, start_iova, iova - start_iova);
+	return 0;
 }
 static int flags_to_prot(u32 flags)
 	}
 }
+static int panthor_vm_lock_region(struct panthor_vm *vm, u64 start, u64 size)
+{
+	struct panthor_device *ptdev = vm->ptdev;
+	int ret = 0;
+	mutex_lock(&ptdev->mmu->as.slots_lock);
+	drm_WARN_ON(&ptdev->base, vm->locked_region.start || vm->locked_region.size);
+	if (vm->as.id >= 0 && size) {
+		/* Lock the region that needs to be updated */
+		gpu_write64(ptdev, AS_LOCKADDR(vm->as.id),
+			    pack_region_range(ptdev, start, size));
+		/* If the lock succeeded, update the locked_region info. */
+		ret = as_send_cmd_and_wait(ptdev, vm->as.id, AS_COMMAND_LOCK);
+	}
+	if (!ret) {
+		vm->locked_region.start = start;
+		vm->locked_region.size = size;
+	}
+	mutex_unlock(&ptdev->mmu->as.slots_lock);
+	return ret;
+}
+static void panthor_vm_unlock_region(struct panthor_vm *vm)
+{
+	struct panthor_device *ptdev = vm->ptdev;
+	mutex_lock(&ptdev->mmu->as.slots_lock);
+	if (vm->as.id >= 0) {
+		int ret;
+		/* flush+invalidate RW caches and invalidate RO ones.
+		 * TODO: See if we can use FLUSH_PA_RANGE when the physical
+		 * range is narrow enough and the HW supports it.
+		 */
+		ret = panthor_gpu_flush_caches(ptdev, CACHE_CLEAN | CACHE_INV,
+					       CACHE_CLEAN | CACHE_INV,
+					       CACHE_INV);
+		/* Unlock the region if the flush is effective. */
+		if (!ret)
+			ret = as_send_cmd_and_wait(ptdev, vm->as.id, AS_COMMAND_UNLOCK);
+		/* If we fail to flush or unlock the region, schedule a GPU reset
+		 * to unblock the situation.
+		 */
+		if (ret)
+			panthor_device_schedule_reset(ptdev);
+	}
+	vm->locked_region.start = 0;
+	vm->locked_region.size = 0;
+	mutex_unlock(&ptdev->mmu->as.slots_lock);
+}
 static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
 {
 	bool has_unhandled_faults = false;
 			ptdev->mmu->as.slots[as].vm->unhandled_fault = true;
 		/* Disable the MMU to kill jobs on this AS. */
-		panthor_mmu_as_disable(ptdev, as);
+		panthor_mmu_as_disable(ptdev, as, false);
 		mutex_unlock(&ptdev->mmu->as.slots_lock);
 		status &= ~mask;
 		struct panthor_vm *vm = ptdev->mmu->as.slots[i].vm;
 		if (vm) {
-			drm_WARN_ON(&ptdev->base, panthor_mmu_as_disable(ptdev, i));
+			drm_WARN_ON(&ptdev->base,
+				    panthor_mmu_as_disable(ptdev, i, false));
 			panthor_vm_release_as_locked(vm);
 		}
 	}
 	drm_sched_entity_destroy(&vm->entity);
 	drm_sched_fini(&vm->sched);
+	mutex_lock(&vm->op_lock);
 	mutex_lock(&ptdev->mmu->as.slots_lock);
 	if (vm->as.id >= 0) {
 		int cookie;
 		if (drm_dev_enter(&ptdev->base, &cookie)) {
-			panthor_mmu_as_disable(ptdev, vm->as.id);
+			panthor_mmu_as_disable(ptdev, vm->as.id, false);
 			drm_dev_exit(cookie);
 		}
 		list_del(&vm->as.lru_node);
 	}
 	mutex_unlock(&ptdev->mmu->as.slots_lock);
+	mutex_unlock(&vm->op_lock);
 	free_io_pgtable_ops(vm->pgtbl_ops);
 	struct panthor_vm_op_ctx *op_ctx = vm->op_ctx;
 	struct panthor_vma *prev_vma = NULL, *next_vma = NULL;
 	u64 unmap_start, unmap_range;
-	int ret;
 	drm_gpuva_op_remap_to_unmap_range(&op->remap, &unmap_start, &unmap_range);
-	ret = panthor_vm_unmap_pages(vm, unmap_start, unmap_range);
+	panthor_vm_unmap_pages(vm, unmap_start, unmap_range);
-	if (ret)
-		return ret;
 	if (op->remap.prev) {
 		prev_vma = panthor_vm_op_ctx_get_vma(op_ctx);
 {
 	struct panthor_vma *unmap_vma = container_of(op->unmap.va, struct panthor_vma, base);
 	struct panthor_vm *vm = priv;
-	int ret;
-	ret = panthor_vm_unmap_pages(vm, unmap_vma->base.va.addr,
-				     unmap_vma->base.va.range);
-	if (drm_WARN_ON(&vm->ptdev->base, ret))
-		return ret;
+	panthor_vm_unmap_pages(vm, unmap_vma->base.va.addr,
+			       unmap_vma->base.va.range);
 	drm_gpuva_unmap(&op->unmap);
 	panthor_vma_unlink(unmap_vma);
 	return 0;
 	mutex_lock(&vm->op_lock);
 	vm->op_ctx = op;
+	ret = panthor_vm_lock_region(vm, op->va.addr, op->va.range);
+	if (ret)
+		goto out;
 	switch (op_type) {
 	case DRM_PANTHOR_VM_BIND_OP_TYPE_MAP: {
 		const struct drm_gpuvm_map_req map_req = {
 		break;
 	}
+	panthor_vm_unlock_region(vm);
+out:
 	if (ret && flag_vm_unusable_on_failure)
-		vm->unusable = true;
+		panthor_vm_declare_unusable(vm);
 	vm->op_ctx = NULL;
 	mutex_unlock(&vm->op_lock);
 		struct panthor_vm *vm = ptdev->mmu->as.slots[i].vm;
 		if (vm) {
-			drm_WARN_ON(&ptdev->base, panthor_mmu_as_disable(ptdev, i));
+			drm_WARN_ON(&ptdev->base,
+				    panthor_mmu_as_disable(ptdev, i, false));
 			panthor_vm_release_as_locked(vm);
 		}
 	}

drivers/gpu/drm/panthor/panthor_sched.c+129−121

@@ -108,15 +108,6 @@ struct panthor_csg_slot { · 107 unmodified lines
108		108
109	/** @priority: Group priority. */	109	/** @priority: Group priority. */
110	u8 priority;	110	u8 priority;
111
112	/**
113	* @idle: True if the group bound to this slot is idle.
114	*
115	* A group is idle when it has nothing waiting for execution on
116	* all its queues, or when queues are blocked waiting for something
117	* to happen (synchronization object).
118	*/
119	bool idle;
120	};	111	};
121		112
122	/**	113	/**
@@ -878,8 +869,11 @@ panthor_queue_get_syncwait_obj(struct panthor_group *group, struct panthor_queue · 755 unmodified lines
878	struct iosys_map map;	869	struct iosys_map map;
879	int ret;	870	int ret;
880		871
881	if (queue->syncwait.kmap)	872	if (queue->syncwait.kmap) {
882	return queue->syncwait.kmap + queue->syncwait.offset;	873	bo = container_of(queue->syncwait.obj,
		874	struct panthor_gem_object, base.base);
		875	goto out_sync;
		876	}
883		877
884	bo = panthor_vm_get_bo_for_va(group->vm,	878	bo = panthor_vm_get_bo_for_va(group->vm,
885	queue->syncwait.gpu_va,	879	queue->syncwait.gpu_va,
@@ -896,6 +890,17 @@ panthor_queue_get_syncwait_obj(struct panthor_group *group, struct panthor_queue · 10 unmodified lines
896	if (drm_WARN_ON(&ptdev->base, !queue->syncwait.kmap))	890	if (drm_WARN_ON(&ptdev->base, !queue->syncwait.kmap))
897	goto err_put_syncwait_obj;	891	goto err_put_syncwait_obj;
898		892
		893	out_sync:
		894	/* Make sure the CPU caches are invalidated before the seqno is read.
		895	* drm_gem_shmem_sync() is a NOP if map_wc=true, so no need to check
		896	* it here.
		897	*/
		898	panthor_gem_sync(&bo->base.base, queue->syncwait.offset,
		899	queue->syncwait.sync64 ?
		900	sizeof(struct panthor_syncobj_64b) :
		901	sizeof(struct panthor_syncobj_32b),
		902	DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE);
		903
899	return queue->syncwait.kmap + queue->syncwait.offset;	904	return queue->syncwait.kmap + queue->syncwait.offset;
900		905
901	err_put_syncwait_obj:	906	err_put_syncwait_obj:
@@ -908,9 +913,8 @@ static void group_free_queue(struct panthor_group group, struct panthor_queue · 6 unmodified lines
908	if (IS_ERR_OR_NULL(queue))	913	if (IS_ERR_OR_NULL(queue))
909	return;	914	return;
910		915
911	/* This should have been disabled before that point. */	916	/* Disable the timeout before tearing down drm_sched components. */
912	drm_WARN_ON(&group->ptdev->base,	917	disable_delayed_work_sync(&queue->timeout.work);
913	disable_delayed_work_sync(&queue->timeout.work));
914		918
915	if (queue->entity.fence_context)	919	if (queue->entity.fence_context)
916	drm_sched_entity_destroy(&queue->entity);	920	drm_sched_entity_destroy(&queue->entity);
@@ -1062,28 +1066,11 @@ group_unbind_locked(struct panthor_group *group) · 145 unmodified lines
1062	static bool	1066	static bool
1063	group_is_idle(struct panthor_group *group)	1067	group_is_idle(struct panthor_group *group)
1064	{	1068	{
1065	struct panthor_device *ptdev = group->ptdev;	1069	u32 inactive_queues = group->idle_queues \| group->blocked_queues;
1066	u32 inactive_queues;
1067
1068	if (group->csg_id >= 0)
1069	return ptdev->scheduler->csg_slots[group->csg_id].idle;
1070		1070
1071	inactive_queues = group->idle_queues \| group->blocked_queues;
1072	return hweight32(inactive_queues) == group->queue_count;	1071	return hweight32(inactive_queues) == group->queue_count;
1073	}	1072	}
1074		1073
1075	static void
1076	queue_reset_timeout_locked(struct panthor_queue *queue)
1077	{
1078	lockdep_assert_held(&queue->fence_ctx.lock);
1079
1080	if (queue->timeout.remaining != MAX_SCHEDULE_TIMEOUT) {
1081	mod_delayed_work(queue->scheduler.timeout_wq,
1082	&queue->timeout.work,
1083	msecs_to_jiffies(JOB_TIMEOUT_MS));
1084	}
1085	}
1086
1087	static bool	1074	static bool
1088	group_can_run(struct panthor_group *group)	1075	group_can_run(struct panthor_group *group)
1089	{	1076	{
@@ -1100,6 +1087,18 @@ queue_timeout_is_suspended(struct panthor_queue *queue) · 10 unmodified lines
1100	return queue->timeout.remaining != MAX_SCHEDULE_TIMEOUT;	1087	return queue->timeout.remaining != MAX_SCHEDULE_TIMEOUT;
1101	}	1088	}
1102		1089
		1090	static void
		1091	queue_reset_timeout_locked(struct panthor_queue *queue)
		1092	{
		1093	lockdep_assert_held(&queue->fence_ctx.lock);
		1094
		1095	if (!queue_timeout_is_suspended(queue)) {
		1096	mod_delayed_work(queue->scheduler.timeout_wq,
		1097	&queue->timeout.work,
		1098	msecs_to_jiffies(JOB_TIMEOUT_MS));
		1099	}
		1100	}
		1101
1103	static void	1102	static void
1104	queue_suspend_timeout_locked(struct panthor_queue *queue)	1103	queue_suspend_timeout_locked(struct panthor_queue *queue)
1105	{	1104	{
@@ -1200,12 +1199,10 @@ cs_slot_prog_locked(struct panthor_device *ptdev, u32 csg_id, u32 cs_id) · 94 unmodified lines
1200	panthor_fw_update_reqs(cs_iface, req,	1199	panthor_fw_update_reqs(cs_iface, req,
1201	CS_IDLE_SYNC_WAIT \|	1200	CS_IDLE_SYNC_WAIT \|
1202	CS_IDLE_EMPTY \|	1201	CS_IDLE_EMPTY \|
1203	CS_STATE_START \|	1202	CS_STATE_START,
1204	CS_EXTRACT_EVENT,
1205	CS_IDLE_SYNC_WAIT \|	1203	CS_IDLE_SYNC_WAIT \|
1206	CS_IDLE_EMPTY \|	1204	CS_IDLE_EMPTY \|
1207	CS_STATE_MASK \|	1205	CS_STATE_MASK);
1208	CS_EXTRACT_EVENT);
1209	if (queue->iface.input->insert != queue->iface.input->extract)	1206	if (queue->iface.input->insert != queue->iface.input->extract)
1210	queue_resume_timeout(queue);	1207	queue_resume_timeout(queue);
1211	}	1208	}
@@ -1725,17 +1722,6 @@ static bool cs_slot_process_irq_locked(struct panthor_device *ptdev, · 513 unmodified lines
1725	return (events & (CS_FAULT \| CS_TILER_OOM)) != 0;	1722	return (events & (CS_FAULT \| CS_TILER_OOM)) != 0;
1726	}	1723	}
1727		1724
1728	static void csg_slot_sync_idle_state_locked(struct panthor_device *ptdev, u32 csg_id)
1729	{
1730	struct panthor_csg_slot *csg_slot = &ptdev->scheduler->csg_slots[csg_id];
1731	struct panthor_fw_csg_iface *csg_iface;
1732
1733	lockdep_assert_held(&ptdev->scheduler->lock);
1734
1735	csg_iface = panthor_fw_get_csg_iface(ptdev, csg_id);
1736	csg_slot->idle = csg_iface->output->status_state & CSG_STATUS_STATE_IS_IDLE;
1737	}
1738
1739	static void csg_slot_process_idle_event_locked(struct panthor_device *ptdev, u32 csg_id)	1725	static void csg_slot_process_idle_event_locked(struct panthor_device *ptdev, u32 csg_id)
1740	{	1726	{
1741	struct panthor_scheduler *sched = ptdev->scheduler;	1727	struct panthor_scheduler *sched = ptdev->scheduler;
@@ -1997,10 +1983,8 @@ static int csgs_upd_ctx_apply_locked(struct panthor_device *ptdev, · 255 unmodified lines
1997	if (acked & CSG_STATE_MASK)	1983	if (acked & CSG_STATE_MASK)
1998	csg_slot_sync_state_locked(ptdev, csg_id);	1984	csg_slot_sync_state_locked(ptdev, csg_id);
1999		1985
2000	if (acked & CSG_STATUS_UPDATE) {	1986	if (acked & CSG_STATUS_UPDATE)
2001	csg_slot_sync_queues_state_locked(ptdev, csg_id);	1987	csg_slot_sync_queues_state_locked(ptdev, csg_id);
2002	csg_slot_sync_idle_state_locked(ptdev, csg_id);
2003	}
2004		1988
2005	if (ret && acked != req_mask &&	1989	if (ret && acked != req_mask &&
2006	((csg_iface->input->req ^ csg_iface->output->ack) & req_mask) != 0) {	1990	((csg_iface->input->req ^ csg_iface->output->ack) & req_mask) != 0) {
@@ -2020,10 +2004,10 @@ struct panthor_sched_tick_ctx { · 13 unmodified lines
2020	struct list_head groups[PANTHOR_CSG_PRIORITY_COUNT];	2004	struct list_head groups[PANTHOR_CSG_PRIORITY_COUNT];
2021	u32 idle_group_count;	2005	u32 idle_group_count;
2022	u32 group_count;	2006	u32 group_count;
2023	enum panthor_csg_priority min_priority;
2024	struct panthor_vm *vms[MAX_CS_PER_CSG];	2007	struct panthor_vm *vms[MAX_CS_PER_CSG];
2025	u32 as_count;	2008	u32 as_count;
2026	bool immediate_tick;	2009	bool immediate_tick;
		2010	bool stop_tick;
2027	u32 csg_upd_failed_mask;	2011	u32 csg_upd_failed_mask;
2028	};	2012	};
2029		2013
@@ -2066,17 +2050,21 @@ tick_ctx_pick_groups_from_list(const struct panthor_scheduler *sched, · 36 unmodified lines
2066	if (!owned_by_tick_ctx)	2050	if (!owned_by_tick_ctx)
2067	group_get(group);	2051	group_get(group);
2068		2052
2069	list_move_tail(&group->run_node, &ctx->groups[group->priority]);
2070	ctx->group_count++;	2053	ctx->group_count++;
		2054
		2055	/* If we have more than one active group with the same priority,
		2056	* we need to keep ticking to rotate the CSG priority.
		2057	*/
2071	if (group_is_idle(group))	2058	if (group_is_idle(group))
2072	ctx->idle_group_count++;	2059	ctx->idle_group_count++;
		2060	else if (!list_empty(&ctx->groups[group->priority]))
		2061	ctx->stop_tick = false;
		2062
		2063	list_move_tail(&group->run_node, &ctx->groups[group->priority]);
2073		2064
2074	if (i == ctx->as_count)	2065	if (i == ctx->as_count)
2075	ctx->vms[ctx->as_count++] = group->vm;	2066	ctx->vms[ctx->as_count++] = group->vm;
2076		2067
2077	if (ctx->min_priority > group->priority)
2078	ctx->min_priority = group->priority;
2079
2080	if (tick_ctx_is_full(sched, ctx))	2068	if (tick_ctx_is_full(sched, ctx))
2081	return;	2069	return;
2082	}	2070	}
@@ -2085,31 +2073,22 @@ tick_ctx_pick_groups_from_list(const struct panthor_scheduler *sched, · 2 unmodified lines
2085	static void	2073	static void
2086	tick_ctx_insert_old_group(struct panthor_scheduler *sched,	2074	tick_ctx_insert_old_group(struct panthor_scheduler *sched,
2087	struct panthor_sched_tick_ctx *ctx,	2075	struct panthor_sched_tick_ctx *ctx,
2088	struct panthor_group *group,	2076	struct panthor_group *group)
2089	bool full_tick)
2090	{	2077	{
2091	struct panthor_csg_slot *csg_slot = &sched->csg_slots[group->csg_id];	2078	struct panthor_csg_slot *csg_slot = &sched->csg_slots[group->csg_id];
2092	struct panthor_group *other_group;	2079	struct panthor_group *other_group;
2093		2080
2094	if (!full_tick) {	2081	/* Class groups in descending priority order so we can easily rotate. */
2095	list_add_tail(&group->run_node, &ctx->old_groups[group->priority]);
2096	return;
2097	}
2098
2099	/* Rotate to make sure groups with lower CSG slot
2100	* priorities have a chance to get a higher CSG slot
2101	* priority next time they get picked. This priority
2102	* has an impact on resource request ordering, so it's
2103	* important to make sure we don't let one group starve
2104	* all other groups with the same group priority.
2105	*/
2106	list_for_each_entry(other_group,	2082	list_for_each_entry(other_group,
2107	&ctx->old_groups[csg_slot->group->priority],	2083	&ctx->old_groups[csg_slot->group->priority],
2108	run_node) {	2084	run_node) {
2109	struct panthor_csg_slot *other_csg_slot = &sched->csg_slots[other_group->csg_id];	2085	struct panthor_csg_slot *other_csg_slot = &sched->csg_slots[other_group->csg_id];
2110		2086
2111	if (other_csg_slot->priority > csg_slot->priority) {	2087	/* Our group has a higher prio than the one we're testing against,
2112	list_add_tail(&csg_slot->group->run_node, &other_group->run_node);	2088	* place it just before.
		2089	*/
		2090	if (csg_slot->priority > other_csg_slot->priority) {
		2091	list_add_tail(&group->run_node, &other_group->run_node);
2113	return;	2092	return;
2114	}	2093	}
2115	}	2094	}
@@ -2119,8 +2098,7 @@ tick_ctx_insert_old_group(struct panthor_scheduler *sched, · 3 unmodified lines
2119		2098
2120	static void	2099	static void
2121	tick_ctx_init(struct panthor_scheduler *sched,	2100	tick_ctx_init(struct panthor_scheduler *sched,
2122	struct panthor_sched_tick_ctx *ctx,	2101	struct panthor_sched_tick_ctx *ctx)
2123	bool full_tick)
2124	{	2102	{
2125	struct panthor_device *ptdev = sched->ptdev;	2103	struct panthor_device *ptdev = sched->ptdev;
2126	struct panthor_csg_slots_upd_ctx upd_ctx;	2104	struct panthor_csg_slots_upd_ctx upd_ctx;
@@ -2130,7 +2108,7 @@ tick_ctx_init(struct panthor_scheduler *sched, · 3 unmodified lines
2130	memset(ctx, 0, sizeof(*ctx));	2108	memset(ctx, 0, sizeof(*ctx));
2131	csgs_upd_ctx_init(&upd_ctx);	2109	csgs_upd_ctx_init(&upd_ctx);
2132		2110
2133	ctx->min_priority = PANTHOR_CSG_PRIORITY_COUNT;	2111	ctx->stop_tick = true;
2134	for (i = 0; i < ARRAY_SIZE(ctx->groups); i++) {	2112	for (i = 0; i < ARRAY_SIZE(ctx->groups); i++) {
2135	INIT_LIST_HEAD(&ctx->groups[i]);	2113	INIT_LIST_HEAD(&ctx->groups[i]);
2136	INIT_LIST_HEAD(&ctx->old_groups[i]);	2114	INIT_LIST_HEAD(&ctx->old_groups[i]);
@@ -2158,7 +2136,7 @@ tick_ctx_init(struct panthor_scheduler *sched, · 21 unmodified lines
2158	group->fatal_queues \|= GENMASK(group->queue_count - 1, 0);	2136	group->fatal_queues \|= GENMASK(group->queue_count - 1, 0);
2159	}	2137	}
2160		2138
2161	tick_ctx_insert_old_group(sched, ctx, group, full_tick);	2139	tick_ctx_insert_old_group(sched, ctx, group);
2162	csgs_upd_ctx_queue_reqs(ptdev, &upd_ctx, i,	2140	csgs_upd_ctx_queue_reqs(ptdev, &upd_ctx, i,
2163	csg_iface->output->ack ^ CSG_STATUS_UPDATE,	2141	csg_iface->output->ack ^ CSG_STATUS_UPDATE,
2164	CSG_STATUS_UPDATE);	2142	CSG_STATUS_UPDATE);
@@ -2442,32 +2420,18 @@ static u64 · 277 unmodified lines
2442	tick_ctx_update_resched_target(struct panthor_scheduler *sched,	2420	tick_ctx_update_resched_target(struct panthor_scheduler *sched,
2443	const struct panthor_sched_tick_ctx *ctx)	2421	const struct panthor_sched_tick_ctx *ctx)
2444	{	2422	{
2445	/* We had space left, no need to reschedule until some external event happens. */	2423	u64 resched_target;
2446	if (!tick_ctx_is_full(sched, ctx))
2447	goto no_tick;
2448
2449	/* If idle groups were scheduled, no need to wake up until some external
2450	* event happens (group unblocked, new job submitted, ...).
2451	*/
2452	if (ctx->idle_group_count)
2453	goto no_tick;
2454		2424
2455	if (drm_WARN_ON(&sched->ptdev->base, ctx->min_priority >= PANTHOR_CSG_PRIORITY_COUNT))	2425	if (ctx->stop_tick)
2456	goto no_tick;	2426	goto no_tick;
2457		2427
2458	/* If there are groups of the same priority waiting, we need to	2428	resched_target = sched->last_tick + sched->tick_period;
2459	* keep the scheduler ticking, otherwise, we'll just wait for
2460	* new groups with higher priority to be queued.
2461	*/
2462	if (!list_empty(&sched->groups.runnable[ctx->min_priority])) {
2463	u64 resched_target = sched->last_tick + sched->tick_period;
2464		2429
2465	if (time_before64(sched->resched_target, sched->last_tick) \|\|	2430	if (time_before64(sched->resched_target, sched->last_tick) \|\|
2466	time_before64(resched_target, sched->resched_target))	2431	time_before64(resched_target, sched->resched_target))
2467	sched->resched_target = resched_target;	2432	sched->resched_target = resched_target;
2468		2433
2469	return sched->resched_target - sched->last_tick;	2434	return sched->resched_target - sched->last_tick;
2470	}
2471		2435
2472	no_tick:	2436	no_tick:
2473	sched->resched_target = U64_MAX;	2437	sched->resched_target = U64_MAX;
@@ -2480,9 +2444,11 @@ static void tick_work(struct work_struct *work) · 6 unmodified lines
2480	tick_work.work);	2444	tick_work.work);
2481	struct panthor_device *ptdev = sched->ptdev;	2445	struct panthor_device *ptdev = sched->ptdev;
2482	struct panthor_sched_tick_ctx ctx;	2446	struct panthor_sched_tick_ctx ctx;
		2447	u64 resched_target = sched->resched_target;
2483	u64 remaining_jiffies = 0, resched_delay;	2448	u64 remaining_jiffies = 0, resched_delay;
2484	u64 now = get_jiffies_64();	2449	u64 now = get_jiffies_64();
2485	int prio, ret, cookie;	2450	int prio, ret, cookie;
		2451	bool full_tick;
2486		2452
2487	if (!drm_dev_enter(&ptdev->base, &cookie))	2453	if (!drm_dev_enter(&ptdev->base, &cookie))
2488	return;	2454	return;
@@ -2491,18 +2457,24 @@ static void tick_work(struct work_struct *work) · 2 unmodified lines
2491	if (drm_WARN_ON(&ptdev->base, ret))	2457	if (drm_WARN_ON(&ptdev->base, ret))
2492	goto out_dev_exit;	2458	goto out_dev_exit;
2493		2459
2494	if (time_before64(now, sched->resched_target))	2460	/* If the tick is stopped, calculate when the next tick would be */
2495	remaining_jiffies = sched->resched_target - now;	2461	if (resched_target == U64_MAX)
		2462	resched_target = sched->last_tick + sched->tick_period;
		2463
		2464	if (time_before64(now, resched_target))
		2465	remaining_jiffies = resched_target - now;
		2466
		2467	full_tick = remaining_jiffies == 0;
2496		2468
2497	mutex_lock(&sched->lock);	2469	mutex_lock(&sched->lock);
2498	if (panthor_device_reset_is_pending(sched->ptdev))	2470	if (panthor_device_reset_is_pending(sched->ptdev))
2499	goto out_unlock;	2471	goto out_unlock;
2500		2472
2501	tick_ctx_init(sched, &ctx, remaining_jiffies != 0);	2473	tick_ctx_init(sched, &ctx);
2502	if (ctx.csg_upd_failed_mask)	2474	if (ctx.csg_upd_failed_mask)
2503	goto out_cleanup_ctx;	2475	goto out_cleanup_ctx;
2504		2476
2505	if (remaining_jiffies) {	2477	if (!full_tick) {
2506	/* Scheduling forced in the middle of a tick. Only RT groups	2478	/* Scheduling forced in the middle of a tick. Only RT groups
2507	* can preempt non-RT ones. Currently running RT groups can't be	2479	* can preempt non-RT ones. Currently running RT groups can't be
2508	* preempted.	2480	* preempted.
@@ -2524,9 +2496,29 @@ static void tick_work(struct work_struct *work) · 15 unmodified lines
2524	for (prio = PANTHOR_CSG_PRIORITY_COUNT - 1;	2496	for (prio = PANTHOR_CSG_PRIORITY_COUNT - 1;
2525	prio >= 0 && !tick_ctx_is_full(sched, &ctx);	2497	prio >= 0 && !tick_ctx_is_full(sched, &ctx);
2526	prio--) {	2498	prio--) {
		2499	struct panthor_group *old_highest_prio_group =
		2500	list_first_entry_or_null(&ctx.old_groups[prio],
		2501	struct panthor_group, run_node);
		2502
		2503	/* Pull out the group with the highest prio for rotation. */
		2504	if (old_highest_prio_group)
		2505	list_del(&old_highest_prio_group->run_node);
		2506
		2507	/* Re-insert old active groups so they get a chance to run with higher prio. */
		2508	tick_ctx_pick_groups_from_list(sched, &ctx, &ctx.old_groups[prio], true, true);
		2509
		2510	/* Fill the remaining slots with runnable groups. */
2527	tick_ctx_pick_groups_from_list(sched, &ctx, &sched->groups.runnable[prio],	2511	tick_ctx_pick_groups_from_list(sched, &ctx, &sched->groups.runnable[prio],
2528	true, false);	2512	true, false);
2529	tick_ctx_pick_groups_from_list(sched, &ctx, &ctx.old_groups[prio], true, true);	2513
		2514	/* Re-insert the old group with the highest prio, and give it a chance to be
		2515	* scheduled again (but with a lower prio) if there's room left.
		2516	*/
		2517	if (old_highest_prio_group) {
		2518	list_add_tail(&old_highest_prio_group->run_node, &ctx.old_groups[prio]);
		2519	tick_ctx_pick_groups_from_list(sched, &ctx, &ctx.old_groups[prio],
		2520	true, true);
		2521	}
2530	}	2522	}
2531		2523
2532	/* If we have free CSG slots left, pick idle groups */	2524	/* If we have free CSG slots left, pick idle groups */
@@ -2651,14 +2643,33 @@ static void sync_upd_work(struct work_struct *work) · 118 unmodified lines
2651	sched_queue_delayed_work(sched, tick, 0);	2643	sched_queue_delayed_work(sched, tick, 0);
2652	}	2644	}
2653		2645
		2646	static void sched_resume_tick(struct panthor_device *ptdev)
		2647	{
		2648	struct panthor_scheduler *sched = ptdev->scheduler;
		2649	u64 delay_jiffies, now;
		2650
		2651	drm_WARN_ON(&ptdev->base, sched->resched_target != U64_MAX);
		2652
		2653	/* Scheduler tick was off, recalculate the resched_target based on the
		2654	* last tick event, and queue the scheduler work.
		2655	*/
		2656	now = get_jiffies_64();
		2657	sched->resched_target = sched->last_tick + sched->tick_period;
		2658	if (sched->used_csg_slot_count == sched->csg_slot_count &&
		2659	time_before64(now, sched->resched_target))
		2660	delay_jiffies = min_t(unsigned long, sched->resched_target - now, ULONG_MAX);
		2661	else
		2662	delay_jiffies = 0;
		2663
		2664	sched_queue_delayed_work(sched, tick, delay_jiffies);
		2665	}
		2666
2654	static void group_schedule_locked(struct panthor_group *group, u32 queue_mask)	2667	static void group_schedule_locked(struct panthor_group *group, u32 queue_mask)
2655	{	2668	{
2656	struct panthor_device *ptdev = group->ptdev;	2669	struct panthor_device *ptdev = group->ptdev;
2657	struct panthor_scheduler *sched = ptdev->scheduler;	2670	struct panthor_scheduler *sched = ptdev->scheduler;
2658	struct list_head *queue = &sched->groups.runnable[group->priority];	2671	struct list_head *queue = &sched->groups.runnable[group->priority];
2659	u64 delay_jiffies = 0;
2660	bool was_idle;	2672	bool was_idle;
2661	u64 now;
2662		2673
2663	if (!group_can_run(group))	2674	if (!group_can_run(group))
2664	return;	2675	return;
@@ -2703,13 +2714,7 @@ static void group_schedule_locked(struct panthor_group *group, u32 queue_mask) · 38 unmodified lines
2703	/* Scheduler tick was off, recalculate the resched_target based on the	2714	/* Scheduler tick was off, recalculate the resched_target based on the
2704	* last tick event, and queue the scheduler work.	2715	* last tick event, and queue the scheduler work.
2705	*/	2716	*/
2706	now = get_jiffies_64();	2717	sched_resume_tick(ptdev);
2707	sched->resched_target = sched->last_tick + sched->tick_period;
2708	if (sched->used_csg_slot_count == sched->csg_slot_count &&
2709	time_before64(now, sched->resched_target))
2710	delay_jiffies = min_t(unsigned long, sched->resched_target - now, ULONG_MAX);
2711
2712	sched_queue_delayed_work(sched, tick, delay_jiffies);
2713	}	2718	}
2714		2719
2715	static void queue_stop(struct panthor_queue *queue,	2720	static void queue_stop(struct panthor_queue *queue,
@@ -2767,13 +2772,6 @@ static void panthor_group_start(struct panthor_group *group) · 51 unmodified lines
2767	group_put(group);	2772	group_put(group);
2768	}	2773	}
2769		2774
2770	static void panthor_sched_immediate_tick(struct panthor_device *ptdev)
2771	{
2772	struct panthor_scheduler *sched = ptdev->scheduler;
2773
2774	sched_queue_delayed_work(sched, tick, 0);
2775	}
2776
2777	/**	2775	/**
2778	* panthor_sched_report_mmu_fault() - Report MMU faults to the scheduler.	2776	* panthor_sched_report_mmu_fault() - Report MMU faults to the scheduler.
2779	*/	2777	*/
@@ -2781,13 +2779,13 @@ void panthor_sched_report_mmu_fault(struct panthor_device *ptdev) · 1 unmodified line
2781	{	2779	{
2782	/* Force a tick to immediately kill faulty groups. */	2780	/* Force a tick to immediately kill faulty groups. */
2783	if (ptdev->scheduler)	2781	if (ptdev->scheduler)
2784	panthor_sched_immediate_tick(ptdev);	2782	sched_queue_delayed_work(ptdev->scheduler, tick, 0);
2785	}	2783	}
2786		2784
2787	void panthor_sched_resume(struct panthor_device *ptdev)	2785	void panthor_sched_resume(struct panthor_device *ptdev)
2788	{	2786	{
2789	/* Force a tick to re-evaluate after a resume. */	2787	/* Force a tick to re-evaluate after a resume. */
2790	panthor_sched_immediate_tick(ptdev);	2788	sched_queue_delayed_work(ptdev->scheduler, tick, 0);
2791	}	2789	}
2792		2790
2793	void panthor_sched_suspend(struct panthor_device *ptdev)	2791	void panthor_sched_suspend(struct panthor_device *ptdev)
@@ -2943,8 +2941,6 @@ void panthor_sched_pre_reset(struct panthor_device *ptdev) · 149 unmodified lines
2943	* new jobs while we're resetting.	2941	* new jobs while we're resetting.
2944	*/	2942	*/
2945	for (i = 0; i < ARRAY_SIZE(sched->groups.runnable); i++) {	2943	for (i = 0; i < ARRAY_SIZE(sched->groups.runnable); i++) {
2946	/* All groups should be in the idle lists. */
2947	drm_WARN_ON(&ptdev->base, !list_empty(&sched->groups.runnable[i]));
2948	list_for_each_entry_safe(group, group_tmp, &sched->groups.runnable[i], run_node)	2944	list_for_each_entry_safe(group, group_tmp, &sched->groups.runnable[i], run_node)
2949	panthor_group_stop(group);	2945	panthor_group_stop(group);
2950	}	2946	}
@@ -3343,6 +3339,18 @@ queue_run_job(struct drm_sched_job *sched_job) · 392 unmodified lines
3343	if (group->csg_id < 0) {	3339	if (group->csg_id < 0) {
3344	group_schedule_locked(group, BIT(job->queue_idx));	3340	group_schedule_locked(group, BIT(job->queue_idx));
3345	} else {	3341	} else {
		3342	u32 queue_mask = BIT(job->queue_idx);
		3343	bool resume_tick = group_is_idle(group) &&
		3344	(group->idle_queues & queue_mask) &&
		3345	!(group->blocked_queues & queue_mask) &&
		3346	sched->resched_target == U64_MAX;
		3347
		3348	/* We just added something to the queue, so it's no longer idle. */
		3349	group->idle_queues &= ~queue_mask;
		3350
		3351	if (resume_tick)
		3352	sched_resume_tick(ptdev);
		3353
3346	gpu_write(ptdev, CSF_DOORBELL(queue->doorbell_id), 1);	3354	gpu_write(ptdev, CSF_DOORBELL(queue->doorbell_id), 1);
3347	if (!sched->pm.has_ref &&	3355	if (!sched->pm.has_ref &&
3348	!(group->blocked_queues & BIT(job->queue_idx))) {	3356	!(group->blocked_queues & BIT(job->queue_idx))) {

drivers/gpu/drm/pl111/pl111_display.c+2−2

@@ -138,7 +138,7 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe, · 137 unmodified lines
138		138
139	ret = clk_set_rate(priv->clk, mode->clock * 1000);	139	ret = clk_set_rate(priv->clk, mode->clock * 1000);
140	if (ret) {	140	if (ret) {
141	dev_err(drm->dev,	141	drm_err(drm,
142	"Failed to set pixel clock rate to %d: %d\n",	142	"Failed to set pixel clock rate to %d: %d\n",
143	mode->clock * 1000, ret);	143	mode->clock * 1000, ret);
144	}	144	}
@@ -553,7 +553,7 @@ pl111_init_clock_divider(struct drm_device *drm) · 408 unmodified lines
553	int ret;	553	int ret;
554		554
555	if (IS_ERR(parent)) {	555	if (IS_ERR(parent)) {
556	dev_err(drm->dev, "CLCD: unable to get clcdclk.\n");	556	drm_err(drm, "CLCD: unable to get clcdclk.\n");
557	return PTR_ERR(parent);	557	return PTR_ERR(parent);
558	}	558	}
559		559

drivers/gpu/drm/pl111/pl111_drv.c+15−14

 #include <drm/drm_gem_framebuffer_helper.h>
 #include <drm/drm_of.h>
 #include <drm/drm_panel.h>
+#include <drm/drm_print.h>
 #include <drm/drm_probe_helper.h>
 #include <drm/drm_vblank.h>
 		struct drm_panel *tmp_panel;
 		struct drm_bridge *tmp_bridge;
-		dev_dbg(dev->dev, "checking endpoint %d\n", i);
+		drm_dbg(dev, "checking endpoint %d\n", i);
 		ret = drm_of_find_panel_or_bridge(dev->dev->of_node,
 						  0, i,
 				defer = true;
 			} else if (ret != -ENODEV) {
 				/* Continue, maybe something else is working */
-				dev_err(dev->dev,
+				drm_err(dev,
 					"endpoint %d returns %d\n", i, ret);
 			}
 		}
 		if (tmp_panel) {
-			dev_info(dev->dev,
+			drm_info(dev,
 				 "found panel on endpoint %d\n", i);
 			panel = tmp_panel;
 		}
 		if (tmp_bridge) {
-			dev_info(dev->dev,
+			drm_info(dev,
 				 "found bridge on endpoint %d\n", i);
 			bridge = tmp_bridge;
 		}
 			goto finish;
 		}
 	} else if (bridge) {
-		dev_info(dev->dev, "Using non-panel bridge\n");
+		drm_info(dev, "Using non-panel bridge\n");
 	} else {
-		dev_err(dev->dev, "No bridge, exiting\n");
+		drm_err(dev, "No bridge, exiting\n");
 		return -ENODEV;
 	}
 	ret = pl111_display_init(dev);
 	if (ret != 0) {
-		dev_err(dev->dev, "Failed to init display\n");
+		drm_err(dev, "Failed to init display\n");
 		goto out_bridge;
 	}
 	if (!priv->variant->broken_vblank) {
 		ret = drm_vblank_init(dev, 1);
 		if (ret != 0) {
-			dev_err(dev->dev, "Failed to init vblank\n");
+			drm_err(dev, "Failed to init vblank\n");
 			goto out_bridge;
 		}
 	}
 	ret = of_reserved_mem_device_init(dev);
 	if (!ret) {
-		dev_info(dev, "using device-specific reserved memory\n");
+		drm_info(drm, "using device-specific reserved memory\n");
 		priv->use_device_memory = true;
 	}
 	if (of_property_read_u32(dev->of_node, "max-memory-bandwidth",
 				 &priv->memory_bw)) {
-		dev_info(dev, "no max memory bandwidth specified, assume unlimited\n");
+		drm_info(drm, "no max memory bandwidth specified, assume unlimited\n");
 		priv->memory_bw = 0;
 	}
 	priv->regs = devm_ioremap_resource(dev, &amba_dev->res);
 	if (IS_ERR(priv->regs)) {
-		dev_err(dev, "%s failed mmio\n", __func__);
+		drm_err(drm, "%s failed mmio\n", __func__);
 		ret = PTR_ERR(priv->regs);
 		goto dev_put;
 	}
 	/* This may override some variant settings */
-	ret = pl111_versatile_init(dev, priv);
+	ret = pl111_versatile_init(drm, priv);
 	if (ret)
 		goto dev_put;
-	pl111_nomadik_init(dev);
+	pl111_nomadik_init(drm);
 	/* turn off interrupts before requesting the irq */
 	writel(0, priv->regs + priv->ienb);
 	ret = devm_request_irq(dev, amba_dev->irq[0], pl111_irq, 0,
 			       variant->name, priv);
 	if (ret != 0) {
-		dev_err(dev, "%s failed irq %d\n", __func__, ret);
+		drm_err(drm, "%s failed irq %d\n", __func__, ret);
 		return ret;
 	}

drivers/gpu/drm/pl111/pl111_nomadik.c+2−2

@@ -9,7 +9,7 @@ · 8 unmodified lines
9	#define PMU_CTRL_OFFSET 0x0000	9	#define PMU_CTRL_OFFSET 0x0000
10	#define PMU_CTRL_LCDNDIF BIT(26)	10	#define PMU_CTRL_LCDNDIF BIT(26)
11		11
12	void pl111_nomadik_init(struct device *dev)	12	void pl111_nomadik_init(struct drm_device *dev)
13	{	13	{
14	struct regmap *pmu_regmap;	14	struct regmap *pmu_regmap;
15		15
@@ -31,6 +31,6 @@ void pl111_nomadik_init(struct device *dev) · 15 unmodified lines
31	PMU_CTRL_OFFSET,	31	PMU_CTRL_OFFSET,
32	PMU_CTRL_LCDNDIF,	32	PMU_CTRL_LCDNDIF,
33	0);	33	0);
34	dev_info(dev, "set Nomadik PMU mux to CLCD mode\n");	34	drm_info(dev, "set Nomadik PMU mux to CLCD mode\n");
35	}	35	}
36	EXPORT_SYMBOL_GPL(pl111_nomadik_init);	36	EXPORT_SYMBOL_GPL(pl111_nomadik_init);

drivers/gpu/drm/pl111/pl111_nomadik.h+2−2

@@ -8,11 +8,11 @@ struct device; · 7 unmodified lines
8		8
9	#ifdef CONFIG_ARCH_NOMADIK	9	#ifdef CONFIG_ARCH_NOMADIK
10		10
11	void pl111_nomadik_init(struct device *dev);	11	void pl111_nomadik_init(struct drm_device *dev);
12		12
13	#else	13	#else
14		14
15	static inline void pl111_nomadik_init(struct device *dev)	15	static inline void pl111_nomadik_init(struct drm_device *dev)
16	{	16	{
17	}	17	}
18		18

drivers/gpu/drm/pl111/pl111_versatile.c+27−26

 #include <linux/vexpress.h>
 #include <drm/drm_fourcc.h>
+#include <drm/drm_print.h>
 #include "pl111_versatile.h"
 #include "pl111_drm.h"
 {
 	u32 val;
-	dev_info(drm->dev, "enable Integrator CLCD connectors\n");
+	drm_info(drm, "enable Integrator CLCD connectors\n");
 	/* FIXME: really needed? */
 	val = INTEGRATOR_CLCD_LCD_STATIC1 | INTEGRATOR_CLCD_LCD_STATIC2 |
 		val |= INTEGRATOR_CLCD_LCDMUX_VGA555;
 		break;
 	default:
-		dev_err(drm->dev, "unhandled format on Integrator 0x%08x\n",
+		drm_err(drm, "unhandled format on Integrator 0x%08x\n",
 			format);
 		break;
 	}
 {
 	u32 val;
-	dev_info(drm->dev, "enable IM-PD1 CLCD connectors\n");
+	drm_info(drm, "enable IM-PD1 CLCD connectors\n");
 	val = IMPD1_CTRL_DISP_VGA | IMPD1_CTRL_DISP_ENABLE;
 	regmap_update_bits(versatile_syscon_map,
 static void pl111_impd1_disable(struct drm_device *drm)
 {
-	dev_info(drm->dev, "disable IM-PD1 CLCD connectors\n");
+	drm_info(drm, "disable IM-PD1 CLCD connectors\n");
 	regmap_update_bits(versatile_syscon_map,
 			   IMPD1_CTRL_OFFSET,
 static void pl111_versatile_disable(struct drm_device *drm)
 {
-	dev_info(drm->dev, "disable Versatile CLCD connectors\n");
+	drm_info(drm, "disable Versatile CLCD connectors\n");
 	regmap_update_bits(versatile_syscon_map,
 			   SYS_CLCD,
 			   SYS_CLCD_CONNECTOR_MASK,
 {
 	u32 val = 0;
-	dev_info(drm->dev, "enable Versatile CLCD connectors\n");
+	drm_info(drm, "enable Versatile CLCD connectors\n");
 	switch (format) {
 	case DRM_FORMAT_ABGR8888:
 		val |= SYS_CLCD_MODE_5551;
 		break;
 	default:
-		dev_err(drm->dev, "unhandled format on Versatile 0x%08x\n",
+		drm_err(drm, "unhandled format on Versatile 0x%08x\n",
 			format);
 		break;
 	}
 static void pl111_realview_clcd_disable(struct drm_device *drm)
 {
-	dev_info(drm->dev, "disable RealView CLCD connectors\n");
+	drm_info(drm, "disable RealView CLCD connectors\n");
 	regmap_update_bits(versatile_syscon_map,
 			   SYS_CLCD,
 			   SYS_CLCD_CONNECTOR_MASK,
 static void pl111_realview_clcd_enable(struct drm_device *drm, u32 format)
 {
-	dev_info(drm->dev, "enable RealView CLCD connectors\n");
+	drm_info(drm, "enable RealView CLCD connectors\n");
 	regmap_update_bits(versatile_syscon_map,
 			   SYS_CLCD,
 			   SYS_CLCD_CONNECTOR_MASK,
 #define VEXPRESS_FPGAMUX_DAUGHTERBOARD_1	0x01
 #define VEXPRESS_FPGAMUX_DAUGHTERBOARD_2	0x02
-static int pl111_vexpress_clcd_init(struct device *dev, struct device_node *np,
+static int pl111_vexpress_clcd_init(struct drm_device *dev, struct device_node *np,
 				    struct pl111_drm_dev_private *priv)
 {
 	struct platform_device *pdev;
 		mux_motherboard = false;
 	if (mux_motherboard) {
-		dev_info(dev, "DVI muxed to motherboard CLCD\n");
+		drm_info(dev, "DVI muxed to motherboard CLCD\n");
 		val = VEXPRESS_FPGAMUX_MOTHERBOARD;
-	} else if (ct_clcd == dev->of_node) {
+	} else if (ct_clcd == dev->dev->of_node) {
-		dev_info(dev,
+		drm_info(dev,
 			 "DVI muxed to daughterboard 1 (core tile) CLCD\n");
 		val = VEXPRESS_FPGAMUX_DAUGHTERBOARD_1;
 	} else {
-		dev_info(dev, "core tile graphics present\n");
+		drm_info(dev, "core tile graphics present\n");
-		dev_info(dev, "this device will be deactivated\n");
+		drm_info(dev, "this device will be deactivated\n");
 		return -ENODEV;
 	}
 	/* Call into deep Vexpress configuration API */
 	pdev = of_find_device_by_node(np);
 	if (!pdev) {
-		dev_err(dev, "can't find the sysreg device, deferring\n");
+		drm_err(dev, "can't find the sysreg device, deferring\n");
 		return -EPROBE_DEFER;
 	}
 	ret = regmap_write(map, 0, val);
 	platform_device_put(pdev);
 	if (ret) {
-		dev_err(dev, "error setting DVI muxmode\n");
+		drm_err(dev, "error setting DVI muxmode\n");
 		return -ENODEV;
 	}
 	priv->variant = &pl111_vexpress;
-	dev_info(dev, "initializing Versatile Express PL111\n");
+	drm_info(dev, "initializing Versatile Express PL111\n");
 	return 0;
 }
-int pl111_versatile_init(struct device *dev, struct pl111_drm_dev_private *priv)
+int pl111_versatile_init(struct drm_device *dev, struct pl111_drm_dev_private *priv)
 {
 	const struct of_device_id *clcd_id;
 	enum versatile_clcd versatile_clcd_type;
 		int ret = pl111_vexpress_clcd_init(dev, np, priv);
 		of_node_put(np);
 		if (ret)
-			dev_err(dev, "Versatile Express init failed - %d", ret);
+			drm_err(dev, "Versatile Express init failed - %d", ret);
 		return ret;
 	}
 	map = syscon_node_to_regmap(np);
 	of_node_put(np);
 	if (IS_ERR(map)) {
-		dev_err(dev, "no Versatile syscon regmap\n");
+		drm_err(dev, "no Versatile syscon regmap\n");
 		return PTR_ERR(map);
 	}
 		versatile_syscon_map = map;
 		priv->variant = &pl110_integrator;
 		priv->variant_display_enable = pl111_integrator_enable;
-		dev_info(dev, "set up callbacks for Integrator PL110\n");
+		drm_info(dev, "set up callbacks for Integrator PL110\n");
 		break;
 	case INTEGRATOR_IMPD1:
 		versatile_syscon_map = map;
 		priv->variant = &pl110_impd1;
 		priv->variant_display_enable = pl111_impd1_enable;
 		priv->variant_display_disable = pl111_impd1_disable;
-		dev_info(dev, "set up callbacks for IM-PD1 PL110\n");
+		drm_info(dev, "set up callbacks for IM-PD1 PL110\n");
 		break;
 	case VERSATILE_CLCD:
 		versatile_syscon_map = map;
 		 */
 		priv->ienb = CLCD_PL111_IENB;
 		priv->ctrl = CLCD_PL111_CNTL;
-		dev_info(dev, "set up callbacks for Versatile PL110\n");
+		drm_info(dev, "set up callbacks for Versatile PL110\n");
 		break;
 	case REALVIEW_CLCD_EB:
 	case REALVIEW_CLCD_PB1176:
 		priv->variant = &pl111_realview;
 		priv->variant_display_enable = pl111_realview_clcd_enable;
 		priv->variant_display_disable = pl111_realview_clcd_disable;
-		dev_info(dev, "set up callbacks for RealView PL111\n");
+		drm_info(dev, "set up callbacks for RealView PL111\n");
 		break;
 	default:
-		dev_info(dev, "unknown Versatile system controller\n");
+		drm_info(dev, "unknown Versatile system controller\n");
 		break;
 	}

drivers/gpu/drm/pl111/pl111_versatile.h+1−1

@@ -7,6 +7,6 @@ · 6 unmodified lines
7	struct device;	7	struct device;
8	struct pl111_drm_dev_private;	8	struct pl111_drm_dev_private;
9		9
10	int pl111_versatile_init(struct device dev, struct pl111_drm_dev_private priv);	10	int pl111_versatile_init(struct drm_device dev, struct pl111_drm_dev_private priv);
11		11
12	#endif	12	#endif

drivers/gpu/drm/radeon/atombios_crtc.c+19−55

 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
 				 struct drm_framebuffer *fb,
-				 int x, int y, int atomic)
+				 int x, int y)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	bool bypass_lut = false;
 	/* no fb bound */
-	if (!atomic && !crtc->primary->fb) {
+	if (!crtc->primary->fb) {
 		DRM_DEBUG_KMS("No FB bound\n");
 		return 0;
 	}
-	if (atomic)
+	target_fb = crtc->primary->fb;
-		target_fb = fb;
-	else
-		target_fb = crtc->primary->fb;
-	/* If atomic, assume fb object is pinned & idle & fenced and
-	 * just update base pointers
-	 */
 	obj = target_fb->obj[0];
 	rbo = gem_to_radeon_bo(obj);
 	r = radeon_bo_reserve(rbo, false);
 	if (unlikely(r != 0))
 		return r;
-	if (atomic)
+	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
-		fb_location = radeon_bo_gpu_offset(rbo);
+	if (unlikely(r != 0)) {
-	else {
+		radeon_bo_unreserve(rbo);
-		r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
+		return -EINVAL;
-		if (unlikely(r != 0)) {
-			radeon_bo_unreserve(rbo);
-			return -EINVAL;
-		}
 	}
 	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 	/* set pageflip to happen anywhere in vblank interval */
 	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
-	if (!atomic && fb && fb != crtc->primary->fb) {
+	if (fb && fb != crtc->primary->fb) {
 		rbo = gem_to_radeon_bo(fb->obj[0]);
 		r = radeon_bo_reserve(rbo, false);
 		if (unlikely(r != 0))
 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
 				  struct drm_framebuffer *fb,
-				  int x, int y, int atomic)
+				  int x, int y)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	bool bypass_lut = false;
 	/* no fb bound */
-	if (!atomic && !crtc->primary->fb) {
+	if (!crtc->primary->fb) {
 		DRM_DEBUG_KMS("No FB bound\n");
 		return 0;
 	}
-	if (atomic)
+	target_fb = crtc->primary->fb;
-		target_fb = fb;
-	else
-		target_fb = crtc->primary->fb;
 	obj = target_fb->obj[0];
 	rbo = gem_to_radeon_bo(obj);
 	if (unlikely(r != 0))
 		return r;
-	/* If atomic, assume fb object is pinned & idle & fenced and
+	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
-	 * just update base pointers
+	if (unlikely(r != 0)) {
-	 */
+		radeon_bo_unreserve(rbo);
-	if (atomic)
+		return -EINVAL;
-		fb_location = radeon_bo_gpu_offset(rbo);
-	else {
-		r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
-		if (unlikely(r != 0)) {
-			radeon_bo_unreserve(rbo);
-			return -EINVAL;
-		}
 	}
 	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 	radeon_bo_unreserve(rbo);
 	/* set pageflip to happen only at start of vblank interval (front porch) */
 	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
-	if (!atomic && fb && fb != crtc->primary->fb) {
+	if (fb && fb != crtc->primary->fb) {
 		rbo = gem_to_radeon_bo(fb->obj[0]);
 		r = radeon_bo_reserve(rbo, false);
 		if (unlikely(r != 0))
 	struct radeon_device *rdev = dev->dev_private;
 	if (ASIC_IS_DCE4(rdev))
-		return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
+		return dce4_crtc_do_set_base(crtc, old_fb, x, y);
-	else if (ASIC_IS_AVIVO(rdev))
-		return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
-	else
-		return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
-}
-int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
-				  struct drm_framebuffer *fb,
-				  int x, int y, enum mode_set_atomic state)
-{
-	struct drm_device *dev = crtc->dev;
-	struct radeon_device *rdev = dev->dev_private;
-	if (ASIC_IS_DCE4(rdev))
-		return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
 	else if (ASIC_IS_AVIVO(rdev))
-		return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
+		return avivo_crtc_do_set_base(crtc, old_fb, x, y);
 	else
-		return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
+		return radeon_crtc_do_set_base(crtc, old_fb, x, y);
 }
 /* properly set additional regs when using atombios */
 	.mode_fixup = atombios_crtc_mode_fixup,
 	.mode_set = atombios_crtc_mode_set,
 	.mode_set_base = atombios_crtc_set_base,
-	.mode_set_base_atomic = atombios_crtc_set_base_atomic,
 	.prepare = atombios_crtc_prepare,
 	.commit = atombios_crtc_commit,
 	.disable = atombios_crtc_disable,

drivers/gpu/drm/radeon/radeon_legacy_crtc.c+6−17

 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 			 struct drm_framebuffer *old_fb)
 {
-	return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
+	return radeon_crtc_do_set_base(crtc, old_fb, x, y);
-}
-int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
-				struct drm_framebuffer *fb,
-				int x, int y, enum mode_set_atomic state)
-{
-	return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
 }
 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 			 struct drm_framebuffer *fb,
-			 int x, int y, int atomic)
+			 int x, int y)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	DRM_DEBUG_KMS("\n");
 	/* no fb bound */
-	if (!atomic && !crtc->primary->fb) {
+	if (!crtc->primary->fb) {
 		DRM_DEBUG_KMS("No FB bound\n");
 		return 0;
 	}
-	if (atomic)
+	target_fb = crtc->primary->fb;
-		target_fb = fb;
-	else
-		target_fb = crtc->primary->fb;
 	switch (target_fb->format->cpp[0] * 8) {
 	case 8:
 		 * We don't shutdown the display controller because new buffer
 		 * will end up in same spot.
 		 */
-		if (!atomic && fb && fb != crtc->primary->fb) {
+		if (fb && fb != crtc->primary->fb) {
 			struct radeon_bo *old_rbo;
 			unsigned long nsize, osize;
 	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
-	if (!atomic && fb && fb != crtc->primary->fb) {
+	if (fb && fb != crtc->primary->fb) {
 		rbo = gem_to_radeon_bo(fb->obj[0]);
 		r = radeon_bo_reserve(rbo, false);
 		if (unlikely(r != 0))
 	.mode_fixup = radeon_crtc_mode_fixup,
 	.mode_set = radeon_crtc_mode_set,
 	.mode_set_base = radeon_crtc_set_base,
-	.mode_set_base_atomic = radeon_crtc_set_base_atomic,
 	.prepare = radeon_crtc_prepare,
 	.commit = radeon_crtc_commit,
 	.disable = radeon_crtc_disable,

drivers/gpu/drm/radeon/radeon_mode.h+1−9

 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 				   struct drm_framebuffer *old_fb);
-extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
-					 struct drm_framebuffer *fb,
-					 int x, int y,
-					 enum mode_set_atomic state);
 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
 				   struct drm_display_mode *mode,
 				   struct drm_display_mode *adjusted_mode,
 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 				 struct drm_framebuffer *old_fb);
-extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
-				       struct drm_framebuffer *fb,
-				       int x, int y,
-				       enum mode_set_atomic state);
 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 				   struct drm_framebuffer *fb,
-				   int x, int y, int atomic);
+				   int x, int y);
 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
 				   struct drm_file *file_priv,
 				   uint32_t handle,

drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c+1−1

@@ -692,7 +692,7 @@ static int threaded_fence_signal(void *arg) · 691 unmodified lines
692		692
693	msleep(20);	693	msleep(20);
694		694
695	return dma_fence_signal(fence);	695	return dma_fence_check_and_signal(fence) ? -EINVAL : 0;
696	}	696	}
697		697
698	static void ttm_bo_validate_move_fence_not_signaled(struct kunit *test)	698	static void ttm_bo_validate_move_fence_not_signaled(struct kunit *test)

drivers/gpu/drm/ttm/ttm_bo.c+33−31

@@ -268,8 +268,8 @@ static void ttm_bo_release(struct kref *kref) · 267 unmodified lines
268	30 * HZ);	268	30 * HZ);
269	}	269	}
270		270
271	if (bo->bdev->funcs->release_notify)	271	if (bdev->funcs->release_notify)
272	bo->bdev->funcs->release_notify(bo);	272	bdev->funcs->release_notify(bo);
273		273
274	drm_vma_offset_remove(bdev->vma_manager, &bo->base.vma_node);	274	drm_vma_offset_remove(bdev->vma_manager, &bo->base.vma_node);
275	ttm_mem_io_free(bdev, bo->resource);	275	ttm_mem_io_free(bdev, bo->resource);
@@ -283,7 +283,7 @@ static void ttm_bo_release(struct kref *kref) · 7 unmodified lines
283	ttm_bo_flush_all_fences(bo);	283	ttm_bo_flush_all_fences(bo);
284	bo->deleted = true;	284	bo->deleted = true;
285		285
286	spin_lock(&bo->bdev->lru_lock);	286	spin_lock(&bdev->lru_lock);
287		287
288	/*	288	/*
289	* Make pinned bos immediately available to	289	* Make pinned bos immediately available to
@@ -299,7 +299,7 @@ static void ttm_bo_release(struct kref *kref) · 9 unmodified lines
299	}	299	}
300		300
301	kref_init(&bo->kref);	301	kref_init(&bo->kref);
302	spin_unlock(&bo->bdev->lru_lock);	302	spin_unlock(&bdev->lru_lock);
303		303
304	INIT_WORK(&bo->delayed_delete, ttm_bo_delayed_delete);	304	INIT_WORK(&bo->delayed_delete, ttm_bo_delayed_delete);
305		305
@@ -359,7 +359,6 @@ static int ttm_bo_bounce_temp_buffer(struct ttm_buffer_object *bo, · 53 unmodified lines
359	static int ttm_bo_evict(struct ttm_buffer_object *bo,	359	static int ttm_bo_evict(struct ttm_buffer_object *bo,
360	struct ttm_operation_ctx *ctx)	360	struct ttm_operation_ctx *ctx)
361	{	361	{
362	struct ttm_device *bdev = bo->bdev;
363	struct ttm_resource *evict_mem;	362	struct ttm_resource *evict_mem;
364	struct ttm_placement placement;	363	struct ttm_placement placement;
365	struct ttm_place hop;	364	struct ttm_place hop;
@@ -370,7 +369,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, · 4 unmodified lines
370	dma_resv_assert_held(bo->base.resv);	369	dma_resv_assert_held(bo->base.resv);
371		370
372	placement.num_placement = 0;	371	placement.num_placement = 0;
373	bdev->funcs->evict_flags(bo, &placement);	372	bo->bdev->funcs->evict_flags(bo, &placement);
374		373
375	if (!placement.num_placement) {	374	if (!placement.num_placement) {
376	ret = ttm_bo_wait_ctx(bo, ctx);	375	ret = ttm_bo_wait_ctx(bo, ctx);
@@ -423,16 +422,16 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, · 46 unmodified lines
423	const struct ttm_place *place)	422	const struct ttm_place *place)
424	{	423	{
425	struct ttm_resource *res = bo->resource;	424	struct ttm_resource *res = bo->resource;
426	struct ttm_device *bdev = bo->bdev;
427		425
428	dma_resv_assert_held(bo->base.resv);	426	dma_resv_assert_held(bo->base.resv);
429	if (bo->resource->mem_type == TTM_PL_SYSTEM)	427
		428	if (res->mem_type == TTM_PL_SYSTEM)
430	return true;	429	return true;
431		430
432	/* Don't evict this BO if it's outside of the	431	/* Don't evict this BO if it's outside of the
433	* requested placement range	432	* requested placement range
434	*/	433	*/
435	return ttm_resource_intersects(bdev, res, place, bo->base.size);	434	return ttm_resource_intersects(bo->bdev, res, place, bo->base.size);
436	}	435	}
437	EXPORT_SYMBOL(ttm_bo_eviction_valuable);	436	EXPORT_SYMBOL(ttm_bo_eviction_valuable);
438		437
@@ -1027,7 +1026,7 @@ int ttm_bo_init_validate(struct ttm_device bdev, struct ttm_buffer_object bo, · 588 unmodified lines
1027	struct sg_table sg, struct dma_resv resv,	1026	struct sg_table sg, struct dma_resv resv,
1028	void (destroy) (struct ttm_buffer_object ))	1027	void (destroy) (struct ttm_buffer_object ))
1029	{	1028	{
1030	struct ttm_operation_ctx ctx = { interruptible, false };	1029	struct ttm_operation_ctx ctx = { .interruptible = interruptible };
1031	int ret;	1030	int ret;
1032		1031
1033	ret = ttm_bo_init_reserved(bdev, bo, type, placement, alignment, &ctx,	1032	ret = ttm_bo_init_reserved(bdev, bo, type, placement, alignment, &ctx,
@@ -1108,10 +1107,13 @@ struct ttm_bo_swapout_walk { · 74 unmodified lines
1108	static s64	1107	static s64
1109	ttm_bo_swapout_cb(struct ttm_lru_walk walk, struct ttm_buffer_object bo)	1108	ttm_bo_swapout_cb(struct ttm_lru_walk walk, struct ttm_buffer_object bo)
1110	{	1109	{
1111	struct ttm_place place = {.mem_type = bo->resource->mem_type};	1110	struct ttm_resource *res = bo->resource;
		1111	struct ttm_place place = { .mem_type = res->mem_type };
1112	struct ttm_bo_swapout_walk *swapout_walk =	1112	struct ttm_bo_swapout_walk *swapout_walk =
1113	container_of(walk, typeof(*swapout_walk), walk);	1113	container_of(walk, typeof(*swapout_walk), walk);
1114	struct ttm_operation_ctx *ctx = walk->arg.ctx;	1114	struct ttm_operation_ctx *ctx = walk->arg.ctx;
		1115	struct ttm_device *bdev = bo->bdev;
		1116	struct ttm_tt *tt = bo->ttm;
1115	s64 ret;	1117	s64 ret;
1116		1118
1117	/*	1119	/*
@@ -1120,20 +1122,19 @@ ttm_bo_swapout_cb(struct ttm_lru_walk walk, struct ttm_buffer_object bo) · 2 unmodified lines
1120	* The driver may use the fact that we're moving from SYSTEM	1122	* The driver may use the fact that we're moving from SYSTEM
1121	* as an indication that we're about to swap out.	1123	* as an indication that we're about to swap out.
1122	*/	1124	*/
1123	if (bo->pin_count \|\| !bo->bdev->funcs->eviction_valuable(bo, &place)) {	1125	if (bo->pin_count \|\| !bdev->funcs->eviction_valuable(bo, &place)) {
1124	ret = -EBUSY;	1126	ret = -EBUSY;
1125	goto out;	1127	goto out;
1126	}	1128	}
1127		1129
1128	if (!bo->ttm \|\| !ttm_tt_is_populated(bo->ttm) \|\|	1130	if (!tt \|\| !ttm_tt_is_populated(tt) \|\|
1129	bo->ttm->page_flags & TTM_TT_FLAG_EXTERNAL \|\|	1131	tt->page_flags & (TTM_TT_FLAG_EXTERNAL \| TTM_TT_FLAG_SWAPPED)) {
1130	bo->ttm->page_flags & TTM_TT_FLAG_SWAPPED) {
1131	ret = -EBUSY;	1132	ret = -EBUSY;
1132	goto out;	1133	goto out;
1133	}	1134	}
1134		1135
1135	if (bo->deleted) {	1136	if (bo->deleted) {
1136	pgoff_t num_pages = bo->ttm->num_pages;	1137	pgoff_t num_pages = tt->num_pages;
1137		1138
1138	ret = ttm_bo_wait_ctx(bo, ctx);	1139	ret = ttm_bo_wait_ctx(bo, ctx);
1139	if (ret)	1140	if (ret)
@@ -1147,7 +1148,7 @@ ttm_bo_swapout_cb(struct ttm_lru_walk walk, struct ttm_buffer_object bo) · 7 unmodified lines
1147	/*	1148	/*
1148	* Move to system cached	1149	* Move to system cached
1149	*/	1150	*/
1150	if (bo->resource->mem_type != TTM_PL_SYSTEM) {	1151	if (res->mem_type != TTM_PL_SYSTEM) {
1151	struct ttm_resource *evict_mem;	1152	struct ttm_resource *evict_mem;
1152	struct ttm_place hop;	1153	struct ttm_place hop;
1153		1154
@@ -1174,21 +1175,21 @@ ttm_bo_swapout_cb(struct ttm_lru_walk walk, struct ttm_buffer_object bo) · 20 unmodified lines
1174	goto out;	1175	goto out;
1175		1176
1176	ttm_bo_unmap_virtual(bo);	1177	ttm_bo_unmap_virtual(bo);
1177	if (bo->bdev->funcs->swap_notify)	1178	if (bdev->funcs->swap_notify)
1178	bo->bdev->funcs->swap_notify(bo);	1179	bdev->funcs->swap_notify(bo);
1179		1180
1180	if (ttm_tt_is_populated(bo->ttm)) {	1181	if (ttm_tt_is_populated(tt)) {
1181	spin_lock(&bo->bdev->lru_lock);	1182	spin_lock(&bdev->lru_lock);
1182	ttm_resource_del_bulk_move(bo->resource, bo);	1183	ttm_resource_del_bulk_move(res, bo);
1183	spin_unlock(&bo->bdev->lru_lock);	1184	spin_unlock(&bdev->lru_lock);
1184		1185
1185	ret = ttm_tt_swapout(bo->bdev, bo->ttm, swapout_walk->gfp_flags);	1186	ret = ttm_tt_swapout(bdev, tt, swapout_walk->gfp_flags);
1186		1187
1187	spin_lock(&bo->bdev->lru_lock);	1188	spin_lock(&bdev->lru_lock);
1188	if (ret)	1189	if (ret)
1189	ttm_resource_add_bulk_move(bo->resource, bo);	1190	ttm_resource_add_bulk_move(res, bo);
1190	ttm_resource_move_to_lru_tail(bo->resource);	1191	ttm_resource_move_to_lru_tail(res);
1191	spin_unlock(&bo->bdev->lru_lock);	1192	spin_unlock(&bdev->lru_lock);
1192	}	1193	}
1193		1194
1194	out:	1195	out:
@@ -1261,6 +1262,7 @@ void ttm_bo_tt_destroy(struct ttm_buffer_object *bo) · 66 unmodified lines
1261	int ttm_bo_populate(struct ttm_buffer_object *bo,	1262	int ttm_bo_populate(struct ttm_buffer_object *bo,
1262	struct ttm_operation_ctx *ctx)	1263	struct ttm_operation_ctx *ctx)
1263	{	1264	{
		1265	struct ttm_device *bdev = bo->bdev;
1264	struct ttm_tt *tt = bo->ttm;	1266	struct ttm_tt *tt = bo->ttm;
1265	bool swapped;	1267	bool swapped;
1266	int ret;	1268	int ret;
@@ -1271,16 +1273,16 @@ int ttm_bo_populate(struct ttm_buffer_object *bo, · 4 unmodified lines
1271	return 0;	1273	return 0;
1272		1274
1273	swapped = ttm_tt_is_swapped(tt);	1275	swapped = ttm_tt_is_swapped(tt);
1274	ret = ttm_tt_populate(bo->bdev, tt, ctx);	1276	ret = ttm_tt_populate(bdev, tt, ctx);
1275	if (ret)	1277	if (ret)
1276	return ret;	1278	return ret;
1277		1279
1278	if (swapped && !ttm_tt_is_swapped(tt) && !bo->pin_count &&	1280	if (swapped && !ttm_tt_is_swapped(tt) && !bo->pin_count &&
1279	bo->resource) {	1281	bo->resource) {
1280	spin_lock(&bo->bdev->lru_lock);	1282	spin_lock(&bdev->lru_lock);
1281	ttm_resource_add_bulk_move(bo->resource, bo);	1283	ttm_resource_add_bulk_move(bo->resource, bo);
1282	ttm_resource_move_to_lru_tail(bo->resource);	1284	ttm_resource_move_to_lru_tail(bo->resource);
1283	spin_unlock(&bo->bdev->lru_lock);	1285	spin_unlock(&bdev->lru_lock);
1284	}	1286	}
1285		1287
1286	return 0;	1288	return 0;

drivers/gpu/drm/ttm/ttm_bo_util.c+25−32

 	dst_iter = ttm_kmap_iter_linear_io_init(&_dst_iter.io, bdev, dst_mem);
 	if (PTR_ERR(dst_iter) == -EINVAL && dst_man->use_tt)
-		dst_iter = ttm_kmap_iter_tt_init(&_dst_iter.tt, bo->ttm);
+		dst_iter = ttm_kmap_iter_tt_init(&_dst_iter.tt, ttm);
 	if (IS_ERR(dst_iter))
 		return PTR_ERR(dst_iter);
 	src_iter = ttm_kmap_iter_linear_io_init(&_src_iter.io, bdev, src_mem);
 	if (PTR_ERR(src_iter) == -EINVAL && src_man->use_tt)
-		src_iter = ttm_kmap_iter_tt_init(&_src_iter.tt, bo->ttm);
+		src_iter = ttm_kmap_iter_tt_init(&_src_iter.tt, ttm);
 	if (IS_ERR(src_iter)) {
 		ret = PTR_ERR(src_iter);
 		goto out_src_iter;
 {
 	struct ttm_resource *mem = bo->resource;
-	if (bo->resource->bus.addr) {
+	if (mem->bus.addr) {
 		map->bo_kmap_type = ttm_bo_map_premapped;
-		map->virtual = ((u8 *)bo->resource->bus.addr) + offset;
+		map->virtual = ((u8 *)mem->bus.addr) + offset;
 	} else {
-		resource_size_t res = bo->resource->bus.offset + offset;
+		resource_size_t res = mem->bus.offset + offset;
 		map->bo_kmap_type = ttm_bo_map_iomap;
 		if (mem->bus.caching == ttm_write_combined)
 			   struct ttm_bo_kmap_obj *map)
 {
 	struct ttm_resource *mem = bo->resource;
-	struct ttm_operation_ctx ctx = {
+	struct ttm_operation_ctx ctx = { };
-		.interruptible = false,
-		.no_wait_gpu = false
-	};
 	struct ttm_tt *ttm = bo->ttm;
 	struct ttm_resource_manager *man =
-			ttm_manager_type(bo->bdev, bo->resource->mem_type);
+			ttm_manager_type(bo->bdev, mem->mem_type);
 	pgprot_t prot;
 	int ret;
 		unsigned long start_page, unsigned long num_pages,
 		struct ttm_bo_kmap_obj *map)
 {
+	struct ttm_resource *res = bo->resource;
 	unsigned long offset, size;
 	int ret;
 	map->virtual = NULL;
 	map->bo = bo;
-	if (num_pages > PFN_UP(bo->resource->size))
+	if (num_pages > PFN_UP(res->size))
 		return -EINVAL;
-	if ((start_page + num_pages) > PFN_UP(bo->resource->size))
+	if ((start_page + num_pages) > PFN_UP(res->size))
 		return -EINVAL;
-	ret = ttm_mem_io_reserve(bo->bdev, bo->resource);
+	ret = ttm_mem_io_reserve(bo->bdev, res);
 	if (ret)
 		return ret;
-	if (!bo->resource->bus.is_iomem) {
+	if (!res->bus.is_iomem) {
 		return ttm_bo_kmap_ttm(bo, start_page, num_pages, map);
 	} else {
 		offset = start_page << PAGE_SHIFT;
 		iosys_map_set_vaddr_iomem(map, vaddr_iomem);
 	} else {
-		struct ttm_operation_ctx ctx = {
+		struct ttm_operation_ctx ctx = { };
-			.interruptible = false,
-			.no_wait_gpu = false
-		};
 		struct ttm_tt *ttm = bo->ttm;
 		pgprot_t prot;
 		void *vaddr;
 		iounmap(map->vaddr_iomem);
 	iosys_map_clear(map);
-	ttm_mem_io_free(bo->bdev, bo->resource);
+	ttm_mem_io_free(bo->bdev, mem);
 }
 EXPORT_SYMBOL(ttm_bo_vunmap);
 static void ttm_bo_move_pipeline_evict(struct ttm_buffer_object *bo,
 				       struct dma_fence *fence)
 {
-	struct ttm_device *bdev = bo->bdev;
 	struct ttm_resource_manager *from;
 	struct dma_fence *tmp;
 	int i;
-	from = ttm_manager_type(bdev, bo->resource->mem_type);
+	from = ttm_manager_type(bo->bdev, bo->resource->mem_type);
 	/**
 	 * BO doesn't have a TTM we need to bind/unbind. Just remember
 void ttm_bo_move_sync_cleanup(struct ttm_buffer_object *bo,
 			      struct ttm_resource *new_mem)
 {
-	struct ttm_device *bdev = bo->bdev;
+	struct ttm_resource_manager *man =
-	struct ttm_resource_manager *man = ttm_manager_type(bdev, new_mem->mem_type);
+		ttm_manager_type(bo->bdev, new_mem->mem_type);
 	int ret;
 	ret = ttm_bo_wait_free_node(bo, man->use_tt);
 				   struct ttm_buffer_object *bo)
 {
 	struct ttm_lru_walk_arg *arg = curs->arg;
-	struct dma_resv *resv = bo->base.resv;
 	int ret;
 	if (arg->ctx->interruptible)
-		ret = dma_resv_lock_interruptible(resv, arg->ticket);
+		ret = dma_resv_lock_interruptible(bo->base.resv, arg->ticket);
 	else
-		ret = dma_resv_lock(resv, arg->ticket);
+		ret = dma_resv_lock(bo->base.resv, arg->ticket);
 	if (!ret) {
 		curs->needs_unlock = true;
 		.num_placement = 1,
 		.placement = &sys_placement_flags,
 	};
-	struct ttm_tt *tt = bo->ttm;
+	struct ttm_device *bdev = bo->bdev;
 	long lret;
 	dma_resv_assert_held(bo->base.resv);
 		return lret;
 	if (bo->bulk_move) {
-		spin_lock(&bo->bdev->lru_lock);
+		spin_lock(&bdev->lru_lock);
 		ttm_resource_del_bulk_move(bo->resource, bo);
-		spin_unlock(&bo->bdev->lru_lock);
+		spin_unlock(&bdev->lru_lock);
 	}
-	lret = ttm_tt_backup(bo->bdev, tt, (struct ttm_backup_flags)
+	lret = ttm_tt_backup(bdev, bo->ttm, (struct ttm_backup_flags)
 			     {.purge = flags.purge,
 			      .writeback = flags.writeback});
 	if (lret <= 0 && bo->bulk_move) {
-		spin_lock(&bo->bdev->lru_lock);
+		spin_lock(&bdev->lru_lock);
 		ttm_resource_add_bulk_move(bo->resource, bo);
-		spin_unlock(&bo->bdev->lru_lock);
+		spin_unlock(&bdev->lru_lock);
 	}
 	if (lret < 0 && lret != -EINTR)

drivers/gpu/drm/ttm/ttm_bo_vm.c+5−7

 {
 	struct vm_area_struct *vma = vmf->vma;
 	struct ttm_buffer_object *bo = vma->vm_private_data;
-	struct ttm_device *bdev = bo->bdev;
 	unsigned long page_offset;
 	unsigned long page_last;
 	unsigned long pfn;
 	if (unlikely(ret != 0))
 		return ret;
-	err = ttm_mem_io_reserve(bdev, bo->resource);
+	err = ttm_mem_io_reserve(bo->bdev, bo->resource);
 	if (unlikely(err != 0))
 		return VM_FAULT_SIGBUS;
 {
 	struct vm_area_struct *vma = vmf->vma;
 	struct ttm_buffer_object *bo = vma->vm_private_data;
-	struct drm_device *ddev = bo->base.dev;
 	vm_fault_t ret = VM_FAULT_NOPAGE;
 	unsigned long address;
 	unsigned long pfn;
 		return VM_FAULT_OOM;
 	/* Set the page to be freed using drmm release action */
-	if (drmm_add_action_or_reset(ddev, ttm_bo_release_dummy_page, page))
+	if (drmm_add_action_or_reset(bo->base.dev, ttm_bo_release_dummy_page,
+				     page))
 		return VM_FAULT_OOM;
 	pfn = page_to_pfn(page);
 vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
 {
 	struct vm_area_struct *vma = vmf->vma;
-	pgprot_t prot;
 	struct ttm_buffer_object *bo = vma->vm_private_data;
-	struct drm_device *ddev = bo->base.dev;
 	vm_fault_t ret;
+	pgprot_t prot;
 	int idx;
 	ret = ttm_bo_vm_reserve(bo, vmf);
 		return ret;
 	prot = vma->vm_page_prot;
-	if (drm_dev_enter(ddev, &idx)) {
+	if (drm_dev_enter(bo->base.dev, &idx)) {
 		ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT);
 		drm_dev_exit(idx);
 	} else {

drivers/gpu/drm/ttm/ttm_device.c+1−4

  */
 int ttm_device_prepare_hibernation(struct ttm_device *bdev)
 {
-	struct ttm_operation_ctx ctx = {
+	struct ttm_operation_ctx ctx = { };
-		.interruptible = false,
-		.no_wait_gpu = false,
-	};
 	int ret;
 	do {

drivers/gpu/drm/ttm/ttm_pool.c+14−12

 int ttm_pool_restore_and_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
 			       const struct ttm_operation_ctx *ctx)
 {
+	struct ttm_pool_tt_restore *restore = tt->restore;
 	struct ttm_pool_alloc_state alloc;
 	if (WARN_ON(!ttm_tt_is_backed_up(tt)))
 		return -EINVAL;
-	if (!tt->restore) {
+	if (!restore) {
 		gfp_t gfp = GFP_KERNEL | __GFP_NOWARN;
 		ttm_pool_alloc_state_init(tt, &alloc);
 		if (ctx->gfp_retry_mayfail)
 			gfp |= __GFP_RETRY_MAYFAIL;
-		tt->restore = kzalloc(sizeof(*tt->restore), gfp);
+		restore = kzalloc(sizeof(*restore), gfp);
-		if (!tt->restore)
+		if (!restore)
 			return -ENOMEM;
-		tt->restore->snapshot_alloc = alloc;
+		restore->snapshot_alloc = alloc;
-		tt->restore->pool = pool;
+		restore->pool = pool;
-		tt->restore->restored_pages = 1;
+		restore->restored_pages = 1;
-	} else {
-		struct ttm_pool_tt_restore *restore = tt->restore;
-		int ret;
+		tt->restore = restore;
+	} else {
 		alloc = restore->snapshot_alloc;
-		if (ttm_pool_restore_valid(tt->restore)) {
+		if (ttm_pool_restore_valid(restore)) {
-			ret = ttm_pool_restore_commit(restore, tt->backup, ctx, &alloc);
+			int ret = ttm_pool_restore_commit(restore, tt->backup,
+							  ctx, &alloc);
 			if (ret)
 				return ret;
 		}
 			return 0;
 	}
-	return __ttm_pool_alloc(pool, tt, ctx, &alloc, tt->restore);
+	return __ttm_pool_alloc(pool, tt, ctx, &alloc, restore);
 }
 /**

drivers/gpu/drm/ttm/ttm_resource.c+4−10

@@ -446,9 +446,6 @@ bool ttm_resource_intersects(struct ttm_device *bdev, · 445 unmodified lines
446	{	446	{
447	struct ttm_resource_manager *man;	447	struct ttm_resource_manager *man;
448		448
449	if (!res)
450	return false;
451
452	man = ttm_manager_type(bdev, res->mem_type);	449	man = ttm_manager_type(bdev, res->mem_type);
453	if (!place \|\| !man->func->intersects)	450	if (!place \|\| !man->func->intersects)
454	return true;	451	return true;
@@ -548,10 +545,7 @@ EXPORT_SYMBOL(ttm_resource_manager_init); · 93 unmodified lines
548	int ttm_resource_manager_evict_all(struct ttm_device *bdev,	545	int ttm_resource_manager_evict_all(struct ttm_device *bdev,
549	struct ttm_resource_manager *man)	546	struct ttm_resource_manager *man)
550	{	547	{
551	struct ttm_operation_ctx ctx = {	548	struct ttm_operation_ctx ctx = { };
552	.interruptible = false,
553	.no_wait_gpu = false,
554	};
555	struct dma_fence *fence;	549	struct dma_fence *fence;
556	int ret, i;	550	int ret, i;
557		551
@@ -628,11 +622,11 @@ ttm_resource_cursor_check_bulk(struct ttm_resource_cursor *cursor, · 70 unmodified lines
628	struct ttm_lru_item *next_lru)	622	struct ttm_lru_item *next_lru)
629	{	623	{
630	struct ttm_resource *next = ttm_lru_item_to_res(next_lru);	624	struct ttm_resource *next = ttm_lru_item_to_res(next_lru);
631	struct ttm_lru_bulk_move *bulk = NULL;	625	struct ttm_lru_bulk_move *bulk;
632	struct ttm_buffer_object *bo = next->bo;
633		626
634	lockdep_assert_held(&cursor->man->bdev->lru_lock);	627	lockdep_assert_held(&cursor->man->bdev->lru_lock);
635	bulk = bo->bulk_move;	628
		629	bulk = next->bo->bulk_move;
636		630
637	if (cursor->bulk != bulk) {	631	if (cursor->bulk != bulk) {
638	if (bulk) {	632	if (bulk) {

drivers/gpu/drm/ttm/ttm_tt.c+1−1

@@ -456,7 +456,7 @@ EXPORT_SYMBOL_FOR_TESTS_ONLY(ttm_tt_unpopulate); · 455 unmodified lines
456	/* Test the shrinker functions and dump the result */	456	/* Test the shrinker functions and dump the result */
457	static int ttm_tt_debugfs_shrink_show(struct seq_file m, void data)	457	static int ttm_tt_debugfs_shrink_show(struct seq_file m, void data)
458	{	458	{
459	struct ttm_operation_ctx ctx = { false, false };	459	struct ttm_operation_ctx ctx = { };
460		460
461	seq_printf(m, "%d\n", ttm_global_swapout(&ctx, GFP_KERNEL));	461	seq_printf(m, "%d\n", ttm_global_swapout(&ctx, GFP_KERNEL));
462	return 0;	462	return 0;

drivers/gpu/drm/v3d/Makefile+1−2

@@ -13,8 +13,7 @@ v3d-y := \ · 12 unmodified lines
13	v3d_trace_points.o \	13	v3d_trace_points.o \
14	v3d_sched.o \	14	v3d_sched.o \
15	v3d_sysfs.o \	15	v3d_sysfs.o \
16	v3d_submit.o \	16	v3d_submit.o
17	v3d_gemfs.o
18		17
19	v3d-$(CONFIG_DEBUG_FS) += v3d_debugfs.o	18	v3d-$(CONFIG_DEBUG_FS) += v3d_debugfs.o
20		19

drivers/gpu/drm/v3d/v3d_bo.c+2−4

 	if (IS_ERR(sgt))
 		return PTR_ERR(sgt);
-	if (!v3d->gemfs)
+	if (!drm_gem_get_huge_mnt(obj->dev))
 		align = SZ_4K;
 	else if (obj->size >= SZ_1M)
 		align = SZ_1M;
 			     size_t unaligned_size)
 {
 	struct drm_gem_shmem_object *shmem_obj;
-	struct v3d_dev *v3d = to_v3d_dev(dev);
 	struct v3d_bo *bo;
 	int ret;
-	shmem_obj = drm_gem_shmem_create_with_mnt(dev, unaligned_size,
+	shmem_obj = drm_gem_shmem_create(dev, unaligned_size);
-						  v3d->gemfs);
 	if (IS_ERR(shmem_obj))
 		return ERR_CAST(shmem_obj);
 	bo = to_v3d_bo(&shmem_obj->base);

drivers/gpu/drm/v3d/v3d_drv.c+1−1

@@ -107,7 +107,7 @@ static int v3d_get_param_ioctl(struct drm_device dev, void data, · 106 unmodified lines
107	args->value = v3d->perfmon_info.max_counters;	107	args->value = v3d->perfmon_info.max_counters;
108	return 0;	108	return 0;
109	case DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES:	109	case DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES:
110	args->value = !!v3d->gemfs;	110	args->value = !!drm_gem_get_huge_mnt(dev);
111	return 0;	111	return 0;
112	case DRM_V3D_PARAM_GLOBAL_RESET_COUNTER:	112	case DRM_V3D_PARAM_GLOBAL_RESET_COUNTER:
113	mutex_lock(&v3d->reset_lock);	113	mutex_lock(&v3d->reset_lock);

drivers/gpu/drm/v3d/v3d_drv.h+1−10

 	struct drm_mm mm;
 	spinlock_t mm_lock;
-	/*
-	 * tmpfs instance used for shmem backed objects
-	 */
-	struct vfsmount *gemfs;
 	struct work_struct overflow_mem_work;
 	struct v3d_queue_state queue[V3D_MAX_QUEUES];
 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue q);
 /* v3d_gem.c */
+extern bool super_pages;
 int v3d_gem_init(struct drm_device *dev);
 void v3d_gem_destroy(struct drm_device *dev);
 void v3d_reset_sms(struct v3d_dev *v3d);
 void v3d_invalidate_caches(struct v3d_dev *v3d);
 void v3d_clean_caches(struct v3d_dev *v3d);
-/* v3d_gemfs.c */
-extern bool super_pages;
-void v3d_gemfs_init(struct v3d_dev *v3d);
-void v3d_gemfs_fini(struct v3d_dev *v3d);
 /* v3d_submit.c */
 void v3d_job_cleanup(struct v3d_job *job);
 void v3d_job_put(struct v3d_job *job);

drivers/gpu/drm/v3d/v3d_gem.c+19−2

 	v3d_invalidate_slices(v3d, 0);
 }
+static void
+v3d_huge_mnt_init(struct v3d_dev *v3d)
+{
+	int err = 0;
+	if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) && super_pages)
+		err = drm_gem_huge_mnt_create(&v3d->drm, "within_size");
+	if (drm_gem_get_huge_mnt(&v3d->drm))
+		drm_info(&v3d->drm, "Using Transparent Hugepages\n");
+	else if (err)
+		drm_warn(&v3d->drm, "Can't use Transparent Hugepages (%d)\n",
+			 err);
+	else
+		drm_notice(&v3d->drm,
+			   "Transparent Hugepage support is recommended for optimal performance on this platform!\n");
+}
 int
 v3d_gem_init(struct drm_device *dev)
 {
 	v3d_init_hw_state(v3d);
 	v3d_mmu_set_page_table(v3d);
-	v3d_gemfs_init(v3d);
+	v3d_huge_mnt_init(v3d);
 	ret = v3d_sched_init(v3d);
 	if (ret) {
 	enum v3d_queue q;
 	v3d_sched_fini(v3d);
-	v3d_gemfs_fini(v3d);
 	/* Waiting for jobs to finish would need to be done before
 	 * unregistering V3D.

drivers/gpu/drm/v3d/v3d_gemfs.c+0−62

@@ -1,62 +0,0 @@
1	// SPDX-License-Identifier: GPL-2.0+
2	/* Copyright (C) 2024 Raspberry Pi */
3
4	#include <linux/fs.h>
5	#include <linux/mount.h>
6	#include <linux/fs_context.h>
7
8	#include <drm/drm_print.h>
9
10	#include "v3d_drv.h"
11
12	void v3d_gemfs_init(struct v3d_dev *v3d)
13	{
14	struct file_system_type *type;
15	struct fs_context *fc;
16	struct vfsmount *gemfs;
17	int ret;
18
19	/*
20	* By creating our own shmemfs mountpoint, we can pass in
21	* mount flags that better match our usecase. However, we
22	* only do so on platforms which benefit from it.
23	*/
24	if (!IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE))
25	goto err;
26
27	/* The user doesn't want to enable Super Pages */
28	if (!super_pages)
29	goto err;
30
31	type = get_fs_type("tmpfs");
32	if (!type)
33	goto err;
34
35	fc = fs_context_for_mount(type, SB_KERNMOUNT);
36	if (IS_ERR(fc))
37	goto err;
38	ret = vfs_parse_fs_string(fc, "source", "tmpfs");
39	if (!ret)
40	ret = vfs_parse_fs_string(fc, "huge", "within_size");
41	if (!ret)
42	gemfs = fc_mount_longterm(fc);
43	put_fs_context(fc);
44	if (ret)
45	goto err;
46
47	v3d->gemfs = gemfs;
48	drm_info(&v3d->drm, "Using Transparent Hugepages\n");
49
50	return;
51
52	err:
53	v3d->gemfs = NULL;
54	drm_notice(&v3d->drm,
55	"Transparent Hugepage support is recommended for optimal performance on this platform!\n");
56	}
57
58	void v3d_gemfs_fini(struct v3d_dev *v3d)
59	{
60	if (v3d->gemfs)
61	kern_unmount(v3d->gemfs);
62	}

drivers/gpu/drm/vgem/Kconfig+9−0

@@ -0,0 +1,9 @@
	1	# SPDX-License-Identifier: GPL-2.0-only
	2	config DRM_VGEM
	3	tristate "Virtual GEM provider"
	4	depends on DRM && MMU
	5	select DRM_GEM_SHMEM_HELPER
	6	help
	7	Choose this option to get a virtual graphics memory manager,
	8	as used by Mesa's software renderer for enhanced performance.
	9	If M is selected the module will be called vgem.

drivers/gpu/drm/xe/xe_hw_fence.c+1−3

 {
 	struct xe_hw_fence *fence, *next;
 	unsigned long flags;
-	int err;
 	bool tmp;
 	if (XE_WARN_ON(!list_empty(&irq->pending))) {
 		spin_lock_irqsave(&irq->lock, flags);
 		list_for_each_entry_safe(fence, next, &irq->pending, irq_link) {
 			list_del_init(&fence->irq_link);
-			err = dma_fence_signal_locked(&fence->dma);
+			XE_WARN_ON(dma_fence_check_and_signal_locked(&fence->dma));
 			dma_fence_put(&fence->dma);
-			XE_WARN_ON(err);
 		}
 		spin_unlock_irqrestore(&irq->lock, flags);
 		dma_fence_end_signalling(tmp);

drivers/video/fbdev/core/fbcon.c+0−24

@@ -2289,28 +2289,6 @@ static bool fbcon_blank(struct vc_data *vc, enum vesa_blank_mode blank, · 2288 unmodified lines
2289	return false;	2289	return false;
2290	}	2290	}
2291		2291
2292	static void fbcon_debug_enter(struct vc_data *vc)
2293	{
2294	struct fb_info *info = fbcon_info_from_console(vc->vc_num);
2295	struct fbcon_par *par = info->fbcon_par;
2296
2297	par->save_graphics = par->graphics;
2298	par->graphics = 0;
2299	if (info->fbops->fb_debug_enter)
2300	info->fbops->fb_debug_enter(info);
2301	fbcon_set_palette(vc, color_table);
2302	}
2303
2304	static void fbcon_debug_leave(struct vc_data *vc)
2305	{
2306	struct fb_info *info = fbcon_info_from_console(vc->vc_num);
2307	struct fbcon_par *par = info->fbcon_par;
2308
2309	par->graphics = par->save_graphics;
2310	if (info->fbops->fb_debug_leave)
2311	info->fbops->fb_debug_leave(info);
2312	}
2313
2314	static int fbcon_get_font(struct vc_data vc, struct console_font font, unsigned int vpitch)	2292	static int fbcon_get_font(struct vc_data vc, struct console_font font, unsigned int vpitch)
2315	{	2293	{
2316	u8 *fontdata = vc->vc_font.data;	2294	u8 *fontdata = vc->vc_font.data;
@@ -3214,8 +3192,6 @@ static const struct consw fb_con = { · 897 unmodified lines
3214	.con_set_palette = fbcon_set_palette,	3192	.con_set_palette = fbcon_set_palette,
3215	.con_invert_region = fbcon_invert_region,	3193	.con_invert_region = fbcon_invert_region,
3216	.con_resize = fbcon_resize,	3194	.con_resize = fbcon_resize,
3217	.con_debug_enter = fbcon_debug_enter,
3218	.con_debug_leave = fbcon_debug_leave,
3219	};	3195	};
3220		3196
3221	static ssize_t rotate_store(struct device *device,	3197	static ssize_t rotate_store(struct device *device,

drivers/video/fbdev/core/fbcon.h+0−1

@@ -79,7 +79,6 @@ struct fbcon_par { · 78 unmodified lines
79	int cursor_reset;	79	int cursor_reset;
80	int blank_state;	80	int blank_state;
81	int graphics;	81	int graphics;
82	int save_graphics; /* for debug enter/leave */
83	bool initialized;	82	bool initialized;
84	int rotate;	83	int rotate;
85	int cur_rotate;	84	int cur_rotate;

include/drm/drm_atomic.h+5−0

  * drm_atomic_helper_wait_for_dependencies().
  */
 struct drm_private_obj {
+	/**
+	 * @dev: parent DRM device
+	 */
+	struct drm_device *dev;
 	/**
 	 * @head: List entry used to attach a private object to a &drm_device
 	 * (queued to &drm_mode_config.privobj_list).

include/drm/drm_bridge.h+12−0

 	 */
 	struct kref refcount;
+	/**
+	 * @unplugged:
+	 *
+	 * Flag to tell if the bridge has been unplugged.
+	 * See drm_bridge_enter() and drm_bridge_unplug().
+	 */
+	bool unplugged;
 	/** @driver_private: pointer to the bridge driver's internal context */
 	void *driver_private;
 	/** @ops: bitmask of operations supported by the bridge */
 	return container_of(priv, struct drm_bridge, base);
 }
+bool drm_bridge_enter(struct drm_bridge *bridge, int *idx);
+void drm_bridge_exit(int idx);
+void drm_bridge_unplug(struct drm_bridge *bridge);
 struct drm_bridge *drm_bridge_get(struct drm_bridge *bridge);
 void drm_bridge_put(struct drm_bridge *bridge);

include/drm/drm_device.h+15−0

@@ -3,6 +3,9 @@ · 2 unmodified lines
3		3
4	#include <linux/list.h>	4	#include <linux/list.h>
5	#include <linux/kref.h>	5	#include <linux/kref.h>
		6	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		7	#include <linux/mount.h>
		8	#endif
6	#include <linux/mutex.h>	9	#include <linux/mutex.h>
7	#include <linux/idr.h>	10	#include <linux/idr.h>
8	#include <linux/sched.h>	11	#include <linux/sched.h>
@@ -168,6 +171,18 @@ struct drm_device { · 159 unmodified lines
168	*/	171	*/
169	struct drm_master *master;	172	struct drm_master *master;
170		173
		174	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		175	/**
		176	* @huge_mnt:
		177	*
		178	* Huge tmpfs mountpoint used at GEM object initialization
		179	* drm_gem_object_init(). Drivers can call drm_gem_huge_mnt_create() to
		180	* create, mount and use it. The default tmpfs mountpoint (`shm_mnt`) is
		181	* used if NULL.
		182	*/
		183	struct vfsmount *huge_mnt;
		184	#endif
		185
171	/**	186	/**
172	* @driver_features: per-device driver features	187	* @driver_features: per-device driver features
173	*	188	*

include/drm/drm_fb_helper.h+0−21

 	 */
 	struct mutex lock;
-	/**
-	 * @kernel_fb_list:
-	 *
-	 * Entry on the global kernel_fb_helper_list, used for kgdb entry/exit.
-	 */
-	struct list_head kernel_fb_list;
 	/**
 	 * @delayed_hotplug:
 	 *
 	.fb_setcmap	= drm_fb_helper_setcmap, \
 	.fb_blank	= drm_fb_helper_blank, \
 	.fb_pan_display	= drm_fb_helper_pan_display, \
-	.fb_debug_enter = drm_fb_helper_debug_enter, \
-	.fb_debug_leave = drm_fb_helper_debug_leave, \
 	.fb_ioctl	= drm_fb_helper_ioctl
 #ifdef CONFIG_DRM_FBDEV_EMULATION
 int drm_fb_helper_hotplug_event(struct drm_fb_helper *fb_helper);
 int drm_fb_helper_initial_config(struct drm_fb_helper *fb_helper);
-int drm_fb_helper_debug_enter(struct fb_info *info);
-int drm_fb_helper_debug_leave(struct fb_info *info);
 #else
 static inline void drm_fb_helper_prepare(struct drm_device *dev,
 					 struct drm_fb_helper *helper,
 {
 	return 0;
 }
-static inline int drm_fb_helper_debug_enter(struct fb_info *info)
-{
-	return 0;
-}
-static inline int drm_fb_helper_debug_leave(struct fb_info *info)
-{
-	return 0;
-}
 #endif
 #endif

include/drm/drm_gem.h+42−3

@@ -40,6 +40,9 @@ · 39 unmodified lines
40	#include <linux/list.h>	40	#include <linux/list.h>
41	#include <linux/mutex.h>	41	#include <linux/mutex.h>
42		42
		43	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		44	#include <drm/drm_device.h>
		45	#endif
43	#include <drm/drm_vma_manager.h>	46	#include <drm/drm_vma_manager.h>
44		47
45	struct iosys_map;	48	struct iosys_map;
@@ -469,6 +472,7 @@ struct drm_gem_object { · 423 unmodified lines
469	.poll = drm_poll,\	472	.poll = drm_poll,\
470	.read = drm_read,\	473	.read = drm_read,\
471	.llseek = noop_llseek,\	474	.llseek = noop_llseek,\
		475	.get_unmapped_area = drm_gem_get_unmapped_area,\
472	.mmap = drm_gem_mmap, \	476	.mmap = drm_gem_mmap, \
473	.fop_flags = FOP_UNSIGNED_OFFSET	477	.fop_flags = FOP_UNSIGNED_OFFSET
474		478
@@ -491,13 +495,40 @@ struct drm_gem_object { · 16 unmodified lines
491	DRM_GEM_FOPS,\	495	DRM_GEM_FOPS,\
492	}	496	}
493		497
		498	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		499	int drm_gem_huge_mnt_create(struct drm_device dev, const char value);
		500	#else
		501	static inline int drm_gem_huge_mnt_create(struct drm_device *dev,
		502	const char *value)
		503	{
		504	return 0;
		505	}
		506	#endif
		507
		508	/**
		509	* drm_gem_get_huge_mnt - Get the huge tmpfs mountpoint used by a DRM device
		510	* @dev: DRM device
		511
		512	* This function gets the huge tmpfs mountpoint used by DRM device @dev. A huge
		513	* tmpfs mountpoint is used instead of `shm_mnt` after a successful call to
		514	* drm_gem_huge_mnt_create() when CONFIG_TRANSPARENT_HUGEPAGE is enabled.
		515
		516	* Returns:
		517	* The huge tmpfs mountpoint in use, NULL otherwise.
		518	*/
		519	static inline struct vfsmount drm_gem_get_huge_mnt(struct drm_device dev)
		520	{
		521	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		522	return dev->huge_mnt;
		523	#else
		524	return NULL;
		525	#endif
		526	}
		527
494	void drm_gem_object_release(struct drm_gem_object *obj);	528	void drm_gem_object_release(struct drm_gem_object *obj);
495	void drm_gem_object_free(struct kref *kref);	529	void drm_gem_object_free(struct kref *kref);
496	int drm_gem_object_init(struct drm_device *dev,	530	int drm_gem_object_init(struct drm_device *dev,
497	struct drm_gem_object *obj, size_t size);	531	struct drm_gem_object *obj, size_t size);
498	int drm_gem_object_init_with_mnt(struct drm_device *dev,
499	struct drm_gem_object *obj, size_t size,
500	struct vfsmount *gemfs);
501	void drm_gem_private_object_init(struct drm_device *dev,	532	void drm_gem_private_object_init(struct drm_device *dev,
502	struct drm_gem_object *obj, size_t size);	533	struct drm_gem_object *obj, size_t size);
503	void drm_gem_private_object_fini(struct drm_gem_object *obj);	534	void drm_gem_private_object_fini(struct drm_gem_object *obj);
@@ -507,6 +538,14 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, · 3 unmodified lines
507	struct vm_area_struct *vma);	538	struct vm_area_struct *vma);
508	int drm_gem_mmap(struct file filp, struct vm_area_struct vma);	539	int drm_gem_mmap(struct file filp, struct vm_area_struct vma);
509		540
		541	#ifdef CONFIG_MMU
		542	unsigned long drm_gem_get_unmapped_area(struct file *filp, unsigned long uaddr,
		543	unsigned long len, unsigned long pgoff,
		544	unsigned long flags);
		545	#else
		546	#define drm_gem_get_unmapped_area NULL
		547	#endif
		548
510	/**	549	/**
511	* drm_gem_object_get - acquire a GEM buffer object reference	550	* drm_gem_object_get - acquire a GEM buffer object reference
512	* @obj: GEM buffer object	551	* @obj: GEM buffer object

include/drm/drm_gem_shmem_helper.h+0−3

@@ -109,9 +109,6 @@ struct drm_gem_shmem_object { · 108 unmodified lines
109		109
110	int drm_gem_shmem_init(struct drm_device dev, struct drm_gem_shmem_object shmem, size_t size);	110	int drm_gem_shmem_init(struct drm_device dev, struct drm_gem_shmem_object shmem, size_t size);
111	struct drm_gem_shmem_object drm_gem_shmem_create(struct drm_device dev, size_t size);	111	struct drm_gem_shmem_object drm_gem_shmem_create(struct drm_device dev, size_t size);
112	struct drm_gem_shmem_object drm_gem_shmem_create_with_mnt(struct drm_device dev,
113	size_t size,
114	struct vfsmount *gemfs);
115	void drm_gem_shmem_release(struct drm_gem_shmem_object *shmem);	112	void drm_gem_shmem_release(struct drm_gem_shmem_object *shmem);
116	void drm_gem_shmem_free(struct drm_gem_shmem_object *shmem);	113	void drm_gem_shmem_free(struct drm_gem_shmem_object *shmem);
117		114

include/drm/drm_modeset_helper_vtables.h+0−23

@@ -52,11 +52,6 @@ struct drm_scanout_buffer; · 51 unmodified lines
52	struct drm_writeback_connector;	52	struct drm_writeback_connector;
53	struct drm_writeback_job;	53	struct drm_writeback_job;
54		54
55	enum mode_set_atomic {
56	LEAVE_ATOMIC_MODE_SET,
57	ENTER_ATOMIC_MODE_SET,
58	};
59
60	/**	55	/**
61	* struct drm_crtc_helper_funcs - helper operations for CRTCs	56	* struct drm_crtc_helper_funcs - helper operations for CRTCs
62	*	57	*
@@ -253,24 +248,6 @@ struct drm_crtc_helper_funcs { · 190 unmodified lines
253	int (mode_set_base)(struct drm_crtc crtc, int x, int y,	248	int (mode_set_base)(struct drm_crtc crtc, int x, int y,
254	struct drm_framebuffer *old_fb);	249	struct drm_framebuffer *old_fb);
255		250
256	/**
257	* @mode_set_base_atomic:
258	*
259	* This callback is used by the fbdev helpers to set a new framebuffer
260	* and scanout without sleeping, i.e. from an atomic calling context. It
261	* is only used to implement kgdb support.
262	*
263	* This callback is optional and only needed for kgdb support in the fbdev
264	* helpers.
265	*
266	* RETURNS:
267	*
268	* 0 on success or a negative error code on failure.
269	*/
270	int (mode_set_base_atomic)(struct drm_crtc crtc,
271	struct drm_framebuffer *fb, int x, int y,
272	enum mode_set_atomic);
273
274	/**	251	/**
275	* @disable:	252	* @disable:
276	*	253	*

include/drm/drm_vblank.h+1−2

 bool drm_crtc_handle_vblank(struct drm_crtc *crtc);
 int drm_crtc_vblank_get(struct drm_crtc *crtc);
 void drm_crtc_vblank_put(struct drm_crtc *crtc);
-void drm_wait_one_vblank(struct drm_device *dev, unsigned int pipe);
+int drm_crtc_wait_one_vblank(struct drm_crtc *crtc);
-void drm_crtc_wait_one_vblank(struct drm_crtc *crtc);
 void drm_crtc_vblank_off(struct drm_crtc *crtc);
 void drm_crtc_vblank_reset(struct drm_crtc *crtc);
 void drm_crtc_vblank_on_config(struct drm_crtc *crtc,

include/linux/dma-fence.h+28−7

 static inline void __dma_fence_might_wait(void) {}
 #endif
-int dma_fence_signal(struct dma_fence *fence);
+void dma_fence_signal(struct dma_fence *fence);
-int dma_fence_signal_locked(struct dma_fence *fence);
+bool dma_fence_check_and_signal(struct dma_fence *fence);
-int dma_fence_signal_timestamp(struct dma_fence *fence, ktime_t timestamp);
+bool dma_fence_check_and_signal_locked(struct dma_fence *fence);
-int dma_fence_signal_timestamp_locked(struct dma_fence *fence,
+void dma_fence_signal_locked(struct dma_fence *fence);
-				      ktime_t timestamp);
+void dma_fence_signal_timestamp(struct dma_fence *fence, ktime_t timestamp);
+void dma_fence_signal_timestamp_locked(struct dma_fence *fence, ktime_t timestamp);
 signed long dma_fence_default_wait(struct dma_fence *fence,
 				   bool intr, signed long timeout);
 int dma_fence_add_callback(struct dma_fence *fence,
 const char __rcu *dma_fence_driver_name(struct dma_fence *fence);
 const char __rcu *dma_fence_timeline_name(struct dma_fence *fence);
+/*
+ * dma_fence_test_signaled_flag - Only check whether a fence is signaled yet.
+ * @fence: the fence to check
+ *
+ * This function just checks whether @fence is signaled, without interacting
+ * with the fence in any way. The user must, therefore, ensure through other
+ * means that fences get signaled eventually.
+ *
+ * This function uses test_bit(), which is thread-safe. Naturally, this function
+ * should be used opportunistically; a fence could get signaled at any moment
+ * after the check is done.
+ *
+ * Return: true if signaled, false otherwise.
+ */
+static inline bool
+dma_fence_test_signaled_flag(struct dma_fence *fence)
+{
+	return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags);
+}
 /**
  * dma_fence_is_signaled_locked - Return an indication if the fence
  *                                is signaled yet.
 static inline bool
 dma_fence_is_signaled_locked(struct dma_fence *fence)
 {
-	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
+	if (dma_fence_test_signaled_flag(fence))
 		return true;
 	if (fence->ops->signaled && fence->ops->signaled(fence)) {
 static inline bool
 dma_fence_is_signaled(struct dma_fence *fence)
 {
-	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
+	if (dma_fence_test_signaled_flag(fence))
 		return true;
 	if (fence->ops->signaled && fence->ops->signaled(fence)) {

include/linux/fb.h+0−4

@@ -304,10 +304,6 @@ struct fb_ops { · 303 unmodified lines
304		304
305	/* teardown any resources to do with this framebuffer */	305	/* teardown any resources to do with this framebuffer */
306	void (fb_destroy)(struct fb_info info);	306	void (fb_destroy)(struct fb_info info);
307
308	/* called at KDB enter and leave time to prepare the console */
309	int (fb_debug_enter)(struct fb_info info);
310	int (fb_debug_leave)(struct fb_info info);
311	};	307	};
312		308
313	#ifdef CONFIG_FB_TILEBLITTING	309	#ifdef CONFIG_FB_TILEBLITTING

include/uapi/drm/panfrost_drm.h+75−1

@@ -24,6 +24,8 @@ extern "C" { · 23 unmodified lines
24	#define DRM_PANFROST_SET_LABEL_BO 0x09	24	#define DRM_PANFROST_SET_LABEL_BO 0x09
25	#define DRM_PANFROST_JM_CTX_CREATE 0x0a	25	#define DRM_PANFROST_JM_CTX_CREATE 0x0a
26	#define DRM_PANFROST_JM_CTX_DESTROY 0x0b	26	#define DRM_PANFROST_JM_CTX_DESTROY 0x0b
		27	#define DRM_PANFROST_SYNC_BO 0x0c
		28	#define DRM_PANFROST_QUERY_BO_INFO 0x0d
27		29
28	#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)	30	#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)
29	#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)	31	#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)
@@ -35,6 +37,8 @@ extern "C" { · 5 unmodified lines
35	#define DRM_IOCTL_PANFROST_SET_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SET_LABEL_BO, struct drm_panfrost_set_label_bo)	37	#define DRM_IOCTL_PANFROST_SET_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SET_LABEL_BO, struct drm_panfrost_set_label_bo)
36	#define DRM_IOCTL_PANFROST_JM_CTX_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_CREATE, struct drm_panfrost_jm_ctx_create)	38	#define DRM_IOCTL_PANFROST_JM_CTX_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_CREATE, struct drm_panfrost_jm_ctx_create)
37	#define DRM_IOCTL_PANFROST_JM_CTX_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_DESTROY, struct drm_panfrost_jm_ctx_destroy)	39	#define DRM_IOCTL_PANFROST_JM_CTX_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_DESTROY, struct drm_panfrost_jm_ctx_destroy)
		40	#define DRM_IOCTL_PANFROST_SYNC_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SYNC_BO, struct drm_panfrost_sync_bo)
		41	#define DRM_IOCTL_PANFROST_QUERY_BO_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_QUERY_BO_INFO, struct drm_panfrost_query_bo_info)
38		42
39	/*	43	/*
40	* Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module	44	* Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module
@@ -120,9 +124,12 @@ struct drm_panfrost_wait_bo { · 79 unmodified lines
120	__s64 timeout_ns;	124	__s64 timeout_ns;
121	};	125	};
122		126
123	/* Valid flags to pass to drm_panfrost_create_bo */	127	/* Valid flags to pass to drm_panfrost_create_bo.
		128	* PANFROST_BO_WB_MMAP can't be set if PANFROST_BO_HEAP is.
		129	*/
124	#define PANFROST_BO_NOEXEC 1	130	#define PANFROST_BO_NOEXEC 1
125	#define PANFROST_BO_HEAP 2	131	#define PANFROST_BO_HEAP 2
		132	#define PANFROST_BO_WB_MMAP 4
126		133
127	/**	134	/**
128	* struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs.	135	* struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs.
@@ -228,6 +235,13 @@ enum drm_panfrost_param { · 99 unmodified lines
228	DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP,	235	DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP,
229	DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP_FREQUENCY,	236	DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP_FREQUENCY,
230	DRM_PANFROST_PARAM_ALLOWED_JM_CTX_PRIORITIES,	237	DRM_PANFROST_PARAM_ALLOWED_JM_CTX_PRIORITIES,
		238	DRM_PANFROST_PARAM_SELECTED_COHERENCY,
		239	};
		240
		241	enum drm_panfrost_gpu_coherency {
		242	DRM_PANFROST_GPU_COHERENCY_ACE_LITE = 0,
		243	DRM_PANFROST_GPU_COHERENCY_ACE = 1,
		244	DRM_PANFROST_GPU_COHERENCY_NONE = 31,
231	};	245	};
232		246
233	struct drm_panfrost_get_param {	247	struct drm_panfrost_get_param {
@@ -301,6 +315,66 @@ struct drm_panfrost_set_label_bo { · 67 unmodified lines
301	__u64 label;	315	__u64 label;
302	};	316	};
303		317
		318	/* Valid flags to pass to drm_panfrost_bo_sync_op */
		319	#define PANFROST_BO_SYNC_CPU_CACHE_FLUSH 0
		320	#define PANFROST_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE 1
		321
		322	/**
		323	* struct drm_panthor_bo_flush_map_op - BO map sync op
		324	*/
		325	struct drm_panfrost_bo_sync_op {
		326	/** @handle: Handle of the buffer object to sync. */
		327	__u32 handle;
		328
		329	/** @type: Type of sync operation. */
		330	__u32 type;
		331
		332	/**
		333	* @offset: Offset into the BO at which the sync range starts.
		334	*
		335	* This will be rounded down to the nearest cache line as needed.
		336	*/
		337	__u32 offset;
		338
		339	/**
		340	* @size: Size of the range to sync
		341	*
		342	* @size + @offset will be rounded up to the nearest cache line as
		343	* needed.
		344	*/
		345	__u32 size;
		346	};
		347
		348	/**
		349	* struct drm_panfrost_sync_bo - ioctl argument for syncing BO maps
		350	*/
		351	struct drm_panfrost_sync_bo {
		352	/** Array of struct drm_panfrost_bo_sync_op */
		353	__u64 ops;
		354
		355	/** Number of BO sync ops */
		356	__u32 op_count;
		357
		358	__u32 pad;
		359	};
		360
		361	/** BO comes from a different subsystem. */
		362	#define DRM_PANFROST_BO_IS_IMPORTED (1 << 0)
		363
		364	struct drm_panfrost_query_bo_info {
		365	/** Handle of the object being queried. */
		366	__u32 handle;
		367
		368	/** Extra flags that are not coming from the BO_CREATE ioctl(). */
		369	__u32 extra_flags;
		370
		371	/** Flags passed at creation time. */
		372	__u32 create_flags;
		373
		374	/** Will be zero on return. */
		375	__u32 pad;
		376	};
		377
304	/* Definitions for coredump decoding in user space */	378	/* Definitions for coredump decoding in user space */
305	#define PANFROSTDUMP_MAJOR 1	379	#define PANFROSTDUMP_MAJOR 1
306	#define PANFROSTDUMP_MINOR 0	380	#define PANFROSTDUMP_MINOR 0

include/uapi/drm/panthor_drm.h+154−3

@@ -144,6 +144,16 @@ enum drm_panthor_ioctl_id { · 143 unmodified lines
144	* pgoff_t size.	144	* pgoff_t size.
145	*/	145	*/
146	DRM_PANTHOR_SET_USER_MMIO_OFFSET,	146	DRM_PANTHOR_SET_USER_MMIO_OFFSET,
		147
		148	/** @DRM_PANTHOR_BO_SYNC: Sync BO data to/from the device */
		149	DRM_PANTHOR_BO_SYNC,
		150
		151	/**
		152	* @DRM_PANTHOR_BO_QUERY_INFO: Query information about a BO.
		153	*
		154	* This is useful for imported BOs.
		155	*/
		156	DRM_PANTHOR_BO_QUERY_INFO,
147	};	157	};
148		158
149	/**	159	/**
@@ -245,6 +255,26 @@ enum drm_panthor_dev_query_type { · 95 unmodified lines
245	DRM_PANTHOR_DEV_QUERY_GROUP_PRIORITIES_INFO,	255	DRM_PANTHOR_DEV_QUERY_GROUP_PRIORITIES_INFO,
246	};	256	};
247		257
		258	/**
		259	* enum drm_panthor_gpu_coherency: Type of GPU coherency
		260	*/
		261	enum drm_panthor_gpu_coherency {
		262	/**
		263	* @DRM_PANTHOR_GPU_COHERENCY_ACE_LITE: ACE Lite coherency.
		264	*/
		265	DRM_PANTHOR_GPU_COHERENCY_ACE_LITE = 0,
		266
		267	/**
		268	* @DRM_PANTHOR_GPU_COHERENCY_ACE: ACE coherency.
		269	*/
		270	DRM_PANTHOR_GPU_COHERENCY_ACE = 1,
		271
		272	/**
		273	* @DRM_PANTHOR_GPU_COHERENCY_NONE: No coherency.
		274	*/
		275	DRM_PANTHOR_GPU_COHERENCY_NONE = 31,
		276	};
		277
248	/**	278	/**
249	* struct drm_panthor_gpu_info - GPU information	279	* struct drm_panthor_gpu_info - GPU information
250	*	280	*
@@ -301,7 +331,16 @@ struct drm_panthor_gpu_info { · 50 unmodified lines
301	*/	331	*/
302	__u32 thread_max_barrier_size;	332	__u32 thread_max_barrier_size;
303		333
304	/** @coherency_features: Coherency features. */	334	/**
		335	* @coherency_features: Coherency features.
		336	*
		337	* Combination of drm_panthor_gpu_coherency flags.
		338	*
		339	* Note that this is just what the coherency protocols supported by the
		340	* GPU, but the actual coherency in place depends on the SoC
		341	* integration and is reflected by
		342	* drm_panthor_gpu_info::selected_coherency.
		343	*/
305	__u32 coherency_features;	344	__u32 coherency_features;
306		345
307	/** @texture_features: Texture features. */	346	/** @texture_features: Texture features. */
@@ -310,8 +349,12 @@ struct drm_panthor_gpu_info { · 2 unmodified lines
310	/** @as_present: Bitmask encoding the number of address-space exposed by the MMU. */	349	/** @as_present: Bitmask encoding the number of address-space exposed by the MMU. */
311	__u32 as_present;	350	__u32 as_present;
312		351
313	/** @pad0: MBZ. */	352	/**
314	__u32 pad0;	353	* @select_coherency: Coherency selected for this device.
		354	*
		355	* One of drm_panthor_gpu_coherency.
		356	*/
		357	__u32 selected_coherency;
315		358
316	/** @shader_present: Bitmask encoding the shader cores exposed by the GPU. */	359	/** @shader_present: Bitmask encoding the shader cores exposed by the GPU. */
317	__u64 shader_present;	360	__u64 shader_present;
@@ -638,6 +681,15 @@ struct drm_panthor_vm_get_state { · 320 unmodified lines
638	enum drm_panthor_bo_flags {	681	enum drm_panthor_bo_flags {
639	/** @DRM_PANTHOR_BO_NO_MMAP: The buffer object will never be CPU-mapped in userspace. */	682	/** @DRM_PANTHOR_BO_NO_MMAP: The buffer object will never be CPU-mapped in userspace. */
640	DRM_PANTHOR_BO_NO_MMAP = (1 << 0),	683	DRM_PANTHOR_BO_NO_MMAP = (1 << 0),
		684
		685	/**
		686	* @DRM_PANTHOR_BO_WB_MMAP: Force "Write-Back Cacheable" CPU mapping.
		687	*
		688	* CPU map the buffer object in userspace by forcing the "Write-Back
		689	* Cacheable" cacheability attribute. The mapping otherwise uses the
		690	* "Non-Cacheable" attribute if the GPU is not IO coherent.
		691	*/
		692	DRM_PANTHOR_BO_WB_MMAP = (1 << 1),
641	};	693	};
642		694
643	/**	695	/**
@@ -1040,6 +1092,101 @@ struct drm_panthor_set_user_mmio_offset { · 396 unmodified lines
1040	__u64 offset;	1092	__u64 offset;
1041	};	1093	};
1042		1094
		1095	/**
		1096	* enum drm_panthor_bo_sync_op_type - BO sync type
		1097	*/
		1098	enum drm_panthor_bo_sync_op_type {
		1099	/** @DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH: Flush CPU caches. */
		1100	DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH = 0,
		1101
		1102	/** @DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE: Flush and invalidate CPU caches. */
		1103	DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE = 1,
		1104	};
		1105
		1106	/**
		1107	* struct drm_panthor_bo_sync_op - BO map sync op
		1108	*/
		1109	struct drm_panthor_bo_sync_op {
		1110	/** @handle: Handle of the buffer object to sync. */
		1111	__u32 handle;
		1112
		1113	/** @type: Type of operation. */
		1114	__u32 type;
		1115
		1116	/**
		1117	* @offset: Offset into the BO at which the sync range starts.
		1118	*
		1119	* This will be rounded down to the nearest cache line as needed.
		1120	*/
		1121	__u64 offset;
		1122
		1123	/**
		1124	* @size: Size of the range to sync
		1125	*
		1126	* @size + @offset will be rounded up to the nearest cache line as
		1127	* needed.
		1128	*/
		1129	__u64 size;
		1130	};
		1131
		1132	/**
		1133	* struct drm_panthor_bo_sync - BO map sync request
		1134	*/
		1135	struct drm_panthor_bo_sync {
		1136	/**
		1137	* @ops: Array of struct drm_panthor_bo_sync_op sync operations.
		1138	*/
		1139	struct drm_panthor_obj_array ops;
		1140	};
		1141
		1142	/**
		1143	* enum drm_panthor_bo_extra_flags - Set of flags returned on a BO_QUERY_INFO request
		1144	*
		1145	* Those are flags reflecting BO properties that are not directly coming from the flags
		1146	* passed are creation time, or information on BOs that were imported from other drivers.
		1147	*/
		1148	enum drm_panthor_bo_extra_flags {
		1149	/**
		1150	* @DRM_PANTHOR_BO_IS_IMPORTED: BO has been imported from an external driver.
		1151	*
		1152	* Note that imported dma-buf handles are not flagged as imported if they
		1153	* where exported by panthor. Only buffers that are coming from other drivers
		1154	* (dma heaps, other GPUs, display controllers, V4L, ...).
		1155	*
		1156	* It's also important to note that all imported BOs are mapped cached and can't
		1157	* be considered IO-coherent even if the GPU is. This means they require explicit
		1158	* syncs that must go through the DRM_PANTHOR_BO_SYNC ioctl (userland cache
		1159	* maintenance is not allowed in that case, because extra operations might be
		1160	* needed to make changes visible to the CPU/device, like buffer migration when the
		1161	* exporter is a GPU with its own VRAM).
		1162	*/
		1163	DRM_PANTHOR_BO_IS_IMPORTED = (1 << 0),
		1164	};
		1165
		1166	/**
		1167	* struct drm_panthor_bo_query_info - Query BO info
		1168	*/
		1169	struct drm_panthor_bo_query_info {
		1170	/** @handle: Handle of the buffer object to query flags on. */
		1171	__u32 handle;
		1172
		1173	/**
		1174	* @extra_flags: Combination of enum drm_panthor_bo_extra_flags flags.
		1175	*/
		1176	__u32 extra_flags;
		1177
		1178	/**
		1179	* @create_flags: Flags passed at creation time.
		1180	*
		1181	* Combination of enum drm_panthor_bo_flags flags.
		1182	* Will be zero if the buffer comes from a different driver.
		1183	*/
		1184	__u32 create_flags;
		1185
		1186	/** @pad: Will be zero on return. */
		1187	__u32 pad;
		1188	};
		1189
1043	/**	1190	/**
1044	* DRM_IOCTL_PANTHOR() - Build a Panthor IOCTL number	1191	* DRM_IOCTL_PANTHOR() - Build a Panthor IOCTL number
1045	* @__access: Access type. Must be R, W or RW.	1192	* @__access: Access type. Must be R, W or RW.
@@ -1086,6 +1233,10 @@ enum { · 40 unmodified lines
1086	DRM_IOCTL_PANTHOR(WR, BO_SET_LABEL, bo_set_label),	1233	DRM_IOCTL_PANTHOR(WR, BO_SET_LABEL, bo_set_label),
1087	DRM_IOCTL_PANTHOR_SET_USER_MMIO_OFFSET =	1234	DRM_IOCTL_PANTHOR_SET_USER_MMIO_OFFSET =
1088	DRM_IOCTL_PANTHOR(WR, SET_USER_MMIO_OFFSET, set_user_mmio_offset),	1235	DRM_IOCTL_PANTHOR(WR, SET_USER_MMIO_OFFSET, set_user_mmio_offset),
		1236	DRM_IOCTL_PANTHOR_BO_SYNC =
		1237	DRM_IOCTL_PANTHOR(WR, BO_SYNC, bo_sync),
		1238	DRM_IOCTL_PANTHOR_BO_QUERY_INFO =
		1239	DRM_IOCTL_PANTHOR(WR, BO_QUERY_INFO, bo_query_info),
1089	};	1240	};
1090		1241
1091	#if defined(__cplusplus)	1242	#if defined(__cplusplus)

Merge tag 'drm-misc-next-2025-12-12' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next

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