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bus: mhi: core: Add support for ringing channel/event ring doorbells

This commit adds support for ringing channel and event ring doorbells by MHI host. The MHI host can use the channel and event ring doorbells for notifying the client device about processing transfer and event rings which it has queued using MMIO registers. This is based on the patch submitted by Sujeev Dias: https://lkml.org/lkml/2018/7/9/989

Manivannan Sadhasivam committed 6 years ago

Commit 6cd330a1 parent da1c4f84 files · +545 −0Browse files

Unified · Split

4 files
  1. drivers/bus/mhi/core/init.c +141 −0
  2. drivers/bus/mhi/core/internal.h +282 −0
  3. drivers/bus/mhi/core/main.c +118 −0
  4. include/linux/mhi.h +4 −0
drivers/bus/mhi/core/init.c+141−0
@@ -17,6 +17,137 @@ · 16 unmodified lines
17#include <linux/wait.h>17#include <linux/wait.h>
18#include "internal.h"18#include "internal.h"
19 19
20int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
21{
22 u32 val;
23 int i, ret;
24 struct mhi_chan *mhi_chan;
25 struct mhi_event *mhi_event;
26 void __iomem *base = mhi_cntrl->regs;
27 struct device *dev = &mhi_cntrl->mhi_dev->dev;
28 struct {
29 u32 offset;
30 u32 mask;
31 u32 shift;
32 u32 val;
33 } reg_info[] = {
34 {
35 CCABAP_HIGHER, U32_MAX, 0,
36 upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
37 },
38 {
39 CCABAP_LOWER, U32_MAX, 0,
40 lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
41 },
42 {
43 ECABAP_HIGHER, U32_MAX, 0,
44 upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
45 },
46 {
47 ECABAP_LOWER, U32_MAX, 0,
48 lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
49 },
50 {
51 CRCBAP_HIGHER, U32_MAX, 0,
52 upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
53 },
54 {
55 CRCBAP_LOWER, U32_MAX, 0,
56 lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
57 },
58 {
59 MHICFG, MHICFG_NER_MASK, MHICFG_NER_SHIFT,
60 mhi_cntrl->total_ev_rings,
61 },
62 {
63 MHICFG, MHICFG_NHWER_MASK, MHICFG_NHWER_SHIFT,
64 mhi_cntrl->hw_ev_rings,
65 },
66 {
67 MHICTRLBASE_HIGHER, U32_MAX, 0,
68 upper_32_bits(mhi_cntrl->iova_start),
69 },
70 {
71 MHICTRLBASE_LOWER, U32_MAX, 0,
72 lower_32_bits(mhi_cntrl->iova_start),
73 },
74 {
75 MHIDATABASE_HIGHER, U32_MAX, 0,
76 upper_32_bits(mhi_cntrl->iova_start),
77 },
78 {
79 MHIDATABASE_LOWER, U32_MAX, 0,
80 lower_32_bits(mhi_cntrl->iova_start),
81 },
82 {
83 MHICTRLLIMIT_HIGHER, U32_MAX, 0,
84 upper_32_bits(mhi_cntrl->iova_stop),
85 },
86 {
87 MHICTRLLIMIT_LOWER, U32_MAX, 0,
88 lower_32_bits(mhi_cntrl->iova_stop),
89 },
90 {
91 MHIDATALIMIT_HIGHER, U32_MAX, 0,
92 upper_32_bits(mhi_cntrl->iova_stop),
93 },
94 {
95 MHIDATALIMIT_LOWER, U32_MAX, 0,
96 lower_32_bits(mhi_cntrl->iova_stop),
97 },
98 { 0, 0, 0 }
99 };
100
101 dev_dbg(dev, "Initializing MHI registers\n");
102
103 /* Read channel db offset */
104 ret = mhi_read_reg_field(mhi_cntrl, base, CHDBOFF, CHDBOFF_CHDBOFF_MASK,
105 CHDBOFF_CHDBOFF_SHIFT, &val);
106 if (ret) {
107 dev_err(dev, "Unable to read CHDBOFF register\n");
108 return -EIO;
109 }
110
111 /* Setup wake db */
112 mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
113 mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0);
114 mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0);
115 mhi_cntrl->wake_set = false;
116
117 /* Setup channel db address for each channel in tre_ring */
118 mhi_chan = mhi_cntrl->mhi_chan;
119 for (i = 0; i < mhi_cntrl->max_chan; i++, val += 8, mhi_chan++)
120 mhi_chan->tre_ring.db_addr = base + val;
121
122 /* Read event ring db offset */
123 ret = mhi_read_reg_field(mhi_cntrl, base, ERDBOFF, ERDBOFF_ERDBOFF_MASK,
124 ERDBOFF_ERDBOFF_SHIFT, &val);
125 if (ret) {
126 dev_err(dev, "Unable to read ERDBOFF register\n");
127 return -EIO;
128 }
129
130 /* Setup event db address for each ev_ring */
131 mhi_event = mhi_cntrl->mhi_event;
132 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) {
133 if (mhi_event->offload_ev)
134 continue;
135
136 mhi_event->ring.db_addr = base + val;
137 }
138
139 /* Setup DB register for primary CMD rings */
140 mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER;
141
142 /* Write to MMIO registers */
143 for (i = 0; reg_info[i].offset; i++)
144 mhi_write_reg_field(mhi_cntrl, base, reg_info[i].offset,
145 reg_info[i].mask, reg_info[i].shift,
146 reg_info[i].val);
147
148 return 0;
149}
150
20static int parse_ev_cfg(struct mhi_controller *mhi_cntrl,151static int parse_ev_cfg(struct mhi_controller *mhi_cntrl,
21 struct mhi_controller_config *config)152 struct mhi_controller_config *config)
22{153{
@@ -62,6 +193,11 @@ static int parse_ev_cfg(struct mhi_controller *mhi_cntrl, · 39 unmodified lines
62 if (MHI_INVALID_BRSTMODE(mhi_event->db_cfg.brstmode))193 if (MHI_INVALID_BRSTMODE(mhi_event->db_cfg.brstmode))
63 goto error_ev_cfg;194 goto error_ev_cfg;
64 195
196 if (mhi_event->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
197 mhi_event->db_cfg.process_db = mhi_db_brstmode;
198 else
199 mhi_event->db_cfg.process_db = mhi_db_brstmode_disable;
200
65 mhi_event->data_type = event_cfg->data_type;201 mhi_event->data_type = event_cfg->data_type;
66 202
67 mhi_event->hw_ring = event_cfg->hardware_event;203 mhi_event->hw_ring = event_cfg->hardware_event;
@@ -185,6 +321,11 @@ static int parse_ch_cfg(struct mhi_controller *mhi_cntrl, · 117 unmodified lines
185 }321 }
186 }322 }
187 323
324 if (mhi_chan->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
325 mhi_chan->db_cfg.process_db = mhi_db_brstmode;
326 else
327 mhi_chan->db_cfg.process_db = mhi_db_brstmode_disable;
328
188 mhi_chan->configured = true;329 mhi_chan->configured = true;
189 330
190 if (mhi_chan->lpm_notify)331 if (mhi_chan->lpm_notify)
drivers/bus/mhi/core/internal.h+282−0
@@ -11,6 +11,262 @@ · 10 unmodified lines
11 11
12extern struct bus_type mhi_bus_type;12extern struct bus_type mhi_bus_type;
13 13
14/* MHI MMIO register mapping */
15#define PCI_INVALID_READ(val) (val == U32_MAX)
16
17#define MHIREGLEN (0x0)
18#define MHIREGLEN_MHIREGLEN_MASK (0xFFFFFFFF)
19#define MHIREGLEN_MHIREGLEN_SHIFT (0)
20
21#define MHIVER (0x8)
22#define MHIVER_MHIVER_MASK (0xFFFFFFFF)
23#define MHIVER_MHIVER_SHIFT (0)
24
25#define MHICFG (0x10)
26#define MHICFG_NHWER_MASK (0xFF000000)
27#define MHICFG_NHWER_SHIFT (24)
28#define MHICFG_NER_MASK (0xFF0000)
29#define MHICFG_NER_SHIFT (16)
30#define MHICFG_NHWCH_MASK (0xFF00)
31#define MHICFG_NHWCH_SHIFT (8)
32#define MHICFG_NCH_MASK (0xFF)
33#define MHICFG_NCH_SHIFT (0)
34
35#define CHDBOFF (0x18)
36#define CHDBOFF_CHDBOFF_MASK (0xFFFFFFFF)
37#define CHDBOFF_CHDBOFF_SHIFT (0)
38
39#define ERDBOFF (0x20)
40#define ERDBOFF_ERDBOFF_MASK (0xFFFFFFFF)
41#define ERDBOFF_ERDBOFF_SHIFT (0)
42
43#define BHIOFF (0x28)
44#define BHIOFF_BHIOFF_MASK (0xFFFFFFFF)
45#define BHIOFF_BHIOFF_SHIFT (0)
46
47#define BHIEOFF (0x2C)
48#define BHIEOFF_BHIEOFF_MASK (0xFFFFFFFF)
49#define BHIEOFF_BHIEOFF_SHIFT (0)
50
51#define DEBUGOFF (0x30)
52#define DEBUGOFF_DEBUGOFF_MASK (0xFFFFFFFF)
53#define DEBUGOFF_DEBUGOFF_SHIFT (0)
54
55#define MHICTRL (0x38)
56#define MHICTRL_MHISTATE_MASK (0x0000FF00)
57#define MHICTRL_MHISTATE_SHIFT (8)
58#define MHICTRL_RESET_MASK (0x2)
59#define MHICTRL_RESET_SHIFT (1)
60
61#define MHISTATUS (0x48)
62#define MHISTATUS_MHISTATE_MASK (0x0000FF00)
63#define MHISTATUS_MHISTATE_SHIFT (8)
64#define MHISTATUS_SYSERR_MASK (0x4)
65#define MHISTATUS_SYSERR_SHIFT (2)
66#define MHISTATUS_READY_MASK (0x1)
67#define MHISTATUS_READY_SHIFT (0)
68
69#define CCABAP_LOWER (0x58)
70#define CCABAP_LOWER_CCABAP_LOWER_MASK (0xFFFFFFFF)
71#define CCABAP_LOWER_CCABAP_LOWER_SHIFT (0)
72
73#define CCABAP_HIGHER (0x5C)
74#define CCABAP_HIGHER_CCABAP_HIGHER_MASK (0xFFFFFFFF)
75#define CCABAP_HIGHER_CCABAP_HIGHER_SHIFT (0)
76
77#define ECABAP_LOWER (0x60)
78#define ECABAP_LOWER_ECABAP_LOWER_MASK (0xFFFFFFFF)
79#define ECABAP_LOWER_ECABAP_LOWER_SHIFT (0)
80
81#define ECABAP_HIGHER (0x64)
82#define ECABAP_HIGHER_ECABAP_HIGHER_MASK (0xFFFFFFFF)
83#define ECABAP_HIGHER_ECABAP_HIGHER_SHIFT (0)
84
85#define CRCBAP_LOWER (0x68)
86#define CRCBAP_LOWER_CRCBAP_LOWER_MASK (0xFFFFFFFF)
87#define CRCBAP_LOWER_CRCBAP_LOWER_SHIFT (0)
88
89#define CRCBAP_HIGHER (0x6C)
90#define CRCBAP_HIGHER_CRCBAP_HIGHER_MASK (0xFFFFFFFF)
91#define CRCBAP_HIGHER_CRCBAP_HIGHER_SHIFT (0)
92
93#define CRDB_LOWER (0x70)
94#define CRDB_LOWER_CRDB_LOWER_MASK (0xFFFFFFFF)
95#define CRDB_LOWER_CRDB_LOWER_SHIFT (0)
96
97#define CRDB_HIGHER (0x74)
98#define CRDB_HIGHER_CRDB_HIGHER_MASK (0xFFFFFFFF)
99#define CRDB_HIGHER_CRDB_HIGHER_SHIFT (0)
100
101#define MHICTRLBASE_LOWER (0x80)
102#define MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_MASK (0xFFFFFFFF)
103#define MHICTRLBASE_LOWER_MHICTRLBASE_LOWER_SHIFT (0)
104
105#define MHICTRLBASE_HIGHER (0x84)
106#define MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_MASK (0xFFFFFFFF)
107#define MHICTRLBASE_HIGHER_MHICTRLBASE_HIGHER_SHIFT (0)
108
109#define MHICTRLLIMIT_LOWER (0x88)
110#define MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_MASK (0xFFFFFFFF)
111#define MHICTRLLIMIT_LOWER_MHICTRLLIMIT_LOWER_SHIFT (0)
112
113#define MHICTRLLIMIT_HIGHER (0x8C)
114#define MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_MASK (0xFFFFFFFF)
115#define MHICTRLLIMIT_HIGHER_MHICTRLLIMIT_HIGHER_SHIFT (0)
116
117#define MHIDATABASE_LOWER (0x98)
118#define MHIDATABASE_LOWER_MHIDATABASE_LOWER_MASK (0xFFFFFFFF)
119#define MHIDATABASE_LOWER_MHIDATABASE_LOWER_SHIFT (0)
120
121#define MHIDATABASE_HIGHER (0x9C)
122#define MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_MASK (0xFFFFFFFF)
123#define MHIDATABASE_HIGHER_MHIDATABASE_HIGHER_SHIFT (0)
124
125#define MHIDATALIMIT_LOWER (0xA0)
126#define MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_MASK (0xFFFFFFFF)
127#define MHIDATALIMIT_LOWER_MHIDATALIMIT_LOWER_SHIFT (0)
128
129#define MHIDATALIMIT_HIGHER (0xA4)
130#define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_MASK (0xFFFFFFFF)
131#define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_SHIFT (0)
132
133/* Host request register */
134#define MHI_SOC_RESET_REQ_OFFSET (0xB0)
135#define MHI_SOC_RESET_REQ BIT(0)
136
137/* MHI BHI offfsets */
138#define BHI_BHIVERSION_MINOR (0x00)
139#define BHI_BHIVERSION_MAJOR (0x04)
140#define BHI_IMGADDR_LOW (0x08)
141#define BHI_IMGADDR_HIGH (0x0C)
142#define BHI_IMGSIZE (0x10)
143#define BHI_RSVD1 (0x14)
144#define BHI_IMGTXDB (0x18)
145#define BHI_TXDB_SEQNUM_BMSK (0x3FFFFFFF)
146#define BHI_TXDB_SEQNUM_SHFT (0)
147#define BHI_RSVD2 (0x1C)
148#define BHI_INTVEC (0x20)
149#define BHI_RSVD3 (0x24)
150#define BHI_EXECENV (0x28)
151#define BHI_STATUS (0x2C)
152#define BHI_ERRCODE (0x30)
153#define BHI_ERRDBG1 (0x34)
154#define BHI_ERRDBG2 (0x38)
155#define BHI_ERRDBG3 (0x3C)
156#define BHI_SERIALNU (0x40)
157#define BHI_SBLANTIROLLVER (0x44)
158#define BHI_NUMSEG (0x48)
159#define BHI_MSMHWID(n) (0x4C + (0x4 * n))
160#define BHI_OEMPKHASH(n) (0x64 + (0x4 * n))
161#define BHI_RSVD5 (0xC4)
162#define BHI_STATUS_MASK (0xC0000000)
163#define BHI_STATUS_SHIFT (30)
164#define BHI_STATUS_ERROR (3)
165#define BHI_STATUS_SUCCESS (2)
166#define BHI_STATUS_RESET (0)
167
168/* MHI BHIE offsets */
169#define BHIE_MSMSOCID_OFFS (0x0000)
170#define BHIE_TXVECADDR_LOW_OFFS (0x002C)
171#define BHIE_TXVECADDR_HIGH_OFFS (0x0030)
172#define BHIE_TXVECSIZE_OFFS (0x0034)
173#define BHIE_TXVECDB_OFFS (0x003C)
174#define BHIE_TXVECDB_SEQNUM_BMSK (0x3FFFFFFF)
175#define BHIE_TXVECDB_SEQNUM_SHFT (0)
176#define BHIE_TXVECSTATUS_OFFS (0x0044)
177#define BHIE_TXVECSTATUS_SEQNUM_BMSK (0x3FFFFFFF)
178#define BHIE_TXVECSTATUS_SEQNUM_SHFT (0)
179#define BHIE_TXVECSTATUS_STATUS_BMSK (0xC0000000)
180#define BHIE_TXVECSTATUS_STATUS_SHFT (30)
181#define BHIE_TXVECSTATUS_STATUS_RESET (0x00)
182#define BHIE_TXVECSTATUS_STATUS_XFER_COMPL (0x02)
183#define BHIE_TXVECSTATUS_STATUS_ERROR (0x03)
184#define BHIE_RXVECADDR_LOW_OFFS (0x0060)
185#define BHIE_RXVECADDR_HIGH_OFFS (0x0064)
186#define BHIE_RXVECSIZE_OFFS (0x0068)
187#define BHIE_RXVECDB_OFFS (0x0070)
188#define BHIE_RXVECDB_SEQNUM_BMSK (0x3FFFFFFF)
189#define BHIE_RXVECDB_SEQNUM_SHFT (0)
190#define BHIE_RXVECSTATUS_OFFS (0x0078)
191#define BHIE_RXVECSTATUS_SEQNUM_BMSK (0x3FFFFFFF)
192#define BHIE_RXVECSTATUS_SEQNUM_SHFT (0)
193#define BHIE_RXVECSTATUS_STATUS_BMSK (0xC0000000)
194#define BHIE_RXVECSTATUS_STATUS_SHFT (30)
195#define BHIE_RXVECSTATUS_STATUS_RESET (0x00)
196#define BHIE_RXVECSTATUS_STATUS_XFER_COMPL (0x02)
197#define BHIE_RXVECSTATUS_STATUS_ERROR (0x03)
198
199#define EV_CTX_RESERVED_MASK GENMASK(7, 0)
200#define EV_CTX_INTMODC_MASK GENMASK(15, 8)
201#define EV_CTX_INTMODC_SHIFT 8
202#define EV_CTX_INTMODT_MASK GENMASK(31, 16)
203#define EV_CTX_INTMODT_SHIFT 16
204struct mhi_event_ctxt {
205 __u32 intmod;
206 __u32 ertype;
207 __u32 msivec;
208
209 __u64 rbase __packed __aligned(4);
210 __u64 rlen __packed __aligned(4);
211 __u64 rp __packed __aligned(4);
212 __u64 wp __packed __aligned(4);
213};
214
215#define CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
216#define CHAN_CTX_CHSTATE_SHIFT 0
217#define CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
218#define CHAN_CTX_BRSTMODE_SHIFT 8
219#define CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
220#define CHAN_CTX_POLLCFG_SHIFT 10
221#define CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
222struct mhi_chan_ctxt {
223 __u32 chcfg;
224 __u32 chtype;
225 __u32 erindex;
226
227 __u64 rbase __packed __aligned(4);
228 __u64 rlen __packed __aligned(4);
229 __u64 rp __packed __aligned(4);
230 __u64 wp __packed __aligned(4);
231};
232
233struct mhi_cmd_ctxt {
234 __u32 reserved0;
235 __u32 reserved1;
236 __u32 reserved2;
237
238 __u64 rbase __packed __aligned(4);
239 __u64 rlen __packed __aligned(4);
240 __u64 rp __packed __aligned(4);
241 __u64 wp __packed __aligned(4);
242};
243
244struct mhi_ctxt {
245 struct mhi_event_ctxt *er_ctxt;
246 struct mhi_chan_ctxt *chan_ctxt;
247 struct mhi_cmd_ctxt *cmd_ctxt;
248 dma_addr_t er_ctxt_addr;
249 dma_addr_t chan_ctxt_addr;
250 dma_addr_t cmd_ctxt_addr;
251};
252
253struct mhi_tre {
254 u64 ptr;
255 u32 dword[2];
256};
257
258struct bhi_vec_entry {
259 u64 dma_addr;
260 u64 size;
261};
262
263enum mhi_cmd_type {
264 MHI_CMD_NOP = 1,
265 MHI_CMD_RESET_CHAN = 16,
266 MHI_CMD_STOP_CHAN = 17,
267 MHI_CMD_START_CHAN = 18,
268};
269
14/* MHI transfer completion events */270/* MHI transfer completion events */
15enum mhi_ev_ccs {271enum mhi_ev_ccs {
16 MHI_EV_CC_INVALID = 0x0,272 MHI_EV_CC_INVALID = 0x0,
@@ -39,6 +295,7 @@ enum mhi_ch_state { · 22 unmodified lines
39#define NR_OF_CMD_RINGS 1295#define NR_OF_CMD_RINGS 1
40#define CMD_EL_PER_RING 128296#define CMD_EL_PER_RING 128
41#define PRIMARY_CMD_RING 0297#define PRIMARY_CMD_RING 0
298#define MHI_DEV_WAKE_DB 127
42#define MHI_MAX_MTU 0xffff299#define MHI_MAX_MTU 0xffff
43 300
44enum mhi_er_type {301enum mhi_er_type {
@@ -148,4 +405,29 @@ struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl); · 103 unmodified lines
148int mhi_destroy_device(struct device *dev, void *data);405int mhi_destroy_device(struct device *dev, void *data);
149void mhi_create_devices(struct mhi_controller *mhi_cntrl);406void mhi_create_devices(struct mhi_controller *mhi_cntrl);
150 407
408/* Register access methods */
409void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, struct db_cfg *db_cfg,
410 void __iomem *db_addr, dma_addr_t db_val);
411void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl,
412 struct db_cfg *db_mode, void __iomem *db_addr,
413 dma_addr_t db_val);
414int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl,
415 void __iomem *base, u32 offset, u32 *out);
416int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl,
417 void __iomem *base, u32 offset, u32 mask,
418 u32 shift, u32 *out);
419void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
420 u32 offset, u32 val);
421void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base,
422 u32 offset, u32 mask, u32 shift, u32 val);
423void mhi_ring_er_db(struct mhi_event *mhi_event);
424void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr,
425 dma_addr_t db_val);
426void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd);
427void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
428 struct mhi_chan *mhi_chan);
429
430/* Initialization methods */
431int mhi_init_mmio(struct mhi_controller *mhi_cntrl);
432
151#endif /* _MHI_INT_H */433#endif /* _MHI_INT_H */
drivers/bus/mhi/core/main.c+118−0
@@ -15,6 +15,124 @@ · 14 unmodified lines
15#include <linux/slab.h>15#include <linux/slab.h>
16#include "internal.h"16#include "internal.h"
17 17
18int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl,
19 void __iomem *base, u32 offset, u32 *out)
20{
21 u32 tmp = readl(base + offset);
22
23 /* If there is any unexpected value, query the link status */
24 if (PCI_INVALID_READ(tmp) &&
25 mhi_cntrl->link_status(mhi_cntrl))
26 return -EIO;
27
28 *out = tmp;
29
30 return 0;
31}
32
33int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl,
34 void __iomem *base, u32 offset,
35 u32 mask, u32 shift, u32 *out)
36{
37 u32 tmp;
38 int ret;
39
40 ret = mhi_read_reg(mhi_cntrl, base, offset, &tmp);
41 if (ret)
42 return ret;
43
44 *out = (tmp & mask) >> shift;
45
46 return 0;
47}
48
49void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
50 u32 offset, u32 val)
51{
52 writel(val, base + offset);
53}
54
55void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base,
56 u32 offset, u32 mask, u32 shift, u32 val)
57{
58 int ret;
59 u32 tmp;
60
61 ret = mhi_read_reg(mhi_cntrl, base, offset, &tmp);
62 if (ret)
63 return;
64
65 tmp &= ~mask;
66 tmp |= (val << shift);
67 mhi_write_reg(mhi_cntrl, base, offset, tmp);
68}
69
70void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr,
71 dma_addr_t db_val)
72{
73 mhi_write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(db_val));
74 mhi_write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(db_val));
75}
76
77void mhi_db_brstmode(struct mhi_controller *mhi_cntrl,
78 struct db_cfg *db_cfg,
79 void __iomem *db_addr,
80 dma_addr_t db_val)
81{
82 if (db_cfg->db_mode) {
83 db_cfg->db_val = db_val;
84 mhi_write_db(mhi_cntrl, db_addr, db_val);
85 db_cfg->db_mode = 0;
86 }
87}
88
89void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl,
90 struct db_cfg *db_cfg,
91 void __iomem *db_addr,
92 dma_addr_t db_val)
93{
94 db_cfg->db_val = db_val;
95 mhi_write_db(mhi_cntrl, db_addr, db_val);
96}
97
98void mhi_ring_er_db(struct mhi_event *mhi_event)
99{
100 struct mhi_ring *ring = &mhi_event->ring;
101
102 mhi_event->db_cfg.process_db(mhi_event->mhi_cntrl, &mhi_event->db_cfg,
103 ring->db_addr, *ring->ctxt_wp);
104}
105
106void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd)
107{
108 dma_addr_t db;
109 struct mhi_ring *ring = &mhi_cmd->ring;
110
111 db = ring->iommu_base + (ring->wp - ring->base);
112 *ring->ctxt_wp = db;
113 mhi_write_db(mhi_cntrl, ring->db_addr, db);
114}
115
116void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
117 struct mhi_chan *mhi_chan)
118{
119 struct mhi_ring *ring = &mhi_chan->tre_ring;
120 dma_addr_t db;
121
122 db = ring->iommu_base + (ring->wp - ring->base);
123 *ring->ctxt_wp = db;
124 mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg,
125 ring->db_addr, db);
126}
127
128enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl)
129{
130 u32 exec;
131 int ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_EXECENV, &exec);
132
133 return (ret) ? MHI_EE_MAX : exec;
134}
135
18int mhi_destroy_device(struct device *dev, void *data)136int mhi_destroy_device(struct device *dev, void *data)
19{137{
20 struct mhi_device *mhi_dev;138 struct mhi_device *mhi_dev;
include/linux/mhi.h+4−0
@@ -240,6 +240,8 @@ struct mhi_controller_config { · 239 unmodified lines
240 * controller (required)240 * controller (required)
241 * @mhi_dev: MHI device instance for the controller241 * @mhi_dev: MHI device instance for the controller
242 * @regs: Base address of MHI MMIO register space (required)242 * @regs: Base address of MHI MMIO register space (required)
243 * @bhi: Points to base of MHI BHI register space
244 * @wake_db: MHI WAKE doorbell register address
243 * @iova_start: IOMMU starting address for data (required)245 * @iova_start: IOMMU starting address for data (required)
244 * @iova_stop: IOMMU stop address for data (required)246 * @iova_stop: IOMMU stop address for data (required)
245 * @fw_image: Firmware image name for normal booting (required)247 * @fw_image: Firmware image name for normal booting (required)
@@ -294,6 +296,8 @@ struct mhi_controller { · 48 unmodified lines
294 struct device *cntrl_dev;296 struct device *cntrl_dev;
295 struct mhi_device *mhi_dev;297 struct mhi_device *mhi_dev;
296 void __iomem *regs;298 void __iomem *regs;
299 void __iomem *bhi;
300 void __iomem *wake_db;
297 dma_addr_t iova_start;301 dma_addr_t iova_start;
298 dma_addr_t iova_stop;302 dma_addr_t iova_stop;
299 const char *fw_image;303 const char *fw_image;