Host driver can't get a hint of DDR mode through ios->ddr flag anymore. ios->timing is currently used to inform DDR mode as a substitute. And capability of MMC_CAP_MMC_HIGHSPEED is added for DDR support.
Unified · Split
| @@ -699,7 +699,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) · 698 unmodified lines | ||
| 699 | 699 | } |
| 700 | 700 | |
| 701 | 701 | /* DDR mode set */ |
| 702 | − if (ios->ddr) { | |
| 702 | + if (ios->timing == MMC_TIMING_UHS_DDR50) { | |
| 703 | 703 | regs = mci_readl(slot->host, UHS_REG); |
| 704 | 704 | regs |= (0x1 << slot->id) << 16; |
| 705 | 705 | mci_writel(slot->host, UHS_REG, regs); |
| @@ -1646,7 +1646,7 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id) · 940 unmodified lines | ||
| 1646 | 1646 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
| 1647 | 1647 | |
| 1648 | 1648 | if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED) |
| 1649 | − mmc->caps |= MMC_CAP_SD_HIGHSPEED; | |
| 1649 | + mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; | |
| 1650 | 1650 | |
| 1651 | 1651 | #ifdef CONFIG_MMC_DW_IDMAC |
| 1652 | 1652 | mmc->max_segs = host->ring_size; |