Merge tag 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI changes from Bjorn Helgaas: "Host bridge hotplug: - Add MMCONFIG support for hot-added host bridges (Jiang Liu) Device hotplug: - Move fixups from __init to __devinit (Sebastian Andrzej Siewior) - Call FINAL fixups for hot-added devices, too (Myron Stowe) - Factor out generic code for P2P bridge hot-add (Yinghai Lu) - Remove all functions in a slot, not just those with _EJx (Amos Kong) Dynamic resource management: - Track bus number allocation (struct resource tree per domain) (Yinghai Lu) - Make P2P bridge 1K I/O windows work with resource reassignment (Bjorn Helgaas, Yinghai Lu) - Disable decoding while updating 64-bit BARs (Bjorn Helgaas) Power management: - Add PCIe runtime D3cold support (Huang Ying) Virtualization: - Add VFIO infrastructure (ACS, DMA source ID quirks) (Alex Williamson) - Add quirks for devices with broken INTx masking (Jan Kiszka) Miscellaneous: - Fix some PCI Express capability version issues (Myron Stowe) - Factor out some arch code with a weak, generic, pcibios_setup() (Myron Stowe)" * tag 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (122 commits) PCI: hotplug: ensure a consistent return value in error case PCI: fix undefined reference to 'pci_fixup_final_inited' PCI: build resource code for M68K architecture PCI: pciehp: remove unused pciehp_get_max_lnk_width(), pciehp_get_cur_lnk_width() PCI: reorder __pci_assign_resource() (no change) PCI: fix truncation of resource size to 32 bits PCI: acpiphp: merge acpiphp_debug and debug PCI: acpiphp: remove unused res_lock sparc/PCI: replace pci_cfg_fake_ranges() with pci_read_bridge_bases() PCI: call final fixups hot-added devices PCI: move final fixups from __init to __devinit x86/PCI: move final fixups from __init to __devinit MIPS/PCI: move final fixups from __init to __devinit PCI: support sizing P2P bridge I/O windows with 1K granularity PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2) PCI: disable MEM decoding while updating 64-bit MEM BARs PCI: leave MEM and IO decoding disabled during 64-bit BAR sizing, too PCI: never discard enable/suspend/resume_early/resume fixups PCI: release temporary reference in __nv_msi_ht_cap_quirk() PCI: restructure 'pci_do_fixups()' ...

Linus Torvalds committed 14 years ago

Commit 6dd53aa2 parents f14121a 63b96f798 files · +1846 −1109Browse files

Unified · Split

98 files

MAINTAINERS +1 −1
arch/alpha/kernel/pci.c +4 −13
arch/arm/kernel/bios32.c +2 −2
arch/cris/arch-v32/drivers/pci/bios.c +0 −5
arch/frv/mb93090-mb00/pci-vdk.c +2 −2
arch/ia64/pci/pci.c +3 −10
arch/microblaze/pci/pci-common.c +2 −7
arch/mips/pci/pci.c +3 −3
arch/mips/pmc-sierra/yosemite/ht.c +0 −11
arch/mips/txx9/generic/pci.c +3 −3
arch/parisc/kernel/pci.c +0 −5
arch/powerpc/include/asm/pci-bridge.h +1 −0
arch/powerpc/kernel/pci-common.c +11 −10
arch/powerpc/kernel/pci_64.c +1 −1
arch/powerpc/kernel/pci_of_scan.c +1 −1
arch/powerpc/platforms/85xx/tqm85xx.c +1 −1
arch/powerpc/platforms/86xx/gef_ppc9a.c +1 −1
arch/powerpc/platforms/86xx/gef_sbc310.c +1 −1
arch/powerpc/platforms/86xx/gef_sbc610.c +1 −1
arch/powerpc/platforms/powernv/pci-ioda.c +4 −4
arch/powerpc/platforms/pseries/pci_dlpar.c +1 −1
arch/powerpc/sysdev/mv64x60_pci.c +1 −1
arch/sh/drivers/pci/fixups-dreamcast.c +1 −1
arch/sh/drivers/pci/fixups-sdk7786.c +2 −2
arch/sh/drivers/pci/pci.c +1 −6
arch/sparc/kernel/leon_pci.c +0 −8
arch/sparc/kernel/pci.c +6 −96
arch/sparc/kernel/pci_impl.h +1 −0
arch/sparc/kernel/pcic.c +0 −13
arch/tile/kernel/pci.c +6 −13
arch/unicore32/kernel/pci.c +1 −1
arch/x86/include/asm/pci_x86.h +7 −0
arch/x86/kernel/quirks.c +1 −1
arch/x86/pci/acpi.c +95 −14
arch/x86/pci/amd_bus.c +3 −4
arch/x86/pci/bus_numa.c +19 −3
arch/x86/pci/bus_numa.h +1 −2
arch/x86/pci/common.c +1 −1
arch/x86/pci/mmconfig-shared.c +248 −124
arch/x86/pci/mmconfig_32.c +27 −3
arch/x86/pci/mmconfig_64.c +37 −15
arch/x86/pci/mrst.c +1 −1
arch/xtensa/kernel/pci.c +1 −7
drivers/acpi/pci_root.c +2 −0
drivers/acpi/sleep.c +19 −5
drivers/iommu/intel-iommu.c +1 −1
drivers/misc/cb710/core.c +1 −1
drivers/net/ethernet/broadcom/tg3.c +2 −2
drivers/parisc/dino.c +11 −5
drivers/parisc/iosapic.c +1 −1
drivers/parisc/lba_pci.c +15 −11
drivers/pci/Makefile +1 −0
drivers/pci/access.c +4 −2
drivers/pci/bus.c +2 −0
drivers/pci/hotplug-pci.c +19 −11
drivers/pci/hotplug/acpiphp.h +1 −3
drivers/pci/hotplug/acpiphp_core.c +2 −5
drivers/pci/hotplug/acpiphp_glue.c +46 −21
drivers/pci/hotplug/cpci_hotplug_core.c +10 −4
drivers/pci/hotplug/cpci_hotplug_pci.c +6 −29
drivers/pci/hotplug/cpqphp_core.c +10 −4
drivers/pci/hotplug/cpqphp_pci.c +4 −4
drivers/pci/hotplug/ibmphp_core.c +4 −4
drivers/pci/hotplug/pciehp.h +0 −4
drivers/pci/hotplug/pciehp_hpc.c +0 −101
drivers/pci/hotplug/pciehp_pci.c +2 −26
drivers/pci/hotplug/pcihp_skeleton.c +10 −4
drivers/pci/hotplug/sgi_hotplug.c +5 −7
drivers/pci/hotplug/shpchp_core.c +10 −4
drivers/pci/hotplug/shpchp_ctrl.c +0 −3
drivers/pci/hotplug/shpchp_pci.c +15 −30
drivers/pci/hotplug/shpchp_sysfs.c +3 −3
drivers/pci/iov.c +2 −2
drivers/pci/pci-acpi.c +33 −3
drivers/pci/pci-driver.c +17 −7
drivers/pci/pci-sysfs.c +30 −1
drivers/pci/pci.c +291 −133
drivers/pci/pci.h +3 −8
drivers/pci/pcie/aer/aerdrv_acpi.c +1 −1
drivers/pci/pcie/portdrv_pci.c +60 −0
drivers/pci/probe.c +191 −55
drivers/pci/quirks.c +163 −79
drivers/pci/remove.c +1 −0
drivers/pci/search.c +2 −0
drivers/pci/setup-bus.c +44 −21
drivers/pci/setup-res.c +72 −53
drivers/pcmcia/cardbus.c +1 −1
drivers/pcmcia/yenta_socket.c +13 −13
drivers/pnp/pnpacpi/core.c +2 −2
drivers/xen/xen-pciback/conf_space.c +3 −3
include/acpi/acnames.h +1 −0
include/acpi/acpi_bus.h +4 −3
include/linux/pci-acpi.h +1 −0
include/linux/pci.h +72 −10
include/linux/pci_regs.h +109 −13
include/linux/sfi_acpi.h +2 −2
kernel/resource.c +8 −5
scripts/mod/modpost.c +11 −0

MAINTAINERS+1−1

@@ -5210,7 +5210,7 @@ PCI SUBSYSTEM · 5209 unmodified lines
5210	5210	M: Bjorn Helgaas <bhelgaas@google.com>
5211	5211	L: linux-pci@vger.kernel.org
5212	5212	Q: http://patchwork.ozlabs.org/project/linux-pci/list/
5213		−T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/linux.git
	5213	+T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
5214	5214	S: Supported
5215	5215	F: Documentation/PCI/
5216	5216	F: drivers/pci/

arch/alpha/kernel/pci.c+4−13

@@ -59,15 +59,13 @@ struct pci_controller *pci_isa_hose; · 58 unmodified lines
59	59	* Quirks.
60	60	*/
61	61
62		−static void __init
63		−quirk_isa_bridge(struct pci_dev *dev)
	62	+static void __devinit quirk_isa_bridge(struct pci_dev *dev)
64	63	{
65	64	dev->class = PCI_CLASS_BRIDGE_ISA << 8;
66	65	}
67	66	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
68	67
69		−static void __init
70		−quirk_cypress(struct pci_dev *dev)
	68	+static void __devinit quirk_cypress(struct pci_dev *dev)
71	69	{
72	70	/* The Notorious Cy82C693 chip. */
73	71
@@ -106,8 +104,7 @@ quirk_cypress(struct pci_dev *dev) · 32 unmodified lines
106	104	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
107	105
108	106	/* Called for each device after PCI setup is done. */
109		−static void __init
110		−pcibios_fixup_final(struct pci_dev *dev)
	107	+static void __devinit pcibios_fixup_final(struct pci_dev *dev)
111	108	{
112	109	unsigned int class = dev->class >> 8;
113	110
@@ -198,12 +195,6 @@ pcibios_init(void) · 84 unmodified lines
198	195
199	196	subsys_initcall(pcibios_init);
200	197
201		−char * __devinit
202		−pcibios_setup(char *str)
203		−{
204		− return str;
205		−}
206		−
207	198	#ifdef ALPHA_RESTORE_SRM_SETUP
208	199	static struct pdev_srm_saved_conf *srm_saved_configs;
209	200
@@ -359,7 +350,7 @@ common_init_pci(void) · 149 unmodified lines
359	350	hose, &resources);
360	351	hose->bus = bus;
361	352	hose->need_domain_info = need_domain_info;
362		− next_busno = bus->subordinate + 1;
	353	+ next_busno = bus->busn_res.end + 1;
363	354	/* Don't allow 8-bit bus number overflow inside the hose -
364	355	reserve some space for bridges. */
365	356	if (next_busno > 224) {

arch/arm/kernel/bios32.c+2−2

@@ -253,7 +253,7 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev) · 252 unmodified lines
253	253	}
254	254	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
255	255
256		−static void __init pci_fixup_it8152(struct pci_dev *dev)
	256	+static void __devinit pci_fixup_it8152(struct pci_dev *dev)
257	257	{
258	258	int i;
259	259	/* fixup for ITE 8152 devices */
@@ -461,7 +461,7 @@ static void __init pcibios_init_hw(struct hw_pci hw, struct list_head head) · 201 unmodified lines
461	461	if (!sys->bus)
462	462	panic("PCI: unable to scan bus!");
463	463
464		− busnr = sys->bus->subordinate + 1;
	464	+ busnr = sys->bus->busn_res.end + 1;
465	465
466	466	list_add(&sys->node, head);
467	467	} else {

arch/cris/arch-v32/drivers/pci/bios.c+0−5

@@ -6,11 +6,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *b) · 5 unmodified lines
6	6	{
7	7	}
8	8
9		−char * __devinit pcibios_setup(char *str)
10		−{
11		− return NULL;
12		−}
13		−
14	9	void pcibios_set_master(struct pci_dev *dev)
15	10	{
16	11	u8 lat;

arch/frv/mb93090-mb00/pci-vdk.c+2−2

@@ -268,7 +268,7 @@ static void __init pci_fixup_umc_ide(struct pci_dev *d) · 267 unmodified lines
268	268	d->resource[i].flags \|= PCI_BASE_ADDRESS_SPACE_IO;
269	269	}
270	270
271		−static void __init pci_fixup_ide_bases(struct pci_dev *d)
	271	+static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
272	272	{
273	273	int i;
274	274
@@ -287,7 +287,7 @@ static void __init pci_fixup_ide_bases(struct pci_dev *d) · 12 unmodified lines
287	287	}
288	288	}
289	289
290		−static void __init pci_fixup_ide_trash(struct pci_dev *d)
	290	+static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
291	291	{
292	292	int i;
293	293

arch/ia64/pci/pci.c+3−10

@@ -351,6 +351,8 @@ pci_acpi_scan_root(struct acpi_pci_root *root) · 350 unmodified lines
351	351	#endif
352	352
353	353	INIT_LIST_HEAD(&info.resources);
	354	+ /* insert busn resource at first */
	355	+ pci_add_resource(&info.resources, &root->secondary);
354	356	acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
355	357	&windows);
356	358	if (windows) {
@@ -384,7 +386,7 @@ pci_acpi_scan_root(struct acpi_pci_root *root) · 27 unmodified lines
384	386	return NULL;
385	387	}
386	388
387		− pbus->subordinate = pci_scan_child_bus(pbus);
	389	+ pci_scan_child_bus(pbus);
388	390	return pbus;
389	391
390	392	out3:
@@ -496,15 +498,6 @@ pcibios_align_resource (void data, const struct resource res, · 105 unmodified lines
496	498	return res->start;
497	499	}
498	500
499		−/*
500		− * PCI BIOS setup, always defaults to SAL interface
501		− */
502		−char * __init
503		−pcibios_setup (char *str)
504		−{
505		− return str;
506		−}
507		−
508	501	int
509	502	pci_mmap_page_range (struct pci_dev dev, struct vm_area_struct vma,
510	503	enum pci_mmap_state mmap_state, int write_combine)

arch/microblaze/pci/pci-common.c+2−7

@@ -192,11 +192,6 @@ void pcibios_set_master(struct pci_dev *dev) · 191 unmodified lines
192	192	/* No special bus mastering setup handling */
193	193	}
194	194
195		−char __devinit pcibios_setup(char str)
196		−{
197		− return str;
198		−}
199		−
200	195	/*
201	196	* Reads the interrupt pin to determine if interrupt is use by card.
202	197	* If the interrupt is used, then gets the interrupt line from the
@@ -1504,10 +1499,10 @@ static void __devinit pcibios_scan_phb(struct pci_controller *hose) · 1301 unmodified lines
1504	1499	pci_free_resource_list(&resources);
1505	1500	return;
1506	1501	}
1507		− bus->secondary = hose->first_busno;
	1502	+ bus->busn_res.start = hose->first_busno;
1508	1503	hose->bus = bus;
1509	1504
1510		− hose->last_busno = bus->subordinate;
	1505	+ hose->last_busno = bus->busn_res.end;
1511	1506	}
1512	1507
1513	1508	static int __init pcibios_init(void)

arch/mips/pci/pci.c+3−3

@@ -102,7 +102,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) · 101 unmodified lines
102	102	need_domain_info = need_domain_info \|\| hose->index;
103	103	hose->need_domain_info = need_domain_info;
104	104	if (bus) {
105		− next_busno = bus->subordinate + 1;
	105	+ next_busno = bus->busn_res.end + 1;
106	106	/* Don't allow 8-bit bus number overflow inside the hose -
107	107	reserve some space for bridges. */
108	108	if (next_busno > 224) {
@@ -348,9 +348,9 @@ int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma, · 239 unmodified lines
348	348	vma->vm_end - vma->vm_start, vma->vm_page_prot);
349	349	}
350	350
351		−char * (pcibios_plat_setup)(char str) __devinitdata;
	351	+char * (pcibios_plat_setup)(char str) __initdata;
352	352
353		−char __devinit pcibios_setup(char str)
	353	+char __init pcibios_setup(char str)
354	354	{
355	355	if (pcibios_plat_setup)
356	356	return pcibios_plat_setup(str);

arch/mips/pmc-sierra/yosemite/ht.c+0−11

@@ -395,17 +395,6 @@ void __init pcibios_init(void) · 394 unmodified lines
395	395	pci_scan_bus(3, &titan_pci_ops, NULL);
396	396	}
397	397
398		−/*
399		− * for parsing "pci=" kernel boot arguments.
400		− */
401		−char pcibios_setup(char str)
402		−{
403		− printk(KERN_INFO "rr: pcibios_setup\n");
404		− /* Nothing to do for now. */
405		−
406		− return str;
407		−}
408		−
409	398	unsigned __init int pcibios_assign_all_busses(void)
410	399	{
411	400	/* We want to use the PCI bus detection done by PMON */

arch/mips/txx9/generic/pci.c+3−3

@@ -256,7 +256,7 @@ static irqreturn_t i8259_interrupt(int irq, void *dev_id) · 255 unmodified lines
256	256	return IRQ_HANDLED;
257	257	}
258	258
259		−static int __init
	259	+static int __devinit
260	260	txx9_i8259_irq_setup(int irq)
261	261	{
262	262	int err;
@@ -398,9 +398,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) · 135 unmodified lines
398	398	return txx9_board_vec->pci_map_irq(dev, slot, pin);
399	399	}
400	400
401		−char * (txx9_board_pcibios_setup)(char str) __devinitdata;
	401	+char * (txx9_board_pcibios_setup)(char str) __initdata;
402	402
403		−char __devinit txx9_pcibios_setup(char str)
	403	+char __init txx9_pcibios_setup(char str)
404	404	{
405	405	if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
406	406	return NULL;

arch/parisc/kernel/pci.c+0−5

@@ -139,11 +139,6 @@ void pcibios_fixup_bus(struct pci_bus *bus) · 138 unmodified lines
139	139	}
140	140
141	141
142		−char pcibios_setup(char str)
143		−{
144		− return str;
145		−}
146		−
147	142	/*
148	143	* Called by pci_set_master() - a driver interface.
149	144	*

arch/powerpc/include/asm/pci-bridge.h+1−0

@@ -30,6 +30,7 @@ struct pci_controller { · 29 unmodified lines
30	30	int first_busno;
31	31	int last_busno;
32	32	int self_busno;
	33	+ struct resource busn;
33	34
34	35	void __iomem *io_base_virt;
35	36	#ifdef CONFIG_PPC64

arch/powerpc/kernel/pci-common.c+11−10

@@ -200,11 +200,6 @@ int pcibios_add_platform_entries(struct pci_dev *pdev) · 199 unmodified lines
200	200	return device_create_file(&pdev->dev, &dev_attr_devspec);
201	201	}
202	202
203		−char __devinit pcibios_setup(char str)
204		−{
205		− return str;
206		−}
207		−
208	203	/*
209	204	* Reads the interrupt pin to determine if interrupt is use by card.
210	205	* If the interrupt is used, then gets the interrupt line from the
@@ -1635,6 +1630,11 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose) · 1424 unmodified lines
1635	1630	/* Wire up PHB bus resources */
1636	1631	pcibios_setup_phb_resources(hose, &resources);
1637	1632
	1633	+ hose->busn.start = hose->first_busno;
	1634	+ hose->busn.end = hose->last_busno;
	1635	+ hose->busn.flags = IORESOURCE_BUS;
	1636	+ pci_add_resource(&resources, &hose->busn);
	1637	+
1638	1638	/* Create an empty bus for the toplevel */
1639	1639	bus = pci_create_root_bus(hose->parent, hose->first_busno,
1640	1640	hose->ops, hose, &resources);
@@ -1651,13 +1651,14 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose) · 10 unmodified lines
1651	1651	if (node && ppc_md.pci_probe_mode)
1652	1652	mode = ppc_md.pci_probe_mode(bus);
1653	1653	pr_debug(" probe mode: %d\n", mode);
1654		− if (mode == PCI_PROBE_DEVTREE) {
1655		− bus->subordinate = hose->last_busno;
	1654	+ if (mode == PCI_PROBE_DEVTREE)
1656	1655	of_scan_bus(node, bus);
1657		− }
1658	1656
1659		− if (mode == PCI_PROBE_NORMAL)
1660		− hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
	1657	+ if (mode == PCI_PROBE_NORMAL) {
	1658	+ pci_bus_update_busn_res_end(bus, 255);
	1659	+ hose->last_busno = pci_scan_child_bus(bus);
	1660	+ pci_bus_update_busn_res_end(bus, hose->last_busno);
	1661	+ }
1661	1662
1662	1663	/* Platform gets a chance to do some global fixups before
1663	1664	* we proceed to resource allocation

arch/powerpc/kernel/pci_64.c+1−1

@@ -236,7 +236,7 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus, · 235 unmodified lines
236	236
237	237	for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
238	238	bus = pci_bus_b(ln);
239		− if (in_bus >= bus->number && in_bus <= bus->subordinate)
	239	+ if (in_bus >= bus->number && in_bus <= bus->busn_res.end)
240	240	break;
241	241	bus = NULL;
242	242	}

arch/powerpc/kernel/pci_of_scan.c+1−1

@@ -239,7 +239,7 @@ void __devinit of_scan_pci_bridge(struct pci_dev *dev) · 238 unmodified lines
239	239	}
240	240
241	241	bus->primary = dev->bus->number;
242		− bus->subordinate = busrange[1];
	242	+ pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
243	243	bus->bridge_ctl = 0;
244	244
245	245	/* parse ranges property */

arch/powerpc/platforms/85xx/tqm85xx.c+1−1

@@ -102,7 +102,7 @@ static void tqm85xx_show_cpuinfo(struct seq_file *m) · 101 unmodified lines
102	102	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
103	103	}
104	104
105		−static void __init tqm85xx_ti1520_fixup(struct pci_dev *pdev)
	105	+static void __devinit tqm85xx_ti1520_fixup(struct pci_dev *pdev)
106	106	{
107	107	unsigned int val;
108	108

arch/powerpc/platforms/86xx/gef_ppc9a.c+1−1

@@ -164,7 +164,7 @@ static void gef_ppc9a_show_cpuinfo(struct seq_file *m) · 163 unmodified lines
164	164	gef_ppc9a_get_vme_is_syscon() ? "yes" : "no");
165	165	}
166	166
167		−static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev)
	167	+static void __devinit gef_ppc9a_nec_fixup(struct pci_dev *pdev)
168	168	{
169	169	unsigned int val;
170	170

arch/powerpc/platforms/86xx/gef_sbc310.c+1−1

@@ -152,7 +152,7 @@ static void gef_sbc310_show_cpuinfo(struct seq_file *m) · 151 unmodified lines
152	152
153	153	}
154	154
155		−static void __init gef_sbc310_nec_fixup(struct pci_dev *pdev)
	155	+static void __devinit gef_sbc310_nec_fixup(struct pci_dev *pdev)
156	156	{
157	157	unsigned int val;
158	158

arch/powerpc/platforms/86xx/gef_sbc610.c+1−1

@@ -141,7 +141,7 @@ static void gef_sbc610_show_cpuinfo(struct seq_file *m) · 140 unmodified lines
141	141	seq_printf(m, "SVR\t\t: 0x%x\n", svid);
142	142	}
143	143
144		−static void __init gef_sbc610_nec_fixup(struct pci_dev *pdev)
	144	+static void __devinit gef_sbc610_nec_fixup(struct pci_dev *pdev)
145	145	{
146	146	unsigned int val;
147	147

arch/powerpc/platforms/powernv/pci-ioda.c+4−4

@@ -589,7 +589,7 @@ static int __devinit pnv_ioda_configure_pe(struct pnv_phb *phb, · 588 unmodified lines
589	589	dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
590	590	fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
591	591	parent = pe->pbus->self;
592		− count = pe->pbus->subordinate - pe->pbus->secondary + 1;
	592	+ count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
593	593	switch(count) {
594	594	case 1: bcomp = OpalPciBusAll; break;
595	595	case 2: bcomp = OpalPciBus7Bits; break;
@@ -816,11 +816,11 @@ static void __devinit pnv_ioda_setup_bus_PE(struct pci_dev *dev, · 220 unmodified lines
816	816	pe->pdev = NULL;
817	817	pe->tce32_seg = -1;
818	818	pe->mve_number = -1;
819		− pe->rid = bus->secondary << 8;
	819	+ pe->rid = bus->busn_res.start << 8;
820	820	pe->dma_weight = 0;
821	821
822		− pe_info(pe, "Secondary busses %d..%d associated with PE\n",
823		− bus->secondary, bus->subordinate);
	822	+ pe_info(pe, "Secondary busses %pR associated with PE\n",
	823	+ &bus->busn_res);
824	824
825	825	if (pnv_ioda_configure_pe(phb, pe)) {
826	826	/* XXX What do we do here ? */

arch/powerpc/platforms/pseries/pci_dlpar.c+1−1

@@ -121,7 +121,7 @@ void pcibios_add_pci_devices(struct pci_bus * bus) · 120 unmodified lines
121	121	if (!num)
122	122	return;
123	123	pcibios_setup_bus_devices(bus);
124		− max = bus->secondary;
	124	+ max = bus->busn_res.start;
125	125	for (pass=0; pass < 2; pass++)
126	126	list_for_each_entry(dev, &bus->devices, bus_list) {
127	127	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE \|\|

arch/powerpc/sysdev/mv64x60_pci.c+1−1

@@ -104,7 +104,7 @@ subsys_initcall(mv64x60_sysfs_init); · 103 unmodified lines
104	104
105	105	#endif /* CONFIG_SYSFS */
106	106
107		−static void __init mv64x60_pci_fixup_early(struct pci_dev *dev)
	107	+static void __devinit mv64x60_pci_fixup_early(struct pci_dev *dev)
108	108	{
109	109	/*
110	110	* Set the host bridge hdr_type to an invalid value so that

arch/sh/drivers/pci/fixups-dreamcast.c+1−1

@@ -28,7 +28,7 @@ · 27 unmodified lines
28	28	#include <asm/irq.h>
29	29	#include <mach/pci.h>
30	30
31		−static void __init gapspci_fixup_resources(struct pci_dev *dev)
	31	+static void __devinit gapspci_fixup_resources(struct pci_dev *dev)
32	32	{
33	33	struct pci_channel *p = dev->sysdata;
34	34

arch/sh/drivers/pci/fixups-sdk7786.c+2−2

@@ -23,9 +23,9 @@ · 22 unmodified lines
23	23	* Misconfigurations can be detected through the FPGA via the slot
24	24	* resistors to determine card presence. Hotplug remains unsupported.
25	25	*/
26		−static unsigned int slot4en __devinitdata;
	26	+static unsigned int slot4en __initdata;
27	27
28		−char __devinit pcibios_setup(char str)
	28	+char __init pcibios_setup(char str)
29	29	{
30	30	if (strcmp(str, "slot4en") == 0) {
31	31	slot4en = 1;

arch/sh/drivers/pci/pci.c+1−6

@@ -59,7 +59,7 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose) · 58 unmodified lines
59	59	need_domain_info = need_domain_info \|\| hose->index;
60	60	hose->need_domain_info = need_domain_info;
61	61	if (bus) {
62		− next_busno = bus->subordinate + 1;
	62	+ next_busno = bus->busn_res.end + 1;
63	63	/* Don't allow 8-bit bus number overflow inside the hose -
64	64	reserve some space for bridges. */
65	65	if (next_busno > 224) {
@@ -197,11 +197,6 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq) · 131 unmodified lines
197	197	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
198	198	}
199	199
200		−char * __devinit __weak pcibios_setup(char *str)
201		−{
202		− return str;
203		−}
204		−
205	200	static void __init
206	201	pcibios_bus_report_status_early(struct pci_channel *hose,
207	202	int top_bus, int current_bus,

arch/sparc/kernel/leon_pci.c+0−8

@@ -91,14 +91,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *pbus) · 90 unmodified lines
91	91	}
92	92	}
93	93
94		−/*
95		− * Other archs parse arguments here.
96		− */
97		−char * __devinit pcibios_setup(char *str)
98		−{
99		− return str;
100		−}
101		−
102	94	resource_size_t pcibios_align_resource(void data, const struct resource res,
103	95	resource_size_t size, resource_size_t align)
104	96	{

arch/sparc/kernel/pci.c+6−96

@@ -375,93 +375,6 @@ static void __devinit apb_calc_first_last(u8 map, u32 first_p, u32 last_p) · 374 unmodified lines
375	375	*last_p = last;
376	376	}
377	377
378		−/* For PCI bus devices which lack a 'ranges' property we interrogate
379		− * the config space values to set the resources, just like the generic
380		− * Linux PCI probing code does.
381		− */
382		−static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
383		− struct pci_bus *bus,
384		− struct pci_pbm_info *pbm)
385		−{
386		− struct pci_bus_region region;
387		− struct resource *res, res2;
388		− u8 io_base_lo, io_limit_lo;
389		− u16 mem_base_lo, mem_limit_lo;
390		− unsigned long base, limit;
391		−
392		− pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
393		− pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
394		− base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
395		− limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
396		−
397		− if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
398		− u16 io_base_hi, io_limit_hi;
399		−
400		− pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
401		− pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
402		− base \|= (io_base_hi << 16);
403		− limit \|= (io_limit_hi << 16);
404		− }
405		−
406		− res = bus->resource[0];
407		− if (base <= limit) {
408		− res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) \| IORESOURCE_IO;
409		− res2.flags = res->flags;
410		− region.start = base;
411		− region.end = limit + 0xfff;
412		− pcibios_bus_to_resource(dev, &res2, &region);
413		− if (!res->start)
414		− res->start = res2.start;
415		− if (!res->end)
416		− res->end = res2.end;
417		− }
418		−
419		− pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
420		− pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
421		− base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
422		− limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
423		−
424		− res = bus->resource[1];
425		− if (base <= limit) {
426		− res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) \|
427		− IORESOURCE_MEM);
428		− region.start = base;
429		− region.end = limit + 0xfffff;
430		− pcibios_bus_to_resource(dev, res, &region);
431		− }
432		−
433		− pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
434		− pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
435		− base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
436		− limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
437		−
438		− if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
439		− u32 mem_base_hi, mem_limit_hi;
440		−
441		− pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
442		− pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
443		−
444		− /*
445		− * Some bridges set the base > limit by default, and some
446		− * (broken) BIOSes do not initialize them. If we find
447		− * this, just assume they are not being used.
448		− */
449		− if (mem_base_hi <= mem_limit_hi) {
450		− base \|= ((long) mem_base_hi) << 32;
451		− limit \|= ((long) mem_limit_hi) << 32;
452		− }
453		− }
454		−
455		− res = bus->resource[2];
456		− if (base <= limit) {
457		− res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) \|
458		− IORESOURCE_MEM \| IORESOURCE_PREFETCH);
459		− region.start = base;
460		− region.end = limit + 0xfffff;
461		− pcibios_bus_to_resource(dev, res, &region);
462		− }
463		−}
464		−
465	378	/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
466	379	* a proper 'ranges' property.
467	380	*/
@@ -535,7 +448,7 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, · 67 unmodified lines
535	448	}
536	449
537	450	bus->primary = dev->bus->number;
538		− bus->subordinate = busrange[1];
	451	+ pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
539	452	bus->bridge_ctl = 0;
540	453
541	454	/* parse ranges property, or cook one up by hand for Simba */
@@ -550,7 +463,7 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, · 8 unmodified lines
550	463	apb_fake_ranges(dev, bus, pbm);
551	464	goto after_ranges;
552	465	} else if (ranges == NULL) {
553		− pci_cfg_fake_ranges(dev, bus, pbm);
	466	+ pci_read_bridge_bases(bus);
554	467	goto after_ranges;
555	468	}
556	469	i = 1;
@@ -685,6 +598,10 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm, · 128 unmodified lines
685	598	pbm->io_space.start);
686	599	pci_add_resource_offset(&resources, &pbm->mem_space,
687	600	pbm->mem_space.start);
	601	+ pbm->busn.start = pbm->pci_first_busno;
	602	+ pbm->busn.end = pbm->pci_last_busno;
	603	+ pbm->busn.flags = IORESOURCE_BUS;
	604	+ pci_add_resource(&resources, &pbm->busn);
688	605	bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
689	606	pbm, &resources);
690	607	if (!bus) {
@@ -693,8 +610,6 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm, · 2 unmodified lines
693	610	pci_free_resource_list(&resources);
694	611	return NULL;
695	612	}
696		− bus->secondary = pbm->pci_first_busno;
697		− bus->subordinate = pbm->pci_last_busno;
698	613
699	614	pci_of_scan_bus(pbm, node, bus);
700	615	pci_bus_add_devices(bus);
@@ -747,11 +662,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) · 46 unmodified lines
747	662	return 0;
748	663	}
749	664
750		−char * __devinit pcibios_setup(char *str)
751		−{
752		− return str;
753		−}
754		−
755	665	/* Platform support for /proc/bus/pci/X/Y mmap()s. */
756	666
757	667	/* If the user uses a host-bridge as the PCI device, he may use

arch/sparc/kernel/pci_impl.h+1−0

@@ -97,6 +97,7 @@ struct pci_pbm_info { · 96 unmodified lines
97	97	/* PBM I/O and Memory space resources. */
98	98	struct resource io_space;
99	99	struct resource mem_space;
	100	+ struct resource busn;
100	101
101	102	/* Base of PCI Config space, can be per-PBM or shared. */
102	103	unsigned long config_space;

arch/sparc/kernel/pcic.c+0−13

@@ -767,14 +767,6 @@ static void watchdog_reset() { · 766 unmodified lines
767	767	}
768	768	#endif
769	769
770		−/*
771		− * Other archs parse arguments here.
772		− */
773		−char * __devinit pcibios_setup(char *str)
774		−{
775		− return str;
776		−}
777		−
778	770	resource_size_t pcibios_align_resource(void data, const struct resource res,
779	771	resource_size_t size, resource_size_t align)
780	772	{
@@ -884,11 +876,6 @@ void __init sun4m_pci_init_IRQ(void) · 103 unmodified lines
884	876	sparc_config.load_profile_irq = pcic_load_profile_irq;
885	877	}
886	878
887		−int pcibios_assign_resource(struct pci_dev *pdev, int resource)
888		−{
889		− return -ENXIO;
890		−}
891		−
892	879	/*
893	880	* This probably belongs here rather than ioport.c because
894	881	* we do not want this crud linked into SBus kernels.

arch/tile/kernel/pci.c+6−13

@@ -310,6 +310,7 @@ int __init pcibios_init(void) · 309 unmodified lines
310	310	if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
311	311	struct pci_controller *controller = &controllers[i];
312	312	struct pci_bus *bus;
	313	+ LIST_HEAD(resources);
313	314
314	315	if (tile_init_irqs(i, controller)) {
315	316	pr_err("PCI: Could not initialize IRQs\n");
@@ -327,9 +328,11 @@ int __init pcibios_init(void) · 11 unmodified lines
327	328	* This is inlined in linux/pci.h and calls into
328	329	* pci_scan_bus_parented() in probe.c.
329	330	*/
330		− bus = pci_scan_bus(0, controller->ops, controller);
	331	+ pci_add_resource(&resources, &ioport_resource);
	332	+ pci_add_resource(&resources, &iomem_resource);
	333	+ bus = pci_scan_root_bus(NULL, 0, controller->ops, controller, &resources);
331	334	controller->root_bus = bus;
332		− controller->last_busno = bus->subordinate;
	335	+ controller->last_busno = bus->busn_res.end;
333	336	}
334	337	}
335	338
@@ -366,7 +369,7 @@ int __init pcibios_init(void) · 30 unmodified lines
366	369	*/
367	370	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
368	371	(PCI_SLOT(dev->devfn) == 0)) {
369		− next_bus = dev->subordinate;
	372	+ next_bus = dev->busn_res.end;
370	373	controllers[i].mem_resources[0] =
371	374	*next_bus->resource[0];
372	375	controllers[i].mem_resources[1] =
@@ -400,16 +403,6 @@ void pcibios_set_master(struct pci_dev *dev) · 27 unmodified lines
400	403	/* No special bus mastering setup handling. */
401	404	}
402	405
403		−/*
404		− * This can be called from the generic PCI layer, but doesn't need to
405		− * do anything.
406		− */
407		−char __devinit pcibios_setup(char str)
408		−{
409		− /* Nothing needs to be done. */
410		− return str;
411		−}
412		−
413	406	/*
414	407	* This is called from the generic Linux layer.
415	408	*/

arch/unicore32/kernel/pci.c+1−1

@@ -296,7 +296,7 @@ static int __init pci_common_init(void) · 295 unmodified lines
296	296	}
297	297	subsys_initcall(pci_common_init);
298	298
299		−char * __devinit pcibios_setup(char *str)
	299	+char * __init pcibios_setup(char *str)
300	300	{
301	301	if (!strcmp(str, "debug")) {
302	302	debug_pci = 1;

arch/x86/include/asm/pci_x86.h+7−0

@@ -104,6 +104,7 @@ struct pci_raw_ops { · 103 unmodified lines
104	104	extern const struct pci_raw_ops *raw_pci_ops;
105	105	extern const struct pci_raw_ops *raw_pci_ext_ops;
106	106
	107	+extern const struct pci_raw_ops pci_mmcfg;
107	108	extern const struct pci_raw_ops pci_direct_conf1;
108	109	extern bool port_cf9_safe;
109	110
@@ -139,6 +140,12 @@ struct pci_mmcfg_region { · 29 unmodified lines
139	140
140	141	extern int __init pci_mmcfg_arch_init(void);
141	142	extern void __init pci_mmcfg_arch_free(void);
	143	+extern int __devinit pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
	144	+extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
	145	+extern int __devinit pci_mmconfig_insert(struct device *dev,
	146	+ u16 seg, u8 start,
	147	+ u8 end, phys_addr_t addr);
	148	+extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
142	149	extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
143	150
144	151	extern struct list_head pci_mmcfg_list;

arch/x86/kernel/quirks.c+1−1

@@ -512,7 +512,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, · 511 unmodified lines
512	512
513	513	#if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
514	514	/* Set correct numa_node information for AMD NB functions */
515		−static void __init quirk_amd_nb_node(struct pci_dev *dev)
	515	+static void __devinit quirk_amd_nb_node(struct pci_dev *dev)
516	516	{
517	517	struct pci_dev *nb_ht;
518	518	unsigned int devfn;

arch/x86/pci/acpi.c+95−14

@@ -12,8 +12,13 @@ struct pci_root_info { · 11 unmodified lines
12	12	char name[16];
13	13	unsigned int res_num;
14	14	struct resource *res;
15		− int busnum;
16	15	struct pci_sysdata sd;
	16	+#ifdef CONFIG_PCI_MMCONFIG
	17	+ bool mcfg_added;
	18	+ u16 segment;
	19	+ u8 start_bus;
	20	+ u8 end_bus;
	21	+#endif
17	22	};
18	23
19	24	static bool pci_use_crs = true;
@@ -120,6 +125,81 @@ void __init pci_acpi_crs_quirks(void) · 100 unmodified lines
120	125	pci_use_crs ? "nocrs" : "use_crs");
121	126	}
122	127
	128	+#ifdef CONFIG_PCI_MMCONFIG
	129	+static int __devinit check_segment(u16 seg, struct device dev, char estr)
	130	+{
	131	+ if (seg) {
	132	+ dev_err(dev,
	133	+ "%s can't access PCI configuration "
	134	+ "space under this host bridge.\n",
	135	+ estr);
	136	+ return -EIO;
	137	+ }
	138	+
	139	+ /*
	140	+ * Failure in adding MMCFG information is not fatal,
	141	+ * just can't access extended configuration space of
	142	+ * devices under this host bridge.
	143	+ */
	144	+ dev_warn(dev,
	145	+ "%s can't access extended PCI configuration "
	146	+ "space under this bridge.\n",
	147	+ estr);
	148	+
	149	+ return 0;
	150	+}
	151	+
	152	+static int __devinit setup_mcfg_map(struct pci_root_info *info,
	153	+ u16 seg, u8 start, u8 end,
	154	+ phys_addr_t addr)
	155	+{
	156	+ int result;
	157	+ struct device *dev = &info->bridge->dev;
	158	+
	159	+ info->start_bus = start;
	160	+ info->end_bus = end;
	161	+ info->mcfg_added = false;
	162	+
	163	+ /* return success if MMCFG is not in use */
	164	+ if (raw_pci_ext_ops && raw_pci_ext_ops != &pci_mmcfg)
	165	+ return 0;
	166	+
	167	+ if (!(pci_probe & PCI_PROBE_MMCONF))
	168	+ return check_segment(seg, dev, "MMCONFIG is disabled,");
	169	+
	170	+ result = pci_mmconfig_insert(dev, seg, start, end, addr);
	171	+ if (result == 0) {
	172	+ /* enable MMCFG if it hasn't been enabled yet */
	173	+ if (raw_pci_ext_ops == NULL)
	174	+ raw_pci_ext_ops = &pci_mmcfg;
	175	+ info->mcfg_added = true;
	176	+ } else if (result != -EEXIST)
	177	+ return check_segment(seg, dev,
	178	+ "fail to add MMCONFIG information,");
	179	+
	180	+ return 0;
	181	+}
	182	+
	183	+static void teardown_mcfg_map(struct pci_root_info *info)
	184	+{
	185	+ if (info->mcfg_added) {
	186	+ pci_mmconfig_delete(info->segment, info->start_bus,
	187	+ info->end_bus);
	188	+ info->mcfg_added = false;
	189	+ }
	190	+}
	191	+#else
	192	+static int __devinit setup_mcfg_map(struct pci_root_info *info,
	193	+ u16 seg, u8 start, u8 end,
	194	+ phys_addr_t addr)
	195	+{
	196	+ return 0;
	197	+}
	198	+static void teardown_mcfg_map(struct pci_root_info *info)
	199	+{
	200	+}
	201	+#endif
	202	+
123	203	static acpi_status
124	204	resource_to_addr(struct acpi_resource *resource,
125	205	struct acpi_resource_address64 *addr)
@@ -234,13 +314,6 @@ setup_resource(struct acpi_resource acpi_res, void data) · 108 unmodified lines
234	314	}
235	315
236	316	info->res_num++;
237		− if (addr.translation_offset)
238		− dev_info(&info->bridge->dev, "host bridge window %pR "
239		− "(PCI address [%#llx-%#llx])\n",
240		− res, res->start - addr.translation_offset,
241		− res->end - addr.translation_offset);
242		− else
243		− dev_info(&info->bridge->dev, "host bridge window %pR\n", res);
244	317
245	318	return AE_OK;
246	319	}
@@ -332,8 +405,11 @@ static void __release_pci_root_info(struct pci_root_info *info) · 85 unmodified lines
332	405
333	406	free_pci_root_info_res(info);
334	407
	408	+ teardown_mcfg_map(info);
	409	+
335	410	kfree(info);
336	411	}
	412	+
337	413	static void release_pci_root_info(struct pci_host_bridge *bridge)
338	414	{
339	415	struct pci_root_info *info = bridge->release_data;
@@ -347,7 +423,9 @@ probe_pci_root_info(struct pci_root_info info, struct acpi_device device, · 7 unmodified lines
347	423	{
348	424	size_t size;
349	425
	426	+ sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
350	427	info->bridge = device;
	428	+
351	429	info->res_num = 0;
352	430	acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource,
353	431	info);
@@ -360,8 +438,6 @@ probe_pci_root_info(struct pci_root_info info, struct acpi_device device, · 6 unmodified lines
360	438	if (!info->res)
361	439	return;
362	440
363		− sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
364		−
365	441	acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource,
366	442	info);
367	443	}
@@ -373,7 +449,7 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) · 5 unmodified lines
373	449	int domain = root->segment;
374	450	int busnum = root->secondary.start;
375	451	LIST_HEAD(resources);
376		− struct pci_bus *bus;
	452	+ struct pci_bus *bus = NULL;
377	453	struct pci_sysdata *sd;
378	454	int node;
379	455	#ifdef CONFIG_ACPI_NUMA
@@ -426,6 +502,8 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) · 46 unmodified lines
426	502	} else {
427	503	probe_pci_root_info(info, device, busnum, domain);
428	504
	505	+ /* insert busn res at first */
	506	+ pci_add_resource(&resources, &root->secondary);
429	507	/*
430	508	* _CRS with no apertures is normal, so only fall back to
431	509	* defaults or native bridge info if we're ignoring _CRS.
@@ -437,10 +515,13 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) · 5 unmodified lines
437	515	x86_pci_root_bus_resources(busnum, &resources);
438	516	}
439	517
440		− bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd,
441		− &resources);
	518	+ if (!setup_mcfg_map(info, domain, (u8)root->secondary.start,
	519	+ (u8)root->secondary.end, root->mcfg_addr))
	520	+ bus = pci_create_root_bus(NULL, busnum, &pci_root_ops,
	521	+ sd, &resources);
	522	+
442	523	if (bus) {
443		− bus->subordinate = pci_scan_child_bus(bus);
	524	+ pci_scan_child_bus(bus);
444	525	pci_set_host_bridge_release(
445	526	to_pci_host_bridge(bus->bridge),
446	527	release_pci_root_info, info);

arch/x86/pci/amd_bus.c+3−4

@@ -121,7 +121,6 @@ static int __init early_fill_mp_bus_info(void) · 120 unmodified lines
121	121	link = (reg >> 8) & 0x03;
122	122
123	123	info = alloc_pci_root_info(min_bus, max_bus, node, link);
124		− sprintf(info->name, "PCI Bus #%02x", min_bus);
125	124	}
126	125
127	126	/* get the default node and link for left over res */
@@ -300,9 +299,9 @@ static int __init early_fill_mp_bus_info(void) · 172 unmodified lines
300	299	int busnum;
301	300	struct pci_root_res *root_res;
302	301
303		− busnum = info->bus_min;
304		− printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
305		− info->bus_min, info->bus_max, info->node, info->link);
	302	+ busnum = info->busn.start;
	303	+ printk(KERN_DEBUG "bus: %pR on node %x link %x\n",
	304	+ &info->busn, info->node, info->link);
306	305	list_for_each_entry(root_res, &info->resources, list)
307	306	printk(KERN_DEBUG "bus: %02x %pR\n",
308	307	busnum, &root_res->res);

arch/x86/pci/bus_numa.c+19−3

@@ -14,7 +14,7 @@ static struct pci_root_info *x86_find_pci_root_info(int bus) · 13 unmodified lines
14	14	return NULL;
15	15
16	16	list_for_each_entry(info, &pci_root_infos, list)
17		− if (info->bus_min == bus)
	17	+ if (info->busn.start == bus)
18	18	return info;
19	19
20	20	return NULL;
@@ -24,6 +24,8 @@ void x86_pci_root_bus_resources(int bus, struct list_head *resources) · 3 unmodified lines
24	24	{
25	25	struct pci_root_info *info = x86_find_pci_root_info(bus);
26	26	struct pci_root_res *root_res;
	27	+ struct pci_host_bridge_window *window;
	28	+ bool found = false;
27	29
28	30	if (!info)
29	31	goto default_resources;
@@ -31,6 +33,16 @@ void x86_pci_root_bus_resources(int bus, struct list_head *resources) · 1 unmodified line
31	33	printk(KERN_DEBUG "PCI: root bus %02x: hardware-probed resources\n",
32	34	bus);
33	35
	36	+ /* already added by acpi ? */
	37	+ list_for_each_entry(window, resources, list)
	38	+ if (window->res->flags & IORESOURCE_BUS) {
	39	+ found = true;
	40	+ break;
	41	+ }
	42	+
	43	+ if (!found)
	44	+ pci_add_resource(resources, &info->busn);
	45	+
34	46	list_for_each_entry(root_res, &info->resources, list) {
35	47	struct resource *res;
36	48	struct resource *root;
@@ -66,9 +78,13 @@ struct pci_root_info __init *alloc_pci_root_info(int bus_min, int bus_max, · 29 unmodified lines
66	78	if (!info)
67	79	return info;
68	80
	81	+ sprintf(info->name, "PCI Bus #%02x", bus_min);
	82	+
69	83	INIT_LIST_HEAD(&info->resources);
70		− info->bus_min = bus_min;
71		− info->bus_max = bus_max;
	84	+ info->busn.name = info->name;
	85	+ info->busn.start = bus_min;
	86	+ info->busn.end = bus_max;
	87	+ info->busn.flags = IORESOURCE_BUS;
72	88	info->node = node;
73	89	info->link = link;
74	90

arch/x86/pci/bus_numa.h+1−2

@@ -13,8 +13,7 @@ struct pci_root_info { · 12 unmodified lines
13	13	struct list_head list;
14	14	char name[12];
15	15	struct list_head resources;
16		− int bus_min;
17		− int bus_max;
	16	+ struct resource busn;
18	17	int node;
19	18	int link;
20	19	};

arch/x86/pci/common.c+1−1

@@ -494,7 +494,7 @@ int __init pcibios_init(void) · 493 unmodified lines
494	494	return 0;
495	495	}
496	496
497		−char * __devinit pcibios_setup(char *str)
	497	+char * __init pcibios_setup(char *str)
498	498	{
499	499	if (!strcmp(str, "off")) {
500	500	pci_probe = 0;

arch/x86/pci/mmconfig-shared.c+248−124

@@ -17,6 +17,8 @@ · 16 unmodified lines
17	17	#include <linux/bitmap.h>
18	18	#include <linux/dmi.h>
19	19	#include <linux/slab.h>
	20	+#include <linux/mutex.h>
	21	+#include <linux/rculist.h>
20	22	#include <asm/e820.h>
21	23	#include <asm/pci_x86.h>
22	24	#include <asm/acpi.h>
@@ -24,7 +26,9 @@ · 1 unmodified line
24	26	#define PREFIX "PCI: "
25	27
26	28	/* Indicate if the mmcfg resources have been placed into the resource table. */
27		−static int __initdata pci_mmcfg_resources_inserted;
	29	+static bool pci_mmcfg_running_state;
	30	+static bool pci_mmcfg_arch_init_failed;
	31	+static DEFINE_MUTEX(pci_mmcfg_lock);
28	32
29	33	LIST_HEAD(pci_mmcfg_list);
30	34
@@ -45,24 +49,25 @@ static __init void free_all_mmcfg(void) · 14 unmodified lines
45	49	pci_mmconfig_remove(cfg);
46	50	}
47	51
48		−static __init void list_add_sorted(struct pci_mmcfg_region *new)
	52	+static __devinit void list_add_sorted(struct pci_mmcfg_region *new)
49	53	{
50	54	struct pci_mmcfg_region *cfg;
51	55
52	56	/* keep list sorted by segment and starting bus number */
53		− list_for_each_entry(cfg, &pci_mmcfg_list, list) {
	57	+ list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
54	58	if (cfg->segment > new->segment \|\|
55	59	(cfg->segment == new->segment &&
56	60	cfg->start_bus >= new->start_bus)) {
57		− list_add_tail(&new->list, &cfg->list);
	61	+ list_add_tail_rcu(&new->list, &cfg->list);
58	62	return;
59	63	}
60	64	}
61		− list_add_tail(&new->list, &pci_mmcfg_list);
	65	+ list_add_tail_rcu(&new->list, &pci_mmcfg_list);
62	66	}
63	67
64		−static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
65		− int end, u64 addr)
	68	+static __devinit struct pci_mmcfg_region *pci_mmconfig_alloc(int segment,
	69	+ int start,
	70	+ int end, u64 addr)
66	71	{
67	72	struct pci_mmcfg_region *new;
68	73	struct resource *res;
@@ -79,8 +84,6 @@ static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, · 10 unmodified lines
79	84	new->start_bus = start;
80	85	new->end_bus = end;
81	86
82		− list_add_sorted(new);
83		−
84	87	res = &new->res;
85	88	res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
86	89	res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
@@ -89,9 +92,25 @@ static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, · 2 unmodified lines
89	92	"PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
90	93	res->name = new->name;
91	94
92		− printk(KERN_INFO PREFIX "MMCONFIG for domain %04x [bus %02x-%02x] at "
93		− "%pR (base %#lx)\n", segment, start, end, &new->res,
94		− (unsigned long) addr);
	95	+ return new;
	96	+}
	97	+
	98	+static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
	99	+ int end, u64 addr)
	100	+{
	101	+ struct pci_mmcfg_region *new;
	102	+
	103	+ new = pci_mmconfig_alloc(segment, start, end, addr);
	104	+ if (new) {
	105	+ mutex_lock(&pci_mmcfg_lock);
	106	+ list_add_sorted(new);
	107	+ mutex_unlock(&pci_mmcfg_lock);
	108	+
	109	+ pr_info(PREFIX
	110	+ "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
	111	+ "(base %#lx)\n",
	112	+ segment, start, end, &new->res, (unsigned long)addr);
	113	+ }
95	114
96	115	return new;
97	116	}
@@ -100,7 +119,7 @@ struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus) · 2 unmodified lines
100	119	{
101	120	struct pci_mmcfg_region *cfg;
102	121
103		− list_for_each_entry(cfg, &pci_mmcfg_list, list)
	122	+ list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
104	123	if (cfg->segment == segment &&
105	124	cfg->start_bus <= bus && bus <= cfg->end_bus)
106	125	return cfg;
@@ -343,8 +362,7 @@ static int __init pci_mmcfg_check_hostbridge(void) · 236 unmodified lines
343	362	name = pci_mmcfg_probes[i].probe();
344	363
345	364	if (name)
346		− printk(KERN_INFO PREFIX "%s with MMCONFIG support\n",
347		− name);
	365	+ pr_info(PREFIX "%s with MMCONFIG support\n", name);
348	366	}
349	367
350	368	/* some end_bus_number is crazy, fix it */
@@ -353,19 +371,8 @@ static int __init pci_mmcfg_check_hostbridge(void) · 2 unmodified lines
353	371	return !list_empty(&pci_mmcfg_list);
354	372	}
355	373
356		−static void __init pci_mmcfg_insert_resources(void)
357		−{
358		− struct pci_mmcfg_region *cfg;
359		−
360		− list_for_each_entry(cfg, &pci_mmcfg_list, list)
361		− insert_resource(&iomem_resource, &cfg->res);
362		−
363		− /* Mark that the resources have been inserted. */
364		− pci_mmcfg_resources_inserted = 1;
365		−}
366		−
367		−static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
368		− void *data)
	374	+static acpi_status __devinit check_mcfg_resource(struct acpi_resource *res,
	375	+ void *data)
369	376	{
370	377	struct resource *mcfg_res = data;
371	378	struct acpi_resource_address64 address;
@@ -401,8 +408,8 @@ static acpi_status __init check_mcfg_resource(struct acpi_resource *res, · 29 unmodified lines
401	408	return AE_OK;
402	409	}
403	410
404		−static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
405		− void context, void *rv)
	411	+static acpi_status __devinit find_mboard_resource(acpi_handle handle, u32 lvl,
	412	+ void context, void *rv)
406	413	{
407	414	struct resource *mcfg_res = context;
408	415
@@ -415,7 +422,7 @@ static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, · 6 unmodified lines
415	422	return AE_OK;
416	423	}
417	424
418		−static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
	425	+static int __devinit is_acpi_reserved(u64 start, u64 end, unsigned not_used)
419	426	{
420	427	struct resource mcfg_res;
421	428
@@ -434,13 +441,15 @@ static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used) · 12 unmodified lines
434	441
435	442	typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
436	443
437		−static int __init is_mmconf_reserved(check_reserved_t is_reserved,
438		− struct pci_mmcfg_region *cfg, int with_e820)
	444	+static int __ref is_mmconf_reserved(check_reserved_t is_reserved,
	445	+ struct pci_mmcfg_region *cfg,
	446	+ struct device *dev, int with_e820)
439	447	{
440	448	u64 addr = cfg->res.start;
441	449	u64 size = resource_size(&cfg->res);
442	450	u64 old_size = size;
443		− int valid = 0, num_buses;
	451	+ int num_buses;
	452	+ char *method = with_e820 ? "E820" : "ACPI motherboard resources";
444	453
445	454	while (!is_reserved(addr, addr + size, E820_RESERVED)) {
446	455	size >>= 1;
@@ -448,30 +457,76 @@ static int __init is_mmconf_reserved(check_reserved_t is_reserved, · 1 unmodified line
448	457	break;
449	458	}
450	459
451		− if (size >= (16UL<<20) \|\| size == old_size) {
452		− printk(KERN_INFO PREFIX "MMCONFIG at %pR reserved in %s\n",
453		− &cfg->res,
454		− with_e820 ? "E820" : "ACPI motherboard resources");
455		− valid = 1;
456		−
457		− if (old_size != size) {
458		− /* update end_bus */
459		− cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
460		− num_buses = cfg->end_bus - cfg->start_bus + 1;
461		− cfg->res.end = cfg->res.start +
462		− PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
463		− snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
464		− "PCI MMCONFIG %04x [bus %02x-%02x]",
465		− cfg->segment, cfg->start_bus, cfg->end_bus);
466		− printk(KERN_INFO PREFIX
467		− "MMCONFIG for %04x [bus%02x-%02x] "
468		− "at %pR (base %#lx) (size reduced!)\n",
469		− cfg->segment, cfg->start_bus, cfg->end_bus,
470		− &cfg->res, (unsigned long) cfg->address);
471		− }
	460	+ if (size < (16UL<<20) && size != old_size)
	461	+ return 0;
	462	+
	463	+ if (dev)
	464	+ dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
	465	+ &cfg->res, method);
	466	+ else
	467	+ pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
	468	+ &cfg->res, method);
	469	+
	470	+ if (old_size != size) {
	471	+ /* update end_bus */
	472	+ cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
	473	+ num_buses = cfg->end_bus - cfg->start_bus + 1;
	474	+ cfg->res.end = cfg->res.start +
	475	+ PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
	476	+ snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
	477	+ "PCI MMCONFIG %04x [bus %02x-%02x]",
	478	+ cfg->segment, cfg->start_bus, cfg->end_bus);
	479	+
	480	+ if (dev)
	481	+ dev_info(dev,
	482	+ "MMCONFIG "
	483	+ "at %pR (base %#lx) (size reduced!)\n",
	484	+ &cfg->res, (unsigned long) cfg->address);
	485	+ else
	486	+ pr_info(PREFIX
	487	+ "MMCONFIG for %04x [bus%02x-%02x] "
	488	+ "at %pR (base %#lx) (size reduced!)\n",
	489	+ cfg->segment, cfg->start_bus, cfg->end_bus,
	490	+ &cfg->res, (unsigned long) cfg->address);
472	491	}
473	492
474		− return valid;
	493	+ return 1;
	494	+}
	495	+
	496	+static int __ref pci_mmcfg_check_reserved(struct device *dev,
	497	+ struct pci_mmcfg_region *cfg, int early)
	498	+{
	499	+ if (!early && !acpi_disabled) {
	500	+ if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
	501	+ return 1;
	502	+
	503	+ if (dev)
	504	+ dev_info(dev, FW_INFO
	505	+ "MMCONFIG at %pR not reserved in "
	506	+ "ACPI motherboard resources\n",
	507	+ &cfg->res);
	508	+ else
	509	+ pr_info(FW_INFO PREFIX
	510	+ "MMCONFIG at %pR not reserved in "
	511	+ "ACPI motherboard resources\n",
	512	+ &cfg->res);
	513	+ }
	514	+
	515	+ /*
	516	+ * e820_all_mapped() is marked as __init.
	517	+ * All entries from ACPI MCFG table have been checked at boot time.
	518	+ * For MCFG information constructed from hotpluggable host bridge's
	519	+ * _CBA method, just assume it's reserved.
	520	+ */
	521	+ if (pci_mmcfg_running_state)
	522	+ return 1;
	523	+
	524	+ /* Don't try to do this check unless configuration
	525	+ type 1 is available. how about type 2 ?*/
	526	+ if (raw_pci_ops)
	527	+ return is_mmconf_reserved(e820_all_mapped, cfg, dev, 1);
	528	+
	529	+ return 0;
475	530	}
476	531
477	532	static void __init pci_mmcfg_reject_broken(int early)
@@ -479,38 +534,14 @@ static void __init pci_mmcfg_reject_broken(int early) · 1 unmodified line
479	534	struct pci_mmcfg_region *cfg;
480	535
481	536	list_for_each_entry(cfg, &pci_mmcfg_list, list) {
482		− int valid = 0;
483		−
484		− if (!early && !acpi_disabled) {
485		− valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0);
486		−
487		− if (valid)
488		− continue;
489		− else
490		− printk(KERN_ERR FW_BUG PREFIX
491		− "MMCONFIG at %pR not reserved in "
492		− "ACPI motherboard resources\n",
493		− &cfg->res);
	537	+ if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
	538	+ pr_info(PREFIX "not using MMCONFIG\n");
	539	+ free_all_mmcfg();
	540	+ return;
494	541	}
495		−
496		− /* Don't try to do this check unless configuration
497		− type 1 is available. how about type 2 ?*/
498		− if (raw_pci_ops)
499		− valid = is_mmconf_reserved(e820_all_mapped, cfg, 1);
500		−
501		− if (!valid)
502		− goto reject;
503	542	}
504		−
505		− return;
506		−
507		−reject:
508		− printk(KERN_INFO PREFIX "not using MMCONFIG\n");
509		− free_all_mmcfg();
510	543	}
511	544
512		−static int __initdata known_bridge;
513		−
514	545	static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
515	546	struct acpi_mcfg_allocation *cfg)
516	547	{
@@ -529,7 +560,7 @@ static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, · 12 unmodified lines
529	560	return 0;
530	561	}
531	562
532		− printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
	563	+ pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
533	564	"is above 4GB, ignored\n", cfg->pci_segment,
534	565	cfg->start_bus_number, cfg->end_bus_number, cfg->address);
535	566	return -EINVAL;
@@ -556,7 +587,7 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header) · 20 unmodified lines
556	587	i -= sizeof(struct acpi_mcfg_allocation);
557	588	};
558	589	if (entries == 0) {
559		− printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
	590	+ pr_err(PREFIX "MMCONFIG has no entries\n");
560	591	return -ENODEV;
561	592	}
562	593
@@ -570,8 +601,7 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header) · 7 unmodified lines
570	601
571	602	if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
572	603	cfg->end_bus_number, cfg->address) == NULL) {
573		− printk(KERN_WARNING PREFIX
574		− "no memory for MCFG entries\n");
	604	+ pr_warn(PREFIX "no memory for MCFG entries\n");
575	605	free_all_mmcfg();
576	606	return -ENOMEM;
577	607	}
@@ -582,28 +612,7 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header) · 4 unmodified lines
582	612
583	613	static void __init __pci_mmcfg_init(int early)
584	614	{
585		− /* MMCONFIG disabled */
586		− if ((pci_probe & PCI_PROBE_MMCONF) == 0)
587		− return;
588		−
589		− /* MMCONFIG already enabled */
590		− if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
591		− return;
592		−
593		− /* for late to exit */
594		− if (known_bridge)
595		− return;
596		−
597		− if (early) {
598		− if (pci_mmcfg_check_hostbridge())
599		− known_bridge = 1;
600		− }
601		−
602		− if (!known_bridge)
603		− acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
604		−
605	615	pci_mmcfg_reject_broken(early);
606		−
607	616	if (list_empty(&pci_mmcfg_list))
608	617	return;
609	618
@@ -620,33 +629,48 @@ static void __init __pci_mmcfg_init(int early) · 10 unmodified lines
620	629	if (pci_mmcfg_arch_init())
621	630	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
622	631	else {
623		− /*
624		− * Signal not to attempt to insert mmcfg resources because
625		− * the architecture mmcfg setup could not initialize.
626		− */
627		− pci_mmcfg_resources_inserted = 1;
	632	+ free_all_mmcfg();
	633	+ pci_mmcfg_arch_init_failed = true;
628	634	}
629	635	}
630	636
	637	+static int __initdata known_bridge;
	638	+
631	639	void __init pci_mmcfg_early_init(void)
632	640	{
633		− __pci_mmcfg_init(1);
	641	+ if (pci_probe & PCI_PROBE_MMCONF) {
	642	+ if (pci_mmcfg_check_hostbridge())
	643	+ known_bridge = 1;
	644	+ else
	645	+ acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
	646	+ __pci_mmcfg_init(1);
	647	+ }
634	648	}
635	649
636	650	void __init pci_mmcfg_late_init(void)
637	651	{
638		− __pci_mmcfg_init(0);
	652	+ /* MMCONFIG disabled */
	653	+ if ((pci_probe & PCI_PROBE_MMCONF) == 0)
	654	+ return;
	655	+
	656	+ if (known_bridge)
	657	+ return;
	658	+
	659	+ /* MMCONFIG hasn't been enabled yet, try again */
	660	+ if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
	661	+ acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
	662	+ __pci_mmcfg_init(0);
	663	+ }
639	664	}
640	665
641	666	static int __init pci_mmcfg_late_insert_resources(void)
642	667	{
643		− /*
644		− * If resources are already inserted or we are not using MMCONFIG,
645		− * don't insert the resources.
646		− */
647		− if ((pci_mmcfg_resources_inserted == 1) \|\|
648		− (pci_probe & PCI_PROBE_MMCONF) == 0 \|\|
649		− list_empty(&pci_mmcfg_list))
	668	+ struct pci_mmcfg_region *cfg;
	669	+
	670	+ pci_mmcfg_running_state = true;
	671	+
	672	+ /* If we are not using MMCONFIG, don't insert the resources. */
	673	+ if ((pci_probe & PCI_PROBE_MMCONF) == 0)
650	674	return 1;
651	675
652	676	/*
@@ -654,7 +678,9 @@ static int __init pci_mmcfg_late_insert_resources(void) · 1 unmodified line
654	678	* marked so it won't cause request errors when __request_region is
655	679	* called.
656	680	*/
657		− pci_mmcfg_insert_resources();
	681	+ list_for_each_entry(cfg, &pci_mmcfg_list, list)
	682	+ if (!cfg->res.parent)
	683	+ insert_resource(&iomem_resource, &cfg->res);
658	684
659	685	return 0;
660	686	}
@@ -665,3 +691,101 @@ static int __init pci_mmcfg_late_insert_resources(void) · 4 unmodified lines
665	691	* with other system resources.
666	692	*/
667	693	late_initcall(pci_mmcfg_late_insert_resources);
	694	+
	695	+/* Add MMCFG information for host bridges */
	696	+int __devinit pci_mmconfig_insert(struct device *dev,
	697	+ u16 seg, u8 start, u8 end,
	698	+ phys_addr_t addr)
	699	+{
	700	+ int rc;
	701	+ struct resource *tmp = NULL;
	702	+ struct pci_mmcfg_region *cfg;
	703	+
	704	+ if (!(pci_probe & PCI_PROBE_MMCONF) \|\| pci_mmcfg_arch_init_failed)
	705	+ return -ENODEV;
	706	+
	707	+ if (start > end)
	708	+ return -EINVAL;
	709	+
	710	+ mutex_lock(&pci_mmcfg_lock);
	711	+ cfg = pci_mmconfig_lookup(seg, start);
	712	+ if (cfg) {
	713	+ if (cfg->end_bus < end)
	714	+ dev_info(dev, FW_INFO
	715	+ "MMCONFIG for "
	716	+ "domain %04x [bus %02x-%02x] "
	717	+ "only partially covers this bridge\n",
	718	+ cfg->segment, cfg->start_bus, cfg->end_bus);
	719	+ mutex_unlock(&pci_mmcfg_lock);
	720	+ return -EEXIST;
	721	+ }
	722	+
	723	+ if (!addr) {
	724	+ mutex_unlock(&pci_mmcfg_lock);
	725	+ return -EINVAL;
	726	+ }
	727	+
	728	+ rc = -EBUSY;
	729	+ cfg = pci_mmconfig_alloc(seg, start, end, addr);
	730	+ if (cfg == NULL) {
	731	+ dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
	732	+ rc = -ENOMEM;
	733	+ } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
	734	+ dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
	735	+ &cfg->res);
	736	+ } else {
	737	+ /* Insert resource if it's not in boot stage */
	738	+ if (pci_mmcfg_running_state)
	739	+ tmp = insert_resource_conflict(&iomem_resource,
	740	+ &cfg->res);
	741	+
	742	+ if (tmp) {
	743	+ dev_warn(dev,
	744	+ "MMCONFIG %pR conflicts with "
	745	+ "%s %pR\n",
	746	+ &cfg->res, tmp->name, tmp);
	747	+ } else if (pci_mmcfg_arch_map(cfg)) {
	748	+ dev_warn(dev, "fail to map MMCONFIG %pR.\n",
	749	+ &cfg->res);
	750	+ } else {
	751	+ list_add_sorted(cfg);
	752	+ dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
	753	+ &cfg->res, (unsigned long)addr);
	754	+ cfg = NULL;
	755	+ rc = 0;
	756	+ }
	757	+ }
	758	+
	759	+ if (cfg) {
	760	+ if (cfg->res.parent)
	761	+ release_resource(&cfg->res);
	762	+ kfree(cfg);
	763	+ }
	764	+
	765	+ mutex_unlock(&pci_mmcfg_lock);
	766	+
	767	+ return rc;
	768	+}
	769	+
	770	+/* Delete MMCFG information for host bridges */
	771	+int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
	772	+{
	773	+ struct pci_mmcfg_region *cfg;
	774	+
	775	+ mutex_lock(&pci_mmcfg_lock);
	776	+ list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
	777	+ if (cfg->segment == seg && cfg->start_bus == start &&
	778	+ cfg->end_bus == end) {
	779	+ list_del_rcu(&cfg->list);
	780	+ synchronize_rcu();
	781	+ pci_mmcfg_arch_unmap(cfg);
	782	+ if (cfg->res.parent)
	783	+ release_resource(&cfg->res);
	784	+ mutex_unlock(&pci_mmcfg_lock);
	785	+ kfree(cfg);
	786	+ return 0;
	787	+ }
	788	+ mutex_unlock(&pci_mmcfg_lock);
	789	+
	790	+ return -ENOENT;
	791	+}

arch/x86/pci/mmconfig_32.c+27−3

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	11
12	12	#include <linux/pci.h>
13	13	#include <linux/init.h>
	14	+#include <linux/rcupdate.h>
14	15	#include <asm/e820.h>
15	16	#include <asm/pci_x86.h>
16	17	#include <acpi/acpi.h>
@@ -60,9 +61,12 @@ err: *value = -1; · 43 unmodified lines
60	61	return -EINVAL;
61	62	}
62	63
	64	+ rcu_read_lock();
63	65	base = get_base_addr(seg, bus, devfn);
64		− if (!base)
	66	+ if (!base) {
	67	+ rcu_read_unlock();
65	68	goto err;
	69	+ }
66	70
67	71	raw_spin_lock_irqsave(&pci_config_lock, flags);
68	72
@@ -80,6 +84,7 @@ err: *value = -1; · 11 unmodified lines
80	84	break;
81	85	}
82	86	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
	87	+ rcu_read_unlock();
83	88
84	89	return 0;
85	90	}
@@ -93,9 +98,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, · 7 unmodified lines
93	98	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095))
94	99	return -EINVAL;
95	100
	101	+ rcu_read_lock();
96	102	base = get_base_addr(seg, bus, devfn);
97		− if (!base)
	103	+ if (!base) {
	104	+ rcu_read_unlock();
98	105	return -EINVAL;
	106	+ }
99	107
100	108	raw_spin_lock_irqsave(&pci_config_lock, flags);
101	109
@@ -113,11 +121,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, · 11 unmodified lines
113	121	break;
114	122	}
115	123	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
	124	+ rcu_read_unlock();
116	125
117	126	return 0;
118	127	}
119	128
120		−static const struct pci_raw_ops pci_mmcfg = {
	129	+const struct pci_raw_ops pci_mmcfg = {
121	130	.read = pci_mmcfg_read,
122	131	.write = pci_mmcfg_write,
123	132	};
@@ -132,3 +141,18 @@ int __init pci_mmcfg_arch_init(void) · 8 unmodified lines
132	141	void __init pci_mmcfg_arch_free(void)
133	142	{
134	143	}
	144	+
	145	+int __devinit pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
	146	+{
	147	+ return 0;
	148	+}
	149	+
	150	+void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
	151	+{
	152	+ unsigned long flags;
	153	+
	154	+ /* Invalidate the cached mmcfg map entry. */
	155	+ raw_spin_lock_irqsave(&pci_config_lock, flags);
	156	+ mmcfg_last_accessed_device = 0;
	157	+ raw_spin_unlock_irqrestore(&pci_config_lock, flags);
	158	+}

arch/x86/pci/mmconfig_64.c+37−15

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	9	#include <linux/init.h>
10	10	#include <linux/acpi.h>
11	11	#include <linux/bitmap.h>
	12	+#include <linux/rcupdate.h>
12	13	#include <asm/e820.h>
13	14	#include <asm/pci_x86.h>
14	15
@@ -34,9 +35,12 @@ err: *value = -1; · 19 unmodified lines
34	35	return -EINVAL;
35	36	}
36	37
	38	+ rcu_read_lock();
37	39	addr = pci_dev_base(seg, bus, devfn);
38		− if (!addr)
	40	+ if (!addr) {
	41	+ rcu_read_unlock();
39	42	goto err;
	43	+ }
40	44
41	45	switch (len) {
42	46	case 1:
@@ -49,6 +53,7 @@ err: *value = -1; · 6 unmodified lines
49	53	*value = mmio_config_readl(addr + reg);
50	54	break;
51	55	}
	56	+ rcu_read_unlock();
52	57
53	58	return 0;
54	59	}
@@ -62,9 +67,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, · 7 unmodified lines
62	67	if (unlikely((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)))
63	68	return -EINVAL;
64	69
	70	+ rcu_read_lock();
65	71	addr = pci_dev_base(seg, bus, devfn);
66		− if (!addr)
	72	+ if (!addr) {
	73	+ rcu_read_unlock();
67	74	return -EINVAL;
	75	+ }
68	76
69	77	switch (len) {
70	78	case 1:
@@ -77,16 +85,17 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, · 6 unmodified lines
77	85	mmio_config_writel(addr + reg, value);
78	86	break;
79	87	}
	88	+ rcu_read_unlock();
80	89
81	90	return 0;
82	91	}
83	92
84		−static const struct pci_raw_ops pci_mmcfg = {
	93	+const struct pci_raw_ops pci_mmcfg = {
85	94	.read = pci_mmcfg_read,
86	95	.write = pci_mmcfg_write,
87	96	};
88	97
89		−static void __iomem * __init mcfg_ioremap(struct pci_mmcfg_region *cfg)
	98	+static void __iomem * __devinit mcfg_ioremap(struct pci_mmcfg_region *cfg)
90	99	{
91	100	void __iomem *addr;
92	101	u64 start, size;
@@ -105,16 +114,14 @@ int __init pci_mmcfg_arch_init(void) · 12 unmodified lines
105	114	{
106	115	struct pci_mmcfg_region *cfg;
107	116
108		− list_for_each_entry(cfg, &pci_mmcfg_list, list) {
109		− cfg->virt = mcfg_ioremap(cfg);
110		− if (!cfg->virt) {
111		− printk(KERN_ERR PREFIX "can't map MMCONFIG at %pR\n",
112		− &cfg->res);
	117	+ list_for_each_entry(cfg, &pci_mmcfg_list, list)
	118	+ if (pci_mmcfg_arch_map(cfg)) {
113	119	pci_mmcfg_arch_free();
114	120	return 0;
115	121	}
116		− }
	122	+
117	123	raw_pci_ext_ops = &pci_mmcfg;
	124	+
118	125	return 1;
119	126	}
120	127
@@ -122,10 +129,25 @@ void __init pci_mmcfg_arch_free(void) · 1 unmodified line
122	129	{
123	130	struct pci_mmcfg_region *cfg;
124	131
125		− list_for_each_entry(cfg, &pci_mmcfg_list, list) {
126		− if (cfg->virt) {
127		− iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
128		− cfg->virt = NULL;
129		− }
	132	+ list_for_each_entry(cfg, &pci_mmcfg_list, list)
	133	+ pci_mmcfg_arch_unmap(cfg);
	134	+}
	135	+
	136	+int __devinit pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
	137	+{
	138	+ cfg->virt = mcfg_ioremap(cfg);
	139	+ if (!cfg->virt) {
	140	+ pr_err(PREFIX "can't map MMCONFIG at %pR\n", &cfg->res);
	141	+ return -ENOMEM;
	142	+ }
	143	+
	144	+ return 0;
	145	+}
	146	+
	147	+void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
	148	+{
	149	+ if (cfg && cfg->virt) {
	150	+ iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
	151	+ cfg->virt = NULL;
130	152	}
131	153	}

arch/x86/pci/mrst.c+1−1

@@ -264,7 +264,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup); · 263 unmodified lines
264	264
265	265	static void __devinit mrst_power_off_unused_dev(struct pci_dev *dev)
266	266	{
267		− pci_set_power_state(dev, PCI_D3cold);
	267	+ pci_set_power_state(dev, PCI_D3hot);
268	268	}
269	269	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
270	270	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);

arch/xtensa/kernel/pci.c+1−7

@@ -46,7 +46,6 @@ · 45 unmodified lines
46	46	* pcibios_fixups
47	47	* pcibios_align_resource
48	48	* pcibios_fixup_bus
49		− * pcibios_setup
50	49	* pci_bus_add_device
51	50	* pci_mmap_page_range
52	51	*/
@@ -187,7 +186,7 @@ static int __init pcibios_init(void) · 134 unmodified lines
187	186	bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
188	187	pci_ctrl->ops, pci_ctrl, &resources);
189	188	pci_ctrl->bus = bus;
190		− pci_ctrl->last_busno = bus->subordinate;
	189	+ pci_ctrl->last_busno = bus->busn_res.end;
191	190	if (next_busno <= pci_ctrl->last_busno)
192	191	next_busno = pci_ctrl->last_busno+1;
193	192	}
@@ -206,11 +205,6 @@ void __init pcibios_fixup_bus(struct pci_bus *bus) · 12 unmodified lines
206	205	}
207	206	}
208	207
209		−char __init pcibios_setup(char str)
210		−{
211		− return str;
212		−}
213		−
214	208	void pcibios_set_master(struct pci_dev *dev)
215	209	{
216	210	/* No special bus mastering setup handling */

drivers/acpi/pci_root.c+2−0

@@ -505,6 +505,8 @@ static int __devinit acpi_pci_root_add(struct acpi_device *device) · 504 unmodified lines
505	505	strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS);
506	506	device->driver_data = root;
507	507
	508	+ root->mcfg_addr = acpi_pci_root_get_mcfg_addr(device->handle);
	509	+
508	510	/*
509	511	* All supported architectures that use ACPI have support for
510	512	* PCI domains, so we indicate this in _OSC support capabilities.

drivers/acpi/sleep.c+19−5

@@ -716,8 +716,9 @@ int acpi_suspend(u32 acpi_state) · 715 unmodified lines
716	716	* @dev: device to examine; its driver model wakeup flags control
717	717	* whether it should be able to wake up the system
718	718	* @d_min_p: used to store the upper limit of allowed states range
719		− * Return value: preferred power state of the device on success, -ENODEV on
720		− * failure (ie. if there's no 'struct acpi_device' for @dev)
	719	+ * @d_max_in: specify the lowest allowed states
	720	+ * Return value: preferred power state of the device on success, -ENODEV
	721	+ * (ie. if there's no 'struct acpi_device' for @dev) or -EINVAL on failure
721	722	*
722	723	* Find the lowest power (highest number) ACPI device power state that
723	724	* device @dev can be in while the system is in the sleep state represented
@@ -732,13 +733,15 @@ int acpi_suspend(u32 acpi_state) · 8 unmodified lines
732	733	* via @wake.
733	734	*/
734	735
735		−int acpi_pm_device_sleep_state(struct device dev, int d_min_p)
	736	+int acpi_pm_device_sleep_state(struct device dev, int d_min_p, int d_max_in)
736	737	{
737	738	acpi_handle handle = DEVICE_ACPI_HANDLE(dev);
738	739	struct acpi_device *adev;
739	740	char acpi_method[] = "_SxD";
740	741	unsigned long long d_min, d_max;
741	742
	743	+ if (d_max_in < ACPI_STATE_D0 \|\| d_max_in > ACPI_STATE_D3)
	744	+ return -EINVAL;
742	745	if (!handle \|\| ACPI_FAILURE(acpi_bus_get_device(handle, &adev))) {
743	746	printk(KERN_DEBUG "ACPI handle has no context!\n");
744	747	return -ENODEV;
@@ -746,8 +749,10 @@ int acpi_pm_device_sleep_state(struct device dev, int d_min_p) · 1 unmodified line
746	749
747	750	acpi_method[2] = '0' + acpi_target_sleep_state;
748	751	/*
749		− * If the sleep state is S0, we will return D3, but if the device has
750		− * _S0W, we will use the value from _S0W
	752	+ * If the sleep state is S0, the lowest limit from ACPI is D3,
	753	+ * but if the device has _S0W, we will use the value from _S0W
	754	+ * as the lowest limit from ACPI. Finally, we will constrain
	755	+ * the lowest limit with the specified one.
751	756	*/
752	757	d_min = ACPI_STATE_D0;
753	758	d_max = ACPI_STATE_D3;
@@ -791,8 +796,17 @@ int acpi_pm_device_sleep_state(struct device dev, int d_min_p) · 37 unmodified lines
791	796	}
792	797	}
793	798
	799	+ if (d_max_in < d_min)
	800	+ return -EINVAL;
794	801	if (d_min_p)
795	802	*d_min_p = d_min;
	803	+ /* constrain d_max with specified lowest limit (max number) */
	804	+ if (d_max > d_max_in) {
	805	+ for (d_max = d_max_in; d_max > d_min; d_max--) {
	806	+ if (adev->power.states[d_max].flags.valid)
	807	+ break;
	808	+ }
	809	+ }
796	810	return d_max;
797	811	}
798	812	#endif /* CONFIG_PM */

drivers/iommu/intel-iommu.c+1−1

@@ -661,7 +661,7 @@ static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn) · 660 unmodified lines
661	661	if (drhd->devices[i] &&
662	662	drhd->devices[i]->subordinate &&
663	663	drhd->devices[i]->subordinate->number <= bus &&
664		− drhd->devices[i]->subordinate->subordinate >= bus)
	664	+ drhd->devices[i]->subordinate->busn_res.end >= bus)
665	665	return drhd->iommu;
666	666	}
667	667

drivers/misc/cb710/core.c+1−1

@@ -180,7 +180,7 @@ static int cb710_suspend(struct pci_dev *pdev, pm_message_t state) · 179 unmodified lines
180	180	pci_save_state(pdev);
181	181	pci_disable_device(pdev);
182	182	if (state.event & PM_EVENT_SLEEP)
183		− pci_set_power_state(pdev, PCI_D3cold);
	183	+ pci_set_power_state(pdev, PCI_D3hot);
184	184	return 0;
185	185	}
186	186

drivers/net/ethernet/broadcom/tg3.c+2−2

@@ -14368,7 +14368,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) · 14367 unmodified lines
14368	14368	if (bridge->subordinate &&
14369	14369	(bridge->subordinate->number <=
14370	14370	tp->pdev->bus->number) &&
14371		− (bridge->subordinate->subordinate >=
	14371	+ (bridge->subordinate->busn_res.end >=
14372	14372	tp->pdev->bus->number)) {
14373	14373	tg3_flag_set(tp, 5701_DMA_BUG);
14374	14374	pci_dev_put(bridge);
@@ -14396,7 +14396,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) · 21 unmodified lines
14396	14396	if (bridge && bridge->subordinate &&
14397	14397	(bridge->subordinate->number <=
14398	14398	tp->pdev->bus->number) &&
14399		− (bridge->subordinate->subordinate >=
	14399	+ (bridge->subordinate->busn_res.end >=
14400	14400	tp->pdev->bus->number)) {
14401	14401	tg3_flag_set(tp, 40BIT_DMA_BUG);
14402	14402	pci_dev_put(bridge);

drivers/parisc/dino.c+11−5

@@ -174,7 +174,7 @@ static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, · 173 unmodified lines
174	174	int size, u32 *val)
175	175	{
176	176	struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
177		− u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
	177	+ u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
178	178	u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
179	179	void __iomem *base_addr = d->hba.base_addr;
180	180	unsigned long flags;
@@ -209,7 +209,7 @@ static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, · 28 unmodified lines
209	209	int size, u32 val)
210	210	{
211	211	struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
212		− u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
	212	+ u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
213	213	u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
214	214	void __iomem *base_addr = d->hba.base_addr;
215	215	unsigned long flags;
@@ -554,7 +554,7 @@ dino_fixup_bus(struct pci_bus *bus) · 338 unmodified lines
554	554	struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
555	555
556	556	DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n",
557		− __func__, bus, bus->secondary,
	557	+ __func__, bus, bus->busn_res.start,
558	558	bus->bridge->platform_data);
559	559
560	560	/* Firmware doesn't set up card-mode dino, so we have to */
@@ -898,6 +898,7 @@ static int __init dino_probe(struct parisc_device *dev) · 337 unmodified lines
898	898	LIST_HEAD(resources);
899	899	struct pci_bus *bus;
900	900	unsigned long hpa = dev->hpa.start;
	901	+ int max;
901	902
902	903	name = "Dino";
903	904	if (is_card_dino(&dev->id)) {
@@ -983,6 +984,10 @@ static int __init dino_probe(struct parisc_device *dev) · 79 unmodified lines
983	984	if (dino_dev->hba.gmmio_space.flags)
984	985	pci_add_resource(&resources, &dino_dev->hba.gmmio_space);
985	986
	987	+ dino_dev->hba.bus_num.start = dino_current_bus;
	988	+ dino_dev->hba.bus_num.end = 255;
	989	+ dino_dev->hba.bus_num.flags = IORESOURCE_BUS;
	990	+ pci_add_resource(&resources, &dino_dev->hba.bus_num);
986	991	/*
987	992	** It's not used to avoid chicken/egg problems
988	993	** with configuration accessor functions.
@@ -998,12 +1003,13 @@ static int __init dino_probe(struct parisc_device *dev) · 9 unmodified lines
998	1003	return 0;
999	1004	}
1000	1005
1001		− bus->subordinate = pci_scan_child_bus(bus);
	1006	+ max = pci_scan_child_bus(bus);
	1007	+ pci_bus_update_busn_res_end(bus, max);
1002	1008
1003	1009	/* This code depends on scanning being single threaded
1004	1010	* if it isn't, this global bus number count will fail
1005	1011	*/
1006		− dino_current_bus = bus->subordinate + 1;
	1012	+ dino_current_bus = max + 1;
1007	1013	pci_bus_assign_resources(bus);
1008	1014	pci_bus_add_devices(bus);
1009	1015	return 0;

drivers/parisc/iosapic.c+1−1

@@ -532,7 +532,7 @@ iosapic_xlate_pin(struct iosapic_info isi, struct pci_dev pcidev) · 531 unmodified lines
532	532	intr_slot = PCI_SLOT(pcidev->devfn);
533	533	}
534	534	DBG_IRT("iosapic_xlate_pin: bus %d slot %d pin %d\n",
535		− pcidev->bus->secondary, intr_slot, intr_pin);
	535	+ pcidev->bus->busn_res.start, intr_slot, intr_pin);
536	536
537	537	return irt_find_irqline(isi, intr_slot, intr_pin);
538	538	}

drivers/parisc/lba_pci.c+15−11

@@ -189,8 +189,8 @@ lba_dump_res(struct resource *r, int d) · 188 unmodified lines
189	189
190	190	static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
191	191	{
192		− u8 first_bus = d->hba.hba_bus->secondary;
193		− u8 last_sub_bus = d->hba.hba_bus->subordinate;
	192	+ u8 first_bus = d->hba.hba_bus->busn_res.start;
	193	+ u8 last_sub_bus = d->hba.hba_bus->busn_res.end;
194	194
195	195	if ((bus < first_bus) \|\|
196	196	(bus > last_sub_bus) \|\|
@@ -364,7 +364,7 @@ lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size) · 167 unmodified lines
364	364	static int elroy_cfg_read(struct pci_bus bus, unsigned int devfn, int pos, int size, u32 data)
365	365	{
366	366	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
367		− u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
	367	+ u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
368	368	u32 tok = LBA_CFG_TOK(local_bus, devfn);
369	369	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
370	370
@@ -380,7 +380,7 @@ static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int · 9 unmodified lines
380	380	return 0;
381	381	}
382	382
383		− if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->secondary, devfn, d)) {
	383	+ if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) {
384	384	DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos);
385	385	/* either don't want to look or know device isn't present. */
386	386	*data = ~0U;
@@ -431,7 +431,7 @@ lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size) · 44 unmodified lines
431	431	static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
432	432	{
433	433	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
434		− u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
	434	+ u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
435	435	u32 tok = LBA_CFG_TOK(local_bus,devfn);
436	436
437	437	if ((pos > 255) \|\| (devfn > 255))
@@ -444,7 +444,7 @@ static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int · 6 unmodified lines
444	444	return 0;
445	445	}
446	446
447		− if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) {
	447	+ if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) {
448	448	DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data);
449	449	return 1; /* New Workaround */
450	450	}
@@ -481,7 +481,7 @@ static struct pci_ops elroy_cfg_ops = { · 30 unmodified lines
481	481	static int mercury_cfg_read(struct pci_bus bus, unsigned int devfn, int pos, int size, u32 data)
482	482	{
483	483	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
484		− u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
	484	+ u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
485	485	u32 tok = LBA_CFG_TOK(local_bus, devfn);
486	486	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
487	487
@@ -514,7 +514,7 @@ static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, i · 26 unmodified lines
514	514	{
515	515	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
516	516	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
517		− u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
	517	+ u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
518	518	u32 tok = LBA_CFG_TOK(local_bus,devfn);
519	519
520	520	if ((pos > 255) \|\| (devfn > 255))
@@ -636,7 +636,7 @@ lba_fixup_bus(struct pci_bus *bus) · 115 unmodified lines
636	636	struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
637	637
638	638	DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
639		− bus, bus->secondary, bus->bridge->platform_data);
	639	+ bus, (int)bus->busn_res.start, bus->bridge->platform_data);
640	640
641	641	/*
642	642	** Properly Setup MMIO resources for this bus.
@@ -989,6 +989,7 @@ lba_pat_resources(struct parisc_device pa_dev, struct lba_device lba_dev) · 346 unmodified lines
989	989	case PAT_PBNUM:
990	990	lba_dev->hba.bus_num.start = p->start;
991	991	lba_dev->hba.bus_num.end = p->end;
	992	+ lba_dev->hba.bus_num.flags = IORESOURCE_BUS;
992	993	break;
993	994
994	995	case PAT_LMMIO:
@@ -1366,6 +1367,7 @@ lba_driver_probe(struct parisc_device *dev) · 371 unmodified lines
1366	1367	void *tmp_obj;
1367	1368	char *version;
1368	1369	void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096);
	1370	+ int max;
1369	1371
1370	1372	/* Read HW Rev First */
1371	1373	func_class = READ_REG32(addr + LBA_FCLASS);
@@ -1502,6 +1504,8 @@ lba_driver_probe(struct parisc_device *dev) · 130 unmodified lines
1502	1504	if (lba_dev->hba.gmmio_space.flags)
1503	1505	pci_add_resource(&resources, &lba_dev->hba.gmmio_space);
1504	1506
	1507	+ pci_add_resource(&resources, &lba_dev->hba.bus_num);
	1508	+
1505	1509	dev->dev.platform_data = lba_dev;
1506	1510	lba_bus = lba_dev->hba.hba_bus =
1507	1511	pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start,
@@ -1511,7 +1515,7 @@ lba_driver_probe(struct parisc_device *dev) · 3 unmodified lines
1511	1515	return 0;
1512	1516	}
1513	1517
1514		− lba_bus->subordinate = pci_scan_child_bus(lba_bus);
	1518	+ max = pci_scan_child_bus(lba_bus);
1515	1519
1516	1520	/* This is in lieu of calling pci_assign_unassigned_resources() */
1517	1521	if (is_pdc_pat()) {
@@ -1541,7 +1545,7 @@ lba_driver_probe(struct parisc_device *dev) · 23 unmodified lines
1541	1545	lba_dev->flags \|= LBA_FLAG_SKIP_PROBE;
1542	1546	}
1543	1547
1544		− lba_next_bus = lba_bus->subordinate + 1;
	1548	+ lba_next_bus = max + 1;
1545	1549	pci_bus_add_devices(lba_bus);
1546	1550
1547	1551	/* Whew! Finally done! Tell services we got this one covered. */

drivers/pci/Makefile+1−0

@@ -49,6 +49,7 @@ obj-$(CONFIG_MN10300) += setup-bus.o · 48 unmodified lines
49	49	obj-$(CONFIG_MICROBLAZE) += setup-bus.o
50	50	obj-$(CONFIG_TILE) += setup-bus.o setup-irq.o
51	51	obj-$(CONFIG_SPARC_LEON) += setup-bus.o setup-irq.o
	52	+obj-$(CONFIG_M68K) += setup-bus.o setup-irq.o
52	53
53	54	#
54	55	# ACPI Related PCI FW Functions

drivers/pci/access.c+4−2

@@ -162,7 +162,8 @@ int pci_user_read_config_##size \ · 161 unmodified lines
162	162	if (ret > 0) \
163	163	ret = -EINVAL; \
164	164	return ret; \
165		−}
	165	+} \
	166	+EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
166	167
167	168	/* Returns 0 on success, negative values indicate error. */
168	169	#define PCI_USER_WRITE_CONFIG(size,type) \
@@ -181,7 +182,8 @@ int pci_user_write_config_##size \ · 12 unmodified lines
181	182	if (ret > 0) \
182	183	ret = -EINVAL; \
183	184	return ret; \
184		−}
	185	+} \
	186	+EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
185	187
186	188	PCI_USER_READ_CONFIG(byte, u8)
187	189	PCI_USER_READ_CONFIG(word, u16)

drivers/pci/bus.c+2−0

@@ -164,6 +164,8 @@ pci_bus_alloc_resource(struct pci_bus bus, struct resource res, · 163 unmodified lines
164	164	int pci_bus_add_device(struct pci_dev *dev)
165	165	{
166	166	int retval;
	167	+
	168	+ pci_fixup_device(pci_fixup_final, dev);
167	169	retval = device_add(&dev->dev);
168	170	if (retval)
169	171	return retval;

drivers/pci/hotplug-pci.c+19−11

@@ -4,18 +4,26 @@ · 3 unmodified lines
4	4	#include <linux/export.h>
5	5	#include "pci.h"
6	6
7		−
8		−unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
	7	+int __ref pci_hp_add_bridge(struct pci_dev *dev)
9	8	{
10		− unsigned int max;
11		−
12		− max = pci_scan_child_bus(bus);
	9	+ struct pci_bus *parent = dev->bus;
	10	+ int pass, busnr, start = parent->busn_res.start;
	11	+ int end = parent->busn_res.end;
13	12
14		− /*
15		− * Make the discovered devices available.
16		− */
17		− pci_bus_add_devices(bus);
	13	+ for (busnr = start; busnr <= end; busnr++) {
	14	+ if (!pci_find_bus(pci_domain_nr(parent), busnr))
	15	+ break;
	16	+ }
	17	+ if (busnr-- > end) {
	18	+ printk(KERN_ERR "No bus number available for hot-added bridge %s\n",
	19	+ pci_name(dev));
	20	+ return -1;
	21	+ }
	22	+ for (pass = 0; pass < 2; pass++)
	23	+ busnr = pci_scan_bridge(parent, dev, busnr, pass);
	24	+ if (!dev->subordinate)
	25	+ return -1;
18	26
19		− return max;
	27	+ return 0;
20	28	}
21		−EXPORT_SYMBOL(pci_do_scan_bus);
	29	+EXPORT_SYMBOL_GPL(pci_hp_add_bridge);

drivers/pci/hotplug/acpiphp.h+1−3

@@ -89,8 +89,6 @@ struct acpiphp_bridge { · 88 unmodified lines
89	89
90	90	/* PCI-to-PCI bridge device */
91	91	struct pci_dev *pci_dev;
92		−
93		− spinlock_t res_lock;
94	92	};
95	93
96	94
@@ -207,6 +205,6 @@ extern u8 acpiphp_get_latch_status (struct acpiphp_slot *slot); · 110 unmodified lines
207	205	extern u8 acpiphp_get_adapter_status (struct acpiphp_slot *slot);
208	206
209	207	/* variables */
210		−extern int acpiphp_debug;
	208	+extern bool acpiphp_debug;
211	209
212	210	#endif /* _ACPIPHP_H */

drivers/pci/hotplug/acpiphp_core.c+2−5

@@ -47,8 +47,7 @@ · 46 unmodified lines
47	47	/* name size which is used for entries in pcihpfs */
48	48	#define SLOT_NAME_SIZE 21 /* {_SUN} */
49	49
50		−static bool debug;
51		−int acpiphp_debug;
	50	+bool acpiphp_debug;
52	51
53	52	/* local variables */
54	53	static int num_slots;
@@ -62,7 +61,7 @@ MODULE_AUTHOR(DRIVER_AUTHOR); · 7 unmodified lines
62	61	MODULE_DESCRIPTION(DRIVER_DESC);
63	62	MODULE_LICENSE("GPL");
64	63	MODULE_PARM_DESC(debug, "Debugging mode enabled or not");
65		−module_param(debug, bool, 0644);
	64	+module_param_named(debug, acpiphp_debug, bool, 0644);
66	65
67	66	/* export the attention callback registration methods */
68	67	EXPORT_SYMBOL_GPL(acpiphp_register_attention);
@@ -379,8 +378,6 @@ static int __init acpiphp_init(void) · 310 unmodified lines
379	378	if (acpi_pci_disabled)
380	379	return 0;
381	380
382		− acpiphp_debug = debug;
383		−
384	381	/* read all the ACPI info from the system */
385	382	return init_acpi();
386	383	}

drivers/pci/hotplug/acpiphp_glue.c+46−21

@@ -100,11 +100,11 @@ static int post_dock_fixups(struct notifier_block *nb, unsigned long val, · 99 unmodified lines
100	100	PCI_PRIMARY_BUS,
101	101	&buses);
102	102
103		− if (((buses >> 8) & 0xff) != bus->secondary) {
	103	+ if (((buses >> 8) & 0xff) != bus->busn_res.start) {
104	104	buses = (buses & 0xff000000)
105	105	\| ((unsigned int)(bus->primary) << 0)
106		− \| ((unsigned int)(bus->secondary) << 8)
107		− \| ((unsigned int)(bus->subordinate) << 16);
	106	+ \| ((unsigned int)(bus->busn_res.start) << 8)
	107	+ \| ((unsigned int)(bus->busn_res.end) << 16);
108	108	pci_write_config_dword(bus->self, PCI_PRIMARY_BUS, buses);
109	109	}
110	110	return NOTIFY_OK;
@@ -132,6 +132,15 @@ register_slot(acpi_handle handle, u32 lvl, void context, void *rv) · 21 unmodified lines
132	132	if (!acpi_pci_check_ejectable(pbus, handle) && !is_dock_device(handle))
133	133	return AE_OK;
134	134
	135	+ status = acpi_evaluate_integer(handle, "_ADR", NULL, &adr);
	136	+ if (ACPI_FAILURE(status)) {
	137	+ warn("can't evaluate _ADR (%#x)\n", status);
	138	+ return AE_OK;
	139	+ }
	140	+
	141	+ device = (adr >> 16) & 0xffff;
	142	+ function = adr & 0xffff;
	143	+
135	144	pdev = pbus->self;
136	145	if (pdev && pci_is_pcie(pdev)) {
137	146	tmp = acpi_find_root_bridge_handle(pdev);
@@ -144,10 +153,6 @@ register_slot(acpi_handle handle, u32 lvl, void context, void *rv) · 6 unmodified lines
144	153	}
145	154	}
146	155
147		− acpi_evaluate_integer(handle, "_ADR", NULL, &adr);
148		− device = (adr >> 16) & 0xffff;
149		− function = adr & 0xffff;
150		−
151	156	newfunc = kzalloc(sizeof(struct acpiphp_func), GFP_KERNEL);
152	157	if (!newfunc)
153	158	return AE_NO_MEMORY;
@@ -391,8 +396,6 @@ static void add_host_bridge(acpi_handle *handle) · 237 unmodified lines
391	396
392	397	bridge->pci_bus = root->bus;
393	398
394		− spin_lock_init(&bridge->res_lock);
395		−
396	399	init_bridge_misc(bridge);
397	400	}
398	401
@@ -425,7 +428,6 @@ static void add_p2p_bridge(acpi_handle *handle) · 26 unmodified lines
425	428	* (which we access during module unload).
426	429	*/
427	430	get_device(&bridge->pci_bus->dev);
428		− spin_lock_init(&bridge->res_lock);
429	431
430	432	init_bridge_misc(bridge);
431	433	return;
@@ -692,7 +694,7 @@ static unsigned char acpiphp_max_busnr(struct pci_bus *bus) · 260 unmodified lines
692	694	* bus->subordinate value because it could have
693	695	* padding in it.
694	696	*/
695		− max = bus->secondary;
	697	+ max = bus->busn_res.start;
696	698
697	699	list_for_each(tmp, &bus->children) {
698	700	n = pci_bus_max_busnr(pci_bus_b(tmp));
@@ -878,6 +880,24 @@ static void disable_bridges(struct pci_bus *bus) · 179 unmodified lines
878	880	}
879	881	}
880	882
	883	+/* return first device in slot, acquiring a reference on it */
	884	+static struct pci_dev dev_in_slot(struct acpiphp_slot slot)
	885	+{
	886	+ struct pci_bus *bus = slot->bridge->pci_bus;
	887	+ struct pci_dev *dev;
	888	+ struct pci_dev *ret = NULL;
	889	+
	890	+ down_read(&pci_bus_sem);
	891	+ list_for_each_entry(dev, &bus->devices, bus_list)
	892	+ if (PCI_SLOT(dev->devfn) == slot->device) {
	893	+ ret = pci_dev_get(dev);
	894	+ break;
	895	+ }
	896	+ up_read(&pci_bus_sem);
	897	+
	898	+ return ret;
	899	+}
	900	+
881	901	/**
882	902	* disable_device - disable a slot
883	903	* @slot: ACPI PHP slot
@@ -893,6 +913,7 @@ static int disable_device(struct acpiphp_slot *slot) · 9 unmodified lines
893	913	pdev = pci_get_slot(bus, PCI_DEVFN(slot->device, 0));
894	914	if (!pdev)
895	915	goto err_exit;
	916	+ pci_dev_put(pdev);
896	917
897	918	list_for_each_entry(func, &slot->funcs, sibling) {
898	919	if (func->bridge) {
@@ -901,18 +922,22 @@ static int disable_device(struct acpiphp_slot *slot) · 2 unmodified lines
901	922	(u32)1, NULL, NULL);
902	923	func->bridge = NULL;
903	924	}
	925	+ }
904	926
905		− pdev = pci_get_slot(slot->bridge->pci_bus,
906		− PCI_DEVFN(slot->device, func->function));
907		− if (pdev) {
908		− pci_stop_bus_device(pdev);
909		− if (pdev->subordinate) {
910		− disable_bridges(pdev->subordinate);
911		− pci_disable_device(pdev);
912		− }
913		− __pci_remove_bus_device(pdev);
914		− pci_dev_put(pdev);
	927	+ /*
	928	+ * enable_device() enumerates all functions in this device via
	929	+ * pci_scan_slot(), whether they have associated ACPI hotplug
	930	+ * methods (_EJ0, etc.) or not. Therefore, we remove all functions
	931	+ * here.
	932	+ */
	933	+ while ((pdev = dev_in_slot(slot))) {
	934	+ pci_stop_bus_device(pdev);
	935	+ if (pdev->subordinate) {
	936	+ disable_bridges(pdev->subordinate);
	937	+ pci_disable_device(pdev);
915	938	}
	939	+ __pci_remove_bus_device(pdev);
	940	+ pci_dev_put(pdev);
916	941	}
917	942
918	943	list_for_each_entry(func, &slot->funcs, sibling) {

drivers/pci/hotplug/cpci_hotplug_core.c+10−4

@@ -225,7 +225,7 @@ cpci_hp_register_bus(struct pci_bus *bus, u8 first, u8 last) · 224 unmodified lines
225	225	struct hotplug_slot *hotplug_slot;
226	226	struct hotplug_slot_info *info;
227	227	char name[SLOT_NAME_SIZE];
228		− int status = -ENOMEM;
	228	+ int status;
229	229	int i;
230	230
231	231	if (!(controller && bus))
@@ -237,18 +237,24 @@ cpci_hp_register_bus(struct pci_bus *bus, u8 first, u8 last) · 5 unmodified lines
237	237	*/
238	238	for (i = first; i <= last; ++i) {
239	239	slot = kzalloc(sizeof (struct slot), GFP_KERNEL);
240		− if (!slot)
	240	+ if (!slot) {
	241	+ status = -ENOMEM;
241	242	goto error;
	243	+ }
242	244
243	245	hotplug_slot =
244	246	kzalloc(sizeof (struct hotplug_slot), GFP_KERNEL);
245		− if (!hotplug_slot)
	247	+ if (!hotplug_slot) {
	248	+ status = -ENOMEM;
246	249	goto error_slot;
	250	+ }
247	251	slot->hotplug_slot = hotplug_slot;
248	252
249	253	info = kzalloc(sizeof (struct hotplug_slot_info), GFP_KERNEL);
250		− if (!info)
	254	+ if (!info) {
	255	+ status = -ENOMEM;
251	256	goto error_hpslot;
	257	+ }
252	258	hotplug_slot->info = info;
253	259
254	260	slot->bus = bus;

drivers/pci/hotplug/cpci_hotplug_pci.c+6−29

@@ -285,42 +285,19 @@ int __ref cpci_configure_slot(struct slot *slot) · 284 unmodified lines
285	285	for (fn = 0; fn < 8; fn++) {
286	286	struct pci_dev *dev;
287	287
288		− dev = pci_get_slot(parent, PCI_DEVFN(PCI_SLOT(slot->devfn), fn));
	288	+ dev = pci_get_slot(parent,
	289	+ PCI_DEVFN(PCI_SLOT(slot->devfn), fn));
289	290	if (!dev)
290	291	continue;
291	292	if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) \|\|
292		− (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) {
293		− /* Find an unused bus number for the new bridge */
294		− struct pci_bus *child;
295		− unsigned char busnr, start = parent->secondary;
296		− unsigned char end = parent->subordinate;
297		−
298		− for (busnr = start; busnr <= end; busnr++) {
299		− if (!pci_find_bus(pci_domain_nr(parent),
300		− busnr))
301		− break;
302		− }
303		− if (busnr >= end) {
304		− err("No free bus for hot-added bridge\n");
305		− pci_dev_put(dev);
306		− continue;
307		− }
308		− child = pci_add_new_bus(parent, dev, busnr);
309		− if (!child) {
310		− err("Cannot add new bus for %s\n",
311		− pci_name(dev));
312		− pci_dev_put(dev);
313		− continue;
314		− }
315		− child->subordinate = pci_do_scan_bus(child);
316		− pci_bus_size_bridges(child);
317		− }
	293	+ (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
	294	+ pci_hp_add_bridge(dev);
318	295	pci_dev_put(dev);
319	296	}
320	297
321		− pci_bus_assign_resources(parent);
	298	+ pci_assign_unassigned_bridge_resources(parent->self);
	299	+
322	300	pci_bus_add_devices(parent);
323		− pci_enable_bridges(parent);
324	301
325	302	dbg("%s - exit", __func__);
326	303	return 0;

drivers/pci/hotplug/cpqphp_core.c+10−4

@@ -611,7 +611,7 @@ static int ctrl_slot_setup(struct controller *ctrl, · 610 unmodified lines
611	611	u32 tempdword;
612	612	char name[SLOT_NAME_SIZE];
613	613	void __iomem *slot_entry= NULL;
614		− int result = -ENOMEM;
	614	+ int result;
615	615
616	616	dbg("%s\n", __func__);
617	617
@@ -623,19 +623,25 @@ static int ctrl_slot_setup(struct controller *ctrl, · 5 unmodified lines
623	623
624	624	while (number_of_slots) {
625	625	slot = kzalloc(sizeof(*slot), GFP_KERNEL);
626		− if (!slot)
	626	+ if (!slot) {
	627	+ result = -ENOMEM;
627	628	goto error;
	629	+ }
628	630
629	631	slot->hotplug_slot = kzalloc(sizeof(*(slot->hotplug_slot)),
630	632	GFP_KERNEL);
631		− if (!slot->hotplug_slot)
	633	+ if (!slot->hotplug_slot) {
	634	+ result = -ENOMEM;
632	635	goto error_slot;
	636	+ }
633	637	hotplug_slot = slot->hotplug_slot;
634	638
635	639	hotplug_slot->info = kzalloc(sizeof(*(hotplug_slot->info)),
636	640	GFP_KERNEL);
637		− if (!hotplug_slot->info)
	641	+ if (!hotplug_slot->info) {
	642	+ result = -ENOMEM;
638	643	goto error_hpslot;
	644	+ }
639	645	hotplug_slot_info = hotplug_slot->info;
640	646
641	647	slot->ctrl = ctrl;

drivers/pci/hotplug/cpqphp_pci.c+4−4

@@ -83,7 +83,6 @@ static void __iomem detect_HRT_floating_pointer(void __iomem begin, void __iom · 82 unmodified lines
83	83
84	84	int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func)
85	85	{
86		− unsigned char bus;
87	86	struct pci_bus *child;
88	87	int num;
89	88
@@ -106,9 +105,10 @@ int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func) · 16 unmodified lines
106	105	}
107	106
108	107	if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
109		− pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus);
110		− child = (struct pci_bus*) pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus);
111		− pci_do_scan_bus(child);
	108	+ pci_hp_add_bridge(func->pci_dev);
	109	+ child = func->pci_dev->subordinate;
	110	+ if (child)
	111	+ pci_bus_add_devices(child);
112	112	}
113	113
114	114	pci_dev_put(func->pci_dev);

drivers/pci/hotplug/ibmphp_core.c+4−4

@@ -775,7 +775,6 @@ static u8 bus_structure_fixup(u8 busno) · 774 unmodified lines
775	775
776	776	static int ibm_configure_device(struct pci_func *func)
777	777	{
778		− unsigned char bus;
779	778	struct pci_bus *child;
780	779	int num;
781	780	int flag = 0; /* this is to make sure we don't double scan the bus,
@@ -805,9 +804,10 @@ static int ibm_configure_device(struct pci_func *func) · 23 unmodified lines
805	804	}
806	805	}
807	806	if (!(flag) && (func->dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
808		− pci_read_config_byte(func->dev, PCI_SECONDARY_BUS, &bus);
809		− child = pci_add_new_bus(func->dev->bus, func->dev, bus);
810		− pci_do_scan_bus(child);
	807	+ pci_hp_add_bridge(func->dev);
	808	+ child = func->dev->subordinate;
	809	+ if (child)
	810	+ pci_bus_add_devices(child);
811	811	}
812	812
813	813	return 0;

drivers/pci/hotplug/pciehp.h+0−4

@@ -149,10 +149,6 @@ int pciehp_get_attention_status(struct slot slot, u8 status); · 148 unmodified lines
149	149	int pciehp_set_attention_status(struct slot *slot, u8 status);
150	150	int pciehp_get_latch_status(struct slot slot, u8 status);
151	151	int pciehp_get_adapter_status(struct slot slot, u8 status);
152		−int pciehp_get_max_link_speed(struct slot slot, enum pci_bus_speed speed);
153		−int pciehp_get_max_link_width(struct slot slot, enum pcie_link_width val);
154		−int pciehp_get_cur_link_speed(struct slot slot, enum pci_bus_speed speed);
155		−int pciehp_get_cur_link_width(struct slot slot, enum pcie_link_width val);
156	152	int pciehp_query_power_fault(struct slot *slot);
157	153	void pciehp_green_led_on(struct slot *slot);
158	154	void pciehp_green_led_off(struct slot *slot);

drivers/pci/hotplug/pciehp_hpc.c+0−101

@@ -705,107 +705,6 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) · 704 unmodified lines
705	705	return IRQ_HANDLED;
706	706	}
707	707
708		−int pciehp_get_max_lnk_width(struct slot *slot,
709		− enum pcie_link_width *value)
710		−{
711		− struct controller *ctrl = slot->ctrl;
712		− enum pcie_link_width lnk_wdth;
713		− u32 lnk_cap;
714		− int retval = 0;
715		−
716		− retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
717		− if (retval) {
718		− ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
719		− return retval;
720		− }
721		−
722		− switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
723		− case 0:
724		− lnk_wdth = PCIE_LNK_WIDTH_RESRV;
725		− break;
726		− case 1:
727		− lnk_wdth = PCIE_LNK_X1;
728		− break;
729		− case 2:
730		− lnk_wdth = PCIE_LNK_X2;
731		− break;
732		− case 4:
733		− lnk_wdth = PCIE_LNK_X4;
734		− break;
735		− case 8:
736		− lnk_wdth = PCIE_LNK_X8;
737		− break;
738		− case 12:
739		− lnk_wdth = PCIE_LNK_X12;
740		− break;
741		− case 16:
742		− lnk_wdth = PCIE_LNK_X16;
743		− break;
744		− case 32:
745		− lnk_wdth = PCIE_LNK_X32;
746		− break;
747		− default:
748		− lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
749		− break;
750		− }
751		−
752		− *value = lnk_wdth;
753		− ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
754		−
755		− return retval;
756		−}
757		−
758		−int pciehp_get_cur_lnk_width(struct slot *slot,
759		− enum pcie_link_width *value)
760		−{
761		− struct controller *ctrl = slot->ctrl;
762		− enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
763		− int retval = 0;
764		− u16 lnk_status;
765		−
766		− retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
767		− if (retval) {
768		− ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
769		− __func__);
770		− return retval;
771		− }
772		−
773		− switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
774		− case 0:
775		− lnk_wdth = PCIE_LNK_WIDTH_RESRV;
776		− break;
777		− case 1:
778		− lnk_wdth = PCIE_LNK_X1;
779		− break;
780		− case 2:
781		− lnk_wdth = PCIE_LNK_X2;
782		− break;
783		− case 4:
784		− lnk_wdth = PCIE_LNK_X4;
785		− break;
786		− case 8:
787		− lnk_wdth = PCIE_LNK_X8;
788		− break;
789		− case 12:
790		− lnk_wdth = PCIE_LNK_X12;
791		− break;
792		− case 16:
793		− lnk_wdth = PCIE_LNK_X16;
794		− break;
795		− case 32:
796		− lnk_wdth = PCIE_LNK_X32;
797		− break;
798		− default:
799		− lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
800		− break;
801		− }
802		−
803		− *value = lnk_wdth;
804		− ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
805		−
806		− return retval;
807		−}
808		−
809	708	int pcie_enable_notification(struct controller *ctrl)
810	709	{
811	710	u16 cmd, mask;

drivers/pci/hotplug/pciehp_pci.c+2−26

@@ -34,29 +34,6 @@ · 33 unmodified lines
34	34	#include "../pci.h"
35	35	#include "pciehp.h"
36	36
37		−static int __ref pciehp_add_bridge(struct pci_dev *dev)
38		−{
39		− struct pci_bus *parent = dev->bus;
40		− int pass, busnr, start = parent->secondary;
41		− int end = parent->subordinate;
42		−
43		− for (busnr = start; busnr <= end; busnr++) {
44		− if (!pci_find_bus(pci_domain_nr(parent), busnr))
45		− break;
46		− }
47		− if (busnr-- > end) {
48		− err("No bus number available for hot-added bridge %s\n",
49		− pci_name(dev));
50		− return -1;
51		− }
52		− for (pass = 0; pass < 2; pass++)
53		− busnr = pci_scan_bridge(parent, dev, busnr, pass);
54		− if (!dev->subordinate)
55		− return -1;
56		−
57		− return 0;
58		−}
59		−
60	37	int pciehp_configure_device(struct slot *p_slot)
61	38	{
62	39	struct pci_dev *dev;
@@ -85,9 +62,8 @@ int pciehp_configure_device(struct slot *p_slot) · 22 unmodified lines
85	62	if (!dev)
86	63	continue;
87	64	if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) \|\|
88		− (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) {
89		− pciehp_add_bridge(dev);
90		− }
	65	+ (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
	66	+ pci_hp_add_bridge(dev);
91	67	pci_dev_put(dev);
92	68	}
93	69

drivers/pci/hotplug/pcihp_skeleton.c+10−4

@@ -252,7 +252,7 @@ static int __init init_slots(void) · 251 unmodified lines
252	252	struct slot *slot;
253	253	struct hotplug_slot *hotplug_slot;
254	254	struct hotplug_slot_info *info;
255		− int retval = -ENOMEM;
	255	+ int retval;
256	256	int i;
257	257
258	258	/*
@@ -261,17 +261,23 @@ static int __init init_slots(void) · 2 unmodified lines
261	261	*/
262	262	for (i = 0; i < num_slots; ++i) {
263	263	slot = kzalloc(sizeof(*slot), GFP_KERNEL);
264		− if (!slot)
	264	+ if (!slot) {
	265	+ retval = -ENOMEM;
265	266	goto error;
	267	+ }
266	268
267	269	hotplug_slot = kzalloc(sizeof(*hotplug_slot), GFP_KERNEL);
268		− if (!hotplug_slot)
	270	+ if (!hotplug_slot) {
	271	+ retval = -ENOMEM;
269	272	goto error_slot;
	273	+ }
270	274	slot->hotplug_slot = hotplug_slot;
271	275
272	276	info = kzalloc(sizeof(*info), GFP_KERNEL);
273		− if (!info)
	277	+ if (!info) {
	278	+ retval = -ENOMEM;
274	279	goto error_hpslot;
	280	+ }
275	281	hotplug_slot->info = info;
276	282
277	283	slot->number = i;

drivers/pci/hotplug/sgi_hotplug.c+5−7

@@ -397,13 +397,11 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot) · 396 unmodified lines
397	397	else
398	398	sn_io_slot_fixup(dev);
399	399	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
400		− unsigned char sec_bus;
401		− pci_read_config_byte(dev, PCI_SECONDARY_BUS,
402		− &sec_bus);
403		− new_bus = pci_add_new_bus(dev->bus, dev,
404		− sec_bus);
405		− pci_scan_child_bus(new_bus);
406		− new_ppb = 1;
	400	+ pci_hp_add_bridge(dev);
	401	+ if (dev->subordinate) {
	402	+ new_bus = dev->subordinate;
	403	+ new_ppb = 1;
	404	+ }
407	405	}
408	406	pci_dev_put(dev);
409	407	}

drivers/pci/hotplug/shpchp_core.c+10−4

@@ -99,22 +99,28 @@ static int init_slots(struct controller *ctrl) · 98 unmodified lines
99	99	struct hotplug_slot *hotplug_slot;
100	100	struct hotplug_slot_info *info;
101	101	char name[SLOT_NAME_SIZE];
102		− int retval = -ENOMEM;
	102	+ int retval;
103	103	int i;
104	104
105	105	for (i = 0; i < ctrl->num_slots; i++) {
106	106	slot = kzalloc(sizeof(*slot), GFP_KERNEL);
107		− if (!slot)
	107	+ if (!slot) {
	108	+ retval = -ENOMEM;
108	109	goto error;
	110	+ }
109	111
110	112	hotplug_slot = kzalloc(sizeof(*hotplug_slot), GFP_KERNEL);
111		− if (!hotplug_slot)
	113	+ if (!hotplug_slot) {
	114	+ retval = -ENOMEM;
112	115	goto error_slot;
	116	+ }
113	117	slot->hotplug_slot = hotplug_slot;
114	118
115	119	info = kzalloc(sizeof(*info), GFP_KERNEL);
116		− if (!info)
	120	+ if (!info) {
	121	+ retval = -ENOMEM;
117	122	goto error_hpslot;
	123	+ }
118	124	hotplug_slot->info = info;
119	125
120	126	slot->hp_slot = i;

drivers/pci/hotplug/shpchp_ctrl.c+0−3

@@ -262,9 +262,6 @@ static int board_added(struct slot *p_slot) · 261 unmodified lines
262	262	}
263	263
264	264	if ((ctrl->pci_dev->vendor == 0x8086) && (ctrl->pci_dev->device == 0x0332)) {
265		− if (slots_not_empty)
266		− return WRONG_BUS_FREQUENCY;
267		−
268	265	if ((rc = p_slot->hpc_ops->set_bus_speed_mode(p_slot, PCI_SPEED_33MHz))) {
269	266	ctrl_err(ctrl, "%s: Issue of set bus speed mode command"
270	267	" failed\n", __func__);

drivers/pci/hotplug/shpchp_pci.c+15−30

@@ -37,9 +37,10 @@ · 36 unmodified lines
37	37	int __ref shpchp_configure_device(struct slot *p_slot)
38	38	{
39	39	struct pci_dev *dev;
40		− struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
41		− int num, fn;
42	40	struct controller *ctrl = p_slot->ctrl;
	41	+ struct pci_dev *bridge = ctrl->pci_dev;
	42	+ struct pci_bus *parent = bridge->subordinate;
	43	+ int num, fn;
43	44
44	45	dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, 0));
45	46	if (dev) {
@@ -61,39 +62,23 @@ int __ref shpchp_configure_device(struct slot *p_slot) · 15 unmodified lines
61	62	if (!dev)
62	63	continue;
63	64	if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) \|\|
64		− (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) {
65		− /* Find an unused bus number for the new bridge */
66		− struct pci_bus *child;
67		− unsigned char busnr, start = parent->secondary;
68		− unsigned char end = parent->subordinate;
69		− for (busnr = start; busnr <= end; busnr++) {
70		− if (!pci_find_bus(pci_domain_nr(parent),
71		− busnr))
72		− break;
73		− }
74		− if (busnr > end) {
75		− ctrl_err(ctrl,
76		− "No free bus for hot-added bridge\n");
77		− pci_dev_put(dev);
78		− continue;
79		− }
80		− child = pci_add_new_bus(parent, dev, busnr);
81		− if (!child) {
82		− ctrl_err(ctrl, "Cannot add new bus for %s\n",
83		− pci_name(dev));
84		− pci_dev_put(dev);
85		− continue;
86		− }
87		− child->subordinate = pci_do_scan_bus(child);
88		− pci_bus_size_bridges(child);
89		− }
	65	+ (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
	66	+ pci_hp_add_bridge(dev);
	67	+ pci_dev_put(dev);
	68	+ }
	69	+
	70	+ pci_assign_unassigned_bridge_resources(bridge);
	71	+
	72	+ for (fn = 0; fn < 8; fn++) {
	73	+ dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, fn));
	74	+ if (!dev)
	75	+ continue;
90	76	pci_configure_slot(dev);
91	77	pci_dev_put(dev);
92	78	}
93	79
94		− pci_bus_assign_resources(parent);
95	80	pci_bus_add_devices(parent);
96		− pci_enable_bridges(parent);
	81	+
97	82	return 0;
98	83	}
99	84

drivers/pci/hotplug/shpchp_sysfs.c+3−3

@@ -73,13 +73,13 @@ static ssize_t show_ctrl (struct device dev, struct device_attribute attr, cha · 72 unmodified lines
73	73	}
74	74	}
75	75	out += sprintf(out, "Free resources: bus numbers\n");
76		− for (busnr = bus->secondary; busnr <= bus->subordinate; busnr++) {
	76	+ for (busnr = bus->busn_res.start; busnr <= bus->busn_res.end; busnr++) {
77	77	if (!pci_find_bus(pci_domain_nr(bus), busnr))
78	78	break;
79	79	}
80		− if (busnr < bus->subordinate)
	80	+ if (busnr < bus->busn_res.end)
81	81	out += sprintf(out, "start = %8.8x, length = %8.8x\n",
82		− busnr, (bus->subordinate - busnr));
	82	+ busnr, (int)(bus->busn_res.end - busnr));
83	83
84	84	return out - buf;
85	85	}

drivers/pci/iov.c+2−2

@@ -47,7 +47,7 @@ static struct pci_bus virtfn_add_bus(struct pci_bus bus, int busnr) · 46 unmodified lines
47	47	if (!child)
48	48	return NULL;
49	49
50		− child->subordinate = busnr;
	50	+ pci_bus_insert_busn_res(child, busnr, busnr);
51	51	child->dev.parent = bus->bridge;
52	52	rc = pci_bus_add_child(child);
53	53	if (rc) {
@@ -327,7 +327,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) · 273 unmodified lines
327	327	iov->offset = offset;
328	328	iov->stride = stride;
329	329
330		− if (virtfn_bus(dev, nr_virtfn - 1) > dev->bus->subordinate) {
	330	+ if (virtfn_bus(dev, nr_virtfn - 1) > dev->bus->busn_res.end) {
331	331	dev_err(&dev->dev, "SR-IOV: bus number out of range\n");
332	332	return -ENOMEM;
333	333	}

drivers/pci/pci-acpi.c+33−3

@@ -48,6 +48,12 @@ static void pci_acpi_wake_dev(acpi_handle handle, u32 event, void *context) · 47 unmodified lines
48	48	if (event != ACPI_NOTIFY_DEVICE_WAKE \|\| !pci_dev)
49	49	return;
50	50
	51	+ if (pci_dev->current_state == PCI_D3cold) {
	52	+ pci_wakeup_event(pci_dev);
	53	+ pm_runtime_resume(&pci_dev->dev);
	54	+ return;
	55	+ }
	56	+
51	57	if (!pci_dev->pm_cap \|\| !pci_dev->pme_support
52	58	\|\| pci_check_pme_status(pci_dev)) {
53	59	if (pci_dev->pme_poll)
@@ -162,6 +168,20 @@ acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev) · 108 unmodified lines
162	168	return remove_pm_notifier(dev, pci_acpi_wake_dev);
163	169	}
164	170
	171	+phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
	172	+{
	173	+ acpi_status status = AE_NOT_EXIST;
	174	+ unsigned long long mcfg_addr;
	175	+
	176	+ if (handle)
	177	+ status = acpi_evaluate_integer(handle, METHOD_NAME__CBA,
	178	+ NULL, &mcfg_addr);
	179	+ if (ACPI_FAILURE(status))
	180	+ return 0;
	181	+
	182	+ return (phys_addr_t)mcfg_addr;
	183	+}
	184	+
165	185	/*
166	186	* _SxD returns the D-state with the highest power
167	187	* (lowest D-state number) supported in the S-state "x".
@@ -187,9 +207,13 @@ acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev) · 19 unmodified lines
187	207
188	208	static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
189	209	{
190		− int acpi_state;
	210	+ int acpi_state, d_max;
191	211
192		− acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL);
	212	+ if (pdev->no_d3cold)
	213	+ d_max = ACPI_STATE_D3_HOT;
	214	+ else
	215	+ d_max = ACPI_STATE_D3_COLD;
	216	+ acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL, d_max);
193	217	if (acpi_state < 0)
194	218	return PCI_POWER_ERROR;
195	219
@@ -296,7 +320,13 @@ static void acpi_pci_propagate_run_wake(struct pci_bus *bus, bool enable) · 100 unmodified lines
296	320
297	321	static int acpi_pci_run_wake(struct pci_dev *dev, bool enable)
298	322	{
299		− if (dev->pme_interrupt)
	323	+ /*
	324	+ * Per PCI Express Base Specification Revision 2.0 section
	325	+ * 5.3.3.2 Link Wakeup, platform support is needed for D3cold
	326	+ * waking up to power on the main link even if there is PME
	327	+ * support for D3cold
	328	+ */
	329	+ if (dev->pme_interrupt && !dev->runtime_d3cold)
300	330	return 0;
301	331
302	332	if (!acpi_pm_device_run_wake(&dev->dev, enable))

drivers/pci/pci-driver.c+17−7

@@ -459,16 +459,17 @@ static int pci_restore_standard_config(struct pci_dev *pci_dev) · 458 unmodified lines
459	459	return 0;
460	460	}
461	461
	462	+#endif
	463	+
	464	+#ifdef CONFIG_PM_SLEEP
	465	+
462	466	static void pci_pm_default_resume_early(struct pci_dev *pci_dev)
463	467	{
464		− pci_restore_standard_config(pci_dev);
	468	+ pci_power_up(pci_dev);
	469	+ pci_restore_state(pci_dev);
465	470	pci_fixup_device(pci_fixup_resume_early, pci_dev);
466	471	}
467	472
468		−#endif
469		−
470		−#ifdef CONFIG_PM_SLEEP
471		−
472	473	/*
473	474	* Default "suspend" method for devices that have no driver provided suspend,
474	475	* or not even a driver at all (second part).
@@ -1031,10 +1032,13 @@ static int pci_pm_runtime_suspend(struct device *dev) · 556 unmodified lines
1031	1032	if (!pm \|\| !pm->runtime_suspend)
1032	1033	return -ENOSYS;
1033	1034
	1035	+ pci_dev->no_d3cold = false;
1034	1036	error = pm->runtime_suspend(dev);
1035	1037	suspend_report_result(pm->runtime_suspend, error);
1036	1038	if (error)
1037	1039	return error;
	1040	+ if (!pci_dev->d3cold_allowed)
	1041	+ pci_dev->no_d3cold = true;
1038	1042
1039	1043	pci_fixup_device(pci_fixup_suspend, pci_dev);
1040	1044
@@ -1056,17 +1060,23 @@ static int pci_pm_runtime_suspend(struct device *dev) · 15 unmodified lines
1056	1060
1057	1061	static int pci_pm_runtime_resume(struct device *dev)
1058	1062	{
	1063	+ int rc;
1059	1064	struct pci_dev *pci_dev = to_pci_dev(dev);
1060	1065	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
1061	1066
1062	1067	if (!pm \|\| !pm->runtime_resume)
1063	1068	return -ENOSYS;
1064	1069
1065		− pci_pm_default_resume_early(pci_dev);
	1070	+ pci_restore_standard_config(pci_dev);
	1071	+ pci_fixup_device(pci_fixup_resume_early, pci_dev);
1066	1072	__pci_enable_wake(pci_dev, PCI_D0, true, false);
1067	1073	pci_fixup_device(pci_fixup_resume, pci_dev);
1068	1074
1069		− return pm->runtime_resume(dev);
	1075	+ rc = pm->runtime_resume(dev);
	1076	+
	1077	+ pci_dev->runtime_d3cold = false;
	1078	+
	1079	+ return rc;
1070	1080	}
1071	1081
1072	1082	static int pci_pm_runtime_idle(struct device *dev)

drivers/pci/pci-sysfs.c+30−1

@@ -28,6 +28,7 @@ · 27 unmodified lines
28	28	#include <linux/pci-aspm.h>
29	29	#include <linux/slab.h>
30	30	#include <linux/vgaarb.h>
	31	+#include <linux/pm_runtime.h>
31	32	#include "pci.h"
32	33
33	34	static int sysfs_initialized; /* = 0 */
@@ -378,6 +379,31 @@ dev_bus_rescan_store(struct device dev, struct device_attribute attr, · 344 unmodified lines
378	379
379	380	#endif
380	381
	382	+#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
	383	+static ssize_t d3cold_allowed_store(struct device *dev,
	384	+ struct device_attribute *attr,
	385	+ const char *buf, size_t count)
	386	+{
	387	+ struct pci_dev *pdev = to_pci_dev(dev);
	388	+ unsigned long val;
	389	+
	390	+ if (strict_strtoul(buf, 0, &val) < 0)
	391	+ return -EINVAL;
	392	+
	393	+ pdev->d3cold_allowed = !!val;
	394	+ pm_runtime_resume(dev);
	395	+
	396	+ return count;
	397	+}
	398	+
	399	+static ssize_t d3cold_allowed_show(struct device *dev,
	400	+ struct device_attribute attr, char buf)
	401	+{
	402	+ struct pci_dev *pdev = to_pci_dev(dev);
	403	+ return sprintf (buf, "%u\n", pdev->d3cold_allowed);
	404	+}
	405	+#endif
	406	+
381	407	struct device_attribute pci_dev_attrs[] = {
382	408	__ATTR_RO(resource),
383	409	__ATTR_RO(vendor),
@@ -401,6 +427,9 @@ struct device_attribute pci_dev_attrs[] = { · 17 unmodified lines
401	427	#ifdef CONFIG_HOTPLUG
402	428	__ATTR(remove, (S_IWUSR\|S_IWGRP), NULL, remove_store),
403	429	__ATTR(rescan, (S_IWUSR\|S_IWGRP), NULL, dev_rescan_store),
	430	+#endif
	431	+#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
	432	+ __ATTR(d3cold_allowed, 0644, d3cold_allowed_show, d3cold_allowed_store),
404	433	#endif
405	434	__ATTR_NULL,
406	435	};
@@ -1112,7 +1141,7 @@ static struct bin_attribute pcie_config_attr = { · 705 unmodified lines
1112	1141	.write = pci_write_config,
1113	1142	};
1114	1143
1115		−int __attribute__ ((weak)) pcibios_add_platform_entries(struct pci_dev *dev)
	1144	+int __weak pcibios_add_platform_entries(struct pci_dev *dev)
1116	1145	{
1117	1146	return 0;
1118	1147	}

drivers/pci/pci.c+291−133

@@ -110,7 +110,7 @@ unsigned char pci_bus_max_busnr(struct pci_bus* bus) · 109 unmodified lines
110	110	struct list_head *tmp;
111	111	unsigned char max, n;
112	112
113		− max = bus->subordinate;
	113	+ max = bus->busn_res.end;
114	114	list_for_each(tmp, &bus->children) {
115	115	n = pci_bus_max_busnr(pci_bus_b(tmp));
116	116	if(n > max)
@@ -136,30 +136,6 @@ void __iomem pci_ioremap_bar(struct pci_dev pdev, int bar) · 19 unmodified lines
136	136	EXPORT_SYMBOL_GPL(pci_ioremap_bar);
137	137	#endif
138	138
139		−#if 0
140		−/**
141		− * pci_max_busnr - returns maximum PCI bus number
142		− *
143		− * Returns the highest PCI bus number present in the system global list of
144		− * PCI buses.
145		− */
146		−unsigned char __devinit
147		−pci_max_busnr(void)
148		−{
149		− struct pci_bus *bus = NULL;
150		− unsigned char max, n;
151		−
152		− max = 0;
153		− while ((bus = pci_find_next_bus(bus)) != NULL) {
154		− n = pci_bus_max_busnr(bus);
155		− if(n > max)
156		− max = n;
157		− }
158		− return max;
159		−}
160		−
161		−#endif /* 0 */
162		−
163	139	#define PCI_FIND_CAP_TTL 48
164	140
165	141	static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
@@ -277,6 +253,38 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) · 111 unmodified lines
277	253	return pos;
278	254	}
279	255
	256	+/**
	257	+ * pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure
	258	+ * @dev: PCI device to check
	259	+ *
	260	+ * Like pci_pcie_cap() but also checks that the PCIe capability version is
	261	+ * >= 2. Note that v1 capability structures could be sparse in that not
	262	+ * all register fields were required. v2 requires the entire structure to
	263	+ * be present size wise, while still allowing for non-implemented registers
	264	+ * to exist but they must be hardwired to 0.
	265	+ *
	266	+ * Due to the differences in the versions of capability structures, one
	267	+ * must be careful not to try and access non-existant registers that may
	268	+ * exist in early versions - v1 - of Express devices.
	269	+ *
	270	+ * Returns the offset of the PCIe capability structure as long as the
	271	+ * capability version is >= 2; otherwise 0 is returned.
	272	+ */
	273	+static int pci_pcie_cap2(struct pci_dev *dev)
	274	+{
	275	+ u16 flags;
	276	+ int pos;
	277	+
	278	+ pos = pci_pcie_cap(dev);
	279	+ if (pos) {
	280	+ pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
	281	+ if ((flags & PCI_EXP_FLAGS_VERS) < 2)
	282	+ pos = 0;
	283	+ }
	284	+
	285	+ return pos;
	286	+}
	287	+
280	288	/**
281	289	* pci_find_ext_capability - Find an extended capability
282	290	* @dev: PCI device to query
@@ -329,49 +337,6 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap) · 46 unmodified lines
329	337	}
330	338	EXPORT_SYMBOL_GPL(pci_find_ext_capability);
331	339
332		−/**
333		− * pci_bus_find_ext_capability - find an extended capability
334		− * @bus: the PCI bus to query
335		− * @devfn: PCI device to query
336		− * @cap: capability code
337		− *
338		− * Like pci_find_ext_capability() but works for pci devices that do not have a
339		− * pci_dev structure set up yet.
340		− *
341		− * Returns the address of the requested capability structure within the
342		− * device's PCI configuration space or 0 in case the device does not
343		− * support it.
344		− */
345		−int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
346		− int cap)
347		−{
348		− u32 header;
349		− int ttl;
350		− int pos = PCI_CFG_SPACE_SIZE;
351		−
352		− /* minimum 8 bytes per capability */
353		− ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
354		−
355		− if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
356		− return 0;
357		− if (header == 0xffffffff \|\| header == 0)
358		− return 0;
359		−
360		− while (ttl-- > 0) {
361		− if (PCI_EXT_CAP_ID(header) == cap)
362		− return pos;
363		−
364		− pos = PCI_EXT_CAP_NEXT(header);
365		− if (pos < PCI_CFG_SPACE_SIZE)
366		− break;
367		−
368		− if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
369		− break;
370		− }
371		−
372		− return 0;
373		−}
374		−
375	340	static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
376	341	{
377	342	int rc, ttl = PCI_FIND_CAP_TTL;
@@ -622,7 +587,8 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) · 244 unmodified lines
622	587	dev_info(&dev->dev, "Refused to change power state, "
623	588	"currently in D%d\n", dev->current_state);
624	589
625		− /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
	590	+ /*
	591	+ * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
626	592	* INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
627	593	* from D3hot to D0 _may_ perform an internal reset, thereby
628	594	* going to "D0 Uninitialized" rather than "D0 Initialized".
@@ -654,6 +620,16 @@ void pci_update_current_state(struct pci_dev *dev, pci_power_t state) · 25 unmodified lines
654	620	if (dev->pm_cap) {
655	621	u16 pmcsr;
656	622
	623	+ /*
	624	+ * Configuration space is not accessible for device in
	625	+ * D3cold, so just keep or set D3cold for safety
	626	+ */
	627	+ if (dev->current_state == PCI_D3cold)
	628	+ return;
	629	+ if (state == PCI_D3cold) {
	630	+ dev->current_state = PCI_D3cold;
	631	+ return;
	632	+ }
657	633	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
658	634	dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
659	635	} else {
@@ -661,6 +637,19 @@ void pci_update_current_state(struct pci_dev *dev, pci_power_t state) · 1 unmodified line
661	637	}
662	638	}
663	639
	640	+/**
	641	+ * pci_power_up - Put the given device into D0 forcibly
	642	+ * @dev: PCI device to power up
	643	+ */
	644	+void pci_power_up(struct pci_dev *dev)
	645	+{
	646	+ if (platform_pci_power_manageable(dev))
	647	+ platform_pci_set_power_state(dev, PCI_D0);
	648	+
	649	+ pci_raw_set_power_state(dev, PCI_D0);
	650	+ pci_update_current_state(dev, PCI_D0);
	651	+}
	652	+
664	653	/**
665	654	* pci_platform_power_transition - Use platform to change device power state
666	655	* @dev: PCI device to handle.
@@ -694,8 +683,50 @@ static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) · 27 unmodified lines
694	683	*/
695	684	static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
696	685	{
697		− if (state == PCI_D0)
	686	+ if (state == PCI_D0) {
698	687	pci_platform_power_transition(dev, PCI_D0);
	688	+ /*
	689	+ * Mandatory power management transition delays, see
	690	+ * PCI Express Base Specification Revision 2.0 Section
	691	+ * 6.6.1: Conventional Reset. Do not delay for
	692	+ * devices powered on/off by corresponding bridge,
	693	+ * because have already delayed for the bridge.
	694	+ */
	695	+ if (dev->runtime_d3cold) {
	696	+ msleep(dev->d3cold_delay);
	697	+ /*
	698	+ * When powering on a bridge from D3cold, the
	699	+ * whole hierarchy may be powered on into
	700	+ * D0uninitialized state, resume them to give
	701	+ * them a chance to suspend again
	702	+ */
	703	+ pci_wakeup_bus(dev->subordinate);
	704	+ }
	705	+ }
	706	+}
	707	+
	708	+/**
	709	+ * __pci_dev_set_current_state - Set current state of a PCI device
	710	+ * @dev: Device to handle
	711	+ * @data: pointer to state to be set
	712	+ */
	713	+static int __pci_dev_set_current_state(struct pci_dev dev, void data)
	714	+{
	715	+ pci_power_t state = (pci_power_t )data;
	716	+
	717	+ dev->current_state = state;
	718	+ return 0;
	719	+}
	720	+
	721	+/**
	722	+ * __pci_bus_set_current_state - Walk given bus and set current state of devices
	723	+ * @bus: Top bus of the subtree to walk.
	724	+ * @state: state to be set
	725	+ */
	726	+static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
	727	+{
	728	+ if (bus)
	729	+ pci_walk_bus(bus, __pci_dev_set_current_state, &state);
699	730	}
700	731
701	732	/**
@@ -707,8 +738,15 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) · 5 unmodified lines
707	738	*/
708	739	int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
709	740	{
710		− return state >= PCI_D0 ?
711		− pci_platform_power_transition(dev, state) : -EINVAL;
	741	+ int ret;
	742	+
	743	+ if (state <= PCI_D0)
	744	+ return -EINVAL;
	745	+ ret = pci_platform_power_transition(dev, state);
	746	+ /* Power off the bridge may power off the whole hierarchy */
	747	+ if (!ret && state == PCI_D3cold)
	748	+ __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
	749	+ return ret;
712	750	}
713	751	EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
714	752
@@ -732,8 +770,8 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state) · 17 unmodified lines
732	770	int error;
733	771
734	772	/* bound the state we're entering */
735		− if (state > PCI_D3hot)
736		− state = PCI_D3hot;
	773	+ if (state > PCI_D3cold)
	774	+ state = PCI_D3cold;
737	775	else if (state < PCI_D0)
738	776	state = PCI_D0;
739	777	else if ((state == PCI_D1 \|\| state == PCI_D2) && pci_no_d1d2(dev))
@@ -744,14 +782,23 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state) · 4 unmodified lines
744	782	*/
745	783	return 0;
746	784
	785	+ /* Check if we're already there */
	786	+ if (dev->current_state == state)
	787	+ return 0;
	788	+
747	789	__pci_start_power_transition(dev, state);
748	790
749	791	/* This device is quirked not to be put into D3, so
750	792	don't put it in D3 */
751		− if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
	793	+ if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
752	794	return 0;
753	795
754		− error = pci_raw_set_power_state(dev, state);
	796	+ /*
	797	+ * To put device in D3cold, we put device into D3hot in native
	798	+ * way, then put device into D3cold with platform ops
	799	+ */
	800	+ error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
	801	+ PCI_D3hot : state);
755	802
756	803	if (!__pci_complete_power_transition(dev, state))
757	804	error = 0;
@@ -822,12 +869,6 @@ EXPORT_SYMBOL(pci_choose_state); · 64 unmodified lines
822	869	((flags & PCI_EXP_FLAGS_VERS) > 1 \|\| \
823	870	(type == PCI_EXP_TYPE_ROOT_PORT \|\| \
824	871	type == PCI_EXP_TYPE_RC_EC))
825		−#define pcie_cap_has_devctl2(type, flags) \
826		− ((flags & PCI_EXP_FLAGS_VERS) > 1)
827		−#define pcie_cap_has_lnkctl2(type, flags) \
828		− ((flags & PCI_EXP_FLAGS_VERS) > 1)
829		−#define pcie_cap_has_sltctl2(type, flags) \
830		− ((flags & PCI_EXP_FLAGS_VERS) > 1)
831	872
832	873	static struct pci_cap_saved_state *pci_find_saved_cap(
833	874	struct pci_dev *pci_dev, char cap)
@@ -870,13 +911,14 @@ static int pci_save_pcie_state(struct pci_dev *dev) · 36 unmodified lines
870	911	pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
871	912	if (pcie_cap_has_rtctl(dev->pcie_type, flags))
872	913	pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
873		− if (pcie_cap_has_devctl2(dev->pcie_type, flags))
874		− pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
875		− if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
876		− pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
877		− if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
878		− pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
879	914
	915	+ pos = pci_pcie_cap2(dev);
	916	+ if (!pos)
	917	+ return 0;
	918	+
	919	+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
	920	+ pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
	921	+ pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
880	922	return 0;
881	923	}
882	924
@@ -903,12 +945,14 @@ static void pci_restore_pcie_state(struct pci_dev *dev) · 20 unmodified lines
903	945	pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
904	946	if (pcie_cap_has_rtctl(dev->pcie_type, flags))
905	947	pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
906		− if (pcie_cap_has_devctl2(dev->pcie_type, flags))
907		− pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
908		− if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
909		− pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
910		− if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
911		− pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
	948	+
	949	+ pos = pci_pcie_cap2(dev);
	950	+ if (!pos)
	951	+ return;
	952	+
	953	+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
	954	+ pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
	955	+ pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
912	956	}
913	957
914	958
@@ -1349,7 +1393,7 @@ void pcim_pin_device(struct pci_dev *pdev) · 434 unmodified lines
1349	1393	* is the default implementation. Architecture implementations can
1350	1394	* override this.
1351	1395	*/
1352		−void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
	1396	+void __weak pcibios_disable_device (struct pci_dev *dev) {}
1353	1397
1354	1398	static void do_pci_disable_device(struct pci_dev *dev)
1355	1399	{
@@ -1413,8 +1457,8 @@ pci_disable_device(struct pci_dev *dev) · 57 unmodified lines
1413	1457	* Sets the PCIe reset state for the device. This is the default
1414	1458	* implementation. Architecture implementations can override this.
1415	1459	*/
1416		−int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1417		− enum pcie_reset_state state)
	1460	+int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
	1461	+ enum pcie_reset_state state)
1418	1462	{
1419	1463	return -EINVAL;
1420	1464	}
@@ -1497,6 +1541,28 @@ void pci_pme_wakeup_bus(struct pci_bus *bus) · 76 unmodified lines
1497	1541	pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1498	1542	}
1499	1543
	1544	+/**
	1545	+ * pci_wakeup - Wake up a PCI device
	1546	+ * @dev: Device to handle.
	1547	+ * @ign: ignored parameter
	1548	+ */
	1549	+static int pci_wakeup(struct pci_dev pci_dev, void ign)
	1550	+{
	1551	+ pci_wakeup_event(pci_dev);
	1552	+ pm_request_resume(&pci_dev->dev);
	1553	+ return 0;
	1554	+}
	1555	+
	1556	+/**
	1557	+ * pci_wakeup_bus - Walk given bus and wake up devices on it
	1558	+ * @bus: Top bus of the subtree to walk.
	1559	+ */
	1560	+void pci_wakeup_bus(struct pci_bus *bus)
	1561	+{
	1562	+ if (bus)
	1563	+ pci_walk_bus(bus, pci_wakeup, NULL);
	1564	+}
	1565	+
1500	1566	/**
1501	1567	* pci_pme_capable - check the capability of PCI device to generate PME#
1502	1568	* @dev: PCI device to handle.
@@ -1518,6 +1584,16 @@ static void pci_pme_list_scan(struct work_struct *work) · 15 unmodified lines
1518	1584	if (!list_empty(&pci_pme_list)) {
1519	1585	list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1520	1586	if (pme_dev->dev->pme_poll) {
	1587	+ struct pci_dev *bridge;
	1588	+
	1589	+ bridge = pme_dev->dev->bus->self;
	1590	+ /*
	1591	+ * If bridge is in low power state, the
	1592	+ * configuration space of subordinate devices
	1593	+ * may be not accessible
	1594	+ */
	1595	+ if (bridge && bridge->current_state != PCI_D0)
	1596	+ continue;
1521	1597	pci_pme_wakeup(pme_dev->dev, NULL);
1522	1598	} else {
1523	1599	list_del(&pme_dev->list);
@@ -1744,6 +1820,10 @@ int pci_prepare_to_sleep(struct pci_dev *dev) · 220 unmodified lines
1744	1820	if (target_state == PCI_POWER_ERROR)
1745	1821	return -EIO;
1746	1822
	1823	+ /* D3cold during system suspend/hibernate is not supported */
	1824	+ if (target_state > PCI_D3hot)
	1825	+ target_state = PCI_D3hot;
	1826	+
1747	1827	pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1748	1828
1749	1829	error = pci_set_power_state(dev, target_state);
@@ -1781,12 +1861,16 @@ int pci_finish_runtime_suspend(struct pci_dev *dev) · 31 unmodified lines
1781	1861	if (target_state == PCI_POWER_ERROR)
1782	1862	return -EIO;
1783	1863
	1864	+ dev->runtime_d3cold = target_state == PCI_D3cold;
	1865	+
1784	1866	__pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1785	1867
1786	1868	error = pci_set_power_state(dev, target_state);
1787	1869
1788		− if (error)
	1870	+ if (error) {
1789	1871	__pci_enable_wake(dev, target_state, true, false);
	1872	+ dev->runtime_d3cold = false;
	1873	+ }
1790	1874
1791	1875	return error;
1792	1876	}
@@ -1856,6 +1940,7 @@ void pci_pm_init(struct pci_dev *dev) · 63 unmodified lines
1856	1940
1857	1941	dev->pm_cap = pm;
1858	1942	dev->d3_delay = PCI_PM_D3_WAIT;
	1943	+ dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1859	1944
1860	1945	dev->d1_support = false;
1861	1946	dev->d2_support = false;
@@ -1983,7 +2068,7 @@ void pci_enable_ari(struct pci_dev *dev) · 121 unmodified lines
1983	2068	{
1984	2069	int pos;
1985	2070	u32 cap;
1986		− u16 flags, ctrl;
	2071	+ u16 ctrl;
1987	2072	struct pci_dev *bridge;
1988	2073
1989	2074	if (pcie_ari_disabled \|\| !pci_is_pcie(dev) \|\| dev->devfn)
@@ -1994,18 +2079,14 @@ void pci_enable_ari(struct pci_dev *dev) · 4 unmodified lines
1994	2079	return;
1995	2080
1996	2081	bridge = dev->bus->self;
1997		− if (!bridge \|\| !pci_is_pcie(bridge))
	2082	+ if (!bridge)
1998	2083	return;
1999	2084
2000		− pos = pci_pcie_cap(bridge);
	2085	+ /* ARI is a PCIe cap v2 feature */
	2086	+ pos = pci_pcie_cap2(bridge);
2001	2087	if (!pos)
2002	2088	return;
2003	2089
2004		− /* ARI is a PCIe v2 feature */
2005		− pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
2006		− if ((flags & PCI_EXP_FLAGS_VERS) < 2)
2007		− return;
2008		−
2009	2090	pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
2010	2091	if (!(cap & PCI_EXP_DEVCAP2_ARI))
2011	2092	return;
@@ -2018,7 +2099,7 @@ void pci_enable_ari(struct pci_dev *dev) · 6 unmodified lines
2018	2099	}
2019	2100
2020	2101	/**
2021		− * pci_enable_ido - enable ID-based ordering on a device
	2102	+ * pci_enable_ido - enable ID-based Ordering on a device
2022	2103	* @dev: the PCI device
2023	2104	* @type: which types of IDO to enable
2024	2105	*
@@ -2031,7 +2112,8 @@ void pci_enable_ido(struct pci_dev *dev, unsigned long type) · 6 unmodified lines
2031	2112	int pos;
2032	2113	u16 ctrl;
2033	2114
2034		− pos = pci_pcie_cap(dev);
	2115	+ /* ID-based Ordering is a PCIe cap v2 feature */
	2116	+ pos = pci_pcie_cap2(dev);
2035	2117	if (!pos)
2036	2118	return;
2037	2119
@@ -2054,10 +2136,8 @@ void pci_disable_ido(struct pci_dev *dev, unsigned long type) · 16 unmodified lines
2054	2136	int pos;
2055	2137	u16 ctrl;
2056	2138
2057		− if (!pci_is_pcie(dev))
2058		− return;
2059		−
2060		− pos = pci_pcie_cap(dev);
	2139	+ /* ID-based Ordering is a PCIe cap v2 feature */
	2140	+ pos = pci_pcie_cap2(dev);
2061	2141	if (!pos)
2062	2142	return;
2063	2143
@@ -2096,10 +2176,8 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) · 32 unmodified lines
2096	2176	u16 ctrl;
2097	2177	int ret;
2098	2178
2099		− if (!pci_is_pcie(dev))
2100		− return -ENOTSUPP;
2101		−
2102		− pos = pci_pcie_cap(dev);
	2179	+ /* OBFF is a PCIe cap v2 feature */
	2180	+ pos = pci_pcie_cap2(dev);
2103	2181	if (!pos)
2104	2182	return -ENOTSUPP;
2105	2183
@@ -2108,7 +2186,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) · 2 unmodified lines
2108	2186	return -ENOTSUPP; /* no OBFF support at all */
2109	2187
2110	2188	/* Make sure the topology supports OBFF as well */
2111		− if (dev->bus) {
	2189	+ if (dev->bus->self) {
2112	2190	ret = pci_enable_obff(dev->bus->self, type);
2113	2191	if (ret)
2114	2192	return ret;
@@ -2149,10 +2227,8 @@ void pci_disable_obff(struct pci_dev *dev) · 34 unmodified lines
2149	2227	int pos;
2150	2228	u16 ctrl;
2151	2229
2152		− if (!pci_is_pcie(dev))
2153		− return;
2154		−
2155		− pos = pci_pcie_cap(dev);
	2230	+ /* OBFF is a PCIe cap v2 feature */
	2231	+ pos = pci_pcie_cap2(dev);
2156	2232	if (!pos)
2157	2233	return;
2158	2234
@@ -2169,15 +2245,13 @@ EXPORT_SYMBOL(pci_disable_obff); · 10 unmodified lines
2169	2245	* RETURNS:
2170	2246	* True if @dev supports latency tolerance reporting, false otherwise.
2171	2247	*/
2172		−bool pci_ltr_supported(struct pci_dev *dev)
	2248	+static bool pci_ltr_supported(struct pci_dev *dev)
2173	2249	{
2174	2250	int pos;
2175	2251	u32 cap;
2176	2252
2177		− if (!pci_is_pcie(dev))
2178		− return false;
2179		−
2180		− pos = pci_pcie_cap(dev);
	2253	+ /* LTR is a PCIe cap v2 feature */
	2254	+ pos = pci_pcie_cap2(dev);
2181	2255	if (!pos)
2182	2256	return false;
2183	2257
@@ -2185,7 +2259,6 @@ bool pci_ltr_supported(struct pci_dev *dev) · 1 unmodified line
2185	2259
2186	2260	return cap & PCI_EXP_DEVCAP2_LTR;
2187	2261	}
2188		−EXPORT_SYMBOL(pci_ltr_supported);
2189	2262
2190	2263	/**
2191	2264	* pci_enable_ltr - enable latency tolerance reporting
@@ -2206,7 +2279,8 @@ int pci_enable_ltr(struct pci_dev *dev) · 14 unmodified lines
2206	2279	if (!pci_ltr_supported(dev))
2207	2280	return -ENOTSUPP;
2208	2281
2209		− pos = pci_pcie_cap(dev);
	2282	+ /* LTR is a PCIe cap v2 feature */
	2283	+ pos = pci_pcie_cap2(dev);
2210	2284	if (!pos)
2211	2285	return -ENOTSUPP;
2212	2286
@@ -2215,7 +2289,7 @@ int pci_enable_ltr(struct pci_dev *dev) · 2 unmodified lines
2215	2289	return -EINVAL;
2216	2290
2217	2291	/* Enable upstream ports first */
2218		− if (dev->bus) {
	2292	+ if (dev->bus->self) {
2219	2293	ret = pci_enable_ltr(dev->bus->self);
2220	2294	if (ret)
2221	2295	return ret;
@@ -2241,7 +2315,8 @@ void pci_disable_ltr(struct pci_dev *dev) · 19 unmodified lines
2241	2315	if (!pci_ltr_supported(dev))
2242	2316	return;
2243	2317
2244		− pos = pci_pcie_cap(dev);
	2318	+ /* LTR is a PCIe cap v2 feature */
	2319	+ pos = pci_pcie_cap2(dev);
2245	2320	if (!pos)
2246	2321	return;
2247	2322
@@ -2359,6 +2434,75 @@ void pci_enable_acs(struct pci_dev *dev) · 111 unmodified lines
2359	2434	pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2360	2435	}
2361	2436
	2437	+/**
	2438	+ * pci_acs_enabled - test ACS against required flags for a given device
	2439	+ * @pdev: device to test
	2440	+ * @acs_flags: required PCI ACS flags
	2441	+ *
	2442	+ * Return true if the device supports the provided flags. Automatically
	2443	+ * filters out flags that are not implemented on multifunction devices.
	2444	+ */
	2445	+bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
	2446	+{
	2447	+ int pos, ret;
	2448	+ u16 ctrl;
	2449	+
	2450	+ ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
	2451	+ if (ret >= 0)
	2452	+ return ret > 0;
	2453	+
	2454	+ if (!pci_is_pcie(pdev))
	2455	+ return false;
	2456	+
	2457	+ /* Filter out flags not applicable to multifunction */
	2458	+ if (pdev->multifunction)
	2459	+ acs_flags &= (PCI_ACS_RR \| PCI_ACS_CR \|
	2460	+ PCI_ACS_EC \| PCI_ACS_DT);
	2461	+
	2462	+ if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM \|\|
	2463	+ pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT \|\|
	2464	+ pdev->multifunction) {
	2465	+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
	2466	+ if (!pos)
	2467	+ return false;
	2468	+
	2469	+ pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
	2470	+ if ((ctrl & acs_flags) != acs_flags)
	2471	+ return false;
	2472	+ }
	2473	+
	2474	+ return true;
	2475	+}
	2476	+
	2477	+/**
	2478	+ * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
	2479	+ * @start: starting downstream device
	2480	+ * @end: ending upstream device or NULL to search to the root bus
	2481	+ * @acs_flags: required flags
	2482	+ *
	2483	+ * Walk up a device tree from start to end testing PCI ACS support. If
	2484	+ * any step along the way does not support the required flags, return false.
	2485	+ */
	2486	+bool pci_acs_path_enabled(struct pci_dev *start,
	2487	+ struct pci_dev *end, u16 acs_flags)
	2488	+{
	2489	+ struct pci_dev pdev, parent = start;
	2490	+
	2491	+ do {
	2492	+ pdev = parent;
	2493	+
	2494	+ if (!pci_acs_enabled(pdev, acs_flags))
	2495	+ return false;
	2496	+
	2497	+ if (pci_is_root_bus(pdev->bus))
	2498	+ return (end == NULL);
	2499	+
	2500	+ parent = pdev->bus->self;
	2501	+ } while (pdev != end);
	2502	+
	2503	+ return true;
	2504	+}
	2505	+
2362	2506	/**
2363	2507	* pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2364	2508	* @dev: the PCI device
@@ -2665,6 +2809,18 @@ static void __pci_set_master(struct pci_dev *dev, bool enable) · 300 unmodified lines
2665	2809	dev->is_busmaster = enable;
2666	2810	}
2667	2811
	2812	+/**
	2813	+ * pcibios_setup - process "pci=" kernel boot arguments
	2814	+ * @str: string used to pass in "pci=" kernel boot arguments
	2815	+ *
	2816	+ * Process kernel boot arguments. This is the default implementation.
	2817	+ * Architecture specific implementations can override this as necessary.
	2818	+ */
	2819	+char * __weak __init pcibios_setup(char *str)
	2820	+{
	2821	+ return str;
	2822	+}
	2823	+
2668	2824	/**
2669	2825	* pcibios_set_master - enable PCI bus-mastering for device dev
2670	2826	* @dev: the PCI device to enable
@@ -2876,6 +3032,9 @@ bool pci_intx_mask_supported(struct pci_dev *dev) · 205 unmodified lines
2876	3032	bool mask_supported = false;
2877	3033	u16 orig, new;
2878	3034
	3035	+ if (dev->broken_intx_masking)
	3036	+ return false;
	3037	+
2879	3038	pci_cfg_access_lock(dev);
2880	3039
2881	3040	pci_read_config_word(dev, PCI_COMMAND, &orig);
@@ -3395,8 +3554,7 @@ int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) · 513 unmodified lines
3395	3554
3396	3555	o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3397	3556	if (o != v) {
3398		− if (v > o && dev->bus &&
3399		− (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
	3557	+ if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3400	3558	return -EIO;
3401	3559
3402	3560	cmd &= ~PCI_X_CMD_MAX_READ;
@@ -3851,7 +4009,7 @@ static void __devinit pci_no_domains(void) · 448 unmodified lines
3851	4009	* greater than 0xff). This is the default implementation. Architecture
3852	4010	* implementations can override this.
3853	4011	*/
3854		−int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
	4012	+int __weak pci_ext_cfg_avail(struct pci_dev *dev)
3855	4013	{
3856	4014	return 1;
3857	4015	}

drivers/pci/pci.h+3−8

@@ -67,9 +67,11 @@ struct pci_platform_pm_ops { · 66 unmodified lines
67	67
68	68	extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
69	69	extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
	70	+extern void pci_power_up(struct pci_dev *dev);
70	71	extern void pci_disable_enabled_device(struct pci_dev *dev);
71	72	extern int pci_finish_runtime_suspend(struct pci_dev *dev);
72	73	extern int __pci_pme_wakeup(struct pci_dev dev, void ign);
	74	+extern void pci_wakeup_bus(struct pci_bus *bus);
73	75	extern void pci_pm_init(struct pci_dev *dev);
74	76	extern void platform_pci_wakeup_init(struct pci_dev *dev);
75	77	extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
@@ -86,13 +88,6 @@ static inline bool pci_is_bridge(struct pci_dev *pci_dev) · 10 unmodified lines
86	88	return !!(pci_dev->subordinate);
87	89	}
88	90
89		−extern int pci_user_read_config_byte(struct pci_dev dev, int where, u8 val);
90		−extern int pci_user_read_config_word(struct pci_dev dev, int where, u16 val);
91		−extern int pci_user_read_config_dword(struct pci_dev dev, int where, u32 val);
92		−extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
93		−extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
94		−extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
95		−
96	91	struct pci_vpd_ops {
97	92	ssize_t (read)(struct pci_dev dev, loff_t pos, size_t count, void *buf);
98	93	ssize_t (write)(struct pci_dev dev, loff_t pos, size_t count, const void *buf);
@@ -124,7 +119,7 @@ static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } · 25 unmodified lines
124	119	#endif
125	120
126	121	/* Functions for PCI Hotplug drivers to use */
127		−extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
	122	+int pci_hp_add_bridge(struct pci_dev *dev);
128	123
129	124	#ifdef HAVE_PCI_LEGACY
130	125	extern void pci_create_legacy_files(struct pci_bus *bus);

drivers/pci/pcie/aer/aerdrv_acpi.c+1−1

@@ -59,7 +59,7 @@ static int aer_hest_parse(struct acpi_hest_header hest_hdr, void data) · 58 unmodified lines
59	59
60	60	p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
61	61	if (p->flags & ACPI_HEST_GLOBAL) {
62		− if ((info->pci_dev->is_pcie &&
	62	+ if ((pci_is_pcie(info->pci_dev) &&
63	63	info->pci_dev->pcie_type == pcie_type) \|\| bridge)
64	64	ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
65	65	} else

drivers/pci/pcie/portdrv_pci.c+60−0

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	11	#include <linux/kernel.h>
12	12	#include <linux/errno.h>
13	13	#include <linux/pm.h>
	14	+#include <linux/pm_runtime.h>
14	15	#include <linux/init.h>
15	16	#include <linux/pcieport_if.h>
16	17	#include <linux/aer.h>
@@ -99,6 +100,51 @@ static int pcie_port_resume_noirq(struct device *dev) · 82 unmodified lines
99	100	return 0;
100	101	}
101	102
	103	+#ifdef CONFIG_PM_RUNTIME
	104	+struct d3cold_info {
	105	+ bool no_d3cold;
	106	+ unsigned int d3cold_delay;
	107	+};
	108	+
	109	+static int pci_dev_d3cold_info(struct pci_dev pdev, void data)
	110	+{
	111	+ struct d3cold_info *info = data;
	112	+
	113	+ info->d3cold_delay = max_t(unsigned int, pdev->d3cold_delay,
	114	+ info->d3cold_delay);
	115	+ if (pdev->no_d3cold)
	116	+ info->no_d3cold = true;
	117	+ return 0;
	118	+}
	119	+
	120	+static int pcie_port_runtime_suspend(struct device *dev)
	121	+{
	122	+ struct pci_dev *pdev = to_pci_dev(dev);
	123	+ struct d3cold_info d3cold_info = {
	124	+ .no_d3cold = false,
	125	+ .d3cold_delay = PCI_PM_D3_WAIT,
	126	+ };
	127	+
	128	+ /*
	129	+ * If any subordinate device disable D3cold, we should not put
	130	+ * the port into D3cold. The D3cold delay of port should be
	131	+ * the max of that of all subordinate devices.
	132	+ */
	133	+ pci_walk_bus(pdev->subordinate, pci_dev_d3cold_info, &d3cold_info);
	134	+ pdev->no_d3cold = d3cold_info.no_d3cold;
	135	+ pdev->d3cold_delay = d3cold_info.d3cold_delay;
	136	+ return 0;
	137	+}
	138	+
	139	+static int pcie_port_runtime_resume(struct device *dev)
	140	+{
	141	+ return 0;
	142	+}
	143	+#else
	144	+#define pcie_port_runtime_suspend NULL
	145	+#define pcie_port_runtime_resume NULL
	146	+#endif
	147	+
102	148	static const struct dev_pm_ops pcie_portdrv_pm_ops = {
103	149	.suspend = pcie_port_device_suspend,
104	150	.resume = pcie_port_device_resume,
@@ -107,6 +153,8 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = { · 2 unmodified lines
107	153	.poweroff = pcie_port_device_suspend,
108	154	.restore = pcie_port_device_resume,
109	155	.resume_noirq = pcie_port_resume_noirq,
	156	+ .runtime_suspend = pcie_port_runtime_suspend,
	157	+ .runtime_resume = pcie_port_runtime_resume,
110	158	};
111	159
112	160	#define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops)
@@ -116,6 +164,14 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = { · 3 unmodified lines
116	164	#define PCIE_PORTDRV_PM_OPS NULL
117	165	#endif /* !PM */
118	166
	167	+/*
	168	+ * PCIe port runtime suspend is broken for some chipsets, so use a
	169	+ * black list to disable runtime PM for these chipsets.
	170	+ */
	171	+static const struct pci_device_id port_runtime_pm_black_list[] = {
	172	+ { /* end: all zeroes */ }
	173	+};
	174	+
119	175	/*
120	176	* pcie_portdrv_probe - Probe PCI-Express port devices
121	177	* @dev: PCI-Express port device being probed
@@ -144,12 +200,16 @@ static int __devinit pcie_portdrv_probe(struct pci_dev *dev, · 22 unmodified lines
144	200	return status;
145	201
146	202	pci_save_state(dev);
	203	+ if (!pci_match_id(port_runtime_pm_black_list, dev))
	204	+ pm_runtime_put_noidle(&dev->dev);
147	205
148	206	return 0;
149	207	}
150	208
151	209	static void pcie_portdrv_remove(struct pci_dev *dev)
152	210	{
	211	+ if (!pci_match_id(port_runtime_pm_black_list, dev))
	212	+ pm_runtime_get_noresume(&dev->dev);
153	213	pcie_port_device_remove(dev);
154	214	pci_disable_device(dev);
155	215	}

drivers/pci/probe.c+191−55

@@ -16,10 +16,47 @@ · 15 unmodified lines
16	16	#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17	17	#define CARDBUS_RESERVE_BUSNR 3
18	18
	19	+struct resource busn_resource = {
	20	+ .name = "PCI busn",
	21	+ .start = 0,
	22	+ .end = 255,
	23	+ .flags = IORESOURCE_BUS,
	24	+};
	25	+
19	26	/* Ugh. Need to stop exporting this to modules. */
20	27	LIST_HEAD(pci_root_buses);
21	28	EXPORT_SYMBOL(pci_root_buses);
22	29
	30	+static LIST_HEAD(pci_domain_busn_res_list);
	31	+
	32	+struct pci_domain_busn_res {
	33	+ struct list_head list;
	34	+ struct resource res;
	35	+ int domain_nr;
	36	+};
	37	+
	38	+static struct resource *get_pci_domain_busn_res(int domain_nr)
	39	+{
	40	+ struct pci_domain_busn_res *r;
	41	+
	42	+ list_for_each_entry(r, &pci_domain_busn_res_list, list)
	43	+ if (r->domain_nr == domain_nr)
	44	+ return &r->res;
	45	+
	46	+ r = kzalloc(sizeof(*r), GFP_KERNEL);
	47	+ if (!r)
	48	+ return NULL;
	49	+
	50	+ r->domain_nr = domain_nr;
	51	+ r->res.start = 0;
	52	+ r->res.end = 0xff;
	53	+ r->res.flags = IORESOURCE_BUS \| IORESOURCE_PCI_FIXED;
	54	+
	55	+ list_add_tail(&r->list, &pci_domain_busn_res_list);
	56	+
	57	+ return &r->res;
	58	+}
	59	+
23	60	static int find_anything(struct device dev, void data)
24	61	{
25	62	return 1;
@@ -152,9 +189,6 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, · 126 unmodified lines
152	189	pci_read_config_dword(dev, pos, &sz);
153	190	pci_write_config_dword(dev, pos, l);
154	191
155		− if (!dev->mmio_always_on)
156		− pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
157		−
158	192	/*
159	193	* All bits set in sz means the device isn't working properly.
160	194	* If the BAR isn't implemented, all bits must be 0. If it's a
@@ -239,6 +273,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, · 78 unmodified lines
239	273	}
240	274
241	275	out:
	276	+ if (!dev->mmio_always_on)
	277	+ pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
	278	+
242	279	return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
243	280	fail:
244	281	res->flags = 0;
@@ -269,34 +306,38 @@ static void __devinit pci_read_bridge_io(struct pci_bus *child) · 24 unmodified lines
269	306	{
270	307	struct pci_dev *dev = child->self;
271	308	u8 io_base_lo, io_limit_lo;
272		− unsigned long base, limit;
	309	+ unsigned long io_mask, io_granularity, base, limit;
273	310	struct pci_bus_region region;
274		− struct resource *res, res2;
	311	+ struct resource *res;
	312	+
	313	+ io_mask = PCI_IO_RANGE_MASK;
	314	+ io_granularity = 0x1000;
	315	+ if (dev->io_window_1k) {
	316	+ /* Support 1K I/O space granularity */
	317	+ io_mask = PCI_IO_1K_RANGE_MASK;
	318	+ io_granularity = 0x400;
	319	+ }
275	320
276	321	res = child->resource[0];
277	322	pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
278	323	pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
279		− base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
280		− limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
	324	+ base = (io_base_lo & io_mask) << 8;
	325	+ limit = (io_limit_lo & io_mask) << 8;
281	326
282	327	if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
283	328	u16 io_base_hi, io_limit_hi;
	329	+
284	330	pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
285	331	pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
286		− base \|= (io_base_hi << 16);
287		− limit \|= (io_limit_hi << 16);
	332	+ base \|= ((unsigned long) io_base_hi << 16);
	333	+ limit \|= ((unsigned long) io_limit_hi << 16);
288	334	}
289	335
290		− if (base && base <= limit) {
	336	+ if (base <= limit) {
291	337	res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) \| IORESOURCE_IO;
292		− res2.flags = res->flags;
293	338	region.start = base;
294		− region.end = limit + 0xfff;
295		− pcibios_bus_to_resource(dev, &res2, &region);
296		− if (!res->start)
297		− res->start = res2.start;
298		− if (!res->end)
299		− res->end = res2.end;
	339	+ region.end = limit + io_granularity - 1;
	340	+ pcibios_bus_to_resource(dev, res, &region);
300	341	dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
301	342	}
302	343	}
@@ -312,9 +353,9 @@ static void __devinit pci_read_bridge_mmio(struct pci_bus *child) · 9 unmodified lines
312	353	res = child->resource[1];
313	354	pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
314	355	pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
315		− base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
316		− limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
317		− if (base && base <= limit) {
	356	+ base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
	357	+ limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
	358	+ if (base <= limit) {
318	359	res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) \| IORESOURCE_MEM;
319	360	region.start = base;
320	361	region.end = limit + 0xfffff;
@@ -334,11 +375,12 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) · 13 unmodified lines
334	375	res = child->resource[2];
335	376	pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
336	377	pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
337		− base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
338		− limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
	378	+ base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
	379	+ limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
339	380
340	381	if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
341	382	u32 mem_base_hi, mem_limit_hi;
	383	+
342	384	pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
343	385	pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
344	386
@@ -349,8 +391,8 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) · 4 unmodified lines
349	391	*/
350	392	if (mem_base_hi <= mem_limit_hi) {
351	393	#if BITS_PER_LONG == 64
352		− base \|= ((long) mem_base_hi) << 32;
353		− limit \|= ((long) mem_limit_hi) << 32;
	394	+ base \|= ((unsigned long) mem_base_hi) << 32;
	395	+ limit \|= ((unsigned long) mem_limit_hi) << 32;
354	396	#else
355	397	if (mem_base_hi \|\| mem_limit_hi) {
356	398	dev_err(&dev->dev, "can't handle 64-bit "
@@ -360,7 +402,7 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) · 3 unmodified lines
360	402	#endif
361	403	}
362	404	}
363		− if (base && base <= limit) {
	405	+ if (base <= limit) {
364	406	res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) \|
365	407	IORESOURCE_MEM \| IORESOURCE_PREFETCH;
366	408	if (res->flags & PCI_PREF_RANGE_TYPE_64)
@@ -381,8 +423,8 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child) · 14 unmodified lines
381	423	if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
382	424	return;
383	425
384		− dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
385		− child->secondary, child->subordinate,
	426	+ dev_info(&dev->dev, "PCI bridge to %pR%s\n",
	427	+ &child->busn_res,
386	428	dev->transparent ? " (subtractive decode)" : "");
387	429
388	430	pci_bus_remove_resources(child);
@@ -599,9 +641,9 @@ static struct pci_bus pci_alloc_child_bus(struct pci_bus parent, · 210 unmodified lines
599	641	* Set up the primary, secondary and subordinate
600	642	* bus numbers.
601	643	*/
602		− child->number = child->secondary = busnr;
603		− child->primary = parent->secondary;
604		− child->subordinate = 0xff;
	644	+ child->number = child->busn_res.start = busnr;
	645	+ child->primary = parent->busn_res.start;
	646	+ child->busn_res.end = 0xff;
605	647
606	648	if (!bridge)
607	649	return child;
@@ -643,8 +685,8 @@ static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) · 35 unmodified lines
643	685	if (!pcibios_assign_all_busses())
644	686	return;
645	687
646		− while (parent->parent && parent->subordinate < max) {
647		− parent->subordinate = max;
	688	+ while (parent->parent && parent->busn_res.end < max) {
	689	+ parent->busn_res.end = max;
648	690	pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
649	691	parent = parent->parent;
650	692	}
@@ -718,15 +760,15 @@ int __devinit pci_scan_bridge(struct pci_bus bus, struct pci_dev dev, int max, · 67 unmodified lines
718	760	if (!child)
719	761	goto out;
720	762	child->primary = primary;
721		− child->subordinate = subordinate;
	763	+ pci_bus_insert_busn_res(child, secondary, subordinate);
722	764	child->bridge_ctl = bctl;
723	765	}
724	766
725	767	cmax = pci_scan_child_bus(child);
726	768	if (cmax > max)
727	769	max = cmax;
728		− if (child->subordinate > max)
729		− max = child->subordinate;
	770	+ if (child->busn_res.end > max)
	771	+ max = child->busn_res.end;
730	772	} else {
731	773	/*
732	774	* We need to assign a number to this bus which we always
@@ -756,11 +798,12 @@ int __devinit pci_scan_bridge(struct pci_bus bus, struct pci_dev dev, int max, · 23 unmodified lines
756	798	child = pci_add_new_bus(bus, dev, ++max);
757	799	if (!child)
758	800	goto out;
	801	+ pci_bus_insert_busn_res(child, max, 0xff);
759	802	}
760	803	buses = (buses & 0xff000000)
761	804	\| ((unsigned int)(child->primary) << 0)
762		− \| ((unsigned int)(child->secondary) << 8)
763		− \| ((unsigned int)(child->subordinate) << 16);
	805	+ \| ((unsigned int)(child->busn_res.start) << 8)
	806	+ \| ((unsigned int)(child->busn_res.end) << 16);
764	807
765	808	/*
766	809	* yenta.c forces a secondary latency timer of 176.
@@ -805,8 +848,8 @@ int __devinit pci_scan_bridge(struct pci_bus bus, struct pci_dev dev, int max, · 38 unmodified lines
805	848	break;
806	849	while (parent->parent) {
807	850	if ((!pcibios_assign_all_busses()) &&
808		− (parent->subordinate > max) &&
809		− (parent->subordinate <= max+i)) {
	851	+ (parent->busn_res.end > max) &&
	852	+ (parent->busn_res.end <= max+i)) {
810	853	j = 1;
811	854	}
812	855	parent = parent->parent;
@@ -827,7 +870,7 @@ int __devinit pci_scan_bridge(struct pci_bus bus, struct pci_dev dev, int max, · 14 unmodified lines
827	870	/*
828	871	* Set the subordinate bus number to its real value.
829	872	*/
830		− child->subordinate = max;
	873	+ pci_bus_update_busn_res_end(child, max);
831	874	pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
832	875	}
833	876
@@ -837,19 +880,19 @@ int __devinit pci_scan_bridge(struct pci_bus bus, struct pci_dev dev, int max, · 3 unmodified lines
837	880
838	881	/* Has only triggered on CardBus, fixup is in yenta_socket */
839	882	while (bus->parent) {
840		− if ((child->subordinate > bus->subordinate) \|\|
841		− (child->number > bus->subordinate) \|\|
	883	+ if ((child->busn_res.end > bus->busn_res.end) \|\|
	884	+ (child->number > bus->busn_res.end) \|\|
842	885	(child->number < bus->number) \|\|
843		− (child->subordinate < bus->number)) {
844		− dev_info(&child->dev, "[bus %02x-%02x] %s "
845		− "hidden behind%s bridge %s [bus %02x-%02x]\n",
846		− child->number, child->subordinate,
847		− (bus->number > child->subordinate &&
848		− bus->subordinate < child->number) ?
	886	+ (child->busn_res.end < bus->number)) {
	887	+ dev_info(&child->dev, "%pR %s "
	888	+ "hidden behind%s bridge %s %pR\n",
	889	+ &child->busn_res,
	890	+ (bus->number > child->busn_res.end &&
	891	+ bus->busn_res.end < child->number) ?
849	892	"wholly" : "partially",
850	893	bus->self->transparent ? " transparent" : "",
851	894	dev_name(&bus->dev),
852		− bus->number, bus->subordinate);
	895	+ &bus->busn_res);
853	896	}
854	897	bus = bus->parent;
855	898	}
@@ -1548,7 +1591,7 @@ EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); · 692 unmodified lines
1548	1591
1549	1592	unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1550	1593	{
1551		− unsigned int devfn, pass, max = bus->secondary;
	1594	+ unsigned int devfn, pass, max = bus->busn_res.start;
1552	1595	struct pci_dev *dev;
1553	1596
1554	1597	dev_dbg(&bus->dev, "scanning bus\n");
@@ -1642,7 +1685,7 @@ struct pci_bus pci_create_root_bus(struct device parent, int bus, · 87 unmodified lines
1642	1685	/* Create legacy_io and legacy_mem files for this bus */
1643	1686	pci_create_legacy_files(b);
1644	1687
1645		− b->number = b->secondary = bus;
	1688	+ b->number = b->busn_res.start = bus;
1646	1689
1647	1690	if (parent)
1648	1691	dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
@@ -1654,7 +1697,10 @@ struct pci_bus pci_create_root_bus(struct device parent, int bus, · 5 unmodified lines
1654	1697	list_move_tail(&window->list, &bridge->windows);
1655	1698	res = window->res;
1656	1699	offset = window->offset;
1657		− pci_bus_add_resource(b, res, 0);
	1700	+ if (res->flags & IORESOURCE_BUS)
	1701	+ pci_bus_insert_busn_res(b, bus, res->end);
	1702	+ else
	1703	+ pci_bus_add_resource(b, res, 0);
1658	1704	if (offset) {
1659	1705	if (resource_type(res) == IORESOURCE_IO)
1660	1706	fmt = " (bus address [%#06llx-%#06llx])";
@@ -1684,16 +1730,104 @@ err_out: · 23 unmodified lines
1684	1730	return NULL;
1685	1731	}
1686	1732
	1733	+int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
	1734	+{
	1735	+ struct resource *res = &b->busn_res;
	1736	+ struct resource parent_res, conflict;
	1737	+
	1738	+ res->start = bus;
	1739	+ res->end = bus_max;
	1740	+ res->flags = IORESOURCE_BUS;
	1741	+
	1742	+ if (!pci_is_root_bus(b))
	1743	+ parent_res = &b->parent->busn_res;
	1744	+ else {
	1745	+ parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
	1746	+ res->flags \|= IORESOURCE_PCI_FIXED;
	1747	+ }
	1748	+
	1749	+ conflict = insert_resource_conflict(parent_res, res);
	1750	+
	1751	+ if (conflict)
	1752	+ dev_printk(KERN_DEBUG, &b->dev,
	1753	+ "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
	1754	+ res, pci_is_root_bus(b) ? "domain " : "",
	1755	+ parent_res, conflict->name, conflict);
	1756	+ else
	1757	+ dev_printk(KERN_DEBUG, &b->dev,
	1758	+ "busn_res: %pR is inserted under %s%pR\n",
	1759	+ res, pci_is_root_bus(b) ? "domain " : "",
	1760	+ parent_res);
	1761	+
	1762	+ return conflict == NULL;
	1763	+}
	1764	+
	1765	+int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
	1766	+{
	1767	+ struct resource *res = &b->busn_res;
	1768	+ struct resource old_res = *res;
	1769	+ resource_size_t size;
	1770	+ int ret;
	1771	+
	1772	+ if (res->start > bus_max)
	1773	+ return -EINVAL;
	1774	+
	1775	+ size = bus_max - res->start + 1;
	1776	+ ret = adjust_resource(res, res->start, size);
	1777	+ dev_printk(KERN_DEBUG, &b->dev,
	1778	+ "busn_res: %pR end %s updated to %02x\n",
	1779	+ &old_res, ret ? "can not be" : "is", bus_max);
	1780	+
	1781	+ if (!ret && !res->parent)
	1782	+ pci_bus_insert_busn_res(b, res->start, res->end);
	1783	+
	1784	+ return ret;
	1785	+}
	1786	+
	1787	+void pci_bus_release_busn_res(struct pci_bus *b)
	1788	+{
	1789	+ struct resource *res = &b->busn_res;
	1790	+ int ret;
	1791	+
	1792	+ if (!res->flags \|\| !res->parent)
	1793	+ return;
	1794	+
	1795	+ ret = release_resource(res);
	1796	+ dev_printk(KERN_DEBUG, &b->dev,
	1797	+ "busn_res: %pR %s released\n",
	1798	+ res, ret ? "can not be" : "is");
	1799	+}
	1800	+
1687	1801	struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
1688	1802	struct pci_ops ops, void sysdata, struct list_head *resources)
1689	1803	{
	1804	+ struct pci_host_bridge_window *window;
	1805	+ bool found = false;
1690	1806	struct pci_bus *b;
	1807	+ int max;
	1808	+
	1809	+ list_for_each_entry(window, resources, list)
	1810	+ if (window->res->flags & IORESOURCE_BUS) {
	1811	+ found = true;
	1812	+ break;
	1813	+ }
1691	1814
1692	1815	b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1693	1816	if (!b)
1694	1817	return NULL;
1695	1818
1696		− b->subordinate = pci_scan_child_bus(b);
	1819	+ if (!found) {
	1820	+ dev_info(&b->dev,
	1821	+ "No busn resource found for root bus, will use [bus %02x-ff]\n",
	1822	+ bus);
	1823	+ pci_bus_insert_busn_res(b, bus, 255);
	1824	+ }
	1825	+
	1826	+ max = pci_scan_child_bus(b);
	1827	+
	1828	+ if (!found)
	1829	+ pci_bus_update_busn_res_end(b, max);
	1830	+
1697	1831	pci_bus_add_devices(b);
1698	1832	return b;
1699	1833	}
@@ -1708,9 +1842,10 @@ struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, · 8 unmodified lines
1708	1842
1709	1843	pci_add_resource(&resources, &ioport_resource);
1710	1844	pci_add_resource(&resources, &iomem_resource);
	1845	+ pci_add_resource(&resources, &busn_resource);
1711	1846	b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
1712	1847	if (b)
1713		− b->subordinate = pci_scan_child_bus(b);
	1848	+ pci_scan_child_bus(b);
1714	1849	else
1715	1850	pci_free_resource_list(&resources);
1716	1851	return b;
@@ -1725,9 +1860,10 @@ struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, · 8 unmodified lines
1725	1860
1726	1861	pci_add_resource(&resources, &ioport_resource);
1727	1862	pci_add_resource(&resources, &iomem_resource);
	1863	+ pci_add_resource(&resources, &busn_resource);
1728	1864	b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1729	1865	if (b) {
1730		− b->subordinate = pci_scan_child_bus(b);
	1866	+ pci_scan_child_bus(b);
1731	1867	pci_bus_add_devices(b);
1732	1868	} else {
1733	1869	pci_free_resource_list(&resources);

drivers/pci/quirks.c+163−79

@@ -253,7 +253,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx) · 252 unmodified lines
253	253	* workaround applied too
254	254	* [Info kindly provided by ALi]
255	255	*/
256		−static void __init quirk_alimagik(struct pci_dev *dev)
	256	+static void __devinit quirk_alimagik(struct pci_dev *dev)
257	257	{
258	258	if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
259	259	dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
@@ -789,7 +789,7 @@ static void __devinit quirk_amd_ioapic(struct pci_dev *dev) · 529 unmodified lines
789	789	}
790	790	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
791	791
792		−static void __init quirk_ioapic_rmw(struct pci_dev *dev)
	792	+static void __devinit quirk_ioapic_rmw(struct pci_dev *dev)
793	793	{
794	794	if (dev->devfn == 0 && dev->bus->number == 0)
795	795	sis_apic_bug = 1;
@@ -801,7 +801,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); · 5 unmodified lines
801	801	* Some settings of MMRBC can lead to data corruption so block changes.
802	802	* See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
803	803	*/
804		−static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
	804	+static void __devinit quirk_amd_8131_mmrbc(struct pci_dev *dev)
805	805	{
806	806	if (dev->subordinate && dev->revision <= 0x12) {
807	807	dev_info(&dev->dev, "AMD8131 rev %x detected; "
@@ -1039,7 +1039,7 @@ static void quirk_disable_pxb(struct pci_dev *pdev) · 231 unmodified lines
1039	1039	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1040	1040	DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1041	1041
1042		−static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
	1042	+static void quirk_amd_ide_mode(struct pci_dev *pdev)
1043	1043	{
1044	1044	/* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1045	1045	u8 tmp;
@@ -1082,7 +1082,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB · 36 unmodified lines
1082	1082	/*
1083	1083	* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1084	1084	*/
1085		−static void __init quirk_ide_samemode(struct pci_dev *pdev)
	1085	+static void __devinit quirk_ide_samemode(struct pci_dev *pdev)
1086	1086	{
1087	1087	u8 prog;
1088	1088
@@ -1121,7 +1121,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, · 32 unmodified lines
1121	1121	/* This was originally an Alpha specific thing, but it really fits here.
1122	1122	* The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1123	1123	*/
1124		−static void __init quirk_eisa_bridge(struct pci_dev *dev)
	1124	+static void __devinit quirk_eisa_bridge(struct pci_dev *dev)
1125	1125	{
1126	1126	dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1127	1127	}
@@ -1155,7 +1155,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_e · 27 unmodified lines
1155	1155	*/
1156	1156	static int asus_hides_smbus;
1157	1157
1158		−static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
	1158	+static void __devinit asus_hides_smbus_hostbridge(struct pci_dev *dev)
1159	1159	{
1160	1160	if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1161	1161	if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
@@ -1538,7 +1538,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB3 · 376 unmodified lines
1538	1538	#endif
1539	1539
1540	1540	#ifdef CONFIG_X86_IO_APIC
1541		−static void __init quirk_alder_ioapic(struct pci_dev *pdev)
	1541	+static void __devinit quirk_alder_ioapic(struct pci_dev *pdev)
1542	1542	{
1543	1543	int i;
1544	1544
@@ -1777,7 +1777,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, qui · 232 unmodified lines
1777	1777	* but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1778	1778	* Re-allocate the region if needed...
1779	1779	*/
1780		−static void __init quirk_tc86c001_ide(struct pci_dev *dev)
	1780	+static void __devinit quirk_tc86c001_ide(struct pci_dev *dev)
1781	1781	{
1782	1782	struct resource *r = &dev->resource[0];
1783	1783
@@ -1938,53 +1938,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1 · 154 unmodified lines
1938	1938	static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1939	1939	{
1940	1940	u16 en1k;
1941		− u8 io_base_lo, io_limit_lo;
1942		− unsigned long base, limit;
1943		− struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1944	1941
1945	1942	pci_read_config_word(dev, 0x40, &en1k);
1946	1943
1947	1944	if (en1k & 0x200) {
1948	1945	dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1949		−
1950		− pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1951		− pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1952		− base = (io_base_lo & (PCI_IO_RANGE_MASK \| 0x0c)) << 8;
1953		− limit = (io_limit_lo & (PCI_IO_RANGE_MASK \| 0x0c)) << 8;
1954		−
1955		− if (base <= limit) {
1956		− res->start = base;
1957		− res->end = limit + 0x3ff;
1958		− }
	1946	+ dev->io_window_1k = 1;
1959	1947	}
1960	1948	}
1961	1949	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1962	1950
1963		−/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1964		− * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1965		− * in drivers/pci/setup-bus.c
1966		− */
1967		−static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1968		−{
1969		− u16 en1k, iobl_adr, iobl_adr_1k;
1970		− struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1971		−
1972		− pci_read_config_word(dev, 0x40, &en1k);
1973		−
1974		− if (en1k & 0x200) {
1975		− pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1976		−
1977		− iobl_adr_1k = iobl_adr \| (res->start >> 8) \| (res->end & 0xfc00);
1978		−
1979		− if (iobl_adr != iobl_adr_1k) {
1980		− dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1981		− iobl_adr,iobl_adr_1k);
1982		− pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1983		− }
1984		− }
1985		−}
1986		−DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1987		−
1988	1951	/* Under some circumstances, AER is not linked with extended capabilities.
1989	1952	* Force it to be linked by setting the corresponding control bit in the
1990	1953	* config space.
@@ -2104,7 +2067,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, · 113 unmodified lines
2104	2067	PCI_DEVICE_ID_NX2_5709S,
2105	2068	quirk_brcm_570x_limit_vpd);
2106	2069
2107		−static void __devinit quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
	2070	+static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2108	2071	{
2109	2072	u32 rev;
2110	2073
@@ -2169,7 +2132,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); · 58 unmodified lines
2169	2132	* aware of it. Instead of setting the flag on all busses in the
2170	2133	* machine, simply disable MSI globally.
2171	2134	*/
2172		−static void __init quirk_disable_all_msi(struct pci_dev *dev)
	2135	+static void __devinit quirk_disable_all_msi(struct pci_dev *dev)
2173	2136	{
2174	2137	pci_no_msi();
2175	2138	dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
@@ -2217,7 +2180,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); · 41 unmodified lines
2217	2180
2218	2181	/* Go through the list of Hypertransport capabilities and
2219	2182	* return 1 if a HT MSI capability is found and enabled */
2220		−static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
	2183	+static int msi_ht_cap_enabled(struct pci_dev *dev)
2221	2184	{
2222	2185	int pos, ttl = 48;
2223	2186
@@ -2241,7 +2204,7 @@ static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) · 17 unmodified lines
2241	2204	}
2242	2205
2243	2206	/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2244		−static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
	2207	+static void quirk_msi_ht_cap(struct pci_dev *dev)
2245	2208	{
2246	2209	if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2247	2210	dev_warn(&dev->dev, "MSI quirk detected; "
@@ -2255,7 +2218,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2 · 7 unmodified lines
2255	2218	/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2256	2219	* MSI are supported if the MSI capability set in any of these mappings.
2257	2220	*/
2258		−static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
	2221	+static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2259	2222	{
2260	2223	struct pci_dev *pdev;
2261	2224
@@ -2279,7 +2242,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, · 17 unmodified lines
2279	2242	quirk_nvidia_ck804_msi_ht_cap);
2280	2243
2281	2244	/* Force enable MSI mapping capability on HT bridges */
2282		−static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
	2245	+static void ht_enable_msi_mapping(struct pci_dev *dev)
2283	2246	{
2284	2247	int pos, ttl = 48;
2285	2248
@@ -2359,7 +2322,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, · 73 unmodified lines
2359	2322	PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2360	2323	nvbridge_check_legacy_irq_routing);
2361	2324
2362		−static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
	2325	+static int ht_check_msi_mapping(struct pci_dev *dev)
2363	2326	{
2364	2327	int pos, ttl = 48;
2365	2328	int found = 0;
@@ -2387,7 +2350,7 @@ static int __devinit ht_check_msi_mapping(struct pci_dev *dev) · 21 unmodified lines
2387	2350	return found;
2388	2351	}
2389	2352
2390		−static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
	2353	+static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2391	2354	{
2392	2355	struct pci_dev *dev;
2393	2356	int pos;
@@ -2421,7 +2384,7 @@ static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) · 27 unmodified lines
2421	2384	#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2422	2385	#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2423	2386
2424		−static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
	2387	+static int is_end_of_ht_chain(struct pci_dev *dev)
2425	2388	{
2426	2389	int pos, ctrl_off;
2427	2390	int end = 0;
@@ -2445,7 +2408,7 @@ out: · 17 unmodified lines
2445	2408	return end;
2446	2409	}
2447	2410
2448		−static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
	2411	+static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2449	2412	{
2450	2413	struct pci_dev *host_bridge;
2451	2414	int pos;
@@ -2484,7 +2447,7 @@ out: · 32 unmodified lines
2484	2447	pci_dev_put(host_bridge);
2485	2448	}
2486	2449
2487		−static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
	2450	+static void ht_disable_msi_mapping(struct pci_dev *dev)
2488	2451	{
2489	2452	int pos, ttl = 48;
2490	2453
@@ -2504,7 +2467,7 @@ static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) · 13 unmodified lines
2504	2467	}
2505	2468	}
2506	2469
2507		−static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
	2470	+static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2508	2471	{
2509	2472	struct pci_dev *host_bridge;
2510	2473	int pos;
@@ -2541,23 +2504,26 @@ static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) · 30 unmodified lines
2541	2504	else
2542	2505	nv_ht_enable_msi_mapping(dev);
2543	2506	}
2544		− return;
	2507	+ goto out;
2545	2508	}
2546	2509
2547	2510	/* HT MSI is not enabled */
2548	2511	if (found == 1)
2549		− return;
	2512	+ goto out;
2550	2513
2551	2514	/* Host bridge is not to HT, disable HT MSI mapping on this device */
2552	2515	ht_disable_msi_mapping(dev);
	2516	+
	2517	+out:
	2518	+ pci_dev_put(host_bridge);
2553	2519	}
2554	2520
2555		−static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
	2521	+static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2556	2522	{
2557	2523	return __nv_msi_ht_cap_quirk(dev, 1);
2558	2524	}
2559	2525
2560		−static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
	2526	+static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2561	2527	{
2562	2528	return __nv_msi_ht_cap_quirk(dev, 0);
2563	2529	}
@@ -2879,20 +2845,34 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); · 315 unmodified lines
2879	2845	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2880	2846
2881	2847
2882		−static void do_one_fixup_debug(void (fn)(struct pci_dev dev), struct pci_dev *dev)
	2848	+static ktime_t fixup_debug_start(struct pci_dev *dev,
	2849	+ void (fn)(struct pci_dev dev))
	2850	+{
	2851	+ ktime_t calltime = ktime_set(0, 0);
	2852	+
	2853	+ dev_dbg(&dev->dev, "calling %pF\n", fn);
	2854	+ if (initcall_debug) {
	2855	+ pr_debug("calling %pF @ %i for %s\n",
	2856	+ fn, task_pid_nr(current), dev_name(&dev->dev));
	2857	+ calltime = ktime_get();
	2858	+ }
	2859	+
	2860	+ return calltime;
	2861	+}
	2862	+
	2863	+static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
	2864	+ void (fn)(struct pci_dev dev))
2883	2865	{
2884		− ktime_t calltime, delta, rettime;
	2866	+ ktime_t delta, rettime;
2885	2867	unsigned long long duration;
2886	2868
2887		− printk(KERN_DEBUG "calling %pF @ %i for %s\n",
2888		− fn, task_pid_nr(current), dev_name(&dev->dev));
2889		− calltime = ktime_get();
2890		− fn(dev);
2891		− rettime = ktime_get();
2892		− delta = ktime_sub(rettime, calltime);
2893		− duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2894		− printk(KERN_DEBUG "pci fixup %pF returned after %lld usecs for %s\n",
2895		− fn, duration, dev_name(&dev->dev));
	2869	+ if (initcall_debug) {
	2870	+ rettime = ktime_get();
	2871	+ delta = ktime_sub(rettime, calltime);
	2872	+ duration = (unsigned long long) ktime_to_ns(delta) >> 10;
	2873	+ pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
	2874	+ fn, duration, dev_name(&dev->dev));
	2875	+ }
2896	2876	}
2897	2877
2898	2878	/*
@@ -2929,9 +2909,25 @@ static void __devinit disable_igfx_irq(struct pci_dev *dev) · 30 unmodified lines
2929	2909	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2930	2910	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2931	2911
	2912	+/*
	2913	+ * Some devices may pass our check in pci_intx_mask_supported if
	2914	+ * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
	2915	+ * support this feature.
	2916	+ */
	2917	+static void __devinit quirk_broken_intx_masking(struct pci_dev *dev)
	2918	+{
	2919	+ dev->broken_intx_masking = 1;
	2920	+}
	2921	+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
	2922	+ quirk_broken_intx_masking);
	2923	+DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
	2924	+ quirk_broken_intx_masking);
	2925	+
2932	2926	static void pci_do_fixups(struct pci_dev dev, struct pci_fixup f,
2933	2927	struct pci_fixup *end)
2934	2928	{
	2929	+ ktime_t calltime;
	2930	+
2935	2931	for (; f < end; f++)
2936	2932	if ((f->class == (u32) (dev->class >> f->class_shift) \|\|
2937	2933	f->class == (u32) PCI_ANY_ID) &&
@@ -2939,11 +2935,9 @@ static void pci_do_fixups(struct pci_dev dev, struct pci_fixup f, · 1 unmodified line
2939	2935	f->vendor == (u16) PCI_ANY_ID) &&
2940	2936	(f->device == dev->device \|\|
2941	2937	f->device == (u16) PCI_ANY_ID)) {
2942		− dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2943		− if (initcall_debug)
2944		− do_one_fixup_debug(f->hook, dev);
2945		− else
2946		− f->hook(dev);
	2938	+ calltime = fixup_debug_start(dev, f->hook);
	2939	+ f->hook(dev);
	2940	+ fixup_debug_report(dev, calltime, f->hook);
2947	2941	}
2948	2942	}
2949	2943
@@ -2962,6 +2956,7 @@ extern struct pci_fixup __end_pci_fixups_resume_early[]; · 12 unmodified lines
2962	2956	extern struct pci_fixup __start_pci_fixups_suspend[];
2963	2957	extern struct pci_fixup __end_pci_fixups_suspend[];
2964	2958
	2959	+static bool pci_apply_fixup_final_quirks;
2965	2960
2966	2961	void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2967	2962	{
@@ -2979,6 +2974,8 @@ void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) · 11 unmodified lines
2979	2974	break;
2980	2975
2981	2976	case pci_fixup_final:
	2977	+ if (!pci_apply_fixup_final_quirks)
	2978	+ return;
2982	2979	start = __start_pci_fixups_final;
2983	2980	end = __end_pci_fixups_final;
2984	2981	break;
@@ -3011,6 +3008,7 @@ void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) · 26 unmodified lines
3011	3008	}
3012	3009	EXPORT_SYMBOL(pci_fixup_device);
3013	3010
	3011	+
3014	3012	static int __init pci_apply_final_quirks(void)
3015	3013	{
3016	3014	struct pci_dev *dev = NULL;
@@ -3021,6 +3019,7 @@ static int __init pci_apply_final_quirks(void) · 4 unmodified lines
3021	3019	printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3022	3020	pci_cache_line_size << 2);
3023	3021
	3022	+ pci_apply_fixup_final_quirks = true;
3024	3023	for_each_pci_dev(dev) {
3025	3024	pci_fixup_device(pci_fixup_final, dev);
3026	3025	/*
@@ -3041,6 +3040,7 @@ static int __init pci_apply_final_quirks(void) · 14 unmodified lines
3041	3040	pci_cache_line_size = pci_dfl_cache_line_size;
3042	3041	}
3043	3042	}
	3043	+
3044	3044	if (!pci_cache_line_size) {
3045	3045	printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3046	3046	cls << 2, pci_dfl_cache_line_size << 2);
@@ -3179,3 +3179,87 @@ int pci_dev_specific_reset(struct pci_dev *dev, int probe) · 132 unmodified lines
3179	3179
3180	3180	return -ENOTTY;
3181	3181	}
	3182	+
	3183	+static struct pci_dev pci_func_0_dma_source(struct pci_dev dev)
	3184	+{
	3185	+ if (!PCI_FUNC(dev->devfn))
	3186	+ return pci_dev_get(dev);
	3187	+
	3188	+ return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
	3189	+}
	3190	+
	3191	+static const struct pci_dev_dma_source {
	3192	+ u16 vendor;
	3193	+ u16 device;
	3194	+ struct pci_dev (dma_source)(struct pci_dev *dev);
	3195	+} pci_dev_dma_source[] = {
	3196	+ /*
	3197	+ * https://bugzilla.redhat.com/show_bug.cgi?id=605888
	3198	+ *
	3199	+ * Some Ricoh devices use the function 0 source ID for DMA on
	3200	+ * other functions of a multifunction device. The DMA devices
	3201	+ * is therefore function 0, which will have implications of the
	3202	+ * iommu grouping of these devices.
	3203	+ */
	3204	+ { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
	3205	+ { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
	3206	+ { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
	3207	+ { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
	3208	+ { 0 }
	3209	+};
	3210	+
	3211	+/*
	3212	+ * IOMMUs with isolation capabilities need to be programmed with the
	3213	+ * correct source ID of a device. In most cases, the source ID matches
	3214	+ * the device doing the DMA, but sometimes hardware is broken and will
	3215	+ * tag the DMA as being sourced from a different device. This function
	3216	+ * allows that translation. Note that the reference count of the
	3217	+ * returned device is incremented on all paths.
	3218	+ */
	3219	+struct pci_dev pci_get_dma_source(struct pci_dev dev)
	3220	+{
	3221	+ const struct pci_dev_dma_source *i;
	3222	+
	3223	+ for (i = pci_dev_dma_source; i->dma_source; i++) {
	3224	+ if ((i->vendor == dev->vendor \|\|
	3225	+ i->vendor == (u16)PCI_ANY_ID) &&
	3226	+ (i->device == dev->device \|\|
	3227	+ i->device == (u16)PCI_ANY_ID))
	3228	+ return i->dma_source(dev);
	3229	+ }
	3230	+
	3231	+ return pci_dev_get(dev);
	3232	+}
	3233	+
	3234	+static const struct pci_dev_acs_enabled {
	3235	+ u16 vendor;
	3236	+ u16 device;
	3237	+ int (acs_enabled)(struct pci_dev dev, u16 acs_flags);
	3238	+} pci_dev_acs_enabled[] = {
	3239	+ { 0 }
	3240	+};
	3241	+
	3242	+int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
	3243	+{
	3244	+ const struct pci_dev_acs_enabled *i;
	3245	+ int ret;
	3246	+
	3247	+ /*
	3248	+ * Allow devices that do not expose standard PCIe ACS capabilities
	3249	+ * or control to indicate their support here. Multi-function express
	3250	+ * devices which do not allow internal peer-to-peer between functions,
	3251	+ * but do not implement PCIe ACS may wish to return true here.
	3252	+ */
	3253	+ for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
	3254	+ if ((i->vendor == dev->vendor \|\|
	3255	+ i->vendor == (u16)PCI_ANY_ID) &&
	3256	+ (i->device == dev->device \|\|
	3257	+ i->device == (u16)PCI_ANY_ID)) {
	3258	+ ret = i->acs_enabled(dev, acs_flags);
	3259	+ if (ret >= 0)
	3260	+ return ret;
	3261	+ }
	3262	+ }
	3263	+
	3264	+ return -ENOTTY;
	3265	+}

drivers/pci/remove.c+1−0

@@ -68,6 +68,7 @@ void pci_remove_bus(struct pci_bus *pci_bus) · 67 unmodified lines
68	68
69	69	down_write(&pci_bus_sem);
70	70	list_del(&pci_bus->node);
	71	+ pci_bus_release_busn_res(pci_bus);
71	72	up_write(&pci_bus_sem);
72	73	if (!pci_bus->is_added)
73	74	return;

drivers/pci/search.c+2−0

@@ -15,6 +15,8 @@ · 14 unmodified lines
15	15	#include "pci.h"
16	16
17	17	DECLARE_RWSEM(pci_bus_sem);
	18	+EXPORT_SYMBOL_GPL(pci_bus_sem);
	19	+
18	20	/*
19	21	* find the upstream PCIe-to-PCI bridge of a PCI device
20	22	* if the device is PCIE, return NULL

drivers/pci/setup-bus.c+44−21

@@ -265,7 +265,7 @@ out: · 264 unmodified lines
265	265	* assign_requested_resources_sorted() - satisfy resource requests
266	266	*
267	267	* @head : head of the list tracking requests for resources
268		− * @failed_list : head of the list tracking requests that could
	268	+ * @fail_head : head of the list tracking requests that could
269	269	* not be allocated
270	270	*
271	271	* Satisfy resource requests of each element in the list. Add
@@ -404,8 +404,8 @@ void pci_setup_cardbus(struct pci_bus *bus) · 132 unmodified lines
404	404	struct resource *res;
405	405	struct pci_bus_region region;
406	406
407		− dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
408		− bus->secondary, bus->subordinate);
	407	+ dev_info(&bridge->dev, "CardBus bridge to %pR\n",
	408	+ &bus->busn_res);
409	409
410	410	res = bus->resource[0];
411	411	pcibios_resource_to_bus(bridge, &region, res);
@@ -469,16 +469,23 @@ static void pci_setup_bridge_io(struct pci_bus *bus) · 57 unmodified lines
469	469	struct pci_dev *bridge = bus->self;
470	470	struct resource *res;
471	471	struct pci_bus_region region;
	472	+ unsigned long io_mask;
	473	+ u8 io_base_lo, io_limit_lo;
472	474	u32 l, io_upper16;
473	475
	476	+ io_mask = PCI_IO_RANGE_MASK;
	477	+ if (bridge->io_window_1k)
	478	+ io_mask = PCI_IO_1K_RANGE_MASK;
	479	+
474	480	/* Set up the top and bottom of the PCI I/O segment for this bus. */
475	481	res = bus->resource[0];
476	482	pcibios_resource_to_bus(bridge, &region, res);
477	483	if (res->flags & IORESOURCE_IO) {
478	484	pci_read_config_dword(bridge, PCI_IO_BASE, &l);
479	485	l &= 0xffff0000;
480		− l \|= (region.start >> 8) & 0x00f0;
481		− l \|= region.end & 0xf000;
	486	+ io_base_lo = (region.start >> 8) & io_mask;
	487	+ io_limit_lo = (region.end >> 8) & io_mask;
	488	+ l \|= ((u32) io_limit_lo << 8) \| io_base_lo;
482	489	/* Set up upper 16 bits of I/O base/limit. */
483	490	io_upper16 = (region.end & 0xffff0000) \| (region.start >> 16);
484	491	dev_info(&bridge->dev, " bridge window %pR\n", res);
@@ -553,8 +560,8 @@ static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) · 68 unmodified lines
553	560	{
554	561	struct pci_dev *bridge = bus->self;
555	562
556		− dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
557		− bus->secondary, bus->subordinate);
	563	+ dev_info(&bridge->dev, "PCI bridge to %pR\n",
	564	+ &bus->busn_res);
558	565
559	566	if (type & IORESOURCE_IO)
560	567	pci_setup_bridge_io(bus);
@@ -699,7 +706,7 @@ static resource_size_t calculate_memsize(resource_size_t size, · 138 unmodified lines
699	706	* @realloc_head : track the additional io window on this list
700	707	*
701	708	* Sizing the IO windows of the PCI-PCI bridge is trivial,
702		− * since these windows have 4K granularity and the IO ranges
	709	+ * since these windows have 1K or 4K granularity and the IO ranges
703	710	* of non-bridge PCI devices are limited to 256 bytes.
704	711	* We must be careful with the ISA aliasing though.
705	712	*/
@@ -710,10 +717,17 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, · 4 unmodified lines
710	717	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
711	718	unsigned long size = 0, size0 = 0, size1 = 0;
712	719	resource_size_t children_add_size = 0;
	720	+ resource_size_t min_align = 4096, align;
713	721
714	722	if (!b_res)
715	723	return;
716	724
	725	+ /*
	726	+ * Per spec, I/O windows are 4K-aligned, but some bridges have an
	727	+ * extension to support 1K alignment.
	728	+ */
	729	+ if (bus->self->io_window_1k)
	730	+ min_align = 1024;
717	731	list_for_each_entry(dev, &bus->devices, bus_list) {
718	732	int i;
719	733
@@ -731,34 +745,43 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, · 11 unmodified lines
731	745	else
732	746	size1 += r_size;
733	747
	748	+ align = pci_resource_alignment(dev, r);
	749	+ if (align > min_align)
	750	+ min_align = align;
	751	+
734	752	if (realloc_head)
735	753	children_add_size += get_res_add_size(realloc_head, r);
736	754	}
737	755	}
	756	+
	757	+ if (min_align > 4096)
	758	+ min_align = 4096;
	759	+
738	760	size0 = calculate_iosize(size, min_size, size1,
739		− resource_size(b_res), 4096);
	761	+ resource_size(b_res), min_align);
740	762	if (children_add_size > add_size)
741	763	add_size = children_add_size;
742	764	size1 = (!realloc_head \|\| (realloc_head && !add_size)) ? size0 :
743	765	calculate_iosize(size, min_size, add_size + size1,
744		− resource_size(b_res), 4096);
	766	+ resource_size(b_res), min_align);
745	767	if (!size0 && !size1) {
746	768	if (b_res->start \|\| b_res->end)
747	769	dev_info(&bus->self->dev, "disabling bridge window "
748		− "%pR to [bus %02x-%02x] (unused)\n", b_res,
749		− bus->secondary, bus->subordinate);
	770	+ "%pR to %pR (unused)\n", b_res,
	771	+ &bus->busn_res);
750	772	b_res->flags = 0;
751	773	return;
752	774	}
753		− /* Alignment of the IO window is always 4K */
754		− b_res->start = 4096;
	775	+
	776	+ b_res->start = min_align;
755	777	b_res->end = b_res->start + size0 - 1;
756	778	b_res->flags \|= IORESOURCE_STARTALIGN;
757	779	if (size1 > size0 && realloc_head) {
758		− add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096);
	780	+ add_to_list(realloc_head, bus->self, b_res, size1-size0,
	781	+ min_align);
759	782	dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
760		− "%pR to [bus %02x-%02x] add_size %lx\n", b_res,
761		− bus->secondary, bus->subordinate, size1-size0);
	783	+ "%pR to %pR add_size %lx\n", b_res,
	784	+ &bus->busn_res, size1-size0);
762	785	}
763	786	}
764	787
@@ -863,8 +886,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, · 98 unmodified lines
863	886	if (!size0 && !size1) {
864	887	if (b_res->start \|\| b_res->end)
865	888	dev_info(&bus->self->dev, "disabling bridge window "
866		− "%pR to [bus %02x-%02x] (unused)\n", b_res,
867		− bus->secondary, bus->subordinate);
	889	+ "%pR to %pR (unused)\n", b_res,
	890	+ &bus->busn_res);
868	891	b_res->flags = 0;
869	892	return 1;
870	893	}
@@ -874,8 +897,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, · 3 unmodified lines
874	897	if (size1 > size0 && realloc_head) {
875	898	add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
876	899	dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
877		− "%pR to [bus %02x-%02x] add_size %llx\n", b_res,
878		− bus->secondary, bus->subordinate, (unsigned long long)size1-size0);
	900	+ "%pR to %pR add_size %llx\n", b_res,
	901	+ &bus->busn_res, (unsigned long long)size1-size0);
879	902	}
880	903	return 1;
881	904	}

drivers/pci/setup-res.c+72−53

@@ -30,6 +30,8 @@ · 29 unmodified lines
30	30	void pci_update_resource(struct pci_dev *dev, int resno)
31	31	{
32	32	struct pci_bus_region region;
	33	+ bool disable;
	34	+ u16 cmd;
33	35	u32 new, check, mask;
34	36	int reg;
35	37	enum pci_bar_type type;
@@ -67,6 +69,18 @@ void pci_update_resource(struct pci_dev *dev, int resno) · 31 unmodified lines
67	69	new \|= PCI_ROM_ADDRESS_ENABLE;
68	70	}
69	71
	72	+ /*
	73	+ * We can't update a 64-bit BAR atomically, so when possible,
	74	+ * disable decoding so that a half-updated BAR won't conflict
	75	+ * with another device.
	76	+ */
	77	+ disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	78	+ if (disable) {
	79	+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
	80	+ pci_write_config_word(dev, PCI_COMMAND,
	81	+ cmd & ~PCI_COMMAND_MEMORY);
	82	+ }
	83	+
70	84	pci_write_config_dword(dev, reg, new);
71	85	pci_read_config_dword(dev, reg, &check);
72	86
@@ -84,6 +98,10 @@ void pci_update_resource(struct pci_dev *dev, int resno) · 11 unmodified lines
84	98	"(high %#08x != %#08x)\n", resno, new, check);
85	99	}
86	100	}
	101	+
	102	+ if (disable)
	103	+ pci_write_config_word(dev, PCI_COMMAND, cmd);
	104	+
87	105	res->flags &= ~IORESOURCE_UNSET;
88	106	dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
89	107	resno, res, (unsigned long long)region.start,
@@ -127,33 +145,6 @@ void pci_disable_bridge_window(struct pci_dev *dev) · 37 unmodified lines
127	145	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
128	146	}
129	147
130		−static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
131		− int resno, resource_size_t size, resource_size_t align)
132		−{
133		− struct resource *res = dev->resource + resno;
134		− resource_size_t min;
135		− int ret;
136		−
137		− min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
138		−
139		− /* First, try exact prefetching match.. */
140		− ret = pci_bus_alloc_resource(bus, res, size, align, min,
141		− IORESOURCE_PREFETCH,
142		− pcibios_align_resource, dev);
143		−
144		− if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
145		− /*
146		− * That failed.
147		− *
148		− * But a prefetching area can handle a non-prefetching
149		− * window (it will just not perform as well).
150		− */
151		− ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
152		− pcibios_align_resource, dev);
153		− }
154		− return ret;
155		−}
156		−
157	148	/*
158	149	* Generic function that returns a value indicating that the device's
159	150	* original BIOS BAR address was not saved and so is not available for
@@ -206,7 +197,35 @@ static int pci_revert_fw_address(struct resource res, struct pci_dev dev, · 46 unmodified lines
206	197	return ret;
207	198	}
208	199
209		−static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
	200	+static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
	201	+ int resno, resource_size_t size, resource_size_t align)
	202	+{
	203	+ struct resource *res = dev->resource + resno;
	204	+ resource_size_t min;
	205	+ int ret;
	206	+
	207	+ min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
	208	+
	209	+ /* First, try exact prefetching match.. */
	210	+ ret = pci_bus_alloc_resource(bus, res, size, align, min,
	211	+ IORESOURCE_PREFETCH,
	212	+ pcibios_align_resource, dev);
	213	+
	214	+ if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
	215	+ /*
	216	+ * That failed.
	217	+ *
	218	+ * But a prefetching area can handle a non-prefetching
	219	+ * window (it will just not perform as well).
	220	+ */
	221	+ ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
	222	+ pcibios_align_resource, dev);
	223	+ }
	224	+ return ret;
	225	+}
	226	+
	227	+static int _pci_assign_resource(struct pci_dev *dev, int resno,
	228	+ resource_size_t size, resource_size_t min_align)
210	229	{
211	230	struct resource *res = dev->resource + resno;
212	231	struct pci_bus *bus;
@@ -238,31 +257,6 @@ static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resour · 25 unmodified lines
238	257	return ret;
239	258	}
240	259
241		−int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
242		− resource_size_t min_align)
243		−{
244		− struct resource *res = dev->resource + resno;
245		− resource_size_t new_size;
246		− int ret;
247		−
248		− if (!res->parent) {
249		− dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
250		− "\n", resno, res);
251		− return -EINVAL;
252		− }
253		−
254		− /* already aligned with min_align */
255		− new_size = resource_size(res) + addsize;
256		− ret = _pci_assign_resource(dev, resno, new_size, min_align);
257		− if (!ret) {
258		− res->flags &= ~IORESOURCE_STARTALIGN;
259		− dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
260		− if (resno < PCI_BRIDGE_RESOURCES)
261		− pci_update_resource(dev, resno);
262		− }
263		− return ret;
264		−}
265		−
266	260	int pci_assign_resource(struct pci_dev *dev, int resno)
267	261	{
268	262	struct resource *res = dev->resource + resno;
@@ -298,6 +292,31 @@ int pci_assign_resource(struct pci_dev *dev, int resno) · 29 unmodified lines
298	292	return ret;
299	293	}
300	294
	295	+int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
	296	+ resource_size_t min_align)
	297	+{
	298	+ struct resource *res = dev->resource + resno;
	299	+ resource_size_t new_size;
	300	+ int ret;
	301	+
	302	+ if (!res->parent) {
	303	+ dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
	304	+ "\n", resno, res);
	305	+ return -EINVAL;
	306	+ }
	307	+
	308	+ /* already aligned with min_align */
	309	+ new_size = resource_size(res) + addsize;
	310	+ ret = _pci_assign_resource(dev, resno, new_size, min_align);
	311	+ if (!ret) {
	312	+ res->flags &= ~IORESOURCE_STARTALIGN;
	313	+ dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
	314	+ if (resno < PCI_BRIDGE_RESOURCES)
	315	+ pci_update_resource(dev, resno);
	316	+ }
	317	+ return ret;
	318	+}
	319	+
301	320	int pci_enable_resources(struct pci_dev *dev, int mask)
302	321	{
303	322	u16 cmd, old_cmd;

drivers/pcmcia/cardbus.c+1−1

@@ -73,7 +73,7 @@ int __ref cb_alloc(struct pcmcia_socket *s) · 72 unmodified lines
73	73	s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
74	74	pci_fixup_cardbus(bus);
75	75
76		− max = bus->secondary;
	76	+ max = bus->busn_res.start;
77	77	for (pass = 0; pass < 2; pass++)
78	78	list_for_each_entry(dev, &bus->devices, bus_list)
79	79	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE \|\|

drivers/pcmcia/yenta_socket.c+13−13

@@ -1048,8 +1048,8 @@ static void yenta_config_init(struct yenta_socket *socket) · 1047 unmodified lines
1048	1048	config_writeb(socket, PCI_LATENCY_TIMER, 168);
1049	1049	config_writel(socket, PCI_PRIMARY_BUS,
1050	1050	(176 << 24) \| /* sec. latency timer */
1051		− (dev->subordinate->subordinate << 16) \| /* subordinate bus */
1052		− (dev->subordinate->secondary << 8) \| /* secondary bus */
	1051	+ ((unsigned int)dev->subordinate->busn_res.end << 16) \| /* subordinate bus */
	1052	+ ((unsigned int)dev->subordinate->busn_res.start << 8) \| /* secondary bus */
1053	1053	dev->subordinate->primary); /* primary bus */
1054	1054
1055	1055	/*
@@ -1086,14 +1086,14 @@ static void yenta_fixup_parent_bridge(struct pci_bus *cardbus_bridge) · 30 unmodified lines
1086	1086	struct pci_bus *bridge_to_fix = cardbus_bridge->parent;
1087	1087
1088	1088	/* Check bus numbers are already set up correctly: */
1089		− if (bridge_to_fix->subordinate >= cardbus_bridge->subordinate)
	1089	+ if (bridge_to_fix->busn_res.end >= cardbus_bridge->busn_res.end)
1090	1090	return; /* The subordinate number is ok, nothing to do */
1091	1091
1092	1092	if (!bridge_to_fix->parent)
1093	1093	return; /* Root bridges are ok */
1094	1094
1095	1095	/* stay within the limits of the bus range of the parent: */
1096		− upper_limit = bridge_to_fix->parent->subordinate;
	1096	+ upper_limit = bridge_to_fix->parent->busn_res.end;
1097	1097
1098	1098	/* check the bus ranges of all silbling bridges to prevent overlap */
1099	1099	list_for_each(tmp, &bridge_to_fix->parent->children) {
@@ -1104,36 +1104,36 @@ static void yenta_fixup_parent_bridge(struct pci_bus *cardbus_bridge) · 4 unmodified lines
1104	1104	* current upper limit, set the new upper limit to
1105	1105	* the bus number below the silbling's range:
1106	1106	*/
1107		− if (silbling->secondary > bridge_to_fix->subordinate
1108		− && silbling->secondary <= upper_limit)
1109		− upper_limit = silbling->secondary - 1;
	1107	+ if (silbling->busn_res.start > bridge_to_fix->busn_res.end
	1108	+ && silbling->busn_res.start <= upper_limit)
	1109	+ upper_limit = silbling->busn_res.start - 1;
1110	1110	}
1111	1111
1112	1112	/* Show that the wanted subordinate number is not possible: */
1113		− if (cardbus_bridge->subordinate > upper_limit)
	1113	+ if (cardbus_bridge->busn_res.end > upper_limit)
1114	1114	dev_printk(KERN_WARNING, &cardbus_bridge->dev,
1115	1115	"Upper limit for fixing this "
1116	1116	"bridge's parent bridge: #%02x\n", upper_limit);
1117	1117
1118	1118	/* If we have room to increase the bridge's subordinate number, */
1119		− if (bridge_to_fix->subordinate < upper_limit) {
	1119	+ if (bridge_to_fix->busn_res.end < upper_limit) {
1120	1120
1121	1121	/* use the highest number of the hidden bus, within limits */
1122	1122	unsigned char subordinate_to_assign =
1123		− min(cardbus_bridge->subordinate, upper_limit);
	1123	+ min_t(int, cardbus_bridge->busn_res.end, upper_limit);
1124	1124
1125	1125	dev_printk(KERN_INFO, &bridge_to_fix->dev,
1126	1126	"Raising subordinate bus# of parent "
1127	1127	"bus (#%02x) from #%02x to #%02x\n",
1128	1128	bridge_to_fix->number,
1129		− bridge_to_fix->subordinate, subordinate_to_assign);
	1129	+ (int)bridge_to_fix->busn_res.end, subordinate_to_assign);
1130	1130
1131	1131	/* Save the new subordinate in the bus struct of the bridge */
1132		− bridge_to_fix->subordinate = subordinate_to_assign;
	1132	+ bridge_to_fix->busn_res.end = subordinate_to_assign;
1133	1133
1134	1134	/* and update the PCI config space with the new subordinate */
1135	1135	pci_write_config_byte(bridge_to_fix->self,
1136		− PCI_SUBORDINATE_BUS, bridge_to_fix->subordinate);
	1136	+ PCI_SUBORDINATE_BUS, bridge_to_fix->busn_res.end);
1137	1137	}
1138	1138	}
1139	1139

drivers/pnp/pnpacpi/core.c+2−2

@@ -170,8 +170,8 @@ static int pnpacpi_suspend(struct pnp_dev *dev, pm_message_t state) · 169 unmodified lines
170	170	}
171	171
172	172	if (acpi_bus_power_manageable(handle)) {
173		− int power_state = acpi_pm_device_sleep_state(&dev->dev, NULL);
174		−
	173	+ int power_state = acpi_pm_device_sleep_state(&dev->dev, NULL,
	174	+ ACPI_STATE_D3);
175	175	if (power_state < 0)
176	176	power_state = (state.event == PM_EVENT_ON) ?
177	177	ACPI_STATE_D0 : ACPI_STATE_D3;

drivers/xen/xen-pciback/conf_space.c+3−3

@@ -124,7 +124,7 @@ static inline u32 merge_value(u32 val, u32 new_val, u32 new_val_mask, · 123 unmodified lines
124	124	return val;
125	125	}
126	126
127		−static int pcibios_err_to_errno(int err)
	127	+static int xen_pcibios_err_to_errno(int err)
128	128	{
129	129	switch (err) {
130	130	case PCIBIOS_SUCCESSFUL:
@@ -202,7 +202,7 @@ out: · 71 unmodified lines
202	202	pci_name(dev), size, offset, value);
203	203
204	204	*ret_val = value;
205		− return pcibios_err_to_errno(err);
	205	+ return xen_pcibios_err_to_errno(err);
206	206	}
207	207
208	208	int xen_pcibk_config_write(struct pci_dev *dev, int offset, int size, u32 value)
@@ -290,7 +290,7 @@ int xen_pcibk_config_write(struct pci_dev *dev, int offset, int size, u32 value) · 81 unmodified lines
290	290	}
291	291	}
292	292
293		− return pcibios_err_to_errno(err);
	293	+ return xen_pcibios_err_to_errno(err);
294	294	}
295	295
296	296	void xen_pcibk_config_free_dyn_fields(struct pci_dev *dev)

include/acpi/acnames.h+1−0

@@ -62,6 +62,7 @@ · 61 unmodified lines
62	62	#define METHOD_NAME__AEI "_AEI"
63	63	#define METHOD_NAME__PRW "_PRW"
64	64	#define METHOD_NAME__SRS "_SRS"
	65	+#define METHOD_NAME__CBA "_CBA"
65	66
66	67	/* Method names - these methods must appear at the namespace root */
67	68

include/acpi/acpi_bus.h+4−3

@@ -396,6 +396,7 @@ struct acpi_pci_root { · 395 unmodified lines
396	396
397	397	u32 osc_support_set; /* _OSC state of support bits */
398	398	u32 osc_control_set; /* _OSC state of control bits */
	399	+ phys_addr_t mcfg_addr;
399	400	};
400	401
401	402	/* helper */
@@ -409,13 +410,13 @@ int acpi_enable_wakeup_device_power(struct acpi_device *dev, int state); · 7 unmodified lines
409	410	int acpi_disable_wakeup_device_power(struct acpi_device *dev);
410	411
411	412	#ifdef CONFIG_PM
412		−int acpi_pm_device_sleep_state(struct device , int );
	413	+int acpi_pm_device_sleep_state(struct device , int , int);
413	414	#else
414		−static inline int acpi_pm_device_sleep_state(struct device d, int p)
	415	+static inline int acpi_pm_device_sleep_state(struct device d, int p, int m)
415	416	{
416	417	if (p)
417	418	*p = ACPI_STATE_D0;
418		− return ACPI_STATE_D3;
	419	+ return (m >= ACPI_STATE_D0 && m <= ACPI_STATE_D3) ? m : ACPI_STATE_D0;
419	420	}
420	421	#endif
421	422

include/linux/pci-acpi.h+1−0

@@ -17,6 +17,7 @@ extern acpi_status pci_acpi_remove_bus_pm_notifier(struct acpi_device *dev); · 16 unmodified lines
17	17	extern acpi_status pci_acpi_add_pm_notifier(struct acpi_device *dev,
18	18	struct pci_dev *pci_dev);
19	19	extern acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev);
	20	+extern phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle);
20	21
21	22	static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
22	23	{

include/linux/pci.h+72−10

@@ -132,9 +132,10 @@ static inline const char *pci_power_name(pci_power_t state) · 131 unmodified lines
132	132	return pci_power_names[1 + (int) state];
133	133	}
134	134
135		−#define PCI_PM_D2_DELAY 200
136		−#define PCI_PM_D3_WAIT 10
137		−#define PCI_PM_BUS_WAIT 50
	135	+#define PCI_PM_D2_DELAY 200
	136	+#define PCI_PM_D3_WAIT 10
	137	+#define PCI_PM_D3COLD_WAIT 100
	138	+#define PCI_PM_BUS_WAIT 50
138	139
139	140	/** The pci_channel state describes connectivity between the CPU and
140	141	* the pci device. If some PCI bus between here and the pci device
@@ -278,11 +279,18 @@ struct pci_dev { · 137 unmodified lines
278	279	unsigned int pme_poll:1; /* Poll device's PME status bit */
279	280	unsigned int d1_support:1; /* Low power state D1 is supported */
280	281	unsigned int d2_support:1; /* Low power state D2 is supported */
281		− unsigned int no_d1d2:1; /* Only allow D0 and D3 */
	282	+ unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
	283	+ unsigned int no_d3cold:1; /* D3cold is forbidden */
	284	+ unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
282	285	unsigned int mmio_always_on:1; /* disallow turning off io/mem
283	286	decoding during bar sizing */
284	287	unsigned int wakeup_prepared:1;
	288	+ unsigned int runtime_d3cold:1; /* whether go through runtime
	289	+ D3cold, not set for devices
	290	+ powered on/off by the
	291	+ corresponding bridge */
285	292	unsigned int d3_delay; /* D3->D0 transition time in ms */
	293	+ unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
286	294
287	295	#ifdef CONFIG_PCIEASPM
288	296	struct pcie_link_state link_state; / ASPM link state. */
@@ -324,6 +332,8 @@ struct pci_dev { · 35 unmodified lines
324	332	unsigned int is_hotplug_bridge:1;
325	333	unsigned int __aer_firmware_first_valid:1;
326	334	unsigned int __aer_firmware_first:1;
	335	+ unsigned int broken_intx_masking:1;
	336	+ unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
327	337	pci_dev_flags_t dev_flags;
328	338	atomic_t enable_cnt; /* pci_enable_device has been called */
329	339
@@ -368,6 +378,8 @@ static inline int pci_channel_offline(struct pci_dev *pdev) · 38 unmodified lines
368	378	return (pdev->error_state != pci_channel_io_normal);
369	379	}
370	380
	381	+extern struct resource busn_resource;
	382	+
371	383	struct pci_host_bridge_window {
372	384	struct list_head list;
373	385	struct resource res; / host bridge aperture (CPU address) */
@@ -419,6 +431,7 @@ struct pci_bus { · 45 unmodified lines
419	431	struct list_head slots; /* list of slots on this bus */
420	432	struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
421	433	struct list_head resources; /* address space routed to this bus */
	434	+ struct resource busn_res; /* bus numbers routed to this bus */
422	435
423	436	struct pci_ops ops; / configuration access functions */
424	437	void sysdata; / hook for sys-specific extension */
@@ -426,8 +439,6 @@ struct pci_bus { · 1 unmodified line
426	439
427	440	unsigned char number; /* bus number */
428	441	unsigned char primary; /* number of primary bridge */
429		− unsigned char secondary; /* number of secondary bridge */
430		− unsigned char subordinate; /* max number of subordinate buses */
431	442	unsigned char max_bus_speed; /* enum pci_bus_speed */
432	443	unsigned char cur_bus_speed; /* enum pci_bus_speed */
433	444
@@ -474,6 +485,32 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; · 40 unmodified lines
474	485	#define PCIBIOS_SET_FAILED 0x88
475	486	#define PCIBIOS_BUFFER_TOO_SMALL 0x89
476	487
	488	+/*
	489	+ * Translate above to generic errno for passing back through non-pci.
	490	+ */
	491	+static inline int pcibios_err_to_errno(int err)
	492	+{
	493	+ if (err <= PCIBIOS_SUCCESSFUL)
	494	+ return err; /* Assume already errno */
	495	+
	496	+ switch (err) {
	497	+ case PCIBIOS_FUNC_NOT_SUPPORTED:
	498	+ return -ENOENT;
	499	+ case PCIBIOS_BAD_VENDOR_ID:
	500	+ return -EINVAL;
	501	+ case PCIBIOS_DEVICE_NOT_FOUND:
	502	+ return -ENODEV;
	503	+ case PCIBIOS_BAD_REGISTER_NUMBER:
	504	+ return -EFAULT;
	505	+ case PCIBIOS_SET_FAILED:
	506	+ return -EIO;
	507	+ case PCIBIOS_BUFFER_TOO_SMALL:
	508	+ return -ENOSPC;
	509	+ }
	510	+
	511	+ return -ENOTTY;
	512	+}
	513	+
477	514	/* Low-level architecture-dependent routines */
478	515
479	516	struct pci_ops {
@@ -642,6 +679,7 @@ extern int no_pci_devices(void); · 162 unmodified lines
642	679
643	680	void pcibios_fixup_bus(struct pci_bus *);
644	681	int __must_check pcibios_enable_device(struct pci_dev *, int mask);
	682	+/* Architecture specific versions may override this (weak) */
645	683	char pcibios_setup(char str);
646	684
647	685	/* Used only when drivers/pci/setup.c is used */
@@ -668,6 +706,9 @@ struct pci_bus pci_scan_bus(int bus, struct pci_ops ops, void *sysdata); · 20 unmodified lines
668	706	struct pci_bus pci_create_root_bus(struct device parent, int bus,
669	707	struct pci_ops ops, void sysdata,
670	708	struct list_head *resources);
	709	+int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
	710	+int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
	711	+void pci_bus_release_busn_res(struct pci_bus *b);
671	712	struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
672	713	struct pci_ops ops, void sysdata,
673	714	struct list_head *resources);
@@ -714,8 +755,6 @@ enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); · 40 unmodified lines
714	755	int pci_find_capability(struct pci_dev *dev, int cap);
715	756	int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
716	757	int pci_find_ext_capability(struct pci_dev *dev, int cap);
717		−int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
718		− int cap);
719	758	int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
720	759	int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
721	760	struct pci_bus pci_find_next_bus(const struct pci_bus from);
@@ -777,6 +816,14 @@ static inline int pci_write_config_dword(const struct pci_dev *dev, int where, · 55 unmodified lines
777	816	return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
778	817	}
779	818
	819	+/* user-space driven config access */
	820	+int pci_user_read_config_byte(struct pci_dev dev, int where, u8 val);
	821	+int pci_user_read_config_word(struct pci_dev dev, int where, u16 val);
	822	+int pci_user_read_config_dword(struct pci_dev dev, int where, u32 val);
	823	+int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
	824	+int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
	825	+int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
	826	+
780	827	int __must_check pci_enable_device(struct pci_dev *dev);
781	828	int __must_check pci_enable_device_io(struct pci_dev *dev);
782	829	int __must_check pci_enable_device_mem(struct pci_dev *dev);
@@ -875,7 +922,6 @@ enum pci_obff_signal_type { · 92 unmodified lines
875	922	int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
876	923	void pci_disable_obff(struct pci_dev *dev);
877	924
878		−bool pci_ltr_supported(struct pci_dev *dev);
879	925	int pci_enable_ltr(struct pci_dev *dev);
880	926	void pci_disable_ltr(struct pci_dev *dev);
881	927	int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
@@ -1332,6 +1378,9 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, · 450 unmodified lines
1332	1378	static inline int pci_domain_nr(struct pci_bus *bus)
1333	1379	{ return 0; }
1334	1380
	1381	+static inline struct pci_dev pci_dev_get(struct pci_dev dev)
	1382	+{ return NULL; }
	1383	+
1335	1384	#define dev_is_pci(d) (false)
1336	1385	#define dev_is_pf(d) (false)
1337	1386	#define dev_num_vf(d) (0)
@@ -1486,9 +1535,20 @@ enum pci_fixup_pass { · 148 unmodified lines
1486	1535
1487	1536	#ifdef CONFIG_PCI_QUIRKS
1488	1537	void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
	1538	+struct pci_dev pci_get_dma_source(struct pci_dev dev);
	1539	+int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1489	1540	#else
1490	1541	static inline void pci_fixup_device(enum pci_fixup_pass pass,
1491	1542	struct pci_dev *dev) {}
	1543	+static inline struct pci_dev pci_get_dma_source(struct pci_dev dev)
	1544	+{
	1545	+ return pci_dev_get(dev);
	1546	+}
	1547	+static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
	1548	+ u16 acs_flags)
	1549	+{
	1550	+ return -ENOTTY;
	1551	+}
1492	1552	#endif
1493	1553
1494	1554	void __iomem pcim_iomap(struct pci_dev pdev, int bar, unsigned long maxlen);
@@ -1591,7 +1651,9 @@ static inline bool pci_is_pcie(struct pci_dev *dev) · 96 unmodified lines
1591	1651	}
1592	1652
1593	1653	void pci_request_acs(void);
1594		−
	1654	+bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
	1655	+bool pci_acs_path_enabled(struct pci_dev *start,
	1656	+ struct pci_dev *end, u16 acs_flags);
1595	1657
1596	1658	#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1597	1659	#define PCI_VPD_LRDT_ID(x) (x \| PCI_VPD_LRDT)

include/linux/pci_regs.h+109−13

@@ -26,6 +26,7 @@ · 25 unmodified lines
26	26	* Under PCI, each device has 256 bytes of configuration address space,
27	27	* of which the first 64 bytes are standardized as follows:
28	28	*/
	29	+#define PCI_STD_HEADER_SIZEOF 64
29	30	#define PCI_VENDOR_ID 0x00 /* 16 bits */
30	31	#define PCI_DEVICE_ID 0x02 /* 16 bits */
31	32	#define PCI_COMMAND 0x04 /* 16 bits */
@@ -125,7 +126,8 @@ · 93 unmodified lines
125	126	#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
126	127	#define PCI_IO_RANGE_TYPE_16 0x00
127	128	#define PCI_IO_RANGE_TYPE_32 0x01
128		−#define PCI_IO_RANGE_MASK (~0x0fUL)
	129	+#define PCI_IO_RANGE_MASK (~0x0fUL) /* Standard 4K I/O windows */
	130	+#define PCI_IO_1K_RANGE_MASK (~0x03UL) /* Intel 1K I/O windows */
129	131	#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
130	132	#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
131	133	#define PCI_MEMORY_LIMIT 0x22
@@ -209,9 +211,12 @@ · 77 unmodified lines
209	211	#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
210	212	#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
211	213	#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
	214	+#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
212	215	#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
213	216	#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
	217	+#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
214	218	#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
	219	+#define PCI_CAP_ID_MAX PCI_CAP_ID_AF
215	220	#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
216	221	#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
217	222	#define PCI_CAP_SIZEOF 4
@@ -276,6 +281,7 @@ · 58 unmodified lines
276	281	#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
277	282	#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
278	283	#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
	284	+#define PCI_CAP_VPD_SIZEOF 8
279	285
280	286	/* Slot Identification */
281	287
@@ -297,8 +303,10 @@ · 15 unmodified lines
297	303	#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
298	304	#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
299	305	#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
	306	+#define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */
300	307	#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
301	308	#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
	309	+#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
302	310
303	311	/* MSI-X registers */
304	312	#define PCI_MSIX_FLAGS 2
@@ -308,6 +316,7 @@ · 3 unmodified lines
308	316	#define PCI_MSIX_TABLE 4
309	317	#define PCI_MSIX_PBA 8
310	318	#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
	319	+#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
311	320
312	321	/* MSI-X entry's format */
313	322	#define PCI_MSIX_ENTRY_SIZE 16
@@ -338,6 +347,7 @@ · 24 unmodified lines
338	347	#define PCI_AF_CTRL_FLR 0x01
339	348	#define PCI_AF_STATUS 5
340	349	#define PCI_AF_STATUS_TP 0x01
	350	+#define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */
341	351
342	352	/* PCI-X registers */
343	353
@@ -374,6 +384,10 @@ · 30 unmodified lines
374	384	#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
375	385	#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
376	386	#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
	387	+#define PCI_X_ECC_CSR 8 /* ECC control and status */
	388	+#define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */
	389	+#define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */
	390	+#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */
377	391
378	392	/* PCI Bridge Subsystem ID registers */
379	393
@@ -462,6 +476,7 @@ · 82 unmodified lines
462	476	#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
463	477	#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
464	478	#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
	479	+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */
465	480	#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
466	481	#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */
467	482	#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */
@@ -507,6 +522,12 @@ · 39 unmodified lines
507	522	#define PCI_EXP_RTSTA 32 /* Root Status */
508	523	#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
509	524	#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
	525	+/*
	526	+ * Note that the following PCI Express 'Capability Structure' registers
	527	+ * were introduced with 'Capability Version' 0x2 (v2). These registers
	528	+ * do not exist on devices with Capability Version 1. Use pci_pcie_cap2()
	529	+ * to use these fields safely.
	530	+ */
510	531	#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
511	532	#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
512	533	#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
@@ -521,6 +542,7 @@ · 8 unmodified lines
521	542	#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
522	543	#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
523	544	#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
	545	+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */
524	546	#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
525	547	#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
526	548
@@ -529,23 +551,43 @@ · 2 unmodified lines
529	551	#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
530	552	#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
531	553
532		−#define PCI_EXT_CAP_ID_ERR 1
533		−#define PCI_EXT_CAP_ID_VC 2
534		−#define PCI_EXT_CAP_ID_DSN 3
535		−#define PCI_EXT_CAP_ID_PWR 4
536		−#define PCI_EXT_CAP_ID_VNDR 11
537		−#define PCI_EXT_CAP_ID_ACS 13
538		−#define PCI_EXT_CAP_ID_ARI 14
539		−#define PCI_EXT_CAP_ID_ATS 15
540		−#define PCI_EXT_CAP_ID_SRIOV 16
541		−#define PCI_EXT_CAP_ID_PRI 19
542		−#define PCI_EXT_CAP_ID_LTR 24
543		−#define PCI_EXT_CAP_ID_PASID 27
	554	+#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
	555	+#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
	556	+#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
	557	+#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
	558	+#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
	559	+#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
	560	+#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
	561	+#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
	562	+#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
	563	+#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
	564	+#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor Specific */
	565	+#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
	566	+#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
	567	+#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
	568	+#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
	569	+#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
	570	+#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
	571	+#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
	572	+#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
	573	+#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* reserved for AMD */
	574	+#define PCI_EXT_CAP_ID_REBAR 0x15 /* resizable BAR */
	575	+#define PCI_EXT_CAP_ID_DPA 0x16 /* dynamic power alloc */
	576	+#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH request */
	577	+#define PCI_EXT_CAP_ID_LTR 0x18 /* latency tolerance reporting */
	578	+#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe */
	579	+#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
	580	+#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
	581	+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID
	582	+
	583	+#define PCI_EXT_CAP_DSN_SIZEOF 12
	584	+#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
544	585
545	586	/* Advanced Error Reporting */
546	587	#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
547	588	#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
548	589	#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
	590	+#define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */
549	591	#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
550	592	#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
551	593	#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
@@ -555,6 +597,11 @@ · 3 unmodified lines
555	597	#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
556	598	#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
557	599	#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
	600	+#define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */
	601	+#define PCI_ERR_UNC_INTN 0x00400000 /* internal error */
	602	+#define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */
	603	+#define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */
	604	+#define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */
558	605	#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
559	606	/* Same bits as above */
560	607	#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
@@ -565,6 +612,9 @@ · 4 unmodified lines
565	612	#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
566	613	#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
567	614	#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
	615	+#define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
	616	+#define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */
	617	+#define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */
568	618	#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
569	619	/* Same bits as above */
570	620	#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
@@ -596,12 +646,18 @@ · 25 unmodified lines
596	646
597	647	/* Virtual Channel */
598	648	#define PCI_VC_PORT_REG1 4
	649	+#define PCI_VC_REG1_EVCC 0x7 /* extended vc count */
599	650	#define PCI_VC_PORT_REG2 8
	651	+#define PCI_VC_REG2_32_PHASE 0x2
	652	+#define PCI_VC_REG2_64_PHASE 0x4
	653	+#define PCI_VC_REG2_128_PHASE 0x8
600	654	#define PCI_VC_PORT_CTRL 12
601	655	#define PCI_VC_PORT_STATUS 14
602	656	#define PCI_VC_RES_CAP 16
603	657	#define PCI_VC_RES_CTRL 20
604	658	#define PCI_VC_RES_STATUS 26
	659	+#define PCI_CAP_VC_BASE_SIZEOF 0x10
	660	+#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C
605	661
606	662	/* Power Budgeting */
607	663	#define PCI_PWR_DSR 4 /* Data Select Register */
@@ -614,6 +670,7 @@ · 6 unmodified lines
614	670	#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
615	671	#define PCI_PWR_CAP 12 /* Capability */
616	672	#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
	673	+#define PCI_EXT_CAP_PWR_SIZEOF 16
617	674
618	675	/*
619	676	* Hypertransport sub capability types
@@ -646,6 +703,8 @@ · 26 unmodified lines
646	703	#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */
647	704	#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */
648	705	#define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */
	706	+#define HT_CAP_SIZEOF_LONG 28 /* slave & primary */
	707	+#define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */
649	708
650	709	/* Alternative Routing-ID Interpretation */
651	710	#define PCI_ARI_CAP 0x04 /* ARI Capability Register */
@@ -656,6 +715,7 @@ · 4 unmodified lines
656	715	#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
657	716	#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
658	717	#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
	718	+#define PCI_EXT_CAP_ARI_SIZEOF 8
659	719
660	720	/* Address Translation Service */
661	721	#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
@@ -665,6 +725,7 @@ · 3 unmodified lines
665	725	#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
666	726	#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
667	727	#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
	728	+#define PCI_EXT_CAP_ATS_SIZEOF 8
668	729
669	730	/* Page Request Interface */
670	731	#define PCI_PRI_CTRL 0x04 /* PRI control register */
@@ -676,6 +737,7 @@ · 5 unmodified lines
676	737	#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
677	738	#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
678	739	#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
	740	+#define PCI_EXT_CAP_PRI_SIZEOF 16
679	741
680	742	/* PASID capability */
681	743	#define PCI_PASID_CAP 0x04 /* PASID feature register */
@@ -685,6 +747,7 @@ · 3 unmodified lines
685	747	#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */
686	748	#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */
687	749	#define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */
	750	+#define PCI_EXT_CAP_PASID_SIZEOF 8
688	751
689	752	/* Single Root I/O Virtualization */
690	753	#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
@@ -716,12 +779,14 @@ · 25 unmodified lines
716	779	#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */
717	780	#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
718	781	#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
	782	+#define PCI_EXT_CAP_SRIOV_SIZEOF 64
719	783
720	784	#define PCI_LTR_MAX_SNOOP_LAT 0x4
721	785	#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
722	786	#define PCI_LTR_VALUE_MASK 0x000003ff
723	787	#define PCI_LTR_SCALE_MASK 0x00001c00
724	788	#define PCI_LTR_SCALE_SHIFT 10
	789	+#define PCI_EXT_CAP_LTR_SIZEOF 8
725	790
726	791	/* Access Control Service */
727	792	#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
@@ -732,7 +797,38 @@ · 4 unmodified lines
732	797	#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
733	798	#define PCI_ACS_EC 0x20 /* P2P Egress Control */
734	799	#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
	800	+#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
735	801	#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
736	802	#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
737	803
	804	+#define PCI_VSEC_HDR 4 /* extended cap - vendor specific */
	805	+#define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */
	806	+
	807	+/* sata capability */
	808	+#define PCI_SATA_REGS 4 /* SATA REGs specifier */
	809	+#define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
	810	+#define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */
	811	+#define PCI_SATA_SIZEOF_SHORT 8
	812	+#define PCI_SATA_SIZEOF_LONG 16
	813	+
	814	+/* resizable BARs */
	815	+#define PCI_REBAR_CTRL 8 /* control register */
	816	+#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */
	817	+#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */
	818	+
	819	+/* dynamic power allocation */
	820	+#define PCI_DPA_CAP 4 /* capability register */
	821	+#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
	822	+#define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */
	823	+
	824	+/* TPH Requester */
	825	+#define PCI_TPH_CAP 4 /* capability register */
	826	+#define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */
	827	+#define PCI_TPH_LOC_NONE 0x000 /* no location */
	828	+#define PCI_TPH_LOC_CAP 0x200 /* in capability */
	829	+#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
	830	+#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */
	831	+#define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */
	832	+#define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */
	833	+
738	834	#endif /* LINUX_PCI_REGS_H */

include/linux/sfi_acpi.h+2−2

@@ -66,7 +66,7 @@ extern int sfi_acpi_table_parse(char signature, char oem_id, · 65 unmodified lines
66	66	char *oem_table_id,
67	67	int (handler)(struct acpi_table_header ));
68	68
69		−static inline int acpi_sfi_table_parse(char *signature,
	69	+static inline int __init acpi_sfi_table_parse(char *signature,
70	70	int (handler)(struct acpi_table_header ))
71	71	{
72	72	if (!acpi_table_parse(signature, handler))
@@ -83,7 +83,7 @@ static inline int sfi_acpi_table_parse(char signature, char oem_id, · 10 unmodified lines
83	83	return -1;
84	84	}
85	85
86		−static inline int acpi_sfi_table_parse(char *signature,
	86	+static inline int __init acpi_sfi_table_parse(char *signature,
87	87	int (handler)(struct acpi_table_header ))
88	88	{
89	89	return acpi_table_parse(signature, handler);

kernel/resource.c+8−5

@@ -722,14 +722,12 @@ int adjust_resource(struct resource *res, resource_size_t start, resource_size_t · 721 unmodified lines
722	722
723	723	write_lock(&resource_lock);
724	724
	725	+ if (!parent)
	726	+ goto skip;
	727	+
725	728	if ((start < parent->start) \|\| (end > parent->end))
726	729	goto out;
727	730
728		− for (tmp = res->child; tmp; tmp = tmp->sibling) {
729		− if ((tmp->start < start) \|\| (tmp->end > end))
730		− goto out;
731		− }
732		−
733	731	if (res->sibling && (res->sibling->start <= end))
734	732	goto out;
735	733
@@ -741,6 +739,11 @@ int adjust_resource(struct resource *res, resource_size_t start, resource_size_t · 5 unmodified lines
741	739	goto out;
742	740	}
743	741
	742	+skip:
	743	+ for (tmp = res->child; tmp; tmp = tmp->sibling)
	744	+ if ((tmp->start < start) \|\| (tmp->end > end))
	745	+ goto out;
	746	+
744	747	res->start = start;
745	748	res->end = end;
746	749	result = 0;

scripts/mod/modpost.c+11−0

@@ -865,6 +865,11 @@ static void check_section(const char modname, struct elf_info elf, · 864 unmodified lines
865	865	#define ALL_EXIT_TEXT_SECTIONS \
866	866	".exit.text$", ".devexit.text$", ".cpuexit.text$", ".memexit.text$"
867	867
	868	+#define ALL_PCI_INIT_SECTIONS \
	869	+ ".pci_fixup_early$", ".pci_fixup_header$", ".pci_fixup_final$", \
	870	+ ".pci_fixup_enable$", ".pci_fixup_resume$", \
	871	+ ".pci_fixup_resume_early$", ".pci_fixup_suspend$"
	872	+
868	873	#define ALL_XXXINIT_SECTIONS DEV_INIT_SECTIONS, CPU_INIT_SECTIONS, \
869	874	MEM_INIT_SECTIONS
870	875	#define ALL_XXXEXIT_SECTIONS DEV_EXIT_SECTIONS, CPU_EXIT_SECTIONS, \
@@ -1027,6 +1032,12 @@ const struct sectioncheck sectioncheck[] = { · 156 unmodified lines
1027	1032	.mismatch = ANY_EXIT_TO_ANY_INIT,
1028	1033	.symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL },
1029	1034	},
	1035	+{
	1036	+ .fromsec = { ALL_PCI_INIT_SECTIONS, NULL },
	1037	+ .tosec = { INIT_SECTIONS, NULL },
	1038	+ .mismatch = ANY_INIT_TO_ANY_EXIT,
	1039	+ .symbol_white_list = { NULL },
	1040	+},
1030	1041	/* Do not export init/exit functions or data */
1031	1042	{
1032	1043	.fromsec = { "__ksymtab*", NULL },

Merge tag 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

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