Merge tag 'drm-next-2025-12-03' of https://gitlab.freedesktop.org/drm/kernel

Pull drm updates from Dave Airlie: "There was a rather late merge of a new color pipeline feature, that some userspace projects are blocked on, and has seen a lot of work in amdgpu. This should have seen some time in -next. There is additional support for this for Intel, that if it arrives in the next day or two I'll pass it on in another pull request and you can decide if you want to take it. Highlights: - Arm Ethos NPU accelerator driver - new DRM color pipeline support - amdgpu will now run discrete SI/CIK cards instead of radeon, which enables vulkan support in userspace - msm gets gen8 gpu support - initial Xe3P support in xe Full detail summary: New driver: - Arm Ethos-U65/U85 accel driver Core: - support the drm color pipeline in vkms/amdgfx - add support for drm colorop pipeline - add COLOR PIPELINE plane property - add DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE - throttle dirty worker with vblank - use drm_for_each_bridge_in_chain_scoped in drm's bridge code - Ensure drm_client_modeset tests are enabled in UML - add simulated vblank interrupt - use in drivers - dumb buffer sizing helper - move freeing of drm client memory to driver - crtc sharpness strength property - stop using system_wq in scheduler/drivers - support emergency restore in drm-client Rust: - make slice::as_flattened usable on all supported rustc - add FromBytes::from_bytes_prefix() method - remove redundant device ptr from Rust GEM object - Change how AlwaysRefCounted is implemented for GEM objects gpuvm: - Add deferred vm_bo cleanup to GPUVM (for rust) atomic: - cleanup and improve state handling interfaces buddy: - optimize block management dma-buf: - heaps: Create heap per CMA reserved location - improve userspace documentation dp: - add POST_LT_ADJ_REQ training sequence - DPCD dSC quirk for synaptics panamera devices - helpers to query branch DSC max throughput ttm: - Rename ttm_bo_put to ttm_bo_fini - allow page protection flags on risc-v - rework pipelined eviction fence handling amdgpu: - enable amdgpu by default for SI/CI dGPUs - enable DC by default on SI - refactor CIK/SI enablement - add ABM KMS property - Re-enable DM idle optimizations - DC Analog encoders support - Powerplay fixes for fiji/iceland - Enable DC on bonaire by default - HMM cleanup - Add new RAS framework - DML2.1 updates - YCbCr420 fixes - DC FP fixes - DMUB fixes - LTTPR fixes - DTBCLK fixes - DMU cursor offload handling - Userq validation improvements - Unify shutdown callback handling - Suspend improvements - Power limit code cleanup - SR-IOV fixes - AUX backlight fixes - DCN 3.5 fixes - HDMI compliance fixes - DCN 4.0.1 cursor updates - DCN interrupt fix - DC KMS full update improvements - Add additional HDCP traces - DCN 3.2 fixes - DP MST fixes - Add support for new SR-IOV mailbox interface - UQ reset support - HDP flush rework - VCE1 support amdkfd: - HMM cleanups - Relax checks on save area overallocations - Fix GPU mappings after prefetch radeon: - refactor CIK/SI enablement xe: - Initial Xe3P support - panic support on VRAM for display - fix stolen size check - Loosen used tracking restriction - New SR-IOV debugfs structure and debugfs updates - Hide the GPU madvise flag behind a VM_BIND flag - Always expose VRAM provisioning data on discrete GPUs - Allow VRAM mappings for userptr when used with SVM - Allow pinning of p2p dma-buf - Use per-tile debugfs where appropriate - Add documentation for Execution Queues - PF improvements - VF migration recovery redesign work - User / Kernel VRAM partitioning - Update Tile-based messages - Allow configfs to disable specific GT types - VF provisioning and migration improvements - use SVM range helpers in PT layer - Initial CRI support - access VF registers using dedicated MMIO view - limit number of jobs per exec queue - add sriov_admin sysfs tree - more crescent island specific support - debugfs residency counter - SRIOV migration work - runtime registers for GFX 35 i915: - add initial Xe3p_LPD display version 35 support - Enable LNL+ content adaptive sharpness filter - Use optimized VRR guardband - Enable Xe3p LT PHY - enable FBC support for Xe3p_LPD display - add display 30.02 firmware support - refactor SKL+ watermark latency setup - refactor fbdev handling - call i915/xe runtime PM via function pointers - refactor i915/xe stolen memory/display interfaces - use display version instead of gfx version in display code - extend i915_display_info with Type-C port details - lots of display cleanups/refactorings - set O_LARGEFILE in __create_shmem - skuip guc communication warning on reset - fix time conversions - defeature DRRS on LNL+ - refactor intel_frontbuffer split between i915/xe/display - convert inteL_rom interfaces to struct drm_device - unify display register polling interfaces - aovid lock inversion when pinning to GGTT on CHV/BXT+VTD panel: - Add KD116N3730A08/A12, chromebook mt8189 - JT101TM023, LQ079L1SX01, - GLD070WX3-SL01 MIPI DSI - Samsung LTL106AL0, Samsung LTL106AL01 - Raystar RFF500F-AWH-DNN - Winstar WF70A8SYJHLNGA - Wanchanglong w552946aaa - Samsung SOFEF00 - Lenovo X13s panel - ilitek-ili9881c - add rpi 5" support - visionx-rm69299 - add backlight support - edp - support AUI B116XAN02.0 bridge: - improve ref counting - ti-sn65dsi86 - add support for DP mode with HPD - synopsis: support CEC, init timer with correct freq - ASL CS5263 DP-to-HDMI bridge support nova-core: - introduce bitfield! macro - introduce safe integer converters - GSP inits to fully booted state on Ampere - Use more future-proof register for GPU identification nova-drm: - select NOVA_CORE - 64-bit only nouveau: - improve reclocking on tegra 186+ - add large page and compression support msm: - GPU: - Gen8 support: A840 (Kaanapali) and X2-85 (Glymur) - A612 support - MDSS: - Added support for Glymur and QCS8300 platforms - DPU: - Enabled Quad-Pipe support, unlocking higher resolutions support - Added support for Glymur platform - Documented DPU on QCS8300 platform as supported - DisplayPort: - Added support for Glymur platform - Added support lame remapping inside DP block - Documented DisplayPort controller on QCS8300 and SM6150/QCS615 as supported tegra: - NVJPG driver panfrost: - display JM contexts over debugfs - export JM contexts to userspace - improve error and job handling panthor: - support custom ASN_HASH for mt8196 - support mali-G1 GPU - flush shmem write before mapping buffers uncached - make timeout per-queue instead of per-job mediatek: - MT8195/88 HDMIv2/DDCv2 support rockchip: - dsi: add support for RK3368 amdxdna: - enhance runtime PM - last hardware error reading uapi - support firmware debug output - add resource and telemetry data uapi - preemption support imx: - add driver for HDMI TX Parallel audio interface ivpu: - add support for user-managed preemption buffer - add userptr support - update JSM firware API to 3.33.0 - add better alloc/free warnings - fix page fault in unbind all bos - rework bind/unbind of imported buffers - enable MCA ECC signalling - split fw runtime and global memory buffers - add fdinfo memory statistics tidss: - convert to drm logging - logging cleanup ast: - refactor generation init paths - add per chip generation detect_tx_chip - set quirks for each chip model atmel-hlcdc: - set LCDC_ATTRE register in plane disable - set correct values for plane scaler solomon: - use drm helper for get_modes and move_valid sitronix: - fix output position when clearing screens qaic: - support dma-buf exports - support new firmware's READ_DATA implementation - sahara AIC200 image table update - add sysfs support - add coredump support - add uevents support - PM support sun4i: - layer refactors to decouple plane from output - improve DE33 support vc4: - switch to generic CEC helpers komeda: - use drm_ logging functions vkms: - configfs support for display configuration vgem: - fix fence timer deadlock etnaviv: - add HWDB entry for GC8000 Nano Ultra VIP r6205" * tag 'drm-next-2025-12-03' of https://gitlab.freedesktop.org/drm/kernel: (1869 commits) Revert "drm/amd: Skip power ungate during suspend for VPE" drm/amdgpu: use common defines for HUB faults drm/amdgpu/gmc12: add amdgpu_vm_handle_fault() handling drm/amdgpu/gmc11: add amdgpu_vm_handle_fault() handling drm/amdgpu: use static ids for ACP platform devs drm/amdgpu/sdma6: Update SDMA 6.0.3 FW version to include UMQ protected-fence fix drm/amdgpu: Forward VMID reservation errors drm/amdgpu/gmc8: Delegate VM faults to soft IRQ handler ring drm/amdgpu/gmc7: Delegate VM faults to soft IRQ handler ring drm/amdgpu/gmc6: Delegate VM faults to soft IRQ handler ring drm/amdgpu/gmc6: Cache VM fault info drm/amdgpu/gmc6: Don't print MC client as it's unknown drm/amdgpu/cz_ih: Enable soft IRQ handler ring drm/amdgpu/tonga_ih: Enable soft IRQ handler ring drm/amdgpu/iceland_ih: Enable soft IRQ handler ring drm/amdgpu/cik_ih: Enable soft IRQ handler ring drm/amdgpu/si_ih: Enable soft IRQ handler ring drm/amd/display: fix typo in display_mode_core_structs.h drm/amd/display: fix Smart Power OLED not working after S4 drm/amd/display: Move RGB-type check for audio sync to DCE HW sequence ...

Linus Torvalds committed 11 months ago

Commit 6dfafbd2 parents 94e244d 06926021799 files · +94407 −21674Browse files

Showing the changes to include/uapi (8 of 1799 files). Show all

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8 files

include/uapi/drm/amdgpu_drm.h +0 −9
include/uapi/drm/amdxdna_accel.h +61 −0
include/uapi/drm/drm.h +15 −0
include/uapi/drm/drm_mode.h +183 −1
include/uapi/drm/ethosu_accel.h +261 −0
include/uapi/drm/ivpu_accel.h +63 −0
include/uapi/drm/panfrost_drm.h +123 −27
include/uapi/drm/xe_drm.h +5 −1

include/uapi/drm/amdgpu_drm.h+0−9

@@ -1656,15 +1656,6 @@ struct drm_amdgpu_info_uq_metadata { · 1655 unmodified lines
1656	1656	#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
1657	1657	#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
1658	1658
1659		−/* FIXME wrong namespace! */
1660		−struct drm_color_ctm_3x4 {
1661		− /*
1662		− * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude
1663		− * (not two's complement!) format.
1664		− */
1665		− __u64 matrix[12];
1666		−};
1667		−
1668	1659	#if defined(__cplusplus)
1669	1660	}
1670	1661	#endif

include/uapi/drm/amdxdna_accel.h+61−0

@@ -442,6 +442,52 @@ enum amdxdna_drm_get_param { · 441 unmodified lines
442	442	DRM_AMDXDNA_QUERY_HW_CONTEXTS,
443	443	DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8,
444	444	DRM_AMDXDNA_GET_POWER_MODE,
	445	+ DRM_AMDXDNA_QUERY_TELEMETRY,
	446	+ DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE,
	447	+ DRM_AMDXDNA_QUERY_RESOURCE_INFO,
	448	+ DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE,
	449	+};
	450	+
	451	+/**
	452	+ * struct amdxdna_drm_get_resource_info - Get resource information
	453	+ */
	454	+struct amdxdna_drm_get_resource_info {
	455	+ /** @npu_clk_max: max H-Clocks */
	456	+ __u64 npu_clk_max;
	457	+ /** @npu_tops_max: max TOPs */
	458	+ __u64 npu_tops_max;
	459	+ /** @npu_task_max: max number of tasks */
	460	+ __u64 npu_task_max;
	461	+ /** @npu_tops_curr: current TOPs */
	462	+ __u64 npu_tops_curr;
	463	+ /** @npu_task_curr: current number of tasks */
	464	+ __u64 npu_task_curr;
	465	+};
	466	+
	467	+/**
	468	+ * struct amdxdna_drm_attribute_state - State of an attribute
	469	+ */
	470	+struct amdxdna_drm_attribute_state {
	471	+ /** @state: enabled or disabled */
	472	+ __u8 state;
	473	+ /** @pad: MBZ */
	474	+ __u8 pad[7];
	475	+};
	476	+
	477	+/**
	478	+ * struct amdxdna_drm_query_telemetry_header - Telemetry data header
	479	+ */
	480	+struct amdxdna_drm_query_telemetry_header {
	481	+ /** @major: Firmware telemetry interface major version number */
	482	+ __u32 major;
	483	+ /** @minor: Firmware telemetry interface minor version number */
	484	+ __u32 minor;
	485	+ /** @type: Telemetry query type */
	486	+ __u32 type;
	487	+ /** @map_num_elements: Total number of elements in the map table */
	488	+ __u32 map_num_elements;
	489	+ /** @map: Element map */
	490	+ __u32 map[];
445	491	};
446	492
447	493	/**
@@ -523,7 +569,20 @@ struct amdxdna_drm_hwctx_entry { · 75 unmodified lines
523	569	__u32 pad;
524	570	};
525	571
	572	+/**
	573	+ * struct amdxdna_async_error - XDNA async error structure
	574	+ */
	575	+struct amdxdna_async_error {
	576	+ /** @err_code: Error code. */
	577	+ __u64 err_code;
	578	+ /** @ts_us: Timestamp. */
	579	+ __u64 ts_us;
	580	+ /** @ex_err_code: Extra error code */
	581	+ __u64 ex_err_code;
	582	+};
	583	+
526	584	#define DRM_AMDXDNA_HW_CONTEXT_ALL 0
	585	+#define DRM_AMDXDNA_HW_LAST_ASYNC_ERR 2
527	586
528	587	/**
529	588	* struct amdxdna_drm_get_array - Get information array.
@@ -566,6 +625,8 @@ enum amdxdna_drm_set_param { · 36 unmodified lines
566	625	DRM_AMDXDNA_SET_POWER_MODE,
567	626	DRM_AMDXDNA_WRITE_AIE_MEM,
568	627	DRM_AMDXDNA_WRITE_AIE_REG,
	628	+ DRM_AMDXDNA_SET_FORCE_PREEMPT,
	629	+ DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT,
569	630	};
570	631
571	632	/**

include/uapi/drm/drm.h+15−0

@@ -906,6 +906,21 @@ struct drm_get_cap { · 905 unmodified lines
906	906	*/
907	907	#define DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT 6
908	908
	909	+/**
	910	+ * DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE
	911	+ *
	912	+ * If set to 1 the DRM core will allow setting the COLOR_PIPELINE
	913	+ * property on a &drm_plane, as well as drm_colorop properties.
	914	+ *
	915	+ * Setting of these plane properties will be rejected when this client
	916	+ * cap is set:
	917	+ * - COLOR_ENCODING
	918	+ * - COLOR_RANGE
	919	+ *
	920	+ * The client must enable &DRM_CLIENT_CAP_ATOMIC first.
	921	+ */
	922	+#define DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE 7
	923	+
909	924	/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
910	925	struct drm_set_client_cap {
911	926	__u64 capability;

include/uapi/drm/drm_mode.h+183−1

@@ -629,6 +629,7 @@ struct drm_mode_connector_set_property { · 628 unmodified lines
629	629	#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
630	630	#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
631	631	#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
	632	+#define DRM_MODE_OBJECT_COLOROP 0xfafafafa
632	633	#define DRM_MODE_OBJECT_ANY 0
633	634
634	635	struct drm_mode_obj_get_properties {
@@ -846,6 +847,20 @@ struct drm_color_ctm { · 211 unmodified lines
846	847	__u64 matrix[9];
847	848	};
848	849
	850	+struct drm_color_ctm_3x4 {
	851	+ /*
	852	+ * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude
	853	+ * (not two's complement!) format.
	854	+ *
	855	+ * out matrix in
	856	+ * \|R\| \|0 1 2 3 \| \| R \|
	857	+ * \|G\| = \|4 5 6 7 \| x \| G \|
	858	+ * \|B\| \|8 9 10 11\| \| B \|
	859	+ * \|1.0\|
	860	+ */
	861	+ __u64 matrix[12];
	862	+};
	863	+
849	864	struct drm_color_lut {
850	865	/*
851	866	* Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
@@ -857,6 +872,125 @@ struct drm_color_lut { · 5 unmodified lines
857	872	__u16 reserved;
858	873	};
859	874
	875	+/*
	876	+ * struct drm_color_lut32
	877	+ *
	878	+ * 32-bit per channel color LUT entry, similar to drm_color_lut.
	879	+ */
	880	+struct drm_color_lut32 {
	881	+ __u32 red;
	882	+ __u32 green;
	883	+ __u32 blue;
	884	+ __u32 reserved;
	885	+};
	886	+
	887	+/**
	888	+ * enum drm_colorop_type - Type of color operation
	889	+ *
	890	+ * drm_colorops can be of many different types. Each type behaves differently
	891	+ * and defines a different set of properties. This enum defines all types and
	892	+ * gives a high-level description.
	893	+ */
	894	+enum drm_colorop_type {
	895	+ /**
	896	+ * @DRM_COLOROP_1D_CURVE:
	897	+ *
	898	+ * enum string "1D Curve"
	899	+ *
	900	+ * A 1D curve that is being applied to all color channels. The
	901	+ * curve is specified via the CURVE_1D_TYPE colorop property.
	902	+ */
	903	+ DRM_COLOROP_1D_CURVE,
	904	+
	905	+ /**
	906	+ * @DRM_COLOROP_1D_LUT:
	907	+ *
	908	+ * enum string "1D LUT"
	909	+ *
	910	+ * A simple 1D LUT of uniformly spaced &drm_color_lut32 entries,
	911	+ * packed into a blob via the DATA property. The driver's
	912	+ * expected LUT size is advertised via the SIZE property.
	913	+ *
	914	+ * The DATA blob is an array of struct drm_color_lut32 with size
	915	+ * of "size".
	916	+ */
	917	+ DRM_COLOROP_1D_LUT,
	918	+
	919	+ /**
	920	+ * @DRM_COLOROP_CTM_3X4:
	921	+ *
	922	+ * enum string "3x4 Matrix"
	923	+ *
	924	+ * A 3x4 matrix. Its values are specified via the
	925	+ * &drm_color_ctm_3x4 struct provided via the DATA property.
	926	+ *
	927	+ * The DATA blob is a float[12]:
	928	+ * out matrix in
	929	+ * \| R \| \| 0 1 2 3 \| \| R \|
	930	+ * \| G \| = \| 4 5 6 7 \| x \| G \|
	931	+ * \| B \| \| 8 9 10 12 \| \| B \|
	932	+ */
	933	+ DRM_COLOROP_CTM_3X4,
	934	+
	935	+ /**
	936	+ * @DRM_COLOROP_MULTIPLIER:
	937	+ *
	938	+ * enum string "Multiplier"
	939	+ *
	940	+ * A simple multiplier, applied to all color values. The
	941	+ * multiplier is specified as a S31.32 via the MULTIPLIER
	942	+ * property.
	943	+ */
	944	+ DRM_COLOROP_MULTIPLIER,
	945	+
	946	+ /**
	947	+ * @DRM_COLOROP_3D_LUT:
	948	+ *
	949	+ * enum string "3D LUT"
	950	+ *
	951	+ * A 3D LUT of &drm_color_lut32 entries,
	952	+ * packed into a blob via the DATA property. The driver's expected
	953	+ * LUT size is advertised via the SIZE property, i.e., a 3D LUT with
	954	+ * 17x17x17 entries will have SIZE set to 17.
	955	+ *
	956	+ * The DATA blob is a 3D array of struct drm_color_lut32 with dimension
	957	+ * length of "size".
	958	+ * The LUT elements are traversed like so:
	959	+ *
	960	+ * for B in range 0..n
	961	+ * for G in range 0..n
	962	+ * for R in range 0..n
	963	+ * index = R + n * (G + n * B)
	964	+ * color = lut3d[index]
	965	+ */
	966	+ DRM_COLOROP_3D_LUT,
	967	+};
	968	+
	969	+/**
	970	+ * enum drm_colorop_lut3d_interpolation_type - type of 3DLUT interpolation
	971	+ */
	972	+enum drm_colorop_lut3d_interpolation_type {
	973	+ /**
	974	+ * @DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL:
	975	+ *
	976	+ * Tetrahedral 3DLUT interpolation
	977	+ */
	978	+ DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
	979	+};
	980	+
	981	+/**
	982	+ * enum drm_colorop_lut1d_interpolation_type - type of interpolation for 1D LUTs
	983	+ */
	984	+enum drm_colorop_lut1d_interpolation_type {
	985	+ /**
	986	+ * @DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR:
	987	+ *
	988	+ * Linear interpolation. Values between points of the LUT will be
	989	+ * linearly interpolated.
	990	+ */
	991	+ DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
	992	+};
	993	+
860	994	/**
861	995	* struct drm_plane_size_hint - Plane size hints
862	996	* @width: The width of the plane in pixel
@@ -1066,7 +1200,7 @@ struct drm_mode_crtc_page_flip_target { · 203 unmodified lines
1066	1200	* struct drm_mode_create_dumb - Create a KMS dumb buffer for scanout.
1067	1201	* @height: buffer height in pixels
1068	1202	* @width: buffer width in pixels
1069		− * @bpp: bits per pixel
	1203	+ * @bpp: color mode
1070	1204	* @flags: must be zero
1071	1205	* @handle: buffer object handle
1072	1206	* @pitch: number of bytes between two consecutive lines
@@ -1074,6 +1208,54 @@ struct drm_mode_crtc_page_flip_target { · 1 unmodified line
1074	1208	*
1075	1209	* User-space fills @height, @width, @bpp and @flags. If the IOCTL succeeds,
1076	1210	* the kernel fills @handle, @pitch and @size.
	1211	+ *
	1212	+ * The value of @bpp is a color-mode number describing a specific format
	1213	+ * or a variant thereof. The value often corresponds to the number of bits
	1214	+ * per pixel for most modes, although there are exceptions. Each color mode
	1215	+ * maps to a DRM format plus a number of modes with similar pixel layout.
	1216	+ * Framebuffer layout is always linear.
	1217	+ *
	1218	+ * Support for all modes and formats is optional. Even if dumb-buffer
	1219	+ * creation with a certain color mode succeeds, it is not guaranteed that
	1220	+ * the DRM driver supports any of the related formats. Most drivers support
	1221	+ * a color mode of 32 with a format of DRM_FORMAT_XRGB8888 on their primary
	1222	+ * plane.
	1223	+ *
	1224	+ * +------------+------------------------+------------------------+
	1225	+ * \| Color mode \| Framebuffer format \| Compatible formats \|
	1226	+ * +============+========================+========================+
	1227	+ * \| 32 \| * DRM_FORMAT_XRGB8888 \| * DRM_FORMAT_BGRX8888 \|
	1228	+ * \| \| \| * DRM_FORMAT_RGBX8888 \|
	1229	+ * \| \| \| * DRM_FORMAT_XBGR8888 \|
	1230	+ * +------------+------------------------+------------------------+
	1231	+ * \| 24 \| * DRM_FORMAT_RGB888 \| * DRM_FORMAT_BGR888 \|
	1232	+ * +------------+------------------------+------------------------+
	1233	+ * \| 16 \| * DRM_FORMAT_RGB565 \| * DRM_FORMAT_BGR565 \|
	1234	+ * +------------+------------------------+------------------------+
	1235	+ * \| 15 \| * DRM_FORMAT_XRGB1555 \| * DRM_FORMAT_BGRX1555 \|
	1236	+ * \| \| \| * DRM_FORMAT_RGBX1555 \|
	1237	+ * \| \| \| * DRM_FORMAT_XBGR1555 \|
	1238	+ * +------------+------------------------+------------------------+
	1239	+ * \| 8 \| * DRM_FORMAT_C8 \| * DRM_FORMAT_D8 \|
	1240	+ * \| \| \| * DRM_FORMAT_R8 \|
	1241	+ * +------------+------------------------+------------------------+
	1242	+ * \| 4 \| * DRM_FORMAT_C4 \| * DRM_FORMAT_D4 \|
	1243	+ * \| \| \| * DRM_FORMAT_R4 \|
	1244	+ * +------------+------------------------+------------------------+
	1245	+ * \| 2 \| * DRM_FORMAT_C2 \| * DRM_FORMAT_D2 \|
	1246	+ * \| \| \| * DRM_FORMAT_R2 \|
	1247	+ * +------------+------------------------+------------------------+
	1248	+ * \| 1 \| * DRM_FORMAT_C1 \| * DRM_FORMAT_D1 \|
	1249	+ * \| \| \| * DRM_FORMAT_R1 \|
	1250	+ * +------------+------------------------+------------------------+
	1251	+ *
	1252	+ * Color modes of 10, 12, 15, 30 and 64 are only supported for use by
	1253	+ * legacy user space. Please don't use them in new code. Other modes
	1254	+ * are not support.
	1255	+ *
	1256	+ * Do not attempt to allocate anything but linear framebuffer memory
	1257	+ * with single-plane RGB data. Allocation of other framebuffer
	1258	+ * layouts requires dedicated ioctls in the respective DRM driver.
1077	1259	*/
1078	1260	struct drm_mode_create_dumb {
1079	1261	__u32 height;

include/uapi/drm/ethosu_accel.h+261−0

@@ -0,0 +1,261 @@
	1	+/* SPDX-License-Identifier: MIT */
	2	+/* Copyright (C) 2025 Arm, Ltd. */
	3	+#ifndef _ETHOSU_DRM_H_
	4	+#define _ETHOSU_DRM_H_
	5	+
	6	+#include "drm.h"
	7	+
	8	+#if defined(__cplusplus)
	9	+extern "C" {
	10	+#endif
	11	+
	12	+/**
	13	+ * DOC: IOCTL IDs
	14	+ *
	15	+ * enum drm_ethosu_ioctl_id - IOCTL IDs
	16	+ *
	17	+ * Place new ioctls at the end, don't re-order, don't replace or remove entries.
	18	+ *
	19	+ * These IDs are not meant to be used directly. Use the DRM_IOCTL_ETHOSU_xxx
	20	+ * definitions instead.
	21	+ */
	22	+enum drm_ethosu_ioctl_id {
	23	+ /** @DRM_ETHOSU_DEV_QUERY: Query device information. */
	24	+ DRM_ETHOSU_DEV_QUERY = 0,
	25	+
	26	+ /** @DRM_ETHOSU_BO_CREATE: Create a buffer object. */
	27	+ DRM_ETHOSU_BO_CREATE,
	28	+
	29	+ /** @DRM_ETHOSU_BO_WAIT: Wait on a buffer object's fence. */
	30	+ DRM_ETHOSU_BO_WAIT,
	31	+
	32	+ /**
	33	+ * @DRM_ETHOSU_BO_MMAP_OFFSET: Get the file offset to pass to
	34	+ * mmap to map a GEM object.
	35	+ */
	36	+ DRM_ETHOSU_BO_MMAP_OFFSET,
	37	+
	38	+ /**
	39	+ * @DRM_ETHOSU_CMDSTREAM_BO_CREATE: Create a command stream buffer
	40	+ * object.
	41	+ */
	42	+ DRM_ETHOSU_CMDSTREAM_BO_CREATE,
	43	+
	44	+ /** @DRM_ETHOSU_SUBMIT: Submit a job and BOs to run. */
	45	+ DRM_ETHOSU_SUBMIT,
	46	+};
	47	+
	48	+/**
	49	+ * DOC: IOCTL arguments
	50	+ */
	51	+
	52	+/**
	53	+ * enum drm_ethosu_dev_query_type - Query type
	54	+ *
	55	+ * Place new types at the end, don't re-order, don't remove or replace.
	56	+ */
	57	+enum drm_ethosu_dev_query_type {
	58	+ /** @DRM_ETHOSU_DEV_QUERY_NPU_INFO: Query NPU information. */
	59	+ DRM_ETHOSU_DEV_QUERY_NPU_INFO = 0,
	60	+};
	61	+
	62	+/**
	63	+ * struct drm_ethosu_gpu_info - NPU information
	64	+ *
	65	+ * Structure grouping all queryable information relating to the NPU.
	66	+ */
	67	+struct drm_ethosu_npu_info {
	68	+ /** @id : NPU ID. */
	69	+ __u32 id;
	70	+#define DRM_ETHOSU_ARCH_MAJOR(x) ((x) >> 28)
	71	+#define DRM_ETHOSU_ARCH_MINOR(x) (((x) >> 20) & 0xff)
	72	+#define DRM_ETHOSU_ARCH_PATCH(x) (((x) >> 16) & 0xf)
	73	+#define DRM_ETHOSU_PRODUCT_MAJOR(x) (((x) >> 12) & 0xf)
	74	+#define DRM_ETHOSU_VERSION_MAJOR(x) (((x) >> 8) & 0xf)
	75	+#define DRM_ETHOSU_VERSION_MINOR(x) (((x) >> 4) & 0xff)
	76	+#define DRM_ETHOSU_VERSION_STATUS(x) ((x) & 0xf)
	77	+
	78	+ /** @gpu_rev: GPU revision. */
	79	+ __u32 config;
	80	+
	81	+ __u32 sram_size;
	82	+};
	83	+
	84	+/**
	85	+ * struct drm_ethosu_dev_query - Arguments passed to DRM_ETHOSU_IOCTL_DEV_QUERY
	86	+ */
	87	+struct drm_ethosu_dev_query {
	88	+ /** @type: the query type (see drm_ethosu_dev_query_type). */
	89	+ __u32 type;
	90	+
	91	+ /**
	92	+ * @size: size of the type being queried.
	93	+ *
	94	+ * If pointer is NULL, size is updated by the driver to provide the
	95	+ * output structure size. If pointer is not NULL, the driver will
	96	+ * only copy min(size, actual_structure_size) bytes to the pointer,
	97	+ * and update the size accordingly. This allows us to extend query
	98	+ * types without breaking userspace.
	99	+ */
	100	+ __u32 size;
	101	+
	102	+ /**
	103	+ * @pointer: user pointer to a query type struct.
	104	+ *
	105	+ * Pointer can be NULL, in which case, nothing is copied, but the
	106	+ * actual structure size is returned. If not NULL, it must point to
	107	+ * a location that's large enough to hold size bytes.
	108	+ */
	109	+ __u64 pointer;
	110	+};
	111	+
	112	+/**
	113	+ * enum drm_ethosu_bo_flags - Buffer object flags, passed at creation time.
	114	+ */
	115	+enum drm_ethosu_bo_flags {
	116	+ /**
	117	+ * @DRM_ETHOSU_BO_NO_MMAP: The buffer object will never be CPU-mapped
	118	+ * in userspace.
	119	+ */
	120	+ DRM_ETHOSU_BO_NO_MMAP = (1 << 0),
	121	+};
	122	+
	123	+/**
	124	+ * struct drm_ethosu_bo_create - Arguments passed to DRM_IOCTL_ETHOSU_BO_CREATE.
	125	+ */
	126	+struct drm_ethosu_bo_create {
	127	+ /**
	128	+ * @size: Requested size for the object
	129	+ *
	130	+ * The (page-aligned) allocated size for the object will be returned.
	131	+ */
	132	+ __u64 size;
	133	+
	134	+ /**
	135	+ * @flags: Flags. Must be a combination of drm_ethosu_bo_flags flags.
	136	+ */
	137	+ __u32 flags;
	138	+
	139	+ /**
	140	+ * @handle: Returned handle for the object.
	141	+ *
	142	+ * Object handles are nonzero.
	143	+ */
	144	+ __u32 handle;
	145	+};
	146	+
	147	+/**
	148	+ * struct drm_ethosu_bo_mmap_offset - Arguments passed to DRM_IOCTL_ETHOSU_BO_MMAP_OFFSET.
	149	+ */
	150	+struct drm_ethosu_bo_mmap_offset {
	151	+ /** @handle: Handle of the object we want an mmap offset for. */
	152	+ __u32 handle;
	153	+
	154	+ /** @pad: MBZ. */
	155	+ __u32 pad;
	156	+
	157	+ /** @offset: The fake offset to use for subsequent mmap calls. */
	158	+ __u64 offset;
	159	+};
	160	+
	161	+/**
	162	+ * struct drm_ethosu_wait_bo - ioctl argument for waiting for
	163	+ * completion of the last DRM_ETHOSU_SUBMIT on a BO.
	164	+ *
	165	+ * This is useful for cases where multiple processes might be
	166	+ * rendering to a BO and you want to wait for all rendering to be
	167	+ * completed.
	168	+ */
	169	+struct drm_ethosu_bo_wait {
	170	+ __u32 handle;
	171	+ __u32 pad;
	172	+ __s64 timeout_ns; /* absolute */
	173	+};
	174	+
	175	+struct drm_ethosu_cmdstream_bo_create {
	176	+ /* Size of the data argument. */
	177	+ __u32 size;
	178	+
	179	+ /* Flags, currently must be 0. */
	180	+ __u32 flags;
	181	+
	182	+ /* Pointer to the data. */
	183	+ __u64 data;
	184	+
	185	+ /** Returned GEM handle for the BO. */
	186	+ __u32 handle;
	187	+
	188	+ /* Pad, must be 0. */
	189	+ __u32 pad;
	190	+};
	191	+
	192	+/**
	193	+ * struct drm_ethosu_job - A job to be run on the NPU
	194	+ *
	195	+ * The kernel will schedule the execution of this job taking into account its
	196	+ * dependencies with other jobs. All tasks in the same job will be executed
	197	+ * sequentially on the same core, to benefit from memory residency in SRAM.
	198	+ */
	199	+struct drm_ethosu_job {
	200	+ /** Input: BO handle for cmdstream. */
	201	+ __u32 cmd_bo;
	202	+
	203	+ /** Input: Amount of SRAM to use. */
	204	+ __u32 sram_size;
	205	+
	206	+#define ETHOSU_MAX_REGIONS 8
	207	+ /** Input: Array of BO handles for each region. */
	208	+ __u32 region_bo_handles[ETHOSU_MAX_REGIONS];
	209	+};
	210	+
	211	+/**
	212	+ * struct drm_ethosu_submit - ioctl argument for submitting commands to the NPU.
	213	+ *
	214	+ * The kernel will schedule the execution of these jobs in dependency order.
	215	+ */
	216	+struct drm_ethosu_submit {
	217	+ /** Input: Pointer to an array of struct drm_ethosu_job. */
	218	+ __u64 jobs;
	219	+
	220	+ /** Input: Number of jobs passed in. */
	221	+ __u32 job_count;
	222	+
	223	+ /** Reserved, must be zero. */
	224	+ __u32 pad;
	225	+};
	226	+
	227	+/**
	228	+ * DRM_IOCTL_ETHOSU() - Build a ethosu IOCTL number
	229	+ * @__access: Access type. Must be R, W or RW.
	230	+ * @__id: One of the DRM_ETHOSU_xxx id.
	231	+ * @__type: Suffix of the type being passed to the IOCTL.
	232	+ *
	233	+ * Don't use this macro directly, use the DRM_IOCTL_ETHOSU_xxx
	234	+ * values instead.
	235	+ *
	236	+ * Return: An IOCTL number to be passed to ioctl() from userspace.
	237	+ */
	238	+#define DRM_IOCTL_ETHOSU(__access, __id, __type) \
	239	+ DRM_IO ## __access(DRM_COMMAND_BASE + DRM_ETHOSU_ ## __id, \
	240	+ struct drm_ethosu_ ## __type)
	241	+
	242	+enum {
	243	+ DRM_IOCTL_ETHOSU_DEV_QUERY =
	244	+ DRM_IOCTL_ETHOSU(WR, DEV_QUERY, dev_query),
	245	+ DRM_IOCTL_ETHOSU_BO_CREATE =
	246	+ DRM_IOCTL_ETHOSU(WR, BO_CREATE, bo_create),
	247	+ DRM_IOCTL_ETHOSU_BO_WAIT =
	248	+ DRM_IOCTL_ETHOSU(WR, BO_WAIT, bo_wait),
	249	+ DRM_IOCTL_ETHOSU_BO_MMAP_OFFSET =
	250	+ DRM_IOCTL_ETHOSU(WR, BO_MMAP_OFFSET, bo_mmap_offset),
	251	+ DRM_IOCTL_ETHOSU_CMDSTREAM_BO_CREATE =
	252	+ DRM_IOCTL_ETHOSU(WR, CMDSTREAM_BO_CREATE, cmdstream_bo_create),
	253	+ DRM_IOCTL_ETHOSU_SUBMIT =
	254	+ DRM_IOCTL_ETHOSU(WR, SUBMIT, submit),
	255	+};
	256	+
	257	+#if defined(__cplusplus)
	258	+}
	259	+#endif
	260	+
	261	+#endif /* _ETHOSU_DRM_H_ */

include/uapi/drm/ivpu_accel.h+63−0

@@ -25,6 +25,7 @@ extern "C" { · 24 unmodified lines
25	25	#define DRM_IVPU_CMDQ_CREATE 0x0b
26	26	#define DRM_IVPU_CMDQ_DESTROY 0x0c
27	27	#define DRM_IVPU_CMDQ_SUBMIT 0x0d
	28	+#define DRM_IVPU_BO_CREATE_FROM_USERPTR 0x0e
28	29
29	30	#define DRM_IOCTL_IVPU_GET_PARAM \
30	31	DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)
@@ -69,6 +70,10 @@ extern "C" { · 38 unmodified lines
69	70	#define DRM_IOCTL_IVPU_CMDQ_SUBMIT \
70	71	DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_SUBMIT, struct drm_ivpu_cmdq_submit)
71	72
	73	+#define DRM_IOCTL_IVPU_BO_CREATE_FROM_USERPTR \
	74	+ DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE_FROM_USERPTR, \
	75	+ struct drm_ivpu_bo_create_from_userptr)
	76	+
72	77	/**
73	78	* DOC: contexts
74	79	*
@@ -90,6 +95,7 @@ extern "C" { · 15 unmodified lines
90	95	#define DRM_IVPU_PARAM_TILE_CONFIG 11
91	96	#define DRM_IVPU_PARAM_SKU 12
92	97	#define DRM_IVPU_PARAM_CAPABILITIES 13
	98	+#define DRM_IVPU_PARAM_PREEMPT_BUFFER_SIZE 14
93	99
94	100	#define DRM_IVPU_PLATFORM_TYPE_SILICON 0
95	101
@@ -126,6 +132,13 @@ extern "C" { · 30 unmodified lines
126	132	* command queue destroy and submit job on specific command queue.
127	133	*/
128	134	#define DRM_IVPU_CAP_MANAGE_CMDQ 3
	135	+/**
	136	+ * DRM_IVPU_CAP_BO_CREATE_FROM_USERPTR
	137	+ *
	138	+ * Driver supports creating buffer objects from user space memory pointers.
	139	+ * This allows creating GEM buffers from existing user memory regions.
	140	+ */
	141	+#define DRM_IVPU_CAP_BO_CREATE_FROM_USERPTR 4
129	142
130	143	/**
131	144	* struct drm_ivpu_param - Get/Set VPU parameters
@@ -176,6 +189,9 @@ struct drm_ivpu_param { · 44 unmodified lines
176	189	*
177	190	* %DRM_IVPU_PARAM_CAPABILITIES:
178	191	* Supported capabilities (read-only)
	192	+ *
	193	+ * %DRM_IVPU_PARAM_PREEMPT_BUFFER_SIZE:
	194	+ * Size of the preemption buffer (read-only)
179	195	*/
180	196	__u32 param;
181	197
@@ -190,6 +206,7 @@ struct drm_ivpu_param { · 8 unmodified lines
190	206	#define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM
191	207	#define DRM_IVPU_BO_MAPPABLE 0x00000002
192	208	#define DRM_IVPU_BO_DMA_MEM 0x00000004
	209	+#define DRM_IVPU_BO_READ_ONLY 0x00000008
193	210
194	211	#define DRM_IVPU_BO_CACHED 0x00000000
195	212	#define DRM_IVPU_BO_UNCACHED 0x00010000
@@ -200,6 +217,7 @@ struct drm_ivpu_param { · 4 unmodified lines
200	217	(DRM_IVPU_BO_HIGH_MEM \| \
201	218	DRM_IVPU_BO_MAPPABLE \| \
202	219	DRM_IVPU_BO_DMA_MEM \| \
	220	+ DRM_IVPU_BO_READ_ONLY \| \
203	221	DRM_IVPU_BO_CACHE_MASK)
204	222
205	223	/**
@@ -251,6 +269,44 @@ struct drm_ivpu_bo_create { · 45 unmodified lines
251	269	__u64 vpu_addr;
252	270	};
253	271
	272	+/**
	273	+ * struct drm_ivpu_bo_create_from_userptr - Create dma-buf from user pointer
	274	+ *
	275	+ * Create a GEM buffer object from a user pointer to a memory region.
	276	+ */
	277	+struct drm_ivpu_bo_create_from_userptr {
	278	+ /** @user_ptr: User pointer to memory region (must be page aligned) */
	279	+ __u64 user_ptr;
	280	+
	281	+ /** @size: Size of the memory region in bytes (must be page aligned) */
	282	+ __u64 size;
	283	+
	284	+ /**
	285	+ * @flags:
	286	+ *
	287	+ * Supported flags:
	288	+ *
	289	+ * %DRM_IVPU_BO_HIGH_MEM:
	290	+ *
	291	+ * Allocate VPU address from >4GB range.
	292	+ *
	293	+ * %DRM_IVPU_BO_DMA_MEM:
	294	+ *
	295	+ * Allocate from DMA memory range accessible by hardware DMA.
	296	+ *
	297	+ * %DRM_IVPU_BO_READ_ONLY:
	298	+ *
	299	+ * Allocate as a read-only buffer object.
	300	+ */
	301	+ __u32 flags;
	302	+
	303	+ /** @handle: Returned GEM object handle */
	304	+ __u32 handle;
	305	+
	306	+ /** @vpu_addr: Returned VPU virtual address */
	307	+ __u64 vpu_addr;
	308	+};
	309	+
254	310	/**
255	311	* struct drm_ivpu_bo_info - Query buffer object info
256	312	*/
@@ -371,6 +427,13 @@ struct drm_ivpu_cmdq_submit { · 114 unmodified lines
371	427	* to be executed. The offset has to be 8-byte aligned.
372	428	*/
373	429	__u32 commands_offset;
	430	+ /**
	431	+ * @preempt_buffer_index:
	432	+ *
	433	+ * Index of the preemption buffer in the buffers_ptr array.
	434	+ */
	435	+ __u32 preempt_buffer_index;
	436	+ __u32 reserved;
374	437	};
375	438
376	439	/* drm_ivpu_bo_wait job status codes */

include/uapi/drm/panfrost_drm.h+123−27

@@ -22,6 +22,8 @@ extern "C" { · 21 unmodified lines
22	22	#define DRM_PANFROST_PERFCNT_DUMP 0x07
23	23	#define DRM_PANFROST_MADVISE 0x08
24	24	#define DRM_PANFROST_SET_LABEL_BO 0x09
	25	+#define DRM_PANFROST_JM_CTX_CREATE 0x0a
	26	+#define DRM_PANFROST_JM_CTX_DESTROY 0x0b
25	27
26	28	#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)
27	29	#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)
@@ -31,6 +33,8 @@ extern "C" { · 3 unmodified lines
31	33	#define DRM_IOCTL_PANFROST_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset)
32	34	#define DRM_IOCTL_PANFROST_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MADVISE, struct drm_panfrost_madvise)
33	35	#define DRM_IOCTL_PANFROST_SET_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SET_LABEL_BO, struct drm_panfrost_set_label_bo)
	36	+#define DRM_IOCTL_PANFROST_JM_CTX_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_CREATE, struct drm_panfrost_jm_ctx_create)
	37	+#define DRM_IOCTL_PANFROST_JM_CTX_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_DESTROY, struct drm_panfrost_jm_ctx_destroy)
34	38
35	39	/*
36	40	* Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module
@@ -50,27 +54,47 @@ extern "C" { · 13 unmodified lines
50	54	* This asks the kernel to have the GPU execute a render command list.
51	55	*/
52	56	struct drm_panfrost_submit {
53		−
54		− /** Address to GPU mapping of job descriptor */
	57	+ /**
	58	+ * @jc: Address to GPU mapping of job descriptor
	59	+ */
55	60	__u64 jc;
56		−
57		− /** An optional array of sync objects to wait on before starting this job. */
	61	+ /**
	62	+ * @in_syncs: An optional array of sync objects to wait on
	63	+ * before starting this job.
	64	+ */
58	65	__u64 in_syncs;
59		−
60		− /** Number of sync objects to wait on before starting this job. */
	66	+ /**
	67	+ * @in_sync_count: Number of sync objects to wait on before
	68	+ * starting this job.
	69	+ */
61	70	__u32 in_sync_count;
62		−
63		− /** An optional sync object to place the completion fence in. */
	71	+ /**
	72	+ * @out_sync: An optional sync object to place the completion fence in.
	73	+ */
64	74	__u32 out_sync;
65		−
66		− /** Pointer to a u32 array of the BOs that are referenced by the job. */
	75	+ /**
	76	+ * @bo_handles: Pointer to a u32 array of the BOs that are
	77	+ * referenced by the job.
	78	+ */
67	79	__u64 bo_handles;
68		−
69		− /** Number of BO handles passed in (size is that times 4). */
	80	+ /**
	81	+ * @bo_handle_count: Number of BO handles passed in (size is
	82	+ * that times 4).
	83	+ */
70	84	__u32 bo_handle_count;
71		−
72		− /** A combination of PANFROST_JD_REQ_* */
	85	+ /**
	86	+ * @requirements: A combination of PANFROST_JD_REQ_*
	87	+ */
73	88	__u32 requirements;
	89	+ /**
	90	+ * @jm_ctx_handle: JM context handle. Zero if you want to use the
	91	+ * default context.
	92	+ */
	93	+ __u32 jm_ctx_handle;
	94	+ /**
	95	+ * @pad: Padding field. Must be zero.
	96	+ */
	97	+ __u32 pad;
74	98	};
75	99
76	100	/**
@@ -82,9 +106,18 @@ struct drm_panfrost_submit { · 5 unmodified lines
82	106	* completed.
83	107	*/
84	108	struct drm_panfrost_wait_bo {
	109	+ /**
	110	+ * @handle: Handle for the object to wait for.
	111	+ */
85	112	__u32 handle;
	113	+ /**
	114	+ * @pad: Padding, must be zero-filled.
	115	+ */
86	116	__u32 pad;
87		− __s64 timeout_ns; /* absolute */
	117	+ /**
	118	+ * @timeout_ns: absolute number of nanoseconds to wait.
	119	+ */
	120	+ __s64 timeout_ns;
88	121	};
89	122
90	123	/* Valid flags to pass to drm_panfrost_create_bo */
@@ -97,16 +130,26 @@ struct drm_panfrost_wait_bo { · 6 unmodified lines
97	130	* The flags argument is a bit mask of PANFROST_BO_* flags.
98	131	*/
99	132	struct drm_panfrost_create_bo {
	133	+ /**
	134	+ * @size: size of shmem/BO area to create (bytes)
	135	+ */
100	136	__u32 size;
	137	+ /**
	138	+ * @flags: see PANFROST_BO_* flags
	139	+ */
101	140	__u32 flags;
102		− /** Returned GEM handle for the BO. */
	141	+ /**
	142	+ * @handle: Returned GEM handle for the BO.
	143	+ */
103	144	__u32 handle;
104		− /* Pad, must be zero-filled. */
	145	+ /**
	146	+ * @pad: Padding, must be zero-filled.
	147	+ */
105	148	__u32 pad;
106	149	/**
107		− * Returned offset for the BO in the GPU address space. This offset
108		− * is private to the DRM fd and is valid for the lifetime of the GEM
109		− * handle.
	150	+ * @offset: Returned offset for the BO in the GPU address space.
	151	+ * This offset is private to the DRM fd and is valid for the
	152	+ * lifetime of the GEM handle.
110	153	*
111	154	* This offset value will always be nonzero, since various HW
112	155	* units treat 0 specially.
@@ -126,10 +169,17 @@ struct drm_panfrost_create_bo { · 13 unmodified lines
126	169	* used in a future extension.
127	170	*/
128	171	struct drm_panfrost_mmap_bo {
129		− /** Handle for the object being mapped. */
	172	+ /**
	173	+ * @handle: Handle for the object being mapped.
	174	+ */
130	175	__u32 handle;
	176	+ /**
	177	+ * @flags: currently not used (should be zero)
	178	+ */
131	179	__u32 flags;
132		− /** offset into the drm node to use for subsequent mmap call. */
	180	+ /**
	181	+ * @offset: offset into the drm node to use for subsequent mmap call.
	182	+ */
133	183	__u64 offset;
134	184	};
135	185
@@ -177,6 +227,7 @@ enum drm_panfrost_param { · 41 unmodified lines
177	227	DRM_PANFROST_PARAM_AFBC_FEATURES,
178	228	DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP,
179	229	DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP_FREQUENCY,
	230	+ DRM_PANFROST_PARAM_ALLOWED_JM_CTX_PRIORITIES,
180	231	};
181	232
182	233	struct drm_panfrost_get_param {
@@ -185,7 +236,7 @@ struct drm_panfrost_get_param { · 2 unmodified lines
185	236	__u64 value;
186	237	};
187	238
188		−/**
	239	+/*
189	240	* Returns the offset for the BO in the GPU address space for this DRM fd.
190	241	* This is the same value returned by drm_panfrost_create_bo, if that was called
191	242	* from this DRM fd.
@@ -233,12 +284,14 @@ struct drm_panfrost_madvise { · 41 unmodified lines
233	284	* struct drm_panfrost_set_label_bo - ioctl argument for labelling Panfrost BOs.
234	285	*/
235	286	struct drm_panfrost_set_label_bo {
236		− /** @handle: Handle of the buffer object to label. */
	287	+ /**
	288	+ * @handle: Handle of the buffer object to label.
	289	+ */
237	290	__u32 handle;
238		−
239		− /** @pad: MBZ. */
	291	+ /**
	292	+ * @pad: Must be zero.
	293	+ */
240	294	__u32 pad;
241		−
242	295	/**
243	296	* @label: User pointer to a NUL-terminated string
244	297	*
@@ -299,6 +352,49 @@ struct panfrost_dump_registers { · 54 unmodified lines
299	352	__u32 value;
300	353	};
301	354
	355	+enum drm_panfrost_jm_ctx_priority {
	356	+ /**
	357	+ * @PANFROST_JM_CTX_PRIORITY_LOW: Low priority context.
	358	+ */
	359	+ PANFROST_JM_CTX_PRIORITY_LOW = 0,
	360	+
	361	+ /**
	362	+ * @PANFROST_JM_CTX_PRIORITY_MEDIUM: Medium priority context.
	363	+ */
	364	+ PANFROST_JM_CTX_PRIORITY_MEDIUM,
	365	+
	366	+ /**
	367	+ * @PANFROST_JM_CTX_PRIORITY_HIGH: High priority context.
	368	+ *
	369	+ * Requires CAP_SYS_NICE or DRM_MASTER.
	370	+ */
	371	+ PANFROST_JM_CTX_PRIORITY_HIGH,
	372	+};
	373	+
	374	+struct drm_panfrost_jm_ctx_create {
	375	+ /**
	376	+ * @handle: Handle of the created JM context
	377	+ */
	378	+ __u32 handle;
	379	+ /**
	380	+ * @priority: Context priority (see enum drm_panfrost_jm_ctx_priority).
	381	+ */
	382	+ __u32 priority;
	383	+};
	384	+
	385	+struct drm_panfrost_jm_ctx_destroy {
	386	+ /**
	387	+ * @handle: Handle of the JM context to destroy.
	388	+ *
	389	+ * Must be a valid context handle returned by DRM_IOCTL_PANTHOR_JM_CTX_CREATE.
	390	+ */
	391	+ __u32 handle;
	392	+ /**
	393	+ * @pad: Padding field, must be zero.
	394	+ */
	395	+ __u32 pad;
	396	+};
	397	+
302	398	#if defined(__cplusplus)
303	399	}
304	400	#endif

include/uapi/drm/xe_drm.h+5−1

@@ -771,7 +771,11 @@ struct drm_xe_device_query { · 770 unmodified lines
771	771	* until the object is either bound to a virtual memory region via
772	772	* VM_BIND or accessed by the CPU. As a result, no backing memory is
773	773	* reserved at the time of GEM object creation.
774		− * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
	774	+ * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is
	775	+ * intended for scanout via the display engine. When set, kernel ensures
	776	+ * that the allocation is placed in a memory region compatible with the
	777	+ * display engine requirements. This may impose restrictions on tiling,
	778	+ * alignment, and memory placement to guarantee proper display functionality.
775	779	* - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
776	780	* possible placement, ensure that the corresponding VRAM allocation
777	781	* will always use the CPU accessible part of VRAM. This is important