lael-labs/linux

.gitignore+0−4

@@ -100,10 +100,6 @@ modules.order · 99 unmodified lines
100	/include/ksym/	100	/include/ksym/
101	/arch/*/include/generated/	101	/arch/*/include/generated/
102		102
103	# Generated lkdtm tests
104	/tools/testing/selftests/lkdtm/*.sh
105	!/tools/testing/selftests/lkdtm/run.sh
106
107	# stgit generated dirs	103	# stgit generated dirs
108	patches-*	104	patches-*
109		105

Documentation/admin-guide/acpi/fan_performance_states.rst+2−2

@@ -18,7 +18,7 @@ may look as follows:: · 17 unmodified lines
18		18
19	$ ls -l /sys/bus/acpi/devices/INT3404:00/	19	$ ls -l /sys/bus/acpi/devices/INT3404:00/
20	total 0	20	total 0
21	...	21	...
22	-r--r--r-- 1 root root 4096 Dec 13 20:38 state0	22	-r--r--r-- 1 root root 4096 Dec 13 20:38 state0
23	-r--r--r-- 1 root root 4096 Dec 13 20:38 state1	23	-r--r--r-- 1 root root 4096 Dec 13 20:38 state1
24	-r--r--r-- 1 root root 4096 Dec 13 20:38 state10	24	-r--r--r-- 1 root root 4096 Dec 13 20:38 state10
@@ -38,7 +38,7 @@ where each of the "state*" files represents one performance state of the fan · 13 unmodified lines
38	and contains a colon-separated list of 5 integer numbers (fields) with the	38	and contains a colon-separated list of 5 integer numbers (fields) with the
39	following interpretation::	39	following interpretation::
40		40
41	control_percent:trip_point_index:speed_rpm:noise_level_mdb:power_mw	41	control_percent:trip_point_index:speed_rpm:noise_level_mdb:power_mw
42		42
43	* ``control_percent``: The percent value to be used to set the fan speed to a	43	* ``control_percent``: The percent value to be used to set the fan speed to a
44	specific level using the _FSL object (0-100).	44	specific level using the _FSL object (0-100).

Documentation/devicetree/bindings/arm/arm,scmi.txt+1−1

@@ -102,7 +102,7 @@ Required sub-node properties: · 101 unmodified lines
102	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt	102	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
103	[2] Documentation/devicetree/bindings/power/power-domain.yaml	103	[2] Documentation/devicetree/bindings/power/power-domain.yaml
104	[3] Documentation/devicetree/bindings/thermal/thermal.txt	104	[3] Documentation/devicetree/bindings/thermal/thermal.txt
105	[4] Documentation/devicetree/bindings/sram/sram.txt	105	[4] Documentation/devicetree/bindings/sram/sram.yaml
106	[5] Documentation/devicetree/bindings/reset/reset.txt	106	[5] Documentation/devicetree/bindings/reset/reset.txt
107		107
108	Example:	108	Example:

Documentation/devicetree/bindings/arm/arm,scpi.txt+1−1

@@ -109,7 +109,7 @@ Required properties: · 108 unmodified lines
109	[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html	109	[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
110	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt	110	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
111	[2] Documentation/devicetree/bindings/thermal/thermal.txt	111	[2] Documentation/devicetree/bindings/thermal/thermal.txt
112	[3] Documentation/devicetree/bindings/sram/sram.txt	112	[3] Documentation/devicetree/bindings/sram/sram.yaml
113	[4] Documentation/devicetree/bindings/power/power-domain.yaml	113	[4] Documentation/devicetree/bindings/power/power-domain.yaml
114		114
115	Example:	115	Example:

Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt+1−1

@@ -62,7 +62,7 @@ Timer node: · 61 unmodified lines
62		62
63	Syscon reboot node:	63	Syscon reboot node:
64		64
65	See Documentation/devicetree/bindings/power/reset/syscon-reboot.txt for the	65	See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the
66	detailed list of properties, the two values defined below are specific to the	66	detailed list of properties, the two values defined below are specific to the
67	BCM6328-style timer:	67	BCM6328-style timer:
68		68

Documentation/devicetree/bindings/arm/cpus.yaml+1−1

@@ -216,7 +216,7 @@ properties: · 215 unmodified lines
216	$ref: '/schemas/types.yaml#/definitions/phandle-array'	216	$ref: '/schemas/types.yaml#/definitions/phandle-array'
217	description: \|	217	description: \|
218	List of phandles to idle state nodes supported	218	List of phandles to idle state nodes supported
219	by this cpu (see ./idle-states.txt).	219	by this cpu (see ./idle-states.yaml).
220		220
221	capacity-dmips-mhz:	221	capacity-dmips-mhz:
222	$ref: '/schemas/types.yaml#/definitions/uint32'	222	$ref: '/schemas/types.yaml#/definitions/uint32'

Documentation/devicetree/bindings/arm/fsl.yaml+1−1

@@ -160,7 +160,7 @@ properties: · 159 unmodified lines
160	items:	160	items:
161	- enum:	161	- enum:
162	- armadeus,imx6dl-apf6 # APF6 (Solo) SoM	162	- armadeus,imx6dl-apf6 # APF6 (Solo) SoM
163	- armadeus,imx6dl-apf6dldev # APF6 (Solo) SoM on APF6Dev board	163	- armadeus,imx6dl-apf6dev # APF6 (Solo) SoM on APF6Dev board
164	- eckelmann,imx6dl-ci4x10	164	- eckelmann,imx6dl-ci4x10
165	- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM	165	- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM
166	- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base	166	- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base

Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt+1−1

@@ -1,7 +1,7 @@
1	* Hisilicon Hi3519 System Controller Block	1	* Hisilicon Hi3519 System Controller Block
2		2
3	This bindings use the following binding:	3	This bindings use the following binding:
4	Documentation/devicetree/bindings/mfd/syscon.txt	4	Documentation/devicetree/bindings/mfd/syscon.yaml
5		5
6	Required properties:	6	Required properties:
7	- compatible: "hisilicon,hi3519-sysctrl".	7	- compatible: "hisilicon,hi3519-sysctrl".

Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt+1−1

@@ -81,4 +81,4 @@ Example: · 80 unmodified lines
81	};	81	};
82	};	82	};
83		83
84	[1]. Documentation/devicetree/bindings/arm/idle-states.txt	84	[1]. Documentation/devicetree/bindings/arm/idle-states.yaml

Documentation/devicetree/bindings/arm/omap/mpu.txt+1−1

@@ -17,7 +17,7 @@ am335x and am437x only: · 16 unmodified lines
17	- pm-sram: Phandles to ocmcram nodes to be used for power management.	17	- pm-sram: Phandles to ocmcram nodes to be used for power management.
18	First should be type 'protect-exec' for the driver to use to copy	18	First should be type 'protect-exec' for the driver to use to copy
19	and run PM functions, second should be regular pool to be used for	19	and run PM functions, second should be regular pool to be used for
20	data region for code. See Documentation/devicetree/bindings/sram/sram.txt	20	data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
21	for more details.	21	for more details.
22		22
23	Examples:	23	Examples:

Documentation/devicetree/bindings/arm/psci.yaml+17−19

       bindings in [1]) must specify this property.
       [1] Kernel documentation - ARM idle states bindings
-        Documentation/devicetree/bindings/arm/idle-states.txt
+        Documentation/devicetree/bindings/arm/idle-states.yaml
-  "#power-domain-cells":
-    description:
-      The number of cells in a PM domain specifier as per binding in [3].
-      Must be 0 as to represent a single PM domain.
+patternProperties:
+  "^power-domain-":
+    allOf:
+      - $ref: "../power/power-domain.yaml#"
+    type: object
+    description: |
       ARM systems can have multiple cores, sometimes in an hierarchical
       arrangement. This often, but not always, maps directly to the processor
       power topology of the system. Individual nodes in a topology have their
       helps to implement support for OSI mode and OS implementations may choose
       to mandate it.
-      [3] Documentation/devicetree/bindings/power/power_domain.txt
+      [3] Documentation/devicetree/bindings/power/power-domain.yaml
-      [4] Documentation/devicetree/bindings/power/domain-idle-state.txt
+      [4] Documentation/devicetree/bindings/power/domain-idle-state.yaml
-  power-domains:
-    $ref: '/schemas/types.yaml#/definitions/phandle-array'
-    description:
-      List of phandles and PM domain specifiers, as defined by bindings of the
-      PM domain provider.
 required:
   - compatible
       CPU0: cpu@0 {
         device_type = "cpu";
-        compatible = "arm,cortex-a53", "arm,armv8";
+        compatible = "arm,cortex-a53";
         reg = <0x0>;
         enable-method = "psci";
         power-domains = <&CPU_PD0>;
       CPU1: cpu@1 {
         device_type = "cpu";
-        compatible = "arm,cortex-a57", "arm,armv8";
+        compatible = "arm,cortex-a53";
         reg = <0x100>;
         enable-method = "psci";
         power-domains = <&CPU_PD1>;
           exit-latency-us = <10>;
           min-residency-us = <100>;
         };
+      };
+      domain-idle-states {
         CLUSTER_RET: cluster-retention {
           compatible = "domain-idle-state";
       compatible = "arm,psci-1.0";
       method = "smc";
-      CPU_PD0: cpu-pd0 {
+      CPU_PD0: power-domain-cpu0 {
         #power-domain-cells = <0>;
         domain-idle-states = <&CPU_PWRDN>;
         power-domains = <&CLUSTER_PD>;
       };
-      CPU_PD1: cpu-pd1 {
+      CPU_PD1: power-domain-cpu1 {
         #power-domain-cells = <0>;
         domain-idle-states =  <&CPU_PWRDN>;
         power-domains = <&CLUSTER_PD>;
       };
-      CLUSTER_PD: cluster-pd {
+      CLUSTER_PD: power-domain-cluster {
         #power-domain-cells = <0>;
         domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
       };

Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml+1−1

@@ -52,7 +52,7 @@ required: · 51 unmodified lines
52		52
53	examples:	53	examples:
54	- \|	54	- \|
55	mlahb: ahb {	55	mlahb: ahb@38000000 {
56	compatible = "st,mlahb", "simple-bus";	56	compatible = "st,mlahb", "simple-bus";
57	#address-cells = <1>;	57	#address-cells = <1>;
58	#size-cells = <1>;	58	#size-cells = <1>;

Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml+0−1

@@ -70,7 +70,6 @@ examples: · 69 unmodified lines
70	#size-cells = <0>;	70	#size-cells = <0>;
71		71
72	pmic@3e3 {	72	pmic@3e3 {
73	compatible = "...";
74	reg = <0x3e3>;	73	reg = <0x3e3>;
75		74
76	/* ... */	75	/* ... */

Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-osc-clk.yaml+1−1

@@ -40,7 +40,7 @@ additionalProperties: false · 39 unmodified lines
40		40
41	examples:	41	examples:
42	- \|	42	- \|
43	osc24M: clk@01c20050 {	43	osc24M: clk@1c20050 {
44	#clock-cells = <0>;	44	#clock-cells = <0>;
45	compatible = "allwinner,sun4i-a10-osc-clk";	45	compatible = "allwinner,sun4i-a10-osc-clk";
46	reg = <0x01c20050 0x4>;	46	reg = <0x01c20050 0x4>;

Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-gt-clk.yaml+1−1

@@ -41,7 +41,7 @@ additionalProperties: false · 40 unmodified lines
41		41
42	examples:	42	examples:
43	- \|	43	- \|
44	clk@0600005c {	44	clk@600005c {
45	#clock-cells = <0>;	45	#clock-cells = <0>;
46	compatible = "allwinner,sun9i-a80-gt-clk";	46	compatible = "allwinner,sun9i-a80-gt-clk";
47	reg = <0x0600005c 0x4>;	47	reg = <0x0600005c 0x4>;

Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml+1−1

@@ -42,7 +42,7 @@ properties: · 41 unmodified lines
42	be part of GCC and hence the TSENS properties can also be part	42	be part of GCC and hence the TSENS properties can also be part
43	of the GCC/clock-controller node.	43	of the GCC/clock-controller node.
44	For more details on the TSENS properties please refer	44	For more details on the TSENS properties please refer
45	Documentation/devicetree/bindings/thermal/qcom-tsens.txt	45	Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
46		46
47	nvmem-cell-names:	47	nvmem-cell-names:
48	minItems: 1	48	minItems: 1

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml+1−5

         resets = <&tcon_ch0_clk 0>;
         port {
-            #address-cells = <1>;
+            tve0_in_tcon0: endpoint {
-            #size-cells = <0>;
-            tve0_in_tcon0: endpoint@0 {
-                reg = <0>;
                 remote-endpoint = <&tcon0_out_tve0>;
             };
         };

Documentation/devicetree/bindings/display/bridge/anx6345.yaml+2−8

           #size-cells = <0>;
           anx6345_in: port@0 {
-            #address-cells = <1>;
-            #size-cells = <0>;
             reg = <0>;
-            anx6345_in_tcon0: endpoint@0 {
+            anx6345_in_tcon0: endpoint {
-              reg = <0>;
               remote-endpoint = <&tcon0_out_anx6345>;
             };
           };
           anx6345_out: port@1 {
-            #address-cells = <1>;
-            #size-cells = <0>;
             reg = <1>;
-            anx6345_out_panel: endpoint@0 {
+            anx6345_out_panel: endpoint {
-              reg = <0>;
               remote-endpoint = <&panel_in_edp>;
             };
           };

Documentation/devicetree/bindings/display/panel/leadtek,ltk500hd1829.yaml+2−0

@@ -37,6 +37,8 @@ examples: · 36 unmodified lines
37	dsi@ff450000 {	37	dsi@ff450000 {
38	#address-cells = <1>;	38	#address-cells = <1>;
39	#size-cells = <0>;	39	#size-cells = <0>;
		40	reg = <0xff450000 0x1000>;
		41
40	panel@0 {	42	panel@0 {
41	compatible = "leadtek,ltk500hd1829";	43	compatible = "leadtek,ltk500hd1829";
42	reg = <0>;	44	reg = <0>;

Documentation/devicetree/bindings/display/panel/xinpeng,xpp055c272.yaml+2−0

@@ -37,6 +37,8 @@ examples: · 36 unmodified lines
37	dsi@ff450000 {	37	dsi@ff450000 {
38	#address-cells = <1>;	38	#address-cells = <1>;
39	#size-cells = <0>;	39	#size-cells = <0>;
		40	reg = <0xff450000 0x1000>;
		41
40	panel@0 {	42	panel@0 {
41	compatible = "xinpeng,xpp055c272";	43	compatible = "xinpeng,xpp055c272";
42	reg = <0>;	44	reg = <0>;

Documentation/devicetree/bindings/display/simple-framebuffer.yaml+1−5

       };
     };
-    soc@1c00000 {
+    lcdc0: lcdc { };
-      lcdc0: lcdc@1c0c000 {
-        compatible = "allwinner,sun4i-a10-lcdc";
-      };
-    };
 ...

Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt+1−1

@@ -37,7 +37,7 @@ Optional nodes: · 36 unmodified lines
37	supports a single port with a single endpoint.	37	supports a single port with a single endpoint.
38		38
39	- See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and	39	- See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and
40	Documentation/devicetree/bindings/display/tilcdc/tfp410.txt for connecting	40	Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt for connecting
41	tfp410 DVI encoder or lcd panel to lcdc	41	tfp410 DVI encoder or lcd panel to lcdc
42		42
43	[1] There is an errata about AM335x color wiring. For 16-bit color mode	43	[1] There is an errata about AM335x color wiring. For 16-bit color mode

Documentation/devicetree/bindings/dma/ti/k3-udma.yaml+1−13

@@ -143,7 +143,7 @@ examples: · 142 unmodified lines
143	#size-cells = <2>;	143	#size-cells = <2>;
144	dma-coherent;	144	dma-coherent;
145	dma-ranges;	145	dma-ranges;
146	ranges;	146	ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
147		147
148	ti,sci-dev-id = <118>;	148	ti,sci-dev-id = <118>;
149		149
@@ -169,16 +169,4 @@ examples: · 19 unmodified lines
169	ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */	169	ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
170	};	170	};
171	};	171	};
172
173	mcasp0: mcasp@02B00000 {
174	dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
175	dma-names = "tx", "rx";
176	};
177
178	crypto: crypto@4E00000 {
179	compatible = "ti,sa2ul-crypto";
180
181	dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>;
182	dma-names = "tx", "rx1", "rx2";
183	};
184	};	172	};

Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml+7−7

@@ -84,31 +84,31 @@ examples: · 83 unmodified lines
84	gpu_opp_table: opp_table0 {	84	gpu_opp_table: opp_table0 {
85	compatible = "operating-points-v2";	85	compatible = "operating-points-v2";
86		86
87	opp@533000000 {	87	opp-533000000 {
88	opp-hz = /bits/ 64 <533000000>;	88	opp-hz = /bits/ 64 <533000000>;
89	opp-microvolt = <1250000>;	89	opp-microvolt = <1250000>;
90	};	90	};
91	opp@450000000 {	91	opp-450000000 {
92	opp-hz = /bits/ 64 <450000000>;	92	opp-hz = /bits/ 64 <450000000>;
93	opp-microvolt = <1150000>;	93	opp-microvolt = <1150000>;
94	};	94	};
95	opp@400000000 {	95	opp-400000000 {
96	opp-hz = /bits/ 64 <400000000>;	96	opp-hz = /bits/ 64 <400000000>;
97	opp-microvolt = <1125000>;	97	opp-microvolt = <1125000>;
98	};	98	};
99	opp@350000000 {	99	opp-350000000 {
100	opp-hz = /bits/ 64 <350000000>;	100	opp-hz = /bits/ 64 <350000000>;
101	opp-microvolt = <1075000>;	101	opp-microvolt = <1075000>;
102	};	102	};
103	opp@266000000 {	103	opp-266000000 {
104	opp-hz = /bits/ 64 <266000000>;	104	opp-hz = /bits/ 64 <266000000>;
105	opp-microvolt = <1025000>;	105	opp-microvolt = <1025000>;
106	};	106	};
107	opp@160000000 {	107	opp-160000000 {
108	opp-hz = /bits/ 64 <160000000>;	108	opp-hz = /bits/ 64 <160000000>;
109	opp-microvolt = <925000>;	109	opp-microvolt = <925000>;
110	};	110	};
111	opp@100000000 {	111	opp-100000000 {
112	opp-hz = /bits/ 64 <100000000>;	112	opp-hz = /bits/ 64 <100000000>;
113	opp-microvolt = <912500>;	113	opp-microvolt = <912500>;
114	};	114	};

Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml+7−7

@@ -138,31 +138,31 @@ examples: · 137 unmodified lines
138	gpu_opp_table: opp_table0 {	138	gpu_opp_table: opp_table0 {
139	compatible = "operating-points-v2";	139	compatible = "operating-points-v2";
140		140
141	opp@533000000 {	141	opp-533000000 {
142	opp-hz = /bits/ 64 <533000000>;	142	opp-hz = /bits/ 64 <533000000>;
143	opp-microvolt = <1250000>;	143	opp-microvolt = <1250000>;
144	};	144	};
145	opp@450000000 {	145	opp-450000000 {
146	opp-hz = /bits/ 64 <450000000>;	146	opp-hz = /bits/ 64 <450000000>;
147	opp-microvolt = <1150000>;	147	opp-microvolt = <1150000>;
148	};	148	};
149	opp@400000000 {	149	opp-400000000 {
150	opp-hz = /bits/ 64 <400000000>;	150	opp-hz = /bits/ 64 <400000000>;
151	opp-microvolt = <1125000>;	151	opp-microvolt = <1125000>;
152	};	152	};
153	opp@350000000 {	153	opp-350000000 {
154	opp-hz = /bits/ 64 <350000000>;	154	opp-hz = /bits/ 64 <350000000>;
155	opp-microvolt = <1075000>;	155	opp-microvolt = <1075000>;
156	};	156	};
157	opp@266000000 {	157	opp-266000000 {
158	opp-hz = /bits/ 64 <266000000>;	158	opp-hz = /bits/ 64 <266000000>;
159	opp-microvolt = <1025000>;	159	opp-microvolt = <1025000>;
160	};	160	};
161	opp@160000000 {	161	opp-160000000 {
162	opp-hz = /bits/ 64 <160000000>;	162	opp-hz = /bits/ 64 <160000000>;
163	opp-microvolt = <925000>;	163	opp-microvolt = <925000>;
164	};	164	};
165	opp@100000000 {	165	opp-100000000 {
166	opp-hz = /bits/ 64 <100000000>;	166	opp-hz = /bits/ 64 <100000000>;
167	opp-microvolt = <912500>;	167	opp-microvolt = <912500>;
168	};	168	};

Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml+1−1

@@ -123,7 +123,7 @@ examples: · 122 unmodified lines
123	samsung,syscon-phandle = <&pmu_system_controller>;	123	samsung,syscon-phandle = <&pmu_system_controller>;
124		124
125	/* NTC thermistor is a hwmon device */	125	/* NTC thermistor is a hwmon device */
126	ncp15wb473@0 {	126	ncp15wb473 {
127	compatible = "murata,ncp15wb473";	127	compatible = "murata,ncp15wb473";
128	pullup-uv = <1800000>;	128	pullup-uv = <1800000>;
129	pullup-ohm = <47000>;	129	pullup-ohm = <47000>;

Documentation/devicetree/bindings/input/touchscreen/goodix.yaml+1−1

@@ -62,7 +62,7 @@ required: · 61 unmodified lines
62		62
63	examples:	63	examples:
64	- \|	64	- \|
65	i2c@00000000 {	65	i2c {
66	#address-cells = <1>;	66	#address-cells = <1>;
67	#size-cells = <0>;	67	#size-cells = <0>;
68	gt928@5d {	68	gt928@5d {

Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt+1−1

@@ -1,7 +1,7 @@
1	Texas Instruments TWL family (twl4030) pwrbutton module	1	Texas Instruments TWL family (twl4030) pwrbutton module
2		2
3	This module is part of the TWL4030. For more details about the whole	3	This module is part of the TWL4030. For more details about the whole
4	chip see Documentation/devicetree/bindings/mfd/twl-familly.txt.	4	chip see Documentation/devicetree/bindings/mfd/twl-family.txt.
5		5
6	This module provides a simple power button event via an Interrupt.	6	This module provides a simple power button event via an Interrupt.
7		7

Documentation/devicetree/bindings/leds/common.yaml+1−1

@@ -85,7 +85,7 @@ properties: · 84 unmodified lines
85	# LED will act as a back-light, controlled by the framebuffer system	85	# LED will act as a back-light, controlled by the framebuffer system
86	- backlight	86	- backlight
87	# LED will turn on (but for leds-gpio see "default-state" property in	87	# LED will turn on (but for leds-gpio see "default-state" property in
88	# Documentation/devicetree/bindings/leds/leds-gpio.txt)	88	# Documentation/devicetree/bindings/leds/leds-gpio.yaml)
89	- default-on	89	- default-on
90	# LED "double" flashes at a load average based rate	90	# LED "double" flashes at a load average based rate
91	- heartbeat	91	- heartbeat

Documentation/devicetree/bindings/leds/register-bit-led.txt+1−1

@@ -5,7 +5,7 @@ where single bits in a certain register can turn on/off a · 4 unmodified lines
5	single LED. The register bit LEDs appear as children to the	5	single LED. The register bit LEDs appear as children to the
6	syscon device, with the proper compatible string. For the	6	syscon device, with the proper compatible string. For the
7	syscon bindings see:	7	syscon bindings see:
8	Documentation/devicetree/bindings/mfd/syscon.txt	8	Documentation/devicetree/bindings/mfd/syscon.yaml
9		9
10	Each LED is represented as a sub-node of the syscon device. Each	10	Each LED is represented as a sub-node of the syscon device. Each
11	node's name represents the name of the corresponding LED.	11	node's name represents the name of the corresponding LED.

Documentation/devicetree/bindings/media/ti,cal.yaml+1−1

@@ -177,7 +177,7 @@ examples: · 176 unmodified lines
177	};	177	};
178	};	178	};
179		179
180	i2c5: i2c@4807c000 {	180	i2c {
181	clock-frequency = <400000>;	181	clock-frequency = <400000>;
182	#address-cells = <1>;	182	#address-cells = <1>;
183	#size-cells = <0>;	183	#size-cells = <0>;

Documentation/devicetree/bindings/memory-controllers/ti/emif.txt+1−1

@@ -32,7 +32,7 @@ Required only for "ti,emif-am3352" and "ti,emif-am4372": · 31 unmodified lines
32	- sram : Phandles for generic sram driver nodes,	32	- sram : Phandles for generic sram driver nodes,
33	first should be type 'protect-exec' for the driver to use to copy	33	first should be type 'protect-exec' for the driver to use to copy
34	and run PM functions, second should be regular pool to be used for	34	and run PM functions, second should be regular pool to be used for
35	data region for code. See Documentation/devicetree/bindings/sram/sram.txt	35	data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
36	for more details.	36	for more details.
37		37
38	Optional properties:	38	Optional properties:

Documentation/devicetree/bindings/mfd/max77650.yaml+2−2

@@ -97,14 +97,14 @@ examples: · 96 unmodified lines
97	regulators {	97	regulators {
98	compatible = "maxim,max77650-regulator";	98	compatible = "maxim,max77650-regulator";
99		99
100	max77650_ldo: regulator@0 {	100	max77650_ldo: regulator-ldo {
101	regulator-compatible = "ldo";	101	regulator-compatible = "ldo";
102	regulator-name = "max77650-ldo";	102	regulator-name = "max77650-ldo";
103	regulator-min-microvolt = <1350000>;	103	regulator-min-microvolt = <1350000>;
104	regulator-max-microvolt = <2937500>;	104	regulator-max-microvolt = <2937500>;
105	};	105	};
106		106
107	max77650_sbb0: regulator@1 {	107	max77650_sbb0: regulator-sbb0 {
108	regulator-compatible = "sbb0";	108	regulator-compatible = "sbb0";
109	regulator-name = "max77650-sbb0";	109	regulator-name = "max77650-sbb0";
110	regulator-min-microvolt = <800000>;	110	regulator-min-microvolt = <800000>;

Documentation/devicetree/bindings/mfd/tps65910.txt+2−2

@@ -26,8 +26,8 @@ Required properties: · 25 unmodified lines
26	ldo6, ldo7, ldo8	26	ldo6, ldo7, ldo8
27		27
28	- xxx-supply: Input voltage supply regulator.	28	- xxx-supply: Input voltage supply regulator.
29	These entries are require if regulators are enabled for a device. Missing of these	29	These entries are required if regulators are enabled for a device. Missing these
30	properties can cause the regulator registration fails.	30	properties can cause the regulator registration to fail.
31	If some of input supply is powered through battery or always-on supply then	31	If some of input supply is powered through battery or always-on supply then
32	also it is require to have these parameters with proper node handle of always	32	also it is require to have these parameters with proper node handle of always
33	on power supply.	33	on power supply.

Documentation/devicetree/bindings/mfd/twl-family.txtrenamed from Documentation/devicetree/bindings/mfd/twl-familly.txt+0−0

File renamed without changes.

Documentation/devicetree/bindings/mfd/zii,rave-sp.txt+1−1

@@ -20,7 +20,7 @@ RAVE SP consists of the following sub-devices: · 19 unmodified lines
20	Device Description	20	Device Description
21	------ -----------	21	------ -----------
22	rave-sp-wdt : Watchdog	22	rave-sp-wdt : Watchdog
23	rave-sp-nvmem : Interface to onborad EEPROM	23	rave-sp-nvmem : Interface to onboard EEPROM
24	rave-sp-backlight : Display backlight	24	rave-sp-backlight : Display backlight
25	rave-sp-hwmon : Interface to onboard hardware sensors	25	rave-sp-hwmon : Interface to onboard hardware sensors
26	rave-sp-leds : Interface to onboard LEDs	26	rave-sp-leds : Interface to onboard LEDs

Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt+1−1

@@ -26,7 +26,7 @@ For generic IOMMU bindings, see · 25 unmodified lines
26	Documentation/devicetree/bindings/iommu/iommu.txt.	26	Documentation/devicetree/bindings/iommu/iommu.txt.
27		27
28	For arm-smmu binding, see:	28	For arm-smmu binding, see:
29	Documentation/devicetree/bindings/iommu/arm,smmu.txt.	29	Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
30		30
31	Required properties:	31	Required properties:
32		32

Documentation/devicetree/bindings/mmc/mmc-controller.yaml+1−0

@@ -370,6 +370,7 @@ examples: · 369 unmodified lines
370	mmc3: mmc@1c12000 {	370	mmc3: mmc@1c12000 {
371	#address-cells = <1>;	371	#address-cells = <1>;
372	#size-cells = <0>;	372	#size-cells = <0>;
		373	reg = <0x1c12000 0x200>;
373	pinctrl-names = "default";	374	pinctrl-names = "default";
374	pinctrl-0 = <&mmc3_pins_a>;	375	pinctrl-0 = <&mmc3_pins_a>;
375	vmmc-supply = <&reg_vmmc3>;	376	vmmc-supply = <&reg_vmmc3>;

Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt+1−1

@@ -27,7 +27,7 @@ Required properties of NAND chips: · 26 unmodified lines
27	- reg: shall contain the native Chip Select ids from 0 to max supported by	27	- reg: shall contain the native Chip Select ids from 0 to max supported by
28	the cadence nand flash controller	28	the cadence nand flash controller
29		29
30	See Documentation/devicetree/bindings/mtd/nand.txt for more details on	30	See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
31	generic bindings.	31	generic bindings.
32		32
33	Example:	33	Example:

Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt+1−1

@@ -45,7 +45,7 @@ Optional properties: · 44 unmodified lines
45	switch queue	45	switch queue
46		46
47	- resets: a single phandle and reset identifier pair. See	47	- resets: a single phandle and reset identifier pair. See
48	Documentation/devicetree/binding/reset/reset.txt for details.	48	Documentation/devicetree/bindings/reset/reset.txt for details.
49		49
50	- reset-names: If the "reset" property is specified, this property should have	50	- reset-names: If the "reset" property is specified, this property should have
51	the value "switch" to denote the switch reset line.	51	the value "switch" to denote the switch reset line.

Documentation/devicetree/bindings/nvmem/nvmem.yaml+2−0

@@ -76,6 +76,8 @@ examples: · 75 unmodified lines
76	qfprom: eeprom@700000 {	76	qfprom: eeprom@700000 {
77	#address-cells = <1>;	77	#address-cells = <1>;
78	#size-cells = <1>;	78	#size-cells = <1>;
		79	reg = <0x00700000 0x100000>;
		80
79	wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;	81	wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
80		82
81	/* ... */	83	/* ... */

Documentation/devicetree/bindings/phy/allwinner,sun4i-a10-usb-phy.yaml+1−1

@@ -86,7 +86,7 @@ examples: · 85 unmodified lines
86	#include <dt-bindings/clock/sun4i-a10-ccu.h>	86	#include <dt-bindings/clock/sun4i-a10-ccu.h>
87	#include <dt-bindings/reset/sun4i-a10-ccu.h>	87	#include <dt-bindings/reset/sun4i-a10-ccu.h>
88		88
89	usbphy: phy@01c13400 {	89	usbphy: phy@1c13400 {
90	#phy-cells = <1>;	90	#phy-cells = <1>;
91	compatible = "allwinner,sun4i-a10-usb-phy";	91	compatible = "allwinner,sun4i-a10-usb-phy";
92	reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;	92	reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;

Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml+1−1

@@ -17,7 +17,7 @@ description: \|+ · 16 unmodified lines
17	"aspeed,ast2400-scu", "syscon", "simple-mfd"	17	"aspeed,ast2400-scu", "syscon", "simple-mfd"
18		18
19	Refer to the the bindings described in	19	Refer to the the bindings described in
20	Documentation/devicetree/bindings/mfd/syscon.txt	20	Documentation/devicetree/bindings/mfd/syscon.yaml
21		21
22	properties:	22	properties:
23	compatible:	23	compatible:

Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml+1−1

@@ -18,7 +18,7 @@ description: \|+ · 17 unmodified lines
18	"aspeed,g5-scu", "syscon", "simple-mfd"	18	"aspeed,g5-scu", "syscon", "simple-mfd"
19		19
20	Refer to the the bindings described in	20	Refer to the the bindings described in
21	Documentation/devicetree/bindings/mfd/syscon.txt	21	Documentation/devicetree/bindings/mfd/syscon.yaml
22		22
23	properties:	23	properties:
24	compatible:	24	compatible:

Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml+1−1

@@ -17,7 +17,7 @@ description: \|+ · 16 unmodified lines
17	"aspeed,ast2600-scu", "syscon", "simple-mfd"	17	"aspeed,ast2600-scu", "syscon", "simple-mfd"
18		18
19	Refer to the the bindings described in	19	Refer to the the bindings described in
20	Documentation/devicetree/bindings/mfd/syscon.txt	20	Documentation/devicetree/bindings/mfd/syscon.yaml
21		21
22	properties:	22	properties:
23	compatible:	23	compatible:

Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml+1−1

@@ -248,7 +248,7 @@ examples: · 247 unmodified lines
248	};	248	};
249		249
250	//Example 3 pin groups	250	//Example 3 pin groups
251	pinctrl@60020000 {	251	pinctrl {
252	usart1_pins_a: usart1-0 {	252	usart1_pins_a: usart1-0 {
253	pins1 {	253	pins1 {
254	pinmux = <STM32_PINMUX('A', 9, AF7)>;	254	pinmux = <STM32_PINMUX('A', 9, AF7)>;

Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml+1−1

@@ -18,7 +18,7 @@ description: \|+ · 17 unmodified lines
18	"amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"	18	"amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"
19		19
20	Refer to the the bindings described in	20	Refer to the the bindings described in
21	Documentation/devicetree/bindings/mfd/syscon.txt	21	Documentation/devicetree/bindings/mfd/syscon.yaml
22		22
23	properties:	23	properties:
24	compatible:	24	compatible:

Documentation/devicetree/bindings/power/domain-idle-state.txt+0−33

@@ -1,33 +0,0 @@
1	PM Domain Idle State Node:
2
3	A domain idle state node represents the state parameters that will be used to
4	select the state when there are no active components in the domain.
5
6	The state node has the following parameters -
7
8	- compatible:
9	Usage: Required
10	Value type: <string>
11	Definition: Must be "domain-idle-state".
12
13	- entry-latency-us
14	Usage: Required
15	Value type: <prop-encoded-array>
16	Definition: u32 value representing worst case latency in
17	microseconds required to enter the idle state.
18	The exit-latency-us duration may be guaranteed
19	only after entry-latency-us has passed.
20
21	- exit-latency-us
22	Usage: Required
23	Value type: <prop-encoded-array>
24	Definition: u32 value representing worst case latency
25	in microseconds required to exit the idle state.
26
27	- min-residency-us
28	Usage: Required
29	Value type: <prop-encoded-array>
30	Definition: u32 value representing minimum residency duration
31	in microseconds after which the idle state will yield
32	power benefits after overcoming the overhead in entering
33	i the idle state.

Documentation/devicetree/bindings/power/domain-idle-state.yaml+64−0

@@ -0,0 +1,64 @@
	1	# SPDX-License-Identifier: GPL-2.0
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: PM Domain Idle States binding description
	8
	9	maintainers:
	10	- Ulf Hansson <ulf.hansson@linaro.org>
	11
	12	description:
	13	A domain idle state node represents the state parameters that will be used to
	14	select the state when there are no active components in the PM domain.
	15
	16	properties:
	17	$nodename:
	18	const: domain-idle-states
	19
	20	patternProperties:
	21	"^(cpu\|cluster\|domain)-":
	22	type: object
	23	description:
	24	Each state node represents a domain idle state description.
	25
	26	properties:
	27	compatible:
	28	const: domain-idle-state
	29
	30	entry-latency-us:
	31	description:
	32	The worst case latency in microseconds required to enter the idle
	33	state. Note that, the exit-latency-us duration may be guaranteed only
	34	after the entry-latency-us has passed.
	35
	36	exit-latency-us:
	37	description:
	38	The worst case latency in microseconds required to exit the idle
	39	state.
	40
	41	min-residency-us:
	42	description:
	43	The minimum residency duration in microseconds after which the idle
	44	state will yield power benefits, after overcoming the overhead while
	45	entering the idle state.
	46
	47	required:
	48	- compatible
	49	- entry-latency-us
	50	- exit-latency-us
	51	- min-residency-us
	52
	53	examples:
	54	- \|
	55
	56	domain-idle-states {
	57	domain_retention: domain-retention {
	58	compatible = "domain-idle-state";
	59	entry-latency-us = <20>;
	60	exit-latency-us = <40>;
	61	min-residency-us = <80>;
	62	};
	63	};
	64	...

Documentation/devicetree/bindings/power/power-domain.yaml+11−13

@@ -25,22 +25,20 @@ description: \|+ · 24 unmodified lines
25		25
26	properties:	26	properties:
27	$nodename:	27	$nodename:
28	pattern: "^(power-controller\|power-domain)(@.*)?$"	28	pattern: "^(power-controller\|power-domain)([@-].*)?$"
29		29
30	domain-idle-states:	30	domain-idle-states:
31	$ref: /schemas/types.yaml#/definitions/phandle-array	31	$ref: /schemas/types.yaml#/definitions/phandle-array
32	description:	32	description: \|
33	A phandle of an idle-state that shall be soaked into a generic domain	33	Phandles of idle states that defines the available states for the
34	power state. The idle state definitions are compatible with	34	power-domain provider. The idle state definitions are compatible with the
35	domain-idle-state specified in	35	domain-idle-state bindings, specified in ./domain-idle-state.yaml.
36	Documentation/devicetree/bindings/power/domain-idle-state.txt	36
37	phandles that are not compatible with domain-idle-state will be ignored.	37	Note that, the domain-idle-state property reflects the idle states of this
38	The domain-idle-state property reflects the idle state of this PM domain	38	PM domain and not the idle states of the devices or sub-domains in the PM
39	and not the idle states of the devices or sub-domains in the PM domain.	39	domain. Devices and sub-domains have their own idle states independent of
40	Devices and sub-domains have their own idle-states independent	40	the parent domain's idle states. In the absence of this property, the
41	of the parent domain's idle states. In the absence of this property,	41	domain would be considered as capable of being powered-on or powered-off.
42	the domain would be considered as capable of being powered-on
43	or powered-off.
44		42
45	operating-points-v2:	43	operating-points-v2:
46	$ref: /schemas/types.yaml#/definitions/phandle-array	44	$ref: /schemas/types.yaml#/definitions/phandle-array

Documentation/devicetree/bindings/power/power_domain.txt+1−1

@@ -109,4 +109,4 @@ Example: · 108 unmodified lines
109	required-opps = <&domain1_opp_1>;	109	required-opps = <&domain1_opp_1>;
110	};	110	};
111		111
112	[1]. Documentation/devicetree/bindings/power/domain-idle-state.txt	112	[1]. Documentation/devicetree/bindings/power/domain-idle-state.yaml

Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt+1−1

@@ -161,7 +161,7 @@ The regulator node houses sub-nodes for each regulator within the device. Each · 160 unmodified lines
161	sub-node is identified using the node's name, with valid values listed for each	161	sub-node is identified using the node's name, with valid values listed for each
162	of the PMICs below.	162	of the PMICs below.
163		163
164	pm8005:	164	pm8004:
165	s2, s5	165	s2, s5
166		166
167	pm8005:	167	pm8005:

Documentation/devicetree/bindings/regulator/regulator.yaml+1−1

@@ -191,7 +191,7 @@ patternProperties: · 190 unmodified lines
191		191
192	examples:	192	examples:
193	- \|	193	- \|
194	xyzreg: regulator@0 {	194	xyzreg: regulator {
195	regulator-min-microvolt = <1000000>;	195	regulator-min-microvolt = <1000000>;
196	regulator-max-microvolt = <2500000>;	196	regulator-max-microvolt = <2500000>;
197	regulator-always-on;	197	regulator-always-on;

Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml+5−1

     description: Global reset register offset and bit offset.
     allOf:
       - $ref: /schemas/types.yaml#/definitions/uint32-array
-      - maxItems: 2
+    items:
+      - description: Register offset
+      - description: Register bit offset
+        minimum: 0
+        maximum: 31
   "#reset-cells":
     minimum: 2

Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt+1−1

@@ -3,4 +3,4 @@ STMicroelectronics STM32MP1 Peripheral Reset Controller · 2 unmodified lines
3		3
4	The RCC IP is both a reset and a clock controller.	4	The RCC IP is both a reset and a clock controller.
5		5
6	Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt	6	Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml

Documentation/devicetree/bindings/sound/st,stm32-sai.txt+1−1

@@ -36,7 +36,7 @@ SAI subnodes required properties: · 35 unmodified lines
36	- clock-names: Must contain "sai_ck".	36	- clock-names: Must contain "sai_ck".
37	Must also contain "MCLK", if SAI shares a master clock,	37	Must also contain "MCLK", if SAI shares a master clock,
38	with a SAI set as MCLK clock provider.	38	with a SAI set as MCLK clock provider.
39	- dmas: see Documentation/devicetree/bindings/dma/stm32-dma.txt	39	- dmas: see Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
40	- dma-names: identifier string for each DMA request line	40	- dma-names: identifier string for each DMA request line
41	"tx": if sai sub-block is configured as playback DAI	41	"tx": if sai sub-block is configured as playback DAI
42	"rx": if sai sub-block is configured as capture DAI	42	"rx": if sai sub-block is configured as capture DAI

Documentation/devicetree/bindings/sound/st,stm32-spdifrx.txt+1−1

@@ -10,7 +10,7 @@ Required properties: · 9 unmodified lines
10	- clock-names: must contain "kclk"	10	- clock-names: must contain "kclk"
11	- interrupts: cpu DAI interrupt line	11	- interrupts: cpu DAI interrupt line
12	- dmas: DMA specifiers for audio data DMA and iec control flow DMA	12	- dmas: DMA specifiers for audio data DMA and iec control flow DMA
13	See STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt	13	See STM32 DMA bindings, Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
14	- dma-names: two dmas have to be defined, "rx" and "rx-ctrl"	14	- dma-names: two dmas have to be defined, "rx" and "rx-ctrl"
15		15
16	Optional properties:	16	Optional properties:

Documentation/devicetree/bindings/spi/st,stm32-spi.yaml+1−1

@@ -49,7 +49,7 @@ properties: · 48 unmodified lines
49	dmas:	49	dmas:
50	description: \|	50	description: \|
51	DMA specifiers for tx and rx dma. DMA fifo mode must be used. See	51	DMA specifiers for tx and rx dma. DMA fifo mode must be used. See
52	the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32-dma.txt.	52	the STM32 DMA bindings Documentation/devicetree/bindings/dma/st,stm32-dma.yaml.
53	items:	53	items:
54	- description: rx DMA channel	54	- description: rx DMA channel
55	- description: tx DMA channel	55	- description: tx DMA channel

Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml+1−1

@@ -125,7 +125,7 @@ examples: · 124 unmodified lines
125	#size-cells = <1>;	125	#size-cells = <1>;
126	ranges;	126	ranges;
127		127
128	sram_a: sram@00000000 {	128	sram_a: sram@0 {
129	compatible = "mmio-sram";	129	compatible = "mmio-sram";
130	reg = <0x00000000 0xc000>;	130	reg = <0x00000000 0xc000>;
131	#address-cells = <1>;	131	#address-cells = <1>;

Documentation/devicetree/bindings/thermal/brcm,avs-ro-thermal.yaml+1−1

@@ -17,7 +17,7 @@ description: \|+ · 16 unmodified lines
17	"brcm,bcm2711-avs-monitor", "syscon", "simple-mfd"	17	"brcm,bcm2711-avs-monitor", "syscon", "simple-mfd"
18		18
19	Refer to the the bindings described in	19	Refer to the the bindings described in
20	Documentation/devicetree/bindings/mfd/syscon.txt	20	Documentation/devicetree/bindings/mfd/syscon.yaml
21		21
22	properties:	22	properties:
23	compatible:	23	compatible:

Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml+1−1

@@ -87,7 +87,7 @@ additionalProperties: false · 86 unmodified lines
87		87
88	examples:	88	examples:
89	- \|	89	- \|
90	timer {	90	timer@1c20c00 {
91	compatible = "allwinner,sun4i-a10-timer";	91	compatible = "allwinner,sun4i-a10-timer";
92	reg = <0x01c20c00 0x400>;	92	reg = <0x01c20c00 0x400>;
93	interrupts = <22>,	93	interrupts = <22>,

Documentation/driver-api/dmaengine/client.rst+10−4

@@ -151,8 +151,8 @@ The details of these operations are: · 150 unmodified lines
151	Note that callbacks will always be invoked from the DMA	151	Note that callbacks will always be invoked from the DMA
152	engines tasklet, never from interrupt context.	152	engines tasklet, never from interrupt context.
153		153
154	Optional: per descriptor metadata	154	Optional: per descriptor metadata
155	---------------------------------	155
156	DMAengine provides two ways for metadata support.	156	DMAengine provides two ways for metadata support.
157		157
158	DESC_METADATA_CLIENT	158	DESC_METADATA_CLIENT
@@ -199,12 +199,15 @@ Optional: per descriptor metadata · 40 unmodified lines
199	DESC_METADATA_CLIENT	199	DESC_METADATA_CLIENT
200		200
201	- DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:	201	- DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
		202
202	1. prepare the descriptor (dmaengine_prep_*)	203	1. prepare the descriptor (dmaengine_prep_*)
203	construct the metadata in the client's buffer	204	construct the metadata in the client's buffer
204	2. use dmaengine_desc_attach_metadata() to attach the buffer to the	205	2. use dmaengine_desc_attach_metadata() to attach the buffer to the
205	descriptor	206	descriptor
206	3. submit the transfer	207	3. submit the transfer
		208
207	- DMA_DEV_TO_MEM:	209	- DMA_DEV_TO_MEM:
		210
208	1. prepare the descriptor (dmaengine_prep_*)	211	1. prepare the descriptor (dmaengine_prep_*)
209	2. use dmaengine_desc_attach_metadata() to attach the buffer to the	212	2. use dmaengine_desc_attach_metadata() to attach the buffer to the
210	descriptor	213	descriptor
@@ -215,6 +218,7 @@ Optional: per descriptor metadata · 4 unmodified lines
215	DESC_METADATA_ENGINE	218	DESC_METADATA_ENGINE
216		219
217	- DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:	220	- DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
		221
218	1. prepare the descriptor (dmaengine_prep_*)	222	1. prepare the descriptor (dmaengine_prep_*)
219	2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the	223	2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the
220	engine's metadata area	224	engine's metadata area
@@ -222,7 +226,9 @@ Optional: per descriptor metadata · 1 unmodified line
222	4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the	226	4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the
223	amount of data the client has placed into the metadata buffer	227	amount of data the client has placed into the metadata buffer
224	5. submit the transfer	228	5. submit the transfer
		229
225	- DMA_DEV_TO_MEM:	230	- DMA_DEV_TO_MEM:
		231
226	1. prepare the descriptor (dmaengine_prep_*)	232	1. prepare the descriptor (dmaengine_prep_*)
227	2. submit the transfer	233	2. submit the transfer
228	3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get	234	3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get
@@ -278,8 +284,8 @@ Optional: per descriptor metadata · 49 unmodified lines
278		284
279	void dma_async_issue_pending(struct dma_chan *chan);	285	void dma_async_issue_pending(struct dma_chan *chan);
280		286
281	Further APIs:	287	Further APIs
282	-------------	288	------------
283		289
284	1. Terminate APIs	290	1. Terminate APIs
285		291

Documentation/filesystems/debugfs.txt+3−3

@@ -164,9 +164,9 @@ file. · 163 unmodified lines
164	void __iomem *base;	164	void __iomem *base;
165	};	165	};
166		166
167	struct dentry debugfs_create_regset32(const char name, umode_t mode,	167	debugfs_create_regset32(const char *name, umode_t mode,
168	struct dentry *parent,	168	struct dentry *parent,
169	struct debugfs_regset32 *regset);	169	struct debugfs_regset32 *regset);
170		170
171	void debugfs_print_regs32(struct seq_file s, struct debugfs_reg32 regs,	171	void debugfs_print_regs32(struct seq_file s, struct debugfs_reg32 regs,
172	int nregs, void __iomem base, char prefix);	172	int nregs, void __iomem base, char prefix);

Documentation/hwmon/adm1177.rst+1−2

@@ -20,8 +20,7 @@ Usage Notes · 19 unmodified lines
20	-----------	20	-----------
21		21
22	This driver does not auto-detect devices. You will have to instantiate the	22	This driver does not auto-detect devices. You will have to instantiate the
23	devices explicitly. Please see Documentation/i2c/instantiating-devices for	23	devices explicitly. Please see :doc:`/i2c/instantiating-devices` for details.
24	details.
25		24
26		25
27	Sysfs entries	26	Sysfs entries

MAINTAINERS+11−10

 M:	Yangtao Li <tiny.windzz@gmail.com>
 L:	linux-pm@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt
+F:	Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
 F:	drivers/cpufreq/sun50i-cpufreq-nvmem.c
 ALLWINNER CRYPTO DRIVERS
 S:	Maintained
 R:	Enric Balletbo i Serra <enric.balletbo@collabora.com>
 R:	Guenter Roeck <groeck@chromium.org>
-F:	Documentation/devicetree/bindings/sound/google,cros-ec-codec.txt
+F:	Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml
 F:	sound/soc/codecs/cros_ec_codec.*
 CIRRUS LOGIC AUDIO CODEC DRIVERS
 T:	git git://linuxtv.org/media_tree.git
 S:	Maintained
 F:	drivers/media/platform/sunxi/sun6i-csi/
-F:	Documentation/devicetree/bindings/media/sun6i-csi.txt
+F:	Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
 CW1200 WLAN driver
 M:	Solomon Peachy <pizza@shaftnet.org>
 T:	git git://anongit.freedesktop.org/drm/drm-misc
 S:	Maintained
 F:	drivers/gpu/drm/stm
-F:	Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+F:	Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
 DRM DRIVERS FOR TI LCDC
 M:	Jyri Sarha <jsarha@ti.com>
 M:	"K. Y. Srinivasan" <kys@microsoft.com>
 M:	Haiyang Zhang <haiyangz@microsoft.com>
 M:	Stephen Hemminger <sthemmin@microsoft.com>
-M:	Sasha Levin <sashal@kernel.org>
+M:	Wei Liu <wei.liu@kernel.org>
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git
 L:	linux-hyperv@vger.kernel.org
 S:	Supported
 M:	Andreas Klinger <ak@it-klinger.de>
 L:	linux-iio@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/iio/proximity/maxbotix,mb1232.txt
+F:	Documentation/devicetree/bindings/iio/proximity/maxbotix,mb1232.yaml
 F:	drivers/iio/proximity/mb1232.c
 MAXIM MAX77650 PMIC MFD DRIVER
 L:	linux-media@vger.kernel.org
 T:	git git://linuxtv.org/media_tree.git
 S:	Supported
-F:	Documentation/devicetree/bindings/media/st,stm32-dcmi.txt
+F:	Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
 F:	drivers/media/platform/stm32/stm32-dcmi.c
 MEDIA DRIVERS FOR NVIDIA TEGRA - VDE
 L:	linux-pci@vger.kernel.org
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Supported
-F:	Documentation/devicetree/bindings/pci/pci-thunder-*
 F:	drivers/pci/controller/pci-thunder-*
 PCIE DRIVER FOR HISILICON
 F:	include/linux/reset.h
 F:	include/linux/reset/
 F:	include/linux/reset-controller.h
-K:      \b(?:devm_|of_)?reset_control(?:ler_[a-z]+|_[a-z_]+)?\b
+K:	\b(?:devm_|of_)?reset_control(?:ler_[a-z]+|_[a-z_]+)?\b
 RESTARTABLE SEQUENCES SUPPORT
 M:	Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
 F:	drivers/pwm/pwm-stm32*
 F:	include/linux/*/stm32-*tim*
 F:	Documentation/ABI/testing/*timer-stm32
-F:	Documentation/devicetree/bindings/*/stm32-*timer*
+F:	Documentation/devicetree/bindings/*/*stm32-*timer*
 F:	Documentation/devicetree/bindings/pwm/pwm-stm32*
 STMMAC ETHERNET DRIVER
 R:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 S:	Maintained
 F:	drivers/tty/serial/8250/8250_dw.c
+F:	drivers/tty/serial/8250/8250_dwlib.*
+F:	drivers/tty/serial/8250/8250_lpss.c
 SYNOPSYS DESIGNWARE APB GPIO DRIVER
 M:	Hoan Tran <hoan@os.amperecomputing.com>

Makefile+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	VERSION = 5	2	VERSION = 5
3	PATCHLEVEL = 6	3	PATCHLEVEL = 6
4	SUBLEVEL = 0	4	SUBLEVEL = 0
5	EXTRAVERSION = -rc4	5	EXTRAVERSION = -rc5
6	NAME = Kleptomaniac Octopus	6	NAME = Kleptomaniac Octopus
7		7
8	# DOCUMENTATION	8	# DOCUMENTATION

arch/Kconfig+3−2

 config HAVE_RELIABLE_STACKTRACE
 	bool
 	help
-	  Architecture has a save_stack_trace_tsk_reliable() function which
+	  Architecture has either save_stack_trace_tsk_reliable() or
-	  only returns a stack trace if it can guarantee the trace is reliable.
+	  arch_stack_walk_reliable() function which only returns a stack trace
+	  if it can guarantee the trace is reliable.
 config HAVE_ARCH_HASH
 	bool

arch/arm/boot/dts/am437x-idk-evm.dts+2−2

@@ -526,11 +526,11 @@ · 525 unmodified lines
526	* Supply voltage supervisor on board will not allow opp50 so	526	* Supply voltage supervisor on board will not allow opp50 so
527	* disable it and set opp100 as suspend OPP.	527	* disable it and set opp100 as suspend OPP.
528	*/	528	*/
529	opp50@300000000 {	529	opp50-300000000 {
530	status = "disabled";	530	status = "disabled";
531	};	531	};
532		532
533	opp100@600000000 {	533	opp100-600000000 {
534	opp-suspend;	534	opp-suspend;
535	};	535	};
536	};	536	};

arch/arm/boot/dts/bcm2711-rpi-4-b.dts+3−0

 	aliases {
 		ethernet0 = &genet;
+		pcie0 = &pcie0;
 	};
 	leds {
 		pwr {
 			label = "PWR";
 			gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+			linux,default-trigger = "default-on";
 		};
 	};

arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts+2−0

 		pwr {
 			label = "PWR";
 			gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+			linux,default-trigger = "default-on";
 		};
 	};
 };

arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts+2−0

@@ -27,6 +27,8 @@ · 26 unmodified lines
27	pwr {	27	pwr {
28	label = "PWR";	28	label = "PWR";
29	gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;	29	gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
		30	default-state = "keep";
		31	linux,default-trigger = "default-on";
30	};	32	};
31	};	33	};
32		34

arch/arm/boot/dts/dra7-evm.dts+2−2

@@ -61,10 +61,10 @@ · 60 unmodified lines
61	regulator-max-microvolt = <1800000>;	61	regulator-max-microvolt = <1800000>;
62	};	62	};
63		63
64	evm_3v3: fixedregulator-evm3v3 {	64	vsys_3v3: fixedregulator-vsys3v3 {
65	/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */	65	/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
66	compatible = "regulator-fixed";	66	compatible = "regulator-fixed";
67	regulator-name = "evm_3v3";	67	regulator-name = "vsys_3v3";
68	regulator-min-microvolt = <3300000>;	68	regulator-min-microvolt = <3300000>;
69	regulator-max-microvolt = <3300000>;	69	regulator-max-microvolt = <3300000>;
70	vin-supply = <&evm_12v0>;	70	vin-supply = <&evm_12v0>;

arch/arm/boot/dts/dra7-l4.dtsi+4−0

 				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
 				clock-names = "fck";
 				interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+				ti,timer-pwm;
 			};
 		};
 				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
 				clock-names = "fck";
 				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+				ti,timer-pwm;
 			};
 		};
 				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
 				clock-names = "fck";
 				interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+				ti,timer-pwm;
 			};
 		};
 				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
 				clock-names = "fck";
 				interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+				ti,timer-pwm;
 			};
 		};

arch/arm/boot/dts/dra7.dtsi+2−0

 				device_type = "pci";
 				ranges = <0x81000000 0 0          0x03000 0 0x00010000
 					  0x82000000 0 0x20013000 0x13000 0 0xffed000>;
+				dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
 				bus-range = <0x00 0xff>;
 				#interrupt-cells = <1>;
 				num-lanes = <1>;
 				device_type = "pci";
 				ranges = <0x81000000 0 0          0x03000 0 0x00010000
 					  0x82000000 0 0x30013000 0x13000 0 0xffed000>;
+				dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
 				bus-range = <0x00 0xff>;
 				#interrupt-cells = <1>;
 				num-lanes = <1>;

arch/arm/boot/dts/dra76x.dtsi+5−0

@@ -128,3 +128,8 @@ · 127 unmodified lines
128	&usb4_tm {	128	&usb4_tm {
129	status = "disabled";	129	status = "disabled";
130	};	130	};
		131
		132	&mmc3 {
		133	/* dra76x is not affected by i887 */
		134	max-frequency = <96000000>;
		135	};

arch/arm/boot/dts/dra7xx-clocks.dtsi+2−10

 		clock-div = <1>;
 	};
-	ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
-		ti,bit-shift = <24>;
-		reg = <0x0520>;
-		assigned-clocks = <&ipu1_gfclk_mux>;
-		assigned-clock-parents = <&dpll_core_h22x2_ck>;
-	};
 	dummy_ck: dummy_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 			compatible = "ti,clkctrl";
 			reg = <0x20 0x4>;
 			#clock-cells = <2>;
+			assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
+			assigned-clock-parents = <&dpll_core_h22x2_ck>;
 		};
 		ipu_clkctrl: ipu-clkctrl@50 {

arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts+2−2

@@ -275,7 +275,7 @@ · 274 unmodified lines
275		275
276	/* SRAM on Colibri nEXT_CS0 */	276	/* SRAM on Colibri nEXT_CS0 */
277	sram@0,0 {	277	sram@0,0 {
278	compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";	278	compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
279	reg = <0 0 0x00010000>;	279	reg = <0 0 0x00010000>;
280	#address-cells = <1>;	280	#address-cells = <1>;
281	#size-cells = <1>;	281	#size-cells = <1>;
@@ -286,7 +286,7 @@ · 4 unmodified lines
286		286
287	/* SRAM on Colibri nEXT_CS1 */	287	/* SRAM on Colibri nEXT_CS1 */
288	sram@1,0 {	288	sram@1,0 {
289	compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";	289	compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
290	reg = <1 0 0x00010000>;	290	reg = <1 0 0x00010000>;
291	#address-cells = <1>;	291	#address-cells = <1>;
292	#size-cells = <1>;	292	#size-cells = <1>;

arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi+0−1

@@ -192,7 +192,6 @@ · 191 unmodified lines
192	pinctrl-0 = <&pinctrl_usdhc4>;	192	pinctrl-0 = <&pinctrl_usdhc4>;
193	bus-width = <8>;	193	bus-width = <8>;
194	non-removable;	194	non-removable;
195	vmmc-supply = <&vdd_emmc_1p8>;
196	status = "disabled";	195	status = "disabled";
197	};	196	};
198		197

arch/arm/boot/dts/imx7-colibri.dtsi+0−1

@@ -336,7 +336,6 @@ · 335 unmodified lines
336	assigned-clock-rates = <400000000>;	336	assigned-clock-rates = <400000000>;
337	bus-width = <8>;	337	bus-width = <8>;
338	fsl,tuning-step = <2>;	338	fsl,tuning-step = <2>;
339	max-frequency = <100000000>;
340	vmmc-supply = <&reg_module_3v3>;	339	vmmc-supply = <&reg_module_3v3>;
341	vqmmc-supply = <&reg_DCDC3>;	340	vqmmc-supply = <&reg_DCDC3>;
342	non-removable;	341	non-removable;

arch/arm/boot/dts/imx7d.dtsi+3−3

@@ -44,7 +44,7 @@ · 43 unmodified lines
44	opp-hz = /bits/ 64 <792000000>;	44	opp-hz = /bits/ 64 <792000000>;
45	opp-microvolt = <1000000>;	45	opp-microvolt = <1000000>;
46	clock-latency-ns = <150000>;	46	clock-latency-ns = <150000>;
47	opp-supported-hw = <0xd>, <0xf>;	47	opp-supported-hw = <0xd>, <0x7>;
48	opp-suspend;	48	opp-suspend;
49	};	49	};
50		50
@@ -52,7 +52,7 @@ · 1 unmodified line
52	opp-hz = /bits/ 64 <996000000>;	52	opp-hz = /bits/ 64 <996000000>;
53	opp-microvolt = <1100000>;	53	opp-microvolt = <1100000>;
54	clock-latency-ns = <150000>;	54	clock-latency-ns = <150000>;
55	opp-supported-hw = <0xc>, <0xf>;	55	opp-supported-hw = <0xc>, <0x7>;
56	opp-suspend;	56	opp-suspend;
57	};	57	};
58		58
@@ -60,7 +60,7 @@ · 1 unmodified line
60	opp-hz = /bits/ 64 <1200000000>;	60	opp-hz = /bits/ 64 <1200000000>;
61	opp-microvolt = <1225000>;	61	opp-microvolt = <1225000>;
62	clock-latency-ns = <150000>;	62	clock-latency-ns = <150000>;
63	opp-supported-hw = <0x8>, <0xf>;	63	opp-supported-hw = <0x8>, <0x3>;
64	opp-suspend;	64	opp-suspend;
65	};	65	};
66	};	66	};

arch/arm/boot/dts/ls1021a.dtsi+2−2

@@ -747,7 +747,7 @@ · 746 unmodified lines
747	};	747	};
748		748
749	mdio0: mdio@2d24000 {	749	mdio0: mdio@2d24000 {
750	compatible = "fsl,etsec2-mdio";	750	compatible = "gianfar";
751	device_type = "mdio";	751	device_type = "mdio";
752	#address-cells = <1>;	752	#address-cells = <1>;
753	#size-cells = <0>;	753	#size-cells = <0>;
@@ -756,7 +756,7 @@ · 2 unmodified lines
756	};	756	};
757		757
758	mdio1: mdio@2d64000 {	758	mdio1: mdio@2d64000 {
759	compatible = "fsl,etsec2-mdio";	759	compatible = "gianfar";
760	device_type = "mdio";	760	device_type = "mdio";
761	#address-cells = <1>;	761	#address-cells = <1>;
762	#size-cells = <0>;	762	#size-cells = <0>;

arch/arm/boot/dts/motorola-mapphone-common.dtsi+11−2

 		pwm-names = "enable", "direction";
 		direction-duty-cycle-ns = <10000000>;
 	};
+	backlight: backlight {
+		compatible = "led-backlight";
+		leds = <&backlight_led>;
+		brightness-levels = <31 63 95 127 159 191 223 255>;
+		default-brightness-level = <6>;
+	};
 };
 &dss {
 		vddi-supply = <&lcd_regulator>;
 		reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;	/* gpio101 */
+		backlight = <&backlight>;
 		width-mm = <50>;
 		height-mm = <89>;
 		ramp-up-us = <1024>;
 		ramp-down-us = <8193>;
-		led@0 {
+		backlight_led: led@0 {
 			reg = <0>;
 			led-sources = <2>;
 			ti,led-mode = <0>;
 			label = ":backlight";
-			linux,default-trigger = "backlight";
 		};
 		led@1 {

arch/arm/boot/dts/r8a7779.dtsi+1−1

@@ -377,7 +377,7 @@ · 376 unmodified lines
377	};	377	};
378		378
379	sata: sata@fc600000 {	379	sata: sata@fc600000 {
380	compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";	380	compatible = "renesas,sata-r8a7779";
381	reg = <0xfc600000 0x200000>;	381	reg = <0xfc600000 0x200000>;
382	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;	382	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
383	clocks = <&mstp1_clks R8A7779_CLK_SATA>;	383	clocks = <&mstp1_clks R8A7779_CLK_SATA>;

arch/arm/configs/bcm2835_defconfig+1−0

@@ -178,6 +178,7 @@ CONFIG_SCHED_TRACER=y · 177 unmodified lines
178	CONFIG_STACK_TRACER=y	178	CONFIG_STACK_TRACER=y
179	CONFIG_FUNCTION_PROFILER=y	179	CONFIG_FUNCTION_PROFILER=y
180	CONFIG_TEST_KSTRTOX=y	180	CONFIG_TEST_KSTRTOX=y
		181	CONFIG_DEBUG_FS=y
181	CONFIG_KGDB=y	182	CONFIG_KGDB=y
182	CONFIG_KGDB_KDB=y	183	CONFIG_KGDB_KDB=y
183	CONFIG_STRICT_DEVMEM=y	184	CONFIG_STRICT_DEVMEM=y

arch/arm/configs/omap2plus_defconfig+1−0

@@ -375,6 +375,7 @@ CONFIG_BACKLIGHT_GENERIC=m · 374 unmodified lines
375	CONFIG_BACKLIGHT_PWM=m	375	CONFIG_BACKLIGHT_PWM=m
376	CONFIG_BACKLIGHT_PANDORA=m	376	CONFIG_BACKLIGHT_PANDORA=m
377	CONFIG_BACKLIGHT_GPIO=m	377	CONFIG_BACKLIGHT_GPIO=m
		378	CONFIG_BACKLIGHT_LED=m
378	CONFIG_FRAMEBUFFER_CONSOLE=y	379	CONFIG_FRAMEBUFFER_CONSOLE=y
379	CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y	380	CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
380	CONFIG_LOGO=y	381	CONFIG_LOGO=y

arch/arm/configs/socfpga_defconfig+1−0

@@ -157,6 +157,7 @@ CONFIG_NLS_ISO8859_1=y · 156 unmodified lines
157	CONFIG_PRINTK_TIME=y	157	CONFIG_PRINTK_TIME=y
158	CONFIG_DEBUG_INFO=y	158	CONFIG_DEBUG_INFO=y
159	CONFIG_MAGIC_SYSRQ=y	159	CONFIG_MAGIC_SYSRQ=y
		160	CONFIG_DEBUG_FS=y
160	CONFIG_DETECT_HUNG_TASK=y	161	CONFIG_DETECT_HUNG_TASK=y
161	# CONFIG_SCHED_DEBUG is not set	162	# CONFIG_SCHED_DEBUG is not set
162	CONFIG_FUNCTION_TRACER=y	163	CONFIG_FUNCTION_TRACER=y

arch/arm/mach-imx/Makefile+2−0

@@ -91,6 +91,8 @@ AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a · 90 unmodified lines
91	obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o	91	obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
92	obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o	92	obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o
93	endif	93	endif
		94	AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a
		95	obj-$(CONFIG_SOC_IMX6) += resume-imx6.o
94	obj-$(CONFIG_SOC_IMX6) += pm-imx6.o	96	obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
95		97
96	obj-$(CONFIG_SOC_IMX1) += mach-imx1.o	98	obj-$(CONFIG_SOC_IMX1) += mach-imx1.o

arch/arm/mach-imx/common.h+2−2

 int imx_cpu_kill(unsigned int cpu);
 #ifdef CONFIG_SUSPEND
-void v7_cpu_resume(void);
 void imx53_suspend(void __iomem *ocram_vbase);
 extern const u32 imx53_suspend_sz;
 void imx6_suspend(void __iomem *ocram_vbase);
 #else
-static inline void v7_cpu_resume(void) {}
 static inline void imx53_suspend(void __iomem *ocram_vbase) {}
 static const u32 imx53_suspend_sz;
 static inline void imx6_suspend(void __iomem *ocram_vbase) {}
 #endif
+void v7_cpu_resume(void);
 void imx6_pm_ccm_init(const char *ccm_compat);
 void imx6q_pm_init(void);
 void imx6dl_pm_init(void);

arch/arm/mach-imx/resume-imx6.S+24−0

@@ -0,0 +1,24 @@
	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
	2	/*
	3	* Copyright 2014 Freescale Semiconductor, Inc.
	4	*/
	5
	6	#include <linux/linkage.h>
	7	#include <asm/assembler.h>
	8	#include <asm/asm-offsets.h>
	9	#include <asm/hardware/cache-l2x0.h>
	10	#include "hardware.h"
	11
	12	/*
	13	* The following code must assume it is running from physical address
	14	* where absolute virtual addresses to the data section have to be
	15	* turned into relative ones.
	16	*/
	17
	18	ENTRY(v7_cpu_resume)
	19	bl v7_invalidate_l1
	20	#ifdef CONFIG_CACHE_L2X0
	21	bl l2c310_early_resume
	22	#endif
	23	b cpu_resume
	24	ENDPROC(v7_cpu_resume)

arch/arm/mach-imx/suspend-imx6.S+0−14

@@ -327,17 +327,3 @@ resume: · 326 unmodified lines
327		327
328	ret lr	328	ret lr
329	ENDPROC(imx6_suspend)	329	ENDPROC(imx6_suspend)
330
331	/*
332	* The following code must assume it is running from physical address
333	* where absolute virtual addresses to the data section have to be
334	* turned into relative ones.
335	*/
336
337	ENTRY(v7_cpu_resume)
338	bl v7_invalidate_l1
339	#ifdef CONFIG_CACHE_L2X0
340	bl l2c310_early_resume
341	#endif
342	b cpu_resume
343	ENDPROC(v7_cpu_resume)

arch/arm/mach-meson/Kconfig+0−1

@@ -9,7 +9,6 @@ menuconfig ARCH_MESON · 8 unmodified lines
9	select CACHE_L2X0	9	select CACHE_L2X0
10	select PINCTRL	10	select PINCTRL
11	select PINCTRL_MESON	11	select PINCTRL_MESON
12	select COMMON_CLK
13	select HAVE_ARM_SCU if SMP	12	select HAVE_ARM_SCU if SMP
14	select HAVE_ARM_TWD if SMP	13	select HAVE_ARM_TWD if SMP
15		14

arch/arm/mach-omap2/Makefile+1−1

@@ -16,7 +16,7 @@ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ · 15 unmodified lines
16	clock-common = clock.o	16	clock-common = clock.o
17	secure-common = omap-smc.o omap-secure.o	17	secure-common = omap-smc.o omap-secure.o
18		18
19	obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)	19	obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
20	obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)	20	obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
21	obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)	21	obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
22	obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)	22	obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)

arch/arm/mach-omap2/io.c+0−2

 	omap_hwmod_init_postsetup();
 	omap_clk_soc_init = omap2420_dt_clk_init;
 	rate_table = omap2420_rate_table;
-	omap_secure_init();
 }
 void __init omap2420_init_late(void)
 	omap_hwmod_init_postsetup();
 	omap_clk_soc_init = omap2430_dt_clk_init;
 	rate_table = omap2430_rate_table;
-	omap_secure_init();
 }
 void __init omap2430_init_late(void)

arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts+1−1

@@ -327,7 +327,7 @@ · 326 unmodified lines
327	#size-cells = <0>;	327	#size-cells = <0>;
328		328
329	bus-width = <4>;	329	bus-width = <4>;
330	max-frequency = <50000000>;	330	max-frequency = <60000000>;
331		331
332	non-removable;	332	non-removable;
333	disable-wp;	333	disable-wp;

arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts+1−0

@@ -593,6 +593,7 @@ · 592 unmodified lines
593	compatible = "brcm,bcm43438-bt";	593	compatible = "brcm,bcm43438-bt";
594	interrupt-parent = <&gpio_intc>;	594	interrupt-parent = <&gpio_intc>;
595	interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;	595	interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
		596	interrupt-names = "host-wakeup";
596	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;	597	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
597	max-speed = <2000000>;	598	max-speed = <2000000>;
598	clocks = <&wifi32k>;	599	clocks = <&wifi32k>;

arch/arm64/boot/dts/freescale/imx8qxp-mek.dts+0−5

 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <0>;
 		};
-		ethphy1: ethernet-phy@1 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
-		};
 	};
 };

arch/arm64/boot/dts/intel/socfpga_agilex.dtsi+3−3

@@ -102,7 +102,7 @@ · 101 unmodified lines
102	};	102	};
103		103
104	gmac0: ethernet@ff800000 {	104	gmac0: ethernet@ff800000 {
105	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";	105	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
106	reg = <0xff800000 0x2000>;	106	reg = <0xff800000 0x2000>;
107	interrupts = <0 90 4>;	107	interrupts = <0 90 4>;
108	interrupt-names = "macirq";	108	interrupt-names = "macirq";
@@ -118,7 +118,7 @@ · 9 unmodified lines
118	};	118	};
119		119
120	gmac1: ethernet@ff802000 {	120	gmac1: ethernet@ff802000 {
121	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";	121	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
122	reg = <0xff802000 0x2000>;	122	reg = <0xff802000 0x2000>;
123	interrupts = <0 91 4>;	123	interrupts = <0 91 4>;
124	interrupt-names = "macirq";	124	interrupt-names = "macirq";
@@ -134,7 +134,7 @@ · 9 unmodified lines
134	};	134	};
135		135
136	gmac2: ethernet@ff804000 {	136	gmac2: ethernet@ff804000 {
137	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";	137	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
138	reg = <0xff804000 0x2000>;	138	reg = <0xff804000 0x2000>;
139	interrupts = <0 92 4>;	139	interrupts = <0 92 4>;
140	interrupt-names = "macirq";	140	interrupt-names = "macirq";

arch/arm64/configs/defconfig+1−1

@@ -773,7 +773,7 @@ CONFIG_ARCH_R8A774A1=y · 772 unmodified lines
773	CONFIG_ARCH_R8A774B1=y	773	CONFIG_ARCH_R8A774B1=y
774	CONFIG_ARCH_R8A774C0=y	774	CONFIG_ARCH_R8A774C0=y
775	CONFIG_ARCH_R8A7795=y	775	CONFIG_ARCH_R8A7795=y
776	CONFIG_ARCH_R8A7796=y	776	CONFIG_ARCH_R8A77960=y
777	CONFIG_ARCH_R8A77961=y	777	CONFIG_ARCH_R8A77961=y
778	CONFIG_ARCH_R8A77965=y	778	CONFIG_ARCH_R8A77965=y
779	CONFIG_ARCH_R8A77970=y	779	CONFIG_ARCH_R8A77970=y

arch/arm64/mm/context.c+15−5

 			CONFIG_CAVIUM_ERRATUM_27456));
 }
-static int asids_init(void)
+static int asids_update_limit(void)
 {
-	asid_bits = get_cpu_asid_bits();
+	unsigned long num_available_asids = NUM_USER_ASIDS;
+	if (arm64_kernel_unmapped_at_el0())
+		num_available_asids /= 2;
 	/*
 	 * Expect allocation after rollover to fail if we don't have at least
 	 * one more ASID than CPUs. ASID #0 is reserved for init_mm.
 	 */
-	WARN_ON(NUM_USER_ASIDS - 1 <= num_possible_cpus());
+	WARN_ON(num_available_asids - 1 <= num_possible_cpus());
+	pr_info("ASID allocator initialised with %lu entries\n",
+		num_available_asids);
+	return 0;
+}
+arch_initcall(asids_update_limit);
+static int asids_init(void)
+{
+	asid_bits = get_cpu_asid_bits();
 	atomic64_set(&asid_generation, ASID_FIRST_VERSION);
 	asid_map = kcalloc(BITS_TO_LONGS(NUM_USER_ASIDS), sizeof(*asid_map),
 			   GFP_KERNEL);
 	 */
 	if (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0))
 		set_kpti_asid_bits();
-	pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
 	return 0;
 }
 early_initcall(asids_init);

arch/powerpc/kernel/cputable.c+3−1

 		 * oprofile_cpu_type already has a value, then we are
 		 * possibly overriding a real PVR with a logical one,
 		 * and, in that case, keep the current value for
-		 * oprofile_cpu_type.
+		 * oprofile_cpu_type. Futhermore, let's ensure that the
+		 * fix for the PMAO bug is enabled on compatibility mode.
 		 */
 		if (old.oprofile_cpu_type != NULL) {
 			t->oprofile_cpu_type = old.oprofile_cpu_type;
 			t->oprofile_type = old.oprofile_type;
+			t->cpu_features |= old.cpu_features & CPU_FTR_PMAO_BUG;
 		}
 	}

arch/powerpc/kernel/hw_breakpoint.c+7−5

@@ -331,11 +331,13 @@ int hw_breakpoint_handler(struct die_args *args) · 330 unmodified lines
331	}	331	}
332		332
333	info->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;	333	info->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
334	if (!dar_within_range(regs->dar, info))	334	if (IS_ENABLED(CONFIG_PPC_8xx)) {
335	info->type \|= HW_BRK_TYPE_EXTRANEOUS_IRQ;	335	if (!dar_within_range(regs->dar, info))
336		336	info->type \|= HW_BRK_TYPE_EXTRANEOUS_IRQ;
337	if (!IS_ENABLED(CONFIG_PPC_8xx) && !stepping_handler(regs, bp, info))	337	} else {
338	goto out;	338	if (!stepping_handler(regs, bp, info))
		339	goto out;
		340	}
339		341
340	/*	342	/*
341	* As a policy, the callback is invoked in a 'trigger-after-execute'	343	* As a policy, the callback is invoked in a 'trigger-after-execute'

arch/powerpc/kernel/vmlinux.lds.S+6−0

 		*(.branch_lt)
 	}
+#ifdef CONFIG_DEBUG_INFO_BTF
+	.BTF : AT(ADDR(.BTF) - LOAD_OFFSET) {
+		*(.BTF)
+	}
+#endif
 	.opd : AT(ADDR(.opd) - LOAD_OFFSET) {
 		__start_opd = .;
 		KEEP(*(.opd))

arch/powerpc/mm/mem.c+2−0

 	 */
 	if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
 		mb(); /* sync */
+		allow_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
 		icbi((void *)addr);
+		prevent_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
 		mb(); /* sync */
 		isync();
 		return true;

arch/riscv/Kconfig+1−0

@@ -121,6 +121,7 @@ config ARCH_FLATMEM_ENABLE · 120 unmodified lines
121		121
122	config ARCH_SPARSEMEM_ENABLE	122	config ARCH_SPARSEMEM_ENABLE
123	def_bool y	123	def_bool y
		124	depends on MMU
124	select SPARSEMEM_VMEMMAP_ENABLE	125	select SPARSEMEM_VMEMMAP_ENABLE
125		126
126	config ARCH_SELECT_MEMORY_MODEL	127	config ARCH_SELECT_MEMORY_MODEL

arch/riscv/Kconfig.socs+24−0

@@ -10,4 +10,28 @@ config SOC_SIFIVE · 9 unmodified lines
10	help	10	help
11	This enables support for SiFive SoC platform hardware.	11	This enables support for SiFive SoC platform hardware.
12		12
		13	config SOC_VIRT
		14	bool "QEMU Virt Machine"
		15	select VIRTIO_PCI
		16	select VIRTIO_BALLOON
		17	select VIRTIO_MMIO
		18	select VIRTIO_CONSOLE
		19	select VIRTIO_NET
		20	select NET_9P_VIRTIO
		21	select VIRTIO_BLK
		22	select SCSI_VIRTIO
		23	select DRM_VIRTIO_GPU
		24	select HW_RANDOM_VIRTIO
		25	select RPMSG_CHAR
		26	select RPMSG_VIRTIO
		27	select CRYPTO_DEV_VIRTIO
		28	select VIRTIO_INPUT
		29	select POWER_RESET_SYSCON
		30	select POWER_RESET_SYSCON_POWEROFF
		31	select GOLDFISH
		32	select RTC_DRV_GOLDFISH
		33	select SIFIVE_PLIC
		34	help
		35	This enables support for QEMU Virt Machine.
		36
13	endmenu	37	endmenu

arch/riscv/Makefile+4−2

@@ -13,8 +13,10 @@ LDFLAGS_vmlinux := · 12 unmodified lines
13	ifeq ($(CONFIG_DYNAMIC_FTRACE),y)	13	ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
14	LDFLAGS_vmlinux := --no-relax	14	LDFLAGS_vmlinux := --no-relax
15	endif	15	endif
16	KBUILD_AFLAGS_MODULE += -fPIC	16
17	KBUILD_CFLAGS_MODULE += -fPIC	17	ifeq ($(CONFIG_64BIT)$(CONFIG_CMODEL_MEDLOW),yy)
		18	KBUILD_CFLAGS_MODULE += -mcmodel=medany
		19	endif
18		20
19	export BITS	21	export BITS
20	ifeq ($(CONFIG_ARCH_RV64I),y)	22	ifeq ($(CONFIG_ARCH_RV64I),y)

arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts+5−0

 /* Copyright (c) 2018-2019 SiFive, Inc */
 #include "fu540-c000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
 #define RTCCLK_FREQ		1000000
 		clock-frequency = <RTCCLK_FREQ>;
 		clock-output-names = "rtcclk";
 	};
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+	};
 };
 &uart0 {

arch/riscv/configs/defconfig+3−14

 CONFIG_EXPERT=y
 CONFIG_BPF_SYSCALL=y
 CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_VIRT=y
 CONFIG_SMP=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NETLINK_DIAG=y
 CONFIG_NET_9P=y
-CONFIG_NET_9P_VIRTIO=y
 CONFIG_PCI=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCI_HOST_GENERIC=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_VIRTIO_BLK=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
-CONFIG_SCSI_VIRTIO=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
-CONFIG_VIRTIO_NET=y
 CONFIG_MACB=y
 CONFIG_E1000E=y
 CONFIG_R8169=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
 CONFIG_HVC_RISCV_SBI=y
-CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_VIRTIO=y
 CONFIG_SPI=y
 CONFIG_SPI_SIFIVE=y
 # CONFIG_PTP_1588_CLOCK is not set
+CONFIG_POWER_RESET=y
 CONFIG_DRM=y
 CONFIG_DRM_RADEON=y
-CONFIG_DRM_VIRTIO_GPU=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_UAS=y
 CONFIG_MMC=y
 CONFIG_MMC_SPI=y
-CONFIG_VIRTIO_PCI=y
+CONFIG_RTC_CLASS=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_INPUT=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_RPMSG_CHAR=y
-CONFIG_RPMSG_VIRTIO=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_9P_FS=y
 CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_DEV_VIRTIO=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_PAGEALLOC=y

arch/riscv/configs/rv32_defconfig+3−15

 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_BPF_SYSCALL=y
+CONFIG_SOC_VIRT=y
 CONFIG_ARCH_RV32I=y
 CONFIG_SMP=y
 CONFIG_MODULES=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NETLINK_DIAG=y
 CONFIG_NET_9P=y
-CONFIG_NET_9P_VIRTIO=y
 CONFIG_PCI=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCI_HOST_GENERIC=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_VIRTIO_BLK=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
-CONFIG_SCSI_VIRTIO=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
-CONFIG_VIRTIO_NET=y
 CONFIG_MACB=y
 CONFIG_E1000E=y
 CONFIG_R8169=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
 CONFIG_HVC_RISCV_SBI=y
-CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_VIRTIO=y
 # CONFIG_PTP_1588_CLOCK is not set
+CONFIG_POWER_RESET=y
 CONFIG_DRM=y
 CONFIG_DRM_RADEON=y
-CONFIG_DRM_VIRTIO_GPU=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_UAS=y
-CONFIG_VIRTIO_PCI=y
+CONFIG_RTC_CLASS=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_INPUT=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_RPMSG_CHAR=y
-CONFIG_RPMSG_VIRTIO=y
-CONFIG_SIFIVE_PLIC=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_9P_FS=y
 CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_DEV_VIRTIO=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_PAGEALLOC=y

arch/riscv/include/asm/syscall.h+0−7

@@ -28,13 +28,6 @@ static inline int syscall_get_nr(struct task_struct *task, · 27 unmodified lines
28	return regs->a7;	28	return regs->a7;
29	}	29	}
30		30
31	static inline void syscall_set_nr(struct task_struct *task,
32	struct pt_regs *regs,
33	int sysno)
34	{
35	regs->a7 = sysno;
36	}
37
38	static inline void syscall_rollback(struct task_struct *task,	31	static inline void syscall_rollback(struct task_struct *task,
39	struct pt_regs *regs)	32	struct pt_regs *regs)
40	{	33	{

arch/riscv/kernel/entry.S+3−8

 	/* Check to make sure we don't jump to a bogus syscall number. */
 	li t0, __NR_syscalls
 	la s0, sys_ni_syscall
-	/*
-	 * The tracer can change syscall number to valid/invalid value.
-	 * We use syscall_set_nr helper in syscall_trace_enter thus we
-	 * cannot trust the current value in a7 and have to reload from
-	 * the current task pt_regs.
-	 */
-	REG_L a7, PT_A7(sp)
 	/*
 	 * Syscall number held in a7.
 	 * If syscall number is above allowed value, redirect to ni_syscall.
 	 */
 	bge a7, t0, 1f
 	/*
-	 * Check if syscall is rejected by tracer or seccomp, i.e., a7 == -1.
+	 * Check if syscall is rejected by tracer, i.e., a7 == -1.
 	 * If yes, we pretend it was executed.
 	 */
 	li t1, -1
 handle_syscall_trace_enter:
 	move a0, sp
 	call do_syscall_trace_enter
+	move t0, a0
 	REG_L a0, PT_A0(sp)
 	REG_L a1, PT_A1(sp)
 	REG_L a2, PT_A2(sp)
 	REG_L a5, PT_A5(sp)
 	REG_L a6, PT_A6(sp)
 	REG_L a7, PT_A7(sp)
+	bnez t0, ret_from_syscall_rejected
 	j check_syscall_nr
 handle_syscall_trace_exit:
 	move a0, sp

arch/riscv/kernel/module.c+16−0

@@ -8,6 +8,10 @@ · 7 unmodified lines
8	#include <linux/err.h>	8	#include <linux/err.h>
9	#include <linux/errno.h>	9	#include <linux/errno.h>
10	#include <linux/moduleloader.h>	10	#include <linux/moduleloader.h>
		11	#include <linux/vmalloc.h>
		12	#include <linux/sizes.h>
		13	#include <asm/pgtable.h>
		14	#include <asm/sections.h>
11		15
12	static int apply_r_riscv_32_rela(struct module me, u32 location, Elf_Addr v)	16	static int apply_r_riscv_32_rela(struct module me, u32 location, Elf_Addr v)
13	{	17	{
@@ -386,3 +390,15 @@ int apply_relocate_add(Elf_Shdr sechdrs, const char strtab, · 372 unmodified lines
386		390
387	return 0;	391	return 0;
388	}	392	}
		393
		394	#if defined(CONFIG_MMU) && defined(CONFIG_64BIT)
		395	#define VMALLOC_MODULE_START \
		396	max(PFN_ALIGN((unsigned long)&_end - SZ_2G), VMALLOC_START)
		397	void *module_alloc(unsigned long size)
		398	{
		399	return __vmalloc_node_range(size, 1, VMALLOC_MODULE_START,
		400	VMALLOC_END, GFP_KERNEL,
		401	PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
		402	__builtin_return_address(0));
		403	}
		404	#endif

arch/riscv/kernel/ptrace.c+5−6

  * Allows PTRACE_SYSCALL to work.  These are called from entry.S in
  * {handle,ret_from}_syscall.
  */
-__visible void do_syscall_trace_enter(struct pt_regs *regs)
+__visible int do_syscall_trace_enter(struct pt_regs *regs)
 {
 	if (test_thread_flag(TIF_SYSCALL_TRACE))
 		if (tracehook_report_syscall_entry(regs))
-			syscall_set_nr(current, regs, -1);
+			return -1;
 	/*
 	 * Do the secure computing after ptrace; failures should be fast.
 	 * If this fails we might have return value in a0 from seccomp
 	 * (via SECCOMP_RET_ERRNO/TRACE).
 	 */
-	if (secure_computing() == -1) {
+	if (secure_computing() == -1)
-		syscall_set_nr(current, regs, -1);
+		return -1;
-		return;
-	}
 #ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS
 	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
 #endif
 	audit_syscall_entry(regs->a7, regs->a0, regs->a1, regs->a2, regs->a3);
+	return 0;
 }
 __visible void do_syscall_trace_exit(struct pt_regs *regs)

arch/riscv/mm/init.c+1−1

@@ -131,7 +131,7 @@ void __init setup_bootmem(void) · 130 unmodified lines
131	for_each_memblock(memory, reg) {	131	for_each_memblock(memory, reg) {
132	phys_addr_t end = reg->base + reg->size;	132	phys_addr_t end = reg->base + reg->size;
133		133
134	if (reg->base <= vmlinux_end && vmlinux_end <= end) {	134	if (reg->base <= vmlinux_start && vmlinux_end <= end) {
135	mem_size = min(reg->size, (phys_addr_t)-PAGE_OFFSET);	135	mem_size = min(reg->size, (phys_addr_t)-PAGE_OFFSET);
136		136
137	/*	137	/*

arch/s390/include/asm/pgtable.h+6−0

 	return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0;
 }
+#define pud_write pud_write
+static inline int pud_write(pud_t pud)
+{
+	return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0;
+}
 static inline int pmd_dirty(pmd_t pmd)
 {
 	return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0;

arch/s390/pci/pci.c+2−2

@@ -424,7 +424,7 @@ static void zpci_map_resources(struct pci_dev *pdev) · 423 unmodified lines
424		424
425	if (zpci_use_mio(zdev))	425	if (zpci_use_mio(zdev))
426	pdev->resource[i].start =	426	pdev->resource[i].start =
427	(resource_size_t __force) zdev->bars[i].mio_wb;	427	(resource_size_t __force) zdev->bars[i].mio_wt;
428	else	428	else
429	pdev->resource[i].start = (resource_size_t __force)	429	pdev->resource[i].start = (resource_size_t __force)
430	pci_iomap_range_fh(pdev, i, 0, 0);	430	pci_iomap_range_fh(pdev, i, 0, 0);
@@ -531,7 +531,7 @@ static int zpci_setup_bus_resources(struct zpci_dev *zdev, · 100 unmodified lines
531	flags \|= IORESOURCE_MEM_64;	531	flags \|= IORESOURCE_MEM_64;
532		532
533	if (zpci_use_mio(zdev))	533	if (zpci_use_mio(zdev))
534	addr = (unsigned long) zdev->bars[i].mio_wb;	534	addr = (unsigned long) zdev->bars[i].mio_wt;
535	else	535	else
536	addr = ZPCI_ADDR(entry);	536	addr = ZPCI_ADDR(entry);
537	size = 1UL << zdev->bars[i].size;	537	size = 1UL << zdev->bars[i].size;

arch/x86/include/asm/io_bitmap.h+8−1

 void io_bitmap_share(struct task_struct *tsk);
 void io_bitmap_exit(void);
-void tss_update_io_bitmap(void);
+void native_tss_update_io_bitmap(void);
+#ifdef CONFIG_PARAVIRT_XXL
+#include <asm/paravirt.h>
+#else
+#define tss_update_io_bitmap native_tss_update_io_bitmap
+#endif
 #else
 static inline void io_bitmap_share(struct task_struct *tsk) { }
 static inline void io_bitmap_exit(void) { }

arch/x86/include/asm/paravirt.h+7−0

@@ -295,6 +295,13 @@ static inline void write_idt_entry(gate_desc dt, int entry, const gate_desc g) · 294 unmodified lines
295	PVOP_VCALL3(cpu.write_idt_entry, dt, entry, g);	295	PVOP_VCALL3(cpu.write_idt_entry, dt, entry, g);
296	}	296	}
297		297
		298	#ifdef CONFIG_X86_IOPL_IOPERM
		299	static inline void tss_update_io_bitmap(void)
		300	{
		301	PVOP_VCALL0(cpu.update_io_bitmap);
		302	}
		303	#endif
		304
298	static inline void paravirt_activate_mm(struct mm_struct *prev,	305	static inline void paravirt_activate_mm(struct mm_struct *prev,
299	struct mm_struct *next)	306	struct mm_struct *next)
300	{	307	{

arch/x86/include/asm/paravirt_types.h+4−0

@@ -140,6 +140,10 @@ struct pv_cpu_ops { · 139 unmodified lines
140		140
141	void (*load_sp0)(unsigned long sp0);	141	void (*load_sp0)(unsigned long sp0);
142		142
		143	#ifdef CONFIG_X86_IOPL_IOPERM
		144	void (*update_io_bitmap)(void);
		145	#endif
		146
143	void (*wbinvd)(void);	147	void (*wbinvd)(void);
144		148
145	/* cpuid emulation, mostly so that caps bits can be disabled */	149	/* cpuid emulation, mostly so that caps bits can be disabled */

arch/x86/kernel/cpu/common.c+1−1

@@ -445,7 +445,7 @@ static __always_inline void setup_pku(struct cpuinfo_x86 *c) · 444 unmodified lines
445	* cpuid bit to be set. We need to ensure that we	445	* cpuid bit to be set. We need to ensure that we
446	* update that bit in this CPU's "cpu_info".	446	* update that bit in this CPU's "cpu_info".
447	*/	447	*/
448	get_cpu_cap(c);	448	set_cpu_cap(c, X86_FEATURE_OSPKE);
449	}	449	}
450		450
451	#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS	451	#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS

arch/x86/kernel/paravirt.c+5−0

 #include <asm/timer.h>
 #include <asm/special_insns.h>
 #include <asm/tlb.h>
+#include <asm/io_bitmap.h>
 /*
  * nop stub, which must not clobber anything *including the stack* to
 	.cpu.iret		= native_iret,
 	.cpu.swapgs		= native_swapgs,
+#ifdef CONFIG_X86_IOPL_IOPERM
+	.cpu.update_io_bitmap	= native_tss_update_io_bitmap,
+#endif
 	.cpu.start_context_switch	= paravirt_nop,
 	.cpu.end_context_switch		= paravirt_nop,

arch/x86/kernel/process.c+1−1

@@ -374,7 +374,7 @@ static void tss_copy_io_bitmap(struct tss_struct tss, struct io_bitmap iobm) · 373 unmodified lines
374	/**	374	/**
375	* tss_update_io_bitmap - Update I/O bitmap before exiting to usermode	375	* tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
376	*/	376	*/
377	void tss_update_io_bitmap(void)	377	void native_tss_update_io_bitmap(void)
378	{	378	{
379	struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);	379	struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
380	struct thread_struct *t = &current->thread;	380	struct thread_struct *t = &current->thread;

arch/x86/mm/dump_pagetables.c+1−6

 {
 	const struct ptdump_range ptdump_ranges[] = {
 #ifdef CONFIG_X86_64
-#define normalize_addr_shift (64 - (__VIRTUAL_MASK_SHIFT + 1))
-#define normalize_addr(u) ((signed long)((u) << normalize_addr_shift) >> \
-			   normalize_addr_shift)
 	{0, PTRS_PER_PGD * PGD_LEVEL_MULT / 2},
-	{normalize_addr(PTRS_PER_PGD * PGD_LEVEL_MULT / 2), ~0UL},
+	{GUARD_HOLE_END_ADDR, ~0UL},
 #else
 	{0, ~0UL},
 #endif

arch/x86/platform/efi/efi_64.c+52−99

 static inline phys_addr_t
 virt_to_phys_or_null_size(void *va, unsigned long size)
 {
-	bool bad_size;
+	phys_addr_t pa;
 	if (!va)
 		return 0;
 	if (virt_addr_valid(va))
 		return virt_to_phys(va);
-	/*
+	pa = slow_virt_to_phys(va);
-	 * A fully aligned variable on the stack is guaranteed not to
-	 * cross a page bounary. Try to catch strings on the stack by
-	 * checking that 'size' is a power of two.
-	 */
-	bad_size = size > PAGE_SIZE || !is_power_of_2(size);
-	WARN_ON(!IS_ALIGNED((unsigned long)va, size) || bad_size);
+	/* check if the object crosses a page boundary */
+	if (WARN_ON((pa ^ (pa + size - 1)) & PAGE_MASK))
+		return 0;
-	return slow_virt_to_phys(va);
+	return pa;
 }
 #define virt_to_phys_or_null(addr)				\
 static efi_status_t efi_thunk_get_time(efi_time_t *tm, efi_time_cap_t *tc)
 {
-	efi_status_t status;
+	return EFI_UNSUPPORTED;
-	u32 phys_tm, phys_tc;
-	unsigned long flags;
-	spin_lock(&rtc_lock);
-	spin_lock_irqsave(&efi_runtime_lock, flags);
-	phys_tm = virt_to_phys_or_null(tm);
-	phys_tc = virt_to_phys_or_null(tc);
-	status = efi_thunk(get_time, phys_tm, phys_tc);
-	spin_unlock_irqrestore(&efi_runtime_lock, flags);
-	spin_unlock(&rtc_lock);
-	return status;
 }
 static efi_status_t efi_thunk_set_time(efi_time_t *tm)
 {
-	efi_status_t status;
+	return EFI_UNSUPPORTED;
-	u32 phys_tm;
-	unsigned long flags;
-	spin_lock(&rtc_lock);
-	spin_lock_irqsave(&efi_runtime_lock, flags);
-	phys_tm = virt_to_phys_or_null(tm);
-	status = efi_thunk(set_time, phys_tm);
-	spin_unlock_irqrestore(&efi_runtime_lock, flags);
-	spin_unlock(&rtc_lock);
-	return status;
 }
 static efi_status_t
 efi_thunk_get_wakeup_time(efi_bool_t *enabled, efi_bool_t *pending,
 			  efi_time_t *tm)
 {
-	efi_status_t status;
+	return EFI_UNSUPPORTED;
-	u32 phys_enabled, phys_pending, phys_tm;
-	unsigned long flags;
-	spin_lock(&rtc_lock);
-	spin_lock_irqsave(&efi_runtime_lock, flags);
-	phys_enabled = virt_to_phys_or_null(enabled);
-	phys_pending = virt_to_phys_or_null(pending);
-	phys_tm = virt_to_phys_or_null(tm);
-	status = efi_thunk(get_wakeup_time, phys_enabled,
-			     phys_pending, phys_tm);
-	spin_unlock_irqrestore(&efi_runtime_lock, flags);
-	spin_unlock(&rtc_lock);
-	return status;
 }
 static efi_status_t
 efi_thunk_set_wakeup_time(efi_bool_t enabled, efi_time_t *tm)
 {
-	efi_status_t status;
+	return EFI_UNSUPPORTED;
-	u32 phys_tm;
-	unsigned long flags;
-	spin_lock(&rtc_lock);
-	spin_lock_irqsave(&efi_runtime_lock, flags);
-	phys_tm = virt_to_phys_or_null(tm);
-	status = efi_thunk(set_wakeup_time, enabled, phys_tm);
-	spin_unlock_irqrestore(&efi_runtime_lock, flags);
-	spin_unlock(&rtc_lock);
-	return status;
 }
 static unsigned long efi_name_size(efi_char16_t *name)
 efi_thunk_get_variable(efi_char16_t *name, efi_guid_t *vendor,
 		       u32 *attr, unsigned long *data_size, void *data)
 {
+	u8 buf[24] __aligned(8);
+	efi_guid_t *vnd = PTR_ALIGN((efi_guid_t *)buf, sizeof(*vnd));
 	efi_status_t status;
 	u32 phys_name, phys_vendor, phys_attr;
 	u32 phys_data_size, phys_data;
 	spin_lock_irqsave(&efi_runtime_lock, flags);
+	*vnd = *vendor;
 	phys_data_size = virt_to_phys_or_null(data_size);
-	phys_vendor = virt_to_phys_or_null(vendor);
+	phys_vendor = virt_to_phys_or_null(vnd);
 	phys_name = virt_to_phys_or_null_size(name, efi_name_size(name));
 	phys_attr = virt_to_phys_or_null(attr);
 	phys_data = virt_to_phys_or_null_size(data, *data_size);
-	status = efi_thunk(get_variable, phys_name, phys_vendor,
+	if (!phys_name || (data && !phys_data))
-			   phys_attr, phys_data_size, phys_data);
+		status = EFI_INVALID_PARAMETER;
+	else
+		status = efi_thunk(get_variable, phys_name, phys_vendor,
+				   phys_attr, phys_data_size, phys_data);
 	spin_unlock_irqrestore(&efi_runtime_lock, flags);
 efi_thunk_set_variable(efi_char16_t *name, efi_guid_t *vendor,
 		       u32 attr, unsigned long data_size, void *data)
 {
+	u8 buf[24] __aligned(8);
+	efi_guid_t *vnd = PTR_ALIGN((efi_guid_t *)buf, sizeof(*vnd));
 	u32 phys_name, phys_vendor, phys_data;
 	efi_status_t status;
 	unsigned long flags;
 	spin_lock_irqsave(&efi_runtime_lock, flags);
+	*vnd = *vendor;
 	phys_name = virt_to_phys_or_null_size(name, efi_name_size(name));
-	phys_vendor = virt_to_phys_or_null(vendor);
+	phys_vendor = virt_to_phys_or_null(vnd);
 	phys_data = virt_to_phys_or_null_size(data, data_size);
-	/* If data_size is > sizeof(u32) we've got problems */
+	if (!phys_name || !phys_data)
-	status = efi_thunk(set_variable, phys_name, phys_vendor,
+		status = EFI_INVALID_PARAMETER;
-			   attr, data_size, phys_data);
+	else
+		status = efi_thunk(set_variable, phys_name, phys_vendor,
+				   attr, data_size, phys_data);
 	spin_unlock_irqrestore(&efi_runtime_lock, flags);
 				   u32 attr, unsigned long data_size,
 				   void *data)
 {
+	u8 buf[24] __aligned(8);
+	efi_guid_t *vnd = PTR_ALIGN((efi_guid_t *)buf, sizeof(*vnd));
 	u32 phys_name, phys_vendor, phys_data;
 	efi_status_t status;
 	unsigned long flags;
 	if (!spin_trylock_irqsave(&efi_runtime_lock, flags))
 		return EFI_NOT_READY;
+	*vnd = *vendor;
 	phys_name = virt_to_phys_or_null_size(name, efi_name_size(name));
-	phys_vendor = virt_to_phys_or_null(vendor);
+	phys_vendor = virt_to_phys_or_null(vnd);
 	phys_data = virt_to_phys_or_null_size(data, data_size);
-	/* If data_size is > sizeof(u32) we've got problems */
+	if (!phys_name || !phys_data)
-	status = efi_thunk(set_variable, phys_name, phys_vendor,
+		status = EFI_INVALID_PARAMETER;
-			   attr, data_size, phys_data);
+	else
+		status = efi_thunk(set_variable, phys_name, phys_vendor,
+				   attr, data_size, phys_data);
 	spin_unlock_irqrestore(&efi_runtime_lock, flags);
 			    efi_char16_t *name,
 			    efi_guid_t *vendor)
 {
+	u8 buf[24] __aligned(8);
+	efi_guid_t *vnd = PTR_ALIGN((efi_guid_t *)buf, sizeof(*vnd));
 	efi_status_t status;
 	u32 phys_name_size, phys_name, phys_vendor;
 	unsigned long flags;
 	spin_lock_irqsave(&efi_runtime_lock, flags);
+	*vnd = *vendor;
 	phys_name_size = virt_to_phys_or_null(name_size);
-	phys_vendor = virt_to_phys_or_null(vendor);
+	phys_vendor = virt_to_phys_or_null(vnd);
 	phys_name = virt_to_phys_or_null_size(name, *name_size);
-	status = efi_thunk(get_next_variable, phys_name_size,
+	if (!phys_name)
-			   phys_name, phys_vendor);
+		status = EFI_INVALID_PARAMETER;
+	else
+		status = efi_thunk(get_next_variable, phys_name_size,
+				   phys_name, phys_vendor);
 	spin_unlock_irqrestore(&efi_runtime_lock, flags);
+	*vendor = *vnd;
 	return status;
 }
 static efi_status_t
 efi_thunk_get_next_high_mono_count(u32 *count)
 {
-	efi_status_t status;
+	return EFI_UNSUPPORTED;
-	u32 phys_count;
-	unsigned long flags;
-	spin_lock_irqsave(&efi_runtime_lock, flags);
-	phys_count = virt_to_phys_or_null(count);
-	status = efi_thunk(get_next_high_mono_count, phys_count);
-	spin_unlock_irqrestore(&efi_runtime_lock, flags);
-	return status;
 }
 static void

arch/x86/xen/enlighten_pv.c+25−0

@@ -72,6 +72,9 @@ · 71 unmodified lines
72	#include <asm/mwait.h>	72	#include <asm/mwait.h>
73	#include <asm/pci_x86.h>	73	#include <asm/pci_x86.h>
74	#include <asm/cpu.h>	74	#include <asm/cpu.h>
		75	#ifdef CONFIG_X86_IOPL_IOPERM
		76	#include <asm/io_bitmap.h>
		77	#endif
75		78
76	#ifdef CONFIG_ACPI	79	#ifdef CONFIG_ACPI
77	#include <linux/acpi.h>	80	#include <linux/acpi.h>
@@ -837,6 +840,25 @@ static void xen_load_sp0(unsigned long sp0) · 759 unmodified lines
837	this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);	840	this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
838	}	841	}
839		842
		843	#ifdef CONFIG_X86_IOPL_IOPERM
		844	static void xen_update_io_bitmap(void)
		845	{
		846	struct physdev_set_iobitmap iobitmap;
		847	struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
		848
		849	native_tss_update_io_bitmap();
		850
		851	iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) +
		852	tss->x86_tss.io_bitmap_base;
		853	if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID)
		854	iobitmap.nr_ports = 0;
		855	else
		856	iobitmap.nr_ports = IO_BITMAP_BITS;
		857
		858	HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap);
		859	}
		860	#endif
		861
840	static void xen_io_delay(void)	862	static void xen_io_delay(void)
841	{	863	{
842	}	864	}
@@ -1047,6 +1069,9 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = { · 204 unmodified lines
1047	.write_idt_entry = xen_write_idt_entry,	1069	.write_idt_entry = xen_write_idt_entry,
1048	.load_sp0 = xen_load_sp0,	1070	.load_sp0 = xen_load_sp0,
1049		1071
		1072	#ifdef CONFIG_X86_IOPL_IOPERM
		1073	.update_io_bitmap = xen_update_io_bitmap,
		1074	#endif
1050	.io_delay = xen_io_delay,	1075	.io_delay = xen_io_delay,
1051		1076
1052	/* Xen takes care of %gs when switching to usermode for us */	1077	/* Xen takes care of %gs when switching to usermode for us */

block/bfq-cgroup.c+5−4

 	 */
 	entity = &bfqg->entity;
 	for_each_entity(entity) {
-		bfqg = container_of(entity, struct bfq_group, entity);
+		struct bfq_group *curr_bfqg = container_of(entity,
-		if (bfqg != bfqd->root_group) {
+						struct bfq_group, entity);
-			parent = bfqg_parent(bfqg);
+		if (curr_bfqg != bfqd->root_group) {
+			parent = bfqg_parent(curr_bfqg);
 			if (!parent)
 				parent = bfqd->root_group;
-			bfq_group_set_parent(bfqg, parent);
+			bfq_group_set_parent(curr_bfqg, parent);
 		}
 	}

block/blk-core.c+0−6

 }
 EXPORT_SYMBOL(kblockd_schedule_work);
-int kblockd_schedule_work_on(int cpu, struct work_struct *work)
-{
-	return queue_work_on(cpu, kblockd_workqueue, work);
-}
-EXPORT_SYMBOL(kblockd_schedule_work_on);
 int kblockd_mod_delayed_work_on(int cpu, struct delayed_work *dwork,
 				unsigned long delay)
 {

drivers/android/binder.c+9−0

 		binder_dev = container_of(filp->private_data,
 					  struct binder_device, miscdev);
 	}
+	refcount_inc(&binder_dev->ref);
 	proc->context = &binder_dev->context;
 	binder_alloc_init(&proc->alloc);
 static void binder_deferred_release(struct binder_proc *proc)
 {
 	struct binder_context *context = proc->context;
+	struct binder_device *device;
 	struct rb_node *n;
 	int threads, nodes, incoming_refs, outgoing_refs, active_transactions;
 		context->binder_context_mgr_node = NULL;
 	}
 	mutex_unlock(&context->context_mgr_node_lock);
+	device = container_of(proc->context, struct binder_device, context);
+	if (refcount_dec_and_test(&device->ref)) {
+		kfree(context->name);
+		kfree(device);
+	}
+	proc->context = NULL;
 	binder_inner_proc_lock(proc);
 	/*
 	 * Make sure proc stays alive after we
 	binder_device->miscdev.minor = MISC_DYNAMIC_MINOR;
 	binder_device->miscdev.name = name;
+	refcount_set(&binder_device->ref, 1);
 	binder_device->context.binder_context_mgr_uid = INVALID_UID;
 	binder_device->context.name = name;
 	mutex_init(&binder_device->context.context_mgr_node_lock);

drivers/android/binder_internal.h+2−0

 #include <linux/list.h>
 #include <linux/miscdevice.h>
 #include <linux/mutex.h>
+#include <linux/refcount.h>
 #include <linux/stddef.h>
 #include <linux/types.h>
 #include <linux/uidgid.h>
 	struct miscdevice miscdev;
 	struct binder_context context;
 	struct inode *binderfs_inode;
+	refcount_t ref;
 };
 /**

drivers/android/binderfs.c+5−2

 	if (!name)
 		goto err;
+	refcount_set(&device->ref, 1);
 	device->binderfs_inode = inode;
 	device->context.binder_context_mgr_uid = INVALID_UID;
 	device->context.name = name;
 	ida_free(&binderfs_minors, device->miscdev.minor);
 	mutex_unlock(&binderfs_minors_mutex);
-	kfree(device->context.name);
+	if (refcount_dec_and_test(&device->ref)) {
-	kfree(device);
+		kfree(device->context.name);
+		kfree(device);
+	}
 }
 /**

drivers/base/core.c+20−7

 {
 	struct device_link *link;
+	if (!dev_has_sync_state(dev))
+		return;
 	if (dev->state_synced)
 		return;
 /**
  * device_links_flush_sync_list - Call sync_state() on a list of devices
  * @list: List of devices to call sync_state() on
+ * @dont_lock_dev: Device for which lock is already held by the caller
  *
  * Calls sync_state() on all the devices that have been queued for it. This
- * function is used in conjunction with __device_links_queue_sync_state().
+ * function is used in conjunction with __device_links_queue_sync_state(). The
+ * @dont_lock_dev parameter is useful when this function is called from a
+ * context where a device lock is already held.
  */
-static void device_links_flush_sync_list(struct list_head *list)
+static void device_links_flush_sync_list(struct list_head *list,
+					 struct device *dont_lock_dev)
 {
 	struct device *dev, *tmp;
 	list_for_each_entry_safe(dev, tmp, list, links.defer_sync) {
 		list_del_init(&dev->links.defer_sync);
-		device_lock(dev);
+		if (dev != dont_lock_dev)
+			device_lock(dev);
 		if (dev->bus->sync_state)
 			dev->bus->sync_state(dev);
 		else if (dev->driver && dev->driver->sync_state)
 			dev->driver->sync_state(dev);
-		device_unlock(dev);
+		if (dev != dont_lock_dev)
+			device_unlock(dev);
 		put_device(dev);
 	}
 out:
 	device_links_write_unlock();
-	device_links_flush_sync_list(&sync_list);
+	device_links_flush_sync_list(&sync_list, NULL);
 }
 static int sync_state_resume_initcall(void)
 static void __device_links_supplier_defer_sync(struct device *sup)
 {
-	if (list_empty(&sup->links.defer_sync))
+	if (list_empty(&sup->links.defer_sync) && dev_has_sync_state(sup))
 		list_add_tail(&sup->links.defer_sync, &deferred_sync);
 }
 			driver_deferred_probe_add(link->consumer);
 	}
+	if (defer_sync_state_count)
+		__device_links_supplier_defer_sync(dev);
+	else
+		__device_links_queue_sync_state(dev, &sync_list);
 	list_for_each_entry(link, &dev->links.suppliers, c_node) {
 		if (!(link->flags & DL_FLAG_MANAGED))
 			continue;
 	device_links_write_unlock();
-	device_links_flush_sync_list(&sync_list);
+	device_links_flush_sync_list(&sync_list, dev);
 }
 static void device_link_drop_managed(struct device_link *link)

drivers/base/swnode.c+7−7

 {
 	struct swnode *swnode = kobj_to_swnode(kobj);
+	if (swnode->parent) {
+		ida_simple_remove(&swnode->parent->child_ids, swnode->id);
+		list_del(&swnode->entry);
+	} else {
+		ida_simple_remove(&swnode_root_ids, swnode->id);
+	}
 	if (swnode->allocated) {
 		property_entries_free(swnode->node->properties);
 		kfree(swnode->node);
 	if (!swnode)
 		return;
-	if (swnode->parent) {
-		ida_simple_remove(&swnode->parent->child_ids, swnode->id);
-		list_del(&swnode->entry);
-	} else {
-		ida_simple_remove(&swnode_root_ids, swnode->id);
-	}
 	kobject_put(&swnode->kobj);
 }
 EXPORT_SYMBOL_GPL(fwnode_remove_software_node);

drivers/block/xen-blkfront.c+42−38

 	struct blk_mq_tag_set tag_set;
 	struct blkfront_ring_info *rinfo;
 	unsigned int nr_rings;
+	unsigned int rinfo_size;
 	/* Save uncomplete reqs and bios for migration. */
 	struct list_head requests;
 	struct bio_list bio_list;
 static void blkfront_gather_backend_features(struct blkfront_info *info);
 static int negotiate_mq(struct blkfront_info *info);
+#define for_each_rinfo(info, ptr, idx)				\
+	for ((ptr) = (info)->rinfo, (idx) = 0;			\
+	     (idx) < (info)->nr_rings;				\
+	     (idx)++, (ptr) = (void *)(ptr) + (info)->rinfo_size)
+static inline struct blkfront_ring_info *
+get_rinfo(const struct blkfront_info *info, unsigned int i)
+{
+	BUG_ON(i >= info->nr_rings);
+	return (void *)info->rinfo + i * info->rinfo_size;
+}
 static int get_id_from_freelist(struct blkfront_ring_info *rinfo)
 {
 	unsigned long free = rinfo->shadow_free;
 	struct blkfront_info *info = hctx->queue->queuedata;
 	struct blkfront_ring_info *rinfo = NULL;
-	BUG_ON(info->nr_rings <= qid);
+	rinfo = get_rinfo(info, qid);
-	rinfo = &info->rinfo[qid];
 	blk_mq_start_request(qd->rq);
 	spin_lock_irqsave(&rinfo->ring_lock, flags);
 	if (RING_FULL(&rinfo->ring))
 static void xlvbd_release_gendisk(struct blkfront_info *info)
 {
 	unsigned int minor, nr_minors, i;
+	struct blkfront_ring_info *rinfo;
 	if (info->rq == NULL)
 		return;
 	/* No more blkif_request(). */
 	blk_mq_stop_hw_queues(info->rq);
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		struct blkfront_ring_info *rinfo = &info->rinfo[i];
 		/* No more gnttab callback work. */
 		gnttab_cancel_free_callback(&rinfo->callback);
 static void blkif_free(struct blkfront_info *info, int suspend)
 {
 	unsigned int i;
+	struct blkfront_ring_info *rinfo;
 	/* Prevent new requests being issued until we fix things up. */
 	info->connected = suspend ?
 	if (info->rq)
 		blk_mq_stop_hw_queues(info->rq);
-	for (i = 0; i < info->nr_rings; i++)
+	for_each_rinfo(info, rinfo, i)
-		blkif_free_ring(&info->rinfo[i]);
+		blkif_free_ring(rinfo);
 	kvfree(info->rinfo);
 	info->rinfo = NULL;
 	int err;
 	unsigned int i, max_page_order;
 	unsigned int ring_page_order;
+	struct blkfront_ring_info *rinfo;
 	if (!info)
 		return -ENODEV;
 	if (err)
 		goto destroy_blkring;
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		struct blkfront_ring_info *rinfo = &info->rinfo[i];
 		/* Create shared ring, alloc event channel. */
 		err = setup_blkring(dev, rinfo);
 		if (err)
 	/* We already got the number of queues/rings in _probe */
 	if (info->nr_rings == 1) {
-		err = write_per_ring_nodes(xbt, &info->rinfo[0], dev->nodename);
+		err = write_per_ring_nodes(xbt, info->rinfo, dev->nodename);
 		if (err)
 			goto destroy_blkring;
 	} else {
 			goto abort_transaction;
 		}
-		for (i = 0; i < info->nr_rings; i++) {
+		for_each_rinfo(info, rinfo, i) {
 			memset(path, 0, pathsize);
 			snprintf(path, pathsize, "%s/queue-%u", dev->nodename, i);
-			err = write_per_ring_nodes(xbt, &info->rinfo[i], path);
+			err = write_per_ring_nodes(xbt, rinfo, path);
 			if (err) {
 				kfree(path);
 				goto destroy_blkring;
 		goto destroy_blkring;
 	}
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
 		unsigned int j;
-		struct blkfront_ring_info *rinfo = &info->rinfo[i];
 		for (j = 0; j < BLK_RING_SIZE(info); j++)
 			rinfo->shadow[j].req.u.rw.id = j + 1;
 {
 	unsigned int backend_max_queues;
 	unsigned int i;
+	struct blkfront_ring_info *rinfo;
 	BUG_ON(info->nr_rings);
 	if (!info->nr_rings)
 		info->nr_rings = 1;
-	info->rinfo = kvcalloc(info->nr_rings,
+	info->rinfo_size = struct_size(info->rinfo, shadow,
-			       struct_size(info->rinfo, shadow,
+				       BLK_RING_SIZE(info));
-					   BLK_RING_SIZE(info)),
+	info->rinfo = kvcalloc(info->nr_rings, info->rinfo_size, GFP_KERNEL);
-			       GFP_KERNEL);
 	if (!info->rinfo) {
 		xenbus_dev_fatal(info->xbdev, -ENOMEM, "allocating ring_info structure");
 		info->nr_rings = 0;
 		return -ENOMEM;
 	}
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		struct blkfront_ring_info *rinfo;
-		rinfo = &info->rinfo[i];
 		INIT_LIST_HEAD(&rinfo->indirect_pages);
 		INIT_LIST_HEAD(&rinfo->grants);
 		rinfo->dev_info = info;
 	int rc;
 	struct bio *bio;
 	unsigned int segs;
+	struct blkfront_ring_info *rinfo;
 	blkfront_gather_backend_features(info);
 	/* Reset limits changed by blk_mq_update_nr_hw_queues(). */
 	segs = info->max_indirect_segments ? : BLKIF_MAX_SEGMENTS_PER_REQUEST;
 	blk_queue_max_segments(info->rq, segs / GRANTS_PER_PSEG);
-	for (r_index = 0; r_index < info->nr_rings; r_index++) {
+	for_each_rinfo(info, rinfo, r_index) {
-		struct blkfront_ring_info *rinfo = &info->rinfo[r_index];
 		rc = blkfront_setup_indirect(rinfo);
 		if (rc)
 			return rc;
 	/* Now safe for us to use the shared ring */
 	info->connected = BLKIF_STATE_CONNECTED;
-	for (r_index = 0; r_index < info->nr_rings; r_index++) {
+	for_each_rinfo(info, rinfo, r_index) {
-		struct blkfront_ring_info *rinfo;
-		rinfo = &info->rinfo[r_index];
 		/* Kick any other new requests queued since we resumed */
 		kick_pending_request_queues(rinfo);
 	}
 	struct blkfront_info *info = dev_get_drvdata(&dev->dev);
 	int err = 0;
 	unsigned int i, j;
+	struct blkfront_ring_info *rinfo;
 	dev_dbg(&dev->dev, "blkfront_resume: %s\n", dev->nodename);
 	bio_list_init(&info->bio_list);
 	INIT_LIST_HEAD(&info->requests);
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		struct blkfront_ring_info *rinfo = &info->rinfo[i];
 		struct bio_list merge_bio;
 		struct blk_shadow *shadow = rinfo->shadow;
 	unsigned int binfo;
 	char *envp[] = { "RESIZE=1", NULL };
 	int err, i;
+	struct blkfront_ring_info *rinfo;
 	switch (info->connected) {
 	case BLKIF_STATE_CONNECTED:
 						    "physical-sector-size",
 						    sector_size);
 	blkfront_gather_backend_features(info);
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		err = blkfront_setup_indirect(&info->rinfo[i]);
+		err = blkfront_setup_indirect(rinfo);
 		if (err) {
 			xenbus_dev_fatal(info->xbdev, err, "setup_indirect at %s",
 					 info->xbdev->otherend);
 	/* Kick pending requests. */
 	info->connected = BLKIF_STATE_CONNECTED;
-	for (i = 0; i < info->nr_rings; i++)
+	for_each_rinfo(info, rinfo, i)
-		kick_pending_request_queues(&info->rinfo[i]);
+		kick_pending_request_queues(rinfo);
 	device_add_disk(&info->xbdev->dev, info->gd, NULL);
 {
 	unsigned int i;
 	unsigned long flags;
+	struct blkfront_ring_info *rinfo;
-	for (i = 0; i < info->nr_rings; i++) {
+	for_each_rinfo(info, rinfo, i) {
-		struct blkfront_ring_info *rinfo = &info->rinfo[i];
 		struct grant *gnt_list_entry, *tmp;
 		spin_lock_irqsave(&rinfo->ring_lock, flags);

drivers/bus/ti-sysc.c+2−2

@@ -1400,7 +1400,7 @@ static void sysc_init_revision_quirks(struct sysc *ddata) · 1399 unmodified lines
1400	}	1400	}
1401		1401
1402	/* 1-wire needs module's internal clocks enabled for reset */	1402	/* 1-wire needs module's internal clocks enabled for reset */
1403	static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)	1403	static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1404	{	1404	{
1405	int offset = 0x0c; /* HDQ_CTRL_STATUS */	1405	int offset = 0x0c; /* HDQ_CTRL_STATUS */
1406	u16 val;	1406	u16 val;
@@ -1488,7 +1488,7 @@ static void sysc_init_module_quirks(struct sysc *ddata) · 81 unmodified lines
1488	return;	1488	return;
1489		1489
1490	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {	1490	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1491	ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w;	1491	ddata->clk_disable_quirk = sysc_pre_reset_quirk_hdq1w;
1492		1492
1493	return;	1493	return;
1494	}	1494	}

drivers/dma-buf/dma-buf.c+1−0

@@ -108,6 +108,7 @@ static int dma_buf_release(struct inode inode, struct file file) · 107 unmodified lines
108	dma_resv_fini(dmabuf->resv);	108	dma_resv_fini(dmabuf->resv);
109		109
110	module_put(dmabuf->owner);	110	module_put(dmabuf->owner);
		111	kfree(dmabuf->name);
111	kfree(dmabuf);	112	kfree(dmabuf);
112	return 0;	113	return 0;
113	}	114	}

drivers/dma/coh901318.c+0−4

 		return;
 	}
-	spin_lock(&cohc->lock);
 	/*
 	 * When we reach this point, at least one queue item
 	 * should have been moved over from cohc->queue to
 	if (coh901318_queue_start(cohc) == NULL)
 		cohc->busy = 0;
-	spin_unlock(&cohc->lock);
 	/*
 	 * This tasklet will remove items from cohc->active
 	 * and thus terminates them.

drivers/dma/idxd/cdev.c+2−2

 	minor = ida_simple_get(&cdev_ctx->minor_ida, 0, MINORMASK, GFP_KERNEL);
 	if (minor < 0) {
 		rc = minor;
+		kfree(dev);
 		goto ida_err;
 	}
 	rc = device_register(dev);
 	if (rc < 0) {
 		dev_err(&idxd->pdev->dev, "device register failed\n");
-		put_device(dev);
 		goto dev_reg_err;
 	}
 	idxd_cdev->minor = minor;
  dev_reg_err:
 	ida_simple_remove(&cdev_ctx->minor_ida, MINOR(dev->devt));
+	put_device(dev);
  ida_err:
-	kfree(dev);
 	idxd_cdev->dev = NULL;
 	return rc;
 }

drivers/dma/idxd/sysfs.c+23−4

 		rc = idxd_device_config(idxd);
 		if (rc < 0) {
 			spin_unlock_irqrestore(&idxd->dev_lock, flags);
+			module_put(THIS_MODULE);
 			dev_warn(dev, "Device config failed: %d\n", rc);
 			return rc;
 		}
 		rc = idxd_device_enable(idxd);
 		if (rc < 0) {
 			spin_unlock_irqrestore(&idxd->dev_lock, flags);
+			module_put(THIS_MODULE);
 			dev_warn(dev, "Device enable failed: %d\n", rc);
 			return rc;
 		}
 		rc = idxd_register_dma_device(idxd);
 		if (rc < 0) {
 			spin_unlock_irqrestore(&idxd->dev_lock, flags);
+			module_put(THIS_MODULE);
 			dev_dbg(dev, "Failed to register dmaengine device\n");
 			return rc;
 		}
 	if (val > idxd->max_tokens)
 		return -EINVAL;
-	if (val > idxd->nr_tokens)
+	if (val > idxd->nr_tokens + group->tokens_reserved)
 		return -EINVAL;
 	group->tokens_reserved = val;
 	return sprintf(buf, "%u\n", wq->size);
 }
+static int total_claimed_wq_size(struct idxd_device *idxd)
+{
+	int i;
+	int wq_size = 0;
+	for (i = 0; i < idxd->max_wqs; i++) {
+		struct idxd_wq *wq = &idxd->wqs[i];
+		wq_size += wq->size;
+	}
+	return wq_size;
+}
 static ssize_t wq_size_store(struct device *dev,
 			     struct device_attribute *attr, const char *buf,
 			     size_t count)
 	if (wq->state != IDXD_WQ_DISABLED)
 		return -EPERM;
-	if (size > idxd->max_wq_size)
+	if (size + total_claimed_wq_size(idxd) - wq->size > idxd->max_wq_size)
 		return -EINVAL;
 	wq->size = size;
 		return -EPERM;
 	old_type = wq->type;
-	if (sysfs_streq(buf, idxd_wq_type_names[IDXD_WQT_KERNEL]))
+	if (sysfs_streq(buf, idxd_wq_type_names[IDXD_WQT_NONE]))
+		wq->type = IDXD_WQT_NONE;
+	else if (sysfs_streq(buf, idxd_wq_type_names[IDXD_WQT_KERNEL]))
 		wq->type = IDXD_WQT_KERNEL;
 	else if (sysfs_streq(buf, idxd_wq_type_names[IDXD_WQT_USER]))
 		wq->type = IDXD_WQT_USER;
 	else
-		wq->type = IDXD_WQT_NONE;
+		return -EINVAL;
 	/* If we are changing queue type, clear the name */
 	if (wq->type != old_type)

drivers/dma/imx-sdma.c+3−2

 	sdma_channel_synchronize(chan);
-	if (sdmac->event_id0)
+	if (sdmac->event_id0 >= 0)
 		sdma_event_disable(sdmac, sdmac->event_id0);
 	if (sdmac->event_id1)
 		sdma_event_disable(sdmac, sdmac->event_id1);
 	sdmac->event_id0 = 0;
 	sdmac->event_id1 = 0;
+	sdmac->context_loaded = false;
 	sdma_set_channel_priority(sdmac, 0);
 	memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
 	/* Set ENBLn earlier to make sure dma request triggered after that */
-	if (sdmac->event_id0) {
+	if (sdmac->event_id0 >= 0) {
 		if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
 			return -EINVAL;
 		sdma_event_enable(sdmac, sdmac->event_id0);

drivers/dma/tegra20-apb-dma.c+1−5

 	/* Do not allocate if desc are waiting for ack */
 	list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
-		if (async_tx_test_ack(&dma_desc->txd)) {
+		if (async_tx_test_ack(&dma_desc->txd) && !dma_desc->cb_count) {
 			list_del(&dma_desc->node);
 			spin_unlock_irqrestore(&tdc->lock, flags);
 			dma_desc->txd.flags = 0;
 	bool was_busy;
 	spin_lock_irqsave(&tdc->lock, flags);
-	if (list_empty(&tdc->pending_sg_req)) {
-		spin_unlock_irqrestore(&tdc->lock, flags);
-		return 0;
-	}
 	if (!tdc->busy)
 		goto skip_dma_stop;

drivers/dma/ti/k3-udma.c+361−132

@@ -5,6 +5,7 @@ · 4 unmodified lines
5	*/	5	*/
6		6
7	#include <linux/kernel.h>	7	#include <linux/kernel.h>
		8	#include <linux/delay.h>
8	#include <linux/dmaengine.h>	9	#include <linux/dmaengine.h>
9	#include <linux/dma-mapping.h>	10	#include <linux/dma-mapping.h>
10	#include <linux/dmapool.h>	11	#include <linux/dmapool.h>
@@ -96,6 +97,24 @@ struct udma_match_data { · 85 unmodified lines
96	u32 level_start_idx[];	97	u32 level_start_idx[];
97	};	98	};
98		99
		100	struct udma_hwdesc {
		101	size_t cppi5_desc_size;
		102	void *cppi5_desc_vaddr;
		103	dma_addr_t cppi5_desc_paddr;
		104
		105	/* TR descriptor internal pointers */
		106	void *tr_req_base;
		107	struct cppi5_tr_resp_t *tr_resp_base;
		108	};
		109
		110	struct udma_rx_flush {
		111	struct udma_hwdesc hwdescs[2];
		112
		113	size_t buffer_size;
		114	void *buffer_vaddr;
		115	dma_addr_t buffer_paddr;
		116	};
		117
99	struct udma_dev {	118	struct udma_dev {
100	struct dma_device ddev;	119	struct dma_device ddev;
101	struct device *dev;	120	struct device *dev;
@@ -112,6 +131,8 @@ struct udma_dev { · 10 unmodified lines
112	struct list_head desc_to_purge;	131	struct list_head desc_to_purge;
113	spinlock_t lock;	132	spinlock_t lock;
114		133
		134	struct udma_rx_flush rx_flush;
		135
115	int tchan_cnt;	136	int tchan_cnt;
116	int echan_cnt;	137	int echan_cnt;
117	int rchan_cnt;	138	int rchan_cnt;
@@ -130,16 +151,6 @@ struct udma_dev { · 12 unmodified lines
130	u32 psil_base;	151	u32 psil_base;
131	};	152	};
132		153
133	struct udma_hwdesc {
134	size_t cppi5_desc_size;
135	void *cppi5_desc_vaddr;
136	dma_addr_t cppi5_desc_paddr;
137
138	/* TR descriptor internal pointers */
139	void *tr_req_base;
140	struct cppi5_tr_resp_t *tr_resp_base;
141	};
142
143	struct udma_desc {	154	struct udma_desc {
144	struct virt_dma_desc vd;	155	struct virt_dma_desc vd;
145		156
@@ -169,7 +180,7 @@ enum udma_chan_state { · 23 unmodified lines
169		180
170	struct udma_tx_drain {	181	struct udma_tx_drain {
171	struct delayed_work work;	182	struct delayed_work work;
172	unsigned long jiffie;	183	ktime_t tstamp;
173	u32 residue;	184	u32 residue;
174	};	185	};
175		186
@@ -502,7 +513,7 @@ static bool udma_is_chan_paused(struct udma_chan *uc) · 326 unmodified lines
502	{	513	{
503	u32 val, pause_mask;	514	u32 val, pause_mask;
504		515
505	switch (uc->desc->dir) {	516	switch (uc->config.dir) {
506	case DMA_DEV_TO_MEM:	517	case DMA_DEV_TO_MEM:
507	val = udma_rchanrt_read(uc->rchan,	518	val = udma_rchanrt_read(uc->rchan,
508	UDMA_RCHAN_RT_PEER_RT_EN_REG);	519	UDMA_RCHAN_RT_PEER_RT_EN_REG);
@@ -551,12 +562,17 @@ static void udma_sync_for_device(struct udma_chan *uc, int idx) · 42 unmodified lines
551	}	562	}
552	}	563	}
553		564
		565	static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *uc)
		566	{
		567	return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr;
		568	}
		569
554	static int udma_push_to_ring(struct udma_chan *uc, int idx)	570	static int udma_push_to_ring(struct udma_chan *uc, int idx)
555	{	571	{
556	struct udma_desc *d = uc->desc;	572	struct udma_desc *d = uc->desc;
557
558	struct k3_ring *ring = NULL;	573	struct k3_ring *ring = NULL;
559	int ret = -EINVAL;	574	dma_addr_t paddr;
		575	int ret;
560		576
561	switch (uc->config.dir) {	577	switch (uc->config.dir) {
562	case DMA_DEV_TO_MEM:	578	case DMA_DEV_TO_MEM:
@@ -567,21 +583,37 @@ static int udma_push_to_ring(struct udma_chan *uc, int idx) · 4 unmodified lines
567	ring = uc->tchan->t_ring;	583	ring = uc->tchan->t_ring;
568	break;	584	break;
569	default:	585	default:
570	break;	586	return -EINVAL;
571	}	587	}
572		588
573	if (ring) {	589	/* RX flush packet: idx == -1 is only passed in case of DEV_TO_MEM */
574	dma_addr_t desc_addr = udma_curr_cppi5_desc_paddr(d, idx);	590	if (idx == -1) {
		591	paddr = udma_get_rx_flush_hwdesc_paddr(uc);
		592	} else {
		593	paddr = udma_curr_cppi5_desc_paddr(d, idx);
575		594
576	wmb(); /* Ensure that writes are not moved over this point */	595	wmb(); /* Ensure that writes are not moved over this point */
577	udma_sync_for_device(uc, idx);	596	udma_sync_for_device(uc, idx);
578	ret = k3_ringacc_ring_push(ring, &desc_addr);
579	uc->in_ring_cnt++;
580	}	597	}
581		598
		599	ret = k3_ringacc_ring_push(ring, &paddr);
		600	if (!ret)
		601	uc->in_ring_cnt++;
		602
582	return ret;	603	return ret;
583	}	604	}
584		605
		606	static bool udma_desc_is_rx_flush(struct udma_chan *uc, dma_addr_t addr)
		607	{
		608	if (uc->config.dir != DMA_DEV_TO_MEM)
		609	return false;
		610
		611	if (addr == udma_get_rx_flush_hwdesc_paddr(uc))
		612	return true;
		613
		614	return false;
		615	}
		616
585	static int udma_pop_from_ring(struct udma_chan uc, dma_addr_t addr)	617	static int udma_pop_from_ring(struct udma_chan uc, dma_addr_t addr)
586	{	618	{
587	struct k3_ring *ring = NULL;	619	struct k3_ring *ring = NULL;
@@ -610,6 +642,10 @@ static int udma_pop_from_ring(struct udma_chan uc, dma_addr_t addr) · 22 unmodified lines
610	if (cppi5_desc_is_tdcm(*addr))	642	if (cppi5_desc_is_tdcm(*addr))
611	return ret;	643	return ret;
612		644
		645	/* Check for flush descriptor */
		646	if (udma_desc_is_rx_flush(uc, *addr))
		647	return -ENOENT;
		648
613	d = udma_udma_desc_from_paddr(uc, *addr);	649	d = udma_udma_desc_from_paddr(uc, *addr);
614		650
615	if (d)	651	if (d)
@@ -890,6 +926,9 @@ static int udma_stop(struct udma_chan *uc) · 274 unmodified lines
890		926
891	switch (uc->config.dir) {	927	switch (uc->config.dir) {
892	case DMA_DEV_TO_MEM:	928	case DMA_DEV_TO_MEM:
		929	if (!uc->cyclic && !uc->desc)
		930	udma_push_to_ring(uc, -1);
		931
893	udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,	932	udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
894	UDMA_PEER_RT_EN_ENABLE \|	933	UDMA_PEER_RT_EN_ENABLE \|
895	UDMA_PEER_RT_EN_TEARDOWN);	934	UDMA_PEER_RT_EN_TEARDOWN);
@@ -946,9 +985,10 @@ static bool udma_is_desc_really_done(struct udma_chan uc, struct udma_desc d) · 50 unmodified lines
946	peer_bcnt = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);	985	peer_bcnt = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
947	bcnt = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);	986	bcnt = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);
948		987
		988	/* Transfer is incomplete, store current residue and time stamp */
949	if (peer_bcnt < bcnt) {	989	if (peer_bcnt < bcnt) {
950	uc->tx_drain.residue = bcnt - peer_bcnt;	990	uc->tx_drain.residue = bcnt - peer_bcnt;
951	uc->tx_drain.jiffie = jiffies;	991	uc->tx_drain.tstamp = ktime_get();
952	return false;	992	return false;
953	}	993	}
954		994
@@ -961,35 +1001,59 @@ static void udma_check_tx_completion(struct work_struct *work) · 6 unmodified lines
961	tx_drain.work.work);	1001	tx_drain.work.work);
962	bool desc_done = true;	1002	bool desc_done = true;
963	u32 residue_diff;	1003	u32 residue_diff;
964	unsigned long jiffie_diff, delay;	1004	ktime_t time_diff;
		1005	unsigned long delay;
		1006
		1007	while (1) {
		1008	if (uc->desc) {
		1009	/* Get previous residue and time stamp */
		1010	residue_diff = uc->tx_drain.residue;
		1011	time_diff = uc->tx_drain.tstamp;
		1012	/*
		1013	* Get current residue and time stamp or see if
		1014	* transfer is complete
		1015	*/
		1016	desc_done = udma_is_desc_really_done(uc, uc->desc);
		1017	}
965		1018
966	if (uc->desc) {	1019	if (!desc_done) {
967	residue_diff = uc->tx_drain.residue;	1020	/*
968	jiffie_diff = uc->tx_drain.jiffie;	1021	* Find the time delta and residue delta w.r.t
969	desc_done = udma_is_desc_really_done(uc, uc->desc);	1022	* previous poll
970	}	1023	*/
971		1024	time_diff = ktime_sub(uc->tx_drain.tstamp,
972	if (!desc_done) {	1025	time_diff) + 1;
973	jiffie_diff = uc->tx_drain.jiffie - jiffie_diff;	1026	residue_diff -= uc->tx_drain.residue;
974	residue_diff -= uc->tx_drain.residue;	1027	if (residue_diff) {
975	if (residue_diff) {	1028	/*
976	/* Try to guess when we should check next time */	1029	* Try to guess when we should check
977	residue_diff /= jiffie_diff;	1030	* next time by calculating rate at
978	delay = uc->tx_drain.residue / residue_diff / 3;	1031	* which data is being drained at the
979	if (jiffies_to_msecs(delay) < 5)	1032	* peer device
980	delay = 0;	1033	*/
981	} else {	1034	delay = (time_diff / residue_diff) *
982	/* No progress, check again in 1 second */	1035	uc->tx_drain.residue;
983	delay = HZ;	1036	} else {
		1037	/* No progress, check again in 1 second */
		1038	schedule_delayed_work(&uc->tx_drain.work, HZ);
		1039	break;
		1040	}
		1041
		1042	usleep_range(ktime_to_us(delay),
		1043	ktime_to_us(delay) + 10);
		1044	continue;
984	}	1045	}
985		1046
986	schedule_delayed_work(&uc->tx_drain.work, delay);	1047	if (uc->desc) {
987	} else if (uc->desc) {	1048	struct udma_desc *d = uc->desc;
988	struct udma_desc *d = uc->desc;
989		1049
990	uc->bcnt += d->residue;	1050	uc->bcnt += d->residue;
991	udma_start(uc);	1051	udma_start(uc);
992	vchan_cookie_complete(&d->vd);	1052	vchan_cookie_complete(&d->vd);
		1053	break;
		1054	}
		1055
		1056	break;
993	}	1057	}
994	}	1058	}
995		1059
@@ -1033,29 +1097,27 @@ static irqreturn_t udma_ring_irq_handler(int irq, void *data) · 37 unmodified lines
1033	goto out;	1097	goto out;
1034	}	1098	}
1035		1099
1036	if (uc->cyclic) {	1100	if (d == uc->desc) {
1037	/* push the descriptor back to the ring */	1101	/* active descriptor */
1038	if (d == uc->desc) {	1102	if (uc->cyclic) {
1039	udma_cyclic_packet_elapsed(uc);	1103	udma_cyclic_packet_elapsed(uc);
1040	vchan_cyclic_callback(&d->vd);	1104	vchan_cyclic_callback(&d->vd);
1041	}	1105	} else {
1042	} else {	1106	if (udma_is_desc_really_done(uc, d)) {
1043	bool desc_done = false;
1044
1045	if (d == uc->desc) {
1046	desc_done = udma_is_desc_really_done(uc, d);
1047
1048	if (desc_done) {
1049	uc->bcnt += d->residue;	1107	uc->bcnt += d->residue;
1050	udma_start(uc);	1108	udma_start(uc);
		1109	vchan_cookie_complete(&d->vd);
1051	} else {	1110	} else {
1052	schedule_delayed_work(&uc->tx_drain.work,	1111	schedule_delayed_work(&uc->tx_drain.work,
1053	0);	1112	0);
1054	}	1113	}
1055	}	1114	}
1056		1115	} else {
1057	if (desc_done)	1116	/*
1058	vchan_cookie_complete(&d->vd);	1117	* terminated descriptor, mark the descriptor as
		1118	* completed to update the channel's cookie marker
		1119	*/
		1120	dma_cookie_complete(&d->vd.tx);
1059	}	1121	}
1060	}	1122	}
1061	out:	1123	out:
@@ -1965,36 +2027,81 @@ static struct udma_desc udma_alloc_tr_desc(struct udma_chan uc, · 903 unmodified lines
1965	return d;	2027	return d;
1966	}	2028	}
1967		2029
		2030	/**
		2031	* udma_get_tr_counters - calculate TR counters for a given length
		2032	* @len: Length of the trasnfer
		2033	* @align_to: Preferred alignment
		2034	* @tr0_cnt0: First TR icnt0
		2035	* @tr0_cnt1: First TR icnt1
		2036	* @tr1_cnt0: Second (if used) TR icnt0
		2037	*
		2038	* For len < SZ_64K only one TR is enough, tr1_cnt0 is not updated
		2039	* For len >= SZ_64K two TRs are used in a simple way:
		2040	* First TR: SZ_64K-alignment blocks (tr0_cnt0, tr0_cnt1)
		2041	* Second TR: the remaining length (tr1_cnt0)
		2042	*
		2043	* Returns the number of TRs the length needs (1 or 2)
		2044	* -EINVAL if the length can not be supported
		2045	*/
		2046	static int udma_get_tr_counters(size_t len, unsigned long align_to,
		2047	u16 tr0_cnt0, u16 tr0_cnt1, u16 *tr1_cnt0)
		2048	{
		2049	if (len < SZ_64K) {
		2050	*tr0_cnt0 = len;
		2051	*tr0_cnt1 = 1;
		2052
		2053	return 1;
		2054	}
		2055
		2056	if (align_to > 3)
		2057	align_to = 3;
		2058
		2059	realign:
		2060	*tr0_cnt0 = SZ_64K - BIT(align_to);
		2061	if (len / *tr0_cnt0 >= SZ_64K) {
		2062	if (align_to) {
		2063	align_to--;
		2064	goto realign;
		2065	}
		2066	return -EINVAL;
		2067	}
		2068
		2069	tr0_cnt1 = len / tr0_cnt0;
		2070	tr1_cnt0 = len % tr0_cnt0;
		2071
		2072	return 2;
		2073	}
		2074
1968	static struct udma_desc *	2075	static struct udma_desc *
1969	udma_prep_slave_sg_tr(struct udma_chan uc, struct scatterlist sgl,	2076	udma_prep_slave_sg_tr(struct udma_chan uc, struct scatterlist sgl,
1970	unsigned int sglen, enum dma_transfer_direction dir,	2077	unsigned int sglen, enum dma_transfer_direction dir,
1971	unsigned long tx_flags, void *context)	2078	unsigned long tx_flags, void *context)
1972	{	2079	{
1973	enum dma_slave_buswidth dev_width;
1974	struct scatterlist *sgent;	2080	struct scatterlist *sgent;
1975	struct udma_desc *d;	2081	struct udma_desc *d;
1976	size_t tr_size;
1977	struct cppi5_tr_type1_t *tr_req = NULL;	2082	struct cppi5_tr_type1_t *tr_req = NULL;
		2083	u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
1978	unsigned int i;	2084	unsigned int i;
1979	u32 burst;	2085	size_t tr_size;
		2086	int num_tr = 0;
		2087	int tr_idx = 0;
1980		2088
1981	if (dir == DMA_DEV_TO_MEM) {	2089	if (!is_slave_direction(dir)) {
1982	dev_width = uc->cfg.src_addr_width;	2090	dev_err(uc->ud->dev, "Only slave cyclic is supported\n");
1983	burst = uc->cfg.src_maxburst;
1984	} else if (dir == DMA_MEM_TO_DEV) {
1985	dev_width = uc->cfg.dst_addr_width;
1986	burst = uc->cfg.dst_maxburst;
1987	} else {
1988	dev_err(uc->ud->dev, "%s: bad direction?\n", __func__);
1989	return NULL;	2091	return NULL;
1990	}	2092	}
1991		2093
1992	if (!burst)	2094	/* estimate the number of TRs we will need */
1993	burst = 1;	2095	for_each_sg(sgl, sgent, sglen, i) {
		2096	if (sg_dma_len(sgent) < SZ_64K)
		2097	num_tr++;
		2098	else
		2099	num_tr += 2;
		2100	}
1994		2101
1995	/* Now allocate and setup the descriptor. */	2102	/* Now allocate and setup the descriptor. */
1996	tr_size = sizeof(struct cppi5_tr_type1_t);	2103	tr_size = sizeof(struct cppi5_tr_type1_t);
1997	d = udma_alloc_tr_desc(uc, tr_size, sglen, dir);	2104	d = udma_alloc_tr_desc(uc, tr_size, num_tr, dir);
1998	if (!d)	2105	if (!d)
1999	return NULL;	2106	return NULL;
2000		2107
@@ -2002,19 +2109,46 @@ udma_prep_slave_sg_tr(struct udma_chan uc, struct scatterlist sgl, · 1 unmodified line
2002		2109
2003	tr_req = d->hwdesc[0].tr_req_base;	2110	tr_req = d->hwdesc[0].tr_req_base;
2004	for_each_sg(sgl, sgent, sglen, i) {	2111	for_each_sg(sgl, sgent, sglen, i) {
2005	d->residue += sg_dma_len(sgent);	2112	dma_addr_t sg_addr = sg_dma_address(sgent);
		2113
		2114	num_tr = udma_get_tr_counters(sg_dma_len(sgent), __ffs(sg_addr),
		2115	&tr0_cnt0, &tr0_cnt1, &tr1_cnt0);
		2116	if (num_tr < 0) {
		2117	dev_err(uc->ud->dev, "size %u is not supported\n",
		2118	sg_dma_len(sgent));
		2119	udma_free_hwdesc(uc, d);
		2120	kfree(d);
		2121	return NULL;
		2122	}
2006		2123
2007	cppi5_tr_init(&tr_req[i].flags, CPPI5_TR_TYPE1, false, false,	2124	cppi5_tr_init(&tr_req[i].flags, CPPI5_TR_TYPE1, false, false,
2008	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);	2125	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
2009	cppi5_tr_csf_set(&tr_req[i].flags, CPPI5_TR_CSF_SUPR_EVT);	2126	cppi5_tr_csf_set(&tr_req[i].flags, CPPI5_TR_CSF_SUPR_EVT);
2010		2127
2011	tr_req[i].addr = sg_dma_address(sgent);	2128	tr_req[tr_idx].addr = sg_addr;
2012	tr_req[i].icnt0 = burst * dev_width;	2129	tr_req[tr_idx].icnt0 = tr0_cnt0;
2013	tr_req[i].dim1 = burst * dev_width;	2130	tr_req[tr_idx].icnt1 = tr0_cnt1;
2014	tr_req[i].icnt1 = sg_dma_len(sgent) / tr_req[i].icnt0;	2131	tr_req[tr_idx].dim1 = tr0_cnt0;
		2132	tr_idx++;
		2133
		2134	if (num_tr == 2) {
		2135	cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,
		2136	false, false,
		2137	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
		2138	cppi5_tr_csf_set(&tr_req[tr_idx].flags,
		2139	CPPI5_TR_CSF_SUPR_EVT);
		2140
		2141	tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0;
		2142	tr_req[tr_idx].icnt0 = tr1_cnt0;
		2143	tr_req[tr_idx].icnt1 = 1;
		2144	tr_req[tr_idx].dim1 = tr1_cnt0;
		2145	tr_idx++;
		2146	}
		2147
		2148	d->residue += sg_dma_len(sgent);
2015	}	2149	}
2016		2150
2017	cppi5_tr_csf_set(&tr_req[i - 1].flags, CPPI5_TR_CSF_EOP);	2151	cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, CPPI5_TR_CSF_EOP);
2018		2152
2019	return d;	2153	return d;
2020	}	2154	}
@@ -2319,47 +2453,66 @@ udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr, · 298 unmodified lines
2319	size_t buf_len, size_t period_len,	2453	size_t buf_len, size_t period_len,
2320	enum dma_transfer_direction dir, unsigned long flags)	2454	enum dma_transfer_direction dir, unsigned long flags)
2321	{	2455	{
2322	enum dma_slave_buswidth dev_width;
2323	struct udma_desc *d;	2456	struct udma_desc *d;
2324	size_t tr_size;	2457	size_t tr_size, period_addr;
2325	struct cppi5_tr_type1_t *tr_req;	2458	struct cppi5_tr_type1_t *tr_req;
2326	unsigned int i;
2327	unsigned int periods = buf_len / period_len;	2459	unsigned int periods = buf_len / period_len;
2328	u32 burst;	2460	u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
		2461	unsigned int i;
		2462	int num_tr;
2329		2463
2330	if (dir == DMA_DEV_TO_MEM) {	2464	if (!is_slave_direction(dir)) {
2331	dev_width = uc->cfg.src_addr_width;	2465	dev_err(uc->ud->dev, "Only slave cyclic is supported\n");
2332	burst = uc->cfg.src_maxburst;
2333	} else if (dir == DMA_MEM_TO_DEV) {
2334	dev_width = uc->cfg.dst_addr_width;
2335	burst = uc->cfg.dst_maxburst;
2336	} else {
2337	dev_err(uc->ud->dev, "%s: bad direction?\n", __func__);
2338	return NULL;	2466	return NULL;
2339	}	2467	}
2340		2468
2341	if (!burst)	2469	num_tr = udma_get_tr_counters(period_len, __ffs(buf_addr), &tr0_cnt0,
2342	burst = 1;	2470	&tr0_cnt1, &tr1_cnt0);
		2471	if (num_tr < 0) {
		2472	dev_err(uc->ud->dev, "size %zu is not supported\n",
		2473	period_len);
		2474	return NULL;
		2475	}
2343		2476
2344	/* Now allocate and setup the descriptor. */	2477	/* Now allocate and setup the descriptor. */
2345	tr_size = sizeof(struct cppi5_tr_type1_t);	2478	tr_size = sizeof(struct cppi5_tr_type1_t);
2346	d = udma_alloc_tr_desc(uc, tr_size, periods, dir);	2479	d = udma_alloc_tr_desc(uc, tr_size, periods * num_tr, dir);
2347	if (!d)	2480	if (!d)
2348	return NULL;	2481	return NULL;
2349		2482
2350	tr_req = d->hwdesc[0].tr_req_base;	2483	tr_req = d->hwdesc[0].tr_req_base;
		2484	period_addr = buf_addr;
2351	for (i = 0; i < periods; i++) {	2485	for (i = 0; i < periods; i++) {
2352	cppi5_tr_init(&tr_req[i].flags, CPPI5_TR_TYPE1, false, false,	2486	int tr_idx = i * num_tr;
2353	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
2354		2487
2355	tr_req[i].addr = buf_addr + period_len * i;	2488	cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
2356	tr_req[i].icnt0 = dev_width;	2489	false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
2357	tr_req[i].icnt1 = period_len / dev_width;	2490
2358	tr_req[i].dim1 = dev_width;	2491	tr_req[tr_idx].addr = period_addr;
		2492	tr_req[tr_idx].icnt0 = tr0_cnt0;
		2493	tr_req[tr_idx].icnt1 = tr0_cnt1;
		2494	tr_req[tr_idx].dim1 = tr0_cnt0;
		2495
		2496	if (num_tr == 2) {
		2497	cppi5_tr_csf_set(&tr_req[tr_idx].flags,
		2498	CPPI5_TR_CSF_SUPR_EVT);
		2499	tr_idx++;
		2500
		2501	cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,
		2502	false, false,
		2503	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
		2504
		2505	tr_req[tr_idx].addr = period_addr + tr0_cnt1 * tr0_cnt0;
		2506	tr_req[tr_idx].icnt0 = tr1_cnt0;
		2507	tr_req[tr_idx].icnt1 = 1;
		2508	tr_req[tr_idx].dim1 = tr1_cnt0;
		2509	}
2359		2510
2360	if (!(flags & DMA_PREP_INTERRUPT))	2511	if (!(flags & DMA_PREP_INTERRUPT))
2361	cppi5_tr_csf_set(&tr_req[i].flags,	2512	cppi5_tr_csf_set(&tr_req[tr_idx].flags,
2362	CPPI5_TR_CSF_SUPR_EVT);	2513	CPPI5_TR_CSF_SUPR_EVT);
		2514
		2515	period_addr += period_len;
2363	}	2516	}
2364		2517
2365	return d;	2518	return d;
@@ -2517,29 +2670,12 @@ udma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, · 151 unmodified lines
2517	return NULL;	2670	return NULL;
2518	}	2671	}
2519		2672
2520	if (len < SZ_64K) {	2673	num_tr = udma_get_tr_counters(len, __ffs(src \| dest), &tr0_cnt0,
2521	num_tr = 1;	2674	&tr0_cnt1, &tr1_cnt0);
2522	tr0_cnt0 = len;	2675	if (num_tr < 0) {
2523	tr0_cnt1 = 1;	2676	dev_err(uc->ud->dev, "size %zu is not supported\n",
2524	} else {	2677	len);
2525	unsigned long align_to = __ffs(src \| dest);	2678	return NULL;
2526
2527	if (align_to > 3)
2528	align_to = 3;
2529	/*
2530	* Keep simple: tr0: SZ_64K-alignment blocks,
2531	* tr1: the remaining
2532	*/
2533	num_tr = 2;
2534	tr0_cnt0 = (SZ_64K - BIT(align_to));
2535	if (len / tr0_cnt0 >= SZ_64K) {
2536	dev_err(uc->ud->dev, "size %zu is not supported\n",
2537	len);
2538	return NULL;
2539	}
2540
2541	tr0_cnt1 = len / tr0_cnt0;
2542	tr1_cnt0 = len % tr0_cnt0;
2543	}	2679	}
2544		2680
2545	d = udma_alloc_tr_desc(uc, tr_size, num_tr, DMA_MEM_TO_MEM);	2681	d = udma_alloc_tr_desc(uc, tr_size, num_tr, DMA_MEM_TO_MEM);
@@ -2631,6 +2767,9 @@ static enum dma_status udma_tx_status(struct dma_chan *chan, · 85 unmodified lines
2631		2767
2632	ret = dma_cookie_status(chan, cookie, txstate);	2768	ret = dma_cookie_status(chan, cookie, txstate);
2633		2769
		2770	if (!udma_is_chan_running(uc))
		2771	ret = DMA_COMPLETE;
		2772
2634	if (ret == DMA_IN_PROGRESS && udma_is_chan_paused(uc))	2773	if (ret == DMA_IN_PROGRESS && udma_is_chan_paused(uc))
2635	ret = DMA_PAUSED;	2774	ret = DMA_PAUSED;
2636		2775
@@ -2697,11 +2836,8 @@ static int udma_pause(struct dma_chan *chan) · 60 unmodified lines
2697	{	2836	{
2698	struct udma_chan *uc = to_udma_chan(chan);	2837	struct udma_chan *uc = to_udma_chan(chan);
2699		2838
2700	if (!uc->desc)
2701	return -EINVAL;
2702
2703	/* pause the channel */	2839	/* pause the channel */
2704	switch (uc->desc->dir) {	2840	switch (uc->config.dir) {
2705	case DMA_DEV_TO_MEM:	2841	case DMA_DEV_TO_MEM:
2706	udma_rchanrt_update_bits(uc->rchan,	2842	udma_rchanrt_update_bits(uc->rchan,
2707	UDMA_RCHAN_RT_PEER_RT_EN_REG,	2843	UDMA_RCHAN_RT_PEER_RT_EN_REG,
@@ -2730,11 +2866,8 @@ static int udma_resume(struct dma_chan *chan) · 22 unmodified lines
2730	{	2866	{
2731	struct udma_chan *uc = to_udma_chan(chan);	2867	struct udma_chan *uc = to_udma_chan(chan);
2732		2868
2733	if (!uc->desc)
2734	return -EINVAL;
2735
2736	/* resume the channel */	2869	/* resume the channel */
2737	switch (uc->desc->dir) {	2870	switch (uc->config.dir) {
2738	case DMA_DEV_TO_MEM:	2871	case DMA_DEV_TO_MEM:
2739	udma_rchanrt_update_bits(uc->rchan,	2872	udma_rchanrt_update_bits(uc->rchan,
2740	UDMA_RCHAN_RT_PEER_RT_EN_REG,	2873	UDMA_RCHAN_RT_PEER_RT_EN_REG,
@@ -3248,6 +3381,98 @@ static int udma_setup_resources(struct udma_dev *ud) · 507 unmodified lines
3248	return ch_count;	3381	return ch_count;
3249	}	3382	}
3250		3383
		3384	static int udma_setup_rx_flush(struct udma_dev *ud)
		3385	{
		3386	struct udma_rx_flush *rx_flush = &ud->rx_flush;
		3387	struct cppi5_desc_hdr_t *tr_desc;
		3388	struct cppi5_tr_type1_t *tr_req;
		3389	struct cppi5_host_desc_t *desc;
		3390	struct device *dev = ud->dev;
		3391	struct udma_hwdesc *hwdesc;
		3392	size_t tr_size;
		3393
		3394	/* Allocate 1K buffer for discarded data on RX channel teardown */
		3395	rx_flush->buffer_size = SZ_1K;
		3396	rx_flush->buffer_vaddr = devm_kzalloc(dev, rx_flush->buffer_size,
		3397	GFP_KERNEL);
		3398	if (!rx_flush->buffer_vaddr)
		3399	return -ENOMEM;
		3400
		3401	rx_flush->buffer_paddr = dma_map_single(dev, rx_flush->buffer_vaddr,
		3402	rx_flush->buffer_size,
		3403	DMA_TO_DEVICE);
		3404	if (dma_mapping_error(dev, rx_flush->buffer_paddr))
		3405	return -ENOMEM;
		3406
		3407	/* Set up descriptor to be used for TR mode */
		3408	hwdesc = &rx_flush->hwdescs[0];
		3409	tr_size = sizeof(struct cppi5_tr_type1_t);
		3410	hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, 1);
		3411	hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size,
		3412	ud->desc_align);
		3413
		3414	hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
		3415	GFP_KERNEL);
		3416	if (!hwdesc->cppi5_desc_vaddr)
		3417	return -ENOMEM;
		3418
		3419	hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
		3420	hwdesc->cppi5_desc_size,
		3421	DMA_TO_DEVICE);
		3422	if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
		3423	return -ENOMEM;
		3424
		3425	/* Start of the TR req records */
		3426	hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size;
		3427	/* Start address of the TR response array */
		3428	hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size;
		3429
		3430	tr_desc = hwdesc->cppi5_desc_vaddr;
		3431	cppi5_trdesc_init(tr_desc, 1, tr_size, 0, 0);
		3432	cppi5_desc_set_pktids(tr_desc, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
		3433	cppi5_desc_set_retpolicy(tr_desc, 0, 0);
		3434
		3435	tr_req = hwdesc->tr_req_base;
		3436	cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false,
		3437	CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
		3438	cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT);
		3439
		3440	tr_req->addr = rx_flush->buffer_paddr;
		3441	tr_req->icnt0 = rx_flush->buffer_size;
		3442	tr_req->icnt1 = 1;
		3443
		3444	/* Set up descriptor to be used for packet mode */
		3445	hwdesc = &rx_flush->hwdescs[1];
		3446	hwdesc->cppi5_desc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
		3447	CPPI5_INFO0_HDESC_EPIB_SIZE +
		3448	CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE,
		3449	ud->desc_align);
		3450
		3451	hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
		3452	GFP_KERNEL);
		3453	if (!hwdesc->cppi5_desc_vaddr)
		3454	return -ENOMEM;
		3455
		3456	hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
		3457	hwdesc->cppi5_desc_size,
		3458	DMA_TO_DEVICE);
		3459	if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
		3460	return -ENOMEM;
		3461
		3462	desc = hwdesc->cppi5_desc_vaddr;
		3463	cppi5_hdesc_init(desc, 0, 0);
		3464	cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
		3465	cppi5_desc_set_retpolicy(&desc->hdr, 0, 0);
		3466
		3467	cppi5_hdesc_attach_buf(desc,
		3468	rx_flush->buffer_paddr, rx_flush->buffer_size,
		3469	rx_flush->buffer_paddr, rx_flush->buffer_size);
		3470
		3471	dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr,
		3472	hwdesc->cppi5_desc_size, DMA_TO_DEVICE);
		3473	return 0;
		3474	}
		3475
3251	#define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) \| \	3476	#define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) \| \
3252	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) \| \	3477	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) \| \
3253	BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) \| \	3478	BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) \| \
@@ -3361,6 +3586,10 @@ static int udma_probe(struct platform_device *pdev) · 107 unmodified lines
3361	if (ud->desc_align < dma_get_cache_alignment())	3586	if (ud->desc_align < dma_get_cache_alignment())
3362	ud->desc_align = dma_get_cache_alignment();	3587	ud->desc_align = dma_get_cache_alignment();
3363		3588
		3589	ret = udma_setup_rx_flush(ud);
		3590	if (ret)
		3591	return ret;
		3592
3364	for (i = 0; i < ud->tchan_cnt; i++) {	3593	for (i = 0; i < ud->tchan_cnt; i++) {
3365	struct udma_tchan *tchan = &ud->tchans[i];	3594	struct udma_tchan *tchan = &ud->tchans[i];
3366		3595

drivers/edac/synopsys_edac.c+7−15

 		pinf = &p->ceinfo;
 		if (!priv->p_data->quirks) {
 			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "DDR ECC error type:%s Row %d Bank %d Col %d ",
+				 "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x",
-				  "CE", pinf->row, pinf->bank, pinf->col);
+				 "CE", pinf->row, pinf->bank, pinf->col,
-			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "Bit Position: %d Data: 0x%08x\n",
 				 pinf->bitpos, pinf->data);
 		} else {
 			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "DDR ECC error type:%s Row %d Bank %d Col %d ",
+				 "DDR ECC error type:%s Row %d Bank %d Col %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x",
-				  "CE", pinf->row, pinf->bank, pinf->col);
+				 "CE", pinf->row, pinf->bank, pinf->col,
-			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
+				 pinf->bankgrpnr, pinf->blknr,
-				 "BankGroup Number %d Block Number %d ",
-				 pinf->bankgrpnr, pinf->blknr);
-			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "Bit Position: %d Data: 0x%08x\n",
 				 pinf->bitpos, pinf->data);
 		}
 				"UE", pinf->row, pinf->bank, pinf->col);
 		} else {
 			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "DDR ECC error type :%s Row %d Bank %d Col %d ",
+				 "DDR ECC error type :%s Row %d Bank %d Col %d BankGroup Number %d Block Number %d",
-				 "UE", pinf->row, pinf->bank, pinf->col);
+				 "UE", pinf->row, pinf->bank, pinf->col,
-			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-				 "BankGroup Number %d Block Number %d",
 				 pinf->bankgrpnr, pinf->blknr);
 		}

drivers/firmware/efi/efi.c+2−2

@@ -552,7 +552,7 @@ int __init efi_config_parse_tables(void *config_tables, int count, int sz, · 551 unmodified lines
552		552
553	seed = early_memremap(efi.rng_seed, sizeof(*seed));	553	seed = early_memremap(efi.rng_seed, sizeof(*seed));
554	if (seed != NULL) {	554	if (seed != NULL) {
555	size = seed->size;	555	size = READ_ONCE(seed->size);
556	early_memunmap(seed, sizeof(*seed));	556	early_memunmap(seed, sizeof(*seed));
557	} else {	557	} else {
558	pr_err("Could not map UEFI random seed!\n");	558	pr_err("Could not map UEFI random seed!\n");
@@ -562,7 +562,7 @@ int __init efi_config_parse_tables(void *config_tables, int count, int sz, · 3 unmodified lines
562	sizeof(*seed) + size);	562	sizeof(*seed) + size);
563	if (seed != NULL) {	563	if (seed != NULL) {
564	pr_notice("seeding entropy pool\n");	564	pr_notice("seeding entropy pool\n");
565	add_bootloader_randomness(seed->bits, seed->size);	565	add_bootloader_randomness(seed->bits, size);
566	early_memunmap(seed, sizeof(*seed) + size);	566	early_memunmap(seed, sizeof(*seed) + size);
567	} else {	567	} else {
568	pr_err("Could not map UEFI random seed!\n");	568	pr_err("Could not map UEFI random seed!\n");

drivers/firmware/imx/imx-scu.c+27−0

@@ -29,6 +29,7 @@ struct imx_sc_chan { · 28 unmodified lines
29	struct mbox_client cl;	29	struct mbox_client cl;
30	struct mbox_chan *ch;	30	struct mbox_chan *ch;
31	int idx;	31	int idx;
		32	struct completion tx_done;
32	};	33	};
33		34
34	struct imx_sc_ipc {	35	struct imx_sc_ipc {
@@ -100,6 +101,14 @@ int imx_scu_get_handle(struct imx_sc_ipc **ipc) · 65 unmodified lines
100	}	101	}
101	EXPORT_SYMBOL(imx_scu_get_handle);	102	EXPORT_SYMBOL(imx_scu_get_handle);
102		103
		104	/* Callback called when the word of a message is ack-ed, eg read by SCU */
		105	static void imx_scu_tx_done(struct mbox_client cl, void mssg, int r)
		106	{
		107	struct imx_sc_chan *sc_chan = container_of(cl, struct imx_sc_chan, cl);
		108
		109	complete(&sc_chan->tx_done);
		110	}
		111
103	static void imx_scu_rx_callback(struct mbox_client c, void msg)	112	static void imx_scu_rx_callback(struct mbox_client c, void msg)
104	{	113	{
105	struct imx_sc_chan *sc_chan = container_of(c, struct imx_sc_chan, cl);	114	struct imx_sc_chan *sc_chan = container_of(c, struct imx_sc_chan, cl);
@@ -149,6 +158,19 @@ static int imx_scu_ipc_write(struct imx_sc_ipc sc_ipc, void msg) · 43 unmodified lines
149		158
150	for (i = 0; i < hdr->size; i++) {	159	for (i = 0; i < hdr->size; i++) {
151	sc_chan = &sc_ipc->chans[i % 4];	160	sc_chan = &sc_ipc->chans[i % 4];
		161
		162	/*
		163	* SCU requires that all messages words are written
		164	* sequentially but linux MU driver implements multiple
		165	* independent channels for each register so ordering between
		166	* different channels must be ensured by SCU API interface.
		167	*
		168	* Wait for tx_done before every send to ensure that no
		169	* queueing happens at the mailbox channel level.
		170	*/
		171	wait_for_completion(&sc_chan->tx_done);
		172	reinit_completion(&sc_chan->tx_done);
		173
152	ret = mbox_send_message(sc_chan->ch, &data[i]);	174	ret = mbox_send_message(sc_chan->ch, &data[i]);
153	if (ret < 0)	175	if (ret < 0)
154	return ret;	176	return ret;
@@ -247,6 +269,11 @@ static int imx_scu_probe(struct platform_device *pdev) · 92 unmodified lines
247	cl->knows_txdone = true;	269	cl->knows_txdone = true;
248	cl->rx_callback = imx_scu_rx_callback;	270	cl->rx_callback = imx_scu_rx_callback;
249		271
		272	/* Initial tx_done completion as "done" */
		273	cl->tx_done = imx_scu_tx_done;
		274	init_completion(&sc_chan->tx_done);
		275	complete(&sc_chan->tx_done);
		276
250	sc_chan->sc_ipc = sc_ipc;	277	sc_chan->sc_ipc = sc_ipc;
251	sc_chan->idx = i % 4;	278	sc_chan->idx = i % 4;
252	sc_chan->ch = mbox_request_channel_byname(cl, chan_name);	279	sc_chan->ch = mbox_request_channel_byname(cl, chan_name);

drivers/firmware/imx/misc.c+4−4

@@ -16,7 +16,7 @@ struct imx_sc_msg_req_misc_set_ctrl { · 15 unmodified lines
16	u32 ctrl;	16	u32 ctrl;
17	u32 val;	17	u32 val;
18	u16 resource;	18	u16 resource;
19	} __packed;	19	} __packed __aligned(4);
20		20
21	struct imx_sc_msg_req_cpu_start {	21	struct imx_sc_msg_req_cpu_start {
22	struct imx_sc_rpc_msg hdr;	22	struct imx_sc_rpc_msg hdr;
@@ -24,18 +24,18 @@ struct imx_sc_msg_req_cpu_start { · 1 unmodified line
24	u32 address_lo;	24	u32 address_lo;
25	u16 resource;	25	u16 resource;
26	u8 enable;	26	u8 enable;
27	} __packed;	27	} __packed __aligned(4);
28		28
29	struct imx_sc_msg_req_misc_get_ctrl {	29	struct imx_sc_msg_req_misc_get_ctrl {
30	struct imx_sc_rpc_msg hdr;	30	struct imx_sc_rpc_msg hdr;
31	u32 ctrl;	31	u32 ctrl;
32	u16 resource;	32	u16 resource;
33	} __packed;	33	} __packed __aligned(4);
34		34
35	struct imx_sc_msg_resp_misc_get_ctrl {	35	struct imx_sc_msg_resp_misc_get_ctrl {
36	struct imx_sc_rpc_msg hdr;	36	struct imx_sc_rpc_msg hdr;
37	u32 val;	37	u32 val;
38	} __packed;	38	} __packed __aligned(4);
39		39
40	/*	40	/*
41	* This function sets a miscellaneous control value.	41	* This function sets a miscellaneous control value.

drivers/firmware/imx/scu-pd.c+1−1

@@ -61,7 +61,7 @@ struct imx_sc_msg_req_set_resource_power_mode { · 60 unmodified lines
61	struct imx_sc_rpc_msg hdr;	61	struct imx_sc_rpc_msg hdr;
62	u16 resource;	62	u16 resource;
63	u8 mode;	63	u8 mode;
64	} __packed;	64	} __packed __aligned(4);
65		65
66	#define IMX_SCU_PD_NAME_SIZE 20	66	#define IMX_SCU_PD_NAME_SIZE 20
67	struct imx_sc_pm_domain {	67	struct imx_sc_pm_domain {

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+52−46

@@ -52,7 +52,7 @@ · 51 unmodified lines
52	* 1. Primary ring	52	* 1. Primary ring
53	* 2. Async ring	53	* 2. Async ring
54	*/	54	*/
55	#define GFX10_NUM_GFX_RINGS 2	55	#define GFX10_NUM_GFX_RINGS_NV1X 1
56	#define GFX10_MEC_HPD_SIZE 2048	56	#define GFX10_MEC_HPD_SIZE 2048
57		57
58	#define F32_CE_PROGRAM_RAM_SIZE 65536	58	#define F32_CE_PROGRAM_RAM_SIZE 65536
@@ -1304,7 +1304,7 @@ static int gfx_v10_0_sw_init(void *handle) · 1245 unmodified lines
1304	case CHIP_NAVI14:	1304	case CHIP_NAVI14:
1305	case CHIP_NAVI12:	1305	case CHIP_NAVI12:
1306	adev->gfx.me.num_me = 1;	1306	adev->gfx.me.num_me = 1;
1307	adev->gfx.me.num_pipe_per_me = 2;	1307	adev->gfx.me.num_pipe_per_me = 1;
1308	adev->gfx.me.num_queue_per_pipe = 1;	1308	adev->gfx.me.num_queue_per_pipe = 1;
1309	adev->gfx.mec.num_mec = 2;	1309	adev->gfx.mec.num_mec = 2;
1310	adev->gfx.mec.num_pipe_per_mec = 4;	1310	adev->gfx.mec.num_pipe_per_mec = 4;
@@ -2710,18 +2710,20 @@ static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) · 1399 unmodified lines
2710	amdgpu_ring_commit(ring);	2710	amdgpu_ring_commit(ring);
2711		2711
2712	/* submit cs packet to copy state 0 to next available state */	2712	/* submit cs packet to copy state 0 to next available state */
2713	ring = &adev->gfx.gfx_ring[1];	2713	if (adev->gfx.num_gfx_rings > 1) {
2714	r = amdgpu_ring_alloc(ring, 2);	2714	/* maximum supported gfx ring is 2 */
2715	if (r) {	2715	ring = &adev->gfx.gfx_ring[1];
2716	DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);	2716	r = amdgpu_ring_alloc(ring, 2);
2717	return r;	2717	if (r) {
2718	}	2718	DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2719		2719	return r;
2720	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));	2720	}
2721	amdgpu_ring_write(ring, 0);
2722		2721
2723	amdgpu_ring_commit(ring);	2722	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
		2723	amdgpu_ring_write(ring, 0);
2724		2724
		2725	amdgpu_ring_commit(ring);
		2726	}
2725	return 0;	2727	return 0;
2726	}	2728	}
2727		2729
@@ -2818,39 +2820,41 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) · 90 unmodified lines
2818	mutex_unlock(&adev->srbm_mutex);	2820	mutex_unlock(&adev->srbm_mutex);
2819		2821
2820	/* Init gfx ring 1 for pipe 1 */	2822	/* Init gfx ring 1 for pipe 1 */
2821	mutex_lock(&adev->srbm_mutex);	2823	if (adev->gfx.num_gfx_rings > 1) {
2822	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);	2824	mutex_lock(&adev->srbm_mutex);
2823	ring = &adev->gfx.gfx_ring[1];	2825	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2824	rb_bufsz = order_base_2(ring->ring_size / 8);	2826	/* maximum supported gfx ring is 2 */
2825	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);	2827	ring = &adev->gfx.gfx_ring[1];
2826	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);	2828	rb_bufsz = order_base_2(ring->ring_size / 8);
2827	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);	2829	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2828	/* Initialize the ring buffer's write pointers */	2830	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2829	ring->wptr = 0;	2831	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2830	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));	2832	/* Initialize the ring buffer's write pointers */
2831	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));	2833	ring->wptr = 0;
2832	/* Set the wb address wether it's enabled or not */	2834	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2833	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);	2835	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2834	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));	2836	/* Set the wb address wether it's enabled or not */
2835	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &	2837	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2836	CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);	2838	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2837	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);	2839	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2838	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,	2840	CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2839	lower_32_bits(wptr_gpu_addr));	2841	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2840	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,	2842	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2841	upper_32_bits(wptr_gpu_addr));	2843	lower_32_bits(wptr_gpu_addr));
2842		2844	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2843	mdelay(1);	2845	upper_32_bits(wptr_gpu_addr));
2844	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);	2846
2845		2847	mdelay(1);
2846	rb_addr = ring->gpu_addr >> 8;	2848	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2847	WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);	2849
2848	WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));	2850	rb_addr = ring->gpu_addr >> 8;
2849	WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);	2851	WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2850		2852	WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2851	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);	2853	WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2852	mutex_unlock(&adev->srbm_mutex);	2854
2853		2855	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
		2856	mutex_unlock(&adev->srbm_mutex);
		2857	}
2854	/* Switch to pipe 0 */	2858	/* Switch to pipe 0 */
2855	mutex_lock(&adev->srbm_mutex);	2859	mutex_lock(&adev->srbm_mutex);
2856	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);	2860	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
@@ -3513,6 +3517,7 @@ static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) · 656 unmodified lines
3513		3517
3514	/* reset ring buffer */	3518	/* reset ring buffer */
3515	ring->wptr = 0;	3519	ring->wptr = 0;
		3520	atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
3516	amdgpu_ring_clear_ring(ring);	3521	amdgpu_ring_clear_ring(ring);
3517	} else {	3522	} else {
3518	amdgpu_ring_clear_ring(ring);	3523	amdgpu_ring_clear_ring(ring);
@@ -3966,7 +3971,8 @@ static int gfx_v10_0_early_init(void *handle) · 447 unmodified lines
3966	{	3971	{
3967	struct amdgpu_device adev = (struct amdgpu_device )handle;	3972	struct amdgpu_device adev = (struct amdgpu_device )handle;
3968		3973
3969	adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;	3974	adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
		3975
3970	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;	3976	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3971		3977
3972	gfx_v10_0_set_kiq_pm4_funcs(adev);	3978	gfx_v10_0_set_kiq_pm4_funcs(adev);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+1−0

@@ -3663,6 +3663,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) · 3662 unmodified lines
3663		3663
3664	/* reset ring buffer */	3664	/* reset ring buffer */
3665	ring->wptr = 0;	3665	ring->wptr = 0;
		3666	atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
3666	amdgpu_ring_clear_ring(ring);	3667	amdgpu_ring_clear_ring(ring);
3667	} else {	3668	} else {
3668	amdgpu_ring_clear_ring(ring);	3669	amdgpu_ring_clear_ring(ring);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+69−0

@@ -1422,6 +1422,73 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) · 1421 unmodified lines
1422	drm_kms_helper_hotplug_event(dev);	1422	drm_kms_helper_hotplug_event(dev);
1423	}	1423	}
1424		1424
		1425	static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
		1426	{
		1427	struct smu_context *smu = &adev->smu;
		1428	int ret = 0;
		1429
		1430	if (!is_support_sw_smu(adev))
		1431	return 0;
		1432
		1433	/* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
		1434	* on window driver dc implementation.
		1435	* For Navi1x, clock settings of dcn watermarks are fixed. the settings
		1436	* should be passed to smu during boot up and resume from s3.
		1437	* boot up: dc calculate dcn watermark clock settings within dc_create,
		1438	* dcn20_resource_construct
		1439	* then call pplib functions below to pass the settings to smu:
		1440	* smu_set_watermarks_for_clock_ranges
		1441	* smu_set_watermarks_table
		1442	* navi10_set_watermarks_table
		1443	* smu_write_watermarks_table
		1444	*
		1445	* For Renoir, clock settings of dcn watermark are also fixed values.
		1446	* dc has implemented different flow for window driver:
		1447	* dc_hardware_init / dc_set_power_state
		1448	* dcn10_init_hw
		1449	* notify_wm_ranges
		1450	* set_wm_ranges
		1451	* -- Linux
		1452	* smu_set_watermarks_for_clock_ranges
		1453	* renoir_set_watermarks_table
		1454	* smu_write_watermarks_table
		1455	*
		1456	* For Linux,
		1457	* dc_hardware_init -> amdgpu_dm_init
		1458	* dc_set_power_state --> dm_resume
		1459	*
		1460	* therefore, this function apply to navi10/12/14 but not Renoir
		1461	* *
		1462	*/
		1463	switch(adev->asic_type) {
		1464	case CHIP_NAVI10:
		1465	case CHIP_NAVI14:
		1466	case CHIP_NAVI12:
		1467	break;
		1468	default:
		1469	return 0;
		1470	}
		1471
		1472	mutex_lock(&smu->mutex);
		1473
		1474	/* pass data to smu controller */
		1475	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
		1476	!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
		1477	ret = smu_write_watermarks_table(smu);
		1478
		1479	if (ret) {
		1480	mutex_unlock(&smu->mutex);
		1481	DRM_ERROR("Failed to update WMTABLE!\n");
		1482	return ret;
		1483	}
		1484	smu->watermarks_bitmap \|= WATERMARKS_LOADED;
		1485	}
		1486
		1487	mutex_unlock(&smu->mutex);
		1488
		1489	return 0;
		1490	}
		1491
1425	/**	1492	/**
1426	* dm_hw_init() - Initialize DC device	1493	* dm_hw_init() - Initialize DC device
1427	* @handle: The base driver device containing the amdgpu_dm device.	1494	* @handle: The base driver device containing the amdgpu_dm device.
@@ -1700,6 +1767,8 @@ static int dm_resume(void *handle) · 272 unmodified lines
1700		1767
1701	amdgpu_dm_irq_resume_late(adev);	1768	amdgpu_dm_irq_resume_late(adev);
1702		1769
		1770	amdgpu_dm_smu_write_watermarks_table(adev);
		1771
1703	return 0;	1772	return 0;
1704	}	1773	}
1705		1774

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+1−0

@@ -451,6 +451,7 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, · 450 unmodified lines
451	aconnector->dc_sink);	451	aconnector->dc_sink);
452	dc_sink_release(aconnector->dc_sink);	452	dc_sink_release(aconnector->dc_sink);
453	aconnector->dc_sink = NULL;	453	aconnector->dc_sink = NULL;
		454	aconnector->dc_link->cur_link_settings.lane_count = 0;
454	}	455	}
455		456
456	drm_connector_unregister(connector);	457	drm_connector_unregister(connector);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c+2−2

@@ -840,8 +840,8 @@ static void hubbub1_det_request_size( · 839 unmodified lines
840		840
841	hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);	841	hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);
842		842
843	swath_bytes_horz_wc = height * blk256_height * bpe;	843	swath_bytes_horz_wc = width * blk256_height * bpe;
844	swath_bytes_vert_wc = width * blk256_width * bpe;	844	swath_bytes_vert_wc = height * blk256_width * bpe;
845		845
846	req128_horz_wc = (2 swath_bytes_horz_wc <= detile_buf_size) ?	846	req128_horz_wc = (2 swath_bytes_horz_wc <= detile_buf_size) ?
847	false : /* full 256B request */	847	false : /* full 256B request */

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c+1−1

@@ -222,7 +222,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, · 221 unmodified lines
222	{	222	{
223	int ret = 0;	223	int ret = 0;
224		224
225	if (min <= 0 && max <= 0)	225	if (min < 0 && max < 0)
226	return -EINVAL;	226	return -EINVAL;
227		227
228	if (!smu_clk_dpm_is_enabled(smu, clk_type))	228	if (!smu_clk_dpm_is_enabled(smu, clk_type))

drivers/gpu/drm/amd/powerplay/renoir_ppt.c+3−3

@@ -111,8 +111,8 @@ static struct smu_12_0_cmn2aisc_mapping renoir_clk_map[SMU_CLK_COUNT] = { · 110 unmodified lines
111	CLK_MAP(GFXCLK, CLOCK_GFXCLK),	111	CLK_MAP(GFXCLK, CLOCK_GFXCLK),
112	CLK_MAP(SCLK, CLOCK_GFXCLK),	112	CLK_MAP(SCLK, CLOCK_GFXCLK),
113	CLK_MAP(SOCCLK, CLOCK_SOCCLK),	113	CLK_MAP(SOCCLK, CLOCK_SOCCLK),
114	CLK_MAP(UCLK, CLOCK_UMCCLK),	114	CLK_MAP(UCLK, CLOCK_FCLK),
115	CLK_MAP(MCLK, CLOCK_UMCCLK),	115	CLK_MAP(MCLK, CLOCK_FCLK),
116	};	116	};
117		117
118	static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {	118	static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
@@ -280,7 +280,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, · 161 unmodified lines
280	break;	280	break;
281	case SMU_MCLK:	281	case SMU_MCLK:
282	count = NUM_MEMCLK_DPM_LEVELS;	282	count = NUM_MEMCLK_DPM_LEVELS;
283	cur_value = metrics.ClockFrequency[CLOCK_UMCCLK];	283	cur_value = metrics.ClockFrequency[CLOCK_FCLK];
284	break;	284	break;
285	case SMU_DCEFCLK:	285	case SMU_DCEFCLK:
286	count = NUM_DCFCLK_DPM_LEVELS;	286	count = NUM_DCFCLK_DPM_LEVELS;

drivers/gpu/drm/amd/powerplay/smu_v12_0.c+0−3

@@ -458,9 +458,6 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ · 457 unmodified lines
458	{	458	{
459	int ret = 0;	459	int ret = 0;
460		460
461	if (max < min)
462	return -EINVAL;
463
464	switch (clk_type) {	461	switch (clk_type) {
465	case SMU_GFXCLK:	462	case SMU_GFXCLK:
466	case SMU_SCLK:	463	case SMU_SCLK:

drivers/gpu/drm/bridge/analogix/analogix-anx6345.c+1−2

@@ -210,8 +210,7 @@ static int anx6345_dp_link_training(struct anx6345 *anx6345) · 209 unmodified lines
210	if (err)	210	if (err)
211	return err;	211	return err;
212		212
213	dpcd[0] = drm_dp_max_link_rate(anx6345->dpcd);	213	dpcd[0] = dp_bw;
214	dpcd[0] = drm_dp_link_rate_to_bw_code(dpcd[0]);
215	err = regmap_write(anx6345->map[I2C_IDX_DPTX],	214	err = regmap_write(anx6345->map[I2C_IDX_DPTX],
216	SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);	215	SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);
217	if (err)	216	if (err)

drivers/gpu/drm/drm_gem_shmem_helper.c+11−5

 	if (ret)
 		goto err_zero_use;
-	if (obj->import_attach)
+	if (obj->import_attach) {
 		shmem->vaddr = dma_buf_vmap(obj->import_attach->dmabuf);
-	else
+	} else {
+		pgprot_t prot = PAGE_KERNEL;
+		if (!shmem->map_cached)
+			prot = pgprot_writecombine(prot);
 		shmem->vaddr = vmap(shmem->pages, obj->size >> PAGE_SHIFT,
-				    VM_MAP, pgprot_writecombine(PAGE_KERNEL));
+				    VM_MAP, prot);
+	}
 	if (!shmem->vaddr) {
 		DRM_DEBUG_KMS("Failed to vmap pages\n");
 	}
 	vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND;
-	vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
+	vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
-	vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
+	if (!shmem->map_cached)
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 	vma->vm_ops = &drm_gem_shmem_vm_ops;
 	return 0;

drivers/gpu/drm/exynos/exynos_drm_dsi.c+7−5

 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
 				      dsi->supplies);
 	if (ret) {
-		dev_info(dev, "failed to get regulators: %d\n", ret);
+		if (ret != -EPROBE_DEFER)
-		return -EPROBE_DEFER;
+			dev_info(dev, "failed to get regulators: %d\n", ret);
+		return ret;
 	}
 	dsi->clks = devm_kcalloc(dev,
 		dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
 		if (IS_ERR(dsi->clks[i])) {
 			if (strcmp(clk_names[i], "sclk_mipi") == 0) {
-				strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
+				dsi->clks[i] = devm_clk_get(dev,
-				i--;
+							OLD_SCLK_MIPI_CLK_NAME);
-				continue;
+				if (!IS_ERR(dsi->clks[i]))
+					continue;
 			}
 			dev_info(dev, "failed to get the clock: %s\n",

drivers/gpu/drm/exynos/exynos_hdmi.c+12−10

@@ -1805,18 +1805,10 @@ static int hdmi_resources_init(struct hdmi_context *hdata) · 1804 unmodified lines
1805		1805
1806	hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");	1806	hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");
1807		1807
1808	if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) {	1808	if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV)
1809	if (IS_ERR(hdata->reg_hdmi_en))	1809	if (IS_ERR(hdata->reg_hdmi_en))
1810	return PTR_ERR(hdata->reg_hdmi_en);	1810	return PTR_ERR(hdata->reg_hdmi_en);
1811		1811
1812	ret = regulator_enable(hdata->reg_hdmi_en);
1813	if (ret) {
1814	DRM_DEV_ERROR(dev,
1815	"failed to enable hdmi-en regulator\n");
1816	return ret;
1817	}
1818	}
1819
1820	return hdmi_bridge_init(hdata);	1812	return hdmi_bridge_init(hdata);
1821	}	1813	}
1822		1814
@@ -2023,6 +2015,15 @@ static int hdmi_probe(struct platform_device *pdev) · 200 unmodified lines
2023	}	2015	}
2024	}	2016	}
2025		2017
		2018	if (!IS_ERR(hdata->reg_hdmi_en)) {
		2019	ret = regulator_enable(hdata->reg_hdmi_en);
		2020	if (ret) {
		2021	DRM_DEV_ERROR(dev,
		2022	"failed to enable hdmi-en regulator\n");
		2023	goto err_hdmiphy;
		2024	}
		2025	}
		2026
2026	pm_runtime_enable(dev);	2027	pm_runtime_enable(dev);
2027		2028
2028	audio_infoframe = &hdata->audio.infoframe;	2029	audio_infoframe = &hdata->audio.infoframe;
@@ -2047,7 +2048,8 @@ err_unregister_audio: · 18 unmodified lines
2047		2048
2048	err_rpm_disable:	2049	err_rpm_disable:
2049	pm_runtime_disable(dev);	2050	pm_runtime_disable(dev);
2050		2051	if (!IS_ERR(hdata->reg_hdmi_en))
		2052	regulator_disable(hdata->reg_hdmi_en);
2051	err_hdmiphy:	2053	err_hdmiphy:
2052	if (hdata->hdmiphy_port)	2054	if (hdata->hdmiphy_port)
2053	put_device(&hdata->hdmiphy_port->dev);	2055	put_device(&hdata->hdmiphy_port->dev);

drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h+0−1

@@ -83,7 +83,6 @@ · 82 unmodified lines
83	#define VSIZE_OFST 20	83	#define VSIZE_OFST 20
84	#define LDI_INT_EN 0x741C	84	#define LDI_INT_EN 0x741C
85	#define FRAME_END_INT_EN_OFST 1	85	#define FRAME_END_INT_EN_OFST 1
86	#define UNDERFLOW_INT_EN_OFST 2
87	#define LDI_CTRL 0x7420	86	#define LDI_CTRL 0x7420
88	#define BPP_OFST 3	87	#define BPP_OFST 3
89	#define DATA_GATE_EN BIT(2)	88	#define DATA_GATE_EN BIT(2)

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c+0−20

 	struct clk *media_noc_clk;
 	struct clk *ade_pix_clk;
 	struct reset_control *reset;
-	struct work_struct display_reset_wq;
 	bool power_on;
 	int irq;
 	 */
 	ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
 			FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND);
-	ade_update_bits(base + LDI_INT_EN, UNDERFLOW_INT_EN_OFST, MASK(1), 1);
 }
 static bool ade_crtc_mode_fixup(struct drm_crtc *crtc,
 			MASK(1), 0);
 }
-static void drm_underflow_wq(struct work_struct *work)
-{
-	struct ade_hw_ctx *ctx = container_of(work, struct ade_hw_ctx,
-					      display_reset_wq);
-	struct drm_device *drm_dev = ctx->crtc->dev;
-	struct drm_atomic_state *state;
-	state = drm_atomic_helper_suspend(drm_dev);
-	drm_atomic_helper_resume(drm_dev, state);
-}
 static irqreturn_t ade_irq_handler(int irq, void *data)
 {
 	struct ade_hw_ctx *ctx = data;
 				MASK(1), 1);
 		drm_crtc_handle_vblank(crtc);
 	}
-	if (status & BIT(UNDERFLOW_INT_EN_OFST)) {
-		ade_update_bits(base + LDI_INT_CLR, UNDERFLOW_INT_EN_OFST,
-				MASK(1), 1);
-		DRM_ERROR("LDI underflow!");
-		schedule_work(&ctx->display_reset_wq);
-	}
 	return IRQ_HANDLED;
 }
 	if (ret)
 		return ERR_PTR(-EIO);
-	INIT_WORK(&ctx->display_reset_wq, drm_underflow_wq);
 	ctx->crtc = crtc;
 	return ctx;

drivers/gpu/drm/i915/display/intel_display_power.c+24−5

 static void icl_mbus_init(struct drm_i915_private *dev_priv)
 {
-	u32 val;
+	u32 mask, val;
-	val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
+	mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
-	      MBUS_ABOX_BT_CREDIT_POOL2(16) |
+		MBUS_ABOX_BT_CREDIT_POOL2_MASK |
-	      MBUS_ABOX_B_CREDIT(1) |
+		MBUS_ABOX_B_CREDIT_MASK |
-	      MBUS_ABOX_BW_CREDIT(1);
+		MBUS_ABOX_BW_CREDIT_MASK;
+	val = I915_READ(MBUS_ABOX_CTL);
+	val &= ~mask;
+	val |= MBUS_ABOX_BT_CREDIT_POOL1(16) |
+		MBUS_ABOX_BT_CREDIT_POOL2(16) |
+		MBUS_ABOX_B_CREDIT(1) |
+		MBUS_ABOX_BW_CREDIT(1);
 	I915_WRITE(MBUS_ABOX_CTL, val);
 }
 		I915_WRITE(BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
 		I915_WRITE(BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
 	} else {
+		u32 val;
 		I915_WRITE(BW_BUDDY1_PAGE_MASK, table[i].page_mask);
 		I915_WRITE(BW_BUDDY2_PAGE_MASK, table[i].page_mask);
+		/* Wa_22010178259:tgl */
+		val = I915_READ(BW_BUDDY1_CTL);
+		val &= ~BW_BUDDY_TLB_REQ_TIMER_MASK;
+		val |= REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8);
+		I915_WRITE(BW_BUDDY1_CTL, val);
+		val = I915_READ(BW_BUDDY2_CTL);
+		val &= ~BW_BUDDY_TLB_REQ_TIMER_MASK;
+		val |= REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8);
+		I915_WRITE(BW_BUDDY2_CTL, val);
 	}
 }

drivers/gpu/drm/i915/display/intel_psr.c+21−4

 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	if (!crtc_state->has_psr)
+	if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp)
 		return;
-	if (WARN_ON(!CAN_PSR(dev_priv)))
+	dev_priv->psr.force_mode_changed = false;
+	if (!crtc_state->has_psr)
 		return;
 	WARN_ON(dev_priv->drrs.dp);
 	if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
 		return;
+	dev_priv->psr.force_mode_changed = false;
 	mutex_lock(&dev_priv->psr.lock);
 	enable = crtc_state->has_psr && psr_global_enabled(psr->debug);
 	struct drm_crtc_state *crtc_state;
 	if (!CAN_PSR(dev_priv) || !new_state->crtc ||
-	    dev_priv->psr.initially_probed)
+	    !dev_priv->psr.force_mode_changed)
 		return;
 	intel_connector = to_intel_connector(connector);
 	crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
 						   new_state->crtc);
 	crtc_state->mode_changed = true;
-	dev_priv->psr.initially_probed = true;
+}
+void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv;
+	if (!intel_dp)
+		return;
+	dev_priv = dp_to_i915(intel_dp);
+	if (!CAN_PSR(dev_priv) || intel_dp != dev_priv->psr.dp)
+		return;
+	dev_priv->psr.force_mode_changed = true;
 }

drivers/gpu/drm/i915/display/intel_psr.h+1−0

@@ -40,5 +40,6 @@ bool intel_psr_enabled(struct intel_dp *intel_dp); · 39 unmodified lines
40	void intel_psr_atomic_check(struct drm_connector *connector,	40	void intel_psr_atomic_check(struct drm_connector *connector,
41	struct drm_connector_state *old_state,	41	struct drm_connector_state *old_state,
42	struct drm_connector_state *new_state);	42	struct drm_connector_state *new_state);
		43	void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp);
43		44
44	#endif /* __INTEL_PSR_H__ */	45	#endif /* __INTEL_PSR_H__ */

drivers/gpu/drm/i915/gem/i915_gem_object.c+1−0

@@ -225,6 +225,7 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915, · 224 unmodified lines
225		225
226	/* But keep the pointer alive for RCU-protected lookups */	226	/* But keep the pointer alive for RCU-protected lookups */
227	call_rcu(&obj->rcu, __i915_gem_free_object_rcu);	227	call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
		228	cond_resched();
228	}	229	}
229	intel_runtime_pm_put(&i915->runtime_pm, wakeref);	230	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
230	}	231	}

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c+1−1

@@ -570,7 +570,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915, · 569 unmodified lines
570		570
571	obj = i915_gem_object_create_internal(i915, size);	571	obj = i915_gem_object_create_internal(i915, size);
572	if (IS_ERR(obj))	572	if (IS_ERR(obj))
573	return PTR_ERR(obj);	573	return false;
574		574
575	mmo = mmap_offset_attach(obj, I915_MMAP_OFFSET_GTT, NULL);	575	mmo = mmap_offset_attach(obj, I915_MMAP_OFFSET_GTT, NULL);
576	i915_gem_object_put(obj);	576	i915_gem_object_put(obj);

drivers/gpu/drm/i915/gt/intel_gt_requests.c+11−3

 			fence = i915_active_fence_get(&tl->last_request);
 			if (fence) {
+				mutex_unlock(&tl->mutex);
 				timeout = dma_fence_wait_timeout(fence,
 								 interruptible,
 								 timeout);
 				dma_fence_put(fence);
+				/* Retirement is best effort */
+				if (!mutex_trylock(&tl->mutex)) {
+					active_count++;
+					goto out_active;
+				}
 			}
 		}
 		if (!retire_requests(tl) || flush_submission(gt))
 			active_count++;
+		mutex_unlock(&tl->mutex);
-		spin_lock(&timelines->lock);
+out_active:	spin_lock(&timelines->lock);
-		/* Resume iteration after dropping lock */
+		/* Resume list iteration after reacquiring spinlock */
 		list_safe_reset_next(tl, tn, link);
 		if (atomic_dec_and_test(&tl->active_count))
 			list_del(&tl->link);
-		mutex_unlock(&tl->mutex);
 		/* Defer the final release to after the spinlock */
 		if (refcount_dec_and_test(&tl->kref.refcount)) {

drivers/gpu/drm/i915/gt/intel_workarounds.c+7−12

 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
-	u32 val;
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
-	/* Wa_1604555607:tgl */
-	val = intel_uncore_read(engine->uncore, FF_MODE2);
-	val &= ~FF_MODE2_TDS_TIMER_MASK;
-	val |= FF_MODE2_TDS_TIMER_128;
 	/*
-	 * FIXME: FF_MODE2 register is not readable till TGL B0. We can
+	 * Wa_1604555607:gen12 and Wa_1608008084:gen12
-	 * enable verification of WA from the later steppings, which enables
+	 * FF_MODE2 register will return the wrong value when read. The default
-	 * the read of FF_MODE2.
+	 * value for this register is zero for all fields and there are no bit
+	 * masks. So instead of doing a RMW we should just write the TDS timer
+	 * value for Wa_1604555607.
 	 */
-	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
+	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
-	       IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
+	       FF_MODE2_TDS_TIMER_128, 0);
-			    FF_MODE2_TDS_TIMER_MASK);
 }
 static void

drivers/gpu/drm/i915/i915_drv.c+3−0

 #include "display/intel_hotplug.h"
 #include "display/intel_overlay.h"
 #include "display/intel_pipe_crc.h"
+#include "display/intel_psr.h"
 #include "display/intel_sprite.h"
 #include "display/intel_vga.h"
 	intel_init_ipc(i915);
+	intel_psr_set_force_mode_changed(i915->psr.dp);
 	return 0;
 cleanup_gem:

drivers/gpu/drm/i915/i915_drv.h+1−1

@@ -505,7 +505,7 @@ struct i915_psr { · 504 unmodified lines
505	bool dc3co_enabled;	505	bool dc3co_enabled;
506	u32 dc3co_exit_delay;	506	u32 dc3co_exit_delay;
507	struct delayed_work idle_work;	507	struct delayed_work idle_work;
508	bool initially_probed;	508	bool force_mode_changed;
509	};	509	};
510		510
511	#define QUIRK_LVDS_SSC_DISABLE (1<<1)	511	#define QUIRK_LVDS_SSC_DISABLE (1<<1)

drivers/gpu/drm/i915/i915_perf.c+41−17

 	return i915_vma_get(oa_bo->vma);
 }
-static int emit_oa_config(struct i915_perf_stream *stream,
+static struct i915_request *
-			  struct i915_oa_config *oa_config,
+emit_oa_config(struct i915_perf_stream *stream,
-			  struct intel_context *ce)
+	       struct i915_oa_config *oa_config,
+	       struct intel_context *ce)
 {
 	struct i915_request *rq;
 	struct i915_vma *vma;
 	vma = get_oa_vma(stream, oa_config);
 	if (IS_ERR(vma))
-		return PTR_ERR(vma);
+		return ERR_CAST(vma);
 	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
 	if (err)
 	err = rq->engine->emit_bb_start(rq,
 					vma->node.start, 0,
 					I915_DISPATCH_SECURE);
+	if (err)
+		goto err_add_request;
+	i915_request_get(rq);
 err_add_request:
 	i915_request_add(rq);
 err_vma_unpin:
 	i915_vma_unpin(vma);
 err_vma_put:
 	i915_vma_put(vma);
-	return err;
+	return err ? ERR_PTR(err) : rq;
 }
 static struct intel_context *oa_context(struct i915_perf_stream *stream)
 	return stream->pinned_ctx ?: stream->engine->kernel_context;
 }
-static int hsw_enable_metric_set(struct i915_perf_stream *stream)
+static struct i915_request *
+hsw_enable_metric_set(struct i915_perf_stream *stream)
 {
 	struct intel_uncore *uncore = stream->uncore;
 	return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
 }
-static int gen8_enable_metric_set(struct i915_perf_stream *stream)
+static struct i915_request *
+gen8_enable_metric_set(struct i915_perf_stream *stream)
 {
 	struct intel_uncore *uncore = stream->uncore;
 	struct i915_oa_config *oa_config = stream->oa_config;
 	 */
 	ret = lrc_configure_all_contexts(stream, oa_config);
 	if (ret)
-		return ret;
+		return ERR_PTR(ret);
 	return emit_oa_config(stream, oa_config, oa_context(stream));
 }
 			     0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
 }
-static int gen12_enable_metric_set(struct i915_perf_stream *stream)
+static struct i915_request *
+gen12_enable_metric_set(struct i915_perf_stream *stream)
 {
 	struct intel_uncore *uncore = stream->uncore;
 	struct i915_oa_config *oa_config = stream->oa_config;
 	 */
 	ret = gen12_configure_all_contexts(stream, oa_config);
 	if (ret)
-		return ret;
+		return ERR_PTR(ret);
 	/*
 	 * For Gen12, performance counters are context
 	if (stream->ctx) {
 		ret = gen12_configure_oar_context(stream, true);
 		if (ret)
-			return ret;
+			return ERR_PTR(ret);
 	}
 	return emit_oa_config(stream, oa_config, oa_context(stream));
 	.read = i915_oa_read,
 };
+static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
+{
+	struct i915_request *rq;
+	rq = stream->perf->ops.enable_metric_set(stream);
+	if (IS_ERR(rq))
+		return PTR_ERR(rq);
+	i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
+	i915_request_put(rq);
+	return 0;
+}
 /**
  * i915_oa_stream_init - validate combined props for OA stream and init
  * @stream: An i915 perf stream
 	stream->ops = &i915_oa_stream_ops;
 	perf->exclusive_stream = stream;
-	ret = perf->ops.enable_metric_set(stream);
+	ret = i915_perf_stream_enable_sync(stream);
 	if (ret) {
 		DRM_DEBUG("Unable to enable metric set\n");
 		goto err_enable;
 		return -EINVAL;
 	if (config != stream->oa_config) {
-		int err;
+		struct i915_request *rq;
 		/*
 		 * If OA is bound to a specific context, emit the
 		 * When set globally, we use a low priority kernel context,
 		 * so it will effectively take effect when idle.
 		 */
-		err = emit_oa_config(stream, config, oa_context(stream));
+		rq = emit_oa_config(stream, config, oa_context(stream));
-		if (err == 0)
+		if (!IS_ERR(rq)) {
 			config = xchg(&stream->oa_config, config);
-		else
+			i915_request_put(rq);
-			ret = err;
+		} else {
+			ret = PTR_ERR(rq);
+		}
 	}
 	i915_oa_config_put(config);

drivers/gpu/drm/i915/i915_perf_types.h+2−1

@@ -339,7 +339,8 @@ struct i915_oa_ops { · 338 unmodified lines
339	* counter reports being sampled. May apply system constraints such as	339	* counter reports being sampled. May apply system constraints such as
340	* disabling EU clock gating as required.	340	* disabling EU clock gating as required.
341	*/	341	*/
342	int (enable_metric_set)(struct i915_perf_stream stream);	342	struct i915_request *
		343	(enable_metric_set)(struct i915_perf_stream stream);
343		344
344	/**	345	/**
345	* @disable_metric_set: Remove system constraints associated with using	346	* @disable_metric_set: Remove system constraints associated with using

drivers/gpu/drm/i915/i915_reg.h+1−0

@@ -7757,6 +7757,7 @@ enum { · 7756 unmodified lines
7757	#define BW_BUDDY1_CTL _MMIO(0x45140)	7757	#define BW_BUDDY1_CTL _MMIO(0x45140)
7758	#define BW_BUDDY2_CTL _MMIO(0x45150)	7758	#define BW_BUDDY2_CTL _MMIO(0x45150)
7759	#define BW_BUDDY_DISABLE REG_BIT(31)	7759	#define BW_BUDDY_DISABLE REG_BIT(31)
		7760	#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
7760		7761
7761	#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144)	7762	#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144)
7762	#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154)	7763	#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154)

drivers/gpu/drm/i915/i915_request.c+28−13

@@ -275,7 +275,7 @@ bool i915_request_retire(struct i915_request *rq) · 274 unmodified lines
275	spin_unlock_irq(&rq->lock);	275	spin_unlock_irq(&rq->lock);
276		276
277	remove_from_client(rq);	277	remove_from_client(rq);
278	list_del(&rq->link);	278	list_del_rcu(&rq->link);
279		279
280	intel_context_exit(rq->context);	280	intel_context_exit(rq->context);
281	intel_context_unpin(rq->context);	281	intel_context_unpin(rq->context);
@@ -721,6 +721,8 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp) · 439 unmodified lines
721	rq->infix = rq->ring->emit; /* end of header; start of user payload */	721	rq->infix = rq->ring->emit; /* end of header; start of user payload */
722		722
723	intel_context_mark_active(ce);	723	intel_context_mark_active(ce);
		724	list_add_tail_rcu(&rq->link, &tl->requests);
		725
724	return rq;	726	return rq;
725		727
726	err_unwind:	728	err_unwind:
@@ -777,13 +779,23 @@ i915_request_await_start(struct i915_request rq, struct i915_request signal) · 50 unmodified lines
777	GEM_BUG_ON(i915_request_timeline(rq) ==	779	GEM_BUG_ON(i915_request_timeline(rq) ==
778	rcu_access_pointer(signal->timeline));	780	rcu_access_pointer(signal->timeline));
779		781
		782	if (i915_request_started(signal))
		783	return 0;
		784
780	fence = NULL;	785	fence = NULL;
781	rcu_read_lock();	786	rcu_read_lock();
782	spin_lock_irq(&signal->lock);	787	spin_lock_irq(&signal->lock);
783	if (!i915_request_started(signal) &&	788	do {
784	!list_is_first(&signal->link,	789	struct list_head *pos = READ_ONCE(signal->link.prev);
785	&rcu_dereference(signal->timeline)->requests)) {	790	struct i915_request *prev;
786	struct i915_request *prev = list_prev_entry(signal, link);	791
		792	/* Confirm signal has not been retired, the link is valid */
		793	if (unlikely(i915_request_started(signal)))
		794	break;
		795
		796	/* Is signal the earliest request on its timeline? */
		797	if (pos == &rcu_dereference(signal->timeline)->requests)
		798	break;
787		799
788	/*	800	/*
789	* Peek at the request before us in the timeline. That	801	* Peek at the request before us in the timeline. That
@@ -791,13 +803,18 @@ i915_request_await_start(struct i915_request rq, struct i915_request signal) · 1 unmodified line
791	* after acquiring a reference to it, confirm that it is	803	* after acquiring a reference to it, confirm that it is
792	* still part of the signaler's timeline.	804	* still part of the signaler's timeline.
793	*/	805	*/
794	if (i915_request_get_rcu(prev)) {	806	prev = list_entry(pos, typeof(*prev), link);
795	if (list_next_entry(prev, link) == signal)	807	if (!i915_request_get_rcu(prev))
796	fence = &prev->fence;	808	break;
797	else	809
798	i915_request_put(prev);	810	/* After the strong barrier, confirm prev is still attached */
		811	if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
		812	i915_request_put(prev);
		813	break;
799	}	814	}
800	}	815
		816	fence = &prev->fence;
		817	} while (0);
801	spin_unlock_irq(&signal->lock);	818	spin_unlock_irq(&signal->lock);
802	rcu_read_unlock();	819	rcu_read_unlock();
803	if (!fence)	820	if (!fence)
@@ -1242,8 +1259,6 @@ __i915_request_add_to_timeline(struct i915_request *rq) · 438 unmodified lines
1242	0);	1259	0);
1243	}	1260	}
1244		1261
1245	list_add_tail(&rq->link, &timeline->requests);
1246
1247	/*	1262	/*
1248	* Make sure that no request gazumped us - if it was allocated after	1263	* Make sure that no request gazumped us - if it was allocated after
1249	* our i915_request_alloc() and called __i915_request_add() before	1264	* our i915_request_alloc() and called __i915_request_add() before

drivers/gpu/drm/mediatek/mtk_drm_crtc.c+20−10

 	}
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 	if (mtk_crtc->cmdq_client) {
+		mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
 		cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
 		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
 static int mtk_drm_crtc_init(struct drm_device *drm,
 			     struct mtk_drm_crtc *mtk_crtc,
-			     struct drm_plane *primary,
+			     unsigned int pipe)
-			     struct drm_plane *cursor, unsigned int pipe)
 {
-	int ret;
+	struct drm_plane *primary = NULL;
+	struct drm_plane *cursor = NULL;
+	int i, ret;
+	for (i = 0; i < mtk_crtc->layer_nr; i++) {
+		if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
+			primary = &mtk_crtc->planes[i];
+		else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
+			cursor = &mtk_crtc->planes[i];
+	}
 	ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
 					&mtk_crtc_funcs, NULL);
 }
 static inline
-enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx)
+enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
+					    unsigned int num_planes)
 {
 	if (plane_idx == 0)
 		return DRM_PLANE_TYPE_PRIMARY;
-	else if (plane_idx == 1)
+	else if (plane_idx == (num_planes - 1))
 		return DRM_PLANE_TYPE_CURSOR;
 	else
 		return DRM_PLANE_TYPE_OVERLAY;
 		ret = mtk_plane_init(drm_dev,
 				&mtk_crtc->planes[mtk_crtc->layer_nr],
 				BIT(pipe),
-				mtk_drm_crtc_plane_type(mtk_crtc->layer_nr),
+				mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
+							num_planes),
 				mtk_ddp_comp_supported_rotations(comp));
 		if (ret)
 			return ret;
 			return ret;
 	}
-	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
+	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
-				mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] :
-				NULL, pipe);
 	if (ret < 0)
 		return ret;
 			drm_crtc_index(&mtk_crtc->base));
 		mtk_crtc->cmdq_client = NULL;
 	}
-	ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
+	ret = of_property_read_u32_index(priv->mutex_node,
+					 "mediatek,gce-events",
 					 drm_crtc_index(&mtk_crtc->base),
 					 &mtk_crtc->cmdq_event);
 	if (ret)

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c+1−0

@@ -471,6 +471,7 @@ int mtk_ddp_comp_init(struct device dev, struct device_node node, · 470 unmodified lines
471	/* Only DMA capable components need the LARB property */	471	/* Only DMA capable components need the LARB property */
472	comp->larb_dev = NULL;	472	comp->larb_dev = NULL;
473	if (type != MTK_DISP_OVL &&	473	if (type != MTK_DISP_OVL &&
		474	type != MTK_DISP_OVL_2L &&
474	type != MTK_DISP_RDMA &&	475	type != MTK_DISP_RDMA &&
475	type != MTK_DISP_WDMA)	476	type != MTK_DISP_WDMA)
476	return 0;	477	return 0;

drivers/gpu/drm/mediatek/mtk_drm_plane.c+7−0

 					struct drm_plane_state *state)
 {
 	struct drm_crtc_state *crtc_state;
+	int ret;
 	if (plane != state->crtc->cursor)
 		return -EINVAL;
 	if (!plane->state->fb)
 		return -EINVAL;
+	ret = mtk_drm_crtc_plane_check(state->crtc, plane,
+				       to_mtk_plane_state(state));
+	if (ret)
+		return ret;
 	if (state->state)
 		crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 								state->crtc);
 	plane->state->src_y = new_state->src_y;
 	plane->state->src_h = new_state->src_h;
 	plane->state->src_w = new_state->src_w;
+	swap(plane->state->fb, new_state->fb);
 	state->pending.async_dirty = true;
 	mtk_drm_crtc_async_update(new_state->crtc, plane, new_state);

drivers/gpu/drm/panfrost/panfrost_mmu.c+19−25

@@ -601,33 +601,27 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) · 600 unmodified lines
601	source_id = (fault_status >> 16);	601	source_id = (fault_status >> 16);
602		602
603	/* Page fault only */	603	/* Page fault only */
604	if ((status & mask) == BIT(i)) {	604	ret = -1;
605	WARN_ON(exception_type < 0xC1 \|\| exception_type > 0xC4);	605	if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0)
606
607	ret = panfrost_mmu_map_fault_addr(pfdev, i, addr);	606	ret = panfrost_mmu_map_fault_addr(pfdev, i, addr);
608	if (!ret) {
609	mmu_write(pfdev, MMU_INT_CLEAR, BIT(i));
610	status &= ~mask;
611	continue;
612	}
613	}
614		607
615	/* terminal fault, print info about the fault */	608	if (ret)
616	dev_err(pfdev->dev,	609	/* terminal fault, print info about the fault */
617	"Unhandled Page fault in AS%d at VA 0x%016llX\n"	610	dev_err(pfdev->dev,
618	"Reason: %s\n"	611	"Unhandled Page fault in AS%d at VA 0x%016llX\n"
619	"raw fault status: 0x%X\n"	612	"Reason: %s\n"
620	"decoded fault status: %s\n"	613	"raw fault status: 0x%X\n"
621	"exception type 0x%X: %s\n"	614	"decoded fault status: %s\n"
622	"access type 0x%X: %s\n"	615	"exception type 0x%X: %s\n"
623	"source id 0x%X\n",	616	"access type 0x%X: %s\n"
624	i, addr,	617	"source id 0x%X\n",
625	"TODO",	618	i, addr,
626	fault_status,	619	"TODO",
627	(fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),	620	fault_status,
628	exception_type, panfrost_exception_name(pfdev, exception_type),	621	(fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),
629	access_type, access_type_name(pfdev, fault_status),	622	exception_type, panfrost_exception_name(pfdev, exception_type),
630	source_id);	623	access_type, access_type_name(pfdev, fault_status),
		624	source_id);
631		625
632	mmu_write(pfdev, MMU_INT_CLEAR, mask);	626	mmu_write(pfdev, MMU_INT_CLEAR, mask);
633		627

drivers/gpu/drm/sun4i/sun8i_mixer.c+92−12

@@ -106,48 +106,128 @@ static const struct de2_fmt_info de2_formats[] = { · 105 unmodified lines
106	.rgb = true,	106	.rgb = true,
107	.csc = SUN8I_CSC_MODE_OFF,	107	.csc = SUN8I_CSC_MODE_OFF,
108	},	108	},
		109	{
		110	/* for DE2 VI layer which ignores alpha */
		111	.drm_fmt = DRM_FORMAT_XRGB4444,
		112	.de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
		113	.rgb = true,
		114	.csc = SUN8I_CSC_MODE_OFF,
		115	},
109	{	116	{
110	.drm_fmt = DRM_FORMAT_ABGR4444,	117	.drm_fmt = DRM_FORMAT_ABGR4444,
111	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,	118	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
112	.rgb = true,	119	.rgb = true,
113	.csc = SUN8I_CSC_MODE_OFF,	120	.csc = SUN8I_CSC_MODE_OFF,
114	},	121	},
		122	{
		123	/* for DE2 VI layer which ignores alpha */
		124	.drm_fmt = DRM_FORMAT_XBGR4444,
		125	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
		126	.rgb = true,
		127	.csc = SUN8I_CSC_MODE_OFF,
		128	},
115	{	129	{
116	.drm_fmt = DRM_FORMAT_RGBA4444,	130	.drm_fmt = DRM_FORMAT_RGBA4444,
117	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,	131	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
118	.rgb = true,	132	.rgb = true,
119	.csc = SUN8I_CSC_MODE_OFF,	133	.csc = SUN8I_CSC_MODE_OFF,
120	},	134	},
		135	{
		136	/* for DE2 VI layer which ignores alpha */
		137	.drm_fmt = DRM_FORMAT_RGBX4444,
		138	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
		139	.rgb = true,
		140	.csc = SUN8I_CSC_MODE_OFF,
		141	},
121	{	142	{
122	.drm_fmt = DRM_FORMAT_BGRA4444,	143	.drm_fmt = DRM_FORMAT_BGRA4444,
123	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,	144	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
124	.rgb = true,	145	.rgb = true,
125	.csc = SUN8I_CSC_MODE_OFF,	146	.csc = SUN8I_CSC_MODE_OFF,
126	},	147	},
		148	{
		149	/* for DE2 VI layer which ignores alpha */
		150	.drm_fmt = DRM_FORMAT_BGRX4444,
		151	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
		152	.rgb = true,
		153	.csc = SUN8I_CSC_MODE_OFF,
		154	},
127	{	155	{
128	.drm_fmt = DRM_FORMAT_ARGB1555,	156	.drm_fmt = DRM_FORMAT_ARGB1555,
129	.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,	157	.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
130	.rgb = true,	158	.rgb = true,
131	.csc = SUN8I_CSC_MODE_OFF,	159	.csc = SUN8I_CSC_MODE_OFF,
132	},	160	},
		161	{
		162	/* for DE2 VI layer which ignores alpha */
		163	.drm_fmt = DRM_FORMAT_XRGB1555,
		164	.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
		165	.rgb = true,
		166	.csc = SUN8I_CSC_MODE_OFF,
		167	},
133	{	168	{
134	.drm_fmt = DRM_FORMAT_ABGR1555,	169	.drm_fmt = DRM_FORMAT_ABGR1555,
135	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,	170	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
136	.rgb = true,	171	.rgb = true,
137	.csc = SUN8I_CSC_MODE_OFF,	172	.csc = SUN8I_CSC_MODE_OFF,
138	},	173	},
		174	{
		175	/* for DE2 VI layer which ignores alpha */
		176	.drm_fmt = DRM_FORMAT_XBGR1555,
		177	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
		178	.rgb = true,
		179	.csc = SUN8I_CSC_MODE_OFF,
		180	},
139	{	181	{
140	.drm_fmt = DRM_FORMAT_RGBA5551,	182	.drm_fmt = DRM_FORMAT_RGBA5551,
141	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,	183	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
142	.rgb = true,	184	.rgb = true,
143	.csc = SUN8I_CSC_MODE_OFF,	185	.csc = SUN8I_CSC_MODE_OFF,
144	},	186	},
		187	{
		188	/* for DE2 VI layer which ignores alpha */
		189	.drm_fmt = DRM_FORMAT_RGBX5551,
		190	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
		191	.rgb = true,
		192	.csc = SUN8I_CSC_MODE_OFF,
		193	},
145	{	194	{
146	.drm_fmt = DRM_FORMAT_BGRA5551,	195	.drm_fmt = DRM_FORMAT_BGRA5551,
147	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,	196	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
148	.rgb = true,	197	.rgb = true,
149	.csc = SUN8I_CSC_MODE_OFF,	198	.csc = SUN8I_CSC_MODE_OFF,
150	},	199	},
		200	{
		201	/* for DE2 VI layer which ignores alpha */
		202	.drm_fmt = DRM_FORMAT_BGRX5551,
		203	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
		204	.rgb = true,
		205	.csc = SUN8I_CSC_MODE_OFF,
		206	},
		207	{
		208	.drm_fmt = DRM_FORMAT_ARGB2101010,
		209	.de2_fmt = SUN8I_MIXER_FBFMT_ARGB2101010,
		210	.rgb = true,
		211	.csc = SUN8I_CSC_MODE_OFF,
		212	},
		213	{
		214	.drm_fmt = DRM_FORMAT_ABGR2101010,
		215	.de2_fmt = SUN8I_MIXER_FBFMT_ABGR2101010,
		216	.rgb = true,
		217	.csc = SUN8I_CSC_MODE_OFF,
		218	},
		219	{
		220	.drm_fmt = DRM_FORMAT_RGBA1010102,
		221	.de2_fmt = SUN8I_MIXER_FBFMT_RGBA1010102,
		222	.rgb = true,
		223	.csc = SUN8I_CSC_MODE_OFF,
		224	},
		225	{
		226	.drm_fmt = DRM_FORMAT_BGRA1010102,
		227	.de2_fmt = SUN8I_MIXER_FBFMT_BGRA1010102,
		228	.rgb = true,
		229	.csc = SUN8I_CSC_MODE_OFF,
		230	},
151	{	231	{
152	.drm_fmt = DRM_FORMAT_UYVY,	232	.drm_fmt = DRM_FORMAT_UYVY,
153	.de2_fmt = SUN8I_MIXER_FBFMT_UYVY,	233	.de2_fmt = SUN8I_MIXER_FBFMT_UYVY,
@@ -196,12 +276,6 @@ static const struct de2_fmt_info de2_formats[] = { · 42 unmodified lines
196	.rgb = false,	276	.rgb = false,
197	.csc = SUN8I_CSC_MODE_YUV2RGB,	277	.csc = SUN8I_CSC_MODE_YUV2RGB,
198	},	278	},
199	{
200	.drm_fmt = DRM_FORMAT_YUV444,
201	.de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
202	.rgb = true,
203	.csc = SUN8I_CSC_MODE_YUV2RGB,
204	},
205	{	279	{
206	.drm_fmt = DRM_FORMAT_YUV422,	280	.drm_fmt = DRM_FORMAT_YUV422,
207	.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,	281	.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
@@ -220,12 +294,6 @@ static const struct de2_fmt_info de2_formats[] = { · 12 unmodified lines
220	.rgb = false,	294	.rgb = false,
221	.csc = SUN8I_CSC_MODE_YUV2RGB,	295	.csc = SUN8I_CSC_MODE_YUV2RGB,
222	},	296	},
223	{
224	.drm_fmt = DRM_FORMAT_YVU444,
225	.de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
226	.rgb = true,
227	.csc = SUN8I_CSC_MODE_YVU2RGB,
228	},
229	{	297	{
230	.drm_fmt = DRM_FORMAT_YVU422,	298	.drm_fmt = DRM_FORMAT_YVU422,
231	.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,	299	.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
@@ -244,6 +312,18 @@ static const struct de2_fmt_info de2_formats[] = { · 12 unmodified lines
244	.rgb = false,	312	.rgb = false,
245	.csc = SUN8I_CSC_MODE_YVU2RGB,	313	.csc = SUN8I_CSC_MODE_YVU2RGB,
246	},	314	},
		315	{
		316	.drm_fmt = DRM_FORMAT_P010,
		317	.de2_fmt = SUN8I_MIXER_FBFMT_P010_YUV,
		318	.rgb = false,
		319	.csc = SUN8I_CSC_MODE_YUV2RGB,
		320	},
		321	{
		322	.drm_fmt = DRM_FORMAT_P210,
		323	.de2_fmt = SUN8I_MIXER_FBFMT_P210_YUV,
		324	.rgb = false,
		325	.csc = SUN8I_CSC_MODE_YUV2RGB,
		326	},
247	};	327	};
248		328
249	const struct de2_fmt_info *sun8i_mixer_format_info(u32 format)	329	const struct de2_fmt_info *sun8i_mixer_format_info(u32 format)

drivers/gpu/drm/sun4i/sun8i_mixer.h+11−0

 #define SUN8I_MIXER_FBFMT_ABGR1555	17
 #define SUN8I_MIXER_FBFMT_RGBA5551	18
 #define SUN8I_MIXER_FBFMT_BGRA5551	19
+#define SUN8I_MIXER_FBFMT_ARGB2101010	20
+#define SUN8I_MIXER_FBFMT_ABGR2101010	21
+#define SUN8I_MIXER_FBFMT_RGBA1010102	22
+#define SUN8I_MIXER_FBFMT_BGRA1010102	23
 #define SUN8I_MIXER_FBFMT_YUYV		0
 #define SUN8I_MIXER_FBFMT_UYVY		1
 /* format 12 is semi-planar YUV411 UVUV */
 /* format 13 is semi-planar YUV411 VUVU */
 #define SUN8I_MIXER_FBFMT_YUV411	14
+/* format 15 doesn't exist */
+/* format 16 is P010 YVU */
+#define SUN8I_MIXER_FBFMT_P010_YUV	17
+/* format 18 is P210 YVU */
+#define SUN8I_MIXER_FBFMT_P210_YUV	19
+/* format 20 is packed YVU444 10-bit */
+/* format 21 is packed YUV444 10-bit */
 /*
  * Sub-engines listed bellow are unused for now. The EN registers are here only

drivers/gpu/drm/sun4i/sun8i_vi_layer.c+58−8

 };
 /*
- * While all RGB formats are supported, VI planes don't support
+ * While DE2 VI layer supports same RGB formats as UI layer, alpha
- * alpha blending, so there is no point having formats with alpha
+ * channel is ignored. This structure lists all unique variants
- * channel if their opaque analog exist.
+ * where alpha channel is replaced with "don't care" (X) channel.
  */
 static const u32 sun8i_vi_layer_formats[] = {
+	DRM_FORMAT_BGR565,
+	DRM_FORMAT_BGR888,
+	DRM_FORMAT_BGRX4444,
+	DRM_FORMAT_BGRX5551,
+	DRM_FORMAT_BGRX8888,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_RGB888,
+	DRM_FORMAT_RGBX4444,
+	DRM_FORMAT_RGBX5551,
+	DRM_FORMAT_RGBX8888,
+	DRM_FORMAT_XBGR1555,
+	DRM_FORMAT_XBGR4444,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB1555,
+	DRM_FORMAT_XRGB4444,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_NV16,
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_NV21,
+	DRM_FORMAT_NV61,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_YUV411,
+	DRM_FORMAT_YUV420,
+	DRM_FORMAT_YUV422,
+	DRM_FORMAT_YVU411,
+	DRM_FORMAT_YVU420,
+	DRM_FORMAT_YVU422,
+};
+static const u32 sun8i_vi_layer_de3_formats[] = {
 	DRM_FORMAT_ABGR1555,
+	DRM_FORMAT_ABGR2101010,
 	DRM_FORMAT_ABGR4444,
+	DRM_FORMAT_ABGR8888,
 	DRM_FORMAT_ARGB1555,
+	DRM_FORMAT_ARGB2101010,
 	DRM_FORMAT_ARGB4444,
+	DRM_FORMAT_ARGB8888,
 	DRM_FORMAT_BGR565,
 	DRM_FORMAT_BGR888,
+	DRM_FORMAT_BGRA1010102,
 	DRM_FORMAT_BGRA5551,
 	DRM_FORMAT_BGRA4444,
+	DRM_FORMAT_BGRA8888,
 	DRM_FORMAT_BGRX8888,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_RGB888,
+	DRM_FORMAT_RGBA1010102,
 	DRM_FORMAT_RGBA4444,
 	DRM_FORMAT_RGBA5551,
+	DRM_FORMAT_RGBA8888,
 	DRM_FORMAT_RGBX8888,
 	DRM_FORMAT_XBGR8888,
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_NV12,
 	DRM_FORMAT_NV21,
 	DRM_FORMAT_NV61,
+	DRM_FORMAT_P010,
+	DRM_FORMAT_P210,
 	DRM_FORMAT_UYVY,
 	DRM_FORMAT_VYUY,
 	DRM_FORMAT_YUYV,
 	DRM_FORMAT_YUV411,
 	DRM_FORMAT_YUV420,
 	DRM_FORMAT_YUV422,
-	DRM_FORMAT_YUV444,
 	DRM_FORMAT_YVU411,
 	DRM_FORMAT_YVU420,
 	DRM_FORMAT_YVU422,
-	DRM_FORMAT_YVU444,
 };
 struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
 					       int index)
 {
 	u32 supported_encodings, supported_ranges;
+	unsigned int plane_cnt, format_count;
 	struct sun8i_vi_layer *layer;
-	unsigned int plane_cnt;
+	const u32 *formats;
 	int ret;
 	layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
 	if (!layer)
 		return ERR_PTR(-ENOMEM);
+	if (mixer->cfg->is_de3) {
+		formats = sun8i_vi_layer_de3_formats;
+		format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
+	} else {
+		formats = sun8i_vi_layer_formats;
+		format_count = ARRAY_SIZE(sun8i_vi_layer_formats);
+	}
 	/* possible crtcs are set later */
 	ret = drm_universal_plane_init(drm, &layer->plane, 0,
 				       &sun8i_vi_layer_funcs,
-				       sun8i_vi_layer_formats,
+				       formats, format_count,
-				       ARRAY_SIZE(sun8i_vi_layer_formats),
 				       NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
 	if (ret) {
 		dev_err(drm->dev, "Couldn't initialize layer\n");

drivers/gpu/drm/ttm/ttm_bo_util.c+1−0

@@ -515,6 +515,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, · 514 unmodified lines
515	fbo->base.base.resv = &fbo->base.base._resv;	515	fbo->base.base.resv = &fbo->base.base._resv;
516		516
517	dma_resv_init(&fbo->base.base._resv);	517	dma_resv_init(&fbo->base.base._resv);
		518	fbo->base.base.dev = NULL;
518	ret = dma_resv_trylock(&fbo->base.base._resv);	519	ret = dma_resv_trylock(&fbo->base.base._resv);
519	WARN_ON(!ret);	520	WARN_ON(!ret);
520		521

drivers/gpu/drm/virtio/virtgpu_object.c+3−2

 		 * "f91a9dd35715 Fix unlinking resources from hash
 		 * table." (Feb 2019) fixes the bug.
 		 */
-		static int handle;
+		static atomic_t seqno = ATOMIC_INIT(0);
-		handle++;
+		int handle = atomic_inc_return(&seqno);
 		*resid = handle + 1;
 	} else {
 		int handle = ida_alloc(&vgdev->resource_ida, GFP_KERNEL);
 		return NULL;
 	bo->base.base.funcs = &virtio_gpu_gem_funcs;
+	bo->base.map_cached = true;
 	return &bo->base.base;
 }

drivers/hid/hid-hyperv.c+2−4

 		goto cleanup;
 	/* The pointer is not NULL when we resume from hibernation */
-	if (input_device->hid_desc != NULL)
+	kfree(input_device->hid_desc);
-		kfree(input_device->hid_desc);
 	input_device->hid_desc = kmemdup(desc, desc->bLength, GFP_ATOMIC);
 	if (!input_device->hid_desc)
 	}
 	/* The pointer is not NULL when we resume from hibernation */
-	if (input_device->report_desc != NULL)
+	kfree(input_device->report_desc);
-		kfree(input_device->report_desc);
 	input_device->report_desc = kzalloc(input_device->report_desc_size,
 					  GFP_ATOMIC);

drivers/hwmon/adt7462.c+1−1

@@ -413,7 +413,7 @@ static int ADT7462_REG_VOLT(struct adt7462_data *data, int which) · 412 unmodified lines
413	return 0x95;	413	return 0x95;
414	break;	414	break;
415	}	415	}
416	return -ENODEV;	416	return 0;
417	}	417	}
418		418
419	/* Provide labels for sysfs */	419	/* Provide labels for sysfs */

drivers/hwmon/pmbus/xdpe12284.c+54−0

@@ -18,6 +18,59 @@ · 17 unmodified lines
18	#define XDPE122_AMD_625MV 0x10 /* AMD mode 6.25mV */	18	#define XDPE122_AMD_625MV 0x10 /* AMD mode 6.25mV */
19	#define XDPE122_PAGE_NUM 2	19	#define XDPE122_PAGE_NUM 2
20		20
		21	static int xdpe122_read_word_data(struct i2c_client *client, int page, int reg)
		22	{
		23	const struct pmbus_driver_info *info = pmbus_get_driver_info(client);
		24	long val;
		25	s16 exponent;
		26	s32 mantissa;
		27	int ret;
		28
		29	switch (reg) {
		30	case PMBUS_VOUT_OV_FAULT_LIMIT:
		31	case PMBUS_VOUT_UV_FAULT_LIMIT:
		32	ret = pmbus_read_word_data(client, page, reg);
		33	if (ret < 0)
		34	return ret;
		35
		36	/* Convert register value to LINEAR11 data. */
		37	exponent = ((s16)ret) >> 11;
		38	mantissa = ((s16)((ret & GENMASK(10, 0)) << 5)) >> 5;
		39	val = mantissa * 1000L;
		40	if (exponent >= 0)
		41	val <<= exponent;
		42	else
		43	val >>= -exponent;
		44
		45	/* Convert data to VID register. */
		46	switch (info->vrm_version[page]) {
		47	case vr13:
		48	if (val >= 500)
		49	return 1 + DIV_ROUND_CLOSEST(val - 500, 10);
		50	return 0;
		51	case vr12:
		52	if (val >= 250)
		53	return 1 + DIV_ROUND_CLOSEST(val - 250, 5);
		54	return 0;
		55	case imvp9:
		56	if (val >= 200)
		57	return 1 + DIV_ROUND_CLOSEST(val - 200, 10);
		58	return 0;
		59	case amd625mv:
		60	if (val >= 200 && val <= 1550)
		61	return DIV_ROUND_CLOSEST((1550 - val) * 100,
		62	625);
		63	return 0;
		64	default:
		65	return -EINVAL;
		66	}
		67	default:
		68	return -ENODATA;
		69	}
		70
		71	return 0;
		72	}
		73
21	static int xdpe122_identify(struct i2c_client *client,	74	static int xdpe122_identify(struct i2c_client *client,
22	struct pmbus_driver_info *info)	75	struct pmbus_driver_info *info)
23	{	76	{
@@ -70,6 +123,7 @@ static struct pmbus_driver_info xdpe122_info = { · 46 unmodified lines
70	PMBUS_HAVE_TEMP \| PMBUS_HAVE_STATUS_TEMP \|	123	PMBUS_HAVE_TEMP \| PMBUS_HAVE_STATUS_TEMP \|
71	PMBUS_HAVE_POUT \| PMBUS_HAVE_PIN \| PMBUS_HAVE_STATUS_INPUT,	124	PMBUS_HAVE_POUT \| PMBUS_HAVE_PIN \| PMBUS_HAVE_STATUS_INPUT,
72	.identify = xdpe122_identify,	125	.identify = xdpe122_identify,
		126	.read_word_data = xdpe122_read_word_data,
73	};	127	};
74		128
75	static int xdpe122_probe(struct i2c_client *client,	129	static int xdpe122_probe(struct i2c_client *client,

drivers/infiniband/core/cm.c+1−0

@@ -1191,6 +1191,7 @@ struct ib_cm_id ib_cm_insert_listen(struct ib_device device, · 1190 unmodified lines
1191	/* Sharing an ib_cm_id with different handlers is not	1191	/* Sharing an ib_cm_id with different handlers is not
1192	* supported */	1192	* supported */
1193	spin_unlock_irqrestore(&cm.lock, flags);	1193	spin_unlock_irqrestore(&cm.lock, flags);
		1194	ib_destroy_cm_id(cm_id);
1194	return ERR_PTR(-EINVAL);	1195	return ERR_PTR(-EINVAL);
1195	}	1196	}
1196	refcount_inc(&cm_id_priv->refcount);	1197	refcount_inc(&cm_id_priv->refcount);

drivers/infiniband/core/cma.c+11−4

 	int ret;
 	id_priv = container_of(id, struct rdma_id_private, id);
+	memcpy(cma_dst_addr(id_priv), dst_addr, rdma_addr_size(dst_addr));
 	if (id_priv->state == RDMA_CM_IDLE) {
 		ret = cma_bind_addr(id, src_addr, dst_addr);
-		if (ret)
+		if (ret) {
+			memset(cma_dst_addr(id_priv), 0,
+			       rdma_addr_size(dst_addr));
 			return ret;
+		}
 	}
-	if (cma_family(id_priv) != dst_addr->sa_family)
+	if (cma_family(id_priv) != dst_addr->sa_family) {
+		memset(cma_dst_addr(id_priv), 0, rdma_addr_size(dst_addr));
 		return -EINVAL;
+	}
-	if (!cma_comp_exch(id_priv, RDMA_CM_ADDR_BOUND, RDMA_CM_ADDR_QUERY))
+	if (!cma_comp_exch(id_priv, RDMA_CM_ADDR_BOUND, RDMA_CM_ADDR_QUERY)) {
+		memset(cma_dst_addr(id_priv), 0, rdma_addr_size(dst_addr));
 		return -EINVAL;
+	}
-	memcpy(cma_dst_addr(id_priv), dst_addr, rdma_addr_size(dst_addr));
 	if (cma_any_addr(dst_addr)) {
 		ret = cma_resolve_loopback(id_priv);
 	} else {

drivers/infiniband/core/core_priv.h+14−0

@@ -338,6 +338,20 @@ static inline struct ib_qp _ib_create_qp(struct ib_device dev, · 337 unmodified lines
338	qp->pd = pd;	338	qp->pd = pd;
339	qp->uobject = uobj;	339	qp->uobject = uobj;
340	qp->real_qp = qp;	340	qp->real_qp = qp;
		341
		342	qp->qp_type = attr->qp_type;
		343	qp->rwq_ind_tbl = attr->rwq_ind_tbl;
		344	qp->send_cq = attr->send_cq;
		345	qp->recv_cq = attr->recv_cq;
		346	qp->srq = attr->srq;
		347	qp->rwq_ind_tbl = attr->rwq_ind_tbl;
		348	qp->event_handler = attr->event_handler;
		349
		350	atomic_set(&qp->usecnt, 0);
		351	spin_lock_init(&qp->mr_lock);
		352	INIT_LIST_HEAD(&qp->rdma_mrs);
		353	INIT_LIST_HEAD(&qp->sig_mrs);
		354
341	/*	355	/*
342	* We don't track XRC QPs for now, because they don't have PD	356	* We don't track XRC QPs for now, because they don't have PD
343	* and more importantly they are created internaly by driver,	357	* and more importantly they are created internaly by driver,

drivers/infiniband/core/iwcm.c+3−1

 {
 	struct list_head *e, *tmp;
-	list_for_each_safe(e, tmp, &cm_id_priv->work_free_list)
+	list_for_each_safe(e, tmp, &cm_id_priv->work_free_list) {
+		list_del(e);
 		kfree(list_entry(e, struct iwcm_work, free_list));
+	}
 }
 static int alloc_work_entries(struct iwcm_id_private *cm_id_priv, int count)

drivers/infiniband/core/nldev.c+2−0

 		if (ret)
 			goto err_msg;
 	} else {
+		if (!tb[RDMA_NLDEV_ATTR_RES_LQPN])
+			goto err_msg;
 		qpn = nla_get_u32(tb[RDMA_NLDEV_ATTR_RES_LQPN]);
 		if (tb[RDMA_NLDEV_ATTR_STAT_COUNTER_ID]) {
 			cntn = nla_get_u32(tb[RDMA_NLDEV_ATTR_STAT_COUNTER_ID]);

drivers/infiniband/core/rw.c+20−11

 	return 1;
 }
+static void rdma_rw_unmap_sg(struct ib_device *dev, struct scatterlist *sg,
+			     u32 sg_cnt, enum dma_data_direction dir)
+{
+	if (is_pci_p2pdma_page(sg_page(sg)))
+		pci_p2pdma_unmap_sg(dev->dma_device, sg, sg_cnt, dir);
+	else
+		ib_dma_unmap_sg(dev, sg, sg_cnt, dir);
+}
+static int rdma_rw_map_sg(struct ib_device *dev, struct scatterlist *sg,
+			  u32 sg_cnt, enum dma_data_direction dir)
+{
+	if (is_pci_p2pdma_page(sg_page(sg)))
+		return pci_p2pdma_map_sg(dev->dma_device, sg, sg_cnt, dir);
+	return ib_dma_map_sg(dev, sg, sg_cnt, dir);
+}
 /**
  * rdma_rw_ctx_init - initialize a RDMA READ/WRITE context
  * @ctx:	context to initialize
 	struct ib_device *dev = qp->pd->device;
 	int ret;
-	if (is_pci_p2pdma_page(sg_page(sg)))
+	ret = rdma_rw_map_sg(dev, sg, sg_cnt, dir);
-		ret = pci_p2pdma_map_sg(dev->dma_device, sg, sg_cnt, dir);
-	else
-		ret = ib_dma_map_sg(dev, sg, sg_cnt, dir);
 	if (!ret)
 		return -ENOMEM;
 	sg_cnt = ret;
 	return ret;
 out_unmap_sg:
-	ib_dma_unmap_sg(dev, sg, sg_cnt, dir);
+	rdma_rw_unmap_sg(dev, sg, sg_cnt, dir);
 	return ret;
 }
 EXPORT_SYMBOL(rdma_rw_ctx_init);
 		break;
 	}
-	if (is_pci_p2pdma_page(sg_page(sg)))
+	rdma_rw_unmap_sg(qp->pd->device, sg, sg_cnt, dir);
-		pci_p2pdma_unmap_sg(qp->pd->device->dma_device, sg,
-				    sg_cnt, dir);
-	else
-		ib_dma_unmap_sg(qp->pd->device, sg, sg_cnt, dir);
 }
 EXPORT_SYMBOL(rdma_rw_ctx_destroy);

drivers/infiniband/core/security.c+9−5

 		return NULL;
 	if (qp_attr_mask & IB_QP_PORT)
-		new_pps->main.port_num =
+		new_pps->main.port_num = qp_attr->port_num;
-			(qp_pps) ? qp_pps->main.port_num : qp_attr->port_num;
+	else if (qp_pps)
+		new_pps->main.port_num = qp_pps->main.port_num;
 	if (qp_attr_mask & IB_QP_PKEY_INDEX)
-		new_pps->main.pkey_index = (qp_pps) ? qp_pps->main.pkey_index :
+		new_pps->main.pkey_index = qp_attr->pkey_index;
-						      qp_attr->pkey_index;
+	else if (qp_pps)
+		new_pps->main.pkey_index = qp_pps->main.pkey_index;
 	if ((qp_attr_mask & IB_QP_PKEY_INDEX) && (qp_attr_mask & IB_QP_PORT))
 		new_pps->main.state = IB_PORT_PKEY_VALID;
-	if (!(qp_attr_mask & (IB_QP_PKEY_INDEX || IB_QP_PORT)) && qp_pps) {
+	if (!(qp_attr_mask & (IB_QP_PKEY_INDEX | IB_QP_PORT)) && qp_pps) {
 		new_pps->main.port_num = qp_pps->main.port_num;
 		new_pps->main.pkey_index = qp_pps->main.pkey_index;
 		if (qp_pps->main.state != IB_PORT_PKEY_NOT_VALID)

drivers/infiniband/core/umem_odp.c+19−5

@@ -181,14 +181,28 @@ ib_umem_odp_alloc_child(struct ib_umem_odp *root, unsigned long addr, · 180 unmodified lines
181	odp_data->page_shift = PAGE_SHIFT;	181	odp_data->page_shift = PAGE_SHIFT;
182	odp_data->notifier.ops = ops;	182	odp_data->notifier.ops = ops;
183		183
		184	/*
		185	* A mmget must be held when registering a notifier, the owming_mm only
		186	* has a mm_grab at this point.
		187	*/
		188	if (!mmget_not_zero(umem->owning_mm)) {
		189	ret = -EFAULT;
		190	goto out_free;
		191	}
		192
184	odp_data->tgid = get_pid(root->tgid);	193	odp_data->tgid = get_pid(root->tgid);
185	ret = ib_init_umem_odp(odp_data, ops);	194	ret = ib_init_umem_odp(odp_data, ops);
186	if (ret) {	195	if (ret)
187	put_pid(odp_data->tgid);	196	goto out_tgid;
188	kfree(odp_data);	197	mmput(umem->owning_mm);
189	return ERR_PTR(ret);
190	}
191	return odp_data;	198	return odp_data;
		199
		200	out_tgid:
		201	put_pid(odp_data->tgid);
		202	mmput(umem->owning_mm);
		203	out_free:
		204	kfree(odp_data);
		205	return ERR_PTR(ret);
192	}	206	}
193	EXPORT_SYMBOL(ib_umem_odp_alloc_child);	207	EXPORT_SYMBOL(ib_umem_odp_alloc_child);
194		208

drivers/infiniband/core/uverbs_cmd.c+0−9

@@ -1445,16 +1445,7 @@ static int create_qp(struct uverbs_attr_bundle *attrs, · 1444 unmodified lines
1445	if (ret)	1445	if (ret)
1446	goto err_cb;	1446	goto err_cb;
1447		1447
1448	qp->pd = pd;
1449	qp->send_cq = attr.send_cq;
1450	qp->recv_cq = attr.recv_cq;
1451	qp->srq = attr.srq;
1452	qp->rwq_ind_tbl = ind_tbl;
1453	qp->event_handler = attr.event_handler;
1454	qp->qp_type = attr.qp_type;
1455	atomic_set(&qp->usecnt, 0);
1456	atomic_inc(&pd->usecnt);	1448	atomic_inc(&pd->usecnt);
1457	qp->port = 0;
1458	if (attr.send_cq)	1449	if (attr.send_cq)
1459	atomic_inc(&attr.send_cq->usecnt);	1450	atomic_inc(&attr.send_cq->usecnt);
1460	if (attr.recv_cq)	1451	if (attr.recv_cq)

drivers/infiniband/core/verbs.c+0−10

@@ -1193,16 +1193,6 @@ struct ib_qp ib_create_qp(struct ib_pd pd, · 1192 unmodified lines
1193	if (ret)	1193	if (ret)
1194	goto err;	1194	goto err;
1195		1195
1196	qp->qp_type = qp_init_attr->qp_type;
1197	qp->rwq_ind_tbl = qp_init_attr->rwq_ind_tbl;
1198
1199	atomic_set(&qp->usecnt, 0);
1200	qp->mrs_used = 0;
1201	spin_lock_init(&qp->mr_lock);
1202	INIT_LIST_HEAD(&qp->rdma_mrs);
1203	INIT_LIST_HEAD(&qp->sig_mrs);
1204	qp->port = 0;
1205
1206	if (qp_init_attr->qp_type == IB_QPT_XRC_TGT) {	1196	if (qp_init_attr->qp_type == IB_QPT_XRC_TGT) {
1207	struct ib_qp *xrc_qp =	1197	struct ib_qp *xrc_qp =
1208	create_xrc_qp_user(qp, qp_init_attr);	1198	create_xrc_qp_user(qp, qp_init_attr);

drivers/infiniband/hw/hfi1/verbs.c+3−1

 				       opa_get_lid(packet->dlid, 9B));
 		if (!mcast)
 			goto drop;
+		rcu_read_lock();
 		list_for_each_entry_rcu(p, &mcast->qp_list, list) {
 			packet->qp = p->qp;
 			if (hfi1_do_pkey_check(packet))
-				goto drop;
+				goto unlock_drop;
 			spin_lock_irqsave(&packet->qp->r_lock, flags);
 			packet_handler = qp_ok(packet);
 			if (likely(packet_handler))
 				ibp->rvp.n_pkt_drops++;
 			spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 		}
+		rcu_read_unlock();
 		/*
 		 * Notify rvt_multicast_detach() if it is waiting for us
 		 * to finish.

drivers/infiniband/hw/mlx5/mlx5_ib.h+1−0

@@ -641,6 +641,7 @@ struct mlx5_ib_mr { · 640 unmodified lines
641		641
642	/* For ODP and implicit */	642	/* For ODP and implicit */
643	atomic_t num_deferred_work;	643	atomic_t num_deferred_work;
		644	wait_queue_head_t q_deferred_work;
644	struct xarray implicit_children;	645	struct xarray implicit_children;
645	union {	646	union {
646	struct rcu_head rcu;	647	struct rcu_head rcu;

drivers/infiniband/hw/mlx5/odp.c+7−10

 	mr->parent = NULL;
 	mlx5_mr_cache_free(mr->dev, mr);
 	ib_umem_odp_release(odp);
-	atomic_dec(&imr->num_deferred_work);
+	if (atomic_dec_and_test(&imr->num_deferred_work))
+		wake_up(&imr->q_deferred_work);
 }
 static void free_implicit_child_mr_work(struct work_struct *work)
 	imr->umem = &umem_odp->umem;
 	imr->is_odp_implicit = true;
 	atomic_set(&imr->num_deferred_work, 0);
+	init_waitqueue_head(&imr->q_deferred_work);
 	xa_init(&imr->implicit_children);
 	err = mlx5_ib_update_xlt(imr, 0,
 	 * under xa_lock while the child is in the xarray. Thus at this point
 	 * it is only decreasing, and all work holding it is now on the wq.
 	 */
-	if (atomic_read(&imr->num_deferred_work)) {
+	wait_event(imr->q_deferred_work, !atomic_read(&imr->num_deferred_work));
-		flush_workqueue(system_unbound_wq);
-		WARN_ON(atomic_read(&imr->num_deferred_work));
-	}
 	/*
 	 * Fence the imr before we destroy the children. This allows us to
 	/* Wait for all running page-fault handlers to finish. */
 	synchronize_srcu(&mr->dev->odp_srcu);
-	if (atomic_read(&mr->num_deferred_work)) {
+	wait_event(mr->q_deferred_work, !atomic_read(&mr->num_deferred_work));
-		flush_workqueue(system_unbound_wq);
-		WARN_ON(atomic_read(&mr->num_deferred_work));
-	}
 	dma_fence_odp_mr(mr);
 }
 	u32 i;
 	for (i = 0; i < work->num_sge; ++i)
-		atomic_dec(&work->frags[i].mr->num_deferred_work);
+		if (atomic_dec_and_test(&work->frags[i].mr->num_deferred_work))
+			wake_up(&work->frags[i].mr->q_deferred_work);
 	kvfree(work);
 }

drivers/infiniband/hw/qib/qib_verbs.c+2−0

 		if (mcast == NULL)
 			goto drop;
 		this_cpu_inc(ibp->pmastats->n_multicast_rcv);
+		rcu_read_lock();
 		list_for_each_entry_rcu(p, &mcast->qp_list, list)
 			qib_qp_rcv(rcd, hdr, 1, data, tlen, p->qp);
+		rcu_read_unlock();
 		/*
 		 * Notify rvt_multicast_detach() if it is waiting for us
 		 * to finish.

drivers/infiniband/sw/siw/siw_main.c+3−3

 		{ .max_segment_size = SZ_2G };
 	base_dev->num_comp_vectors = num_possible_cpus();
+	xa_init_flags(&sdev->qp_xa, XA_FLAGS_ALLOC1);
+	xa_init_flags(&sdev->mem_xa, XA_FLAGS_ALLOC1);
 	ib_set_device_ops(base_dev, &siw_device_ops);
 	rv = ib_device_set_netdev(base_dev, netdev, 1);
 	if (rv)
 	sdev->attrs.max_srq_wr = SIW_MAX_SRQ_WR;
 	sdev->attrs.max_srq_sge = SIW_MAX_SGE;
-	xa_init_flags(&sdev->qp_xa, XA_FLAGS_ALLOC1);
-	xa_init_flags(&sdev->mem_xa, XA_FLAGS_ALLOC1);
 	INIT_LIST_HEAD(&sdev->cep_list);
 	INIT_LIST_HEAD(&sdev->qp_list);

drivers/interconnect/core.c+9−0

 		path->name = kasprintf(GFP_KERNEL, "%s-%s",
 				       src_node->name, dst_node->name);
+	if (!path->name) {
+		kfree(path);
+		return ERR_PTR(-ENOMEM);
+	}
 	return path;
 }
 EXPORT_SYMBOL_GPL(of_icc_get);
 	}
 	path->name = kasprintf(GFP_KERNEL, "%s-%s", src->name, dst->name);
+	if (!path->name) {
+		kfree(path);
+		path = ERR_PTR(-ENOMEM);
+	}
 out:
 	mutex_unlock(&icc_lock);
 	return path;

drivers/md/bcache/alloc.c+2−16

@@ -67,7 +67,6 @@ · 66 unmodified lines
67	#include <linux/blkdev.h>	67	#include <linux/blkdev.h>
68	#include <linux/kthread.h>	68	#include <linux/kthread.h>
69	#include <linux/random.h>	69	#include <linux/random.h>
70	#include <linux/sched/signal.h>
71	#include <trace/events/bcache.h>	70	#include <trace/events/bcache.h>
72		71
73	#define MAX_OPEN_BUCKETS 128	72	#define MAX_OPEN_BUCKETS 128
@@ -734,21 +733,8 @@ int bch_open_buckets_alloc(struct cache_set *c) · 660 unmodified lines
734		733
735	int bch_cache_allocator_start(struct cache *ca)	734	int bch_cache_allocator_start(struct cache *ca)
736	{	735	{
737	struct task_struct *k;	736	struct task_struct *k = kthread_run(bch_allocator_thread,
738		737	ca, "bcache_allocator");
739	/*
740	* In case previous btree check operation occupies too many
741	* system memory for bcache btree node cache, and the
742	* registering process is selected by OOM killer. Here just
743	* ignore the SIGKILL sent by OOM killer if there is, to
744	* avoid kthread_run() being failed by pending signals. The
745	* bcache registering process will exit after the registration
746	* done.
747	*/
748	if (signal_pending(current))
749	flush_signals(current);
750
751	k = kthread_run(bch_allocator_thread, ca, "bcache_allocator");
752	if (IS_ERR(k))	738	if (IS_ERR(k))
753	return PTR_ERR(k);	739	return PTR_ERR(k);
754		740

drivers/md/bcache/btree.c+0−13

@@ -34,7 +34,6 @@ · 33 unmodified lines
34	#include <linux/random.h>	34	#include <linux/random.h>
35	#include <linux/rcupdate.h>	35	#include <linux/rcupdate.h>
36	#include <linux/sched/clock.h>	36	#include <linux/sched/clock.h>
37	#include <linux/sched/signal.h>
38	#include <linux/rculist.h>	37	#include <linux/rculist.h>
39	#include <linux/delay.h>	38	#include <linux/delay.h>
40	#include <trace/events/bcache.h>	39	#include <trace/events/bcache.h>
@@ -1914,18 +1913,6 @@ static int bch_gc_thread(void *arg) · 1873 unmodified lines
1914		1913
1915	int bch_gc_thread_start(struct cache_set *c)	1914	int bch_gc_thread_start(struct cache_set *c)
1916	{	1915	{
1917	/*
1918	* In case previous btree check operation occupies too many
1919	* system memory for bcache btree node cache, and the
1920	* registering process is selected by OOM killer. Here just
1921	* ignore the SIGKILL sent by OOM killer if there is, to
1922	* avoid kthread_run() being failed by pending signals. The
1923	* bcache registering process will exit after the registration
1924	* done.
1925	*/
1926	if (signal_pending(current))
1927	flush_signals(current);
1928
1929	c->gc_thread = kthread_run(bch_gc_thread, c, "bcache_gc");	1916	c->gc_thread = kthread_run(bch_gc_thread, c, "bcache_gc");
1930	return PTR_ERR_OR_ZERO(c->gc_thread);	1917	return PTR_ERR_OR_ZERO(c->gc_thread);
1931	}	1918	}

drivers/md/dm-bio-record.h+15−0

 struct dm_bio_details {
 	struct gendisk *bi_disk;
 	u8 bi_partno;
+	int __bi_remaining;
 	unsigned long bi_flags;
 	struct bvec_iter bi_iter;
+	bio_end_io_t *bi_end_io;
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+	struct bio_integrity_payload *bi_integrity;
+#endif
 };
 static inline void dm_bio_record(struct dm_bio_details *bd, struct bio *bio)
 	bd->bi_partno = bio->bi_partno;
 	bd->bi_flags = bio->bi_flags;
 	bd->bi_iter = bio->bi_iter;
+	bd->__bi_remaining = atomic_read(&bio->__bi_remaining);
+	bd->bi_end_io = bio->bi_end_io;
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+	bd->bi_integrity = bio_integrity(bio);
+#endif
 }
 static inline void dm_bio_restore(struct dm_bio_details *bd, struct bio *bio)
 	bio->bi_partno = bd->bi_partno;
 	bio->bi_flags = bd->bi_flags;
 	bio->bi_iter = bd->bi_iter;
+	atomic_set(&bio->__bi_remaining, bd->__bi_remaining);
+	bio->bi_end_io = bd->bi_end_io;
+#if defined(CONFIG_BLK_DEV_INTEGRITY)
+	bio->bi_integrity = bd->bi_integrity;
+#endif
 }
 #endif

drivers/md/dm-cache-target.c+3−3

@@ -2846,8 +2846,8 @@ static void cache_postsuspend(struct dm_target *ti) · 2845 unmodified lines
2846	prevent_background_work(cache);	2846	prevent_background_work(cache);
2847	BUG_ON(atomic_read(&cache->nr_io_migrations));	2847	BUG_ON(atomic_read(&cache->nr_io_migrations));
2848		2848
2849	cancel_delayed_work(&cache->waker);	2849	cancel_delayed_work_sync(&cache->waker);
2850	flush_workqueue(cache->wq);	2850	drain_workqueue(cache->wq);
2851	WARN_ON(cache->tracker.in_flight);	2851	WARN_ON(cache->tracker.in_flight);
2852		2852
2853	/*	2853	/*
@@ -3492,7 +3492,7 @@ static void cache_io_hints(struct dm_target ti, struct queue_limits limits) · 638 unmodified lines
3492		3492
3493	static struct target_type cache_target = {	3493	static struct target_type cache_target = {
3494	.name = "cache",	3494	.name = "cache",
3495	.version = {2, 1, 0},	3495	.version = {2, 2, 0},
3496	.module = THIS_MODULE,	3496	.module = THIS_MODULE,
3497	.ctr = cache_ctr,	3497	.ctr = cache_ctr,
3498	.dtr = cache_dtr,	3498	.dtr = cache_dtr,

drivers/md/dm-integrity.c+43−41

  * This file is released under the GPL.
  */
+#include "dm-bio-record.h"
 #include <linux/compiler.h>
 #include <linux/module.h>
 #include <linux/device-mapper.h>
 	__u8 log2_blocks_per_bitmap_bit;
 	unsigned char mode;
-	int suspending;
 	int failed;
 	struct crypto_shash *internal_hash;
+	struct dm_target *ti;
 	/* these variables are locked with endio_wait.lock */
 	struct rb_root in_progress;
 	struct list_head wait_list;
 	wait_queue_head_t endio_wait;
 	struct workqueue_struct *wait_wq;
+	struct workqueue_struct *offload_wq;
 	unsigned char commit_seq;
 	commit_id_t commit_ids[N_COMMIT_IDS];
 	struct completion *completion;
-	struct gendisk *orig_bi_disk;
+	struct dm_bio_details bio_details;
-	u8 orig_bi_partno;
-	bio_end_io_t *orig_bi_end_io;
-	struct bio_integrity_payload *orig_bi_integrity;
-	struct bvec_iter orig_bi_iter;
 };
 struct journal_completion {
 			dio->range.logical_sector += dio->range.n_sectors;
 			bio_advance(bio, dio->range.n_sectors << SECTOR_SHIFT);
 			INIT_WORK(&dio->work, integrity_bio_wait);
-			queue_work(ic->wait_wq, &dio->work);
+			queue_work(ic->offload_wq, &dio->work);
 			return;
 		}
 		do_endio_flush(ic, dio);
 {
 	struct dm_integrity_io *dio = dm_per_bio_data(bio, sizeof(struct dm_integrity_io));
-	bio->bi_iter = dio->orig_bi_iter;
+	dm_bio_restore(&dio->bio_details, bio);
-	bio->bi_disk = dio->orig_bi_disk;
+	if (bio->bi_integrity)
-	bio->bi_partno = dio->orig_bi_partno;
-	if (dio->orig_bi_integrity) {
-		bio->bi_integrity = dio->orig_bi_integrity;
 		bio->bi_opf |= REQ_INTEGRITY;
-	}
-	bio->bi_end_io = dio->orig_bi_end_io;
 	if (dio->completion)
 		complete(dio->completion);
 			}
 		}
-		__bio_for_each_segment(bv, bio, iter, dio->orig_bi_iter) {
+		__bio_for_each_segment(bv, bio, iter, dio->bio_details.bi_iter) {
 			unsigned pos;
 			char *mem, *checksums_ptr;
 		if (likely(checksums != checksums_onstack))
 			kfree(checksums);
 	} else {
-		struct bio_integrity_payload *bip = dio->orig_bi_integrity;
+		struct bio_integrity_payload *bip = dio->bio_details.bi_integrity;
 		if (bip) {
 			struct bio_vec biv;
 	if (need_sync_io && from_map) {
 		INIT_WORK(&dio->work, integrity_bio_wait);
-		queue_work(ic->metadata_wq, &dio->work);
+		queue_work(ic->offload_wq, &dio->work);
 		return;
 	}
 	} else
 		dio->completion = NULL;
-	dio->orig_bi_iter = bio->bi_iter;
+	dm_bio_record(&dio->bio_details, bio);
-	dio->orig_bi_disk = bio->bi_disk;
-	dio->orig_bi_partno = bio->bi_partno;
 	bio_set_dev(bio, ic->dev->bdev);
-	dio->orig_bi_integrity = bio_integrity(bio);
 	bio->bi_integrity = NULL;
 	bio->bi_opf &= ~REQ_INTEGRITY;
-	dio->orig_bi_end_io = bio->bi_end_io;
 	bio->bi_end_io = integrity_end_io;
 	bio->bi_iter.bi_size = dio->range.n_sectors << SECTOR_SHIFT;
 	generic_make_request(bio);
 	if (need_sync_io) {
 	unsigned prev_free_sectors;
 	/* the following test is not needed, but it tests the replay code */
-	if (READ_ONCE(ic->suspending) && !ic->meta_dev)
+	if (unlikely(dm_suspended(ic->ti)) && !ic->meta_dev)
 		return;
 	spin_lock_irq(&ic->endio_wait.lock);
 next_chunk:
-	if (unlikely(READ_ONCE(ic->suspending)))
+	if (unlikely(dm_suspended(ic->ti)))
 		goto unlock_ret;
 	range.logical_sector = le64_to_cpu(ic->sb->recalc_sector);
 				    dio->range.n_sectors, BITMAP_OP_TEST_ALL_SET)) {
 			remove_range(ic, &dio->range);
 			INIT_WORK(&dio->work, integrity_bio_wait);
-			queue_work(ic->wait_wq, &dio->work);
+			queue_work(ic->offload_wq, &dio->work);
 		} else {
 			block_bitmap_op(ic, ic->journal, dio->range.logical_sector,
 					dio->range.n_sectors, BITMAP_OP_SET);
 		remove_range(ic, &dio->range);
 		INIT_WORK(&dio->work, integrity_bio_wait);
-		queue_work(ic->wait_wq, &dio->work);
+		queue_work(ic->offload_wq, &dio->work);
 	}
 	queue_delayed_work(ic->commit_wq, &ic->bitmap_flush_work, ic->bitmap_flush_interval);
 	del_timer_sync(&ic->autocommit_timer);
-	WRITE_ONCE(ic->suspending, 1);
 	if (ic->recalc_wq)
 		drain_workqueue(ic->recalc_wq);
 #endif
 	}
-	WRITE_ONCE(ic->suspending, 0);
 	BUG_ON(!RB_EMPTY_ROOT(&ic->in_progress));
 	ic->journal_uptodate = true;
 	} else {
 		replay_journal(ic);
 		if (ic->mode == 'B') {
-			int mode;
 			ic->sb->flags |= cpu_to_le32(SB_FLAG_DIRTY_BITMAP);
 			ic->sb->log2_blocks_per_bitmap_bit = ic->log2_blocks_per_bitmap_bit;
 			r = sync_rw_sb(ic, REQ_OP_WRITE, REQ_FUA);
 			if (unlikely(r))
 				dm_integrity_io_error(ic, "writing superblock", r);
-			mode = ic->recalculate_flag ? BITMAP_OP_SET : BITMAP_OP_CLEAR;
+			block_bitmap_op(ic, ic->journal, 0, ic->provided_data_sectors, BITMAP_OP_CLEAR);
-			block_bitmap_op(ic, ic->journal, 0, ic->provided_data_sectors, mode);
+			block_bitmap_op(ic, ic->recalc_bitmap, 0, ic->provided_data_sectors, BITMAP_OP_CLEAR);
-			block_bitmap_op(ic, ic->recalc_bitmap, 0, ic->provided_data_sectors, mode);
+			block_bitmap_op(ic, ic->may_write_bitmap, 0, ic->provided_data_sectors, BITMAP_OP_CLEAR);
-			block_bitmap_op(ic, ic->may_write_bitmap, 0, ic->provided_data_sectors, mode);
+			if (ic->sb->flags & cpu_to_le32(SB_FLAG_RECALCULATING) &&
+			    le64_to_cpu(ic->sb->recalc_sector) < ic->provided_data_sectors) {
+				block_bitmap_op(ic, ic->journal, le64_to_cpu(ic->sb->recalc_sector),
+						ic->provided_data_sectors - le64_to_cpu(ic->sb->recalc_sector), BITMAP_OP_SET);
+				block_bitmap_op(ic, ic->recalc_bitmap, le64_to_cpu(ic->sb->recalc_sector),
+						ic->provided_data_sectors - le64_to_cpu(ic->sb->recalc_sector), BITMAP_OP_SET);
+				block_bitmap_op(ic, ic->may_write_bitmap, le64_to_cpu(ic->sb->recalc_sector),
+						ic->provided_data_sectors - le64_to_cpu(ic->sb->recalc_sector), BITMAP_OP_SET);
+			}
 			rw_journal_sectors(ic, REQ_OP_WRITE, REQ_FUA | REQ_SYNC, 0,
 					   ic->n_bitmap_blocks * (BITMAP_BLOCK_SIZE >> SECTOR_SHIFT), NULL);
 		}
 			DMEMIT(" meta_device:%s", ic->meta_dev->name);
 		if (ic->sectors_per_block != 1)
 			DMEMIT(" block_size:%u", ic->sectors_per_block << SECTOR_SHIFT);
-		if (ic->recalculate_flag)
+		if (ic->sb->flags & cpu_to_le32(SB_FLAG_RECALCULATING))
 			DMEMIT(" recalculate");
 		DMEMIT(" journal_sectors:%u", ic->initial_sectors - SB_SECTORS);
 		DMEMIT(" interleave_sectors:%u", 1U << ic->sb->log2_interleave_sectors);
 	}
 	ti->private = ic;
 	ti->per_io_data_size = sizeof(struct dm_integrity_io);
+	ic->ti = ti;
 	ic->in_progress = RB_ROOT;
 	INIT_LIST_HEAD(&ic->wait_list);
 		goto bad;
 	}
+	ic->offload_wq = alloc_workqueue("dm-integrity-offload", WQ_MEM_RECLAIM,
+					  METADATA_WORKQUEUE_MAX_ACTIVE);
+	if (!ic->offload_wq) {
+		ti->error = "Cannot allocate workqueue";
+		r = -ENOMEM;
+		goto bad;
+	}
 	ic->commit_wq = alloc_workqueue("dm-integrity-commit", WQ_MEM_RECLAIM, 1);
 	if (!ic->commit_wq) {
 		ti->error = "Cannot allocate workqueue";
 		destroy_workqueue(ic->metadata_wq);
 	if (ic->wait_wq)
 		destroy_workqueue(ic->wait_wq);
+	if (ic->offload_wq)
+		destroy_workqueue(ic->offload_wq);
 	if (ic->commit_wq)
 		destroy_workqueue(ic->commit_wq);
 	if (ic->writer_wq)
 static struct target_type integrity_target = {
 	.name			= "integrity",
-	.version		= {1, 4, 0},
+	.version		= {1, 5, 0},
 	.module			= THIS_MODULE,
 	.features		= DM_TARGET_SINGLETON | DM_TARGET_INTEGRITY,
 	.ctr			= dm_integrity_ctr,

drivers/md/dm-mpath.c+1−1

@@ -2053,7 +2053,7 @@ static int multipath_busy(struct dm_target *ti) · 2052 unmodified lines
2053	---------------------------------------------------------------/	2053	---------------------------------------------------------------/
2054	static struct target_type multipath_target = {	2054	static struct target_type multipath_target = {
2055	.name = "multipath",	2055	.name = "multipath",
2056	.version = {1, 13, 0},	2056	.version = {1, 14, 0},
2057	.features = DM_TARGET_SINGLETON \| DM_TARGET_IMMUTABLE \|	2057	.features = DM_TARGET_SINGLETON \| DM_TARGET_IMMUTABLE \|
2058	DM_TARGET_PASSES_INTEGRITY,	2058	DM_TARGET_PASSES_INTEGRITY,
2059	.module = THIS_MODULE,	2059	.module = THIS_MODULE,

drivers/md/dm-thin-metadata.c+1−1

 			DMWARN("%s: __commit_transaction() failed, error = %d",
 			       __func__, r);
 	}
+	pmd_write_unlock(pmd);
 	if (!pmd->fail_io)
 		__destroy_persistent_data_objects(pmd);
-	pmd_write_unlock(pmd);
 	kfree(pmd);
 	return 0;

drivers/md/dm-verity-target.c+1−1

@@ -1221,7 +1221,7 @@ bad: · 1220 unmodified lines
1221		1221
1222	static struct target_type verity_target = {	1222	static struct target_type verity_target = {
1223	.name = "verity",	1223	.name = "verity",
1224	.version = {1, 5, 0},	1224	.version = {1, 6, 0},
1225	.module = THIS_MODULE,	1225	.module = THIS_MODULE,
1226	.ctr = verity_ctr,	1226	.ctr = verity_ctr,
1227	.dtr = verity_dtr,	1227	.dtr = verity_dtr,

drivers/md/dm-writecache.c+12−4

@@ -625,6 +625,12 @@ static void writecache_add_to_freelist(struct dm_writecache *wc, struct wc_entry · 624 unmodified lines
625	wc->freelist_size++;	625	wc->freelist_size++;
626	}	626	}
627		627
		628	static inline void writecache_verify_watermark(struct dm_writecache *wc)
		629	{
		630	if (unlikely(wc->freelist_size + wc->writeback_size <= wc->freelist_high_watermark))
		631	queue_work(wc->writeback_wq, &wc->writeback_work);
		632	}
		633
628	static struct wc_entry writecache_pop_from_freelist(struct dm_writecache wc, sector_t expected_sector)	634	static struct wc_entry writecache_pop_from_freelist(struct dm_writecache wc, sector_t expected_sector)
629	{	635	{
630	struct wc_entry *e;	636	struct wc_entry *e;
@@ -650,8 +656,8 @@ static struct wc_entry writecache_pop_from_freelist(struct dm_writecache wc, s · 19 unmodified lines
650	list_del(&e->lru);	656	list_del(&e->lru);
651	}	657	}
652	wc->freelist_size--;	658	wc->freelist_size--;
653	if (unlikely(wc->freelist_size + wc->writeback_size <= wc->freelist_high_watermark))	659
654	queue_work(wc->writeback_wq, &wc->writeback_work);	660	writecache_verify_watermark(wc);
655		661
656	return e;	662	return e;
657	}	663	}
@@ -842,7 +848,7 @@ static void writecache_suspend(struct dm_target *ti) · 184 unmodified lines
842	}	848	}
843	wc_unlock(wc);	849	wc_unlock(wc);
844		850
845	flush_workqueue(wc->writeback_wq);	851	drain_workqueue(wc->writeback_wq);
846		852
847	wc_lock(wc);	853	wc_lock(wc);
848	if (flush_on_suspend)	854	if (flush_on_suspend)
@@ -965,6 +971,8 @@ erase_this: · 116 unmodified lines
965	writecache_commit_flushed(wc, false);	971	writecache_commit_flushed(wc, false);
966	}	972	}
967		973
		974	writecache_verify_watermark(wc);
		975
968	wc_unlock(wc);	976	wc_unlock(wc);
969	}	977	}
970		978
@@ -2312,7 +2320,7 @@ static void writecache_status(struct dm_target *ti, status_type_t type, · 1341 unmodified lines
2312		2320
2313	static struct target_type writecache_target = {	2321	static struct target_type writecache_target = {
2314	.name = "writecache",	2322	.name = "writecache",
2315	.version = {1, 1, 1},	2323	.version = {1, 2, 0},
2316	.module = THIS_MODULE,	2324	.module = THIS_MODULE,
2317	.ctr = writecache_ctr,	2325	.ctr = writecache_ctr,
2318	.dtr = writecache_dtr,	2326	.dtr = writecache_dtr,

drivers/md/dm-zoned-target.c+5−5

@@ -533,8 +533,9 @@ static int dmz_queue_chunk_work(struct dmz_target dmz, struct bio bio) · 532 unmodified lines
533		533
534	/* Get the BIO chunk work. If one is not active yet, create one */	534	/* Get the BIO chunk work. If one is not active yet, create one */
535	cw = radix_tree_lookup(&dmz->chunk_rxtree, chunk);	535	cw = radix_tree_lookup(&dmz->chunk_rxtree, chunk);
536	if (!cw) {	536	if (cw) {
537		537	dmz_get_chunk_work(cw);
		538	} else {
538	/* Create a new chunk work */	539	/* Create a new chunk work */
539	cw = kmalloc(sizeof(struct dm_chunk_work), GFP_NOIO);	540	cw = kmalloc(sizeof(struct dm_chunk_work), GFP_NOIO);
540	if (unlikely(!cw)) {	541	if (unlikely(!cw)) {
@@ -543,7 +544,7 @@ static int dmz_queue_chunk_work(struct dmz_target dmz, struct bio bio) · 2 unmodified lines
543	}	544	}
544		545
545	INIT_WORK(&cw->work, dmz_chunk_work);	546	INIT_WORK(&cw->work, dmz_chunk_work);
546	refcount_set(&cw->refcount, 0);	547	refcount_set(&cw->refcount, 1);
547	cw->target = dmz;	548	cw->target = dmz;
548	cw->chunk = chunk;	549	cw->chunk = chunk;
549	bio_list_init(&cw->bio_list);	550	bio_list_init(&cw->bio_list);
@@ -556,7 +557,6 @@ static int dmz_queue_chunk_work(struct dmz_target dmz, struct bio bio) · 6 unmodified lines
556	}	557	}
557		558
558	bio_list_add(&cw->bio_list, bio);	559	bio_list_add(&cw->bio_list, bio);
559	dmz_get_chunk_work(cw);
560		560
561	dmz_reclaim_bio_acc(dmz->reclaim);	561	dmz_reclaim_bio_acc(dmz->reclaim);
562	if (queue_work(dmz->chunk_wq, &cw->work))	562	if (queue_work(dmz->chunk_wq, &cw->work))
@@ -967,7 +967,7 @@ static int dmz_iterate_devices(struct dm_target *ti, · 404 unmodified lines
967		967
968	static struct target_type dmz_type = {	968	static struct target_type dmz_type = {
969	.name = "zoned",	969	.name = "zoned",
970	.version = {1, 0, 0},	970	.version = {1, 1, 0},
971	.features = DM_TARGET_SINGLETON \| DM_TARGET_ZONED_HM,	971	.features = DM_TARGET_SINGLETON \| DM_TARGET_ZONED_HM,
972	.module = THIS_MODULE,	972	.module = THIS_MODULE,
973	.ctr = dmz_ctr,	973	.ctr = dmz_ctr,

drivers/md/dm.c+11−11

 			 * With request-based DM we only need to check the
 			 * top-level queue for congestion.
 			 */
-			r = md->queue->backing_dev_info->wb.state & bdi_bits;
+			struct backing_dev_info *bdi = md->queue->backing_dev_info;
+			r = bdi->wb.congested->state & bdi_bits;
 		} else {
 			map = dm_get_live_table_fast(md);
 			if (map)
 static void dm_wq_work(struct work_struct *work);
-static void dm_init_normal_md_queue(struct mapped_device *md)
-{
-	/*
-	 * Initialize aspects of queue that aren't relevant for blk-mq
-	 */
-	md->queue->backing_dev_info->congested_data = md;
-	md->queue->backing_dev_info->congested_fn = dm_any_congested;
-}
 static void cleanup_mapped_device(struct mapped_device *md)
 {
 	if (md->wq)
 }
 EXPORT_SYMBOL_GPL(dm_get_queue_limits);
+static void dm_init_congested_fn(struct mapped_device *md)
+{
+	md->queue->backing_dev_info->congested_data = md;
+	md->queue->backing_dev_info->congested_fn = dm_any_congested;
+}
 /*
  * Setup the DM device's queue based on md's type
  */
 			DMERR("Cannot initialize queue for request-based dm-mq mapped device");
 			return r;
 		}
+		dm_init_congested_fn(md);
 		break;
 	case DM_TYPE_BIO_BASED:
 	case DM_TYPE_DAX_BIO_BASED:
 	case DM_TYPE_NVME_BIO_BASED:
-		dm_init_normal_md_queue(md);
+		dm_init_congested_fn(md);
 		break;
 	case DM_TYPE_NONE:
 		WARN_ON_ONCE(true);
 	map = dm_get_live_table(md, &srcu_idx);
 	if (!dm_suspended_md(md)) {
 		dm_table_presuspend_targets(map);
+		set_bit(DMF_SUSPENDED, &md->flags);
 		dm_table_postsuspend_targets(map);
 	}
 	/* dm_put_live_table must be before msleep, otherwise deadlock is possible */

drivers/media/mc/mc-entity.c+2−2

@@ -639,9 +639,9 @@ int media_get_pad_index(struct media_entity *entity, bool is_sink, · 638 unmodified lines
639	return -EINVAL;	639	return -EINVAL;
640		640
641	for (i = 0; i < entity->num_pads; i++) {	641	for (i = 0; i < entity->num_pads; i++) {
642	if (entity->pads[i].flags == MEDIA_PAD_FL_SINK)	642	if (entity->pads[i].flags & MEDIA_PAD_FL_SINK)
643	pad_is_sink = true;	643	pad_is_sink = true;
644	else if (entity->pads[i].flags == MEDIA_PAD_FL_SOURCE)	644	else if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
645	pad_is_sink = false;	645	pad_is_sink = false;
646	else	646	else
647	continue; /* This is an error! */	647	continue; /* This is an error! */

drivers/media/platform/vicodec/codec-v4l2-fwht.c+9−25

 	{ V4L2_PIX_FMT_BGR24,   3, 3, 1, 3, 3, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_RGB24,   3, 3, 1, 3, 3, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_HSV24,   3, 3, 1, 3, 3, 1, 1, 3, 1, FWHT_FL_PIXENC_HSV},
-	{ V4L2_PIX_FMT_BGR32,   4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_BGR32,   4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_XBGR32,  4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_XBGR32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_ABGR32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_RGB32,   4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_RGB32,   4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_XRGB32,  4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_XRGB32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_ARGB32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_BGRX32,  4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_BGRX32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_BGRA32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_RGBX32,  4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
+	{ V4L2_PIX_FMT_RGBX32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
 	{ V4L2_PIX_FMT_RGBA32,  4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
-	{ V4L2_PIX_FMT_HSV32,   4, 4, 1, 4, 4, 1, 1, 3, 1, FWHT_FL_PIXENC_HSV},
+	{ V4L2_PIX_FMT_HSV32,   4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_HSV},
 	{ V4L2_PIX_FMT_GREY,    1, 1, 1, 1, 0, 1, 1, 1, 1, FWHT_FL_PIXENC_RGB},
 };
 	case V4L2_PIX_FMT_RGB32:
 	case V4L2_PIX_FMT_XRGB32:
 	case V4L2_PIX_FMT_HSV32:
-		rf->cr = rf->luma + 1;
-		rf->cb = rf->cr + 2;
-		rf->luma += 2;
-		break;
-	case V4L2_PIX_FMT_BGR32:
-	case V4L2_PIX_FMT_XBGR32:
-		rf->cb = rf->luma;
-		rf->cr = rf->cb + 2;
-		rf->luma++;
-		break;
 	case V4L2_PIX_FMT_ARGB32:
 		rf->alpha = rf->luma;
 		rf->cr = rf->luma + 1;
 		rf->cb = rf->cr + 2;
 		rf->luma += 2;
 		break;
+	case V4L2_PIX_FMT_BGR32:
+	case V4L2_PIX_FMT_XBGR32:
 	case V4L2_PIX_FMT_ABGR32:
 		rf->cb = rf->luma;
 		rf->cr = rf->cb + 2;
 		rf->alpha = rf->cr + 1;
 		break;
 	case V4L2_PIX_FMT_BGRX32:
-		rf->cb = rf->luma + 1;
-		rf->cr = rf->cb + 2;
-		rf->luma += 2;
-		break;
 	case V4L2_PIX_FMT_BGRA32:
 		rf->alpha = rf->luma;
 		rf->cb = rf->luma + 1;
 		rf->luma += 2;
 		break;
 	case V4L2_PIX_FMT_RGBX32:
-		rf->cr = rf->luma;
-		rf->cb = rf->cr + 2;
-		rf->luma++;
-		break;
 	case V4L2_PIX_FMT_RGBA32:
 		rf->alpha = rf->luma + 3;
 		rf->cr = rf->luma;

drivers/media/usb/pulse8-cec/pulse8-cec.c+7−5

 	cancel_delayed_work_sync(&pulse8->ping_eeprom_work);
 	cancel_work_sync(&pulse8->irq_work);
 	cancel_work_sync(&pulse8->tx_work);
-	serio_close(pulse8->serio);
-	serio_set_drvdata(pulse8->serio, NULL);
 	kfree(pulse8);
 }
 	struct pulse8 *pulse8 = serio_get_drvdata(serio);
 	cec_unregister_adapter(pulse8->adap);
+	pulse8->serio = NULL;
+	serio_set_drvdata(serio, NULL);
+	serio_close(serio);
 }
 static int pulse8_setup(struct pulse8 *pulse8, struct serio *serio,
 	serio_set_drvdata(serio, pulse8);
 	INIT_WORK(&pulse8->irq_work, pulse8_irq_work_handler);
 	INIT_WORK(&pulse8->tx_work, pulse8_tx_work_handler);
+	INIT_DELAYED_WORK(&pulse8->ping_eeprom_work,
+			  pulse8_ping_eeprom_work_handler);
 	mutex_init(&pulse8->lock);
 	spin_lock_init(&pulse8->msg_lock);
 	pulse8->config_pending = false;
 		pulse8->restoring_config = true;
 	}
-	INIT_DELAYED_WORK(&pulse8->ping_eeprom_work,
-			  pulse8_ping_eeprom_work_handler);
 	schedule_delayed_work(&pulse8->ping_eeprom_work, PING_PERIOD);
 	return 0;
 close_serio:
+	pulse8->serio = NULL;
+	serio_set_drvdata(serio, NULL);
 	serio_close(serio);
 delete_adap:
 	cec_delete_adapter(pulse8->adap);
-	serio_set_drvdata(serio, NULL);
 free_device:
 	kfree(pulse8);
 	return err;

drivers/media/v4l2-core/v4l2-mem2mem.c+2−2

@@ -880,12 +880,12 @@ int v4l2_m2m_register_media_controller(struct v4l2_m2m_dev *m2m_dev, · 879 unmodified lines
880	goto err_rel_entity1;	880	goto err_rel_entity1;
881		881
882	/* Connect the three entities */	882	/* Connect the three entities */
883	ret = media_create_pad_link(m2m_dev->source, 0, &m2m_dev->proc, 1,	883	ret = media_create_pad_link(m2m_dev->source, 0, &m2m_dev->proc, 0,
884	MEDIA_LNK_FL_IMMUTABLE \| MEDIA_LNK_FL_ENABLED);	884	MEDIA_LNK_FL_IMMUTABLE \| MEDIA_LNK_FL_ENABLED);
885	if (ret)	885	if (ret)
886	goto err_rel_entity2;	886	goto err_rel_entity2;
887		887
888	ret = media_create_pad_link(&m2m_dev->proc, 0, &m2m_dev->sink, 0,	888	ret = media_create_pad_link(&m2m_dev->proc, 1, &m2m_dev->sink, 0,
889	MEDIA_LNK_FL_IMMUTABLE \| MEDIA_LNK_FL_ENABLED);	889	MEDIA_LNK_FL_IMMUTABLE \| MEDIA_LNK_FL_ENABLED);
890	if (ret)	890	if (ret)
891	goto err_rm_links0;	891	goto err_rm_links0;

drivers/misc/altera-stapl/altera.c+6−6

@@ -2112,8 +2112,8 @@ exit_done: · 2111 unmodified lines
2112	return status;	2112	return status;
2113	}	2113	}
2114		2114
2115	static int altera_get_note(u8 *p, s32 program_size,	2115	static int altera_get_note(u8 p, s32 program_size, s32 offset,
2116	s32 offset, char key, char *value, int length)	2116	char key, char value, int keylen, int vallen)
2117	/*	2117	/*
2118	* Gets key and value of NOTE fields in the JBC file.	2118	* Gets key and value of NOTE fields in the JBC file.
2119	* Can be called in two modes: if offset pointer is NULL,	2119	* Can be called in two modes: if offset pointer is NULL,
@@ -2170,7 +2170,7 @@ static int altera_get_note(u8 *p, s32 program_size, · 50 unmodified lines
2170	&p[note_table + (8 * i) + 4])];	2170	&p[note_table + (8 * i) + 4])];
2171		2171
2172	if (value != NULL)	2172	if (value != NULL)
2173	strlcpy(value, value_ptr, length);	2173	strlcpy(value, value_ptr, vallen);
2174		2174
2175	}	2175	}
2176	}	2176	}
@@ -2189,13 +2189,13 @@ static int altera_get_note(u8 *p, s32 program_size, · 12 unmodified lines
2189	strlcpy(key, &p[note_strings +	2189	strlcpy(key, &p[note_strings +
2190	get_unaligned_be32(	2190	get_unaligned_be32(
2191	&p[note_table + (8 * i)])],	2191	&p[note_table + (8 * i)])],
2192	length);	2192	keylen);
2193		2193
2194	if (value != NULL)	2194	if (value != NULL)
2195	strlcpy(value, &p[note_strings +	2195	strlcpy(value, &p[note_strings +
2196	get_unaligned_be32(	2196	get_unaligned_be32(
2197	&p[note_table + (8 * i) + 4])],	2197	&p[note_table + (8 * i) + 4])],
2198	length);	2198	vallen);
2199		2199
2200	*offset = i + 1;	2200	*offset = i + 1;
2201	}	2201	}
@@ -2449,7 +2449,7 @@ int altera_init(struct altera_config config, const struct firmware fw) · 247 unmodified lines
2449	__func__, (format_version == 2) ? "Jam STAPL" :	2449	__func__, (format_version == 2) ? "Jam STAPL" :
2450	"pre-standardized Jam 1.1");	2450	"pre-standardized Jam 1.1");
2451	while (altera_get_note((u8 *)fw->data, fw->size,	2451	while (altera_get_note((u8 *)fw->data, fw->size,
2452	&offset, key, value, 256) == 0)	2452	&offset, key, value, 32, 256) == 0)
2453	printk(KERN_INFO "%s: NOTE \"%s\" = \"%s\"\n",	2453	printk(KERN_INFO "%s: NOTE \"%s\" = \"%s\"\n",
2454	__func__, key, value);	2454	__func__, key, value);
2455	}	2455	}

drivers/perf/arm_pmu_acpi.c+2−5

 	int gsi, trigger;
 	gicc = acpi_cpu_get_madt_gicc(cpu);
-	if (WARN_ON(!gicc))
-		return -EINVAL;
 	gsi = gicc->performance_interrupt;
 	int gsi;
 	gicc = acpi_cpu_get_madt_gicc(cpu);
-	if (!gicc)
-		return;
 	gsi = gicc->performance_interrupt;
-	acpi_unregister_gsi(gsi);
+	if (gsi)
+		acpi_unregister_gsi(gsi);
 }
 #if IS_ENABLED(CONFIG_ARM_SPE_PMU)

drivers/perf/fsl_imx8_ddr_perf.c+6−4

 	if (enable) {
 		/*
-		 * must disable first, then enable again
+		 * cycle counter is special which should firstly write 0 then
-		 * otherwise, cycle counter will not work
+		 * write 1 into CLEAR bit to clear it. Other counters only
-		 * if previous state is enabled.
+		 * need write 0 into CLEAR bit and it turns out to be 1 by
+		 * hardware. Below enable flow is harmless for all counters.
 		 */
 		writel(0, pmu->base + reg);
 		val = CNTL_EN | CNTL_CLEAR;
 		writel(val, pmu->base + reg);
 	} else {
 		/* Disable counter */
-		writel(0, pmu->base + reg);
+		val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK;
+		writel(val, pmu->base + reg);
 	}
 }

drivers/phy/allwinner/phy-sun50i-usb3.c+1−1

@@ -49,7 +49,7 @@ · 48 unmodified lines
49	#define SUNXI_LOS_BIAS(n) ((n) << 3)	49	#define SUNXI_LOS_BIAS(n) ((n) << 3)
50	#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)	50	#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)
51	#define SUNXI_TXVBOOSTLVL(n) ((n) << 0)	51	#define SUNXI_TXVBOOSTLVL(n) ((n) << 0)
52	#define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2)	52	#define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0)
53		53
54	struct sun50i_usb3_phy {	54	struct sun50i_usb3_phy {
55	struct phy *phy;	55	struct phy *phy;

drivers/phy/broadcom/phy-brcm-sata.c+65−83

 	PHY_CTRL_1_RESET			= BIT(0),
 };
-static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
-{
-	struct brcm_sata_phy *priv = port->phy_priv;
-	u32 size = 0;
-	switch (priv->version) {
-	case BRCM_SATA_PHY_STB_16NM:
-	case BRCM_SATA_PHY_STB_28NM:
-	case BRCM_SATA_PHY_IPROC_NS2:
-	case BRCM_SATA_PHY_DSL_28NM:
-		size = SATA_PCB_REG_28NM_SPACE_SIZE;
-		break;
-	case BRCM_SATA_PHY_STB_40NM:
-		size = SATA_PCB_REG_40NM_SPACE_SIZE;
-		break;
-	default:
-		dev_err(priv->dev, "invalid phy version\n");
-		break;
-	}
-	return priv->phy_base + (port->portnum * size);
-}
 static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
 {
 	struct brcm_sata_phy *priv = port->phy_priv;
 	return priv->ctrl_base + (port->portnum * size);
 }
-static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank,
+static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank,
 			     u32 ofs, u32 msk, u32 value)
 {
+	struct brcm_sata_phy *priv = port->phy_priv;
+	void __iomem *pcb_base = priv->phy_base;
 	u32 tmp;
+	if (priv->version == BRCM_SATA_PHY_STB_40NM)
+		bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
+	else
+		pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
 	writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
 	tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
 	tmp = (tmp & msk) | value;
 	writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
 }
-static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
+static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs)
 {
+	struct brcm_sata_phy *priv = port->phy_priv;
+	void __iomem *pcb_base = priv->phy_base;
+	if (priv->version == BRCM_SATA_PHY_STB_40NM)
+		bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
+	else
+		pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
 	writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
 	return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
 }
 static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
 {
-	void __iomem *base = brcm_sata_pcb_base(port);
 	struct brcm_sata_phy *priv = port->phy_priv;
 	u32 tmp;
 	/* override the TX spread spectrum setting */
 	tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
-	brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
+	brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
 	/* set fixed min freq */
-	brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
+	brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
 			 ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
 			 STB_FMIN_VAL_DEFAULT);
 		tmp = STB_FMAX_VAL_DEFAULT;
 	}
-	brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
+	brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
 			  ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
 }
 static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
 {
-	void __iomem *base = brcm_sata_pcb_base(port);
 	u32 tmp = 0, reg = 0;
 	switch (port->rxaeq_mode) {
 		break;
 	}
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
 	return 0;
 }
 static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
 {
-	void __iomem *base = brcm_sata_pcb_base(port);
 	u32 tmp, value;
 	/* Reduce CP tail current to 1/16th of its default value */
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
 	/* Turn off CP tail current boost */
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
 	/* Set a specific AEQ equalizer value */
 	tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
 			 ~(tmp | AEQ_RFZ_FRC_VAL |
 			   AEQ_FRC_EQ_VAL_MASK << AEQ_FRC_EQ_VAL_SHIFT),
 			 tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
 		value = 0x52;
 	else
 		value = 0;
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
 			 ~RXPMD_RX_PPM_VAL_MASK, value);
 	/* Set proportional loop bandwith Gen1/2/3 */
 		value = 1 << RXPMD_G1_CDR_PROP_BW_SHIFT |
 			1 << RXPMD_G2_CDR_PROP_BW_SHIFT |
 			1 << RXPMD_G3_CDR_PROB_BW_SHIFT;
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
 			 value);
 	/* Set CDR integral loop acquisition bandwidth for Gen1/2/3 */
 			1 << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
 	else
 		value = 0;
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
 			 ~tmp, value);
 	/* Set CDR integral loop locking bandwidth to 1 for Gen 1/2/3 */
 			1 << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
 	else
 		value = 0;
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
 			 ~tmp, value);
 	/* Set no guard band and clamp CDR */
 		value = 0x51;
 	else
 		value = 0;
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
 			 ~tmp, RXPMD_MON_CORRECT_EN | value);
 	/* Turn on/off SSC */
-	brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
+	brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
 			 port->ssc_en ? TX_ACTRL5_SSC_EN : 0);
 	return 0;
 {
 	int try;
 	unsigned int val;
-	void __iomem *base = brcm_sata_pcb_base(port);
 	void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
 	struct device *dev = port->phy_priv->dev;
 	val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
 	val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
 	val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
 	val = 0x0;
 	val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
 	val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
 	val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
 	/* Configure PHY PLL register bank 1 */
 	val = NS2_PLL1_ACTRL2_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
 	val = NS2_PLL1_ACTRL3_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
 	val = NS2_PLL1_ACTRL4_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
 	/* Configure PHY BLOCK0 register bank */
 	/* Set oob_clk_sel to refclk/2 */
-	brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE,
+	brcm_sata_phy_wr(port, BLOCK0_REG_BANK, BLOCK0_SPARE,
 			 ~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
 			 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
 	/* Wait for PHY PLL lock by polling pll_lock bit */
 	try = 50;
 	while (try) {
-		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+		val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 					BLOCK0_XGXSSTATUS);
 		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
 			break;
 static int brcm_nsp_sata_init(struct brcm_sata_port *port)
 {
-	struct brcm_sata_phy *priv = port->phy_priv;
 	struct device *dev = port->phy_priv->dev;
-	void __iomem *base = priv->phy_base;
 	unsigned int oob_bank;
 	unsigned int val, try;
 	val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
 	val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
 	val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
-	brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val);
+	brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val);
 	val = 0x0;
 	val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
 	val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
 	val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
-	brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val);
+	brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL2,
 		~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
 		0x0c << PLL_ACTRL2_SELDIV_SHIFT);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CONTROL,
 						0xff0, 0x4f0);
 	val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 								~val, val);
 	val = PLLCONTROL_0_SEQ_START;
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 								~val, 0);
 	mdelay(10);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 								~val, val);
 	/* Wait for pll_seq_done bit */
 	try = 50;
 	while (--try) {
-		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+		val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 					BLOCK0_XGXSSTATUS);
 		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
 			break;
 static int brcm_sr_sata_init(struct brcm_sata_port *port)
 {
-	struct brcm_sata_phy *priv = port->phy_priv;
 	struct device *dev = port->phy_priv->dev;
-	void __iomem *base = priv->phy_base;
 	unsigned int val, try;
 	/* Configure PHY PLL register bank 1 */
 	val = SR_PLL1_ACTRL2_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
 	val = SR_PLL1_ACTRL3_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
 	val = SR_PLL1_ACTRL4_MAGIC;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
 	/* Configure PHY PLL register bank 0 */
 	val = SR_PLL0_ACTRL6_MAGIC;
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
 	/* Wait for PHY PLL lock by polling pll_lock bit */
 	try = 50;
 	do {
-		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+		val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 					BLOCK0_XGXSSTATUS);
 		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
 			break;
 	}
 	/* Invert Tx polarity */
-	brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0,
+	brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL0,
 			 ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP);
 	/* Configure OOB control to handle 100MHz reference clock */
 		(0x4 << OOB_CTRL1_BURST_MIN_SHIFT) |
 		(0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) |
 		(0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT));
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
 	val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
 		(0x2 << OOB_CTRL2_BURST_CNT_SHIFT) |
 		(0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT));
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
 	return 0;
 }
 static int brcm_dsl_sata_init(struct brcm_sata_port *port)
 {
-	void __iomem *base = brcm_sata_pcb_base(port);
 	struct device *dev = port->phy_priv->dev;
 	unsigned int try;
 	u32 tmp;
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 			 0, 0x3089);
 	usleep_range(1000, 2000);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
 			 0, 0x3088);
 	usleep_range(1000, 2000);
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
 			 0, 0x3000);
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
 			 0, 0x3000);
 	usleep_range(1000, 2000);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
 	usleep_range(1000, 2000);
 	/* Acquire PLL lock */
 	try = 50;
 	while (try) {
-		tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+		tmp = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
 				       BLOCK0_XGXSSTATUS);
 		if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
 			break;
 static void brcm_stb_sata_calibrate(struct brcm_sata_port *port)
 {
-	void __iomem *base = brcm_sata_pcb_base(port);
 	u32 tmp = BIT(8);
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
 			 ~tmp, tmp);
 }

drivers/phy/motorola/phy-mapphone-mdm6600.c+24−3

 #define PHY_MDM6600_PHY_DELAY_MS	4000	/* PHY enable 2.2s to 3.5s */
 #define PHY_MDM6600_ENABLED_DELAY_MS	8000	/* 8s more total for MDM6600 */
+#define PHY_MDM6600_WAKE_KICK_MS	600	/* time on after GPIO toggle */
 #define MDM6600_MODEM_IDLE_DELAY_MS	1000	/* modem after USB suspend */
 #define MDM6600_MODEM_WAKE_DELAY_MS	200	/* modem response after idle */
 {
 	struct phy_mdm6600 *ddata = data;
 	struct gpio_desc *mode_gpio1;
+	int error, wakeup;
 	mode_gpio1 = ddata->mode_gpios->desc[PHY_MDM6600_MODE1];
-	dev_dbg(ddata->dev, "OOB wake on mode_gpio1: %i\n",
+	wakeup = gpiod_get_value(mode_gpio1);
-		gpiod_get_value(mode_gpio1));
+	if (!wakeup)
+		return IRQ_NONE;
+	dev_dbg(ddata->dev, "OOB wake on mode_gpio1: %i\n", wakeup);
+	error = pm_runtime_get_sync(ddata->dev);
+	if (error < 0) {
+		pm_runtime_put_noidle(ddata->dev);
+		return IRQ_NONE;
+	}
+	/* Just wake-up and kick the autosuspend timer */
+	pm_runtime_mark_last_busy(ddata->dev);
+	pm_runtime_put_autosuspend(ddata->dev);
 	return IRQ_HANDLED;
 }
 	ddata = container_of(work, struct phy_mdm6600, modem_wake_work.work);
 	phy_mdm6600_wake_modem(ddata);
+	/*
+	 * The modem does not always stay awake 1.2 seconds after toggling
+	 * the wake GPIO, and sometimes it idles after about some 600 ms
+	 * making writes time out.
+	 */
 	schedule_delayed_work(&ddata->modem_wake_work,
-			      msecs_to_jiffies(MDM6600_MODEM_IDLE_DELAY_MS));
+			      msecs_to_jiffies(PHY_MDM6600_WAKE_KICK_MS));
 }
 static int __maybe_unused phy_mdm6600_runtime_suspend(struct device *dev)

drivers/phy/phy-core.c+6−12

 	get_device(&phy->dev);
 	link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
-	if (!link) {
+	if (!link)
-		dev_err(dev, "failed to create device link to %s\n",
+		dev_dbg(dev, "failed to create device link to %s\n",
 			dev_name(phy->dev.parent));
-		return ERR_PTR(-EINVAL);
-	}
 	return phy;
 }
 	}
 	link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
-	if (!link) {
+	if (!link)
-		dev_err(dev, "failed to create device link to %s\n",
+		dev_dbg(dev, "failed to create device link to %s\n",
 			dev_name(phy->dev.parent));
-		return ERR_PTR(-EINVAL);
-	}
 	return phy;
 }
 	devres_add(dev, ptr);
 	link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
-	if (!link) {
+	if (!link)
-		dev_err(dev, "failed to create device link to %s\n",
+		dev_dbg(dev, "failed to create device link to %s\n",
 			dev_name(phy->dev.parent));
-		return ERR_PTR(-EINVAL);
-	}
 	return phy;
 }

drivers/phy/ti/phy-gmii-sel.c+5−5

 		break;
 	case PHY_INTERFACE_MODE_MII:
-		mode = AM33XX_GMII_SEL_MODE_MII;
+	case PHY_INTERFACE_MODE_GMII:
+		gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII;
 		break;
 	default:
-		dev_warn(dev,
+		dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
-			 "port%u: unsupported mode: \"%s\". Defaulting to MII.\n",
+			 if_phy->id, phy_modes(submode));
-			 if_phy->id, phy_modes(rgmii_id));
 		return -EINVAL;
 	}
 	if_phy->phy_if_mode = submode;
 	dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n",
-		__func__, if_phy->id, mode, rgmii_id,
+		__func__, if_phy->id, submode, rgmii_id,
 		if_phy->rmii_clock_external);
 	regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE];

drivers/regulator/stm32-vrefbuf.c+2−1

 	}
 	val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
-	val = (val & ~STM32_ENVR) | STM32_HIZ;
+	val &= ~STM32_ENVR;
 	writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
 	pm_runtime_mark_last_busy(priv->dev);
 	.volt_table = stm32_vrefbuf_voltages,
 	.n_voltages = ARRAY_SIZE(stm32_vrefbuf_voltages),
 	.ops = &stm32_vrefbuf_volt_ops,
+	.off_on_delay = 1000,
 	.type = REGULATOR_VOLTAGE,
 	.owner = THIS_MODULE,
 };

drivers/reset/Kconfig+2−1

 config RESET_BRCMSTB_RESCAL
 	bool "Broadcom STB RESCAL reset controller"
+	depends on HAS_IOMEM
 	default ARCH_BRCMSTB || COMPILE_TEST
 	help
 	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
 config RESET_INTEL_GW
 	bool "Intel Reset Controller Driver"
-	depends on OF
+	depends on OF && HAS_IOMEM
 	select REGMAP_MMIO
 	help
 	  This enables the reset controller driver for Intel Gateway SoCs.

drivers/soc/imx/soc-imx-scu.c+1−1

@@ -25,7 +25,7 @@ struct imx_sc_msg_misc_get_soc_id { · 24 unmodified lines
25	u32 id;	25	u32 id;
26	} resp;	26	} resp;
27	} data;	27	} data;
28	} __packed;	28	} __packed __aligned(4);
29		29
30	struct imx_sc_msg_misc_get_soc_uid {	30	struct imx_sc_msg_misc_get_soc_uid {
31	struct imx_sc_rpc_msg hdr;	31	struct imx_sc_rpc_msg hdr;

drivers/spi/atmel-quadspi.c+11−0

 	struct clk		*qspick;
 	struct platform_device	*pdev;
 	const struct atmel_qspi_caps *caps;
+	resource_size_t		mmap_size;
 	u32			pending;
 	u32			mr;
 	u32			scr;
 	u32 sr, offset;
 	int err;
+	/*
+	 * Check if the address exceeds the MMIO window size. An improvement
+	 * would be to add support for regular SPI mode and fall back to it
+	 * when the flash memories overrun the controller's memory space.
+	 */
+	if (op->addr.val + op->data.nbytes > aq->mmap_size)
+		return -ENOTSUPP;
 	err = atmel_qspi_set_cfg(aq, op, &offset);
 	if (err)
 		return err;
 		goto exit;
 	}
+	aq->mmap_size = resource_size(res);
 	/* Get the peripheral clock */
 	aq->pclk = devm_clk_get(&pdev->dev, "pclk");
 	if (IS_ERR(aq->pclk))

drivers/spi/spi-bcm63xx-hsspi.c+0−1

@@ -366,7 +366,6 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) · 365 unmodified lines
366	goto out_disable_clk;	366	goto out_disable_clk;
367		367
368	rate = clk_get_rate(pll_clk);	368	rate = clk_get_rate(pll_clk);
369	clk_disable_unprepare(pll_clk);
370	if (!rate) {	369	if (!rate) {
371	ret = -EINVAL;	370	ret = -EINVAL;
372	goto out_disable_pll_clk;	371	goto out_disable_pll_clk;

drivers/spi/spi-omap2-mcspi.c+64−39

 	int			fifo_depth;
 	bool			slave_aborted;
 	unsigned int		pin_dir:1;
+	size_t			max_xfer_len;
 };
 struct omap2_mcspi_cs {
  * Note that we currently allow DMA only if we get a channel
  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
  */
-static int omap2_mcspi_request_dma(struct spi_device *spi)
+static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
+				   struct omap2_mcspi_dma *mcspi_dma)
 {
-	struct spi_master	*master = spi->master;
-	struct omap2_mcspi	*mcspi;
-	struct omap2_mcspi_dma	*mcspi_dma;
 	int ret = 0;
-	mcspi = spi_master_get_devdata(master);
+	mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
-	mcspi_dma = mcspi->dma_channels + spi->chip_select;
-	init_completion(&mcspi_dma->dma_rx_completion);
-	init_completion(&mcspi_dma->dma_tx_completion);
-	mcspi_dma->dma_rx = dma_request_chan(&master->dev,
 					     mcspi_dma->dma_rx_ch_name);
 	if (IS_ERR(mcspi_dma->dma_rx)) {
 		ret = PTR_ERR(mcspi_dma->dma_rx);
 		goto no_dma;
 	}
-	mcspi_dma->dma_tx = dma_request_chan(&master->dev,
+	mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
 					     mcspi_dma->dma_tx_ch_name);
 	if (IS_ERR(mcspi_dma->dma_tx)) {
 		ret = PTR_ERR(mcspi_dma->dma_tx);
 		mcspi_dma->dma_rx = NULL;
 	}
+	init_completion(&mcspi_dma->dma_rx_completion);
+	init_completion(&mcspi_dma->dma_tx_completion);
 no_dma:
 	return ret;
 }
+static void omap2_mcspi_release_dma(struct spi_master *master)
+{
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
+	struct omap2_mcspi_dma	*mcspi_dma;
+	int i;
+	for (i = 0; i < master->num_chipselect; i++) {
+		mcspi_dma = &mcspi->dma_channels[i];
+		if (mcspi_dma->dma_rx) {
+			dma_release_channel(mcspi_dma->dma_rx);
+			mcspi_dma->dma_rx = NULL;
+		}
+		if (mcspi_dma->dma_tx) {
+			dma_release_channel(mcspi_dma->dma_tx);
+			mcspi_dma->dma_tx = NULL;
+		}
+	}
+}
 static int omap2_mcspi_setup(struct spi_device *spi)
 {
 	int			ret;
 	struct omap2_mcspi	*mcspi = spi_master_get_devdata(spi->master);
 	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
-	struct omap2_mcspi_dma	*mcspi_dma;
 	struct omap2_mcspi_cs	*cs = spi->controller_state;
-	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 	if (!cs) {
 		cs = kzalloc(sizeof *cs, GFP_KERNEL);
 		if (!cs)
 		}
 	}
-	if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
-		ret = omap2_mcspi_request_dma(spi);
-		if (ret)
-			dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
-				 ret);
-	}
 	ret = pm_runtime_get_sync(mcspi->dev);
 	if (ret < 0) {
 		pm_runtime_put_noidle(mcspi->dev);
 static void omap2_mcspi_cleanup(struct spi_device *spi)
 {
-	struct omap2_mcspi	*mcspi;
-	struct omap2_mcspi_dma	*mcspi_dma;
 	struct omap2_mcspi_cs	*cs;
-	mcspi = spi_master_get_devdata(spi->master);
 	if (spi->controller_state) {
 		/* Unlink controller state from context save list */
 		cs = spi->controller_state;
 		kfree(cs);
 	}
-	if (spi->chip_select < spi->master->num_chipselect) {
-		mcspi_dma = &mcspi->dma_channels[spi->chip_select];
-		if (mcspi_dma->dma_rx) {
-			dma_release_channel(mcspi_dma->dma_rx);
-			mcspi_dma->dma_rx = NULL;
-		}
-		if (mcspi_dma->dma_tx) {
-			dma_release_channel(mcspi_dma->dma_tx);
-			mcspi_dma->dma_tx = NULL;
-		}
-	}
 	if (gpio_is_valid(spi->cs_gpio))
 		gpio_free(spi->cs_gpio);
 }
 	if (spi_controller_is_slave(master))
 		return true;
+	master->dma_rx = mcspi_dma->dma_rx;
+	master->dma_tx = mcspi_dma->dma_tx;
 	return (xfer->len >= DMA_MIN_BYTES);
 }
+static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
+{
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
+	struct omap2_mcspi_dma *mcspi_dma =
+		&mcspi->dma_channels[spi->chip_select];
+	if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
+		return mcspi->max_xfer_len;
+	return SIZE_MAX;
+}
 static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
 {
 	struct spi_master	*master = mcspi->master;
 	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
 };
+static struct omap2_mcspi_platform_config am654_pdata = {
+	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
+	.max_xfer_len = SZ_4K - 1,
+};
 static const struct of_device_id omap_mcspi_of_match[] = {
 	{
 		.compatible = "ti,omap2-mcspi",
 		.compatible = "ti,omap4-mcspi",
 		.data = &omap4_pdata,
 	},
+	{
+		.compatible = "ti,am654-mcspi",
+		.data = &am654_pdata,
+	},
 	{ },
 };
 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
 		mcspi->pin_dir = pdata->pin_dir;
 	}
 	regs_offset = pdata->regs_offset;
+	if (pdata->max_xfer_len) {
+		mcspi->max_xfer_len = pdata->max_xfer_len;
+		master->max_transfer_size = omap2_mcspi_max_xfer_size;
+	}
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	mcspi->base = devm_ioremap_resource(&pdev->dev, r);
 	for (i = 0; i < master->num_chipselect; i++) {
 		sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
 		sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
+		status = omap2_mcspi_request_dma(mcspi,
+						 &mcspi->dma_channels[i]);
+		if (status == -EPROBE_DEFER)
+			goto free_master;
 	}
 	status = platform_get_irq(pdev, 0);
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 free_master:
+	omap2_mcspi_release_dma(master);
 	spi_master_put(master);
 	return status;
 }
 	struct spi_master *master = platform_get_drvdata(pdev);
 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
+	omap2_mcspi_release_dma(master);
 	pm_runtime_dont_use_autosuspend(mcspi->dev);
 	pm_runtime_put_sync(mcspi->dev);
 	pm_runtime_disable(&pdev->dev);

drivers/spi/spi-pxa2xx.c+23−0

 #define LPSS_CAPS_CS_EN_SHIFT			9
 #define LPSS_CAPS_CS_EN_MASK			(0xf << LPSS_CAPS_CS_EN_SHIFT)
+#define LPSS_PRIV_CLOCK_GATE 0x38
+#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
+#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
 struct lpss_config {
 	/* LPSS offset from drv_data->ioaddr */
 	unsigned offset;
 	unsigned cs_sel_shift;
 	unsigned cs_sel_mask;
 	unsigned cs_num;
+	/* Quirks */
+	unsigned cs_clk_stays_gated : 1;
 };
 /* Keep these sorted with enum pxa_ssp_type */
 		.tx_threshold_hi = 56,
 		.cs_sel_shift = 8,
 		.cs_sel_mask = 3 << 8,
+		.cs_clk_stays_gated = true,
 	},
 };
 	else
 		value |= LPSS_CS_CONTROL_CS_HIGH;
 	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
+	if (config->cs_clk_stays_gated) {
+		u32 clkgate;
+		/*
+		 * Changing CS alone when dynamic clock gating is on won't
+		 * actually flip CS at that time. This ruins SPI transfers
+		 * that specify delays, or have no data. Toggle the clock mode
+		 * to force on briefly to poke the CS pin to move.
+		 */
+		clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
+		value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
+			LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
+		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
+		__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
+	}
 }
 static void cs_assert(struct spi_device *spi)

drivers/spi/spi-qup.c+7−4

 	struct spi_qup *controller = spi_master_get_devdata(master);
 	int ret;
+	if (pm_runtime_suspended(device)) {
+		ret = spi_qup_pm_resume_runtime(device);
+		if (ret)
+			return ret;
+	}
 	ret = spi_master_suspend(master);
 	if (ret)
 		return ret;
 	if (ret)
 		return ret;
-	if (!pm_runtime_suspended(device)) {
+	clk_disable_unprepare(controller->cclk);
-		clk_disable_unprepare(controller->cclk);
+	clk_disable_unprepare(controller->iclk);
-		clk_disable_unprepare(controller->iclk);
-	}
 	return 0;
 }

drivers/spi/spi-zynqmp-gqspi.c+0−3

@@ -401,9 +401,6 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) · 400 unmodified lines
401		401
402	zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);	402	zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
403		403
404	/* Dummy generic FIFO entry */
405	zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
406
407	/* Manually start the generic FIFO command */	404	/* Manually start the generic FIFO command */
408	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,	405	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
409	zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) \|	406	zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) \|

drivers/spi/spi.c+15−17

 		if (ctlr->use_gpio_descriptors) {
 			status = spi_get_gpio_descs(ctlr);
 			if (status)
-				return status;
+				goto free_bus_id;
 			/*
 			 * A controller using GPIO descriptors always
 			 * supports SPI_CS_HIGH if need be.
 			/* Legacy code path for GPIOs from DT */
 			status = of_spi_get_gpio_numbers(ctlr);
 			if (status)
-				return status;
+				goto free_bus_id;
 		}
 	}
 	 * Even if it's just one always-selected device, there must
 	 * be at least one chipselect.
 	 */
-	if (!ctlr->num_chipselect)
+	if (!ctlr->num_chipselect) {
-		return -EINVAL;
+		status = -EINVAL;
+		goto free_bus_id;
+	}
 	status = device_add(&ctlr->dev);
-	if (status < 0) {
+	if (status < 0)
-		/* free bus id */
+		goto free_bus_id;
-		mutex_lock(&board_lock);
-		idr_remove(&spi_master_idr, ctlr->bus_num);
-		mutex_unlock(&board_lock);
-		goto done;
-	}
 	dev_dbg(dev, "registered %s %s\n",
 			spi_controller_is_slave(ctlr) ? "slave" : "master",
 			dev_name(&ctlr->dev));
 		status = spi_controller_initialize_queue(ctlr);
 		if (status) {
 			device_del(&ctlr->dev);
-			/* free bus id */
+			goto free_bus_id;
-			mutex_lock(&board_lock);
-			idr_remove(&spi_master_idr, ctlr->bus_num);
-			mutex_unlock(&board_lock);
-			goto done;
 		}
 	}
 	/* add statistics */
 	/* Register devices from the device tree and ACPI */
 	of_register_spi_devices(ctlr);
 	acpi_register_spi_devices(ctlr);
-done:
+	return status;
+free_bus_id:
+	mutex_lock(&board_lock);
+	idr_remove(&spi_master_idr, ctlr->bus_num);
+	mutex_unlock(&board_lock);
 	return status;
 }
 EXPORT_SYMBOL_GPL(spi_register_controller);

drivers/spi/spidev.c+5−0

 		else
 			retval = get_user(tmp, (u32 __user *)arg);
 		if (retval == 0) {
+			struct spi_controller *ctlr = spi->controller;
 			u32	save = spi->mode;
 			if (tmp & ~SPI_MODE_MASK) {
 				break;
 			}
+			if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods &&
+			    ctlr->cs_gpiods[spi->chip_select])
+				tmp |= SPI_CS_HIGH;
 			tmp |= spi->mode & ~SPI_MODE_MASK;
 			spi->mode = (u16)tmp;
 			retval = spi_setup(spi);

drivers/staging/media/hantro/hantro_drv.c+2−2

@@ -558,13 +558,13 @@ static int hantro_attach_func(struct hantro_dev *vpu, · 557 unmodified lines
558	goto err_rel_entity1;	558	goto err_rel_entity1;
559		559
560	/* Connect the three entities */	560	/* Connect the three entities */
561	ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 1,	561	ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 0,
562	MEDIA_LNK_FL_IMMUTABLE \|	562	MEDIA_LNK_FL_IMMUTABLE \|
563	MEDIA_LNK_FL_ENABLED);	563	MEDIA_LNK_FL_ENABLED);
564	if (ret)	564	if (ret)
565	goto err_rel_entity2;	565	goto err_rel_entity2;
566		566
567	ret = media_create_pad_link(&func->proc, 0, &func->sink, 0,	567	ret = media_create_pad_link(&func->proc, 1, &func->sink, 0,
568	MEDIA_LNK_FL_IMMUTABLE \|	568	MEDIA_LNK_FL_IMMUTABLE \|
569	MEDIA_LNK_FL_ENABLED);	569	MEDIA_LNK_FL_ENABLED);
570	if (ret)	570	if (ret)

drivers/staging/speakup/selection.c+0−2

@@ -51,9 +51,7 @@ static void __speakup_set_selection(struct work_struct *work) · 50 unmodified lines
51	goto unref;	51	goto unref;
52	}	52	}
53		53
54	console_lock();
55	set_selection_kernel(&sel, tty);	54	set_selection_kernel(&sel, tty);
56	console_unlock();
57		55
58	unref:	56	unref:
59	tty_kref_put(tty);	57	tty_kref_put(tty);

drivers/staging/wfx/Documentation/devicetree/bindings/net/wireless/siliabs,wfx.txt+1−1

@@ -93,5 +93,5 @@ Some properties are recognized either by SPI and SDIO versions: · 92 unmodified lines
93	Must contains 64 hexadecimal digits. Not supported in current version.	93	Must contains 64 hexadecimal digits. Not supported in current version.
94		94
95	WFx driver also supports `mac-address` and `local-mac-address` as described in	95	WFx driver also supports `mac-address` and `local-mac-address` as described in
96	Documentation/devicetree/binding/net/ethernet.txt	96	Documentation/devicetree/bindings/net/ethernet.txt
97		97

drivers/tee/amdtee/core.c+24−24

@@ -212,6 +212,19 @@ unlock: · 211 unmodified lines
212	return rc;	212	return rc;
213	}	213	}
214		214
		215	static void destroy_session(struct kref *ref)
		216	{
		217	struct amdtee_session *sess = container_of(ref, struct amdtee_session,
		218	refcount);
		219
		220	/* Unload the TA from TEE */
		221	handle_unload_ta(sess->ta_handle);
		222	mutex_lock(&session_list_mutex);
		223	list_del(&sess->list_node);
		224	mutex_unlock(&session_list_mutex);
		225	kfree(sess);
		226	}
		227
215	int amdtee_open_session(struct tee_context *ctx,	228	int amdtee_open_session(struct tee_context *ctx,
216	struct tee_ioctl_open_session_arg *arg,	229	struct tee_ioctl_open_session_arg *arg,
217	struct tee_param *param)	230	struct tee_param *param)
@@ -236,15 +249,13 @@ int amdtee_open_session(struct tee_context *ctx, · 18 unmodified lines
236		249
237	/* Load the TA binary into TEE environment */	250	/* Load the TA binary into TEE environment */
238	handle_load_ta(ta, ta_size, arg);	251	handle_load_ta(ta, ta_size, arg);
239	if (arg->ret == TEEC_SUCCESS) {
240	mutex_lock(&session_list_mutex);
241	sess = alloc_session(ctxdata, arg->session);
242	mutex_unlock(&session_list_mutex);
243	}
244
245	if (arg->ret != TEEC_SUCCESS)	252	if (arg->ret != TEEC_SUCCESS)
246	goto out;	253	goto out;
247		254
		255	mutex_lock(&session_list_mutex);
		256	sess = alloc_session(ctxdata, arg->session);
		257	mutex_unlock(&session_list_mutex);
		258
248	if (!sess) {	259	if (!sess) {
249	rc = -ENOMEM;	260	rc = -ENOMEM;
250	goto out;	261	goto out;
@@ -259,40 +270,29 @@ int amdtee_open_session(struct tee_context *ctx, · 8 unmodified lines
259		270
260	if (i >= TEE_NUM_SESSIONS) {	271	if (i >= TEE_NUM_SESSIONS) {
261	pr_err("reached maximum session count %d\n", TEE_NUM_SESSIONS);	272	pr_err("reached maximum session count %d\n", TEE_NUM_SESSIONS);
		273	kref_put(&sess->refcount, destroy_session);
262	rc = -ENOMEM;	274	rc = -ENOMEM;
263	goto out;	275	goto out;
264	}	276	}
265		277
266	/* Open session with loaded TA */	278	/* Open session with loaded TA */
267	handle_open_session(arg, &session_info, param);	279	handle_open_session(arg, &session_info, param);
268		280	if (arg->ret != TEEC_SUCCESS) {
269	if (arg->ret == TEEC_SUCCESS) {
270	sess->session_info[i] = session_info;
271	set_session_id(sess->ta_handle, i, &arg->session);
272	} else {
273	pr_err("open_session failed %d\n", arg->ret);	281	pr_err("open_session failed %d\n", arg->ret);
274	spin_lock(&sess->lock);	282	spin_lock(&sess->lock);
275	clear_bit(i, sess->sess_mask);	283	clear_bit(i, sess->sess_mask);
276	spin_unlock(&sess->lock);	284	spin_unlock(&sess->lock);
		285	kref_put(&sess->refcount, destroy_session);
		286	goto out;
277	}	287	}
		288
		289	sess->session_info[i] = session_info;
		290	set_session_id(sess->ta_handle, i, &arg->session);
278	out:	291	out:
279	free_pages((u64)ta, get_order(ta_size));	292	free_pages((u64)ta, get_order(ta_size));
280	return rc;	293	return rc;
281	}	294	}
282		295
283	static void destroy_session(struct kref *ref)
284	{
285	struct amdtee_session *sess = container_of(ref, struct amdtee_session,
286	refcount);
287
288	/* Unload the TA from TEE */
289	handle_unload_ta(sess->ta_handle);
290	mutex_lock(&session_list_mutex);
291	list_del(&sess->list_node);
292	mutex_unlock(&session_list_mutex);
293	kfree(sess);
294	}
295
296	int amdtee_close_session(struct tee_context *ctx, u32 session)	296	int amdtee_close_session(struct tee_context *ctx, u32 session)
297	{	297	{
298	struct amdtee_context_data *ctxdata = ctx->data;	298	struct amdtee_context_data *ctxdata = ctx->data;

drivers/tty/serdev/core.c+10−0

 #include <linux/sched.h>
 #include <linux/serdev.h>
 #include <linux/slab.h>
+#include <linux/platform_data/x86/apple.h>
 static bool is_registered;
 static DEFINE_IDA(ctrl_ida);
 	if (ret)
 		return ret;
+	/*
+	 * Apple machines provide an empty resource template, so on those
+	 * machines just look for immediate children with a "baud" property
+	 * (from the _DSM method) instead.
+	 */
+	if (!lookup.controller_handle && x86_apple_machine &&
+	    !acpi_dev_get_property(adev, "baud", ACPI_TYPE_BUFFER, NULL))
+		acpi_get_parent(adev->handle, &lookup.controller_handle);
 	/* Make sure controller and ResourceSource handle match */
 	if (ACPI_HANDLE(ctrl->dev.parent) != lookup.controller_handle)
 		return -ENODEV;

drivers/tty/serial/8250/8250_exar.c+33−0

@@ -25,6 +25,14 @@ · 24 unmodified lines
25		25
26	#include "8250.h"	26	#include "8250.h"
27		27
		28	#define PCI_DEVICE_ID_ACCES_COM_2S 0x1052
		29	#define PCI_DEVICE_ID_ACCES_COM_4S 0x105d
		30	#define PCI_DEVICE_ID_ACCES_COM_8S 0x106c
		31	#define PCI_DEVICE_ID_ACCES_COM232_8 0x10a8
		32	#define PCI_DEVICE_ID_ACCES_COM_2SM 0x10d2
		33	#define PCI_DEVICE_ID_ACCES_COM_4SM 0x10db
		34	#define PCI_DEVICE_ID_ACCES_COM_8SM 0x10ea
		35
28	#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002	36	#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
29	#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004	37	#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
30	#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a	38	#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
@@ -677,6 +685,22 @@ static int __maybe_unused exar_resume(struct device *dev) · 646 unmodified lines
677		685
678	static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);	686	static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
679		687
		688	static const struct exar8250_board acces_com_2x = {
		689	.num_ports = 2,
		690	.setup = pci_xr17c154_setup,
		691	};
		692
		693	static const struct exar8250_board acces_com_4x = {
		694	.num_ports = 4,
		695	.setup = pci_xr17c154_setup,
		696	};
		697
		698	static const struct exar8250_board acces_com_8x = {
		699	.num_ports = 8,
		700	.setup = pci_xr17c154_setup,
		701	};
		702
		703
680	static const struct exar8250_board pbn_fastcom335_2 = {	704	static const struct exar8250_board pbn_fastcom335_2 = {
681	.num_ports = 2,	705	.num_ports = 2,
682	.setup = pci_fastcom335_setup,	706	.setup = pci_fastcom335_setup,
@@ -745,6 +769,15 @@ static const struct exar8250_board pbn_exar_XR17V8358 = { · 62 unmodified lines
745	}	769	}
746		770
747	static const struct pci_device_id exar_pci_tbl[] = {	771	static const struct pci_device_id exar_pci_tbl[] = {
		772	EXAR_DEVICE(ACCESSIO, ACCES_COM_2S, acces_com_2x),
		773	EXAR_DEVICE(ACCESSIO, ACCES_COM_4S, acces_com_4x),
		774	EXAR_DEVICE(ACCESSIO, ACCES_COM_8S, acces_com_8x),
		775	EXAR_DEVICE(ACCESSIO, ACCES_COM232_8, acces_com_8x),
		776	EXAR_DEVICE(ACCESSIO, ACCES_COM_2SM, acces_com_2x),
		777	EXAR_DEVICE(ACCESSIO, ACCES_COM_4SM, acces_com_4x),
		778	EXAR_DEVICE(ACCESSIO, ACCES_COM_8SM, acces_com_8x),
		779
		780
748	CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),	781	CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
749	CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),	782	CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
750	CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),	783	CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),

drivers/tty/serial/fsl_lpuart.c+26−15

 	int			rx_dma_rng_buf_len;
 	unsigned int		dma_tx_nents;
 	wait_queue_head_t	dma_wait;
+	bool			id_allocated;
 };
 struct lpuart_soc_data {
 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
+EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
+EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
 #define LPUART_CONSOLE	(&lpuart_console)
 #define LPUART32_CONSOLE	(&lpuart32_console)
 	if (!sport)
 		return -ENOMEM;
-	ret = of_alias_get_id(np, "serial");
-	if (ret < 0) {
-		ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
-		if (ret < 0) {
-			dev_err(&pdev->dev, "port line is full, add device failed\n");
-			return ret;
-		}
-	}
-	if (ret >= ARRAY_SIZE(lpuart_ports)) {
-		dev_err(&pdev->dev, "serial%d out of range\n", ret);
-		return -EINVAL;
-	}
-	sport->port.line = ret;
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(sport->port.membase))
 		}
 	}
+	ret = of_alias_get_id(np, "serial");
+	if (ret < 0) {
+		ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "port line is full, add device failed\n");
+			return ret;
+		}
+		sport->id_allocated = true;
+	}
+	if (ret >= ARRAY_SIZE(lpuart_ports)) {
+		dev_err(&pdev->dev, "serial%d out of range\n", ret);
+		ret = -EINVAL;
+		goto failed_out_of_range;
+	}
+	sport->port.line = ret;
 	ret = lpuart_enable_clks(sport);
 	if (ret)
-		return ret;
+		goto failed_clock_enable;
 	sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
 	lpuart_ports[sport->port.line] = sport;
 failed_attach_port:
 failed_irq_request:
 	lpuart_disable_clks(sport);
+failed_clock_enable:
+failed_out_of_range:
+	if (sport->id_allocated)
+		ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
 	return ret;
 }
 	uart_remove_one_port(&lpuart_reg, &sport->port);
-	ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
+	if (sport->id_allocated)
+		ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
 	lpuart_disable_clks(sport);

drivers/tty/serial/mvebu-uart.c+1−1

@@ -851,7 +851,7 @@ static int mvebu_uart_probe(struct platform_device *pdev) · 850 unmodified lines
851		851
852	port->membase = devm_ioremap_resource(&pdev->dev, reg);	852	port->membase = devm_ioremap_resource(&pdev->dev, reg);
853	if (IS_ERR(port->membase))	853	if (IS_ERR(port->membase))
854	return -PTR_ERR(port->membase);	854	return PTR_ERR(port->membase);
855		855
856	mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),	856	mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
857	GFP_KERNEL);	857	GFP_KERNEL);

drivers/tty/vt/selection.c+18−9

@@ -181,7 +181,7 @@ int set_selection_user(const struct tiocl_selection __user *sel, · 180 unmodified lines
181	return set_selection_kernel(&v, tty);	181	return set_selection_kernel(&v, tty);
182	}	182	}
183		183
184	int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty)	184	static int __set_selection_kernel(struct tiocl_selection v, struct tty_struct tty)
185	{	185	{
186	struct vc_data *vc = vc_cons[fg_console].d;	186	struct vc_data *vc = vc_cons[fg_console].d;
187	int new_sel_start, new_sel_end, spc;	187	int new_sel_start, new_sel_end, spc;
@@ -214,7 +214,6 @@ int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty) · 26 unmodified lines
214	if (ps > pe) /* make sel_start <= sel_end */	214	if (ps > pe) /* make sel_start <= sel_end */
215	swap(ps, pe);	215	swap(ps, pe);
216		216
217	mutex_lock(&sel_lock);
218	if (sel_cons != vc_cons[fg_console].d) {	217	if (sel_cons != vc_cons[fg_console].d) {
219	clear_selection();	218	clear_selection();
220	sel_cons = vc_cons[fg_console].d;	219	sel_cons = vc_cons[fg_console].d;
@@ -260,10 +259,9 @@ int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty) · 39 unmodified lines
260	break;	259	break;
261	case TIOCL_SELPOINTER:	260	case TIOCL_SELPOINTER:
262	highlight_pointer(pe);	261	highlight_pointer(pe);
263	goto unlock;	262	return 0;
264	default:	263	default:
265	ret = -EINVAL;	264	return -EINVAL;
266	goto unlock;
267	}	265	}
268		266
269	/* remove the pointer */	267	/* remove the pointer */
@@ -285,7 +283,7 @@ int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty) · 15 unmodified lines
285	else if (new_sel_start == sel_start)	283	else if (new_sel_start == sel_start)
286	{	284	{
287	if (new_sel_end == sel_end) /* no action required */	285	if (new_sel_end == sel_end) /* no action required */
288	goto unlock;	286	return 0;
289	else if (new_sel_end > sel_end) /* extend to right */	287	else if (new_sel_end > sel_end) /* extend to right */
290	highlight(sel_end + 2, new_sel_end);	288	highlight(sel_end + 2, new_sel_end);
291	else /* contract from right */	289	else /* contract from right */
@@ -313,8 +311,7 @@ int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty) · 21 unmodified lines
313	if (!bp) {	311	if (!bp) {
314	printk(KERN_WARNING "selection: kmalloc() failed\n");	312	printk(KERN_WARNING "selection: kmalloc() failed\n");
315	clear_selection();	313	clear_selection();
316	ret = -ENOMEM;	314	return -ENOMEM;
317	goto unlock;
318	}	315	}
319	kfree(sel_buffer);	316	kfree(sel_buffer);
320	sel_buffer = bp;	317	sel_buffer = bp;
@@ -339,8 +336,20 @@ int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty) · 18 unmodified lines
339	}	336	}
340	}	337	}
341	sel_buffer_lth = bp - sel_buffer;	338	sel_buffer_lth = bp - sel_buffer;
342	unlock:	339
		340	return ret;
		341	}
		342
		343	int set_selection_kernel(struct tiocl_selection v, struct tty_struct tty)
		344	{
		345	int ret;
		346
		347	mutex_lock(&sel_lock);
		348	console_lock();
		349	ret = __set_selection_kernel(v, tty);
		350	console_unlock();
343	mutex_unlock(&sel_lock);	351	mutex_unlock(&sel_lock);
		352
344	return ret;	353	return ret;
345	}	354	}
346	EXPORT_SYMBOL_GPL(set_selection_kernel);	355	EXPORT_SYMBOL_GPL(set_selection_kernel);

drivers/tty/vt/vt.c+0−2

 	switch (type)
 	{
 		case TIOCL_SETSEL:
-			console_lock();
 			ret = set_selection_user((struct tiocl_selection
 						 __user *)(p+1), tty);
-			console_unlock();
 			break;
 		case TIOCL_PASTESEL:
 			ret = paste_selection(tty);

drivers/usb/cdns3/gadget.c+15−4

@@ -2550,7 +2550,7 @@ found: · 2549 unmodified lines
2550	/* Update ring only if removed request is on pending_req_list list */	2550	/* Update ring only if removed request is on pending_req_list list */
2551	if (req_on_hw_ring) {	2551	if (req_on_hw_ring) {
2552	link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma +	2552	link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma +
2553	(priv_req->start_trb * TRB_SIZE));	2553	((priv_req->end_trb + 1) * TRB_SIZE));
2554	link_trb->control = (link_trb->control & TRB_CYCLE) \|	2554	link_trb->control = (link_trb->control & TRB_CYCLE) \|
2555	TRB_TYPE(TRB_LINK) \| TRB_CHAIN;	2555	TRB_TYPE(TRB_LINK) \| TRB_CHAIN;
2556		2556
@@ -2595,11 +2595,21 @@ int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep) · 38 unmodified lines
2595	{	2595	{
2596	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;	2596	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
2597	struct usb_request *request;	2597	struct usb_request *request;
		2598	struct cdns3_request *priv_req;
		2599	struct cdns3_trb *trb = NULL;
2598	int ret;	2600	int ret;
2599	int val;	2601	int val;
2600		2602
2601	trace_cdns3_halt(priv_ep, 0, 0);	2603	trace_cdns3_halt(priv_ep, 0, 0);
2602		2604
		2605	request = cdns3_next_request(&priv_ep->pending_req_list);
		2606	if (request) {
		2607	priv_req = to_cdns3_request(request);
		2608	trb = priv_req->trb;
		2609	if (trb)
		2610	trb->control = trb->control ^ TRB_CYCLE;
		2611	}
		2612
2603	writel(EP_CMD_CSTALL \| EP_CMD_EPRST, &priv_dev->regs->ep_cmd);	2613	writel(EP_CMD_CSTALL \| EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
2604		2614
2605	/* wait for EPRST cleared */	2615	/* wait for EPRST cleared */
@@ -2610,10 +2620,11 @@ int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep) · 4 unmodified lines
2610		2620
2611	priv_ep->flags &= ~(EP_STALLED \| EP_STALL_PENDING);	2621	priv_ep->flags &= ~(EP_STALLED \| EP_STALL_PENDING);
2612		2622
2613	request = cdns3_next_request(&priv_ep->pending_req_list);	2623	if (request) {
2614		2624	if (trb)
2615	if (request)	2625	trb->control = trb->control ^ TRB_CYCLE;
2616	cdns3_rearm_transfer(priv_ep, 1);	2626	cdns3_rearm_transfer(priv_ep, 1);
		2627	}
2617		2628
2618	cdns3_start_all_request(priv_dev, priv_ep);	2629	cdns3_start_all_request(priv_dev, priv_ep);
2619	return ret;	2630	return ret;

drivers/usb/core/hub.c+6−2

 {
 	struct usb_hub *hub;
 	struct usb_interface *intf;
+	int ret;
 	if (!udev->parent)	/* Can't remove a root hub */
 		return -EINVAL;
 	hub = usb_hub_to_struct_hub(udev->parent);
 	intf = to_usb_interface(hub->intfdev);
-	usb_autopm_get_interface(intf);
+	ret = usb_autopm_get_interface(intf);
+	if (ret < 0)
+		return ret;
 	set_bit(udev->portnum, hub->removed_bits);
 	hub_port_logical_disconnect(hub, udev->portnum);
 	usb_autopm_put_interface(intf);
 	if (id->driver_info & HUB_QUIRK_DISABLE_AUTOSUSPEND) {
 		hub->quirk_disable_autosuspend = 1;
-		usb_autopm_get_interface(intf);
+		usb_autopm_get_interface_no_resume(intf);
 	}
 	if (hub_configure(hub, &desc->endpoint[0].desc) >= 0)

drivers/usb/core/port.c+8−2

 	if (!port_dev->is_superspeed && peer)
 		pm_runtime_get_sync(&peer->dev);
-	usb_autopm_get_interface(intf);
+	retval = usb_autopm_get_interface(intf);
+	if (retval < 0)
+		return retval;
 	retval = usb_hub_set_port_power(hdev, hub, port1, true);
 	msleep(hub_power_on_good_delay(hub));
 	if (udev && !retval) {
 	if (usb_port_block_power_off)
 		return -EBUSY;
-	usb_autopm_get_interface(intf);
+	retval = usb_autopm_get_interface(intf);
+	if (retval < 0)
+		return retval;
 	retval = usb_hub_set_port_power(hdev, hub, port1, false);
 	usb_clear_port_feature(hdev, port1, USB_PORT_FEAT_C_CONNECTION);
 	if (!port_dev->is_superspeed)

drivers/usb/core/quirks.c+3−0

@@ -231,6 +231,9 @@ static const struct usb_device_id usb_quirk_list[] = { · 230 unmodified lines
231	/* Logitech PTZ Pro Camera */	231	/* Logitech PTZ Pro Camera */
232	{ USB_DEVICE(0x046d, 0x0853), .driver_info = USB_QUIRK_DELAY_INIT },	232	{ USB_DEVICE(0x046d, 0x0853), .driver_info = USB_QUIRK_DELAY_INIT },
233		233
		234	/* Logitech Screen Share */
		235	{ USB_DEVICE(0x046d, 0x086c), .driver_info = USB_QUIRK_NO_LPM },
		236
234	/* Logitech Quickcam Fusion */	237	/* Logitech Quickcam Fusion */
235	{ USB_DEVICE(0x046d, 0x08c1), .driver_info = USB_QUIRK_RESET_RESUME },	238	{ USB_DEVICE(0x046d, 0x08c1), .driver_info = USB_QUIRK_RESET_RESUME },
236		239

drivers/usb/dwc3/gadget.c+8−1

 		unsigned int rem = length % maxp;
 		unsigned chain = true;
-		if (sg_is_last(s))
+		/*
+		 * IOMMU driver is coalescing the list of sgs which shares a
+		 * page boundary into one and giving it to USB driver. With
+		 * this the number of sgs mapped is not equal to the number of
+		 * sgs passed. So mark the chain bit to false if it isthe last
+		 * mapped sg.
+		 */
+		if (i == remaining - 1)
 			chain = false;
 		if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {

drivers/usb/misc/usb251xb.c+16−4

 		return err;
 	}
-	hub->vdd = devm_regulator_get(dev, "vdd");
-	if (IS_ERR(hub->vdd))
-		return PTR_ERR(hub->vdd);
 	if (of_property_read_u16_array(np, "vendor-id", &hub->vendor_id, 1))
 		hub->vendor_id = USB251XB_DEF_VENDOR_ID;
 }
 #endif /* CONFIG_OF */
+static void usb251xb_regulator_disable_action(void *data)
+{
+	struct usb251xb *hub = data;
+	regulator_disable(hub->vdd);
+}
 static int usb251xb_probe(struct usb251xb *hub)
 {
 	struct device *dev = hub->dev;
 	if (err)
 		return err;
+	hub->vdd = devm_regulator_get(dev, "vdd");
+	if (IS_ERR(hub->vdd))
+		return PTR_ERR(hub->vdd);
 	err = regulator_enable(hub->vdd);
 	if (err)
 		return err;
+	err = devm_add_action_or_reset(dev,
+				       usb251xb_regulator_disable_action, hub);
+	if (err)
+		return err;
 	err = usb251xb_connect(hub);
 	if (err) {
 		dev_err(dev, "Failed to connect hub (%d)\n", err);

drivers/usb/storage/unusual_devs.h+6−0

 		USB_SC_RBC, USB_PR_BULK, NULL,
 		0 ),
+UNUSUAL_DEV(0x090c, 0x1000, 0x1100, 0x1100,
+		"Samsung",
+		"Flash Drive FIT",
+		USB_SC_DEVICE, USB_PR_DEVICE, NULL,
+		US_FL_MAX_SECTORS_64),
 /* aeb */
 UNUSUAL_DEV( 0x090c, 0x1132, 0x0000, 0xffff,
 		"Feiya",

drivers/video/backlight/Kconfig+7−0

@@ -456,6 +456,13 @@ config BACKLIGHT_RAVE_SP · 455 unmodified lines
456	help	456	help
457	Support for backlight control on RAVE SP device.	457	Support for backlight control on RAVE SP device.
458		458
		459	config BACKLIGHT_LED
		460	tristate "Generic LED based Backlight Driver"
		461	depends on LEDS_CLASS && OF
		462	help
		463	If you have a LCD backlight adjustable by LED class driver, say Y
		464	to enable this driver.
		465
459	endif # BACKLIGHT_CLASS_DEVICE	466	endif # BACKLIGHT_CLASS_DEVICE
460		467
461	endmenu	468	endmenu

drivers/video/backlight/Makefile+1−0

@@ -57,3 +57,4 @@ obj-$(CONFIG_BACKLIGHT_TPS65217) += tps65217_bl.o · 56 unmodified lines
57	obj-$(CONFIG_BACKLIGHT_WM831X) += wm831x_bl.o	57	obj-$(CONFIG_BACKLIGHT_WM831X) += wm831x_bl.o
58	obj-$(CONFIG_BACKLIGHT_ARCXCNN) += arcxcnn_bl.o	58	obj-$(CONFIG_BACKLIGHT_ARCXCNN) += arcxcnn_bl.o
59	obj-$(CONFIG_BACKLIGHT_RAVE_SP) += rave-sp-backlight.o	59	obj-$(CONFIG_BACKLIGHT_RAVE_SP) += rave-sp-backlight.o
		60	obj-$(CONFIG_BACKLIGHT_LED) += led_bl.o

drivers/video/backlight/led_bl.c+260−0

@@ -0,0 +1,260 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/
	4	* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
	5	*
	6	* Based on pwm_bl.c
	7	*/
	8
	9	#include <linux/backlight.h>
	10	#include <linux/leds.h>
	11	#include <linux/module.h>
	12	#include <linux/platform_device.h>
	13
	14	struct led_bl_data {
	15	struct device *dev;
	16	struct backlight_device *bl_dev;
	17	struct led_classdev **leds;
	18	bool enabled;
	19	int nb_leds;
	20	unsigned int *levels;
	21	unsigned int default_brightness;
	22	unsigned int max_brightness;
	23	};
	24
	25	static void led_bl_set_brightness(struct led_bl_data *priv, int level)
	26	{
	27	int i;
	28	int bkl_brightness;
	29
	30	if (priv->levels)
	31	bkl_brightness = priv->levels[level];
	32	else
	33	bkl_brightness = level;
	34
	35	for (i = 0; i < priv->nb_leds; i++)
	36	led_set_brightness(priv->leds[i], bkl_brightness);
	37
	38	priv->enabled = true;
	39	}
	40
	41	static void led_bl_power_off(struct led_bl_data *priv)
	42	{
	43	int i;
	44
	45	if (!priv->enabled)
	46	return;
	47
	48	for (i = 0; i < priv->nb_leds; i++)
	49	led_set_brightness(priv->leds[i], LED_OFF);
	50
	51	priv->enabled = false;
	52	}
	53
	54	static int led_bl_update_status(struct backlight_device *bl)
	55	{
	56	struct led_bl_data *priv = bl_get_data(bl);
	57	int brightness = bl->props.brightness;
	58
	59	if (bl->props.power != FB_BLANK_UNBLANK \|\|
	60	bl->props.fb_blank != FB_BLANK_UNBLANK \|\|
	61	bl->props.state & BL_CORE_FBBLANK)
	62	brightness = 0;
	63
	64	if (brightness > 0)
	65	led_bl_set_brightness(priv, brightness);
	66	else
	67	led_bl_power_off(priv);
	68
	69	return 0;
	70	}
	71
	72	static const struct backlight_ops led_bl_ops = {
	73	.update_status = led_bl_update_status,
	74	};
	75
	76	static int led_bl_get_leds(struct device *dev,
	77	struct led_bl_data *priv)
	78	{
	79	int i, nb_leds, ret;
	80	struct device_node *node = dev->of_node;
	81	struct led_classdev **leds;
	82	unsigned int max_brightness;
	83	unsigned int default_brightness;
	84
	85	ret = of_count_phandle_with_args(node, "leds", NULL);
	86	if (ret < 0) {
	87	dev_err(dev, "Unable to get led count\n");
	88	return -EINVAL;
	89	}
	90
	91	nb_leds = ret;
	92	if (nb_leds < 1) {
	93	dev_err(dev, "At least one LED must be specified!\n");
	94	return -EINVAL;
	95	}
	96
	97	leds = devm_kzalloc(dev, sizeof(struct led_classdev ) nb_leds,
	98	GFP_KERNEL);
	99	if (!leds)
	100	return -ENOMEM;
	101
	102	for (i = 0; i < nb_leds; i++) {
	103	leds[i] = devm_of_led_get(dev, i);
	104	if (IS_ERR(leds[i]))
	105	return PTR_ERR(leds[i]);
	106	}
	107
	108	/* check that the LEDs all have the same brightness range */
	109	max_brightness = leds[0]->max_brightness;
	110	for (i = 1; i < nb_leds; i++) {
	111	if (max_brightness != leds[i]->max_brightness) {
	112	dev_err(dev, "LEDs must have identical ranges\n");
	113	return -EINVAL;
	114	}
	115	}
	116
	117	/* get the default brightness from the first LED from the list */
	118	default_brightness = leds[0]->brightness;
	119
	120	priv->nb_leds = nb_leds;
	121	priv->leds = leds;
	122	priv->max_brightness = max_brightness;
	123	priv->default_brightness = default_brightness;
	124
	125	return 0;
	126	}
	127
	128	static int led_bl_parse_levels(struct device *dev,
	129	struct led_bl_data *priv)
	130	{
	131	struct device_node *node = dev->of_node;
	132	int num_levels;
	133	u32 value;
	134	int ret;
	135
	136	if (!node)
	137	return -ENODEV;
	138
	139	num_levels = of_property_count_u32_elems(node, "brightness-levels");
	140	if (num_levels > 1) {
	141	int i;
	142	unsigned int db;
	143	u32 *levels = NULL;
	144
	145	levels = devm_kzalloc(dev, sizeof(u32) * num_levels,
	146	GFP_KERNEL);
	147	if (!levels)
	148	return -ENOMEM;
	149
	150	ret = of_property_read_u32_array(node, "brightness-levels",
	151	levels,
	152	num_levels);
	153	if (ret < 0)
	154	return ret;
	155
	156	/*
	157	* Try to map actual LED brightness to backlight brightness
	158	* level
	159	*/
	160	db = priv->default_brightness;
	161	for (i = 0 ; i < num_levels; i++) {
	162	if ((i && db > levels[i-1]) && db <= levels[i])
	163	break;
	164	}
	165	priv->default_brightness = i;
	166	priv->max_brightness = num_levels - 1;
	167	priv->levels = levels;
	168	} else if (num_levels >= 0)
	169	dev_warn(dev, "Not enough levels defined\n");
	170
	171	ret = of_property_read_u32(node, "default-brightness-level", &value);
	172	if (!ret && value <= priv->max_brightness)
	173	priv->default_brightness = value;
	174	else if (!ret && value > priv->max_brightness)
	175	dev_warn(dev, "Invalid default brightness. Ignoring it\n");
	176
	177	return 0;
	178	}
	179
	180	static int led_bl_probe(struct platform_device *pdev)
	181	{
	182	struct backlight_properties props;
	183	struct led_bl_data *priv;
	184	int ret, i;
	185
	186	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	187	if (!priv)
	188	return -ENOMEM;
	189
	190	platform_set_drvdata(pdev, priv);
	191
	192	priv->dev = &pdev->dev;
	193
	194	ret = led_bl_get_leds(&pdev->dev, priv);
	195	if (ret)
	196	return ret;
	197
	198	ret = led_bl_parse_levels(&pdev->dev, priv);
	199	if (ret < 0) {
	200	dev_err(&pdev->dev, "Failed to parse DT data\n");
	201	return ret;
	202	}
	203
	204	memset(&props, 0, sizeof(struct backlight_properties));
	205	props.type = BACKLIGHT_RAW;
	206	props.max_brightness = priv->max_brightness;
	207	props.brightness = priv->default_brightness;
	208	props.power = (priv->default_brightness > 0) ? FB_BLANK_POWERDOWN :
	209	FB_BLANK_UNBLANK;
	210	priv->bl_dev = backlight_device_register(dev_name(&pdev->dev),
	211	&pdev->dev, priv, &led_bl_ops, &props);
	212	if (IS_ERR(priv->bl_dev)) {
	213	dev_err(&pdev->dev, "Failed to register backlight\n");
	214	return PTR_ERR(priv->bl_dev);
	215	}
	216
	217	for (i = 0; i < priv->nb_leds; i++)
	218	led_sysfs_disable(priv->leds[i]);
	219
	220	backlight_update_status(priv->bl_dev);
	221
	222	return 0;
	223	}
	224
	225	static int led_bl_remove(struct platform_device *pdev)
	226	{
	227	struct led_bl_data *priv = platform_get_drvdata(pdev);
	228	struct backlight_device *bl = priv->bl_dev;
	229	int i;
	230
	231	backlight_device_unregister(bl);
	232
	233	led_bl_power_off(priv);
	234	for (i = 0; i < priv->nb_leds; i++)
	235	led_sysfs_enable(priv->leds[i]);
	236
	237	return 0;
	238	}
	239
	240	static const struct of_device_id led_bl_of_match[] = {
	241	{ .compatible = "led-backlight" },
	242	{ }
	243	};
	244
	245	MODULE_DEVICE_TABLE(of, led_bl_of_match);
	246
	247	static struct platform_driver led_bl_driver = {
	248	.driver = {
	249	.name = "led-backlight",
	250	.of_match_table = of_match_ptr(led_bl_of_match),
	251	},
	252	.probe = led_bl_probe,
	253	.remove = led_bl_remove,
	254	};
	255
	256	module_platform_driver(led_bl_driver);
	257
	258	MODULE_DESCRIPTION("LED based Backlight Driver");
	259	MODULE_LICENSE("GPL");
	260	MODULE_ALIAS("platform:led-backlight");

drivers/video/console/vgacon.c+3−0

 static int vgacon_resize(struct vc_data *c, unsigned int width,
 			 unsigned int height, unsigned int user)
 {
+	if ((width << 1) * height > vga_vram_size)
+		return -EINVAL;
 	if (width % 2 || width > screen_info.orig_video_cols ||
 	    height > (screen_info.orig_video_lines * vga_default_font_height)/
 	    c->vc_font.height)

drivers/xen/xen-pciback/pciback.h+1−1

@@ -52,7 +52,7 @@ struct xen_pcibk_dev_data { · 51 unmodified lines
52	unsigned int ack_intr:1; /* .. and ACK-ing */	52	unsigned int ack_intr:1; /* .. and ACK-ing */
53	unsigned long handled;	53	unsigned long handled;
54	unsigned int irq; /* Saved in case device transitions to MSI/MSI-X */	54	unsigned int irq; /* Saved in case device transitions to MSI/MSI-X */
55	char irq_name[0]; /* xen-pcibk[000:04:00.0] */	55	char irq_name[]; /* xen-pcibk[000:04:00.0] */
56	};	56	};
57		57
58	/* Used by XenBus and xen_pcibk_ops.c */	58	/* Used by XenBus and xen_pcibk_ops.c */

drivers/xen/xenbus/xenbus_comms.c+4−0

 			req->msg.type = state.msg.type;
 			req->msg.len = state.msg.len;
 			req->body = state.body;
+			/* write body, then update state */
+			virt_wmb();
 			req->state = xb_req_state_got_reply;
 			req->cb(req);
 		} else
 	if (state.req->state == xb_req_state_aborted)
 		kfree(state.req);
 	else {
+		/* write err, then update state */
+		virt_wmb();
 		state.req->state = xb_req_state_got_reply;
 		wake_up(&state.req->wq);
 	}

drivers/xen/xenbus/xenbus_probe.c+5−5

@@ -239,9 +239,9 @@ int xenbus_dev_probe(struct device *_dev) · 238 unmodified lines
239	goto fail;	239	goto fail;
240	}	240	}
241		241
242	spin_lock(&dev->reclaim_lock);	242	down(&dev->reclaim_sem);
243	err = drv->probe(dev, id);	243	err = drv->probe(dev, id);
244	spin_unlock(&dev->reclaim_lock);	244	up(&dev->reclaim_sem);
245	if (err)	245	if (err)
246	goto fail_put;	246	goto fail_put;
247		247
@@ -271,9 +271,9 @@ int xenbus_dev_remove(struct device *_dev) · 23 unmodified lines
271	free_otherend_watch(dev);	271	free_otherend_watch(dev);
272		272
273	if (drv->remove) {	273	if (drv->remove) {
274	spin_lock(&dev->reclaim_lock);	274	down(&dev->reclaim_sem);
275	drv->remove(dev);	275	drv->remove(dev);
276	spin_unlock(&dev->reclaim_lock);	276	up(&dev->reclaim_sem);
277	}	277	}
278		278
279	module_put(drv->driver.owner);	279	module_put(drv->driver.owner);
@@ -473,7 +473,7 @@ int xenbus_probe_node(struct xen_bus_type *bus, · 193 unmodified lines
473	goto fail;	473	goto fail;
474		474
475	dev_set_name(&xendev->dev, "%s", devname);	475	dev_set_name(&xendev->dev, "%s", devname);
476	spin_lock_init(&xendev->reclaim_lock);	476	sema_init(&xendev->reclaim_sem, 1);
477		477
478	/* Register with generic device framework. */	478	/* Register with generic device framework. */
479	err = device_register(&xendev->dev);	479	err = device_register(&xendev->dev);

drivers/xen/xenbus/xenbus_probe_backend.c+3−2

 #include <linux/mm.h>
 #include <linux/notifier.h>
 #include <linux/export.h>
+#include <linux/semaphore.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 	drv = to_xenbus_driver(dev->driver);
 	if (drv && drv->reclaim_memory) {
 		xdev = to_xenbus_device(dev);
-		if (!spin_trylock(&xdev->reclaim_lock))
+		if (down_trylock(&xdev->reclaim_sem))
 			return 0;
 		drv->reclaim_memory(xdev);
-		spin_unlock(&xdev->reclaim_lock);
+		up(&xdev->reclaim_sem);
 	}
 	return 0;
 }

drivers/xen/xenbus/xenbus_xs.c+6−3

 static bool test_reply(struct xb_req_data *req)
 {
-	if (req->state == xb_req_state_got_reply || !xenbus_ok())
+	if (req->state == xb_req_state_got_reply || !xenbus_ok()) {
+		/* read req->state before all other fields */
+		virt_rmb();
 		return true;
+	}
 	/* Make sure to reread req->state each time. */
 	barrier();
 static void *read_reply(struct xb_req_data *req)
 {
-	while (req->state != xb_req_state_got_reply) {
+	do {
 		wait_event(req->wq, test_reply(req));
 		if (!xenbus_ok())
 		if (req->err)
 			return ERR_PTR(req->err);
-	}
+	} while (req->state != xb_req_state_got_reply);
 	return req->body;
 }

fs/btrfs/inode.c+3−1

 {
 	struct btrfs_io_bio *io_bio = btrfs_io_bio(bio);
 	struct btrfs_io_bio *orig_io_bio = btrfs_io_bio(dip->orig_bio);
+	u16 csum_size;
 	blk_status_t ret;
 	/*
 	file_offset -= dip->logical_offset;
 	file_offset >>= inode->i_sb->s_blocksize_bits;
-	io_bio->csum = (u8 *)(((u32 *)orig_io_bio->csum) + file_offset);
+	csum_size = btrfs_super_csum_size(btrfs_sb(inode->i_sb)->super_copy);
+	io_bio->csum = orig_io_bio->csum + csum_size * file_offset;
 	return 0;
 }

fs/cifs/cifs_dfs_ref.c+2−0

@@ -324,6 +324,8 @@ static struct vfsmount cifs_dfs_do_automount(struct dentry mntpt) · 323 unmodified lines
324	if (full_path == NULL)	324	if (full_path == NULL)
325	goto cdda_exit;	325	goto cdda_exit;
326		326
		327	convert_delimiter(full_path, '\\');
		328
327	cifs_dbg(FYI, "%s: full_path: %s\n", __func__, full_path);	329	cifs_dbg(FYI, "%s: full_path: %s\n", __func__, full_path);
328		330
329	if (!cifs_sb_master_tlink(cifs_sb)) {	331	if (!cifs_sb_master_tlink(cifs_sb)) {

fs/cifs/cifsfs.c+2−0

@@ -530,6 +530,8 @@ cifs_show_options(struct seq_file s, struct dentry root) · 529 unmodified lines
530		530
531	if (tcon->seal)	531	if (tcon->seal)
532	seq_puts(s, ",seal");	532	seq_puts(s, ",seal");
		533	else if (tcon->ses->server->ignore_signature)
		534	seq_puts(s, ",signloosely");
533	if (tcon->nocase)	535	if (tcon->nocase)
534	seq_puts(s, ",nocase");	536	seq_puts(s, ",nocase");
535	if (tcon->local_lease)	537	if (tcon->local_lease)

fs/cifs/cifsglob.h+7−0

 	__u64 volatile_fid;	/* volatile file id for smb2 */
 	__u8 lease_key[SMB2_LEASE_KEY_SIZE];	/* lease key for smb2 */
 	__u8 create_guid[16];
+	__u32 access;
 	struct cifs_pending_open *pending_open;
 	unsigned int epoch;
 #ifdef CONFIG_CIFS_DEBUG2
 	return false;
 }
+/* cifs_get_writable_file() flags */
+#define FIND_WR_ANY         0
+#define FIND_WR_FSUID_ONLY  1
+#define FIND_WR_WITH_DELETE 2
 #define   MID_FREE 0
 #define   MID_REQUEST_ALLOCATED 1
 #define   MID_REQUEST_SUBMITTED 2

fs/cifs/cifsproto.h+3−2

 extern bool is_size_safe_to_change(struct cifsInodeInfo *, __u64 eof);
 extern void cifs_update_eof(struct cifsInodeInfo *cifsi, loff_t offset,
 			    unsigned int bytes_written);
-extern struct cifsFileInfo *find_writable_file(struct cifsInodeInfo *, bool);
+extern struct cifsFileInfo *find_writable_file(struct cifsInodeInfo *, int);
 extern int cifs_get_writable_file(struct cifsInodeInfo *cifs_inode,
-				  bool fsuid_only,
+				  int flags,
 				  struct cifsFileInfo **ret_file);
 extern int cifs_get_writable_path(struct cifs_tcon *tcon, const char *name,
+				  int flags,
 				  struct cifsFileInfo **ret_file);
 extern struct cifsFileInfo *find_readable_file(struct cifsInodeInfo *, bool);
 extern int cifs_get_readable_path(struct cifs_tcon *tcon, const char *name,

fs/cifs/cifssmb.c+2−1

 	*oplock = rsp->OplockLevel;
 	/* cifs fid stays in le */
 	oparms->fid->netfid = rsp->Fid;
+	oparms->fid->access = desired_access;
 	/* Let caller know file was created so we can set the mode. */
 	/* Do we care about the CreateAction in any other cases? */
 		wdata2->tailsz = tailsz;
 		wdata2->bytes = cur_len;
-		rc = cifs_get_writable_file(CIFS_I(inode), false,
+		rc = cifs_get_writable_file(CIFS_I(inode), FIND_WR_ANY,
 					    &wdata2->cfile);
 		if (!wdata2->cfile) {
 			cifs_dbg(VFS, "No writable handle to retry writepages rc=%d\n",

fs/cifs/file.c+12−7

@@ -1958,7 +1958,7 @@ struct cifsFileInfo find_readable_file(struct cifsInodeInfo cifs_inode, · 1957 unmodified lines
1958		1958
1959	/* Return -EBADF if no handle is found and general rc otherwise */	1959	/* Return -EBADF if no handle is found and general rc otherwise */
1960	int	1960	int
1961	cifs_get_writable_file(struct cifsInodeInfo *cifs_inode, bool fsuid_only,	1961	cifs_get_writable_file(struct cifsInodeInfo *cifs_inode, int flags,
1962	struct cifsFileInfo **ret_file)	1962	struct cifsFileInfo **ret_file)
1963	{	1963	{
1964	struct cifsFileInfo open_file, inv_file = NULL;	1964	struct cifsFileInfo open_file, inv_file = NULL;
@@ -1966,7 +1966,8 @@ cifs_get_writable_file(struct cifsInodeInfo *cifs_inode, bool fsuid_only, · 1 unmodified line
1966	bool any_available = false;	1966	bool any_available = false;
1967	int rc = -EBADF;	1967	int rc = -EBADF;
1968	unsigned int refind = 0;	1968	unsigned int refind = 0;
1969		1969	bool fsuid_only = flags & FIND_WR_FSUID_ONLY;
		1970	bool with_delete = flags & FIND_WR_WITH_DELETE;
1970	*ret_file = NULL;	1971	*ret_file = NULL;
1971		1972
1972	/*	1973	/*
@@ -1998,6 +1999,8 @@ refind_writable: · 25 unmodified lines
1998	continue;	1999	continue;
1999	if (fsuid_only && !uid_eq(open_file->uid, current_fsuid()))	2000	if (fsuid_only && !uid_eq(open_file->uid, current_fsuid()))
2000	continue;	2001	continue;
		2002	if (with_delete && !(open_file->fid.access & DELETE))
		2003	continue;
2001	if (OPEN_FMODE(open_file->f_flags) & FMODE_WRITE) {	2004	if (OPEN_FMODE(open_file->f_flags) & FMODE_WRITE) {
2002	if (!open_file->invalidHandle) {	2005	if (!open_file->invalidHandle) {
2003	/* found a good writable file */	2006	/* found a good writable file */
@@ -2045,12 +2048,12 @@ refind_writable: · 41 unmodified lines
2045	}	2048	}
2046		2049
2047	struct cifsFileInfo *	2050	struct cifsFileInfo *
2048	find_writable_file(struct cifsInodeInfo *cifs_inode, bool fsuid_only)	2051	find_writable_file(struct cifsInodeInfo *cifs_inode, int flags)
2049	{	2052	{
2050	struct cifsFileInfo *cfile;	2053	struct cifsFileInfo *cfile;
2051	int rc;	2054	int rc;
2052		2055
2053	rc = cifs_get_writable_file(cifs_inode, fsuid_only, &cfile);	2056	rc = cifs_get_writable_file(cifs_inode, flags, &cfile);
2054	if (rc)	2057	if (rc)
2055	cifs_dbg(FYI, "couldn't find writable handle rc=%d", rc);	2058	cifs_dbg(FYI, "couldn't find writable handle rc=%d", rc);
2056		2059
@@ -2059,6 +2062,7 @@ find_writable_file(struct cifsInodeInfo *cifs_inode, bool fsuid_only) · 2 unmodified lines
2059		2062
2060	int	2063	int
2061	cifs_get_writable_path(struct cifs_tcon tcon, const char name,	2064	cifs_get_writable_path(struct cifs_tcon tcon, const char name,
		2065	int flags,
2062	struct cifsFileInfo **ret_file)	2066	struct cifsFileInfo **ret_file)
2063	{	2067	{
2064	struct list_head *tmp;	2068	struct list_head *tmp;
@@ -2085,7 +2089,7 @@ cifs_get_writable_path(struct cifs_tcon tcon, const char name, · 20 unmodified lines
2085	kfree(full_path);	2089	kfree(full_path);
2086	cinode = CIFS_I(d_inode(cfile->dentry));	2090	cinode = CIFS_I(d_inode(cfile->dentry));
2087	spin_unlock(&tcon->open_file_lock);	2091	spin_unlock(&tcon->open_file_lock);
2088	return cifs_get_writable_file(cinode, 0, ret_file);	2092	return cifs_get_writable_file(cinode, flags, ret_file);
2089	}	2093	}
2090		2094
2091	spin_unlock(&tcon->open_file_lock);	2095	spin_unlock(&tcon->open_file_lock);
@@ -2162,7 +2166,8 @@ static int cifs_partialpagewrite(struct page *page, unsigned from, unsigned to) · 70 unmodified lines
2162	if (mapping->host->i_size - offset < (loff_t)to)	2166	if (mapping->host->i_size - offset < (loff_t)to)
2163	to = (unsigned)(mapping->host->i_size - offset);	2167	to = (unsigned)(mapping->host->i_size - offset);
2164		2168
2165	rc = cifs_get_writable_file(CIFS_I(mapping->host), false, &open_file);	2169	rc = cifs_get_writable_file(CIFS_I(mapping->host), FIND_WR_ANY,
		2170	&open_file);
2166	if (!rc) {	2171	if (!rc) {
2167	bytes_written = cifs_write(open_file, open_file->pid,	2172	bytes_written = cifs_write(open_file, open_file->pid,
2168	write_data, to - from, &offset);	2173	write_data, to - from, &offset);
@@ -2355,7 +2360,7 @@ retry: · 186 unmodified lines
2355	if (cfile)	2360	if (cfile)
2356	cifsFileInfo_put(cfile);	2361	cifsFileInfo_put(cfile);
2357		2362
2358	rc = cifs_get_writable_file(CIFS_I(inode), false, &cfile);	2363	rc = cifs_get_writable_file(CIFS_I(inode), FIND_WR_ANY, &cfile);
2359		2364
2360	/* in case of an error store it to return later */	2365	/* in case of an error store it to return later */
2361	if (rc)	2366	if (rc)

fs/cifs/inode.c+10−6

@@ -653,8 +653,8 @@ cifs_all_info_to_fattr(struct cifs_fattr fattr, FILE_ALL_INFO info, · 652 unmodified lines
653	*/	653	*/
654	if ((fattr->cf_nlink < 1) && !tcon->unix_ext &&	654	if ((fattr->cf_nlink < 1) && !tcon->unix_ext &&
655	!info->DeletePending) {	655	!info->DeletePending) {
656	cifs_dbg(1, "bogus file nlink value %u\n",	656	cifs_dbg(VFS, "bogus file nlink value %u\n",
657	fattr->cf_nlink);	657	fattr->cf_nlink);
658	fattr->cf_flags \|= CIFS_FATTR_UNKNOWN_NLINK;	658	fattr->cf_flags \|= CIFS_FATTR_UNKNOWN_NLINK;
659	}	659	}
660	}	660	}
@@ -2073,6 +2073,7 @@ int cifs_revalidate_dentry_attr(struct dentry *dentry) · 1412 unmodified lines
2073	struct inode *inode = d_inode(dentry);	2073	struct inode *inode = d_inode(dentry);
2074	struct super_block *sb = dentry->d_sb;	2074	struct super_block *sb = dentry->d_sb;
2075	char *full_path = NULL;	2075	char *full_path = NULL;
		2076	int count = 0;
2076		2077
2077	if (inode == NULL)	2078	if (inode == NULL)
2078	return -ENOENT;	2079	return -ENOENT;
@@ -2094,15 +2095,18 @@ int cifs_revalidate_dentry_attr(struct dentry *dentry) · 15 unmodified lines
2094	full_path, inode, inode->i_count.counter,	2095	full_path, inode, inode->i_count.counter,
2095	dentry, cifs_get_time(dentry), jiffies);	2096	dentry, cifs_get_time(dentry), jiffies);
2096		2097
		2098	again:
2097	if (cifs_sb_master_tcon(CIFS_SB(sb))->unix_ext)	2099	if (cifs_sb_master_tcon(CIFS_SB(sb))->unix_ext)
2098	rc = cifs_get_inode_info_unix(&inode, full_path, sb, xid);	2100	rc = cifs_get_inode_info_unix(&inode, full_path, sb, xid);
2099	else	2101	else
2100	rc = cifs_get_inode_info(&inode, full_path, NULL, sb,	2102	rc = cifs_get_inode_info(&inode, full_path, NULL, sb,
2101	xid, NULL);	2103	xid, NULL);
2102		2104	if (rc == -EAGAIN && count++ < 10)
		2105	goto again;
2103	out:	2106	out:
2104	kfree(full_path);	2107	kfree(full_path);
2105	free_xid(xid);	2108	free_xid(xid);
		2109
2106	return rc;	2110	return rc;
2107	}	2111	}
2108		2112
@@ -2278,7 +2282,7 @@ cifs_set_file_size(struct inode inode, struct iattr attrs, · 169 unmodified lines
2278	* writebehind data than the SMB timeout for the SetPathInfo	2282	* writebehind data than the SMB timeout for the SetPathInfo
2279	* request would allow	2283	* request would allow
2280	*/	2284	*/
2281	open_file = find_writable_file(cifsInode, true);	2285	open_file = find_writable_file(cifsInode, FIND_WR_FSUID_ONLY);
2282	if (open_file) {	2286	if (open_file) {
2283	tcon = tlink_tcon(open_file->tlink);	2287	tcon = tlink_tcon(open_file->tlink);
2284	server = tcon->ses->server;	2288	server = tcon->ses->server;
@@ -2428,7 +2432,7 @@ cifs_setattr_unix(struct dentry direntry, struct iattr attrs) · 143 unmodified lines
2428	args->ctime = NO_CHANGE_64;	2432	args->ctime = NO_CHANGE_64;
2429		2433
2430	args->device = 0;	2434	args->device = 0;
2431	open_file = find_writable_file(cifsInode, true);	2435	open_file = find_writable_file(cifsInode, FIND_WR_FSUID_ONLY);
2432	if (open_file) {	2436	if (open_file) {
2433	u16 nfid = open_file->fid.netfid;	2437	u16 nfid = open_file->fid.netfid;
2434	u32 npid = open_file->pid;	2438	u32 npid = open_file->pid;
@@ -2531,7 +2535,7 @@ cifs_setattr_nounix(struct dentry direntry, struct iattr attrs) · 96 unmodified lines
2531	rc = 0;	2535	rc = 0;
2532		2536
2533	if (attrs->ia_valid & ATTR_MTIME) {	2537	if (attrs->ia_valid & ATTR_MTIME) {
2534	rc = cifs_get_writable_file(cifsInode, false, &wfile);	2538	rc = cifs_get_writable_file(cifsInode, FIND_WR_ANY, &wfile);
2535	if (!rc) {	2539	if (!rc) {
2536	tcon = tlink_tcon(wfile->tlink);	2540	tcon = tlink_tcon(wfile->tlink);
2537	rc = tcon->ses->server->ops->flush(xid, tcon, &wfile->fid);	2541	rc = tcon->ses->server->ops->flush(xid, tcon, &wfile->fid);

fs/cifs/smb1ops.c+1−1

@@ -766,7 +766,7 @@ smb_set_file_info(struct inode inode, const char full_path, · 765 unmodified lines
766	struct cifs_tcon *tcon;	766	struct cifs_tcon *tcon;
767		767
768	/* if the file is already open for write, just use that fileid */	768	/* if the file is already open for write, just use that fileid */
769	open_file = find_writable_file(cinode, true);	769	open_file = find_writable_file(cinode, FIND_WR_FSUID_ONLY);
770	if (open_file) {	770	if (open_file) {
771	fid.netfid = open_file->fid.netfid;	771	fid.netfid = open_file->fid.netfid;
772	netpid = open_file->pid;	772	netpid = open_file->pid;

fs/cifs/smb2inode.c+2−2

@@ -521,7 +521,7 @@ smb2_mkdir_setinfo(struct inode inode, const char name, · 520 unmodified lines
521	cifs_i = CIFS_I(inode);	521	cifs_i = CIFS_I(inode);
522	dosattrs = cifs_i->cifsAttrs \| ATTR_READONLY;	522	dosattrs = cifs_i->cifsAttrs \| ATTR_READONLY;
523	data.Attributes = cpu_to_le32(dosattrs);	523	data.Attributes = cpu_to_le32(dosattrs);
524	cifs_get_writable_path(tcon, name, &cfile);	524	cifs_get_writable_path(tcon, name, FIND_WR_ANY, &cfile);
525	tmprc = smb2_compound_op(xid, tcon, cifs_sb, name,	525	tmprc = smb2_compound_op(xid, tcon, cifs_sb, name,
526	FILE_WRITE_ATTRIBUTES, FILE_CREATE,	526	FILE_WRITE_ATTRIBUTES, FILE_CREATE,
527	CREATE_NOT_FILE, ACL_NO_MODE,	527	CREATE_NOT_FILE, ACL_NO_MODE,
@@ -577,7 +577,7 @@ smb2_rename_path(const unsigned int xid, struct cifs_tcon *tcon, · 49 unmodified lines
577	{	577	{
578	struct cifsFileInfo *cfile;	578	struct cifsFileInfo *cfile;
579		579
580	cifs_get_writable_path(tcon, from_name, &cfile);	580	cifs_get_writable_path(tcon, from_name, FIND_WR_WITH_DELETE, &cfile);
581		581
582	return smb2_set_path_attr(xid, tcon, from_name, to_name,	582	return smb2_set_path_attr(xid, tcon, from_name, to_name,
583	cifs_sb, DELETE, SMB2_OP_RENAME, cfile);	583	cifs_sb, DELETE, SMB2_OP_RENAME, cfile);

fs/cifs/smb2ops.c+2−1

 	cfile->fid.persistent_fid = fid->persistent_fid;
 	cfile->fid.volatile_fid = fid->volatile_fid;
+	cfile->fid.access = fid->access;
 #ifdef CONFIG_CIFS_DEBUG2
 	cfile->fid.mid = fid->mid;
 #endif /* CIFS_DEBUG2 */
 	 * some servers (Windows2016) will not reflect recent writes in
 	 * QUERY_ALLOCATED_RANGES until SMB2_flush is called.
 	 */
-	wrcfile = find_writable_file(cifsi, false);
+	wrcfile = find_writable_file(cifsi, FIND_WR_ANY);
 	if (wrcfile) {
 		filemap_write_and_wait(inode->i_mapping);
 		smb2_flush_file(xid, tcon, &wrcfile->fid);

fs/cifs/smb2pdu.c+1−0

@@ -2771,6 +2771,7 @@ SMB2_open(const unsigned int xid, struct cifs_open_parms oparms, __le16 path, · 2770 unmodified lines
2771	atomic_inc(&tcon->num_remote_opens);	2771	atomic_inc(&tcon->num_remote_opens);
2772	oparms->fid->persistent_fid = rsp->PersistentFileId;	2772	oparms->fid->persistent_fid = rsp->PersistentFileId;
2773	oparms->fid->volatile_fid = rsp->VolatileFileId;	2773	oparms->fid->volatile_fid = rsp->VolatileFileId;
		2774	oparms->fid->access = oparms->desired_access;
2774	#ifdef CONFIG_CIFS_DEBUG2	2775	#ifdef CONFIG_CIFS_DEBUG2
2775	oparms->fid->mid = le64_to_cpu(rsp->sync_hdr.MessageId);	2776	oparms->fid->mid = le64_to_cpu(rsp->sync_hdr.MessageId);
2776	#endif /* CIFS_DEBUG2 */	2777	#endif /* CIFS_DEBUG2 */

fs/debugfs/file.c+4−13

  * This function creates a file in debugfs with the given name that reports
  * the names and values of a set of 32-bit registers. If the @mode variable
  * is so set it can be read from. Writing is not supported.
- *
- * This function will return a pointer to a dentry if it succeeds.  This
- * pointer must be passed to the debugfs_remove() function when the file is
- * to be removed (no automatic cleanup happens if your module is unloaded,
- * you are responsible here.)  If an error occurs, ERR_PTR(-ERROR) will be
- * returned.
- *
- * If debugfs is not enabled in the kernel, the value ERR_PTR(-ENODEV) will
- * be returned.
  */
-struct dentry *debugfs_create_regset32(const char *name, umode_t mode,
+void debugfs_create_regset32(const char *name, umode_t mode,
-				       struct dentry *parent,
+			     struct dentry *parent,
-				       struct debugfs_regset32 *regset)
+			     struct debugfs_regset32 *regset)
 {
-	return debugfs_create_file(name, mode, parent, regset, &fops_regset32);
+	debugfs_create_file(name, mode, parent, regset, &fops_regset32);
 }
 EXPORT_SYMBOL_GPL(debugfs_create_regset32);

fs/fat/inode.c+7−12

 		return NULL;
 	init_rwsem(&ei->truncate_lock);
+	/* Zeroing to allow iput() even if partial initialized inode. */
+	ei->mmu_private = 0;
+	ei->i_start = 0;
+	ei->i_logstart = 0;
+	ei->i_attrs = 0;
+	ei->i_pos = 0;
 	return &ei->vfs_inode;
 }
 	return 0;
 }
-static void fat_dummy_inode_init(struct inode *inode)
-{
-	/* Initialize this dummy inode to work as no-op. */
-	MSDOS_I(inode)->mmu_private = 0;
-	MSDOS_I(inode)->i_start = 0;
-	MSDOS_I(inode)->i_logstart = 0;
-	MSDOS_I(inode)->i_attrs = 0;
-	MSDOS_I(inode)->i_pos = 0;
-}
 static int fat_read_root(struct inode *inode)
 {
 	struct msdos_sb_info *sbi = MSDOS_SB(inode->i_sb);
 	fat_inode = new_inode(sb);
 	if (!fat_inode)
 		goto out_fail;
-	fat_dummy_inode_init(fat_inode);
 	sbi->fat_inode = fat_inode;
 	fsinfo_inode = new_inode(sb);
 	if (!fsinfo_inode)
 		goto out_fail;
-	fat_dummy_inode_init(fsinfo_inode);
 	fsinfo_inode->i_ino = MSDOS_FSINFO_INO;
 	sbi->fsinfo_inode = fsinfo_inode;
 	insert_inode_hash(fsinfo_inode);

fs/fcntl.c+4−2

 		return;
 	switch (signum) {
-		kernel_siginfo_t si;
+		default: {
-		default:
+			kernel_siginfo_t si;
 			/* Queue a rt signal with the appropriate fd as its
 			   value.  We use SI_SIGIO as the source, not
 			   SI_KERNEL, since kernel signals always get
 			si.si_fd    = fd;
 			if (!do_send_sig_info(signum, &si, p, type))
 				break;
+		}
 		/* fall-through - fall back on the old plain SIGIO signal */
 		case 0:
 			do_send_sig_info(SIGIO, SEND_SIG_PRIV, p, type);

fs/io-wq.c+15−43

 		if (worker->mm)
 			work->flags |= IO_WQ_WORK_HAS_MM;
-		if (wq->get_work && !(work->flags & IO_WQ_WORK_INTERNAL)) {
+		if (wq->get_work) {
 			put_work = work;
 			wq->get_work(work);
 		}
 	return true;
 }
+static void io_run_cancel(struct io_wq_work *work)
+{
+	do {
+		struct io_wq_work *old_work = work;
+		work->flags |= IO_WQ_WORK_CANCEL;
+		work->func(&work);
+		work = (work == old_work) ? NULL : work;
+	} while (work);
+}
 static void io_wqe_enqueue(struct io_wqe *wqe, struct io_wq_work *work)
 {
 	struct io_wqe_acct *acct = io_work_get_acct(wqe, work);
 	 * It's close enough to not be an issue, fork() has the same delay.
 	 */
 	if (unlikely(!io_wq_can_queue(wqe, acct, work))) {
-		work->flags |= IO_WQ_WORK_CANCEL;
+		io_run_cancel(work);
-		work->func(&work);
 		return;
 	}
 	spin_unlock_irqrestore(&wqe->lock, flags);
 	if (found) {
-		work->flags |= IO_WQ_WORK_CANCEL;
+		io_run_cancel(work);
-		work->func(&work);
 		return IO_WQ_CANCEL_OK;
 	}
 	spin_unlock_irqrestore(&wqe->lock, flags);
 	if (found) {
-		work->flags |= IO_WQ_WORK_CANCEL;
+		io_run_cancel(work);
-		work->func(&work);
 		return IO_WQ_CANCEL_OK;
 	}
 	return ret;
 }
-struct io_wq_flush_data {
-	struct io_wq_work work;
-	struct completion done;
-};
-static void io_wq_flush_func(struct io_wq_work **workptr)
-{
-	struct io_wq_work *work = *workptr;
-	struct io_wq_flush_data *data;
-	data = container_of(work, struct io_wq_flush_data, work);
-	complete(&data->done);
-}
-/*
- * Doesn't wait for previously queued work to finish. When this completes,
- * it just means that previously queued work was started.
- */
-void io_wq_flush(struct io_wq *wq)
-{
-	struct io_wq_flush_data data;
-	int node;
-	for_each_node(node) {
-		struct io_wqe *wqe = wq->wqes[node];
-		if (!node_online(node))
-			continue;
-		init_completion(&data.done);
-		INIT_IO_WORK(&data.work, io_wq_flush_func);
-		data.work.flags |= IO_WQ_WORK_INTERNAL;
-		io_wqe_enqueue(wqe, &data.work);
-		wait_for_completion(&data.done);
-	}
-}
 struct io_wq *io_wq_create(unsigned bounded, struct io_wq_data *data)
 {
 	int ret = -ENOMEM, node;

fs/io-wq.h+0−2

 	IO_WQ_WORK_HAS_MM	= 2,
 	IO_WQ_WORK_HASHED	= 4,
 	IO_WQ_WORK_UNBOUND	= 32,
-	IO_WQ_WORK_INTERNAL	= 64,
 	IO_WQ_WORK_CB		= 128,
 	IO_WQ_WORK_NO_CANCEL	= 256,
 	IO_WQ_WORK_CONCURRENT	= 512,
 void io_wq_enqueue(struct io_wq *wq, struct io_wq_work *work);
 void io_wq_enqueue_hashed(struct io_wq *wq, struct io_wq_work *work, void *val);
-void io_wq_flush(struct io_wq *wq);
 void io_wq_cancel_all(struct io_wq *wq);
 enum io_wq_cancel io_wq_cancel_work(struct io_wq *wq, struct io_wq_work *cwork);

fs/io_uring.c+23−2

 	struct llist_head		put_llist;
 	struct work_struct		ref_work;
 	struct completion		done;
+	struct rcu_head			rcu;
 };
 struct io_ring_ctx {
 	if (ret != -1) {
 		atomic_inc(&req->ctx->cq_timeouts);
 		list_del_init(&req->list);
+		req->flags |= REQ_F_COMP_LOCKED;
 		io_cqring_fill_event(req, 0);
 		io_put_req(req);
 	}
 	complete(&data->done);
 }
+static void __io_file_ref_exit_and_free(struct rcu_head *rcu)
+{
+	struct fixed_file_data *data = container_of(rcu, struct fixed_file_data,
+							rcu);
+	percpu_ref_exit(&data->refs);
+	kfree(data);
+}
+static void io_file_ref_exit_and_free(struct rcu_head *rcu)
+{
+	/*
+	 * We need to order our exit+free call against the potentially
+	 * existing call_rcu() for switching to atomic. One way to do that
+	 * is to have this rcu callback queue the final put and free, as we
+	 * could otherwise have a pre-existing atomic switch complete _after_
+	 * the free callback we queued.
+	 */
+	call_rcu(rcu, __io_file_ref_exit_and_free);
+}
 static int io_sqe_files_unregister(struct io_ring_ctx *ctx)
 {
 	struct fixed_file_data *data = ctx->file_data;
 	flush_work(&data->ref_work);
 	wait_for_completion(&data->done);
 	io_ring_file_ref_flush(data);
-	percpu_ref_exit(&data->refs);
 	__io_sqe_files_unregister(ctx);
 	nr_tables = DIV_ROUND_UP(ctx->nr_user_files, IORING_MAX_FILES_TABLE);
 	for (i = 0; i < nr_tables; i++)
 		kfree(data->table[i].files);
 	kfree(data->table);
-	kfree(data);
+	call_rcu(&data->rcu, io_file_ref_exit_and_free);
 	ctx->file_data = NULL;
 	ctx->nr_user_files = 0;
 	return 0;

fs/locks.c+0−14

@@ -753,20 +753,6 @@ int locks_delete_block(struct file_lock *waiter) · 752 unmodified lines
753	{	753	{
754	int status = -ENOENT;	754	int status = -ENOENT;
755		755
756	/*
757	* If fl_blocker is NULL, it won't be set again as this thread
758	* "owns" the lock and is the only one that might try to claim
759	* the lock. So it is safe to test fl_blocker locklessly.
760	* Also if fl_blocker is NULL, this waiter is not listed on
761	* fl_blocked_requests for some lock, so no other request can
762	* be added to the list of fl_blocked_requests for this
763	* request. So if fl_blocker is NULL, it is safe to
764	* locklessly check if fl_blocked_requests is empty. If both
765	* of these checks succeed, there is no need to take the lock.
766	*/
767	if (waiter->fl_blocker == NULL &&
768	list_empty(&waiter->fl_blocked_requests))
769	return status;
770	spin_lock(&blocked_lock_lock);	756	spin_lock(&blocked_lock_lock);
771	if (waiter->fl_blocker)	757	if (waiter->fl_blocker)
772	status = 0;	758	status = 0;

include/drm/drm_gem_shmem_helper.h+5−0

 	 * The address are un-mapped when the count reaches zero.
 	 */
 	unsigned int vmap_use_count;
+	/**
+	 * @map_cached: map object cached (instead of using writecombine).
+	 */
+	bool map_cached;
 };
 #define to_drm_gem_shmem_obj(obj) \

include/linux/blkdev.h+0−1

@@ -1494,7 +1494,6 @@ static inline void put_dev_sector(Sector p) · 1493 unmodified lines
1494	}	1494	}
1495		1495
1496	int kblockd_schedule_work(struct work_struct *work);	1496	int kblockd_schedule_work(struct work_struct *work);
1497	int kblockd_schedule_work_on(int cpu, struct work_struct *work);
1498	int kblockd_mod_delayed_work_on(int cpu, struct delayed_work *dwork, unsigned long delay);	1497	int kblockd_mod_delayed_work_on(int cpu, struct delayed_work *dwork, unsigned long delay);
1499		1498
1500	#define MODULE_ALIAS_BLOCKDEV(major,minor) \	1499	#define MODULE_ALIAS_BLOCKDEV(major,minor) \

include/linux/debugfs.h+6−7

 				  struct dentry *parent,
 				  struct debugfs_blob_wrapper *blob);
-struct dentry *debugfs_create_regset32(const char *name, umode_t mode,
+void debugfs_create_regset32(const char *name, umode_t mode,
-				     struct dentry *parent,
+			     struct dentry *parent,
-				     struct debugfs_regset32 *regset);
+			     struct debugfs_regset32 *regset);
 void debugfs_print_regs32(struct seq_file *s, const struct debugfs_reg32 *regs,
 			  int nregs, void __iomem *base, char *prefix);
 	return ERR_PTR(-ENODEV);
 }
-static inline struct dentry *debugfs_create_regset32(const char *name,
+static inline void debugfs_create_regset32(const char *name, umode_t mode,
-				   umode_t mode, struct dentry *parent,
+					   struct dentry *parent,
-				   struct debugfs_regset32 *regset)
+					   struct debugfs_regset32 *regset)
 {
-	return ERR_PTR(-ENODEV);
 }
 static inline void debugfs_print_regs32(struct seq_file *s, const struct debugfs_reg32 *regs,

include/linux/device.h+11−0

@@ -798,6 +798,17 @@ static inline struct device_node dev_of_node(struct device dev) · 797 unmodified lines
798	return dev->of_node;	798	return dev->of_node;
799	}	799	}
800		800
		801	static inline bool dev_has_sync_state(struct device *dev)
		802	{
		803	if (!dev)
		804	return false;
		805	if (dev->driver && dev->driver->sync_state)
		806	return true;
		807	if (dev->bus && dev->bus->sync_state)
		808	return true;
		809	return false;
		810	}
		811
801	/*	812	/*
802	* High level routines for use by the bus drivers	813	* High level routines for use by the bus drivers
803	*/	814	*/

include/linux/mm.h+4−0

 #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_ARCH_HAS_SET_DIRECT_MAP)
 extern void __kernel_map_pages(struct page *page, int numpages, int enable);
+/*
+ * When called in DEBUG_PAGEALLOC context, the call should most likely be
+ * guarded by debug_pagealloc_enabled() or debug_pagealloc_enabled_static()
+ */
 static inline void
 kernel_map_pages(struct page *page, int numpages, int enable)
 {

include/linux/platform_data/spi-omap2-mcspi.h+1−0

@@ -11,6 +11,7 @@ struct omap2_mcspi_platform_config { · 10 unmodified lines
11	unsigned short num_cs;	11	unsigned short num_cs;
12	unsigned int regs_offset;	12	unsigned int regs_offset;
13	unsigned int pin_dir:1;	13	unsigned int pin_dir:1;
		14	size_t max_xfer_len;
14	};	15	};
15		16
16	struct omap2_mcspi_device_config {	17	struct omap2_mcspi_device_config {

include/sound/soc.h+1−1

@@ -1157,7 +1157,7 @@ struct snd_soc_pcm_runtime { · 1156 unmodified lines
1157	((i) < rtd->num_codecs) && ((dai) = rtd->codec_dais[i]); \	1157	((i) < rtd->num_codecs) && ((dai) = rtd->codec_dais[i]); \
1158	(i)++)	1158	(i)++)
1159	#define for_each_rtd_codec_dai_rollback(rtd, i, dai) \	1159	#define for_each_rtd_codec_dai_rollback(rtd, i, dai) \
1160	for (; ((--i) >= 0) && ((dai) = rtd->codec_dais[i]);)	1160	for (; (--(i) >= 0) && ((dai) = rtd->codec_dais[i]);)
1161		1161
1162	void snd_soc_close_delayed_work(struct snd_soc_pcm_runtime *rtd);	1162	void snd_soc_close_delayed_work(struct snd_soc_pcm_runtime *rtd);
1163		1163

include/uapi/linux/dm-ioctl.h+2−2

@@ -272,9 +272,9 @@ enum { · 271 unmodified lines
272	#define DM_DEV_SET_GEOMETRY _IOWR(DM_IOCTL, DM_DEV_SET_GEOMETRY_CMD, struct dm_ioctl)	272	#define DM_DEV_SET_GEOMETRY _IOWR(DM_IOCTL, DM_DEV_SET_GEOMETRY_CMD, struct dm_ioctl)
273		273
274	#define DM_VERSION_MAJOR 4	274	#define DM_VERSION_MAJOR 4
275	#define DM_VERSION_MINOR 41	275	#define DM_VERSION_MINOR 42
276	#define DM_VERSION_PATCHLEVEL 0	276	#define DM_VERSION_PATCHLEVEL 0
277	#define DM_VERSION_EXTRA "-ioctl (2019-09-16)"	277	#define DM_VERSION_EXTRA "-ioctl (2020-02-27)"
278		278
279	/* Status bits */	279	/* Status bits */
280	#define DM_READONLY_FLAG (1 << 0) /* In/Out */	280	#define DM_READONLY_FLAG (1 << 0) /* In/Out */

include/xen/interface/io/tpmif.h+1−1

@@ -46,7 +46,7 @@ struct vtpm_shared_page { · 45 unmodified lines
46	uint8_t pad;	46	uint8_t pad;
47		47
48	uint8_t nr_extra_pages; /* extra pages for long packets; may be zero */	48	uint8_t nr_extra_pages; /* extra pages for long packets; may be zero */
49	uint32_t extra_pages[0]; /* grant IDs; length in nr_extra_pages */	49	uint32_t extra_pages[]; /* grant IDs; length in nr_extra_pages */
50	};	50	};
51		51
52	#endif	52	#endif

include/xen/xenbus.h+2−1

 #include <linux/completion.h>
 #include <linux/init.h>
 #include <linux/slab.h>
+#include <linux/semaphore.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/grant_table.h>
 #include <xen/interface/io/xenbus.h>
 	enum xenbus_state state;
 	struct completion down;
 	struct work_struct work;
-	spinlock_t reclaim_lock;
+	struct semaphore reclaim_sem;
 };
 static inline struct xenbus_device *to_xenbus_device(struct device *dev)

kernel/exit.c+2−2

@@ -619,8 +619,8 @@ static void forget_original_parent(struct task_struct *father, · 618 unmodified lines
619	reaper = find_new_reaper(father, reaper);	619	reaper = find_new_reaper(father, reaper);
620	list_for_each_entry(p, &father->children, sibling) {	620	list_for_each_entry(p, &father->children, sibling) {
621	for_each_thread(p, t) {	621	for_each_thread(p, t) {
622	t->real_parent = reaper;	622	RCU_INIT_POINTER(t->real_parent, reaper);
623	BUG_ON((!t->ptrace) != (t->parent == father));	623	BUG_ON((!t->ptrace) != (rcu_access_pointer(t->parent) == father));
624	if (likely(!t->ptrace))	624	if (likely(!t->ptrace))
625	t->parent = t->real_parent;	625	t->parent = t->real_parent;
626	if (t->pdeath_signal)	626	if (t->pdeath_signal)

kernel/fork.c+1−1

@@ -1508,7 +1508,7 @@ static int copy_sighand(unsigned long clone_flags, struct task_struct *tsk) · 1507 unmodified lines
1508	return 0;	1508	return 0;
1509	}	1509	}
1510	sig = kmem_cache_alloc(sighand_cachep, GFP_KERNEL);	1510	sig = kmem_cache_alloc(sighand_cachep, GFP_KERNEL);
1511	rcu_assign_pointer(tsk->sighand, sig);	1511	RCU_INIT_POINTER(tsk->sighand, sig);
1512	if (!sig)	1512	if (!sig)
1513	return -ENOMEM;	1513	return -ENOMEM;
1514		1514

kernel/sched/fair.c+2−0

@@ -8337,6 +8337,8 @@ static inline void update_sg_wakeup_stats(struct sched_domain *sd, · 8336 unmodified lines
8337		8337
8338	sgs->group_capacity = group->sgc->capacity;	8338	sgs->group_capacity = group->sgc->capacity;
8339		8339
		8340	sgs->group_weight = group->group_weight;
		8341
8340	sgs->group_type = group_classify(sd->imbalance_pct, group, sgs);	8342	sgs->group_type = group_classify(sd->imbalance_pct, group, sgs);
8341		8343
8342	/*	8344	/*

kernel/trace/blktrace.c+4−1

 	}
 	ret = 0;
-	if (bt == NULL)
+	if (bt == NULL) {
 		ret = blk_trace_setup_queue(q, bdev);
+		bt = rcu_dereference_protected(q->blk_trace,
+				lockdep_is_held(&q->blk_trace_mutex));
+	}
 	if (ret == 0) {
 		if (attr == &dev_attr_act_mask)

mm/huge_memory.c+1−2

@@ -3043,8 +3043,7 @@ void set_pmd_migration_entry(struct page_vma_mapped_walk *pvmw, · 3042 unmodified lines
3043	return;	3043	return;
3044		3044
3045	flush_cache_range(vma, address, address + HPAGE_PMD_SIZE);	3045	flush_cache_range(vma, address, address + HPAGE_PMD_SIZE);
3046	pmdval = *pvmw->pmd;	3046	pmdval = pmdp_invalidate(vma, address, pvmw->pmd);
3047	pmdp_invalidate(vma, address, pvmw->pmd);
3048	if (pmd_dirty(pmdval))	3047	if (pmd_dirty(pmdval))
3049	set_page_dirty(page);	3048	set_page_dirty(page);
3050	entry = make_migration_entry(page, pmd_write(pmdval));	3049	entry = make_migration_entry(page, pmd_write(pmdval));

mm/memory.c+27−8

 	bool ret;
 	void *kaddr;
 	void __user *uaddr;
-	bool force_mkyoung;
+	bool locked = false;
 	struct vm_area_struct *vma = vmf->vma;
 	struct mm_struct *mm = vma->vm_mm;
 	unsigned long addr = vmf->address;
 	 * On architectures with software "accessed" bits, we would
 	 * take a double page fault, so mark it accessed here.
 	 */
-	force_mkyoung = arch_faults_on_old_pte() && !pte_young(vmf->orig_pte);
+	if (arch_faults_on_old_pte() && !pte_young(vmf->orig_pte)) {
-	if (force_mkyoung) {
 		pte_t entry;
 		vmf->pte = pte_offset_map_lock(mm, vmf->pmd, addr, &vmf->ptl);
+		locked = true;
 		if (!likely(pte_same(*vmf->pte, vmf->orig_pte))) {
 			/*
 			 * Other thread has already handled the fault
 	 * zeroes.
 	 */
 	if (__copy_from_user_inatomic(kaddr, uaddr, PAGE_SIZE)) {
+		if (locked)
+			goto warn;
+		/* Re-validate under PTL if the page is still mapped */
+		vmf->pte = pte_offset_map_lock(mm, vmf->pmd, addr, &vmf->ptl);
+		locked = true;
+		if (!likely(pte_same(*vmf->pte, vmf->orig_pte))) {
+			/* The PTE changed under us. Retry page fault. */
+			ret = false;
+			goto pte_unlock;
+		}
 		/*
-		 * Give a warn in case there can be some obscure
+		 * The same page can be mapped back since last copy attampt.
-		 * use-case
+		 * Try to copy again under PTL.
 		 */
-		WARN_ON_ONCE(1);
+		if (__copy_from_user_inatomic(kaddr, uaddr, PAGE_SIZE)) {
-		clear_page(kaddr);
+			/*
+			 * Give a warn in case there can be some obscure
+			 * use-case
+			 */
+warn:
+			WARN_ON_ONCE(1);
+			clear_page(kaddr);
+		}
 	}
 	ret = true;
 pte_unlock:
-	if (force_mkyoung)
+	if (locked)
 		pte_unmap_unlock(vmf->pte, vmf->ptl);
 	kunmap_atomic(kaddr);
 	flush_dcache_page(dst);

mm/memory_hotplug.c+7−1

 void generic_online_page(struct page *page, unsigned int order)
 {
-	kernel_map_pages(page, 1 << order, 1);
+	/*
+	 * Freeing the page with debug_pagealloc enabled will try to unmap it,
+	 * so we should map it first. This is better than introducing a special
+	 * case in page freeing fast path.
+	 */
+	if (debug_pagealloc_enabled_static())
+		kernel_map_pages(page, 1 << order, 1);
 	__free_pages_core(page, order);
 	totalram_pages_add(1UL << order);
 #ifdef CONFIG_HIGHMEM

mm/mprotect.c+36−2

@@ -161,6 +161,31 @@ static unsigned long change_pte_range(struct vm_area_struct vma, pmd_t pmd, · 160 unmodified lines
161	return pages;	161	return pages;
162	}	162	}
163		163
		164	/*
		165	* Used when setting automatic NUMA hinting protection where it is
		166	* critical that a numa hinting PMD is not confused with a bad PMD.
		167	*/
		168	static inline int pmd_none_or_clear_bad_unless_trans_huge(pmd_t *pmd)
		169	{
		170	pmd_t pmdval = pmd_read_atomic(pmd);
		171
		172	/* See pmd_none_or_trans_huge_or_clear_bad for info on barrier */
		173	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
		174	barrier();
		175	#endif
		176
		177	if (pmd_none(pmdval))
		178	return 1;
		179	if (pmd_trans_huge(pmdval))
		180	return 0;
		181	if (unlikely(pmd_bad(pmdval))) {
		182	pmd_clear_bad(pmd);
		183	return 1;
		184	}
		185
		186	return 0;
		187	}
		188
164	static inline unsigned long change_pmd_range(struct vm_area_struct *vma,	189	static inline unsigned long change_pmd_range(struct vm_area_struct *vma,
165	pud_t *pud, unsigned long addr, unsigned long end,	190	pud_t *pud, unsigned long addr, unsigned long end,
166	pgprot_t newprot, int dirty_accountable, int prot_numa)	191	pgprot_t newprot, int dirty_accountable, int prot_numa)
@@ -178,8 +203,17 @@ static inline unsigned long change_pmd_range(struct vm_area_struct *vma, · 11 unmodified lines
178	unsigned long this_pages;	203	unsigned long this_pages;
179		204
180	next = pmd_addr_end(addr, end);	205	next = pmd_addr_end(addr, end);
181	if (!is_swap_pmd(pmd) && !pmd_trans_huge(pmd) && !pmd_devmap(*pmd)	206
182	&& pmd_none_or_clear_bad(pmd))	207	/*
		208	* Automatic NUMA balancing walks the tables with mmap_sem
		209	* held for read. It's possible a parallel update to occur
		210	* between pmd_trans_huge() and a pmd_none_or_clear_bad()
		211	* check leading to a false positive and clearing.
		212	* Hence, it's necessary to atomically read the PMD value
		213	* for all the checks.
		214	*/
		215	if (!is_swap_pmd(pmd) && !pmd_devmap(pmd) &&
		216	pmd_none_or_clear_bad_unless_trans_huge(pmd))
183	goto next;	217	goto next;
184		218
185	/* invoke the mmu notifier if the pmd is populated */	219	/* invoke the mmu notifier if the pmd is populated */

mm/z3fold.c+0−1

@@ -41,7 +41,6 @@ · 40 unmodified lines
41	#include <linux/workqueue.h>	41	#include <linux/workqueue.h>
42	#include <linux/slab.h>	42	#include <linux/slab.h>
43	#include <linux/spinlock.h>	43	#include <linux/spinlock.h>
44	#include <linux/rwlock.h>
45	#include <linux/zpool.h>	44	#include <linux/zpool.h>
46	#include <linux/magic.h>	45	#include <linux/magic.h>
47		46

scripts/parse-maintainers.pl+0−0

File mode changed from 100644 to 100755.

sound/mips/sgio2audio.c+0−6

 static const struct snd_pcm_ops snd_sgio2audio_playback1_ops = {
 	.open =        snd_sgio2audio_playback1_open,
 	.close =       snd_sgio2audio_pcm_close,
-	.hw_params =   snd_sgio2audio_pcm_hw_params,
-	.hw_free =     snd_sgio2audio_pcm_hw_free,
 	.prepare =     snd_sgio2audio_pcm_prepare,
 	.trigger =     snd_sgio2audio_pcm_trigger,
 	.pointer =     snd_sgio2audio_pcm_pointer,
 static const struct snd_pcm_ops snd_sgio2audio_playback2_ops = {
 	.open =        snd_sgio2audio_playback2_open,
 	.close =       snd_sgio2audio_pcm_close,
-	.hw_params =   snd_sgio2audio_pcm_hw_params,
-	.hw_free =     snd_sgio2audio_pcm_hw_free,
 	.prepare =     snd_sgio2audio_pcm_prepare,
 	.trigger =     snd_sgio2audio_pcm_trigger,
 	.pointer =     snd_sgio2audio_pcm_pointer,
 static const struct snd_pcm_ops snd_sgio2audio_capture_ops = {
 	.open =        snd_sgio2audio_capture_open,
 	.close =       snd_sgio2audio_pcm_close,
-	.hw_params =   snd_sgio2audio_pcm_hw_params,
-	.hw_free =     snd_sgio2audio_pcm_hw_free,
 	.prepare =     snd_sgio2audio_pcm_prepare,
 	.trigger =     snd_sgio2audio_pcm_trigger,
 	.pointer =     snd_sgio2audio_pcm_pointer,

sound/pci/hda/patch_realtek.c+27−4

@@ -2447,6 +2447,7 @@ static const struct snd_pci_quirk alc882_fixup_tbl[] = { · 2446 unmodified lines
2447	SND_PCI_QUIRK(0x1071, 0x8258, "Evesham Voyaeger", ALC882_FIXUP_EAPD),	2447	SND_PCI_QUIRK(0x1071, 0x8258, "Evesham Voyaeger", ALC882_FIXUP_EAPD),
2448	SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte EP45-DS3/Z87X-UD3H", ALC889_FIXUP_FRONT_HP_NO_PRESENCE),	2448	SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte EP45-DS3/Z87X-UD3H", ALC889_FIXUP_FRONT_HP_NO_PRESENCE),
2449	SND_PCI_QUIRK(0x1458, 0xa0b8, "Gigabyte AZ370-Gaming", ALC1220_FIXUP_GB_DUAL_CODECS),	2449	SND_PCI_QUIRK(0x1458, 0xa0b8, "Gigabyte AZ370-Gaming", ALC1220_FIXUP_GB_DUAL_CODECS),
		2450	SND_PCI_QUIRK(0x1458, 0xa0cd, "Gigabyte X570 Aorus Master", ALC1220_FIXUP_CLEVO_P950),
2450	SND_PCI_QUIRK(0x1462, 0x1228, "MSI-GP63", ALC1220_FIXUP_CLEVO_P950),	2451	SND_PCI_QUIRK(0x1462, 0x1228, "MSI-GP63", ALC1220_FIXUP_CLEVO_P950),
2451	SND_PCI_QUIRK(0x1462, 0x1276, "MSI-GL73", ALC1220_FIXUP_CLEVO_P950),	2452	SND_PCI_QUIRK(0x1462, 0x1276, "MSI-GL73", ALC1220_FIXUP_CLEVO_P950),
2452	SND_PCI_QUIRK(0x1462, 0x1293, "MSI-GP65", ALC1220_FIXUP_CLEVO_P950),	2453	SND_PCI_QUIRK(0x1462, 0x1293, "MSI-GP65", ALC1220_FIXUP_CLEVO_P950),
@@ -5920,7 +5921,8 @@ enum { · 3467 unmodified lines
5920	ALC289_FIXUP_DUAL_SPK,	5921	ALC289_FIXUP_DUAL_SPK,
5921	ALC294_FIXUP_SPK2_TO_DAC1,	5922	ALC294_FIXUP_SPK2_TO_DAC1,
5922	ALC294_FIXUP_ASUS_DUAL_SPK,	5923	ALC294_FIXUP_ASUS_DUAL_SPK,
5923		5924	ALC285_FIXUP_THINKPAD_HEADSET_JACK,
		5925	ALC294_FIXUP_ASUS_HPE,
5924	};	5926	};
5925		5927
5926	static const struct hda_fixup alc269_fixups[] = {	5928	static const struct hda_fixup alc269_fixups[] = {
@@ -6684,6 +6686,8 @@ static const struct hda_fixup alc269_fixups[] = { · 757 unmodified lines
6684	[ALC285_FIXUP_SPEAKER2_TO_DAC1] = {	6686	[ALC285_FIXUP_SPEAKER2_TO_DAC1] = {
6685	.type = HDA_FIXUP_FUNC,	6687	.type = HDA_FIXUP_FUNC,
6686	.v.func = alc285_fixup_speaker2_to_dac1,	6688	.v.func = alc285_fixup_speaker2_to_dac1,
		6689	.chained = true,
		6690	.chain_id = ALC269_FIXUP_THINKPAD_ACPI
6687	},	6691	},
6688	[ALC256_FIXUP_DELL_INSPIRON_7559_SUBWOOFER] = {	6692	[ALC256_FIXUP_DELL_INSPIRON_7559_SUBWOOFER] = {
6689	.type = HDA_FIXUP_PINS,	6693	.type = HDA_FIXUP_PINS,
@@ -7040,7 +7044,23 @@ static const struct hda_fixup alc269_fixups[] = { · 350 unmodified lines
7040	.chained = true,	7044	.chained = true,
7041	.chain_id = ALC294_FIXUP_SPK2_TO_DAC1	7045	.chain_id = ALC294_FIXUP_SPK2_TO_DAC1
7042	},	7046	},
7043		7047	[ALC285_FIXUP_THINKPAD_HEADSET_JACK] = {
		7048	.type = HDA_FIXUP_FUNC,
		7049	.v.func = alc_fixup_headset_jack,
		7050	.chained = true,
		7051	.chain_id = ALC285_FIXUP_SPEAKER2_TO_DAC1
		7052	},
		7053	[ALC294_FIXUP_ASUS_HPE] = {
		7054	.type = HDA_FIXUP_VERBS,
		7055	.v.verbs = (const struct hda_verb[]) {
		7056	/* Set EAPD high */
		7057	{ 0x20, AC_VERB_SET_COEF_INDEX, 0x0f },
		7058	{ 0x20, AC_VERB_SET_PROC_COEF, 0x7774 },
		7059	{ }
		7060	},
		7061	.chained = true,
		7062	.chain_id = ALC294_FIXUP_ASUS_HEADSET_MIC
		7063	},
7044	};	7064	};
7045		7065
7046	static const struct snd_pci_quirk alc269_fixup_tbl[] = {	7066	static const struct snd_pci_quirk alc269_fixup_tbl[] = {
@@ -7115,6 +7135,8 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { · 68 unmodified lines
7115	SND_PCI_QUIRK(0x1028, 0x0935, "Dell", ALC274_FIXUP_DELL_AIO_LINEOUT_VERB),	7135	SND_PCI_QUIRK(0x1028, 0x0935, "Dell", ALC274_FIXUP_DELL_AIO_LINEOUT_VERB),
7116	SND_PCI_QUIRK(0x1028, 0x097e, "Dell Precision", ALC289_FIXUP_DUAL_SPK),	7136	SND_PCI_QUIRK(0x1028, 0x097e, "Dell Precision", ALC289_FIXUP_DUAL_SPK),
7117	SND_PCI_QUIRK(0x1028, 0x097d, "Dell Precision", ALC289_FIXUP_DUAL_SPK),	7137	SND_PCI_QUIRK(0x1028, 0x097d, "Dell Precision", ALC289_FIXUP_DUAL_SPK),
		7138	SND_PCI_QUIRK(0x1028, 0x098d, "Dell Precision", ALC233_FIXUP_ASUS_MIC_NO_PRESENCE),
		7139	SND_PCI_QUIRK(0x1028, 0x09bf, "Dell Precision", ALC233_FIXUP_ASUS_MIC_NO_PRESENCE),
7118	SND_PCI_QUIRK(0x1028, 0x164a, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE),	7140	SND_PCI_QUIRK(0x1028, 0x164a, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE),
7119	SND_PCI_QUIRK(0x1028, 0x164b, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE),	7141	SND_PCI_QUIRK(0x1028, 0x164b, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE),
7120	SND_PCI_QUIRK(0x103c, 0x1586, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC2),	7142	SND_PCI_QUIRK(0x103c, 0x1586, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC2),
@@ -7204,6 +7226,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { · 83 unmodified lines
7204	SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_FIXUP_STEREO_DMIC),	7226	SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_FIXUP_STEREO_DMIC),
7205	SND_PCI_QUIRK(0x1043, 0x17d1, "ASUS UX431FL", ALC294_FIXUP_ASUS_DUAL_SPK),	7227	SND_PCI_QUIRK(0x1043, 0x17d1, "ASUS UX431FL", ALC294_FIXUP_ASUS_DUAL_SPK),
7206	SND_PCI_QUIRK(0x1043, 0x18b1, "Asus MJ401TA", ALC256_FIXUP_ASUS_HEADSET_MIC),	7228	SND_PCI_QUIRK(0x1043, 0x18b1, "Asus MJ401TA", ALC256_FIXUP_ASUS_HEADSET_MIC),
		7229	SND_PCI_QUIRK(0x1043, 0x19ce, "ASUS B9450FA", ALC294_FIXUP_ASUS_HPE),
7207	SND_PCI_QUIRK(0x1043, 0x1a13, "Asus G73Jw", ALC269_FIXUP_ASUS_G73JW),	7230	SND_PCI_QUIRK(0x1043, 0x1a13, "Asus G73Jw", ALC269_FIXUP_ASUS_G73JW),
7208	SND_PCI_QUIRK(0x1043, 0x1a30, "ASUS X705UD", ALC256_FIXUP_ASUS_MIC),	7231	SND_PCI_QUIRK(0x1043, 0x1a30, "ASUS X705UD", ALC256_FIXUP_ASUS_MIC),
7209	SND_PCI_QUIRK(0x1043, 0x1b13, "Asus U41SV", ALC269_FIXUP_INV_DMIC),	7232	SND_PCI_QUIRK(0x1043, 0x1b13, "Asus U41SV", ALC269_FIXUP_INV_DMIC),
@@ -7274,8 +7297,8 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { · 64 unmodified lines
7274	SND_PCI_QUIRK(0x17aa, 0x224c, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),	7297	SND_PCI_QUIRK(0x17aa, 0x224c, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
7275	SND_PCI_QUIRK(0x17aa, 0x224d, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),	7298	SND_PCI_QUIRK(0x17aa, 0x224d, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
7276	SND_PCI_QUIRK(0x17aa, 0x225d, "Thinkpad T480", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),	7299	SND_PCI_QUIRK(0x17aa, 0x225d, "Thinkpad T480", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
7277	SND_PCI_QUIRK(0x17aa, 0x2292, "Thinkpad X1 Yoga 7th", ALC285_FIXUP_SPEAKER2_TO_DAC1),	7300	SND_PCI_QUIRK(0x17aa, 0x2292, "Thinkpad X1 Yoga 7th", ALC285_FIXUP_THINKPAD_HEADSET_JACK),
7278	SND_PCI_QUIRK(0x17aa, 0x2293, "Thinkpad X1 Carbon 7th", ALC285_FIXUP_SPEAKER2_TO_DAC1),	7301	SND_PCI_QUIRK(0x17aa, 0x2293, "Thinkpad X1 Carbon 7th", ALC285_FIXUP_THINKPAD_HEADSET_JACK),
7279	SND_PCI_QUIRK(0x17aa, 0x30bb, "ThinkCentre AIO", ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY),	7302	SND_PCI_QUIRK(0x17aa, 0x30bb, "ThinkCentre AIO", ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY),
7280	SND_PCI_QUIRK(0x17aa, 0x30e2, "ThinkCentre AIO", ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY),	7303	SND_PCI_QUIRK(0x17aa, 0x30e2, "ThinkCentre AIO", ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY),
7281	SND_PCI_QUIRK(0x17aa, 0x310c, "ThinkCentre Station", ALC294_FIXUP_LENOVO_MIC_LOCATION),	7304	SND_PCI_QUIRK(0x17aa, 0x310c, "ThinkCentre Station", ALC294_FIXUP_LENOVO_MIC_LOCATION),

sound/soc/codecs/Kconfig+1−1

@@ -1406,7 +1406,7 @@ config SND_SOC_WM8737 · 1405 unmodified lines
1406	depends on SND_SOC_I2C_AND_SPI	1406	depends on SND_SOC_I2C_AND_SPI
1407		1407
1408	config SND_SOC_WM8741	1408	config SND_SOC_WM8741
1409	tristate "Wolfson Microelectronics WM8737 DAC"	1409	tristate "Wolfson Microelectronics WM8741 DAC"
1410	depends on SND_SOC_I2C_AND_SPI	1410	depends on SND_SOC_I2C_AND_SPI
1411		1411
1412	config SND_SOC_WM8750	1412	config SND_SOC_WM8750

sound/soc/codecs/pcm512x.c+5−3

 	}
 	pcm512x->sclk = devm_clk_get(dev, NULL);
-	if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
+	if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) {
-		return -EPROBE_DEFER;
+		ret = -EPROBE_DEFER;
+		goto err;
+	}
 	if (!IS_ERR(pcm512x->sclk)) {
 		ret = clk_prepare_enable(pcm512x->sclk);
 		if (ret != 0) {
 			dev_err(dev, "Failed to enable SCLK: %d\n", ret);
-			return ret;
+			goto err;
 		}
 	}

sound/soc/codecs/rt1015.c+2−1

 	snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
 		RT1015_I2S_DL_MASK, val_len);
 	snd_soc_component_update_bits(component, RT1015_CLK2,
-		RT1015_FS_PD_MASK, pre_div);
+		RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
 	return 0;
 }
 			.rates = RT1015_STEREO_RATES,
 			.formats = RT1015_FORMATS,
 		},
+		.ops = &rt1015_aif_dai_ops,
 	}
 };

sound/soc/codecs/tas2562.c+3−2

 		break;
 	default:
-		dev_info(tas2562->dev, "Not supported params format\n");
+		dev_info(tas2562->dev, "Unsupported bitwidth format\n");
+		return -EINVAL;
 	}
 	ret = snd_soc_component_update_bits(tas2562->component,
 	ret = tas2562_set_samplerate(tas2562, params_rate(params));
 	if (ret)
-		dev_err(tas2562->dev, "set bitwidth failed, %d\n", ret);
+		dev_err(tas2562->dev, "set sample rate failed, %d\n", ret);
 	return ret;
 }

sound/soc/intel/skylake/skl-debug.c+17−15

 	int i;
 	ssize_t ret = 0;
-	for (i = 0; i < max_pin; i++)
+	for (i = 0; i < max_pin; i++) {
-		ret += snprintf(buf + size, MOD_BUF - size,
+		ret += scnprintf(buf + size, MOD_BUF - size,
 				"%s %d\n\tModule %d\n\tInstance %d\n\t"
 				"In-used %s\n\tType %s\n"
 				"\tState %d\n\tIndex %d\n",
 				m_pin[i].in_use ? "Used" : "Unused",
 				m_pin[i].is_dynamic ? "Dynamic" : "Static",
 				m_pin[i].pin_state, i);
+		size += ret;
+	}
 	return ret;
 }
 static ssize_t skl_print_fmt(struct skl_module_fmt *fmt, char *buf,
 					ssize_t size, bool direction)
 {
-	return snprintf(buf + size, MOD_BUF - size,
+	return scnprintf(buf + size, MOD_BUF - size,
 			"%s\n\tCh %d\n\tFreq %d\n\tBit depth %d\n\t"
 			"Valid bit depth %d\n\tCh config %#x\n\tInterleaving %d\n\t"
 			"Sample Type %d\n\tCh Map %#x\n",
 	if (!buf)
 		return -ENOMEM;
-	ret = snprintf(buf, MOD_BUF, "Module:\n\tUUID %pUL\n\tModule id %d\n"
+	ret = scnprintf(buf, MOD_BUF, "Module:\n\tUUID %pUL\n\tModule id %d\n"
 			"\tInstance id %d\n\tPvt_id %d\n", mconfig->guid,
 			mconfig->id.module_id, mconfig->id.instance_id,
 			mconfig->id.pvt_id);
-	ret += snprintf(buf + ret, MOD_BUF - ret,
+	ret += scnprintf(buf + ret, MOD_BUF - ret,
 			"Resources:\n\tCPC %#x\n\tIBS %#x\n\tOBS %#x\t\n",
 			res->cpc, res->ibs, res->obs);
-	ret += snprintf(buf + ret, MOD_BUF - ret,
+	ret += scnprintf(buf + ret, MOD_BUF - ret,
 			"Module data:\n\tCore %d\n\tIn queue %d\n\t"
 			"Out queue %d\n\tType %s\n",
 			mconfig->core_id, mconfig->max_in_queue,
 	ret += skl_print_fmt(mconfig->in_fmt, buf, ret, true);
 	ret += skl_print_fmt(mconfig->out_fmt, buf, ret, false);
-	ret += snprintf(buf + ret, MOD_BUF - ret,
+	ret += scnprintf(buf + ret, MOD_BUF - ret,
 			"Fixup:\n\tParams %#x\n\tConverter %#x\n",
 			mconfig->params_fixup, mconfig->converter);
-	ret += snprintf(buf + ret, MOD_BUF - ret,
+	ret += scnprintf(buf + ret, MOD_BUF - ret,
 			"Module Gateway:\n\tType %#x\n\tVbus %#x\n\tHW conn %#x\n\tSlot %#x\n",
 			mconfig->dev_type, mconfig->vbus_id,
 			mconfig->hw_conn_type, mconfig->time_slot);
-	ret += snprintf(buf + ret, MOD_BUF - ret,
+	ret += scnprintf(buf + ret, MOD_BUF - ret,
 			"Pipeline:\n\tID %d\n\tPriority %d\n\tConn Type %d\n\t"
 			"Pages %#x\n", mconfig->pipe->ppl_id,
 			mconfig->pipe->pipe_priority, mconfig->pipe->conn_type,
 			mconfig->pipe->memory_pages);
-	ret += snprintf(buf + ret, MOD_BUF - ret,
+	ret += scnprintf(buf + ret, MOD_BUF - ret,
 			"\tParams:\n\t\tHost DMA %d\n\t\tLink DMA %d\n",
 			mconfig->pipe->p_params->host_dma_id,
 			mconfig->pipe->p_params->link_dma_id);
-	ret += snprintf(buf + ret, MOD_BUF - ret,
+	ret += scnprintf(buf + ret, MOD_BUF - ret,
 			"\tPCM params:\n\t\tCh %d\n\t\tFreq %d\n\t\tFormat %d\n",
 			mconfig->pipe->p_params->ch,
 			mconfig->pipe->p_params->s_freq,
 			mconfig->pipe->p_params->s_fmt);
-	ret += snprintf(buf + ret, MOD_BUF - ret,
+	ret += scnprintf(buf + ret, MOD_BUF - ret,
 			"\tLink %#x\n\tStream %#x\n",
 			mconfig->pipe->p_params->linktype,
 			mconfig->pipe->p_params->stream);
-	ret += snprintf(buf + ret, MOD_BUF - ret,
+	ret += scnprintf(buf + ret, MOD_BUF - ret,
 			"\tState %d\n\tPassthru %s\n",
 			mconfig->pipe->state,
 			mconfig->pipe->passthru ? "true" : "false");
 	ret += skl_print_pins(mconfig->m_out_pin, buf,
 			mconfig->max_out_queue, ret, false);
-	ret += snprintf(buf + ret, MOD_BUF - ret,
+	ret += scnprintf(buf + ret, MOD_BUF - ret,
 			"Other:\n\tDomain %d\n\tHomogeneous Input %s\n\t"
 			"Homogeneous Output %s\n\tIn Queue Mask %d\n\t"
 			"Out Queue Mask %d\n\tDMA ID %d\n\tMem Pages %d\n\t"
 		__ioread32_copy(d->fw_read_buff, fw_reg_addr, w0_stat_sz >> 2);
 	for (offset = 0; offset < FW_REG_SIZE; offset += 16) {
-		ret += snprintf(tmp + ret, FW_REG_BUF - ret, "%#.4x: ", offset);
+		ret += scnprintf(tmp + ret, FW_REG_BUF - ret, "%#.4x: ", offset);
 		hex_dump_to_buffer(d->fw_read_buff + offset, 16, 16, 4,
 				   tmp + ret, FW_REG_BUF - ret, 0);
 		ret += strlen(tmp + ret);

sound/soc/intel/skylake/skl-ssp-clk.c+3−1

 				&clks[i], clk_pdata, i);
 		if (IS_ERR(data->clk[data->avail_clk_cnt])) {
-			ret = PTR_ERR(data->clk[data->avail_clk_cnt++]);
+			ret = PTR_ERR(data->clk[data->avail_clk_cnt]);
 			goto err_unreg_skl_clk;
 		}
+		data->avail_clk_cnt++;
 	}
 	platform_set_drvdata(pdev, data);

sound/soc/meson/g12a-tohdmitx.c+6−0

 #include <linux/module.h>
 #include <sound/pcm_params.h>
 #include <linux/regmap.h>
+#include <linux/reset.h>
 #include <sound/soc.h>
 #include <sound/soc-dai.h>
 	struct device *dev = &pdev->dev;
 	void __iomem *regs;
 	struct regmap *map;
+	int ret;
+	ret = device_reset(dev);
+	if (ret)
+		return ret;
 	regs = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(regs))

sound/soc/soc-component.c+1−1

@@ -451,7 +451,7 @@ int snd_soc_pcm_component_sync_stop(struct snd_pcm_substream *substream) · 450 unmodified lines
451	int i, ret;	451	int i, ret;
452		452
453	for_each_rtd_components(rtd, i, component) {	453	for_each_rtd_components(rtd, i, component) {
454	if (component->driver->ioctl) {	454	if (component->driver->sync_stop) {
455	ret = component->driver->sync_stop(component,	455	ret = component->driver->sync_stop(component,
456	substream);	456	substream);
457	if (ret < 0)	457	if (ret < 0)

sound/soc/soc-compress.c+1−1

@@ -299,7 +299,7 @@ static int soc_compr_free_fe(struct snd_compr_stream *cstream) · 298 unmodified lines
299	for_each_dpcm_be(fe, stream, dpcm)	299	for_each_dpcm_be(fe, stream, dpcm)
300	dpcm->state = SND_SOC_DPCM_LINK_STATE_FREE;	300	dpcm->state = SND_SOC_DPCM_LINK_STATE_FREE;
301		301
302	snd_soc_dapm_stream_stop(fe, stream);	302	dpcm_dapm_stream_event(fe, stream, SND_SOC_DAPM_STREAM_STOP);
303		303
304	fe->dpcm[stream].state = SND_SOC_DPCM_STATE_CLOSE;	304	fe->dpcm[stream].state = SND_SOC_DPCM_STATE_CLOSE;
305	fe->dpcm[stream].runtime_update = SND_SOC_DPCM_UPDATE_NO;	305	fe->dpcm[stream].runtime_update = SND_SOC_DPCM_UPDATE_NO;

sound/soc/soc-dapm.c+1−1

@@ -4772,7 +4772,7 @@ static void soc_dapm_shutdown_dapm(struct snd_soc_dapm_context *dapm) · 4771 unmodified lines
4772	continue;	4772	continue;
4773	if (w->power) {	4773	if (w->power) {
4774	dapm_seq_insert(w, &down_list, false);	4774	dapm_seq_insert(w, &down_list, false);
4775	w->power = 0;	4775	w->new_power = 0;
4776	powerdown = 1;	4776	powerdown = 1;
4777	}	4777	}
4778	}	4778	}

sound/soc/soc-pcm.c+9−9

@@ -2006,7 +2006,7 @@ static int dpcm_fe_dai_shutdown(struct snd_pcm_substream *substream) · 2005 unmodified lines
2006	soc_pcm_close(substream);	2006	soc_pcm_close(substream);
2007		2007
2008	/* run the stream event for each BE */	2008	/* run the stream event for each BE */
2009	snd_soc_dapm_stream_stop(fe, stream);	2009	dpcm_dapm_stream_event(fe, stream, SND_SOC_DAPM_STREAM_STOP);
2010		2010
2011	fe->dpcm[stream].state = SND_SOC_DPCM_STATE_CLOSE;	2011	fe->dpcm[stream].state = SND_SOC_DPCM_STATE_CLOSE;
2012	dpcm_set_fe_update_state(fe, stream, SND_SOC_DPCM_UPDATE_NO);	2012	dpcm_set_fe_update_state(fe, stream, SND_SOC_DPCM_UPDATE_NO);
@@ -3171,16 +3171,16 @@ static ssize_t dpcm_show_state(struct snd_soc_pcm_runtime *fe, · 1158 unmodified lines
3171	unsigned long flags;	3171	unsigned long flags;
3172		3172
3173	/* FE state */	3173	/* FE state */
3174	offset += snprintf(buf + offset, size - offset,	3174	offset += scnprintf(buf + offset, size - offset,
3175	"[%s - %s]\n", fe->dai_link->name,	3175	"[%s - %s]\n", fe->dai_link->name,
3176	stream ? "Capture" : "Playback");	3176	stream ? "Capture" : "Playback");
3177		3177
3178	offset += snprintf(buf + offset, size - offset, "State: %s\n",	3178	offset += scnprintf(buf + offset, size - offset, "State: %s\n",
3179	dpcm_state_string(fe->dpcm[stream].state));	3179	dpcm_state_string(fe->dpcm[stream].state));
3180		3180
3181	if ((fe->dpcm[stream].state >= SND_SOC_DPCM_STATE_HW_PARAMS) &&	3181	if ((fe->dpcm[stream].state >= SND_SOC_DPCM_STATE_HW_PARAMS) &&
3182	(fe->dpcm[stream].state <= SND_SOC_DPCM_STATE_STOP))	3182	(fe->dpcm[stream].state <= SND_SOC_DPCM_STATE_STOP))
3183	offset += snprintf(buf + offset, size - offset,	3183	offset += scnprintf(buf + offset, size - offset,
3184	"Hardware Params: "	3184	"Hardware Params: "
3185	"Format = %s, Channels = %d, Rate = %d\n",	3185	"Format = %s, Channels = %d, Rate = %d\n",
3186	snd_pcm_format_name(params_format(params)),	3186	snd_pcm_format_name(params_format(params)),
@@ -3188,10 +3188,10 @@ static ssize_t dpcm_show_state(struct snd_soc_pcm_runtime *fe, · 1 unmodified line
3188	params_rate(params));	3188	params_rate(params));
3189		3189
3190	/* BEs state */	3190	/* BEs state */
3191	offset += snprintf(buf + offset, size - offset, "Backends:\n");	3191	offset += scnprintf(buf + offset, size - offset, "Backends:\n");
3192		3192
3193	if (list_empty(&fe->dpcm[stream].be_clients)) {	3193	if (list_empty(&fe->dpcm[stream].be_clients)) {
3194	offset += snprintf(buf + offset, size - offset,	3194	offset += scnprintf(buf + offset, size - offset,
3195	" No active DSP links\n");	3195	" No active DSP links\n");
3196	goto out;	3196	goto out;
3197	}	3197	}
@@ -3201,16 +3201,16 @@ static ssize_t dpcm_show_state(struct snd_soc_pcm_runtime *fe, · 3 unmodified lines
3201	struct snd_soc_pcm_runtime *be = dpcm->be;	3201	struct snd_soc_pcm_runtime *be = dpcm->be;
3202	params = &dpcm->hw_params;	3202	params = &dpcm->hw_params;
3203		3203
3204	offset += snprintf(buf + offset, size - offset,	3204	offset += scnprintf(buf + offset, size - offset,
3205	"- %s\n", be->dai_link->name);	3205	"- %s\n", be->dai_link->name);
3206		3206
3207	offset += snprintf(buf + offset, size - offset,	3207	offset += scnprintf(buf + offset, size - offset,
3208	" State: %s\n",	3208	" State: %s\n",
3209	dpcm_state_string(be->dpcm[stream].state));	3209	dpcm_state_string(be->dpcm[stream].state));
3210		3210
3211	if ((be->dpcm[stream].state >= SND_SOC_DPCM_STATE_HW_PARAMS) &&	3211	if ((be->dpcm[stream].state >= SND_SOC_DPCM_STATE_HW_PARAMS) &&
3212	(be->dpcm[stream].state <= SND_SOC_DPCM_STATE_STOP))	3212	(be->dpcm[stream].state <= SND_SOC_DPCM_STATE_STOP))
3213	offset += snprintf(buf + offset, size - offset,	3213	offset += scnprintf(buf + offset, size - offset,
3214	" Hardware Params: "	3214	" Hardware Params: "
3215	"Format = %s, Channels = %d, Rate = %d\n",	3215	"Format = %s, Channels = %d, Rate = %d\n",
3216	snd_pcm_format_name(params_format(params)),	3216	snd_pcm_format_name(params_format(params)),

sound/soc/soc-topology.c+10−7

 		}
 		ret = soc_tplg_link_config(tplg, _link);
-		if (ret < 0)
+		if (ret < 0) {
+			if (!abi_match)
+				kfree(_link);
 			return ret;
+		}
 		/* offset by version-specific struct size and
 		 * real priv data size
 {
 	struct snd_soc_tplg_manifest *manifest, *_manifest;
 	bool abi_match;
-	int err;
+	int ret = 0;
 	if (tplg->pass != SOC_TPLG_PASS_MANIFEST)
 		return 0;
 		_manifest = manifest;
 	} else {
 		abi_match = false;
-		err = manifest_new_ver(tplg, manifest, &_manifest);
+		ret = manifest_new_ver(tplg, manifest, &_manifest);
-		if (err < 0)
+		if (ret < 0)
-			return err;
+			return ret;
 	}
 	/* pass control to component driver for optional further init */
 	if (tplg->comp && tplg->ops && tplg->ops->manifest)
-		return tplg->ops->manifest(tplg->comp, tplg->index, _manifest);
+		ret = tplg->ops->manifest(tplg->comp, tplg->index, _manifest);
 	if (!abi_match)	/* free the duplicated one */
 		kfree(_manifest);
-	return 0;
+	return ret;
 }
 /* validate header magic, size and type */

sound/soc/sof/ipc.c+1−1

@@ -499,7 +499,7 @@ int snd_sof_ipc_stream_posn(struct snd_soc_component *scomp, · 498 unmodified lines
499		499
500	/* send IPC to the DSP */	500	/* send IPC to the DSP */
501	err = sof_ipc_tx_message(sdev->ipc,	501	err = sof_ipc_tx_message(sdev->ipc,
502	stream.hdr.cmd, &stream, sizeof(stream), &posn,	502	stream.hdr.cmd, &stream, sizeof(stream), posn,
503	sizeof(*posn));	503	sizeof(*posn));
504	if (err < 0) {	504	if (err < 0) {
505	dev_err(sdev->dev, "error: failed to get stream %d position\n",	505	dev_err(sdev->dev, "error: failed to get stream %d position\n",

sound/soc/stm/stm32_sai_sub.c+10−8

 		return ret;
 	}
-	ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component,
+	ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
-					      &sai->cpu_dai_drv, 1);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not register pcm dma\n");
+		return ret;
+	}
+	ret = snd_soc_register_component(&pdev->dev, &stm32_component,
+					 &sai->cpu_dai_drv, 1);
 	if (ret)
 		return ret;
 	if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
 		conf = &stm32_sai_pcm_config_spdif;
-	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
-	if (ret) {
-		dev_err(&pdev->dev, "Could not register pcm dma\n");
-		return ret;
-	}
 	return 0;
 }
 	struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev);
 	clk_unprepare(sai->pdata->pclk);
+	snd_dmaengine_pcm_unregister(&pdev->dev);
+	snd_soc_unregister_component(&pdev->dev);
 	return 0;
 }

tools/arch/x86/include/asm/msr-index.h+2−0

@@ -512,6 +512,8 @@ · 511 unmodified lines
512	#define MSR_K7_HWCR 0xc0010015	512	#define MSR_K7_HWCR 0xc0010015
513	#define MSR_K7_HWCR_SMMLOCK_BIT 0	513	#define MSR_K7_HWCR_SMMLOCK_BIT 0
514	#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)	514	#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
		515	#define MSR_K7_HWCR_IRPERF_EN_BIT 30
		516	#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
515	#define MSR_K7_FID_VID_CTL 0xc0010041	517	#define MSR_K7_FID_VID_CTL 0xc0010041
516	#define MSR_K7_FID_VID_STATUS 0xc0010042	518	#define MSR_K7_FID_VID_STATUS 0xc0010042
517		519

tools/arch/x86/include/uapi/asm/kvm.h+1−0

@@ -390,6 +390,7 @@ struct kvm_sync_regs { · 389 unmodified lines
390	#define KVM_STATE_NESTED_GUEST_MODE 0x00000001	390	#define KVM_STATE_NESTED_GUEST_MODE 0x00000001
391	#define KVM_STATE_NESTED_RUN_PENDING 0x00000002	391	#define KVM_STATE_NESTED_RUN_PENDING 0x00000002
392	#define KVM_STATE_NESTED_EVMCS 0x00000004	392	#define KVM_STATE_NESTED_EVMCS 0x00000004
		393	#define KVM_STATE_NESTED_MTF_PENDING 0x00000008
393		394
394	#define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001	395	#define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001
395	#define KVM_STATE_NESTED_SMM_VMXON 0x00000002	396	#define KVM_STATE_NESTED_SMM_VMXON 0x00000002

tools/perf/Documentation/perf-config.txt+73−1

@@ -239,7 +239,6 @@ buildid.*:: · 238 unmodified lines
239	set buildid.dir to /dev/null. The default is $HOME/.debug	239	set buildid.dir to /dev/null. The default is $HOME/.debug
240		240
241	annotate.*::	241	annotate.*::
242	These options work only for TUI.
243	These are in control of addresses, jump function, source code	242	These are in control of addresses, jump function, source code
244	in lines of assembly code from a specific program.	243	in lines of assembly code from a specific program.
245		244
@@ -269,6 +268,8 @@ annotate.*:: · 23 unmodified lines
269	│ mov (%rdi),%rdx	268	│ mov (%rdi),%rdx
270	│ return n;	269	│ return n;
271		270
		271	This option works with tui, stdio2 browsers.
		272
272	annotate.use_offset::	273	annotate.use_offset::
273	Basing on a first address of a loaded function, offset can be used.	274	Basing on a first address of a loaded function, offset can be used.
274	Instead of using original addresses of assembly code,	275	Instead of using original addresses of assembly code,
@@ -287,6 +288,8 @@ annotate.*:: · 12 unmodified lines
287		288
288	368:│ mov 0x8(%r14),%rdi	289	368:│ mov 0x8(%r14),%rdi
289		290
		291	This option works with tui, stdio2 browsers.
		292
290	annotate.jump_arrows::	293	annotate.jump_arrows::
291	There can be jump instruction among assembly code.	294	There can be jump instruction among assembly code.
292	Depending on a boolean value of jump_arrows,	295	Depending on a boolean value of jump_arrows,
@@ -306,6 +309,8 @@ annotate.*:: · 13 unmodified lines
306	│1330: mov %r15,%r10	309	│1330: mov %r15,%r10
307	│1333: cmp %r15,%r14	310	│1333: cmp %r15,%r14
308		311
		312	This option works with tui browser.
		313
309	annotate.show_linenr::	314	annotate.show_linenr::
310	When showing source code if this option is 'true',	315	When showing source code if this option is 'true',
311	line numbers are printed as below.	316	line numbers are printed as below.
@@ -325,6 +330,8 @@ annotate.*:: · 13 unmodified lines
325	│ array++;	330	│ array++;
326	│ }	331	│ }
327		332
		333	This option works with tui, stdio2 browsers.
		334
328	annotate.show_nr_jumps::	335	annotate.show_nr_jumps::
329	Let's see a part of assembly code.	336	Let's see a part of assembly code.
330		337
@@ -335,6 +342,8 @@ annotate.*:: · 4 unmodified lines
335		342
336	│1 1382: movb $0x1,-0x270(%rbp)	343	│1 1382: movb $0x1,-0x270(%rbp)
337		344
		345	This option works with tui, stdio2 browsers.
		346
338	annotate.show_total_period::	347	annotate.show_total_period::
339	To compare two records on an instruction base, with this option	348	To compare two records on an instruction base, with this option
340	provided, display total number of samples that belong to a line	349	provided, display total number of samples that belong to a line
@@ -348,11 +357,30 @@ annotate.*:: · 7 unmodified lines
348		357
349	99.93 │ mov %eax,%eax	358	99.93 │ mov %eax,%eax
350		359
		360	This option works with tui, stdio2, stdio browsers.
		361
		362	annotate.show_nr_samples::
		363	By default perf annotate shows percentage of samples. This option
		364	can be used to print absolute number of samples. Ex, when set as
		365	false:
		366
		367	Percent│
		368	74.03 │ mov %fs:0x28,%rax
		369
		370	When set as true:
		371
		372	Samples│
		373	6 │ mov %fs:0x28,%rax
		374
		375	This option works with tui, stdio2, stdio browsers.
		376
351	annotate.offset_level::	377	annotate.offset_level::
352	Default is '1', meaning just jump targets will have offsets show right beside	378	Default is '1', meaning just jump targets will have offsets show right beside
353	the instruction. When set to '2' 'call' instructions will also have its offsets	379	the instruction. When set to '2' 'call' instructions will also have its offsets
354	shown, 3 or higher will show offsets for all instructions.	380	shown, 3 or higher will show offsets for all instructions.
355		381
		382	This option works with tui, stdio2 browsers.
		383
356	hist.*::	384	hist.*::
357	hist.percentage::	385	hist.percentage::
358	This option control the way to calculate overhead of filtered entries -	386	This option control the way to calculate overhead of filtered entries -
@@ -490,6 +518,12 @@ top.*:: · 131 unmodified lines
490	column by default.	518	column by default.
491	The default is 'true'.	519	The default is 'true'.
492		520
		521	top.call-graph::
		522	This is identical to 'call-graph.record-mode', except it is
		523	applicable only for 'top' subcommand. This option ONLY setup
		524	the unwind method. To enable 'perf top' to actually use it,
		525	the command line option -g must be specified.
		526
493	man.*::	527	man.*::
494	man.viewer::	528	man.viewer::
495	This option can assign a tool to view manual pages when 'help'	529	This option can assign a tool to view manual pages when 'help'
@@ -517,6 +551,16 @@ record.*:: · 21 unmodified lines
517	But if this option is 'no-cache', it will not update the build-id cache.	551	But if this option is 'no-cache', it will not update the build-id cache.
518	'skip' skips post-processing and does not update the cache.	552	'skip' skips post-processing and does not update the cache.
519		553
		554	record.call-graph::
		555	This is identical to 'call-graph.record-mode', except it is
		556	applicable only for 'record' subcommand. This option ONLY setup
		557	the unwind method. To enable 'perf record' to actually use it,
		558	the command line option -g must be specified.
		559
		560	record.aio::
		561	Use 'n' control blocks in asynchronous (Posix AIO) trace writing
		562	mode ('n' default: 1, max: 4).
		563
520	diff.*::	564	diff.*::
521	diff.order::	565	diff.order::
522	This option sets the number of columns to sort the result.	566	This option sets the number of columns to sort the result.
@@ -566,6 +610,11 @@ trace.*:: · 43 unmodified lines
566	"libbeauty", the default, to use the same argument beautifiers used in the	610	"libbeauty", the default, to use the same argument beautifiers used in the
567	strace-like sys_enter+sys_exit lines.	611	strace-like sys_enter+sys_exit lines.
568		612
		613	ftrace.*::
		614	ftrace.tracer::
		615	Can be used to select the default tracer. Possible values are
		616	'function' and 'function_graph'.
		617
569	llvm.*::	618	llvm.*::
570	llvm.clang-path::	619	llvm.clang-path::
571	Path to clang. If omit, search it from $PATH.	620	Path to clang. If omit, search it from $PATH.
@@ -610,6 +659,29 @@ scripts.*:: · 38 unmodified lines
610	The script gets the same options passed as a full perf script,	659	The script gets the same options passed as a full perf script,
611	in particular -i perfdata file, --cpu, --tid	660	in particular -i perfdata file, --cpu, --tid
612		661
		662	convert.*::
		663
		664	convert.queue-size::
		665	Limit the size of ordered_events queue, so we could control
		666	allocation size of perf data files without proper finished
		667	round events.
		668
		669	intel-pt.*::
		670
		671	intel-pt.cache-divisor::
		672
		673	intel-pt.mispred-all::
		674	If set, Intel PT decoder will set the mispred flag on all
		675	branches.
		676
		677	auxtrace.*::
		678
		679	auxtrace.dumpdir::
		680	s390 only. The directory to save the auxiliary trace buffer
		681	can be changed using this option. Ex, auxtrace.dumpdir=/tmp.
		682	If the directory does not exist or has the wrong file type,
		683	the current directory is used.
		684
613	SEE ALSO	685	SEE ALSO
614	--------	686	--------
615	linkperf:perf[1]	687	linkperf:perf[1]

tools/perf/arch/arm/util/cs-etm.c+2−16

 	free(ptr);
 }
-static int cs_etm_read_finish(struct auxtrace_record *itr, int idx)
-{
-	struct cs_etm_recording *ptr =
-			container_of(itr, struct cs_etm_recording, itr);
-	struct evsel *evsel;
-	evlist__for_each_entry(ptr->evlist, evsel) {
-		if (evsel->core.attr.type == ptr->cs_etm_pmu->type)
-			return perf_evlist__enable_event_idx(ptr->evlist,
-							     evsel, idx);
-	}
-	return -EINVAL;
-}
 struct auxtrace_record *cs_etm_record_init(int *err)
 {
 	struct perf_pmu *cs_etm_pmu;
 	}
 	ptr->cs_etm_pmu			= cs_etm_pmu;
+	ptr->itr.pmu			= cs_etm_pmu;
 	ptr->itr.parse_snapshot_options	= cs_etm_parse_snapshot_options;
 	ptr->itr.recording_options	= cs_etm_recording_options;
 	ptr->itr.info_priv_size		= cs_etm_info_priv_size;
 	ptr->itr.snapshot_finish	= cs_etm_snapshot_finish;
 	ptr->itr.reference		= cs_etm_reference;
 	ptr->itr.free			= cs_etm_recording_free;
-	ptr->itr.read_finish		= cs_etm_read_finish;
+	ptr->itr.read_finish		= auxtrace_record__read_finish;
 	*err = 0;
 	return &ptr->itr;

tools/perf/arch/arm64/util/arm-spe.c+2−15

 	free(sper);
 }
-static int arm_spe_read_finish(struct auxtrace_record *itr, int idx)
-{
-	struct arm_spe_recording *sper =
-			container_of(itr, struct arm_spe_recording, itr);
-	struct evsel *evsel;
-	evlist__for_each_entry(sper->evlist, evsel) {
-		if (evsel->core.attr.type == sper->arm_spe_pmu->type)
-			return perf_evlist__enable_event_idx(sper->evlist,
-							     evsel, idx);
-	}
-	return -EINVAL;
-}
 struct auxtrace_record *arm_spe_recording_init(int *err,
 					       struct perf_pmu *arm_spe_pmu)
 {
 	}
 	sper->arm_spe_pmu = arm_spe_pmu;
+	sper->itr.pmu = arm_spe_pmu;
 	sper->itr.recording_options = arm_spe_recording_options;
 	sper->itr.info_priv_size = arm_spe_info_priv_size;
 	sper->itr.info_fill = arm_spe_info_fill;
 	sper->itr.free = arm_spe_recording_free;
 	sper->itr.reference = arm_spe_reference;
-	sper->itr.read_finish = arm_spe_read_finish;
+	sper->itr.read_finish = auxtrace_record__read_finish;
 	sper->itr.alignment = 0;
 	*err = 0;

tools/perf/arch/powerpc/entry/syscalls/syscall.tbl+2−0

@@ -517,3 +517,5 @@ · 516 unmodified lines
517	433 common fspick sys_fspick	517	433 common fspick sys_fspick
518	434 common pidfd_open sys_pidfd_open	518	434 common pidfd_open sys_pidfd_open
519	435 nospu clone3 ppc_clone3	519	435 nospu clone3 ppc_clone3
		520	437 common openat2 sys_openat2
		521	438 common pidfd_getfd sys_pidfd_getfd

tools/perf/arch/x86/util/intel-bts.c+2−15

 	return err;
 }
-static int intel_bts_read_finish(struct auxtrace_record *itr, int idx)
-{
-	struct intel_bts_recording *btsr =
-			container_of(itr, struct intel_bts_recording, itr);
-	struct evsel *evsel;
-	evlist__for_each_entry(btsr->evlist, evsel) {
-		if (evsel->core.attr.type == btsr->intel_bts_pmu->type)
-			return perf_evlist__enable_event_idx(btsr->evlist,
-							     evsel, idx);
-	}
-	return -EINVAL;
-}
 struct auxtrace_record *intel_bts_recording_init(int *err)
 {
 	struct perf_pmu *intel_bts_pmu = perf_pmu__find(INTEL_BTS_PMU_NAME);
 	}
 	btsr->intel_bts_pmu = intel_bts_pmu;
+	btsr->itr.pmu = intel_bts_pmu;
 	btsr->itr.recording_options = intel_bts_recording_options;
 	btsr->itr.info_priv_size = intel_bts_info_priv_size;
 	btsr->itr.info_fill = intel_bts_info_fill;
 	btsr->itr.find_snapshot = intel_bts_find_snapshot;
 	btsr->itr.parse_snapshot_options = intel_bts_parse_snapshot_options;
 	btsr->itr.reference = intel_bts_reference;
-	btsr->itr.read_finish = intel_bts_read_finish;
+	btsr->itr.read_finish = auxtrace_record__read_finish;
 	btsr->itr.alignment = sizeof(struct branch);
 	return &btsr->itr;
 }

tools/perf/arch/x86/util/intel-pt.c+2−15

 	return rdtsc();
 }
-static int intel_pt_read_finish(struct auxtrace_record *itr, int idx)
-{
-	struct intel_pt_recording *ptr =
-			container_of(itr, struct intel_pt_recording, itr);
-	struct evsel *evsel;
-	evlist__for_each_entry(ptr->evlist, evsel) {
-		if (evsel->core.attr.type == ptr->intel_pt_pmu->type)
-			return perf_evlist__enable_event_idx(ptr->evlist, evsel,
-							     idx);
-	}
-	return -EINVAL;
-}
 struct auxtrace_record *intel_pt_recording_init(int *err)
 {
 	struct perf_pmu *intel_pt_pmu = perf_pmu__find(INTEL_PT_PMU_NAME);
 	}
 	ptr->intel_pt_pmu = intel_pt_pmu;
+	ptr->itr.pmu = intel_pt_pmu;
 	ptr->itr.recording_options = intel_pt_recording_options;
 	ptr->itr.info_priv_size = intel_pt_info_priv_size;
 	ptr->itr.info_fill = intel_pt_info_fill;
 	ptr->itr.find_snapshot = intel_pt_find_snapshot;
 	ptr->itr.parse_snapshot_options = intel_pt_parse_snapshot_options;
 	ptr->itr.reference = intel_pt_reference;
-	ptr->itr.read_finish = intel_pt_read_finish;
+	ptr->itr.read_finish = auxtrace_record__read_finish;
 	/*
 	 * Decoding starts at a PSB packet. Minimum PSB period is 2K so 4K
 	 * should give at least 1 PSB per sample.

tools/perf/builtin-annotate.c+2−2

 	if (ret < 0)
 		return ret;
+	annotation_config__init(&annotate.opts);
 	argc = parse_options(argc, argv, options, annotate_usage, 0);
 	if (argc) {
 		/*
 	if (ret < 0)
 		goto out_delete;
-	annotation_config__init();
 	symbol_conf.try_vmlinux_path = true;
 	ret = symbol__init(&annotate.session->header.env);

tools/perf/builtin-probe.c+4−2

 		ret = probe_file__del_strlist(kfd, klist);
 		if (ret < 0)
 			goto error;
-	}
+	} else if (ret == -ENOMEM)
+		goto error;
 	ret2 = probe_file__get_events(ufd, filter, ulist);
 	if (ret2 == 0) {
 		ret2 = probe_file__del_strlist(ufd, ulist);
 		if (ret2 < 0)
 			goto error;
-	}
+	} else if (ret2 == -ENOMEM)
+		goto error;
 	if (ret == -ENOENT && ret2 == -ENOENT)
 		pr_warning("\"%s\" does not hit any event.\n", str);

tools/perf/builtin-report.c+1−1

@@ -1507,7 +1507,7 @@ repeat: · 1506 unmodified lines
1507	symbol_conf.priv_size += sizeof(u32);	1507	symbol_conf.priv_size += sizeof(u32);
1508	symbol_conf.sort_by_name = true;	1508	symbol_conf.sort_by_name = true;
1509	}	1509	}
1510	annotation_config__init();	1510	annotation_config__init(&report.annotation_opts);
1511	}	1511	}
1512		1512
1513	if (symbol__init(&session->header.env) < 0)	1513	if (symbol__init(&session->header.env) < 0)

tools/perf/builtin-top.c+2−2

@@ -143,7 +143,7 @@ static int perf_top__parse_source(struct perf_top top, struct hist_entry he) · 142 unmodified lines
143	return err;	143	return err;
144	}	144	}
145		145
146	err = symbol__annotate(&he->ms, evsel, 0, &top->annotation_opts, NULL);	146	err = symbol__annotate(&he->ms, evsel, &top->annotation_opts, NULL);
147	if (err == 0) {	147	if (err == 0) {
148	top->sym_filter_entry = he;	148	top->sym_filter_entry = he;
149	} else {	149	} else {
@@ -1683,7 +1683,7 @@ int cmd_top(int argc, const char **argv) · 1533 unmodified lines
1683	if (status < 0)	1683	if (status < 0)
1684	goto out_delete_evlist;	1684	goto out_delete_evlist;
1685		1685
1686	annotation_config__init();	1686	annotation_config__init(&top.annotation_opts);
1687		1687
1688	symbol_conf.try_vmlinux_path = (symbol_conf.vmlinux_name == NULL);	1688	symbol_conf.try_vmlinux_path = (symbol_conf.vmlinux_name == NULL);
1689	status = symbol__init(NULL);	1689	status = symbol__init(NULL);

tools/perf/include/bpf/pid_filter.h+1−1

@@ -3,7 +3,7 @@ · 2 unmodified lines
3	#ifndef _PERF_BPF_PID_FILTER_	3	#ifndef _PERF_BPF_PID_FILTER_
4	#define _PERF_BPF_PID_FILTER_	4	#define _PERF_BPF_PID_FILTER_
5		5
6	#include <bpf/bpf.h>	6	#include <bpf.h>
7		7
8	#define pid_filter(name) pid_map(name, bool)	8	#define pid_filter(name) pid_map(name, bool)
9		9

tools/perf/include/bpf/stdio.h+1−1

@@ -1,6 +1,6 @@
1	// SPDX-License-Identifier: GPL-2.0	1	// SPDX-License-Identifier: GPL-2.0
2		2
3	#include <bpf/bpf.h>	3	#include <bpf.h>
4		4
5	struct bpf_map SEC("maps") __bpf_stdout__ = {	5	struct bpf_map SEC("maps") __bpf_stdout__ = {
6	.type = BPF_MAP_TYPE_PERF_EVENT_ARRAY,	6	.type = BPF_MAP_TYPE_PERF_EVENT_ARRAY,

tools/perf/include/bpf/unistd.h+1−1

@@ -1,6 +1,6 @@
1	// SPDX-License-Identifier: LGPL-2.1	1	// SPDX-License-Identifier: LGPL-2.1
2		2
3	#include <bpf/bpf.h>	3	#include <bpf.h>
4		4
5	static int (bpf_get_current_pid_tgid)(void) = (void )BPF_FUNC_get_current_pid_tgid;	5	static int (bpf_get_current_pid_tgid)(void) = (void )BPF_FUNC_get_current_pid_tgid;
6		6

tools/perf/tests/shell/lib/probe_vfs_getname.sh+1−1

@@ -14,7 +14,7 @@ add_probe_vfs_getname() { · 13 unmodified lines
14	if [ $had_vfs_getname -eq 1 ] ; then	14	if [ $had_vfs_getname -eq 1 ] ; then
15	line=$(perf probe -L getname_flags 2>&1 \| egrep 'result.=.filename;' \| sed -r 's/[[:space:]]+([[:digit:]]+)[[:space:]]+result->uptr.*/\1/')	15	line=$(perf probe -L getname_flags 2>&1 \| egrep 'result.=.filename;' \| sed -r 's/[[:space:]]+([[:digit:]]+)[[:space:]]+result->uptr.*/\1/')
16	perf probe -q "vfs_getname=getname_flags:${line} pathname=result->name:string" \|\| \	16	perf probe -q "vfs_getname=getname_flags:${line} pathname=result->name:string" \|\| \
17	perf probe $verbose "vfs_getname=getname_flags:${line} pathname=filename:string"	17	perf probe $verbose "vfs_getname=getname_flags:${line} pathname=filename:ustring"
18	fi	18	fi
19	}	19	}
20		20

tools/perf/ui/browsers/annotate.c+9−10

 		"?             Search string backwards\n");
 			continue;
 		case 'r':
-			{
+			script_browse(NULL, NULL);
-				script_browse(NULL, NULL);
+			annotate_browser__show(&browser->b, title, help);
-				continue;
+			continue;
-			}
 		case 'k':
 			notes->options->show_linenr = !notes->options->show_linenr;
 			break;
 			map_symbol__annotation_dump(ms, evsel, browser->opts);
 			continue;
 		case 't':
-			if (notes->options->show_total_period) {
+			if (symbol_conf.show_total_period) {
-				notes->options->show_total_period = false;
+				symbol_conf.show_total_period = false;
-				notes->options->show_nr_samples = true;
+				symbol_conf.show_nr_samples = true;
-			} else if (notes->options->show_nr_samples)
+			} else if (symbol_conf.show_nr_samples)
-				notes->options->show_nr_samples = false;
+				symbol_conf.show_nr_samples = false;
 			else
-				notes->options->show_total_period = true;
+				symbol_conf.show_total_period = true;
 			annotation__update_column_widths(notes);
 			continue;
 		case 'c':

tools/perf/ui/gtk/annotate.c+1−1

@@ -174,7 +174,7 @@ static int symbol__gtk_annotate(struct map_symbol ms, struct evsel evsel, · 173 unmodified lines
174	if (ms->map->dso->annotate_warned)	174	if (ms->map->dso->annotate_warned)
175	return -1;	175	return -1;
176		176
177	err = symbol__annotate(ms, evsel, 0, &annotation__default_options, NULL);	177	err = symbol__annotate(ms, evsel, &annotation__default_options, NULL);
178	if (err) {	178	if (err) {
179	char msg[BUFSIZ];	179	char msg[BUFSIZ];
180	symbol__strerror_disassemble(ms, err, msg, sizeof(msg));	180	symbol__strerror_disassemble(ms, err, msg, sizeof(msg));

tools/perf/util/annotate.c+75−119

@@ -1143,93 +1143,70 @@ out: · 1142 unmodified lines
1143	}	1143	}
1144		1144
1145	struct annotate_args {	1145	struct annotate_args {
1146	size_t privsize;	1146	struct arch *arch;
1147	struct arch *arch;	1147	struct map_symbol ms;
1148	struct map_symbol ms;	1148	struct evsel *evsel;
1149	struct evsel *evsel;
1150	struct annotation_options *options;	1149	struct annotation_options *options;
1151	s64 offset;	1150	s64 offset;
1152	char *line;	1151	char *line;
1153	int line_nr;	1152	int line_nr;
1154	};	1153	};
1155		1154
1156	static void annotation_line__delete(struct annotation_line *al)	1155	static void annotation_line__init(struct annotation_line *al,
		1156	struct annotate_args *args,
		1157	int nr)
1157	{	1158	{
1158	void ptr = (void ) al - al->privsize;	1159	al->offset = args->offset;
		1160	al->line = strdup(args->line);
		1161	al->line_nr = args->line_nr;
		1162	al->data_nr = nr;
		1163	}
1159		1164
		1165	static void annotation_line__exit(struct annotation_line *al)
		1166	{
1160	free_srcline(al->path);	1167	free_srcline(al->path);
1161	zfree(&al->line);	1168	zfree(&al->line);
1162	free(ptr);
1163	}	1169	}
1164		1170
1165	/*	1171	static size_t disasm_line_size(int nr)
1166	* Allocating the annotation line data with following
1167	* structure:
1168	*
1169	* --------------------------------------
1170	* private space \| struct annotation_line
1171	* --------------------------------------
1172	*
1173	* Size of the private space is stored in 'struct annotation_line'.
1174	*
1175	*/
1176	static struct annotation_line *
1177	annotation_line__new(struct annotate_args *args, size_t privsize)
1178	{	1172	{
1179	struct annotation_line *al;	1173	struct annotation_line *al;
1180	struct evsel *evsel = args->evsel;
1181	size_t size = privsize + sizeof(*al);
1182	int nr = 1;
1183
1184	if (perf_evsel__is_group_event(evsel))
1185	nr = evsel->core.nr_members;
1186		1174
1187	size += sizeof(al->data[0]) * nr;	1175	return (sizeof(struct disasm_line) + (sizeof(al->data[0]) * nr));
1188
1189	al = zalloc(size);
1190	if (al) {
1191	al = (void *) al + privsize;
1192	al->privsize = privsize;
1193	al->offset = args->offset;
1194	al->line = strdup(args->line);
1195	al->line_nr = args->line_nr;
1196	al->data_nr = nr;
1197	}
1198
1199	return al;
1200	}	1176	}
1201		1177
1202	/*	1178	/*
1203	* Allocating the disasm annotation line data with	1179	* Allocating the disasm annotation line data with
1204	* following structure:	1180	* following structure:
1205	*	1181	*
1206	* ------------------------------------------------------------	1182	* -------------------------------------------
1207	* privsize space \| struct disasm_line \| struct annotation_line	1183	* struct disasm_line \| struct annotation_line
1208	* ------------------------------------------------------------	1184	* -------------------------------------------
1209	*	1185	*
1210	* We have 'struct annotation_line' member as last member	1186	* We have 'struct annotation_line' member as last member
1211	* of 'struct disasm_line' to have an easy access.	1187	* of 'struct disasm_line' to have an easy access.
1212	*
1213	*/	1188	*/
1214	static struct disasm_line disasm_line__new(struct annotate_args args)	1189	static struct disasm_line disasm_line__new(struct annotate_args args)
1215	{	1190	{
1216	struct disasm_line *dl = NULL;	1191	struct disasm_line *dl = NULL;
1217	struct annotation_line *al;	1192	int nr = 1;
1218	size_t privsize = args->privsize + offsetof(struct disasm_line, al);
1219		1193
1220	al = annotation_line__new(args, privsize);	1194	if (perf_evsel__is_group_event(args->evsel))
1221	if (al != NULL) {	1195	nr = args->evsel->core.nr_members;
1222	dl = disasm_line(al);
1223		1196
1224	if (dl->al.line == NULL)	1197	dl = zalloc(disasm_line_size(nr));
1225	goto out_delete;	1198	if (!dl)
		1199	return NULL;
1226		1200
1227	if (args->offset != -1) {	1201	annotation_line__init(&dl->al, args, nr);
1228	if (disasm_line__parse(dl->al.line, &dl->ins.name, &dl->ops.raw) < 0)	1202	if (dl->al.line == NULL)
1229	goto out_free_line;	1203	goto out_delete;
1230		1204
1231	disasm_line__init_ins(dl, args->arch, &args->ms);	1205	if (args->offset != -1) {
1232	}	1206	if (disasm_line__parse(dl->al.line, &dl->ins.name, &dl->ops.raw) < 0)
		1207	goto out_free_line;
		1208
		1209	disasm_line__init_ins(dl, args->arch, &args->ms);
1233	}	1210	}
1234		1211
1235	return dl;	1212	return dl;
@@ -1248,7 +1225,8 @@ void disasm_line__free(struct disasm_line *dl) · 12 unmodified lines
1248	else	1225	else
1249	ins__delete(&dl->ops);	1226	ins__delete(&dl->ops);
1250	zfree(&dl->ins.name);	1227	zfree(&dl->ins.name);
1251	annotation_line__delete(&dl->al);	1228	annotation_line__exit(&dl->al);
		1229	free(dl);
1252	}	1230	}
1253		1231
1254	int disasm_line__scnprintf(struct disasm_line dl, char bf, size_t size, bool raw, int max_ins_name)	1232	int disasm_line__scnprintf(struct disasm_line dl, char bf, size_t size, bool raw, int max_ins_name)
@@ -2149,13 +2127,12 @@ void symbol__calc_percent(struct symbol sym, struct evsel evsel) · 894 unmodified lines
2149	annotation__calc_percent(notes, evsel, symbol__size(sym));	2127	annotation__calc_percent(notes, evsel, symbol__size(sym));
2150	}	2128	}
2151		2129
2152	int symbol__annotate(struct map_symbol ms, struct evsel evsel, size_t privsize,	2130	int symbol__annotate(struct map_symbol ms, struct evsel evsel,
2153	struct annotation_options options, struct arch *parch)	2131	struct annotation_options options, struct arch *parch)
2154	{	2132	{
2155	struct symbol *sym = ms->sym;	2133	struct symbol *sym = ms->sym;
2156	struct annotation *notes = symbol__annotation(sym);	2134	struct annotation *notes = symbol__annotation(sym);
2157	struct annotate_args args = {	2135	struct annotate_args args = {
2158	.privsize = privsize,
2159	.evsel = evsel,	2136	.evsel = evsel,
2160	.options = options,	2137	.options = options,
2161	};	2138	};
@@ -2644,6 +2621,8 @@ void annotation__set_offsets(struct annotation *notes, s64 size) · 482 unmodified lines
2644	struct annotation_line *al;	2621	struct annotation_line *al;
2645		2622
2646	notes->max_line_len = 0;	2623	notes->max_line_len = 0;
		2624	notes->nr_entries = 0;
		2625	notes->nr_asm_entries = 0;
2647		2626
2648	list_for_each_entry(al, &notes->src->source, node) {	2627	list_for_each_entry(al, &notes->src->source, node) {
2649	size_t line_len = strlen(al->line);	2628	size_t line_len = strlen(al->line);
@@ -2790,7 +2769,7 @@ int symbol__tty_annotate(struct map_symbol ms, struct evsel evsel, · 140 unmodified lines
2790	struct symbol *sym = ms->sym;	2769	struct symbol *sym = ms->sym;
2791	struct rb_root source_line = RB_ROOT;	2770	struct rb_root source_line = RB_ROOT;
2792		2771
2793	if (symbol__annotate(ms, evsel, 0, opts, NULL) < 0)	2772	if (symbol__annotate(ms, evsel, opts, NULL) < 0)
2794	return -1;	2773	return -1;
2795		2774
2796	symbol__calc_percent(sym, evsel);	2775	symbol__calc_percent(sym, evsel);
@@ -2915,9 +2894,9 @@ static void __annotation_line__write(struct annotation_line *al, struct annotati · 118 unmodified lines
2915	percent = annotation_data__percent(&al->data[i], percent_type);	2894	percent = annotation_data__percent(&al->data[i], percent_type);
2916		2895
2917	obj__set_percent_color(obj, percent, current_entry);	2896	obj__set_percent_color(obj, percent, current_entry);
2918	if (notes->options->show_total_period) {	2897	if (symbol_conf.show_total_period) {
2919	obj__printf(obj, "%11" PRIu64 " ", al->data[i].he.period);	2898	obj__printf(obj, "%11" PRIu64 " ", al->data[i].he.period);
2920	} else if (notes->options->show_nr_samples) {	2899	} else if (symbol_conf.show_nr_samples) {
2921	obj__printf(obj, "%6" PRIu64 " ",	2900	obj__printf(obj, "%6" PRIu64 " ",
2922	al->data[i].he.nr_samples);	2901	al->data[i].he.nr_samples);
2923	} else {	2902	} else {
@@ -2931,8 +2910,8 @@ static void __annotation_line__write(struct annotation_line *al, struct annotati · 7 unmodified lines
2931	obj__printf(obj, "%-*s", pcnt_width, " ");	2910	obj__printf(obj, "%-*s", pcnt_width, " ");
2932	else {	2911	else {
2933	obj__printf(obj, "%-*s", pcnt_width,	2912	obj__printf(obj, "%-*s", pcnt_width,
2934	notes->options->show_total_period ? "Period" :	2913	symbol_conf.show_total_period ? "Period" :
2935	notes->options->show_nr_samples ? "Samples" : "Percent");	2914	symbol_conf.show_nr_samples ? "Samples" : "Percent");
2936	}	2915	}
2937	}	2916	}
2938		2917
@@ -3070,7 +3049,7 @@ int symbol__annotate2(struct map_symbol ms, struct evsel evsel, · 131 unmodified lines
3070	if (perf_evsel__is_group_event(evsel))	3049	if (perf_evsel__is_group_event(evsel))
3071	nr_pcnt = evsel->core.nr_members;	3050	nr_pcnt = evsel->core.nr_members;
3072		3051
3073	err = symbol__annotate(ms, evsel, 0, options, parch);	3052	err = symbol__annotate(ms, evsel, options, parch);
3074	if (err)	3053	if (err)
3075	goto out_free_offsets;	3054	goto out_free_offsets;
3076		3055
@@ -3094,69 +3073,46 @@ out_free_offsets: · 17 unmodified lines
3094	return err;	3073	return err;
3095	}	3074	}
3096		3075
3097	#define ANNOTATION__CFG(n) \	3076	static int annotation__config(const char var, const char value, void *data)
3098	{ .name = #n, .value = &annotation__default_options.n, }
3099
3100	/*
3101	* Keep the entries sorted, they are bsearch'ed
3102	*/
3103	static struct annotation_config {
3104	const char *name;
3105	void *value;
3106	} annotation__configs[] = {
3107	ANNOTATION__CFG(hide_src_code),
3108	ANNOTATION__CFG(jump_arrows),
3109	ANNOTATION__CFG(offset_level),
3110	ANNOTATION__CFG(show_linenr),
3111	ANNOTATION__CFG(show_nr_jumps),
3112	ANNOTATION__CFG(show_nr_samples),
3113	ANNOTATION__CFG(show_total_period),
3114	ANNOTATION__CFG(use_offset),
3115	};
3116
3117	#undef ANNOTATION__CFG
3118
3119	static int annotation_config__cmp(const void name, const void cfgp)
3120	{
3121	const struct annotation_config *cfg = cfgp;
3122
3123	return strcmp(name, cfg->name);
3124	}
3125
3126	static int annotation__config(const char var, const char value,
3127	void *data __maybe_unused)
3128	{	3077	{
3129	struct annotation_config *cfg;	3078	struct annotation_options *opt = data;
3130	const char *name;
3131		3079
3132	if (!strstarts(var, "annotate."))	3080	if (!strstarts(var, "annotate."))
3133	return 0;	3081	return 0;
3134		3082
3135	name = var + 9;	3083	if (!strcmp(var, "annotate.offset_level")) {
3136	cfg = bsearch(name, annotation__configs, ARRAY_SIZE(annotation__configs),	3084	perf_config_u8(&opt->offset_level, "offset_level", value);
3137	sizeof(struct annotation_config), annotation_config__cmp);	3085
3138		3086	if (opt->offset_level > ANNOTATION__MAX_OFFSET_LEVEL)
3139	if (cfg == NULL)	3087	opt->offset_level = ANNOTATION__MAX_OFFSET_LEVEL;
3140	pr_debug("%s variable unknown, ignoring...", var);	3088	else if (opt->offset_level < ANNOTATION__MIN_OFFSET_LEVEL)
3141	else if (strcmp(var, "annotate.offset_level") == 0) {	3089	opt->offset_level = ANNOTATION__MIN_OFFSET_LEVEL;
3142	perf_config_int(cfg->value, name, value);	3090	} else if (!strcmp(var, "annotate.hide_src_code")) {
3143		3091	opt->hide_src_code = perf_config_bool("hide_src_code", value);
3144	if ((int )cfg->value > ANNOTATION__MAX_OFFSET_LEVEL)	3092	} else if (!strcmp(var, "annotate.jump_arrows")) {
3145	(int )cfg->value = ANNOTATION__MAX_OFFSET_LEVEL;	3093	opt->jump_arrows = perf_config_bool("jump_arrows", value);
3146	else if ((int )cfg->value < ANNOTATION__MIN_OFFSET_LEVEL)	3094	} else if (!strcmp(var, "annotate.show_linenr")) {
3147	(int )cfg->value = ANNOTATION__MIN_OFFSET_LEVEL;	3095	opt->show_linenr = perf_config_bool("show_linenr", value);
		3096	} else if (!strcmp(var, "annotate.show_nr_jumps")) {
		3097	opt->show_nr_jumps = perf_config_bool("show_nr_jumps", value);
		3098	} else if (!strcmp(var, "annotate.show_nr_samples")) {
		3099	symbol_conf.show_nr_samples = perf_config_bool("show_nr_samples",
		3100	value);
		3101	} else if (!strcmp(var, "annotate.show_total_period")) {
		3102	symbol_conf.show_total_period = perf_config_bool("show_total_period",
		3103	value);
		3104	} else if (!strcmp(var, "annotate.use_offset")) {
		3105	opt->use_offset = perf_config_bool("use_offset", value);
3148	} else {	3106	} else {
3149	(bool )cfg->value = perf_config_bool(name, value);	3107	pr_debug("%s variable unknown, ignoring...", var);
3150	}	3108	}
		3109
3151	return 0;	3110	return 0;
3152	}	3111	}
3153		3112
3154	void annotation_config__init(void)	3113	void annotation_config__init(struct annotation_options *opt)
3155	{	3114	{
3156	perf_config(annotation__config, NULL);	3115	perf_config(annotation__config, opt);
3157
3158	annotation__default_options.show_total_period = symbol_conf.show_total_period;
3159	annotation__default_options.show_nr_samples = symbol_conf.show_nr_samples;
3160	}	3116	}
3161		3117
3162	static unsigned int parse_percent_type(char str1, char str2)	3118	static unsigned int parse_percent_type(char str1, char str2)

tools/perf/util/annotate.h+3−6

 	     full_path,
 	     show_linenr,
 	     show_nr_jumps,
-	     show_nr_samples,
-	     show_total_period,
 	     show_minmax_cycle,
 	     show_asm_raw,
 	     annotate_src;
 	u64			 cycles;
 	u64			 cycles_max;
 	u64			 cycles_min;
-	size_t			 privsize;
 	char			*path;
 	u32			 idx;
 	int			 idx_asm;
 static inline int annotation__pcnt_width(struct annotation *notes)
 {
-	return (notes->options->show_total_period ? 12 : 7) * notes->nr_events;
+	return (symbol_conf.show_total_period ? 12 : 7) * notes->nr_events;
 }
 static inline bool annotation_line__filter(struct annotation_line *al, struct annotation *notes)
 void symbol__annotate_zero_histograms(struct symbol *sym);
 int symbol__annotate(struct map_symbol *ms,
-		     struct evsel *evsel, size_t privsize,
+		     struct evsel *evsel,
 		     struct annotation_options *options,
 		     struct arch **parch);
 int symbol__annotate2(struct map_symbol *ms,
 }
 #endif
-void annotation_config__init(void);
+void annotation_config__init(struct annotation_options *opt);
 int annotate_parse_percent_type(const struct option *opt, const char *_str,
 				int unset);

tools/perf/util/auxtrace.c+21−1

@@ -629,8 +629,10 @@ int auxtrace_record__options(struct auxtrace_record *itr, · 628 unmodified lines
629	struct evlist *evlist,	629	struct evlist *evlist,
630	struct record_opts *opts)	630	struct record_opts *opts)
631	{	631	{
632	if (itr)	632	if (itr) {
		633	itr->evlist = evlist;
633	return itr->recording_options(itr, evlist, opts);	634	return itr->recording_options(itr, evlist, opts);
		635	}
634	return 0;	636	return 0;
635	}	637	}
636		638
@@ -664,6 +666,24 @@ int auxtrace_parse_snapshot_options(struct auxtrace_record *itr, · 27 unmodified lines
664	return -EINVAL;	666	return -EINVAL;
665	}	667	}
666		668
		669	int auxtrace_record__read_finish(struct auxtrace_record *itr, int idx)
		670	{
		671	struct evsel *evsel;
		672
		673	if (!itr->evlist \|\| !itr->pmu)
		674	return -EINVAL;
		675
		676	evlist__for_each_entry(itr->evlist, evsel) {
		677	if (evsel->core.attr.type == itr->pmu->type) {
		678	if (evsel->disabled)
		679	return 0;
		680	return perf_evlist__enable_event_idx(itr->evlist, evsel,
		681	idx);
		682	}
		683	}
		684	return -EINVAL;
		685	}
		686
667	/*	687	/*
668	* Event record size is 16-bit which results in a maximum size of about 64KiB.	688	* Event record size is 16-bit which results in a maximum size of about 64KiB.
669	* Allow about 4KiB for the rest of the sample record, to give a maximum	689	* Allow about 4KiB for the rest of the sample record, to give a maximum

tools/perf/util/auxtrace.h+6−0

 struct perf_record_auxtrace_error;
 struct perf_record_auxtrace_info;
 struct events_stats;
+struct perf_pmu;
 enum auxtrace_error_type {
        PERF_AUXTRACE_ERROR_ITRACE  = 1,
  * @read_finish: called after reading from an auxtrace mmap
  * @alignment: alignment (if any) for AUX area data
  * @default_aux_sample_size: default sample size for --aux sample option
+ * @pmu: associated pmu
+ * @evlist: selected events list
  */
 struct auxtrace_record {
 	int (*recording_options)(struct auxtrace_record *itr,
 	int (*read_finish)(struct auxtrace_record *itr, int idx);
 	unsigned int alignment;
 	unsigned int default_aux_sample_size;
+	struct perf_pmu *pmu;
+	struct evlist *evlist;
 };
 /**
 				   struct auxtrace_mmap *mm,
 				   unsigned char *data, u64 *head, u64 *old);
 u64 auxtrace_record__reference(struct auxtrace_record *itr);
+int auxtrace_record__read_finish(struct auxtrace_record *itr, int idx);
 int auxtrace_index__auxtrace_event(struct list_head *head, union perf_event *event,
 				   off_t file_offset);

tools/perf/util/config.c+12−0

@@ -374,6 +374,18 @@ int perf_config_int(int dest, const char name, const char *value) · 373 unmodified lines
374	return 0;	374	return 0;
375	}	375	}
376		376
		377	int perf_config_u8(u8 dest, const char name, const char *value)
		378	{
		379	long ret = 0;
		380
		381	if (!perf_parse_long(value, &ret)) {
		382	bad_config(name);
		383	return -1;
		384	}
		385	*dest = ret;
		386	return 0;
		387	}
		388
377	static int perf_config_bool_or_int(const char name, const char value, int *is_bool)	389	static int perf_config_bool_or_int(const char name, const char value, int *is_bool)
378	{	390	{
379	int ret;	391	int ret;

tools/perf/util/config.h+1−0

@@ -29,6 +29,7 @@ typedef int (config_fn_t)(const char , const char , void ); · 28 unmodified lines
29	int perf_default_config(const char , const char , void *);	29	int perf_default_config(const char , const char , void *);
30	int perf_config(config_fn_t fn, void *);	30	int perf_config(config_fn_t fn, void *);
31	int perf_config_int(int dest, const char , const char *);	31	int perf_config_int(int dest, const char , const char *);
		32	int perf_config_u8(u8 dest, const char name, const char *value);
32	int perf_config_u64(u64 dest, const char , const char *);	33	int perf_config_u64(u64 dest, const char , const char *);
33	int perf_config_bool(const char , const char );	34	int perf_config_bool(const char , const char );
34	int config_error_nonbool(const char *);	35	int config_error_nonbool(const char *);

tools/perf/util/probe-file.c+24−4

 		p = strchr(ent->s, ':');
 		if ((p && strfilter__compare(filter, p + 1)) ||
 		    strfilter__compare(filter, ent->s)) {
-			strlist__add(plist, ent->s);
+			ret = strlist__add(plist, ent->s);
+			if (ret == -ENOMEM) {
+				pr_err("strlist__add failed with -ENOMEM\n");
+				goto out;
+			}
 			ret = 0;
 		}
 	}
+out:
 	strlist__delete(namelist);
 	return ret;
 				ret = -EINVAL;
 				goto out;
 			}
-			strlist__add(entry->tevlist, buf);
+			ret = strlist__add(entry->tevlist, buf);
+			if (ret == -ENOMEM) {
+				pr_err("strlist__add failed with -ENOMEM\n");
+				goto out;
+			}
 		}
 	}
 out:
 		command = synthesize_probe_trace_command(&tevs[i]);
 		if (!command)
 			goto out_err;
-		strlist__add(entry->tevlist, command);
+		ret = strlist__add(entry->tevlist, command);
+		if (ret == -ENOMEM) {
+			pr_err("strlist__add failed with -ENOMEM\n");
+			goto out_err;
+		}
 		free(command);
 	}
 	list_add_tail(&entry->node, &pcache->entries);
 			break;
 		}
-		strlist__add(entry->tevlist, buf);
+		ret = strlist__add(entry->tevlist, buf);
 		free(buf);
 		entry = NULL;
+		if (ret == -ENOMEM) {
+			pr_err("strlist__add failed with -ENOMEM\n");
+			break;
+		}
 	}
 	if (entry) {
 		list_del_init(&entry->node);

tools/testing/selftests/lkdtm/.gitignore+2−0

@@ -0,0 +1,2 @@
	1	*.sh
	2	!run.sh

tools/testing/selftests/pidfd/.gitignore+1−0

@@ -2,4 +2,5 @@ pidfd_open_test · 1 unmodified line
2	pidfd_poll_test	2	pidfd_poll_test
3	pidfd_test	3	pidfd_test
4	pidfd_wait	4	pidfd_wait
		5	pidfd_fdinfo_test
5	pidfd_getfd_test	6	pidfd_getfd_test