Add registers and definitions to support 1000BASE-T1. This includes the PCS Control and Status registers (3.2304 and 3.2305) as well as some missing bits on the PMA/PMD extended ability register (1.18) and PMA/PMD CTRL (1.2100) register.
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| @@ -82,6 +82,8 @@ · 81 unmodified lines | ||
| 82 | 82 | #define MDIO_AN_10BT1_AN_CTRL 526 /* 10BASE-T1 AN control register */ |
| 83 | 83 | #define MDIO_AN_10BT1_AN_STAT 527 /* 10BASE-T1 AN status register */ |
| 84 | 84 | #define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */ |
| 85 | +#define MDIO_PCS_1000BT1_CTRL 2304 /* 1000BASE-T1 PCS control register */ | |
| 86 | +#define MDIO_PCS_1000BT1_STAT 2305 /* 1000BASE-T1 PCS status register */ | |
| 85 | 87 | |
| 86 | 88 | /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ |
| 87 | 89 | #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ |
| @@ -332,6 +334,8 @@ · 244 unmodified lines | ||
| 332 | 334 | #define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */ |
| 333 | 335 | |
| 334 | 336 | /* BASE-T1 PMA/PMD extended ability register. */ |
| 337 | +#define MDIO_PMA_PMD_BT1_B100_ABLE 0x0001 /* 100BASE-T1 Ability */ | |
| 338 | +#define MDIO_PMA_PMD_BT1_B1000_ABLE 0x0002 /* 1000BASE-T1 Ability */ | |
| 335 | 339 | #define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 /* 10BASE-T1L Ability */ |
| 336 | 340 | |
| 337 | 341 | /* BASE-T1 auto-negotiation advertisement register [15:0] */ |
| @@ -373,7 +377,19 @@ · 35 unmodified lines | ||
| 373 | 377 | #define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 /* 10BASE-T1L LP EEE ability advertisement */ |
| 374 | 378 | |
| 375 | 379 | /* BASE-T1 PMA/PMD control register */ |
| 376 | −#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */ | |
| 380 | +#define MDIO_PMA_PMD_BT1_CTRL_STRAP 0x000F /* Type selection (Strap) */ | |
| 381 | +#define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000 0x0001 /* Select 1000BASE-T1 */ | |
| 382 | +#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */ | |
| 383 | + | |
| 384 | +/* 1000BASE-T1 PCS control register */ | |
| 385 | +#define MDIO_PCS_1000BT1_CTRL_LOW_POWER 0x0800 /* Low power mode */ | |
| 386 | +#define MDIO_PCS_1000BT1_CTRL_DISABLE_TX 0x4000 /* Global PMA transmit disable */ | |
| 387 | +#define MDIO_PCS_1000BT1_CTRL_RESET 0x8000 /* Software reset value */ | |
| 388 | + | |
| 389 | +/* 1000BASE-T1 PCS status register */ | |
| 390 | +#define MDIO_PCS_1000BT1_STAT_LINK 0x0004 /* PCS Link is up */ | |
| 391 | +#define MDIO_PCS_1000BT1_STAT_FAULT 0x0080 /* There is a fault condition */ | |
| 392 | + | |
| 377 | 393 | |
| 378 | 394 | /* EEE Supported/Advertisement/LP Advertisement registers. |
| 379 | 395 | * |