Use DesignWare helper functions to configure Fast Training Sequence. Drop the respective code in the driver.
Unified · Split
| @@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[]; · 50 unmodified lines | |||
| 51 | #define ACK_N_FTS_MASK GENMASK(15, 8) | 51 | #define ACK_N_FTS_MASK GENMASK(15, 8) |
| 52 | #define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK) | 52 | #define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK) |
| 53 | 53 | ||
| 54 | #define FAST_TRAINING_SEQ_MASK GENMASK(7, 0) | ||
| 55 | #define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK) | ||
| 56 | |||
| 57 | /* ARTPEC-6 specific registers */ | 54 | /* ARTPEC-6 specific registers */ |
| 58 | #define PCIECFG 0x18 | 55 | #define PCIECFG 0x18 |
| 59 | #define PCIECFG_DBG_OEN BIT(24) | 56 | #define PCIECFG_DBG_OEN BIT(24) |
| @@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie) · 253 unmodified lines | |||
| 313 | * Set the Number of Fast Training Sequences that the core | 310 | * Set the Number of Fast Training Sequences that the core |
| 314 | * advertises as its N_FTS during Gen2 or Gen3 link training. | 311 | * advertises as its N_FTS during Gen2 or Gen3 link training. |
| 315 | */ | 312 | */ |
| 316 | val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); | 313 | dw_pcie_link_set_n_fts(pci, 180); |
| 317 | val &= ~FAST_TRAINING_SEQ_MASK; | ||
| 318 | val |= FAST_TRAINING_SEQ(180); | ||
| 319 | dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); | ||
| 320 | } | 314 | } |
| 321 | 315 | ||
| 322 | static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie) | 316 | static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie) |