History

Merge tag 'pci-v6.9-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull PCI updates from Bjorn Helgaas: "Enumeration: - Consolidate interrupt related code in irq.c (Ilpo Järvinen) - Reduce kernel size by replacing sysfs resource macros with functions (Ilpo Järvinen) - Reduce kernel size by compiling sysfs support only when CONFIG_SYSFS=y (Lukas Wunner) - Avoid using Extended Tags on 3ware-9650SE Root Port to work around an apparent hardware defect (Jörg Wedekind) Resource management: - Fix an MMIO mapping leak in pci_iounmap() (Philipp Stanner) - Move pci_iomap.c and other PCI-specific devres code to drivers/pci (Philipp Stanner) - Consolidate PCI devres code in devres.c (Philipp Stanner) Power management: - Avoid D3cold on Asus B1400 PCI-NVMe bridge, where firmware doesn't know how to return correctly to D0, and remove previous quirk that wasn't as specific (Daniel Drake) - Allow runtime PM when the driver enables it but doesn't need any runtime PM callbacks (Raag Jadav) - Drain runtime-idle callbacks before driver removal to avoid races between .remove() and .runtime_idle(), which caused intermittent page faults when the rtsx .runtime_idle() accessed registers that its .remove() had already unmapped (Rafael J. Wysocki) Virtualization: - Avoid Secondary Bus Reset on LSI FW643 so it can be assigned to VMs with VFIO, e.g., for professional audio software on many Apple machines, at the cost of leaking state between VMs (Edmund Raile) Error handling: - Print all logged TLP Prefixes, not just the first, after AER or DPC errors (Ilpo Järvinen) - Quirk the DPC PIO log size for Intel Raptor Lake Root Ports, which still don't advertise a legal size (Paul Menzel) - Ignore expected DPC Surprise Down errors on hot removal (Smita Koralahalli) - Block runtime suspend while handling AER errors to avoid races that prevent the device form being resumed from D3hot (Stanislaw Gruszka) Peer-to-peer DMA: - Use atomic XA allocation in RCU read section (Christophe JAILLET) ASPM: - Collect bits of ASPM-related code that we need even without CONFIG_PCIEASPM into aspm.c (David E. Box) - Save/restore L1 PM Substates config for suspend/resume (David E. Box) - Update save_save when ASPM config is changed, so a .slot_reset() during error recovery restores the changed config, not the .probe()-time config (Vidya Sagar) Endpoint framework: - Refactor and improve pci_epf_alloc_space() API (Niklas Cassel) - Clean up endpoint BAR descriptions (Niklas Cassel) - Fix ntb_register_device() name leak in error path (Yang Yingliang) - Return actual error code for pci_vntb_probe() failure (Yang Yingliang) Broadcom STB PCIe controller driver: - Fix MDIO write polling, which previously never waited for completion (Jonathan Bell) Cadence PCIe endpoint driver: - Clear the ARI "Next Function Number" of last function (Jasko-EXT Wojciech) Freescale i.MX6 PCIe controller driver: - Simplify by replacing switch statements with function pointers for different hardware variants (Frank Li) - Simplify by using clk_bulk*() API (Frank Li) - Remove redundant DT clock and reg/reg-name details (Frank Li) - Add i.MX95 DT and driver support for both Root Complex and Endpoint mode (Frank Li) Microsoft Hyper-V host bridge driver: - Reduce memory usage by limiting ring buffer size to 16KB instead of 4 pages (Michael Kelley) Qualcomm PCIe controller driver: - Add X1E80100 DT and driver support (Abel Vesa) - Add DT 'required-opps' for SoCs that require a minimum performance level (Johan Hovold) - Make DT 'msi-map-mask' optional, depending on how MSI interrupts are mapped (Johan Hovold) - Disable ASPM L0s for sc8280xp, sa8540p and sa8295p because the PHY configuration isn't tuned correctly for L0s (Johan Hovold) - Split dt-binding qcom,pcie.yaml into qcom,pcie-common.yaml and separate files for SA8775p, SC7280, SC8180X, SC8280XP, SM8150, SM8250, SM8350, SM8450, SM8550 for easier reviewing (Krzysztof Kozlowski) - Enable BDF to SID translation by disabling bypass mode (Manivannan Sadhasivam) - Add endpoint MHI support for Snapdragon SA8775P SoC (Mrinmay Sarkar) Synopsys DesignWare PCIe controller driver: - Allocate 64-bit MSI address if no 32-bit address is available (Ajay Agarwal) - Fix endpoint Resizable BAR to actually advertise the required 1MB size (Niklas Cassel) MicroSemi Switchtec management driver: - Release resources if the .probe() fails (Christophe JAILLET) Miscellaneous: - Make pcie_port_bus_type const (Ricardo B. Marliere)" * tag 'pci-v6.9-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (77 commits) PCI/ASPM: Update save_state when configuration changes PCI/ASPM: Disable L1 before configuring L1 Substates PCI/ASPM: Call pci_save_ltr_state() from pci_save_pcie_state() PCI/ASPM: Save L1 PM Substates Capability for suspend/resume PCI: hv: Fix ring buffer size calculation PCI: dwc: endpoint: Fix advertised resizable BAR size PCI: cadence: Clear the ARI Capability Next Function Number of the last function PCI: dwc: Strengthen the MSI address allocation logic PCI: brcmstb: Fix broken brcm_pcie_mdio_write() polling PCI: qcom: Add X1E80100 PCIe support dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller PCI: qcom: Enable BDF to SID translation properly PCI/AER: Generalize TLP Header Log reading PCI/AER: Use explicit register size for PCI_ERR_CAP PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p dt-bindings: PCI: qcom: Do not require 'msi-map-mask' dt-bindings: PCI: qcom: Allow 'required-opps' PCI/AER: Block runtime suspend when handling errors PCI/ASPM: Move pci_save_ltr_state() to aspm.c PCI/ASPM: Always build aspm.c ...

Linus Torvalds committed 2 years ago

Commit 705c1da2 parents 66fd6d0 aabf71773 files · +3793 −1771Browse files

Unified · Split

73 files
  1. Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats +9 −9
  2. Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +1 −16
  3. Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +38 −8
  4. Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +39 −10
  5. Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +100 −0
  6. Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml +166 −0
  7. Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +166 −0
  8. Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml +170 −0
  9. Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml +180 −0
  10. Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml +158 −0
  11. Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml +173 −0
  12. Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml +184 −0
  13. Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +178 −0
  14. Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml +171 −0
  15. Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +165 −0
  16. Documentation/devicetree/bindings/pci/qcom,pcie.yaml +3 −375
  17. Documentation/driver-api/device-io.rst +0 −3
  18. Documentation/driver-api/pci/pci.rst +6 −0
  19. MAINTAINERS +0 −1
  20. arch/x86/pci/fixup.c +48 −0
  21. drivers/acpi/sleep.c +0 −12
  22. drivers/firmware/efi/cper.c +2 −2
  23. drivers/ntb/core.c +7 −1
  24. drivers/pci/Kconfig +5 −0
  25. drivers/pci/Makefile +4 −3
  26. drivers/pci/controller/cadence/pcie-cadence-ep.c +13 −1
  27. drivers/pci/controller/cadence/pcie-cadence.h +6 −0
  28. drivers/pci/controller/dwc/pci-imx6.c +354 −276
  29. drivers/pci/controller/dwc/pci-keystone.c +6 −6
  30. drivers/pci/controller/dwc/pci-layerscape-ep.c +4 −1
  31. drivers/pci/controller/dwc/pcie-designware-ep.c +6 −1
  32. drivers/pci/controller/dwc/pcie-designware-host.c +13 −8
  33. drivers/pci/controller/dwc/pcie-keembay.c +6 −2
  34. drivers/pci/controller/dwc/pcie-qcom.c +40 −2
  35. drivers/pci/controller/dwc/pcie-rcar-gen4.c +3 −1
  36. drivers/pci/controller/dwc/pcie-tegra194.c +7 −3
  37. drivers/pci/controller/dwc/pcie-uniphier-ep.c +12 −3
  38. drivers/pci/controller/pci-hyperv.c +2 −1
  39. drivers/pci/controller/pcie-brcmstb.c +1 −1
  40. drivers/pci/controller/pcie-rcar-ep.c +9 −5
  41. drivers/pci/devres.c +448 −0
  42. drivers/pci/endpoint/functions/pci-epf-mhi.c +19 −2
  43. drivers/pci/endpoint/functions/pci-epf-ntb.c +3 −3
  44. drivers/pci/endpoint/functions/pci-epf-test.c +5 −16
  45. drivers/pci/endpoint/functions/pci-epf-vntb.c +5 −20
  46. drivers/pci/endpoint/pci-epc-core.c +10 −15
  47. drivers/pci/endpoint/pci-epf-core.c +16 −4
  48. drivers/pci/iomap.c +1 −4
  49. drivers/pci/irq.c +204 −0
  50. drivers/pci/mmap.c +29 −0
  51. drivers/pci/p2pdma.c +1 −1
  52. drivers/pci/pci-driver.c +9 −14
  53. drivers/pci/pci-sysfs.c +75 −92
  54. drivers/pci/pci.c +38 −458
  55. drivers/pci/pci.h +48 −7
  56. drivers/pci/pcie/Makefile +1 −1
  57. drivers/pci/pcie/aer.c +6 −14
  58. drivers/pci/pcie/aspm.c +267 −1
  59. drivers/pci/pcie/dpc.c +65 −11
  60. drivers/pci/pcie/err.c +20 −0
  61. drivers/pci/pcie/portdrv.h +1 −1
  62. drivers/pci/probe.c +5 −61
  63. drivers/pci/quirks.c +11 −0
  64. drivers/pci/setup-irq.c +0 −64
  65. drivers/pci/switch/switchtec.c +3 −1
  66. include/linux/aer.h +5 −6
  67. include/linux/pci-epc.h +33 −6
  68. include/linux/pci-epf.h +3 −1
  69. include/linux/pci.h +1 −1
  70. include/ras/ras_event.h +5 −5
  71. lib/Kconfig +0 −3
  72. lib/Makefile +0 −1
  73. lib/devres.c +1 −207
Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats+9−9
@@ -11,7 +11,7 @@ saw any problems). · 10 unmodified lines
1111
1212 What: /sys/bus/pci/devices/<dev>/aer_dev_correctable
1313 Date: July 2018
14−KernelVersion: 4.19.0
14+KernelVersion: 4.19.0
1515 Contact: linux-pci@vger.kernel.org, rajatja@google.com
1616 Description: List of correctable errors seen and reported by this
1717 PCI device using ERR_COR. Note that since multiple errors may
@@ -32,7 +32,7 @@ Description: List of correctable errors seen and reported by this · 14 unmodified lines
3232
3333 What: /sys/bus/pci/devices/<dev>/aer_dev_fatal
3434 Date: July 2018
35−KernelVersion: 4.19.0
35+KernelVersion: 4.19.0
3636 Contact: linux-pci@vger.kernel.org, rajatja@google.com
3737 Description: List of uncorrectable fatal errors seen and reported by this
3838 PCI device using ERR_FATAL. Note that since multiple errors may
@@ -62,7 +62,7 @@ Description: List of uncorrectable fatal errors seen and reported by this · 23 unmodified lines
6262
6363 What: /sys/bus/pci/devices/<dev>/aer_dev_nonfatal
6464 Date: July 2018
65−KernelVersion: 4.19.0
65+KernelVersion: 4.19.0
6666 Contact: linux-pci@vger.kernel.org, rajatja@google.com
6767 Description: List of uncorrectable nonfatal errors seen and reported by this
6868 PCI device using ERR_NONFATAL. Note that since multiple errors
@@ -100,20 +100,20 @@ collectors) that are AER capable. These indicate the number of error messages as · 31 unmodified lines
100100 device, so these counters include them and are thus cumulative of all the error
101101 messages on the PCI hierarchy originating at that root port.
102102
103−What: /sys/bus/pci/devices/<dev>/aer_stats/aer_rootport_total_err_cor
103+What: /sys/bus/pci/devices/<dev>/aer_rootport_total_err_cor
104104 Date: July 2018
105−KernelVersion: 4.19.0
105+KernelVersion: 4.19.0
106106 Contact: linux-pci@vger.kernel.org, rajatja@google.com
107107 Description: Total number of ERR_COR messages reported to rootport.
108108
109−What: /sys/bus/pci/devices/<dev>/aer_stats/aer_rootport_total_err_fatal
109+What: /sys/bus/pci/devices/<dev>/aer_rootport_total_err_fatal
110110 Date: July 2018
111−KernelVersion: 4.19.0
111+KernelVersion: 4.19.0
112112 Contact: linux-pci@vger.kernel.org, rajatja@google.com
113113 Description: Total number of ERR_FATAL messages reported to rootport.
114114
115−What: /sys/bus/pci/devices/<dev>/aer_stats/aer_rootport_total_err_nonfatal
115+What: /sys/bus/pci/devices/<dev>/aer_rootport_total_err_nonfatal
116116 Date: July 2018
117−KernelVersion: 4.19.0
117+KernelVersion: 4.19.0
118118 Contact: linux-pci@vger.kernel.org, rajatja@google.com
119119 Description: Total number of ERR_NONFATAL messages reported to rootport.
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml+1−16
@@ -150,22 +150,6 @@ allOf: · 149 unmodified lines
150150 - {}
151151 - const: pcie_phy
152152 - const: pcie_aux
153− - if:
154− properties:
155− compatible:
156− not:
157− contains:
158− enum:
159− - fsl,imx6sx-pcie
160− - fsl,imx8mq-pcie
161− - fsl,imx6sx-pcie-ep
162− - fsl,imx8mq-pcie-ep
163− then:
164− properties:
165− clocks:
166− maxItems: 3
167− clock-names:
168− maxItems: 3
169153
170154 - if:
171155 properties:
@@ -223,6 +207,7 @@ allOf: · 51 unmodified lines
223207 - fsl,imx6sx-pcie
224208 - fsl,imx6q-pcie
225209 - fsl,imx6qp-pcie
210+ - fsl,imx95-pcie
226211 - fsl,imx6sx-pcie-ep
227212 - fsl,imx6q-pcie-ep
228213 - fsl,imx6qp-pcie-ep
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml+38−8
@@ -22,14 +22,7 @@ properties: · 21 unmodified lines
2222 - fsl,imx8mm-pcie-ep
2323 - fsl,imx8mq-pcie-ep
2424 - fsl,imx8mp-pcie-ep
25−
26− reg:
27− minItems: 2
28−
29− reg-names:
30− items:
31− - const: dbi
32− - const: addr_space
25+ - fsl,imx95-pcie-ep
3326
3427 clocks:
3528 minItems: 3
@@ -62,11 +55,48 @@ required: · 26 unmodified lines
6255 allOf:
6356 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
6457 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
58+ - if:
59+ properties:
60+ compatible:
61+ enum:
62+ - fsl,imx8mm-pcie-ep
63+ - fsl,imx8mq-pcie-ep
64+ - fsl,imx8mp-pcie-ep
65+ then:
66+ properties:
67+ reg:
68+ minItems: 2
69+ maxItems: 2
70+ reg-names:
71+ items:
72+ - const: dbi
73+ - const: addr_space
74+
75+ - if:
76+ properties:
77+ compatible:
78+ enum:
79+ - fsl,imx95-pcie-ep
80+ then:
81+ properties:
82+ reg:
83+ minItems: 6
84+ maxItems: 6
85+ reg-names:
86+ items:
87+ - const: dbi
88+ - const: atu
89+ - const: dbi2
90+ - const: app
91+ - const: dma
92+ - const: addr_space
93+
6594 - if:
6695 properties:
6796 compatible:
6897 enum:
6998 - fsl,imx8mq-pcie-ep
99+ - fsl,imx95-pcie-ep
70100 then:
71101 properties:
72102 clocks:
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml+39−10
@@ -29,16 +29,7 @@ properties: · 28 unmodified lines
2929 - fsl,imx8mq-pcie
3030 - fsl,imx8mm-pcie
3131 - fsl,imx8mp-pcie
32−
33− reg:
34− items:
35− - description: Data Bus Interface (DBI) registers.
36− - description: PCIe configuration space region.
37−
38− reg-names:
39− items:
40− - const: dbi
41− - const: config
32+ - fsl,imx95-pcie
4233
4334 clocks:
4435 minItems: 3
@@ -90,6 +81,43 @@ required: · 45 unmodified lines
9081 allOf:
9182 - $ref: /schemas/pci/snps,dw-pcie.yaml#
9283 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
84+ - if:
85+ properties:
86+ compatible:
87+ enum:
88+ - fsl,imx6q-pcie
89+ - fsl,imx6sx-pcie
90+ - fsl,imx6qp-pcie
91+ - fsl,imx7d-pcie
92+ - fsl,imx8mq-pcie
93+ - fsl,imx8mm-pcie
94+ - fsl,imx8mp-pcie
95+ then:
96+ properties:
97+ reg:
98+ maxItems: 2
99+ reg-names:
100+ items:
101+ - const: dbi
102+ - const: config
103+
104+ - if:
105+ properties:
106+ compatible:
107+ enum:
108+ - fsl,imx95-pcie
109+ then:
110+ properties:
111+ reg:
112+ minItems: 4
113+ maxItems: 4
114+ reg-names:
115+ items:
116+ - const: dbi
117+ - const: config
118+ - const: atu
119+ - const: app
120+
93121 - if:
94122 properties:
95123 compatible:
@@ -111,6 +139,7 @@ allOf: · 15 unmodified lines
111139 compatible:
112140 enum:
113141 - fsl,imx8mq-pcie
142+ - fsl,imx95-pcie
114143 then:
115144 properties:
116145 clocks:
Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml+100−0
@@ -0,0 +1,100 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm PCI Express Root Complex Common Properties
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+properties:
14+ reg:
15+ minItems: 4
16+ maxItems: 6
17+
18+ reg-names:
19+ minItems: 4
20+ maxItems: 6
21+
22+ interrupts:
23+ minItems: 1
24+ maxItems: 8
25+
26+ interrupt-names:
27+ minItems: 1
28+ maxItems: 8
29+
30+ iommu-map:
31+ minItems: 1
32+ maxItems: 16
33+
34+ clocks:
35+ minItems: 3
36+ maxItems: 13
37+
38+ clock-names:
39+ minItems: 3
40+ maxItems: 13
41+
42+ dma-coherent: true
43+
44+ interconnects:
45+ maxItems: 2
46+
47+ interconnect-names:
48+ items:
49+ - const: pcie-mem
50+ - const: cpu-pcie
51+
52+ phys:
53+ maxItems: 1
54+
55+ phy-names:
56+ items:
57+ - const: pciephy
58+
59+ power-domains:
60+ maxItems: 1
61+
62+ required-opps:
63+ maxItems: 1
64+
65+ resets:
66+ minItems: 1
67+ maxItems: 12
68+
69+ reset-names:
70+ minItems: 1
71+ maxItems: 12
72+
73+ perst-gpios:
74+ description: GPIO controlled connection to PERST# signal
75+ maxItems: 1
76+
77+ wake-gpios:
78+ description: GPIO controlled connection to WAKE# signal
79+ maxItems: 1
80+
81+required:
82+ - reg
83+ - reg-names
84+ - interrupt-map-mask
85+ - interrupt-map
86+ - clocks
87+ - clock-names
88+
89+anyOf:
90+ - required:
91+ - interrupts
92+ - interrupt-names
93+ - "#interrupt-cells"
94+ - required:
95+ - msi-map
96+
97+allOf:
98+ - $ref: /schemas/pci/pci-bus.yaml#
99+
100+additionalProperties: true
Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml+166−0
@@ -0,0 +1,166 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm SA8775p PCI Express Root Complex
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+description:
14+ Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
15+ DesignWare PCIe IP.
16+
17+properties:
18+ compatible:
19+ const: qcom,pcie-sa8775p
20+
21+ reg:
22+ minItems: 6
23+ maxItems: 6
24+
25+ reg-names:
26+ items:
27+ - const: parf # Qualcomm specific registers
28+ - const: dbi # DesignWare PCIe registers
29+ - const: elbi # External local bus interface registers
30+ - const: atu # ATU address space
31+ - const: config # PCIe configuration space
32+ - const: mhi # MHI registers
33+
34+ clocks:
35+ minItems: 5
36+ maxItems: 5
37+
38+ clock-names:
39+ items:
40+ - const: aux # Auxiliary clock
41+ - const: cfg # Configuration clock
42+ - const: bus_master # Master AXI clock
43+ - const: bus_slave # Slave AXI clock
44+ - const: slave_q2a # Slave Q2A clock
45+
46+ interrupts:
47+ minItems: 8
48+ maxItems: 8
49+
50+ interrupt-names:
51+ items:
52+ - const: msi0
53+ - const: msi1
54+ - const: msi2
55+ - const: msi3
56+ - const: msi4
57+ - const: msi5
58+ - const: msi6
59+ - const: msi7
60+
61+ resets:
62+ maxItems: 1
63+
64+ reset-names:
65+ items:
66+ - const: pci
67+
68+required:
69+ - interconnects
70+ - interconnect-names
71+
72+allOf:
73+ - $ref: qcom,pcie-common.yaml#
74+
75+unevaluatedProperties: false
76+
77+examples:
78+ - |
79+ #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
80+ #include <dt-bindings/clock/qcom,rpmh.h>
81+ #include <dt-bindings/gpio/gpio.h>
82+ #include <dt-bindings/interrupt-controller/arm-gic.h>
83+ #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
84+
85+ soc {
86+ #address-cells = <2>;
87+ #size-cells = <2>;
88+
89+ pcie@1c00000 {
90+ compatible = "qcom,pcie-sa8775p";
91+ reg = <0x0 0x01c00000 0x0 0x3000>,
92+ <0x0 0x40000000 0x0 0xf20>,
93+ <0x0 0x40000f20 0x0 0xa8>,
94+ <0x0 0x40001000 0x0 0x4000>,
95+ <0x0 0x40100000 0x0 0x100000>,
96+ <0x0 0x01c03000 0x0 0x1000>;
97+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
98+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
99+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
100+
101+ bus-range = <0x00 0xff>;
102+ device_type = "pci";
103+ linux,pci-domain = <0>;
104+ num-lanes = <2>;
105+
106+ #address-cells = <3>;
107+ #size-cells = <2>;
108+
109+ assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
110+ assigned-clock-rates = <19200000>;
111+
112+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
113+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
114+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
115+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
116+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
117+ clock-names = "aux",
118+ "cfg",
119+ "bus_master",
120+ "bus_slave",
121+ "slave_q2a";
122+
123+ dma-coherent;
124+
125+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
126+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
127+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
128+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
129+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
130+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
131+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
132+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
133+ interrupt-names = "msi0",
134+ "msi1",
135+ "msi2",
136+ "msi3",
137+ "msi4",
138+ "msi5",
139+ "msi6",
140+ "msi7";
141+ #interrupt-cells = <1>;
142+ interrupt-map-mask = <0 0 0 0x7>;
143+ interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
144+ <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
145+ <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
146+ <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
147+
148+ interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
149+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
150+ interconnect-names = "pcie-mem", "cpu-pcie";
151+
152+ iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
153+ <0x100 &pcie_smmu 0x0001 0x1>;
154+
155+ phys = <&pcie0_phy>;
156+ phy-names = "pciephy";
157+
158+ power-domains = <&gcc PCIE_0_GDSC>;
159+
160+ resets = <&gcc GCC_PCIE_0_BCR>;
161+ reset-names = "pci";
162+
163+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
164+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
165+ };
166+ };
Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml+166−0
@@ -0,0 +1,166 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm SC7280 PCI Express Root Complex
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+description:
14+ Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
15+ DesignWare PCIe IP.
16+
17+properties:
18+ compatible:
19+ const: qcom,pcie-sc7280
20+
21+ reg:
22+ minItems: 5
23+ maxItems: 6
24+
25+ reg-names:
26+ minItems: 5
27+ items:
28+ - const: parf # Qualcomm specific registers
29+ - const: dbi # DesignWare PCIe registers
30+ - const: elbi # External local bus interface registers
31+ - const: atu # ATU address space
32+ - const: config # PCIe configuration space
33+ - const: mhi # MHI registers
34+
35+ clocks:
36+ minItems: 13
37+ maxItems: 13
38+
39+ clock-names:
40+ items:
41+ - const: pipe # PIPE clock
42+ - const: pipe_mux # PIPE MUX
43+ - const: phy_pipe # PIPE output clock
44+ - const: ref # REFERENCE clock
45+ - const: aux # Auxiliary clock
46+ - const: cfg # Configuration clock
47+ - const: bus_master # Master AXI clock
48+ - const: bus_slave # Slave AXI clock
49+ - const: slave_q2a # Slave Q2A clock
50+ - const: tbu # PCIe TBU clock
51+ - const: ddrss_sf_tbu # PCIe SF TBU clock
52+ - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
53+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
54+
55+ interrupts:
56+ maxItems: 1
57+
58+ interrupt-names:
59+ items:
60+ - const: msi
61+
62+ resets:
63+ maxItems: 1
64+
65+ reset-names:
66+ items:
67+ - const: pci
68+
69+ vddpe-3v3-supply:
70+ description: PCIe endpoint power supply
71+
72+allOf:
73+ - $ref: qcom,pcie-common.yaml#
74+
75+unevaluatedProperties: false
76+
77+examples:
78+ - |
79+ #include <dt-bindings/clock/qcom,gcc-sc7280.h>
80+ #include <dt-bindings/clock/qcom,rpmh.h>
81+ #include <dt-bindings/gpio/gpio.h>
82+ #include <dt-bindings/interrupt-controller/arm-gic.h>
83+
84+ soc {
85+ #address-cells = <2>;
86+ #size-cells = <2>;
87+
88+ pcie@1c08000 {
89+ compatible = "qcom,pcie-sc7280";
90+ reg = <0 0x01c08000 0 0x3000>,
91+ <0 0x40000000 0 0xf1d>,
92+ <0 0x40000f20 0 0xa8>,
93+ <0 0x40001000 0 0x1000>,
94+ <0 0x40100000 0 0x100000>;
95+ reg-names = "parf", "dbi", "elbi", "atu", "config";
96+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
97+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
98+
99+ bus-range = <0x00 0xff>;
100+ device_type = "pci";
101+ linux,pci-domain = <1>;
102+ num-lanes = <2>;
103+
104+ #address-cells = <3>;
105+ #size-cells = <2>;
106+
107+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
108+ assigned-clock-rates = <19200000>;
109+
110+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
111+ <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
112+ <&pcie1_phy>,
113+ <&rpmhcc RPMH_CXO_CLK>,
114+ <&gcc GCC_PCIE_1_AUX_CLK>,
115+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
116+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
117+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
118+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
119+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
120+ <&gcc GCC_DDRSS_PCIE_SF_CLK>,
121+ <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
122+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
123+
124+ clock-names = "pipe",
125+ "pipe_mux",
126+ "phy_pipe",
127+ "ref",
128+ "aux",
129+ "cfg",
130+ "bus_master",
131+ "bus_slave",
132+ "slave_q2a",
133+ "tbu",
134+ "ddrss_sf_tbu",
135+ "aggre0",
136+ "aggre1";
137+
138+ dma-coherent;
139+
140+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
141+ interrupt-names = "msi";
142+ #interrupt-cells = <1>;
143+ interrupt-map-mask = <0 0 0 0x7>;
144+ interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
145+ <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
146+ <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
147+ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
148+
149+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
150+ <0x100 &apps_smmu 0x1c81 0x1>;
151+
152+ phys = <&pcie1_phy>;
153+ phy-names = "pciephy";
154+
155+ pinctrl-names = "default";
156+ pinctrl-0 = <&pcie1_clkreq_n>;
157+
158+ power-domains = <&gcc GCC_PCIE_1_GDSC>;
159+
160+ resets = <&gcc GCC_PCIE_1_BCR>;
161+ reset-names = "pci";
162+
163+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
164+ vddpe-3v3-supply = <&pp3300_ssd>;
165+ };
166+ };
Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml+170−0
@@ -0,0 +1,170 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm SC8180x PCI Express Root Complex
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+description:
14+ Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
15+ DesignWare PCIe IP.
16+
17+properties:
18+ compatible:
19+ const: qcom,pcie-sc8180x
20+
21+ reg:
22+ minItems: 5
23+ maxItems: 6
24+
25+ reg-names:
26+ minItems: 5
27+ items:
28+ - const: parf # Qualcomm specific registers
29+ - const: dbi # DesignWare PCIe registers
30+ - const: elbi # External local bus interface registers
31+ - const: atu # ATU address space
32+ - const: config # PCIe configuration space
33+ - const: mhi # MHI registers
34+
35+ clocks:
36+ minItems: 8
37+ maxItems: 8
38+
39+ clock-names:
40+ items:
41+ - const: pipe # PIPE clock
42+ - const: aux # Auxiliary clock
43+ - const: cfg # Configuration clock
44+ - const: bus_master # Master AXI clock
45+ - const: bus_slave # Slave AXI clock
46+ - const: slave_q2a # Slave Q2A clock
47+ - const: ref # REFERENCE clock
48+ - const: tbu # PCIe TBU clock
49+
50+ interrupts:
51+ minItems: 8
52+ maxItems: 8
53+
54+ interrupt-names:
55+ items:
56+ - const: msi0
57+ - const: msi1
58+ - const: msi2
59+ - const: msi3
60+ - const: msi4
61+ - const: msi5
62+ - const: msi6
63+ - const: msi7
64+
65+ resets:
66+ maxItems: 1
67+
68+ reset-names:
69+ items:
70+ - const: pci
71+
72+allOf:
73+ - $ref: qcom,pcie-common.yaml#
74+
75+unevaluatedProperties: false
76+
77+examples:
78+ - |
79+ #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
80+ #include <dt-bindings/interconnect/qcom,sc8180x.h>
81+ #include <dt-bindings/interrupt-controller/arm-gic.h>
82+
83+ soc {
84+ #address-cells = <2>;
85+ #size-cells = <2>;
86+
87+ pcie@1c00000 {
88+ compatible = "qcom,pcie-sc8180x";
89+ reg = <0 0x01c00000 0 0x3000>,
90+ <0 0x60000000 0 0xf1d>,
91+ <0 0x60000f20 0 0xa8>,
92+ <0 0x60001000 0 0x1000>,
93+ <0 0x60100000 0 0x100000>;
94+ reg-names = "parf",
95+ "dbi",
96+ "elbi",
97+ "atu",
98+ "config";
99+ ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
100+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
101+
102+ bus-range = <0x00 0xff>;
103+ device_type = "pci";
104+ linux,pci-domain = <0>;
105+ num-lanes = <2>;
106+
107+ #address-cells = <3>;
108+ #size-cells = <2>;
109+
110+ assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
111+ assigned-clock-rates = <19200000>;
112+
113+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
114+ <&gcc GCC_PCIE_0_AUX_CLK>,
115+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
116+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
117+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
118+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
119+ <&gcc GCC_PCIE_0_CLKREF_CLK>,
120+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
121+ clock-names = "pipe",
122+ "aux",
123+ "cfg",
124+ "bus_master",
125+ "bus_slave",
126+ "slave_q2a",
127+ "ref",
128+ "tbu";
129+
130+ dma-coherent;
131+
132+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
133+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
134+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
135+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
136+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
137+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
138+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
139+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
140+ interrupt-names = "msi0",
141+ "msi1",
142+ "msi2",
143+ "msi3",
144+ "msi4",
145+ "msi5",
146+ "msi6",
147+ "msi7";
148+ #interrupt-cells = <1>;
149+ interrupt-map-mask = <0 0 0 0x7>;
150+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
151+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
152+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
153+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
154+
155+ interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
156+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
157+ interconnect-names = "pcie-mem", "cpu-pcie";
158+
159+ iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
160+ <0x100 &apps_smmu 0x1d81 0x1>;
161+
162+ phys = <&pcie0_phy>;
163+ phy-names = "pciephy";
164+
165+ power-domains = <&gcc PCIE_0_GDSC>;
166+
167+ resets = <&gcc GCC_PCIE_0_BCR>;
168+ reset-names = "pci";
169+ };
170+ };
Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml+180−0
@@ -0,0 +1,180 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm SC8280XP PCI Express Root Complex
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+description:
14+ Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
15+ DesignWare PCIe IP.
16+
17+properties:
18+ compatible:
19+ enum:
20+ - qcom,pcie-sa8540p
21+ - qcom,pcie-sc8280xp
22+
23+ reg:
24+ minItems: 5
25+ maxItems: 6
26+
27+ reg-names:
28+ minItems: 5
29+ items:
30+ - const: parf # Qualcomm specific registers
31+ - const: dbi # DesignWare PCIe registers
32+ - const: elbi # External local bus interface registers
33+ - const: atu # ATU address space
34+ - const: config # PCIe configuration space
35+ - const: mhi # MHI registers
36+
37+ clocks:
38+ minItems: 8
39+ maxItems: 9
40+
41+ clock-names:
42+ minItems: 8
43+ items:
44+ - const: aux # Auxiliary clock
45+ - const: cfg # Configuration clock
46+ - const: bus_master # Master AXI clock
47+ - const: bus_slave # Slave AXI clock
48+ - const: slave_q2a # Slave Q2A clock
49+ - const: ddrss_sf_tbu # PCIe SF TBU clock
50+ - const: noc_aggr_4 # NoC aggregate 4 clock
51+ - const: noc_aggr_south_sf # NoC aggregate South SF clock
52+ - const: cnoc_qx # Configuration NoC QX clock
53+
54+ resets:
55+ maxItems: 1
56+
57+ reset-names:
58+ items:
59+ - const: pci
60+
61+ vddpe-3v3-supply:
62+ description: A phandle to the PCIe endpoint power supply
63+
64+required:
65+ - interconnects
66+ - interconnect-names
67+
68+allOf:
69+ - $ref: qcom,pcie-common.yaml#
70+ - if:
71+ properties:
72+ compatible:
73+ contains:
74+ enum:
75+ - qcom,pcie-sc8280xp
76+ then:
77+ properties:
78+ interrupts:
79+ minItems: 4
80+ maxItems: 4
81+ interrupt-names:
82+ items:
83+ - const: msi0
84+ - const: msi1
85+ - const: msi2
86+ - const: msi3
87+ else:
88+ properties:
89+ interrupts:
90+ maxItems: 1
91+ interrupt-names:
92+ items:
93+ - const: msi
94+
95+unevaluatedProperties: false
96+
97+examples:
98+ - |
99+ #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
100+ #include <dt-bindings/gpio/gpio.h>
101+ #include <dt-bindings/interconnect/qcom,sc8280xp.h>
102+ #include <dt-bindings/interrupt-controller/arm-gic.h>
103+
104+ soc {
105+ #address-cells = <2>;
106+ #size-cells = <2>;
107+
108+ pcie@1c20000 {
109+ compatible = "qcom,pcie-sc8280xp";
110+ reg = <0x0 0x01c20000 0x0 0x3000>,
111+ <0x0 0x3c000000 0x0 0xf1d>,
112+ <0x0 0x3c000f20 0x0 0xa8>,
113+ <0x0 0x3c001000 0x0 0x1000>,
114+ <0x0 0x3c100000 0x0 0x100000>,
115+ <0x0 0x01c23000 0x0 0x1000>;
116+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
117+ ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
118+ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
119+
120+ bus-range = <0x00 0xff>;
121+ device_type = "pci";
122+ linux,pci-domain = <2>;
123+ num-lanes = <4>;
124+
125+ #address-cells = <3>;
126+ #size-cells = <2>;
127+
128+ assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
129+ assigned-clock-rates = <19200000>;
130+ clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
131+ <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
132+ <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
133+ <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
134+ <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
135+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
136+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
137+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
138+ clock-names = "aux",
139+ "cfg",
140+ "bus_master",
141+ "bus_slave",
142+ "slave_q2a",
143+ "ddrss_sf_tbu",
144+ "noc_aggr_4",
145+ "noc_aggr_south_sf";
146+
147+ dma-coherent;
148+
149+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
150+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
151+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
152+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
153+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
154+ #interrupt-cells = <1>;
155+ interrupt-map-mask = <0 0 0 0x7>;
156+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
157+ <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
158+ <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
159+ <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
160+
161+ interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
162+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
163+ interconnect-names = "pcie-mem", "cpu-pcie";
164+
165+ phys = <&pcie2a_phy>;
166+ phy-names = "pciephy";
167+
168+ pinctrl-0 = <&pcie2a_default>;
169+ pinctrl-names = "default";
170+
171+ power-domains = <&gcc PCIE_2A_GDSC>;
172+
173+ resets = <&gcc GCC_PCIE_2A_BCR>;
174+ reset-names = "pci";
175+
176+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
177+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
178+ vddpe-3v3-supply = <&vreg_nvme>;
179+ };
180+ };
Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml+158−0
@@ -0,0 +1,158 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm SM8150 PCI Express Root Complex
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+description:
14+ Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
15+ DesignWare PCIe IP.
16+
17+properties:
18+ compatible:
19+ const: qcom,pcie-sm8150
20+
21+ reg:
22+ minItems: 5
23+ maxItems: 6
24+
25+ reg-names:
26+ minItems: 5
27+ items:
28+ - const: parf # Qualcomm specific registers
29+ - const: dbi # DesignWare PCIe registers
30+ - const: elbi # External local bus interface registers
31+ - const: atu # ATU address space
32+ - const: config # PCIe configuration space
33+ - const: mhi # MHI registers
34+
35+ clocks:
36+ minItems: 8
37+ maxItems: 8
38+
39+ clock-names:
40+ items:
41+ - const: pipe # PIPE clock
42+ - const: aux # Auxiliary clock
43+ - const: cfg # Configuration clock
44+ - const: bus_master # Master AXI clock
45+ - const: bus_slave # Slave AXI clock
46+ - const: slave_q2a # Slave Q2A clock
47+ - const: tbu # PCIe TBU clock
48+ - const: ref # REFERENCE clock
49+
50+ interrupts:
51+ minItems: 8
52+ maxItems: 8
53+
54+ interrupt-names:
55+ items:
56+ - const: msi0
57+ - const: msi1
58+ - const: msi2
59+ - const: msi3
60+ - const: msi4
61+ - const: msi5
62+ - const: msi6
63+ - const: msi7
64+
65+ resets:
66+ maxItems: 1
67+
68+ reset-names:
69+ items:
70+ - const: pci
71+
72+allOf:
73+ - $ref: qcom,pcie-common.yaml#
74+
75+unevaluatedProperties: false
76+
77+examples:
78+ - |
79+ #include <dt-bindings/clock/qcom,gcc-sm8150.h>
80+ #include <dt-bindings/clock/qcom,rpmh.h>
81+ #include <dt-bindings/gpio/gpio.h>
82+ #include <dt-bindings/interconnect/qcom,sm8150.h>
83+ #include <dt-bindings/interrupt-controller/arm-gic.h>
84+
85+ soc {
86+ #address-cells = <2>;
87+ #size-cells = <2>;
88+ pcie@1c00000 {
89+ compatible = "qcom,pcie-sm8150";
90+ reg = <0 0x01c00000 0 0x3000>,
91+ <0 0x60000000 0 0xf1d>,
92+ <0 0x60000f20 0 0xa8>,
93+ <0 0x60001000 0 0x1000>,
94+ <0 0x60100000 0 0x100000>;
95+ reg-names = "parf", "dbi", "elbi", "atu", "config";
96+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
97+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
98+
99+ bus-range = <0x00 0xff>;
100+ device_type = "pci";
101+ linux,pci-domain = <0>;
102+ num-lanes = <1>;
103+
104+ #address-cells = <3>;
105+ #size-cells = <2>;
106+
107+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
108+ <&gcc GCC_PCIE_0_AUX_CLK>,
109+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
110+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
111+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
112+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
113+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
114+ <&rpmhcc RPMH_CXO_CLK>;
115+ clock-names = "pipe",
116+ "aux",
117+ "cfg",
118+ "bus_master",
119+ "bus_slave",
120+ "slave_q2a",
121+ "tbu",
122+ "ref";
123+
124+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
125+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
126+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
127+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
128+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
129+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
130+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
131+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
132+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
133+ "msi4", "msi5", "msi6", "msi7";
134+ #interrupt-cells = <1>;
135+ interrupt-map-mask = <0 0 0 0x7>;
136+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
137+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
138+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
139+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
140+
141+ iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
142+ <0x100 &apps_smmu 0x1d81 0x1>;
143+
144+ phys = <&pcie0_phy>;
145+ phy-names = "pciephy";
146+
147+ pinctrl-0 = <&pcie0_default_state>;
148+ pinctrl-names = "default";
149+
150+ power-domains = <&gcc PCIE_0_GDSC>;
151+
152+ resets = <&gcc GCC_PCIE_0_BCR>;
153+ reset-names = "pci";
154+
155+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
156+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
157+ };
158+ };
Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml+173−0
@@ -0,0 +1,173 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm SM8250 PCI Express Root Complex
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+description:
14+ Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys
15+ DesignWare PCIe IP.
16+
17+properties:
18+ compatible:
19+ const: qcom,pcie-sm8250
20+
21+ reg:
22+ minItems: 5
23+ maxItems: 6
24+
25+ reg-names:
26+ minItems: 5
27+ items:
28+ - const: parf # Qualcomm specific registers
29+ - const: dbi # DesignWare PCIe registers
30+ - const: elbi # External local bus interface registers
31+ - const: atu # ATU address space
32+ - const: config # PCIe configuration space
33+ - const: mhi # MHI registers
34+
35+ clocks:
36+ minItems: 8
37+ maxItems: 9
38+
39+ clock-names:
40+ # Unfortunately the "optional" ref clock is used in the middle of the list
41+ oneOf:
42+ - items:
43+ - const: pipe # PIPE clock
44+ - const: aux # Auxiliary clock
45+ - const: cfg # Configuration clock
46+ - const: bus_master # Master AXI clock
47+ - const: bus_slave # Slave AXI clock
48+ - const: slave_q2a # Slave Q2A clock
49+ - const: ref # REFERENCE clock
50+ - const: tbu # PCIe TBU clock
51+ - const: ddrss_sf_tbu # PCIe SF TBU clock
52+ - items:
53+ - const: pipe # PIPE clock
54+ - const: aux # Auxiliary clock
55+ - const: cfg # Configuration clock
56+ - const: bus_master # Master AXI clock
57+ - const: bus_slave # Slave AXI clock
58+ - const: slave_q2a # Slave Q2A clock
59+ - const: tbu # PCIe TBU clock
60+ - const: ddrss_sf_tbu # PCIe SF TBU clock
61+
62+ interrupts:
63+ minItems: 8
64+ maxItems: 8
65+
66+ interrupt-names:
67+ items:
68+ - const: msi0
69+ - const: msi1
70+ - const: msi2
71+ - const: msi3
72+ - const: msi4
73+ - const: msi5
74+ - const: msi6
75+ - const: msi7
76+
77+ resets:
78+ maxItems: 1
79+
80+ reset-names:
81+ items:
82+ - const: pci
83+
84+allOf:
85+ - $ref: qcom,pcie-common.yaml#
86+
87+unevaluatedProperties: false
88+
89+examples:
90+ - |
91+ #include <dt-bindings/clock/qcom,gcc-sm8250.h>
92+ #include <dt-bindings/gpio/gpio.h>
93+ #include <dt-bindings/interconnect/qcom,sm8250.h>
94+ #include <dt-bindings/interrupt-controller/arm-gic.h>
95+
96+ soc {
97+ #address-cells = <2>;
98+ #size-cells = <2>;
99+
100+ pcie@1c00000 {
101+ compatible = "qcom,pcie-sm8250";
102+ reg = <0 0x01c00000 0 0x3000>,
103+ <0 0x60000000 0 0xf1d>,
104+ <0 0x60000f20 0 0xa8>,
105+ <0 0x60001000 0 0x1000>,
106+ <0 0x60100000 0 0x100000>,
107+ <0 0x01c03000 0 0x1000>;
108+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
109+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
110+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
111+
112+ bus-range = <0x00 0xff>;
113+ device_type = "pci";
114+ linux,pci-domain = <0>;
115+ num-lanes = <1>;
116+
117+ #address-cells = <3>;
118+ #size-cells = <2>;
119+
120+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
121+ <&gcc GCC_PCIE_0_AUX_CLK>,
122+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
123+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
124+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
125+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
126+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
127+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
128+ clock-names = "pipe",
129+ "aux",
130+ "cfg",
131+ "bus_master",
132+ "bus_slave",
133+ "slave_q2a",
134+ "tbu",
135+ "ddrss_sf_tbu";
136+
137+ dma-coherent;
138+
139+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
140+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
141+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
142+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
143+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
144+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
145+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
146+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
147+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
148+ "msi4", "msi5", "msi6", "msi7";
149+ #interrupt-cells = <1>;
150+ interrupt-map-mask = <0 0 0 0x7>;
151+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
152+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
153+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
154+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
155+
156+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
157+ <0x100 &apps_smmu 0x1c01 0x1>;
158+
159+ phys = <&pcie0_phy>;
160+ phy-names = "pciephy";
161+
162+ pinctrl-0 = <&pcie0_default_state>;
163+ pinctrl-names = "default";
164+
165+ power-domains = <&gcc PCIE_0_GDSC>;
166+
167+ resets = <&gcc GCC_PCIE_0_BCR>;
168+ reset-names = "pci";
169+
170+ perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
171+ wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
172+ };
173+ };
Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml+184−0
@@ -0,0 +1,184 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm SM8350 PCI Express Root Complex
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+description:
14+ Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys
15+ DesignWare PCIe IP.
16+
17+properties:
18+ compatible:
19+ const: qcom,pcie-sm8350
20+
21+ reg:
22+ minItems: 5
23+ maxItems: 6
24+
25+ reg-names:
26+ minItems: 5
27+ items:
28+ - const: parf # Qualcomm specific registers
29+ - const: dbi # DesignWare PCIe registers
30+ - const: elbi # External local bus interface registers
31+ - const: atu # ATU address space
32+ - const: config # PCIe configuration space
33+ - const: mhi # MHI registers
34+
35+ clocks:
36+ minItems: 8
37+ maxItems: 9
38+
39+ clock-names:
40+ minItems: 8
41+ items:
42+ - const: aux # Auxiliary clock
43+ - const: cfg # Configuration clock
44+ - const: bus_master # Master AXI clock
45+ - const: bus_slave # Slave AXI clock
46+ - const: slave_q2a # Slave Q2A clock
47+ - const: tbu # PCIe TBU clock
48+ - const: ddrss_sf_tbu # PCIe SF TBU clock
49+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
50+ - const: aggre0 # Aggre NoC PCIe0 AXI clock
51+
52+ interrupts:
53+ minItems: 8
54+ maxItems: 8
55+
56+ interrupt-names:
57+ items:
58+ - const: msi0
59+ - const: msi1
60+ - const: msi2
61+ - const: msi3
62+ - const: msi4
63+ - const: msi5
64+ - const: msi6
65+ - const: msi7
66+
67+ resets:
68+ maxItems: 1
69+
70+ reset-names:
71+ items:
72+ - const: pci
73+
74+oneOf:
75+ - properties:
76+ interrupts:
77+ maxItems: 1
78+ interrupt-names:
79+ items:
80+ - const: msi
81+
82+ - properties:
83+ interrupts:
84+ minItems: 8
85+ interrupt-names:
86+ items:
87+ - const: msi0
88+ - const: msi1
89+ - const: msi2
90+ - const: msi3
91+ - const: msi4
92+ - const: msi5
93+ - const: msi6
94+ - const: msi7
95+
96+allOf:
97+ - $ref: qcom,pcie-common.yaml#
98+
99+unevaluatedProperties: false
100+
101+examples:
102+ - |
103+ #include <dt-bindings/clock/qcom,gcc-sm8350.h>
104+ #include <dt-bindings/gpio/gpio.h>
105+ #include <dt-bindings/interconnect/qcom,sm8350.h>
106+ #include <dt-bindings/interrupt-controller/arm-gic.h>
107+
108+ soc {
109+ #address-cells = <2>;
110+ #size-cells = <2>;
111+
112+ pcie@1c00000 {
113+ compatible = "qcom,pcie-sm8350";
114+ reg = <0 0x01c00000 0 0x3000>,
115+ <0 0x60000000 0 0xf1d>,
116+ <0 0x60000f20 0 0xa8>,
117+ <0 0x60001000 0 0x1000>,
118+ <0 0x60100000 0 0x100000>;
119+ reg-names = "parf", "dbi", "elbi", "atu", "config";
120+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
121+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
122+
123+ bus-range = <0x00 0xff>;
124+ device_type = "pci";
125+ linux,pci-domain = <0>;
126+ num-lanes = <1>;
127+
128+ #address-cells = <3>;
129+ #size-cells = <2>;
130+
131+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
132+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
133+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
134+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
135+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
136+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
137+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
138+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
139+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
140+ clock-names = "aux",
141+ "cfg",
142+ "bus_master",
143+ "bus_slave",
144+ "slave_q2a",
145+ "tbu",
146+ "ddrss_sf_tbu",
147+ "aggre1",
148+ "aggre0";
149+
150+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
151+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
152+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
153+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
154+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
155+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
156+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
157+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
158+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
159+ "msi4", "msi5", "msi6", "msi7";
160+ #interrupt-cells = <1>;
161+ interrupt-map-mask = <0 0 0 0x7>;
162+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
163+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
164+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
165+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
166+
167+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
168+ <0x100 &apps_smmu 0x1c01 0x1>;
169+
170+ phys = <&pcie0_phy>;
171+ phy-names = "pciephy";
172+
173+ pinctrl-0 = <&pcie0_default_state>;
174+ pinctrl-names = "default";
175+
176+ power-domains = <&gcc PCIE_0_GDSC>;
177+
178+ resets = <&gcc GCC_PCIE_0_BCR>;
179+ reset-names = "pci";
180+
181+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
182+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
183+ };
184+ };
Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml+178−0
@@ -0,0 +1,178 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm SM8450 PCI Express Root Complex
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+description:
14+ Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
15+ DesignWare PCIe IP.
16+
17+properties:
18+ compatible:
19+ enum:
20+ - qcom,pcie-sm8450-pcie0
21+ - qcom,pcie-sm8450-pcie1
22+
23+ reg:
24+ minItems: 5
25+ maxItems: 6
26+
27+ reg-names:
28+ minItems: 5
29+ items:
30+ - const: parf # Qualcomm specific registers
31+ - const: dbi # DesignWare PCIe registers
32+ - const: elbi # External local bus interface registers
33+ - const: atu # ATU address space
34+ - const: config # PCIe configuration space
35+ - const: mhi # MHI registers
36+
37+ clocks:
38+ minItems: 11
39+ maxItems: 12
40+
41+ clock-names:
42+ minItems: 11
43+ items:
44+ - const: pipe # PIPE clock
45+ - const: pipe_mux # PIPE MUX
46+ - const: phy_pipe # PIPE output clock
47+ - const: ref # REFERENCE clock
48+ - const: aux # Auxiliary clock
49+ - const: cfg # Configuration clock
50+ - const: bus_master # Master AXI clock
51+ - const: bus_slave # Slave AXI clock
52+ - const: slave_q2a # Slave Q2A clock
53+ - const: ddrss_sf_tbu # PCIe SF TBU clock
54+ - enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock
55+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
56+
57+ interrupts:
58+ minItems: 8
59+ maxItems: 8
60+
61+ interrupt-names:
62+ items:
63+ - const: msi0
64+ - const: msi1
65+ - const: msi2
66+ - const: msi3
67+ - const: msi4
68+ - const: msi5
69+ - const: msi6
70+ - const: msi7
71+
72+ resets:
73+ maxItems: 1
74+
75+ reset-names:
76+ items:
77+ - const: pci
78+
79+allOf:
80+ - $ref: qcom,pcie-common.yaml#
81+
82+unevaluatedProperties: false
83+
84+examples:
85+ - |
86+ #include <dt-bindings/clock/qcom,gcc-sm8450.h>
87+ #include <dt-bindings/clock/qcom,rpmh.h>
88+ #include <dt-bindings/gpio/gpio.h>
89+ #include <dt-bindings/interconnect/qcom,sm8450.h>
90+ #include <dt-bindings/interrupt-controller/arm-gic.h>
91+
92+ soc {
93+ #address-cells = <2>;
94+ #size-cells = <2>;
95+
96+ pcie@1c00000 {
97+ compatible = "qcom,pcie-sm8450-pcie0";
98+ reg = <0 0x01c00000 0 0x3000>,
99+ <0 0x60000000 0 0xf1d>,
100+ <0 0x60000f20 0 0xa8>,
101+ <0 0x60001000 0 0x1000>,
102+ <0 0x60100000 0 0x100000>;
103+ reg-names = "parf", "dbi", "elbi", "atu", "config";
104+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
105+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
106+
107+ bus-range = <0x00 0xff>;
108+ device_type = "pci";
109+ linux,pci-domain = <0>;
110+ max-link-speed = <2>;
111+ num-lanes = <1>;
112+
113+ #address-cells = <3>;
114+ #size-cells = <2>;
115+
116+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
117+ <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
118+ <&pcie0_phy>,
119+ <&rpmhcc RPMH_CXO_CLK>,
120+ <&gcc GCC_PCIE_0_AUX_CLK>,
121+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
122+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
123+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
124+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
125+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
126+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
127+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
128+ clock-names = "pipe",
129+ "pipe_mux",
130+ "phy_pipe",
131+ "ref",
132+ "aux",
133+ "cfg",
134+ "bus_master",
135+ "bus_slave",
136+ "slave_q2a",
137+ "ddrss_sf_tbu",
138+ "aggre0",
139+ "aggre1";
140+
141+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
142+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
143+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
144+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
145+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
146+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
147+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
148+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
149+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
150+ "msi4", "msi5", "msi6", "msi7";
151+ #interrupt-cells = <1>;
152+ interrupt-map-mask = <0 0 0 0x7>;
153+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
154+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
155+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
156+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
157+ msi-map = <0x0 &gic_its 0x5981 0x1>,
158+ <0x100 &gic_its 0x5980 0x1>;
159+ msi-map-mask = <0xff00>;
160+
161+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
162+ <0x100 &apps_smmu 0x1c01 0x1>;
163+
164+ phys = <&pcie0_phy>;
165+ phy-names = "pciephy";
166+
167+ pinctrl-0 = <&pcie0_default_state>;
168+ pinctrl-names = "default";
169+
170+ power-domains = <&gcc PCIE_0_GDSC>;
171+
172+ resets = <&gcc GCC_PCIE_0_BCR>;
173+ reset-names = "pci";
174+
175+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
176+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
177+ };
178+ };
Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml+171−0
@@ -0,0 +1,171 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm SM8550 PCI Express Root Complex
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+description:
14+ Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
15+ the Synopsys DesignWare PCIe IP.
16+
17+properties:
18+ compatible:
19+ oneOf:
20+ - const: qcom,pcie-sm8550
21+ - items:
22+ - enum:
23+ - qcom,pcie-sm8650
24+ - const: qcom,pcie-sm8550
25+
26+ reg:
27+ minItems: 5
28+ maxItems: 6
29+
30+ reg-names:
31+ minItems: 5
32+ items:
33+ - const: parf # Qualcomm specific registers
34+ - const: dbi # DesignWare PCIe registers
35+ - const: elbi # External local bus interface registers
36+ - const: atu # ATU address space
37+ - const: config # PCIe configuration space
38+ - const: mhi # MHI registers
39+
40+ clocks:
41+ minItems: 7
42+ maxItems: 8
43+
44+ clock-names:
45+ minItems: 7
46+ items:
47+ - const: aux # Auxiliary clock
48+ - const: cfg # Configuration clock
49+ - const: bus_master # Master AXI clock
50+ - const: bus_slave # Slave AXI clock
51+ - const: slave_q2a # Slave Q2A clock
52+ - const: ddrss_sf_tbu # PCIe SF TBU clock
53+ - const: noc_aggr # Aggre NoC PCIe AXI clock
54+ - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
55+
56+ interrupts:
57+ minItems: 8
58+ maxItems: 8
59+
60+ interrupt-names:
61+ items:
62+ - const: msi0
63+ - const: msi1
64+ - const: msi2
65+ - const: msi3
66+ - const: msi4
67+ - const: msi5
68+ - const: msi6
69+ - const: msi7
70+
71+ resets:
72+ minItems: 1
73+ maxItems: 2
74+
75+ reset-names:
76+ minItems: 1
77+ items:
78+ - const: pci # PCIe core reset
79+ - const: link_down # PCIe link down reset
80+
81+allOf:
82+ - $ref: qcom,pcie-common.yaml#
83+
84+unevaluatedProperties: false
85+
86+examples:
87+ - |
88+ #include <dt-bindings/clock/qcom,sm8550-gcc.h>
89+ #include <dt-bindings/gpio/gpio.h>
90+ #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
91+ #include <dt-bindings/interrupt-controller/arm-gic.h>
92+
93+ soc {
94+ #address-cells = <2>;
95+ #size-cells = <2>;
96+
97+ pcie@1c00000 {
98+ compatible = "qcom,pcie-sm8550";
99+ reg = <0 0x01c00000 0 0x3000>,
100+ <0 0x60000000 0 0xf1d>,
101+ <0 0x60000f20 0 0xa8>,
102+ <0 0x60001000 0 0x1000>,
103+ <0 0x60100000 0 0x100000>;
104+ reg-names = "parf", "dbi", "elbi", "atu", "config";
105+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
106+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
107+
108+ bus-range = <0x00 0xff>;
109+ device_type = "pci";
110+ linux,pci-domain = <0>;
111+ num-lanes = <2>;
112+
113+ #address-cells = <3>;
114+ #size-cells = <2>;
115+
116+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
117+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
118+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
119+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
120+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
121+ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
122+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
123+ clock-names = "aux",
124+ "cfg",
125+ "bus_master",
126+ "bus_slave",
127+ "slave_q2a",
128+ "ddrss_sf_tbu",
129+ "noc_aggr";
130+
131+ dma-coherent;
132+
133+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
134+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
135+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
136+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
137+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
138+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
139+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
140+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
141+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
142+ "msi4", "msi5", "msi6", "msi7";
143+ #interrupt-cells = <1>;
144+ interrupt-map-mask = <0 0 0 0x7>;
145+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
146+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
147+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
148+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
149+
150+ interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
151+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
152+ interconnect-names = "pcie-mem", "cpu-pcie";
153+
154+ iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
155+ <0x100 &apps_smmu 0x1401 0x1>;
156+
157+ phys = <&pcie0_phy>;
158+ phy-names = "pciephy";
159+
160+ pinctrl-0 = <&pcie0_default_state>;
161+ pinctrl-names = "default";
162+
163+ power-domains = <&gcc PCIE_0_GDSC>;
164+
165+ resets = <&gcc GCC_PCIE_0_BCR>;
166+ reset-names = "pci";
167+
168+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
169+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
170+ };
171+ };
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml+165−0
@@ -0,0 +1,165 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Qualcomm X1E80100 PCI Express Root Complex
8+
9+maintainers:
10+ - Bjorn Andersson <andersson@kernel.org>
11+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+description:
14+ Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
15+ the Synopsys DesignWare PCIe IP.
16+
17+properties:
18+ compatible:
19+ const: qcom,pcie-x1e80100
20+
21+ reg:
22+ minItems: 5
23+ maxItems: 6
24+
25+ reg-names:
26+ minItems: 5
27+ items:
28+ - const: parf # Qualcomm specific registers
29+ - const: dbi # DesignWare PCIe registers
30+ - const: elbi # External local bus interface registers
31+ - const: atu # ATU address space
32+ - const: config # PCIe configuration space
33+ - const: mhi # MHI registers
34+
35+ clocks:
36+ minItems: 7
37+ maxItems: 7
38+
39+ clock-names:
40+ items:
41+ - const: aux # Auxiliary clock
42+ - const: cfg # Configuration clock
43+ - const: bus_master # Master AXI clock
44+ - const: bus_slave # Slave AXI clock
45+ - const: slave_q2a # Slave Q2A clock
46+ - const: noc_aggr # Aggre NoC PCIe AXI clock
47+ - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
48+
49+ interrupts:
50+ minItems: 8
51+ maxItems: 8
52+
53+ interrupt-names:
54+ items:
55+ - const: msi0
56+ - const: msi1
57+ - const: msi2
58+ - const: msi3
59+ - const: msi4
60+ - const: msi5
61+ - const: msi6
62+ - const: msi7
63+
64+ resets:
65+ minItems: 1
66+ maxItems: 2
67+
68+ reset-names:
69+ minItems: 1
70+ items:
71+ - const: pci # PCIe core reset
72+ - const: link_down # PCIe link down reset
73+
74+allOf:
75+ - $ref: qcom,pcie-common.yaml#
76+
77+unevaluatedProperties: false
78+
79+examples:
80+ - |
81+ #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
82+ #include <dt-bindings/gpio/gpio.h>
83+ #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
84+ #include <dt-bindings/interrupt-controller/arm-gic.h>
85+
86+ soc {
87+ #address-cells = <2>;
88+ #size-cells = <2>;
89+
90+ pcie@1c08000 {
91+ compatible = "qcom,pcie-x1e80100";
92+ reg = <0 0x01c08000 0 0x3000>,
93+ <0 0x7c000000 0 0xf1d>,
94+ <0 0x7c000f40 0 0xa8>,
95+ <0 0x7c001000 0 0x1000>,
96+ <0 0x7c100000 0 0x100000>,
97+ <0 0x01c0b000 0 0x1000>;
98+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
99+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
100+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
101+
102+ bus-range = <0x00 0xff>;
103+ device_type = "pci";
104+ linux,pci-domain = <0>;
105+ num-lanes = <2>;
106+
107+ #address-cells = <3>;
108+ #size-cells = <2>;
109+
110+ clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
111+ <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
112+ <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
113+ <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
114+ <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
115+ <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
116+ <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
117+ clock-names = "aux",
118+ "cfg",
119+ "bus_master",
120+ "bus_slave",
121+ "slave_q2a",
122+ "noc_aggr",
123+ "cnoc_sf_axi";
124+
125+ dma-coherent;
126+
127+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
128+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
129+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
130+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
131+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
132+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
133+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
134+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
135+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
136+ "msi4", "msi5", "msi6", "msi7";
137+ #interrupt-cells = <1>;
138+ interrupt-map-mask = <0 0 0 0x7>;
139+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
140+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
141+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
142+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
143+
144+ interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
145+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>;
146+ interconnect-names = "pcie-mem", "cpu-pcie";
147+
148+ iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
149+ <0x100 &apps_smmu 0x1401 0x1>;
150+
151+ phys = <&pcie4_phy>;
152+ phy-names = "pciephy";
153+
154+ pinctrl-0 = <&pcie0_default_state>;
155+ pinctrl-names = "default";
156+
157+ power-domains = <&gcc GCC_PCIE_4_GDSC>;
158+
159+ resets = <&gcc GCC_PCIE_4_BCR>;
160+ reset-names = "pci";
161+
162+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
163+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
164+ };
165+ };
Documentation/devicetree/bindings/pci/qcom,pcie.yaml+3−375
@@ -28,23 +28,8 @@ properties: · 27 unmodified lines
2828 - qcom,pcie-ipq8074-gen3
2929 - qcom,pcie-msm8996
3030 - qcom,pcie-qcs404
31− - qcom,pcie-sa8540p
32− - qcom,pcie-sa8775p
33− - qcom,pcie-sc7280
34− - qcom,pcie-sc8180x
35− - qcom,pcie-sc8280xp
3631 - qcom,pcie-sdm845
3732 - qcom,pcie-sdx55
38− - qcom,pcie-sm8150
39− - qcom,pcie-sm8250
40− - qcom,pcie-sm8350
41− - qcom,pcie-sm8450-pcie0
42− - qcom,pcie-sm8450-pcie1
43− - qcom,pcie-sm8550
44− - items:
45− - enum:
46− - qcom,pcie-sm8650
47− - const: qcom,pcie-sm8550
4833 - items:
4934 - const: qcom,pcie-msm8998
5035 - const: qcom,pcie-msm8996
@@ -106,9 +91,6 @@ properties: · 55 unmodified lines
10691 vdda_refclk-supply:
10792 description: A phandle to the core analog power supply for IC which generates reference clock
10893
109− vddpe-3v3-supply:
110− description: A phandle to the PCIe endpoint power supply
111−
11294 phys:
11395 maxItems: 1
11496
@@ -123,6 +105,9 @@ properties: · 8 unmodified lines
123105 description: GPIO controlled connection to PERST# signal
124106 maxItems: 1
125107
108+ required-opps:
109+ maxItems: 1
110+
126111 wake-gpios:
127112 description: GPIO controlled connection to WAKE# signal
128113 maxItems: 1
@@ -143,7 +128,6 @@ anyOf: · 14 unmodified lines
143128 - "#interrupt-cells"
144129 - required:
145130 - msi-map
146− - msi-map-mask
147131
148132 allOf:
149133 - $ref: /schemas/pci/pci-bus.yaml#
@@ -217,16 +201,7 @@ allOf: · 67 unmodified lines
217201 compatible:
218202 contains:
219203 enum:
220− - qcom,pcie-sa8775p
221− - qcom,pcie-sc7280
222− - qcom,pcie-sc8180x
223− - qcom,pcie-sc8280xp
224204 - qcom,pcie-sdx55
225− - qcom,pcie-sm8250
226− - qcom,pcie-sm8350
227− - qcom,pcie-sm8450-pcie0
228− - qcom,pcie-sm8450-pcie1
229− - qcom,pcie-sm8550
230205 then:
231206 properties:
232207 reg:
@@ -451,65 +426,6 @@ allOf: · 218 unmodified lines
451426 - const: pwr # PWR reset
452427 - const: ahb # AHB reset
453428
454− - if:
455− properties:
456− compatible:
457− contains:
458− enum:
459− - qcom,pcie-sc7280
460− then:
461− properties:
462− clocks:
463− minItems: 13
464− maxItems: 13
465− clock-names:
466− items:
467− - const: pipe # PIPE clock
468− - const: pipe_mux # PIPE MUX
469− - const: phy_pipe # PIPE output clock
470− - const: ref # REFERENCE clock
471− - const: aux # Auxiliary clock
472− - const: cfg # Configuration clock
473− - const: bus_master # Master AXI clock
474− - const: bus_slave # Slave AXI clock
475− - const: slave_q2a # Slave Q2A clock
476− - const: tbu # PCIe TBU clock
477− - const: ddrss_sf_tbu # PCIe SF TBU clock
478− - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
479− - const: aggre1 # Aggre NoC PCIe1 AXI clock
480− resets:
481− maxItems: 1
482− reset-names:
483− items:
484− - const: pci # PCIe core reset
485−
486− - if:
487− properties:
488− compatible:
489− contains:
490− enum:
491− - qcom,pcie-sc8180x
492− then:
493− properties:
494− clocks:
495− minItems: 8
496− maxItems: 8
497− clock-names:
498− items:
499− - const: pipe # PIPE clock
500− - const: aux # Auxiliary clock
501− - const: cfg # Configuration clock
502− - const: bus_master # Master AXI clock
503− - const: bus_slave # Slave AXI clock
504− - const: slave_q2a # Slave Q2A clock
505− - const: ref # REFERENCE clock
506− - const: tbu # PCIe TBU clock
507− resets:
508− maxItems: 1
509− reset-names:
510− items:
511− - const: pci # PCIe core reset
512−
513429 - if:
514430 properties:
515431 compatible:
@@ -553,229 +469,6 @@ allOf: · 37 unmodified lines
553469 items:
554470 - const: pci # PCIe core reset
555471
556− - if:
557− properties:
558− compatible:
559− contains:
560− enum:
561− - qcom,pcie-sm8150
562− then:
563− properties:
564− clocks:
565− minItems: 8
566− maxItems: 8
567− clock-names:
568− items:
569− - const: pipe # PIPE clock
570− - const: aux # Auxiliary clock
571− - const: cfg # Configuration clock
572− - const: bus_master # Master AXI clock
573− - const: bus_slave # Slave AXI clock
574− - const: slave_q2a # Slave Q2A clock
575− - const: tbu # PCIe TBU clock
576− - const: ref # REFERENCE clock
577− resets:
578− maxItems: 1
579− reset-names:
580− items:
581− - const: pci # PCIe core reset
582−
583− - if:
584− properties:
585− compatible:
586− contains:
587− enum:
588− - qcom,pcie-sm8250
589− then:
590− oneOf:
591− # Unfortunately the "optional" ref clock is used in the middle of the list
592− - properties:
593− clocks:
594− minItems: 9
595− maxItems: 9
596− clock-names:
597− items:
598− - const: pipe # PIPE clock
599− - const: aux # Auxiliary clock
600− - const: cfg # Configuration clock
601− - const: bus_master # Master AXI clock
602− - const: bus_slave # Slave AXI clock
603− - const: slave_q2a # Slave Q2A clock
604− - const: ref # REFERENCE clock
605− - const: tbu # PCIe TBU clock
606− - const: ddrss_sf_tbu # PCIe SF TBU clock
607− - properties:
608− clocks:
609− minItems: 8
610− maxItems: 8
611− clock-names:
612− items:
613− - const: pipe # PIPE clock
614− - const: aux # Auxiliary clock
615− - const: cfg # Configuration clock
616− - const: bus_master # Master AXI clock
617− - const: bus_slave # Slave AXI clock
618− - const: slave_q2a # Slave Q2A clock
619− - const: tbu # PCIe TBU clock
620− - const: ddrss_sf_tbu # PCIe SF TBU clock
621− properties:
622− resets:
623− maxItems: 1
624− reset-names:
625− items:
626− - const: pci # PCIe core reset
627−
628− - if:
629− properties:
630− compatible:
631− contains:
632− enum:
633− - qcom,pcie-sm8350
634− then:
635− properties:
636− clocks:
637− minItems: 8
638− maxItems: 9
639− clock-names:
640− minItems: 8
641− items:
642− - const: aux # Auxiliary clock
643− - const: cfg # Configuration clock
644− - const: bus_master # Master AXI clock
645− - const: bus_slave # Slave AXI clock
646− - const: slave_q2a # Slave Q2A clock
647− - const: tbu # PCIe TBU clock
648− - const: ddrss_sf_tbu # PCIe SF TBU clock
649− - const: aggre1 # Aggre NoC PCIe1 AXI clock
650− - const: aggre0 # Aggre NoC PCIe0 AXI clock
651− resets:
652− maxItems: 1
653− reset-names:
654− items:
655− - const: pci # PCIe core reset
656−
657− - if:
658− properties:
659− compatible:
660− contains:
661− enum:
662− - qcom,pcie-sm8450-pcie0
663− then:
664− properties:
665− clocks:
666− minItems: 12
667− maxItems: 12
668− clock-names:
669− items:
670− - const: pipe # PIPE clock
671− - const: pipe_mux # PIPE MUX
672− - const: phy_pipe # PIPE output clock
673− - const: ref # REFERENCE clock
674− - const: aux # Auxiliary clock
675− - const: cfg # Configuration clock
676− - const: bus_master # Master AXI clock
677− - const: bus_slave # Slave AXI clock
678− - const: slave_q2a # Slave Q2A clock
679− - const: ddrss_sf_tbu # PCIe SF TBU clock
680− - const: aggre0 # Aggre NoC PCIe0 AXI clock
681− - const: aggre1 # Aggre NoC PCIe1 AXI clock
682− resets:
683− maxItems: 1
684− reset-names:
685− items:
686− - const: pci # PCIe core reset
687−
688− - if:
689− properties:
690− compatible:
691− contains:
692− enum:
693− - qcom,pcie-sm8450-pcie1
694− then:
695− properties:
696− clocks:
697− minItems: 11
698− maxItems: 11
699− clock-names:
700− items:
701− - const: pipe # PIPE clock
702− - const: pipe_mux # PIPE MUX
703− - const: phy_pipe # PIPE output clock
704− - const: ref # REFERENCE clock
705− - const: aux # Auxiliary clock
706− - const: cfg # Configuration clock
707− - const: bus_master # Master AXI clock
708− - const: bus_slave # Slave AXI clock
709− - const: slave_q2a # Slave Q2A clock
710− - const: ddrss_sf_tbu # PCIe SF TBU clock
711− - const: aggre1 # Aggre NoC PCIe1 AXI clock
712− resets:
713− maxItems: 1
714− reset-names:
715− items:
716− - const: pci # PCIe core reset
717−
718− - if:
719− properties:
720− compatible:
721− contains:
722− enum:
723− - qcom,pcie-sm8550
724− then:
725− properties:
726− clocks:
727− minItems: 7
728− maxItems: 8
729− clock-names:
730− minItems: 7
731− items:
732− - const: aux # Auxiliary clock
733− - const: cfg # Configuration clock
734− - const: bus_master # Master AXI clock
735− - const: bus_slave # Slave AXI clock
736− - const: slave_q2a # Slave Q2A clock
737− - const: ddrss_sf_tbu # PCIe SF TBU clock
738− - const: noc_aggr # Aggre NoC PCIe AXI clock
739− - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
740− resets:
741− minItems: 1
742− maxItems: 2
743− reset-names:
744− minItems: 1
745− items:
746− - const: pci # PCIe core reset
747− - const: link_down # PCIe link down reset
748−
749− - if:
750− properties:
751− compatible:
752− contains:
753− enum:
754− - qcom,pcie-sa8540p
755− - qcom,pcie-sc8280xp
756− then:
757− properties:
758− clocks:
759− minItems: 8
760− maxItems: 9
761− clock-names:
762− minItems: 8
763− items:
764− - const: aux # Auxiliary clock
765− - const: cfg # Configuration clock
766− - const: bus_master # Master AXI clock
767− - const: bus_slave # Slave AXI clock
768− - const: slave_q2a # Slave Q2A clock
769− - const: ddrss_sf_tbu # PCIe SF TBU clock
770− - const: noc_aggr_4 # NoC aggregate 4 clock
771− - const: noc_aggr_south_sf # NoC aggregate South SF clock
772− - const: cnoc_qx # Configuration NoC QX clock
773− resets:
774− maxItems: 1
775− reset-names:
776− items:
777− - const: pci # PCIe core reset
778−
779472 - if:
780473 properties:
781474 compatible:
@@ -802,43 +495,6 @@ allOf: · 20 unmodified lines
802495 items:
803496 - const: pci # PCIe core reset
804497
805− - if:
806− properties:
807− compatible:
808− contains:
809− enum:
810− - qcom,pcie-sa8775p
811− then:
812− properties:
813− clocks:
814− minItems: 5
815− maxItems: 5
816− clock-names:
817− items:
818− - const: aux # Auxiliary clock
819− - const: cfg # Configuration clock
820− - const: bus_master # Master AXI clock
821− - const: bus_slave # Slave AXI clock
822− - const: slave_q2a # Slave Q2A clock
823− resets:
824− maxItems: 1
825− reset-names:
826− items:
827− - const: pci # PCIe core reset
828−
829− - if:
830− properties:
831− compatible:
832− contains:
833− enum:
834− - qcom,pcie-sa8540p
835− - qcom,pcie-sa8775p
836− - qcom,pcie-sc8280xp
837− then:
838− required:
839− - interconnects
840− - interconnect-names
841−
842498 - if:
843499 not:
844500 properties:
@@ -874,16 +530,7 @@ allOf: · 29 unmodified lines
874530 contains:
875531 enum:
876532 - qcom,pcie-msm8996
877− - qcom,pcie-sa8775p
878− - qcom,pcie-sc7280
879− - qcom,pcie-sc8180x
880533 - qcom,pcie-sdm845
881− - qcom,pcie-sm8150
882− - qcom,pcie-sm8250
883− - qcom,pcie-sm8350
884− - qcom,pcie-sm8450-pcie0
885− - qcom,pcie-sm8450-pcie1
886− - qcom,pcie-sm8550
887534 then:
888535 oneOf:
889536 - properties:
@@ -906,24 +553,6 @@ allOf: · 16 unmodified lines
906553 - const: msi6
907554 - const: msi7
908555
909− - if:
910− properties:
911− compatible:
912− contains:
913− enum:
914− - qcom,pcie-sc8280xp
915− then:
916− properties:
917− interrupts:
918− minItems: 4
919− maxItems: 4
920− interrupt-names:
921− items:
922− - const: msi0
923− - const: msi1
924− - const: msi2
925− - const: msi3
926−
927556 - if:
928557 properties:
929558 compatible:
@@ -938,7 +567,6 @@ allOf: · 8 unmodified lines
938567 - qcom,pcie-ipq8074
939568 - qcom,pcie-ipq8074-gen3
940569 - qcom,pcie-qcs404
941− - qcom,pcie-sa8540p
942570 then:
943571 properties:
944572 interrupts:
Documentation/driver-api/device-io.rst+0−3
@@ -517,6 +517,3 @@ Public Functions Provided · 516 unmodified lines
517517
518518 .. kernel-doc:: arch/x86/include/asm/io.h
519519 :internal:
520−
521−.. kernel-doc:: lib/pci_iomap.c
522− :export:
Documentation/driver-api/pci/pci.rst+6−0
@@ -4,6 +4,12 @@ PCI Support Library · 3 unmodified lines
44 .. kernel-doc:: drivers/pci/pci.c
55 :export:
66
7+.. kernel-doc:: drivers/pci/iomap.c
8+ :export:
9+
10+.. kernel-doc:: drivers/pci/devres.c
11+ :export:
12+
713 .. kernel-doc:: drivers/pci/pci-driver.c
814 :export:
915
MAINTAINERS+0−1
@@ -17018,7 +17018,6 @@ F: include/asm-generic/pci* · 17017 unmodified lines
1701817018 F: include/linux/of_pci.h
1701917019 F: include/linux/pci*
1702017020 F: include/uapi/linux/pci*
17021−F: lib/pci*
1702217021
1702317022 PCIE DRIVER FOR AMAZON ANNAPURNA LABS
1702417023 M: Jonathan Chocron <jonnyc@amazon.com>
arch/x86/pci/fixup.c+48−0
@@ -907,6 +907,54 @@ static void chromeos_fixup_apl_pci_l1ss_capability(struct pci_dev *dev) · 906 unmodified lines
907907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability);
908908 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability);
909909
910+/*
911+ * Disable D3cold on Asus B1400 PCI-NVMe bridge
912+ *
913+ * On this platform with VMD off, the NVMe device cannot successfully power
914+ * back on from D3cold. This appears to be an untested transition by the
915+ * vendor: Windows leaves the NVMe and parent bridge in D0 during suspend.
916+ *
917+ * We disable D3cold on the parent bridge for simplicity, and the fact that
918+ * both parent bridge and NVMe device share the same power resource.
919+ *
920+ * This is only needed on BIOS versions before 308; the newer versions flip
921+ * StorageD3Enable from 1 to 0.
922+ */
923+static const struct dmi_system_id asus_nvme_broken_d3cold_table[] = {
924+ {
925+ .matches = {
926+ DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
927+ DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.304"),
928+ },
929+ },
930+ {
931+ .matches = {
932+ DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
933+ DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.305"),
934+ },
935+ },
936+ {
937+ .matches = {
938+ DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
939+ DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.306"),
940+ },
941+ },
942+ {
943+ .matches = {
944+ DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
945+ DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.307"),
946+ },
947+ },
948+ {}
949+};
950+
951+static void asus_disable_nvme_d3cold(struct pci_dev *pdev)
952+{
953+ if (dmi_check_system(asus_nvme_broken_d3cold_table) > 0)
954+ pci_d3cold_disable(pdev);
955+}
956+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x9a09, asus_disable_nvme_d3cold);
957+
910958 #ifdef CONFIG_SUSPEND
911959 /*
912960 * Root Ports on some AMD SoCs advertise PME_Support for D3hot and D3cold, but
drivers/acpi/sleep.c+0−12
@@ -385,18 +385,6 @@ static const struct dmi_system_id acpisleep_dmi_table[] __initconst = { · 384 unmodified lines
385385 DMI_MATCH(DMI_PRODUCT_NAME, "20GGA00L00"),
386386 },
387387 },
388− /*
389− * ASUS B1400CEAE hangs on resume from suspend (see
390− * https://bugzilla.kernel.org/show_bug.cgi?id=215742).
391− */
392− {
393− .callback = init_default_s3,
394− .ident = "ASUS B1400CEAE",
395− .matches = {
396− DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
397− DMI_MATCH(DMI_PRODUCT_NAME, "ASUS EXPERTBOOK B1400CEAE"),
398− },
399− },
400388 {},
401389 };
402390
drivers/firmware/efi/cper.c+2−2
@@ -445,8 +445,8 @@ static void cper_print_pcie(const char *pfx, const struct cper_sec_pcie *pcie, · 444 unmodified lines
445445 printk("%saer_uncor_severity: 0x%08x\n",
446446 pfx, aer->uncor_severity);
447447 printk("%sTLP Header: %08x %08x %08x %08x\n", pfx,
448− aer->header_log.dw0, aer->header_log.dw1,
449− aer->header_log.dw2, aer->header_log.dw3);
448+ aer->header_log.dw[0], aer->header_log.dw[1],
449+ aer->header_log.dw[2], aer->header_log.dw[3]);
450450 }
451451 }
452452
drivers/ntb/core.c+7−1
@@ -100,6 +100,8 @@ EXPORT_SYMBOL(ntb_unregister_client); · 99 unmodified lines
100100
101101 int ntb_register_device(struct ntb_dev *ntb)
102102 {
103+ int ret;
104+
103105 if (!ntb)
104106 return -EINVAL;
105107 if (!ntb->pdev)
@@ -120,7 +122,11 @@ int ntb_register_device(struct ntb_dev *ntb) · 14 unmodified lines
120122 ntb->ctx_ops = NULL;
121123 spin_lock_init(&ntb->ctx_lock);
122124
123− return device_register(&ntb->dev);
125+ ret = device_register(&ntb->dev);
126+ if (ret)
127+ put_device(&ntb->dev);
128+
129+ return ret;
124130 }
125131 EXPORT_SYMBOL(ntb_register_device);
126132
drivers/pci/Kconfig+5−0
@@ -13,6 +13,11 @@ config FORCE_PCI · 12 unmodified lines
1313 select HAVE_PCI
1414 select PCI
1515
16+# select this to provide a generic PCI iomap,
17+# without PCI itself having to be defined
18+config GENERIC_PCI_IOMAP
19+ bool
20+
1621 menuconfig PCI
1722 bool "PCI support"
1823 depends on HAVE_PCI
drivers/pci/Makefile+4−3
@@ -4,16 +4,17 @@ · 3 unmodified lines
44
55 obj-$(CONFIG_PCI) += access.o bus.o probe.o host-bridge.o \
66 remove.o pci.o pci-driver.o search.o \
7− pci-sysfs.o rom.o setup-res.o irq.o vpd.o \
8− setup-bus.o vc.o mmap.o setup-irq.o
7+ rom.o setup-res.o irq.o vpd.o \
8+ setup-bus.o vc.o mmap.o devres.o
99
1010 obj-$(CONFIG_PCI) += msi/
1111 obj-$(CONFIG_PCI) += pcie/
1212
1313 ifdef CONFIG_PCI
1414 obj-$(CONFIG_PROC_FS) += proc.o
15−obj-$(CONFIG_SYSFS) += slot.o
15+obj-$(CONFIG_SYSFS) += pci-sysfs.o slot.o
1616 obj-$(CONFIG_ACPI) += pci-acpi.o
17+obj-$(CONFIG_GENERIC_PCI_IOMAP) += iomap.o
1718 endif
1819
1920 obj-$(CONFIG_OF) += of.o
drivers/pci/controller/cadence/pcie-cadence-ep.c+13−1
@@ -565,7 +565,8 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) · 564 unmodified lines
565565 struct cdns_pcie *pcie = &ep->pcie;
566566 struct device *dev = pcie->dev;
567567 int max_epfs = sizeof(epc->function_num_map) * 8;
568− int ret, value, epf;
568+ int ret, epf, last_fn;
569+ u32 reg, value;
569570
570571 /*
571572 * BIT(0) is hardwired to 1, hence function 0 is always enabled
@@ -573,6 +574,17 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) · 1 unmodified line
573574 */
574575 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map);
575576
577+ /*
578+ * Next function field in ARI_CAP_AND_CTR register for last function
579+ * should be 0.
580+ * Clearing Next Function Number field for the last function used.
581+ */
582+ last_fn = find_last_bit(&epc->function_num_map, BITS_PER_LONG);
583+ reg = CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn);
584+ value = cdns_pcie_readl(pcie, reg);
585+ value &= ~CDNS_PCIE_ARI_CAP_NFN_MASK;
586+ cdns_pcie_writel(pcie, reg, value);
587+
576588 if (ep->quirk_disable_flr) {
577589 for (epf = 0; epf < max_epfs; epf++) {
578590 if (!(epc->function_num_map & BIT(epf)))
drivers/pci/controller/cadence/pcie-cadence.h+6−0
@@ -130,6 +130,12 @@ · 129 unmodified lines
130130 #define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0
131131 #define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200
132132
133+/*
134+ * Endpoint PF Registers
135+ */
136+#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000)
137+#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8)
138+
133139 /*
134140 * Root Port Registers (PCI configuration space for the root port function)
135141 */
drivers/pci/controller/dwc/pci-imx6.c+354−276
@@ -42,6 +42,19 @@ · 41 unmodified lines
4242 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
4343 #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
4444
45+#define IMX95_PCIE_PHY_GEN_CTRL 0x0
46+#define IMX95_PCIE_REF_USE_PAD BIT(17)
47+
48+#define IMX95_PCIE_SS_RW_REG_0 0xf0
49+#define IMX95_PCIE_REF_CLKEN BIT(23)
50+#define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9)
51+
52+#define IMX95_PE0_GEN_CTRL_1 0x1050
53+#define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0)
54+
55+#define IMX95_PE0_GEN_CTRL_3 0x1058
56+#define IMX95_PCIE_LTSSM_EN BIT(0)
57+
4558 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
4659
4760 enum imx6_pcie_variants {
@@ -52,14 +65,29 @@ enum imx6_pcie_variants { · 4 unmodified lines
5265 IMX8MQ,
5366 IMX8MM,
5467 IMX8MP,
68+ IMX95,
5569 IMX8MQ_EP,
5670 IMX8MM_EP,
5771 IMX8MP_EP,
72+ IMX95_EP,
5873 };
5974
6075 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
6176 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
6277 #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
78+#define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3)
79+#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4)
80+#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5)
81+#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6)
82+#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7)
83+
84+#define imx6_check_flag(pci, val) (pci->drvdata->flags & val)
85+
86+#define IMX6_PCIE_MAX_CLKS 6
87+
88+#define IMX6_PCIE_MAX_INSTANCES 2
89+
90+struct imx6_pcie;
6391
6492 struct imx6_pcie_drvdata {
6593 enum imx6_pcie_variants variant;
@@ -67,6 +95,14 @@ struct imx6_pcie_drvdata { · 1 unmodified line
6795 u32 flags;
6896 int dbi_length;
6997 const char *gpr;
98+ const char * const *clk_names;
99+ const u32 clks_cnt;
100+ const u32 ltssm_off;
101+ const u32 ltssm_mask;
102+ const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
103+ const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
104+ const struct pci_epc_features *epc_features;
105+ int (*init_phy)(struct imx6_pcie *pcie);
70106 };
71107
72108 struct imx6_pcie {
@@ -74,11 +110,7 @@ struct imx6_pcie { · 1 unmodified line
74110 int reset_gpio;
75111 bool gpio_active_high;
76112 bool link_is_up;
77− struct clk *pcie_bus;
78− struct clk *pcie_phy;
79− struct clk *pcie_inbound_axi;
80− struct clk *pcie;
81− struct clk *pcie_aux;
113+ struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
82114 struct regmap *iomuxc_gpr;
83115 u16 msi_ctrl;
84116 u32 controller_id;
@@ -165,34 +197,44 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) · 80 unmodified lines
165197 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
166198 }
167199
200+static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
201+{
202+ regmap_update_bits(imx6_pcie->iomuxc_gpr,
203+ IMX95_PCIE_SS_RW_REG_0,
204+ IMX95_PCIE_PHY_CR_PARA_SEL,
205+ IMX95_PCIE_PHY_CR_PARA_SEL);
206+
207+ regmap_update_bits(imx6_pcie->iomuxc_gpr,
208+ IMX95_PCIE_PHY_GEN_CTRL,
209+ IMX95_PCIE_REF_USE_PAD, 0);
210+ regmap_update_bits(imx6_pcie->iomuxc_gpr,
211+ IMX95_PCIE_SS_RW_REG_0,
212+ IMX95_PCIE_REF_CLKEN,
213+ IMX95_PCIE_REF_CLKEN);
214+
215+ return 0;
216+}
217+
168218 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
169219 {
170− unsigned int mask, val, mode;
220+ const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
221+ unsigned int mask, val, mode, id;
171222
172− if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE)
223+ if (drvdata->mode == DW_PCIE_EP_TYPE)
173224 mode = PCI_EXP_TYPE_ENDPOINT;
174225 else
175226 mode = PCI_EXP_TYPE_ROOT_PORT;
176227
177− switch (imx6_pcie->drvdata->variant) {
178− case IMX8MQ:
179− case IMX8MQ_EP:
180− if (imx6_pcie->controller_id == 1) {
181− mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
182− val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
183− mode);
184− } else {
185− mask = IMX6Q_GPR12_DEVICE_TYPE;
186− val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
187− }
188− break;
189− default:
190− mask = IMX6Q_GPR12_DEVICE_TYPE;
191− val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
192− break;
193− }
228+ id = imx6_pcie->controller_id;
229+
230+ /* If mode_mask[id] is zero, means each controller have its individual gpr */
231+ if (!drvdata->mode_mask[id])
232+ id = 0;
233+
234+ mask = drvdata->mode_mask[id];
235+ val = mode << (ffs(mask) - 1);
194236
195− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
237+ regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
196238 }
197239
198240 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
@@ -320,76 +362,66 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) · 121 unmodified lines
320362 return 0;
321363 }
322364
323−static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
365+static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie)
324366 {
325− switch (imx6_pcie->drvdata->variant) {
326− case IMX8MM:
327− case IMX8MM_EP:
328− case IMX8MP:
329− case IMX8MP_EP:
330− /*
331− * The PHY initialization had been done in the PHY
332− * driver, break here directly.
333− */
334− break;
335− case IMX8MQ:
336− case IMX8MQ_EP:
337− /*
338− * TODO: Currently this code assumes external
339− * oscillator is being used
340− */
367+ /* TODO: Currently this code assumes external oscillator is being used */
368+ regmap_update_bits(imx6_pcie->iomuxc_gpr,
369+ imx6_pcie_grp_offset(imx6_pcie),
370+ IMX8MQ_GPR_PCIE_REF_USE_PAD,
371+ IMX8MQ_GPR_PCIE_REF_USE_PAD);
372+ /*
373+ * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is
374+ * supplied by 3.3V, the VREG_BYPASS should be cleared to zero.
375+ */
376+ if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000)
341377 regmap_update_bits(imx6_pcie->iomuxc_gpr,
342378 imx6_pcie_grp_offset(imx6_pcie),
343− IMX8MQ_GPR_PCIE_REF_USE_PAD,
344− IMX8MQ_GPR_PCIE_REF_USE_PAD);
345− /*
346− * Regarding the datasheet, the PCIE_VPH is suggested
347− * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
348− * VREG_BYPASS should be cleared to zero.
349− */
350− if (imx6_pcie->vph &&
351− regulator_get_voltage(imx6_pcie->vph) > 3000000)
352− regmap_update_bits(imx6_pcie->iomuxc_gpr,
353− imx6_pcie_grp_offset(imx6_pcie),
354− IMX8MQ_GPR_PCIE_VREG_BYPASS,
355− 0);
356− break;
357− case IMX7D:
358− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
359− IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
360− break;
361− case IMX6SX:
362− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
363− IMX6SX_GPR12_PCIE_RX_EQ_MASK,
364− IMX6SX_GPR12_PCIE_RX_EQ_2);
365− fallthrough;
366− default:
367− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
379+ IMX8MQ_GPR_PCIE_VREG_BYPASS,
380+ 0);
381+
382+ return 0;
383+}
384+
385+static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie)
386+{
387+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
388+
389+ return 0;
390+}
391+
392+static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
393+{
394+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
368395 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
369396
370− /* configure constant input signal to the pcie ctrl and phy */
371− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
372− IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
373−
374− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
375− IMX6Q_GPR8_TX_DEEMPH_GEN1,
376− imx6_pcie->tx_deemph_gen1 << 0);
377− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
378− IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
379− imx6_pcie->tx_deemph_gen2_3p5db << 6);
380− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
381− IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
382− imx6_pcie->tx_deemph_gen2_6db << 12);
383− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
384− IMX6Q_GPR8_TX_SWING_FULL,
385− imx6_pcie->tx_swing_full << 18);
386− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
387− IMX6Q_GPR8_TX_SWING_LOW,
388− imx6_pcie->tx_swing_low << 25);
389− break;
390− }
397+ /* configure constant input signal to the pcie ctrl and phy */
398+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
399+ IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
400+
401+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
402+ IMX6Q_GPR8_TX_DEEMPH_GEN1,
403+ imx6_pcie->tx_deemph_gen1 << 0);
404+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
405+ IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
406+ imx6_pcie->tx_deemph_gen2_3p5db << 6);
407+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
408+ IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
409+ imx6_pcie->tx_deemph_gen2_6db << 12);
410+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
411+ IMX6Q_GPR8_TX_SWING_FULL,
412+ imx6_pcie->tx_swing_full << 18);
413+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
414+ IMX6Q_GPR8_TX_SWING_LOW,
415+ imx6_pcie->tx_swing_low << 25);
416+ return 0;
417+}
391418
392− imx6_pcie_configure_type(imx6_pcie);
419+static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie)
420+{
421+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
422+ IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2);
423+
424+ return imx6_pcie_init_phy(imx6_pcie);
393425 }
394426
395427 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
@@ -407,13 +439,18 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) · 11 unmodified lines
407439
408440 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
409441 {
410− unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
442+ unsigned long phy_rate = 0;
411443 int mult, div;
412444 u16 val;
445+ int i;
413446
414447 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
415448 return 0;
416449
450+ for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++)
451+ if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0)
452+ phy_rate = clk_get_rate(imx6_pcie->clks[i].clk);
453+
417454 switch (phy_rate) {
418455 case 125000000:
419456 /*
@@ -550,19 +587,11 @@ static int imx6_pcie_attach_pd(struct device *dev) · 130 unmodified lines
550587
551588 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
552589 {
553− struct dw_pcie *pci = imx6_pcie->pci;
554− struct device *dev = pci->dev;
555590 unsigned int offset;
556591 int ret = 0;
557592
558593 switch (imx6_pcie->drvdata->variant) {
559594 case IMX6SX:
560− ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
561− if (ret) {
562− dev_err(dev, "unable to enable pcie_axi clock\n");
563− break;
564− }
565−
566595 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
567596 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
568597 break;
@@ -582,6 +611,8 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) · 13 unmodified lines
582611 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
583612 break;
584613 case IMX7D:
614+ case IMX95:
615+ case IMX95_EP:
585616 break;
586617 case IMX8MM:
587618 case IMX8MM_EP:
@@ -589,12 +620,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) · 1 unmodified line
589620 case IMX8MQ_EP:
590621 case IMX8MP:
591622 case IMX8MP_EP:
592− ret = clk_prepare_enable(imx6_pcie->pcie_aux);
593− if (ret) {
594− dev_err(dev, "unable to enable pcie_aux clock\n");
595− break;
596− }
597−
598623 offset = imx6_pcie_grp_offset(imx6_pcie);
599624 /*
600625 * Set the over ride low and enabled
@@ -615,9 +640,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) · 14 unmodified lines
615640 static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
616641 {
617642 switch (imx6_pcie->drvdata->variant) {
618− case IMX6SX:
619− clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
620− break;
621643 case IMX6QP:
622644 case IMX6Q:
623645 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
@@ -631,14 +653,6 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) · 7 unmodified lines
631653 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
632654 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
633655 break;
634− case IMX8MM:
635− case IMX8MM_EP:
636− case IMX8MQ:
637− case IMX8MQ_EP:
638− case IMX8MP:
639− case IMX8MP_EP:
640− clk_disable_unprepare(imx6_pcie->pcie_aux);
641− break;
642656 default:
643657 break;
644658 }
@@ -650,23 +664,9 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) · 5 unmodified lines
650664 struct device *dev = pci->dev;
651665 int ret;
652666
653− ret = clk_prepare_enable(imx6_pcie->pcie_phy);
654− if (ret) {
655− dev_err(dev, "unable to enable pcie_phy clock\n");
667+ ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
668+ if (ret)
656669 return ret;
657− }
658−
659− ret = clk_prepare_enable(imx6_pcie->pcie_bus);
660− if (ret) {
661− dev_err(dev, "unable to enable pcie_bus clock\n");
662− goto err_pcie_bus;
663− }
664−
665− ret = clk_prepare_enable(imx6_pcie->pcie);
666− if (ret) {
667− dev_err(dev, "unable to enable pcie clock\n");
668− goto err_pcie;
669− }
670670
671671 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
672672 if (ret) {
@@ -679,11 +679,7 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) · 6 unmodified lines
679679 return 0;
680680
681681 err_ref_clk:
682− clk_disable_unprepare(imx6_pcie->pcie);
683−err_pcie:
684− clk_disable_unprepare(imx6_pcie->pcie_bus);
685−err_pcie_bus:
686− clk_disable_unprepare(imx6_pcie->pcie_phy);
682+ clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
687683
688684 return ret;
689685 }
@@ -691,25 +687,15 @@ err_pcie_bus: · 1 unmodified line
691687 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
692688 {
693689 imx6_pcie_disable_ref_clk(imx6_pcie);
694− clk_disable_unprepare(imx6_pcie->pcie);
695− clk_disable_unprepare(imx6_pcie->pcie_bus);
696− clk_disable_unprepare(imx6_pcie->pcie_phy);
690+ clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
697691 }
698692
699693 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
700694 {
695+ reset_control_assert(imx6_pcie->pciephy_reset);
696+ reset_control_assert(imx6_pcie->apps_reset);
697+
701698 switch (imx6_pcie->drvdata->variant) {
702− case IMX7D:
703− case IMX8MQ:
704− case IMX8MQ_EP:
705− reset_control_assert(imx6_pcie->pciephy_reset);
706− fallthrough;
707− case IMX8MM:
708− case IMX8MM_EP:
709− case IMX8MP:
710− case IMX8MP_EP:
711− reset_control_assert(imx6_pcie->apps_reset);
712− break;
713699 case IMX6SX:
714700 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
715701 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
@@ -730,6 +716,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) · 14 unmodified lines
730716 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
731717 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
732718 break;
719+ default:
720+ break;
733721 }
734722
735723 /* Some boards don't have PCIe reset GPIO. */
@@ -743,14 +731,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) · 7 unmodified lines
743731 struct dw_pcie *pci = imx6_pcie->pci;
744732 struct device *dev = pci->dev;
745733
734+ reset_control_deassert(imx6_pcie->pciephy_reset);
735+
746736 switch (imx6_pcie->drvdata->variant) {
747− case IMX8MQ:
748− case IMX8MQ_EP:
749− reset_control_deassert(imx6_pcie->pciephy_reset);
750− break;
751737 case IMX7D:
752− reset_control_deassert(imx6_pcie->pciephy_reset);
753−
754738 /* Workaround for ERR010728, failure of PCI-e PLL VCO to
755739 * oscillate, especially when cold. This turns off "Duty-cycle
756740 * Corrector" and other mysterious undocumented things.
@@ -782,11 +766,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) · 25 unmodified lines
782766
783767 usleep_range(200, 500);
784768 break;
785− case IMX6Q: /* Nothing to do */
786− case IMX8MM:
787− case IMX8MM_EP:
788− case IMX8MP:
789− case IMX8MP_EP:
769+ default:
790770 break;
791771 }
792772
@@ -824,48 +804,25 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) · 31 unmodified lines
824804 static void imx6_pcie_ltssm_enable(struct device *dev)
825805 {
826806 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
807+ const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
827808
828− switch (imx6_pcie->drvdata->variant) {
829− case IMX6Q:
830− case IMX6SX:
831− case IMX6QP:
832− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
833− IMX6Q_GPR12_PCIE_CTL_2,
834− IMX6Q_GPR12_PCIE_CTL_2);
835− break;
836− case IMX7D:
837− case IMX8MQ:
838− case IMX8MQ_EP:
839− case IMX8MM:
840− case IMX8MM_EP:
841− case IMX8MP:
842− case IMX8MP_EP:
843− reset_control_deassert(imx6_pcie->apps_reset);
844− break;
845− }
809+ if (drvdata->ltssm_mask)
810+ regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
811+ drvdata->ltssm_mask);
812+
813+ reset_control_deassert(imx6_pcie->apps_reset);
846814 }
847815
848816 static void imx6_pcie_ltssm_disable(struct device *dev)
849817 {
850818 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
819+ const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
851820
852− switch (imx6_pcie->drvdata->variant) {
853− case IMX6Q:
854− case IMX6SX:
855− case IMX6QP:
856− regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
857− IMX6Q_GPR12_PCIE_CTL_2, 0);
858− break;
859− case IMX7D:
860− case IMX8MQ:
861− case IMX8MQ_EP:
862− case IMX8MM:
863− case IMX8MM_EP:
864− case IMX8MP:
865− case IMX8MP_EP:
866− reset_control_assert(imx6_pcie->apps_reset);
867− break;
868− }
821+ if (drvdata->ltssm_mask)
822+ regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off,
823+ drvdata->ltssm_mask, 0);
824+
825+ reset_control_assert(imx6_pcie->apps_reset);
869826 }
870827
871828 static int imx6_pcie_start_link(struct dw_pcie *pci)
@@ -977,7 +934,11 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp) · 105 unmodified lines
977934 }
978935
979936 imx6_pcie_assert_core_reset(imx6_pcie);
980− imx6_pcie_init_phy(imx6_pcie);
937+
938+ if (imx6_pcie->drvdata->init_phy)
939+ imx6_pcie->drvdata->init_phy(imx6_pcie);
940+
941+ imx6_pcie_configure_type(imx6_pcie);
981942
982943 ret = imx6_pcie_clk_enable(imx6_pcie);
983944 if (ret) {
@@ -1081,14 +1042,35 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { · 97 unmodified lines
10811042 .linkup_notifier = false,
10821043 .msi_capable = true,
10831044 .msix_capable = false,
1084− .reserved_bar = 1 << BAR_1 | 1 << BAR_3,
1045+ .bar[BAR_1] = { .type = BAR_RESERVED, },
1046+ .bar[BAR_3] = { .type = BAR_RESERVED, },
10851047 .align = SZ_64K,
10861048 };
10871049
1050+/*
1051+ * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme
1052+ * ================================================================================================
1053+ * BAR0 | Enable | 64-bit | 1 MB | Programmable Size
1054+ * BAR1 | Disable | 32-bit | 64 KB | Fixed Size
1055+ * BAR1 should be disabled if BAR0 is 64bit.
1056+ * BAR2 | Enable | 32-bit | 1 MB | Programmable Size
1057+ * BAR3 | Enable | 32-bit | 64 KB | Programmable Size
1058+ * BAR4 | Enable | 32-bit | 1M | Programmable Size
1059+ * BAR5 | Enable | 32-bit | 64 KB | Programmable Size
1060+ */
1061+static const struct pci_epc_features imx95_pcie_epc_features = {
1062+ .msi_capable = true,
1063+ .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
1064+ .align = SZ_4K,
1065+};
1066+
10881067 static const struct pci_epc_features*
10891068 imx6_pcie_ep_get_features(struct dw_pcie_ep *ep)
10901069 {
1091− return &imx8m_pcie_epc_features;
1070+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1071+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
1072+
1073+ return imx6_pcie->drvdata->epc_features;
10921074 }
10931075
10941076 static const struct dw_pcie_ep_ops pcie_ep_ops = {
@@ -1103,7 +1085,6 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, · 8 unmodified lines
11031085 int ret;
11041086 unsigned int pcie_dbi2_offset;
11051087 struct dw_pcie_ep *ep;
1106− struct resource *res;
11071088 struct dw_pcie *pci = imx6_pcie->pci;
11081089 struct dw_pcie_rp *pp = &pci->pp;
11091090 struct device *dev = pci->dev;
@@ -1122,14 +1103,20 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, · 12 unmodified lines
11221103 pcie_dbi2_offset = SZ_4K;
11231104 break;
11241105 }
1106+
11251107 pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset;
1126− res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
1127− if (!res)
1128− return -EINVAL;
11291108
1130− ep->phys_base = res->start;
1131− ep->addr_size = resource_size(res);
1132− ep->page_size = SZ_64K;
1109+ /*
1110+ * FIXME: Ideally, dbi2 base address should come from DT. But since only IMX95 is defining
1111+ * "dbi2" in DT, "dbi_base2" is set to NULL here for that platform alone so that the DWC
1112+ * core code can fetch that from DT. But once all platform DTs were fixed, this and the
1113+ * above "dbi_base2" setting should be removed.
1114+ */
1115+ if (device_property_match_string(dev, "reg-names", "dbi2") >= 0)
1116+ pci->dbi_base2 = NULL;
1117+
1118+ if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT))
1119+ dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
11331120
11341121 ret = dw_pcie_ep_init(ep);
11351122 if (ret) {
@@ -1251,6 +1238,7 @@ static int imx6_pcie_probe(struct platform_device *pdev) · 115 unmodified lines
12511238 struct device_node *node = dev->of_node;
12521239 int ret;
12531240 u16 val;
1241+ int i;
12541242
12551243 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
12561244 if (!imx6_pcie)
@@ -1304,81 +1292,48 @@ static int imx6_pcie_probe(struct platform_device *pdev) · 47 unmodified lines
13041292 return imx6_pcie->reset_gpio;
13051293 }
13061294
1307− /* Fetch clocks */
1308− imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
1309− if (IS_ERR(imx6_pcie->pcie_bus))
1310− return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
1311− "pcie_bus clock source missing or invalid\n");
1295+ if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
1296+ return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
13121297
1313− imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1314− if (IS_ERR(imx6_pcie->pcie))
1315− return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
1316− "pcie clock source missing or invalid\n");
1298+ for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++)
1299+ imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i];
13171300
1318− switch (imx6_pcie->drvdata->variant) {
1319− case IMX6SX:
1320− imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
1321− "pcie_inbound_axi");
1322− if (IS_ERR(imx6_pcie->pcie_inbound_axi))
1323− return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi),
1324− "pcie_inbound_axi clock missing or invalid\n");
1325− break;
1326− case IMX8MQ:
1327− case IMX8MQ_EP:
1328− imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1329− if (IS_ERR(imx6_pcie->pcie_aux))
1330− return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1331− "pcie_aux clock source missing or invalid\n");
1332− fallthrough;
1333− case IMX7D:
1334− if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1335− imx6_pcie->controller_id = 1;
1301+ /* Fetch clocks */
1302+ ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
1303+ if (ret)
1304+ return ret;
13361305
1337− imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
1338− "pciephy");
1339− if (IS_ERR(imx6_pcie->pciephy_reset)) {
1340− dev_err(dev, "Failed to get PCIEPHY reset control\n");
1341− return PTR_ERR(imx6_pcie->pciephy_reset);
1342− }
1306+ if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) {
1307+ imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
1308+ if (IS_ERR(imx6_pcie->phy))
1309+ return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),
1310+ "failed to get pcie phy\n");
1311+ }
13431312
1344− imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1345− "apps");
1346− if (IS_ERR(imx6_pcie->apps_reset)) {
1347− dev_err(dev, "Failed to get PCIE APPS reset control\n");
1348− return PTR_ERR(imx6_pcie->apps_reset);
1349− }
1350− break;
1351− case IMX8MM:
1352− case IMX8MM_EP:
1353− case IMX8MP:
1354− case IMX8MP_EP:
1355− imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1356− if (IS_ERR(imx6_pcie->pcie_aux))
1357− return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1358− "pcie_aux clock source missing or invalid\n");
1359− imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1360− "apps");
1313+ if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) {
1314+ imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps");
13611315 if (IS_ERR(imx6_pcie->apps_reset))
13621316 return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset),
13631317 "failed to get pcie apps reset control\n");
1318+ }
13641319
1365− imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
1366− if (IS_ERR(imx6_pcie->phy))
1367− return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),
1368− "failed to get pcie phy\n");
1320+ if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) {
1321+ imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy");
1322+ if (IS_ERR(imx6_pcie->pciephy_reset))
1323+ return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset),
1324+ "Failed to get PCIEPHY reset control\n");
1325+ }
13691326
1327+ switch (imx6_pcie->drvdata->variant) {
1328+ case IMX8MQ:
1329+ case IMX8MQ_EP:
1330+ case IMX7D:
1331+ if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1332+ imx6_pcie->controller_id = 1;
13701333 break;
13711334 default:
13721335 break;
13731336 }
1374− /* Don't fetch the pcie_phy clock, if it has abstract PHY driver */
1375− if (imx6_pcie->phy == NULL) {
1376− imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
1377− if (IS_ERR(imx6_pcie->pcie_phy))
1378− return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
1379− "pcie_phy clock source missing or invalid\n");
1380− }
1381−
13821337
13831338 /* Grab turnoff reset */
13841339 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
@@ -1387,12 +1342,32 @@ static int imx6_pcie_probe(struct platform_device *pdev) · 2 unmodified lines
13871342 return PTR_ERR(imx6_pcie->turnoff_reset);
13881343 }
13891344
1345+ if (imx6_pcie->drvdata->gpr) {
13901346 /* Grab GPR config register range */
1391− imx6_pcie->iomuxc_gpr =
1392− syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
1393− if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1394− dev_err(dev, "unable to find iomuxc registers\n");
1395− return PTR_ERR(imx6_pcie->iomuxc_gpr);
1347+ imx6_pcie->iomuxc_gpr =
1348+ syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
1349+ if (IS_ERR(imx6_pcie->iomuxc_gpr))
1350+ return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
1351+ "unable to find iomuxc registers\n");
1352+ }
1353+
1354+ if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) {
1355+ void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app");
1356+
1357+ if (IS_ERR(off))
1358+ return dev_err_probe(dev, PTR_ERR(off),
1359+ "unable to find serdes registers\n");
1360+
1361+ static const struct regmap_config regmap_config = {
1362+ .reg_bits = 32,
1363+ .val_bits = 32,
1364+ .reg_stride = 4,
1365+ };
1366+
1367+ imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, &regmap_config);
1368+ if (IS_ERR(imx6_pcie->iomuxc_gpr))
1369+ return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
1370+ "unable to find iomuxc registers\n");
13961371 }
13971372
13981373 /* Grab PCIe PHY Tx Settings */
@@ -1469,6 +1444,11 @@ static void imx6_pcie_shutdown(struct platform_device *pdev) · 70 unmodified lines
14691444 imx6_pcie_assert_core_reset(imx6_pcie);
14701445 }
14711446
1447+static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"};
1448+static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
1449+static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
1450+static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
1451+
14721452 static const struct imx6_pcie_drvdata drvdata[] = {
14731453 [IMX6Q] = {
14741454 .variant = IMX6Q,
@@ -1476,6 +1456,13 @@ static const struct imx6_pcie_drvdata drvdata[] = { · 1 unmodified line
14761456 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
14771457 .dbi_length = 0x200,
14781458 .gpr = "fsl,imx6q-iomuxc-gpr",
1459+ .clk_names = imx6q_clks,
1460+ .clks_cnt = ARRAY_SIZE(imx6q_clks),
1461+ .ltssm_off = IOMUXC_GPR12,
1462+ .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
1463+ .mode_off[0] = IOMUXC_GPR12,
1464+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1465+ .init_phy = imx6_pcie_init_phy,
14791466 },
14801467 [IMX6SX] = {
14811468 .variant = IMX6SX,
@@ -1483,6 +1470,13 @@ static const struct imx6_pcie_drvdata drvdata[] = { · 1 unmodified line
14831470 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
14841471 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
14851472 .gpr = "fsl,imx6q-iomuxc-gpr",
1473+ .clk_names = imx6sx_clks,
1474+ .clks_cnt = ARRAY_SIZE(imx6sx_clks),
1475+ .ltssm_off = IOMUXC_GPR12,
1476+ .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
1477+ .mode_off[0] = IOMUXC_GPR12,
1478+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1479+ .init_phy = imx6sx_pcie_init_phy,
14861480 },
14871481 [IMX6QP] = {
14881482 .variant = IMX6QP,
@@ -1491,40 +1485,122 @@ static const struct imx6_pcie_drvdata drvdata[] = { · 2 unmodified lines
14911485 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
14921486 .dbi_length = 0x200,
14931487 .gpr = "fsl,imx6q-iomuxc-gpr",
1488+ .clk_names = imx6q_clks,
1489+ .clks_cnt = ARRAY_SIZE(imx6q_clks),
1490+ .ltssm_off = IOMUXC_GPR12,
1491+ .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
1492+ .mode_off[0] = IOMUXC_GPR12,
1493+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1494+ .init_phy = imx6_pcie_init_phy,
14941495 },
14951496 [IMX7D] = {
14961497 .variant = IMX7D,
1497− .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1498+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
1499+ IMX6_PCIE_FLAG_HAS_APP_RESET |
1500+ IMX6_PCIE_FLAG_HAS_PHY_RESET,
14981501 .gpr = "fsl,imx7d-iomuxc-gpr",
1502+ .clk_names = imx6q_clks,
1503+ .clks_cnt = ARRAY_SIZE(imx6q_clks),
1504+ .mode_off[0] = IOMUXC_GPR12,
1505+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1506+ .init_phy = imx7d_pcie_init_phy,
14991507 },
15001508 [IMX8MQ] = {
15011509 .variant = IMX8MQ,
1510+ .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
1511+ IMX6_PCIE_FLAG_HAS_PHY_RESET,
15021512 .gpr = "fsl,imx8mq-iomuxc-gpr",
1513+ .clk_names = imx8mq_clks,
1514+ .clks_cnt = ARRAY_SIZE(imx8mq_clks),
1515+ .mode_off[0] = IOMUXC_GPR12,
1516+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1517+ .mode_off[1] = IOMUXC_GPR12,
1518+ .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
1519+ .init_phy = imx8mq_pcie_init_phy,
15031520 },
15041521 [IMX8MM] = {
15051522 .variant = IMX8MM,
1506− .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1523+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
1524+ IMX6_PCIE_FLAG_HAS_PHYDRV |
1525+ IMX6_PCIE_FLAG_HAS_APP_RESET,
15071526 .gpr = "fsl,imx8mm-iomuxc-gpr",
1527+ .clk_names = imx8mm_clks,
1528+ .clks_cnt = ARRAY_SIZE(imx8mm_clks),
1529+ .mode_off[0] = IOMUXC_GPR12,
1530+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
15081531 },
15091532 [IMX8MP] = {
15101533 .variant = IMX8MP,
1511− .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1534+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
1535+ IMX6_PCIE_FLAG_HAS_PHYDRV |
1536+ IMX6_PCIE_FLAG_HAS_APP_RESET,
15121537 .gpr = "fsl,imx8mp-iomuxc-gpr",
1538+ .clk_names = imx8mm_clks,
1539+ .clks_cnt = ARRAY_SIZE(imx8mm_clks),
1540+ .mode_off[0] = IOMUXC_GPR12,
1541+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1542+ },
1543+ [IMX95] = {
1544+ .variant = IMX95,
1545+ .flags = IMX6_PCIE_FLAG_HAS_SERDES,
1546+ .clk_names = imx8mq_clks,
1547+ .clks_cnt = ARRAY_SIZE(imx8mq_clks),
1548+ .ltssm_off = IMX95_PE0_GEN_CTRL_3,
1549+ .ltssm_mask = IMX95_PCIE_LTSSM_EN,
1550+ .mode_off[0] = IMX95_PE0_GEN_CTRL_1,
1551+ .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
1552+ .init_phy = imx95_pcie_init_phy,
15131553 },
15141554 [IMX8MQ_EP] = {
15151555 .variant = IMX8MQ_EP,
1556+ .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
1557+ IMX6_PCIE_FLAG_HAS_PHY_RESET,
15161558 .mode = DW_PCIE_EP_TYPE,
15171559 .gpr = "fsl,imx8mq-iomuxc-gpr",
1560+ .clk_names = imx8mq_clks,
1561+ .clks_cnt = ARRAY_SIZE(imx8mq_clks),
1562+ .mode_off[0] = IOMUXC_GPR12,
1563+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1564+ .mode_off[1] = IOMUXC_GPR12,
1565+ .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
1566+ .epc_features = &imx8m_pcie_epc_features,
1567+ .init_phy = imx8mq_pcie_init_phy,
15181568 },
15191569 [IMX8MM_EP] = {
15201570 .variant = IMX8MM_EP,
1571+ .flags = IMX6_PCIE_FLAG_HAS_PHYDRV,
15211572 .mode = DW_PCIE_EP_TYPE,
15221573 .gpr = "fsl,imx8mm-iomuxc-gpr",
1574+ .clk_names = imx8mm_clks,
1575+ .clks_cnt = ARRAY_SIZE(imx8mm_clks),
1576+ .mode_off[0] = IOMUXC_GPR12,
1577+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1578+ .epc_features = &imx8m_pcie_epc_features,
15231579 },
15241580 [IMX8MP_EP] = {
15251581 .variant = IMX8MP_EP,
1582+ .flags = IMX6_PCIE_FLAG_HAS_PHYDRV,
15261583 .mode = DW_PCIE_EP_TYPE,
15271584 .gpr = "fsl,imx8mp-iomuxc-gpr",
1585+ .clk_names = imx8mm_clks,
1586+ .clks_cnt = ARRAY_SIZE(imx8mm_clks),
1587+ .mode_off[0] = IOMUXC_GPR12,
1588+ .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1589+ .epc_features = &imx8m_pcie_epc_features,
1590+ },
1591+ [IMX95_EP] = {
1592+ .variant = IMX95_EP,
1593+ .flags = IMX6_PCIE_FLAG_HAS_SERDES |
1594+ IMX6_PCIE_FLAG_SUPPORT_64BIT,
1595+ .clk_names = imx8mq_clks,
1596+ .clks_cnt = ARRAY_SIZE(imx8mq_clks),
1597+ .ltssm_off = IMX95_PE0_GEN_CTRL_3,
1598+ .ltssm_mask = IMX95_PCIE_LTSSM_EN,
1599+ .mode_off[0] = IMX95_PE0_GEN_CTRL_1,
1600+ .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
1601+ .init_phy = imx95_pcie_init_phy,
1602+ .epc_features = &imx95_pcie_epc_features,
1603+ .mode = DW_PCIE_EP_TYPE,
15281604 },
15291605 };
15301606
@@ -1536,9 +1612,11 @@ static const struct of_device_id imx6_pcie_of_match[] = { · 5 unmodified lines
15361612 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
15371613 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
15381614 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
1615+ { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
15391616 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
15401617 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
15411618 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
1619+ { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
15421620 {},
15431621 };
15441622
drivers/pci/controller/dwc/pci-keystone.c+6−6
@@ -924,12 +924,12 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = { · 923 unmodified lines
924924 .linkup_notifier = false,
925925 .msi_capable = true,
926926 .msix_capable = true,
927− .reserved_bar = 1 << BAR_0 | 1 << BAR_1,
928− .bar_fixed_64bit = 1 << BAR_0,
929− .bar_fixed_size[2] = SZ_1M,
930− .bar_fixed_size[3] = SZ_64K,
931− .bar_fixed_size[4] = 256,
932− .bar_fixed_size[5] = SZ_1M,
927+ .bar[BAR_0] = { .type = BAR_RESERVED, },
928+ .bar[BAR_1] = { .type = BAR_RESERVED, },
929+ .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
930+ .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, },
931+ .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, },
932+ .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
933933 .align = SZ_1M,
934934 };
935935
drivers/pci/controller/dwc/pci-layerscape-ep.c+4−1
@@ -250,7 +250,10 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) · 249 unmodified lines
250250 pci->dev = dev;
251251 pci->ops = pcie->drvdata->dw_pcie_ops;
252252
253− ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4);
253+ ls_epc->bar[BAR_2].only_64bit = true;
254+ ls_epc->bar[BAR_3].type = BAR_RESERVED;
255+ ls_epc->bar[BAR_4].only_64bit = true;
256+ ls_epc->bar[BAR_5].type = BAR_RESERVED;
254257 ls_epc->linkup_notifier = true;
255258
256259 pcie->pci = pci;
drivers/pci/controller/dwc/pcie-designware-ep.c+6−1
@@ -629,8 +629,13 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) · 628 unmodified lines
629629 nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
630630 PCI_REBAR_CTRL_NBAR_SHIFT;
631631
632+ /*
633+ * PCIe r6.0, sec 7.8.6.2 require us to support at least one
634+ * size in the range from 1 MB to 512 GB. Advertise support
635+ * for 1 MB BAR size only.
636+ */
632637 for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
633− dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
638+ dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, BIT(4));
634639 }
635640
636641 /*
drivers/pci/controller/dwc/pcie-designware-host.c+13−8
@@ -328,7 +328,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) · 327 unmodified lines
328328 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
329329 struct device *dev = pci->dev;
330330 struct platform_device *pdev = to_platform_device(dev);
331− u64 *msi_vaddr;
331+ u64 *msi_vaddr = NULL;
332332 int ret;
333333 u32 ctrl, num_ctrls;
334334
@@ -379,15 +379,20 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) · 44 unmodified lines
379379 * memory.
380380 */
381381 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
382− if (ret)
383− dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
382+ if (!ret)
383+ msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
384+ GFP_KERNEL);
384385
385− msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
386− GFP_KERNEL);
387386 if (!msi_vaddr) {
388− dev_err(dev, "Failed to alloc and map MSI data\n");
389− dw_pcie_free_msi(pp);
390− return -ENOMEM;
387+ dev_warn(dev, "Failed to allocate 32-bit MSI address\n");
388+ dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
389+ msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
390+ GFP_KERNEL);
391+ if (!msi_vaddr) {
392+ dev_err(dev, "Failed to allocate MSI address\n");
393+ dw_pcie_free_msi(pp);
394+ return -ENOMEM;
395+ }
391396 }
392397
393398 return 0;
drivers/pci/controller/dwc/pcie-keembay.c+6−2
@@ -312,8 +312,12 @@ static const struct pci_epc_features keembay_pcie_epc_features = { · 311 unmodified lines
312312 .linkup_notifier = false,
313313 .msi_capable = true,
314314 .msix_capable = true,
315− .reserved_bar = BIT(BAR_1) | BIT(BAR_3) | BIT(BAR_5),
316− .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
315+ .bar[BAR_0] = { .only_64bit = true, },
316+ .bar[BAR_1] = { .type = BAR_RESERVED, },
317+ .bar[BAR_2] = { .only_64bit = true, },
318+ .bar[BAR_3] = { .type = BAR_RESERVED, },
319+ .bar[BAR_4] = { .only_64bit = true, },
320+ .bar[BAR_5] = { .type = BAR_RESERVED, },
317321 .align = SZ_16K,
318322 };
319323
drivers/pci/controller/dwc/pcie-qcom.c+40−2
@@ -53,6 +53,7 @@ · 52 unmodified lines
5353 #define PARF_SLV_ADDR_SPACE_SIZE 0x358
5454 #define PARF_DEVICE_TYPE 0x1000
5555 #define PARF_BDF_TO_SID_TABLE_N 0x2000
56+#define PARF_BDF_TO_SID_CFG 0x2c00
5657
5758 /* ELBI registers */
5859 #define ELBI_SYS_CTRL 0x04
@@ -120,6 +121,9 @@ · 61 unmodified lines
120121 /* PARF_DEVICE_TYPE register fields */
121122 #define DEVICE_TYPE_RC 0x4
122123
124+/* PARF_BDF_TO_SID_CFG fields */
125+#define BDF_TO_SID_BYPASS BIT(0)
126+
123127 /* ELBI_SYS_CTRL register fields */
124128 #define ELBI_SYS_CTRL_LT_ENABLE BIT(0)
125129
@@ -229,6 +233,7 @@ struct qcom_pcie_ops { · 103 unmodified lines
229233
230234 struct qcom_pcie_cfg {
231235 const struct qcom_pcie_ops *ops;
236+ bool no_l0s;
232237 };
233238
234239 struct qcom_pcie {
@@ -272,6 +277,26 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) · 37 unmodified lines
272277 return 0;
273278 }
274279
280+static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci)
281+{
282+ struct qcom_pcie *pcie = to_qcom_pcie(pci);
283+ u16 offset;
284+ u32 val;
285+
286+ if (!pcie->cfg->no_l0s)
287+ return;
288+
289+ offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
290+
291+ dw_pcie_dbi_ro_wr_en(pci);
292+
293+ val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
294+ val &= ~PCI_EXP_LNKCAP_ASPM_L0S;
295+ writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
296+
297+ dw_pcie_dbi_ro_wr_dis(pci);
298+}
299+
275300 static void qcom_pcie_clear_hpc(struct dw_pcie *pci)
276301 {
277302 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
@@ -961,6 +986,7 @@ err_disable_regulators: · 683 unmodified lines
961986
962987 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
963988 {
989+ qcom_pcie_clear_aspm_l0s(pcie->pci);
964990 qcom_pcie_clear_hpc(pcie->pci);
965991
966992 return 0;
@@ -1008,11 +1034,17 @@ static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) · 41 unmodified lines
10081034 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
10091035 int i, nr_map, size = 0;
10101036 u32 smmu_sid_base;
1037+ u32 val;
10111038
10121039 of_get_property(dev->of_node, "iommu-map", &size);
10131040 if (!size)
10141041 return 0;
10151042
1043+ /* Enable BDF to SID translation by disabling bypass mode (default) */
1044+ val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);
1045+ val &= ~BDF_TO_SID_BYPASS;
1046+ writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);
1047+
10161048 map = kzalloc(size, GFP_KERNEL);
10171049 if (!map)
10181050 return -ENOMEM;
@@ -1358,6 +1390,11 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { · 339 unmodified lines
13581390 .ops = &ops_2_9_0,
13591391 };
13601392
1393+static const struct qcom_pcie_cfg cfg_sc8280xp = {
1394+ .ops = &ops_1_9_0,
1395+ .no_l0s = true,
1396+};
1397+
13611398 static const struct dw_pcie_ops dw_pcie_ops = {
13621399 .link_up = qcom_pcie_link_up,
13631400 .start_link = qcom_pcie_start_link,
@@ -1629,11 +1666,11 @@ static const struct of_device_id qcom_pcie_match[] = { · 265 unmodified lines
16291666 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
16301667 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
16311668 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1632− { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
1669+ { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
16331670 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_9_0},
16341671 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
16351672 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1636− { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
1673+ { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
16371674 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
16381675 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
16391676 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
@@ -1642,6 +1679,7 @@ static const struct of_device_id qcom_pcie_match[] = { · 2 unmodified lines
16421679 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
16431680 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
16441681 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1682+ { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 },
16451683 { }
16461684 };
16471685
drivers/pci/controller/dwc/pcie-rcar-gen4.c+3−1
@@ -383,7 +383,9 @@ static const struct pci_epc_features rcar_gen4_pcie_epc_features = { · 382 unmodified lines
383383 .linkup_notifier = false,
384384 .msi_capable = true,
385385 .msix_capable = false,
386− .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
386+ .bar[BAR_1] = { .type = BAR_RESERVED, },
387+ .bar[BAR_3] = { .type = BAR_RESERVED, },
388+ .bar[BAR_5] = { .type = BAR_RESERVED, },
387389 .align = SZ_1M,
388390 };
389391
drivers/pci/controller/dwc/pcie-tegra194.c+7−3
@@ -2007,9 +2007,13 @@ static const struct pci_epc_features tegra_pcie_epc_features = { · 2006 unmodified lines
20072007 .core_init_notifier = true,
20082008 .msi_capable = false,
20092009 .msix_capable = false,
2010− .reserved_bar = 1 << BAR_2 | 1 << BAR_3 | 1 << BAR_4 | 1 << BAR_5,
2011− .bar_fixed_64bit = 1 << BAR_0,
2012− .bar_fixed_size[0] = SZ_1M,
2010+ .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
2011+ .only_64bit = true, },
2012+ .bar[BAR_1] = { .type = BAR_RESERVED, },
2013+ .bar[BAR_2] = { .type = BAR_RESERVED, },
2014+ .bar[BAR_3] = { .type = BAR_RESERVED, },
2015+ .bar[BAR_4] = { .type = BAR_RESERVED, },
2016+ .bar[BAR_5] = { .type = BAR_RESERVED, },
20132017 };
20142018
20152019 static const struct pci_epc_features*
drivers/pci/controller/dwc/pcie-uniphier-ep.c+12−3
@@ -411,8 +411,12 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = { · 410 unmodified lines
411411 .msi_capable = true,
412412 .msix_capable = false,
413413 .align = 1 << 16,
414− .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
415− .reserved_bar = BIT(BAR_4),
414+ .bar[BAR_0] = { .only_64bit = true, },
415+ .bar[BAR_1] = { .type = BAR_RESERVED, },
416+ .bar[BAR_2] = { .only_64bit = true, },
417+ .bar[BAR_3] = { .type = BAR_RESERVED, },
418+ .bar[BAR_4] = { .type = BAR_RESERVED, },
419+ .bar[BAR_5] = { .type = BAR_RESERVED, },
416420 },
417421 };
418422
@@ -425,7 +429,12 @@ static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = { · 6 unmodified lines
425429 .msi_capable = true,
426430 .msix_capable = false,
427431 .align = 1 << 12,
428− .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
432+ .bar[BAR_0] = { .only_64bit = true, },
433+ .bar[BAR_1] = { .type = BAR_RESERVED, },
434+ .bar[BAR_2] = { .only_64bit = true, },
435+ .bar[BAR_3] = { .type = BAR_RESERVED, },
436+ .bar[BAR_4] = { .only_64bit = true, },
437+ .bar[BAR_5] = { .type = BAR_RESERVED, },
429438 },
430439 };
431440
drivers/pci/controller/pci-hyperv.c+2−1
@@ -49,6 +49,7 @@ · 48 unmodified lines
4949 #include <linux/refcount.h>
5050 #include <linux/irqdomain.h>
5151 #include <linux/acpi.h>
52+#include <linux/sizes.h>
5253 #include <asm/mshyperv.h>
5354
5455 /*
@@ -465,7 +466,7 @@ struct pci_eject_response { · 410 unmodified lines
465466 u32 status;
466467 } __packed;
467468
468−static int pci_ring_size = (4 * PAGE_SIZE);
469+static int pci_ring_size = VMBUS_RING_SIZE(SZ_16K);
469470
470471 /*
471472 * Driver specific state.
drivers/pci/controller/pcie-brcmstb.c+1−1
@@ -336,7 +336,7 @@ static int brcm_pcie_mdio_write(void __iomem *base, u8 port, · 335 unmodified lines
336336 readl(base + PCIE_RC_DL_MDIO_ADDR);
337337 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
338338
339− err = readw_poll_timeout_atomic(base + PCIE_RC_DL_MDIO_WR_DATA, data,
339+ err = readl_poll_timeout_atomic(base + PCIE_RC_DL_MDIO_WR_DATA, data,
340340 MDIO_WT_DONE(data), 10, 100);
341341 return err;
342342 }
drivers/pci/controller/pcie-rcar-ep.c+9−5
@@ -440,11 +440,15 @@ static const struct pci_epc_features rcar_pcie_epc_features = { · 439 unmodified lines
440440 .msi_capable = true,
441441 .msix_capable = false,
442442 /* use 64-bit BARs so mark BAR[1,3,5] as reserved */
443− .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
444− .bar_fixed_64bit = 1 << BAR_0 | 1 << BAR_2 | 1 << BAR_4,
445− .bar_fixed_size[0] = 128,
446− .bar_fixed_size[2] = 256,
447− .bar_fixed_size[4] = 256,
443+ .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = 128,
444+ .only_64bit = true, },
445+ .bar[BAR_1] = { .type = BAR_RESERVED, },
446+ .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = 256,
447+ .only_64bit = true, },
448+ .bar[BAR_3] = { .type = BAR_RESERVED, },
449+ .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256,
450+ .only_64bit = true, },
451+ .bar[BAR_5] = { .type = BAR_RESERVED, },
448452 };
449453
450454 static const struct pci_epc_features*
drivers/pci/devres.c+448−0
@@ -0,0 +1,448 @@
1+// SPDX-License-Identifier: GPL-2.0
2+#include <linux/device.h>
3+#include <linux/pci.h>
4+#include "pci.h"
5+
6+/*
7+ * PCI iomap devres
8+ */
9+#define PCIM_IOMAP_MAX PCI_STD_NUM_BARS
10+
11+struct pcim_iomap_devres {
12+ void __iomem *table[PCIM_IOMAP_MAX];
13+};
14+
15+
16+static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
17+{
18+ struct resource **res = ptr;
19+
20+ pci_unmap_iospace(*res);
21+}
22+
23+/**
24+ * devm_pci_remap_iospace - Managed pci_remap_iospace()
25+ * @dev: Generic device to remap IO address for
26+ * @res: Resource describing the I/O space
27+ * @phys_addr: physical address of range to be mapped
28+ *
29+ * Managed pci_remap_iospace(). Map is automatically unmapped on driver
30+ * detach.
31+ */
32+int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
33+ phys_addr_t phys_addr)
34+{
35+ const struct resource **ptr;
36+ int error;
37+
38+ ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
39+ if (!ptr)
40+ return -ENOMEM;
41+
42+ error = pci_remap_iospace(res, phys_addr);
43+ if (error) {
44+ devres_free(ptr);
45+ } else {
46+ *ptr = res;
47+ devres_add(dev, ptr);
48+ }
49+
50+ return error;
51+}
52+EXPORT_SYMBOL(devm_pci_remap_iospace);
53+
54+/**
55+ * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
56+ * @dev: Generic device to remap IO address for
57+ * @offset: Resource address to map
58+ * @size: Size of map
59+ *
60+ * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
61+ * detach.
62+ */
63+void __iomem *devm_pci_remap_cfgspace(struct device *dev,
64+ resource_size_t offset,
65+ resource_size_t size)
66+{
67+ void __iomem **ptr, *addr;
68+
69+ ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
70+ if (!ptr)
71+ return NULL;
72+
73+ addr = pci_remap_cfgspace(offset, size);
74+ if (addr) {
75+ *ptr = addr;
76+ devres_add(dev, ptr);
77+ } else
78+ devres_free(ptr);
79+
80+ return addr;
81+}
82+EXPORT_SYMBOL(devm_pci_remap_cfgspace);
83+
84+/**
85+ * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
86+ * @dev: generic device to handle the resource for
87+ * @res: configuration space resource to be handled
88+ *
89+ * Checks that a resource is a valid memory region, requests the memory
90+ * region and ioremaps with pci_remap_cfgspace() API that ensures the
91+ * proper PCI configuration space memory attributes are guaranteed.
92+ *
93+ * All operations are managed and will be undone on driver detach.
94+ *
95+ * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
96+ * on failure. Usage example::
97+ *
98+ * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
99+ * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
100+ * if (IS_ERR(base))
101+ * return PTR_ERR(base);
102+ */
103+void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
104+ struct resource *res)
105+{
106+ resource_size_t size;
107+ const char *name;
108+ void __iomem *dest_ptr;
109+
110+ BUG_ON(!dev);
111+
112+ if (!res || resource_type(res) != IORESOURCE_MEM) {
113+ dev_err(dev, "invalid resource\n");
114+ return IOMEM_ERR_PTR(-EINVAL);
115+ }
116+
117+ size = resource_size(res);
118+
119+ if (res->name)
120+ name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
121+ res->name);
122+ else
123+ name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
124+ if (!name)
125+ return IOMEM_ERR_PTR(-ENOMEM);
126+
127+ if (!devm_request_mem_region(dev, res->start, size, name)) {
128+ dev_err(dev, "can't request region for resource %pR\n", res);
129+ return IOMEM_ERR_PTR(-EBUSY);
130+ }
131+
132+ dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
133+ if (!dest_ptr) {
134+ dev_err(dev, "ioremap failed for resource %pR\n", res);
135+ devm_release_mem_region(dev, res->start, size);
136+ dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
137+ }
138+
139+ return dest_ptr;
140+}
141+EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
142+
143+/**
144+ * pcim_set_mwi - a device-managed pci_set_mwi()
145+ * @dev: the PCI device for which MWI is enabled
146+ *
147+ * Managed pci_set_mwi().
148+ *
149+ * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
150+ */
151+int pcim_set_mwi(struct pci_dev *dev)
152+{
153+ struct pci_devres *dr;
154+
155+ dr = find_pci_dr(dev);
156+ if (!dr)
157+ return -ENOMEM;
158+
159+ dr->mwi = 1;
160+ return pci_set_mwi(dev);
161+}
162+EXPORT_SYMBOL(pcim_set_mwi);
163+
164+
165+static void pcim_release(struct device *gendev, void *res)
166+{
167+ struct pci_dev *dev = to_pci_dev(gendev);
168+ struct pci_devres *this = res;
169+ int i;
170+
171+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
172+ if (this->region_mask & (1 << i))
173+ pci_release_region(dev, i);
174+
175+ if (this->mwi)
176+ pci_clear_mwi(dev);
177+
178+ if (this->restore_intx)
179+ pci_intx(dev, this->orig_intx);
180+
181+ if (this->enabled && !this->pinned)
182+ pci_disable_device(dev);
183+}
184+
185+/*
186+ * TODO: After the last four callers in pci.c are ported, find_pci_dr()
187+ * needs to be made static again.
188+ */
189+struct pci_devres *find_pci_dr(struct pci_dev *pdev)
190+{
191+ if (pci_is_managed(pdev))
192+ return devres_find(&pdev->dev, pcim_release, NULL, NULL);
193+ return NULL;
194+}
195+
196+static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
197+{
198+ struct pci_devres *dr, *new_dr;
199+
200+ dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
201+ if (dr)
202+ return dr;
203+
204+ new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
205+ if (!new_dr)
206+ return NULL;
207+ return devres_get(&pdev->dev, new_dr, NULL, NULL);
208+}
209+
210+/**
211+ * pcim_enable_device - Managed pci_enable_device()
212+ * @pdev: PCI device to be initialized
213+ *
214+ * Managed pci_enable_device().
215+ */
216+int pcim_enable_device(struct pci_dev *pdev)
217+{
218+ struct pci_devres *dr;
219+ int rc;
220+
221+ dr = get_pci_dr(pdev);
222+ if (unlikely(!dr))
223+ return -ENOMEM;
224+ if (dr->enabled)
225+ return 0;
226+
227+ rc = pci_enable_device(pdev);
228+ if (!rc) {
229+ pdev->is_managed = 1;
230+ dr->enabled = 1;
231+ }
232+ return rc;
233+}
234+EXPORT_SYMBOL(pcim_enable_device);
235+
236+/**
237+ * pcim_pin_device - Pin managed PCI device
238+ * @pdev: PCI device to pin
239+ *
240+ * Pin managed PCI device @pdev. Pinned device won't be disabled on
241+ * driver detach. @pdev must have been enabled with
242+ * pcim_enable_device().
243+ */
244+void pcim_pin_device(struct pci_dev *pdev)
245+{
246+ struct pci_devres *dr;
247+
248+ dr = find_pci_dr(pdev);
249+ WARN_ON(!dr || !dr->enabled);
250+ if (dr)
251+ dr->pinned = 1;
252+}
253+EXPORT_SYMBOL(pcim_pin_device);
254+
255+static void pcim_iomap_release(struct device *gendev, void *res)
256+{
257+ struct pci_dev *dev = to_pci_dev(gendev);
258+ struct pcim_iomap_devres *this = res;
259+ int i;
260+
261+ for (i = 0; i < PCIM_IOMAP_MAX; i++)
262+ if (this->table[i])
263+ pci_iounmap(dev, this->table[i]);
264+}
265+
266+/**
267+ * pcim_iomap_table - access iomap allocation table
268+ * @pdev: PCI device to access iomap table for
269+ *
270+ * Access iomap allocation table for @dev. If iomap table doesn't
271+ * exist and @pdev is managed, it will be allocated. All iomaps
272+ * recorded in the iomap table are automatically unmapped on driver
273+ * detach.
274+ *
275+ * This function might sleep when the table is first allocated but can
276+ * be safely called without context and guaranteed to succeed once
277+ * allocated.
278+ */
279+void __iomem * const *pcim_iomap_table(struct pci_dev *pdev)
280+{
281+ struct pcim_iomap_devres *dr, *new_dr;
282+
283+ dr = devres_find(&pdev->dev, pcim_iomap_release, NULL, NULL);
284+ if (dr)
285+ return dr->table;
286+
287+ new_dr = devres_alloc_node(pcim_iomap_release, sizeof(*new_dr), GFP_KERNEL,
288+ dev_to_node(&pdev->dev));
289+ if (!new_dr)
290+ return NULL;
291+ dr = devres_get(&pdev->dev, new_dr, NULL, NULL);
292+ return dr->table;
293+}
294+EXPORT_SYMBOL(pcim_iomap_table);
295+
296+/**
297+ * pcim_iomap - Managed pcim_iomap()
298+ * @pdev: PCI device to iomap for
299+ * @bar: BAR to iomap
300+ * @maxlen: Maximum length of iomap
301+ *
302+ * Managed pci_iomap(). Map is automatically unmapped on driver
303+ * detach.
304+ */
305+void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen)
306+{
307+ void __iomem **tbl;
308+
309+ BUG_ON(bar >= PCIM_IOMAP_MAX);
310+
311+ tbl = (void __iomem **)pcim_iomap_table(pdev);
312+ if (!tbl || tbl[bar]) /* duplicate mappings not allowed */
313+ return NULL;
314+
315+ tbl[bar] = pci_iomap(pdev, bar, maxlen);
316+ return tbl[bar];
317+}
318+EXPORT_SYMBOL(pcim_iomap);
319+
320+/**
321+ * pcim_iounmap - Managed pci_iounmap()
322+ * @pdev: PCI device to iounmap for
323+ * @addr: Address to unmap
324+ *
325+ * Managed pci_iounmap(). @addr must have been mapped using pcim_iomap().
326+ */
327+void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr)
328+{
329+ void __iomem **tbl;
330+ int i;
331+
332+ pci_iounmap(pdev, addr);
333+
334+ tbl = (void __iomem **)pcim_iomap_table(pdev);
335+ BUG_ON(!tbl);
336+
337+ for (i = 0; i < PCIM_IOMAP_MAX; i++)
338+ if (tbl[i] == addr) {
339+ tbl[i] = NULL;
340+ return;
341+ }
342+ WARN_ON(1);
343+}
344+EXPORT_SYMBOL(pcim_iounmap);
345+
346+/**
347+ * pcim_iomap_regions - Request and iomap PCI BARs
348+ * @pdev: PCI device to map IO resources for
349+ * @mask: Mask of BARs to request and iomap
350+ * @name: Name used when requesting regions
351+ *
352+ * Request and iomap regions specified by @mask.
353+ */
354+int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name)
355+{
356+ void __iomem * const *iomap;
357+ int i, rc;
358+
359+ iomap = pcim_iomap_table(pdev);
360+ if (!iomap)
361+ return -ENOMEM;
362+
363+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
364+ unsigned long len;
365+
366+ if (!(mask & (1 << i)))
367+ continue;
368+
369+ rc = -EINVAL;
370+ len = pci_resource_len(pdev, i);
371+ if (!len)
372+ goto err_inval;
373+
374+ rc = pci_request_region(pdev, i, name);
375+ if (rc)
376+ goto err_inval;
377+
378+ rc = -ENOMEM;
379+ if (!pcim_iomap(pdev, i, 0))
380+ goto err_region;
381+ }
382+
383+ return 0;
384+
385+ err_region:
386+ pci_release_region(pdev, i);
387+ err_inval:
388+ while (--i >= 0) {
389+ if (!(mask & (1 << i)))
390+ continue;
391+ pcim_iounmap(pdev, iomap[i]);
392+ pci_release_region(pdev, i);
393+ }
394+
395+ return rc;
396+}
397+EXPORT_SYMBOL(pcim_iomap_regions);
398+
399+/**
400+ * pcim_iomap_regions_request_all - Request all BARs and iomap specified ones
401+ * @pdev: PCI device to map IO resources for
402+ * @mask: Mask of BARs to iomap
403+ * @name: Name used when requesting regions
404+ *
405+ * Request all PCI BARs and iomap regions specified by @mask.
406+ */
407+int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
408+ const char *name)
409+{
410+ int request_mask = ((1 << 6) - 1) & ~mask;
411+ int rc;
412+
413+ rc = pci_request_selected_regions(pdev, request_mask, name);
414+ if (rc)
415+ return rc;
416+
417+ rc = pcim_iomap_regions(pdev, mask, name);
418+ if (rc)
419+ pci_release_selected_regions(pdev, request_mask);
420+ return rc;
421+}
422+EXPORT_SYMBOL(pcim_iomap_regions_request_all);
423+
424+/**
425+ * pcim_iounmap_regions - Unmap and release PCI BARs
426+ * @pdev: PCI device to map IO resources for
427+ * @mask: Mask of BARs to unmap and release
428+ *
429+ * Unmap and release regions specified by @mask.
430+ */
431+void pcim_iounmap_regions(struct pci_dev *pdev, int mask)
432+{
433+ void __iomem * const *iomap;
434+ int i;
435+
436+ iomap = pcim_iomap_table(pdev);
437+ if (!iomap)
438+ return;
439+
440+ for (i = 0; i < PCIM_IOMAP_MAX; i++) {
441+ if (!(mask & (1 << i)))
442+ continue;
443+
444+ pcim_iounmap(pdev, iomap[i]);
445+ pci_release_region(pdev, i);
446+ }
447+}
448+EXPORT_SYMBOL(pcim_iounmap_regions);
drivers/pci/endpoint/functions/pci-epf-mhi.c+19−2
@@ -123,6 +123,22 @@ static const struct pci_epf_mhi_ep_info sm8450_info = { · 122 unmodified lines
123123 .flags = MHI_EPF_USE_DMA,
124124 };
125125
126+static struct pci_epf_header sa8775p_header = {
127+ .vendorid = PCI_VENDOR_ID_QCOM,
128+ .deviceid = 0x0306, /* FIXME: Update deviceid for sa8775p EP */
129+ .baseclass_code = PCI_CLASS_OTHERS,
130+ .interrupt_pin = PCI_INTERRUPT_INTA,
131+};
132+
133+static const struct pci_epf_mhi_ep_info sa8775p_info = {
134+ .config = &mhi_v1_config,
135+ .epf_header = &sa8775p_header,
136+ .bar_num = BAR_0,
137+ .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32,
138+ .msi_count = 32,
139+ .mru = 0x8000,
140+};
141+
126142 struct pci_epf_mhi {
127143 const struct pci_epc_features *epc_features;
128144 const struct pci_epf_mhi_ep_info *info;
@@ -913,8 +929,9 @@ static int pci_epf_mhi_probe(struct pci_epf *epf, · 784 unmodified lines
913929 }
914930
915931 static const struct pci_epf_device_id pci_epf_mhi_ids[] = {
916− { .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info },
917− { .name = "sm8450", .driver_data = (kernel_ulong_t)&sm8450_info },
932+ { .name = "pci_epf_mhi_sa8775p", .driver_data = (kernel_ulong_t)&sa8775p_info },
933+ { .name = "pci_epf_mhi_sdx55", .driver_data = (kernel_ulong_t)&sdx55_info },
934+ { .name = "pci_epf_mhi_sm8450", .driver_data = (kernel_ulong_t)&sm8450_info },
918935 {},
919936 };
920937
drivers/pci/endpoint/functions/pci-epf-ntb.c+3−3
@@ -1012,13 +1012,13 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb, · 1011 unmodified lines
10121012
10131013 epc_features = ntb_epc->epc_features;
10141014 barno = ntb_epc->epf_ntb_bar[BAR_CONFIG];
1015− size = epc_features->bar_fixed_size[barno];
1015+ size = epc_features->bar[barno].fixed_size;
10161016 align = epc_features->align;
10171017
10181018 peer_ntb_epc = ntb->epc[!type];
10191019 peer_epc_features = peer_ntb_epc->epc_features;
10201020 peer_barno = ntb_epc->epf_ntb_bar[BAR_PEER_SPAD];
1021− peer_size = peer_epc_features->bar_fixed_size[peer_barno];
1021+ peer_size = peer_epc_features->bar[peer_barno].fixed_size;
10221022
10231023 /* Check if epc_features is populated incorrectly */
10241024 if ((!IS_ALIGNED(size, align)))
@@ -1067,7 +1067,7 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb, · 42 unmodified lines
10671067 else if (size < ctrl_size + spad_size)
10681068 return -EINVAL;
10691069
1070− base = pci_epf_alloc_space(epf, size, barno, align, type);
1070+ base = pci_epf_alloc_space(epf, size, barno, epc_features, type);
10711071 if (!base) {
10721072 dev_err(dev, "%s intf: Config/Status/SPAD alloc region fail\n",
10731073 pci_epc_interface_string(type));
drivers/pci/endpoint/functions/pci-epf-test.c+5−16
@@ -729,7 +729,7 @@ static int pci_epf_test_set_bar(struct pci_epf *epf) · 728 unmodified lines
729729 */
730730 add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
731731
732− if (!!(epc_features->reserved_bar & (1 << bar)))
732+ if (epc_features->bar[bar].type == BAR_RESERVED)
733733 continue;
734734
735735 ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no,
@@ -841,14 +841,8 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) · 105 unmodified lines
841841 }
842842 test_reg_size = test_reg_bar_size + msix_table_size + pba_size;
843843
844− if (epc_features->bar_fixed_size[test_reg_bar]) {
845− if (test_reg_size > bar_size[test_reg_bar])
846− return -ENOMEM;
847− test_reg_size = bar_size[test_reg_bar];
848− }
849−
850844 base = pci_epf_alloc_space(epf, test_reg_size, test_reg_bar,
851− epc_features->align, PRIMARY_INTERFACE);
845+ epc_features, PRIMARY_INTERFACE);
852846 if (!base) {
853847 dev_err(dev, "Failed to allocated register space\n");
854848 return -ENOMEM;
@@ -862,12 +856,11 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) · 7 unmodified lines
862856 if (bar == test_reg_bar)
863857 continue;
864858
865− if (!!(epc_features->reserved_bar & (1 << bar)))
859+ if (epc_features->bar[bar].type == BAR_RESERVED)
866860 continue;
867861
868862 base = pci_epf_alloc_space(epf, bar_size[bar], bar,
869− epc_features->align,
870− PRIMARY_INTERFACE);
863+ epc_features, PRIMARY_INTERFACE);
871864 if (!base)
872865 dev_err(dev, "Failed to allocate space for BAR%d\n",
873866 bar);
@@ -881,16 +874,12 @@ static void pci_epf_configure_bar(struct pci_epf *epf, · 7 unmodified lines
881874 const struct pci_epc_features *epc_features)
882875 {
883876 struct pci_epf_bar *epf_bar;
884− bool bar_fixed_64bit;
885877 int i;
886878
887879 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
888880 epf_bar = &epf->bar[i];
889− bar_fixed_64bit = !!(epc_features->bar_fixed_64bit & (1 << i));
890− if (bar_fixed_64bit)
881+ if (epc_features->bar[i].only_64bit)
891882 epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
892− if (epc_features->bar_fixed_size[i])
893− bar_size[i] = epc_features->bar_fixed_size[i];
894883 }
895884 }
896885
drivers/pci/endpoint/functions/pci-epf-vntb.c+5−20
@@ -422,7 +422,7 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb) · 421 unmodified lines
422422 epf->func_no,
423423 epf->vfunc_no);
424424 barno = ntb->epf_ntb_bar[BAR_CONFIG];
425− size = epc_features->bar_fixed_size[barno];
425+ size = epc_features->bar[barno].fixed_size;
426426 align = epc_features->align;
427427
428428 if ((!IS_ALIGNED(size, align)))
@@ -446,7 +446,7 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb) · 17 unmodified lines
446446 else if (size < ctrl_size + spad_size)
447447 return -EINVAL;
448448
449− base = pci_epf_alloc_space(epf, size, barno, align, 0);
449+ base = pci_epf_alloc_space(epf, size, barno, epc_features, 0);
450450 if (!base) {
451451 dev_err(dev, "Config/Status/SPAD alloc region fail\n");
452452 return -ENOMEM;
@@ -527,7 +527,6 @@ static int epf_ntb_configure_interrupt(struct epf_ntb *ntb) · 74 unmodified lines
527527 static int epf_ntb_db_bar_init(struct epf_ntb *ntb)
528528 {
529529 const struct pci_epc_features *epc_features;
530− u32 align;
531530 struct device *dev = &ntb->epf->dev;
532531 int ret;
533532 struct pci_epf_bar *epf_bar;
@@ -538,19 +537,9 @@ static int epf_ntb_db_bar_init(struct epf_ntb *ntb) · 4 unmodified lines
538537 epc_features = pci_epc_get_features(ntb->epf->epc,
539538 ntb->epf->func_no,
540539 ntb->epf->vfunc_no);
541− align = epc_features->align;
542−
543− if (size < 128)
544− size = 128;
545−
546− if (align)
547− size = ALIGN(size, align);
548− else
549− size = roundup_pow_of_two(size);
550−
551540 barno = ntb->epf_ntb_bar[BAR_DB];
552541
553− mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0);
542+ mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, epc_features, 0);
554543 if (!mw_addr) {
555544 dev_err(dev, "Failed to allocate OB address\n");
556545 return -ENOMEM;
@@ -1269,21 +1258,17 @@ static int pci_vntb_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 712 unmodified lines
12691258 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
12701259 if (ret) {
12711260 dev_err(dev, "Cannot set DMA mask\n");
1272− return -EINVAL;
1261+ return ret;
12731262 }
12741263
12751264 ret = ntb_register_device(&ndev->ntb);
12761265 if (ret) {
12771266 dev_err(dev, "Failed to register NTB device\n");
1278− goto err_register_dev;
1267+ return ret;
12791268 }
12801269
12811270 dev_dbg(dev, "PCI Virtual NTB driver loaded\n");
12821271 return 0;
1283−
1284−err_register_dev:
1285− put_device(&ndev->ntb.dev);
1286− return -EINVAL;
12871272 }
12881273
12891274 static struct pci_device_id pci_vntb_table[] = {
drivers/pci/endpoint/pci-epc-core.c+10−15
@@ -87,7 +87,7 @@ EXPORT_SYMBOL_GPL(pci_epc_get); · 86 unmodified lines
8787 * @epc_features: pci_epc_features structure that holds the reserved bar bitmap
8888 *
8989 * Invoke to get the first unreserved BAR that can be used by the endpoint
90− * function. For any incorrect value in reserved_bar return '0'.
90+ * function.
9191 */
9292 enum pci_barno
9393 pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features)
@@ -102,32 +102,27 @@ EXPORT_SYMBOL_GPL(pci_epc_get_first_free_bar); · 8 unmodified lines
102102 * @bar: the starting BAR number from where unreserved BAR should be searched
103103 *
104104 * Invoke to get the next unreserved BAR starting from @bar that can be used
105− * for endpoint function. For any incorrect value in reserved_bar return '0'.
105+ * for endpoint function.
106106 */
107107 enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
108108 *epc_features, enum pci_barno bar)
109109 {
110− unsigned long free_bar;
110+ int i;
111111
112112 if (!epc_features)
113113 return BAR_0;
114114
115115 /* If 'bar - 1' is a 64-bit BAR, move to the next BAR */
116− if ((epc_features->bar_fixed_64bit << 1) & 1 << bar)
116+ if (bar > 0 && epc_features->bar[bar - 1].only_64bit)
117117 bar++;
118118
119− /* Find if the reserved BAR is also a 64-bit BAR */
120− free_bar = epc_features->reserved_bar & epc_features->bar_fixed_64bit;
121−
122− /* Set the adjacent bit if the reserved BAR is also a 64-bit BAR */
123− free_bar <<= 1;
124− free_bar |= epc_features->reserved_bar;
125−
126− free_bar = find_next_zero_bit(&free_bar, 6, bar);
127− if (free_bar > 5)
128− return NO_BAR;
119+ for (i = bar; i < PCI_STD_NUM_BARS; i++) {
120+ /* If the BAR is not reserved, return it. */
121+ if (epc_features->bar[i].type != BAR_RESERVED)
122+ return i;
123+ }
129124
130− return free_bar;
125+ return NO_BAR;
131126 }
132127 EXPORT_SYMBOL_GPL(pci_epc_get_next_free_bar);
133128
drivers/pci/endpoint/pci-epf-core.c+16−4
@@ -17,7 +17,7 @@ · 16 unmodified lines
1717
1818 static DEFINE_MUTEX(pci_epf_mutex);
1919
20−static struct bus_type pci_epf_bus_type;
20+static const struct bus_type pci_epf_bus_type;
2121 static const struct device_type pci_epf_type;
2222
2323 /**
@@ -251,14 +251,17 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space); · 227 unmodified lines
251251 * @epf: the EPF device to whom allocate the memory
252252 * @size: the size of the memory that has to be allocated
253253 * @bar: the BAR number corresponding to the allocated register space
254− * @align: alignment size for the allocation region
254+ * @epc_features: the features provided by the EPC specific to this EPF
255255 * @type: Identifies if the allocation is for primary EPC or secondary EPC
256256 *
257257 * Invoke to allocate memory for the PCI EPF register space.
258258 */
259259 void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar,
260− size_t align, enum pci_epc_interface_type type)
260+ const struct pci_epc_features *epc_features,
261+ enum pci_epc_interface_type type)
261262 {
263+ u64 bar_fixed_size = epc_features->bar[bar].fixed_size;
264+ size_t align = epc_features->align;
262265 struct pci_epf_bar *epf_bar;
263266 dma_addr_t phys_addr;
264267 struct pci_epc *epc;
@@ -268,6 +271,15 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, · 3 unmodified lines
268271 if (size < 128)
269272 size = 128;
270273
274+ if (epc_features->bar[bar].type == BAR_FIXED && bar_fixed_size) {
275+ if (size > bar_fixed_size) {
276+ dev_err(&epf->dev,
277+ "requested BAR size is larger than fixed size\n");
278+ return NULL;
279+ }
280+ size = bar_fixed_size;
281+ }
282+
271283 if (align)
272284 size = ALIGN(size, align);
273285 else
@@ -507,7 +519,7 @@ static void pci_epf_device_remove(struct device *dev) · 233 unmodified lines
507519 epf->driver = NULL;
508520 }
509521
510−static struct bus_type pci_epf_bus_type = {
522+static const struct bus_type pci_epf_bus_type = {
511523 .name = "pci-epf",
512524 .match = pci_epf_device_match,
513525 .probe = pci_epf_device_probe,
drivers/pci/iomap.crenamed from lib/pci_iomap.c+1−4
@@ -9,7 +9,6 @@ · 8 unmodified lines
99
1010 #include <linux/export.h>
1111
12−#ifdef CONFIG_PCI
1312 /**
1413 * pci_iomap_range - create a virtual mapping cookie for a PCI BAR
1514 * @dev: PCI device that owns the BAR
@@ -170,11 +169,9 @@ void pci_iounmap(struct pci_dev *dev, void __iomem *p) · 154 unmodified lines
170169
171170 if (addr >= start && addr < start + IO_SPACE_LIMIT)
172171 return;
173− iounmap(p);
174172 #endif
173+ iounmap(p);
175174 }
176175 EXPORT_SYMBOL(pci_iounmap);
177176
178177 #endif /* ARCH_WANTS_GENERIC_PCI_IOUNMAP */
179−
180−#endif /* CONFIG_PCI */
drivers/pci/irq.c+204−0
@@ -8,9 +8,13 @@ · 7 unmodified lines
88
99 #include <linux/device.h>
1010 #include <linux/kernel.h>
11+#include <linux/errno.h>
1112 #include <linux/export.h>
13+#include <linux/interrupt.h>
1214 #include <linux/pci.h>
1315
16+#include "pci.h"
17+
1418 /**
1519 * pci_request_irq - allocate an interrupt line for a PCI device
1620 * @dev: PCI device to operate on
@@ -74,3 +78,203 @@ void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id) · 57 unmodified lines
7478 kfree(free_irq(pci_irq_vector(dev, nr), dev_id));
7579 }
7680 EXPORT_SYMBOL(pci_free_irq);
81+
82+/**
83+ * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
84+ * @dev: the PCI device
85+ * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
86+ *
87+ * Perform INTx swizzling for a device behind one level of bridge. This is
88+ * required by section 9.1 of the PCI-to-PCI bridge specification for devices
89+ * behind bridges on add-in cards. For devices with ARI enabled, the slot
90+ * number is always 0 (see the Implementation Note in section 2.2.8.1 of
91+ * the PCI Express Base Specification, Revision 2.1)
92+ */
93+u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
94+{
95+ int slot;
96+
97+ if (pci_ari_enabled(dev->bus))
98+ slot = 0;
99+ else
100+ slot = PCI_SLOT(dev->devfn);
101+
102+ return (((pin - 1) + slot) % 4) + 1;
103+}
104+
105+int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
106+{
107+ u8 pin;
108+
109+ pin = dev->pin;
110+ if (!pin)
111+ return -1;
112+
113+ while (!pci_is_root_bus(dev->bus)) {
114+ pin = pci_swizzle_interrupt_pin(dev, pin);
115+ dev = dev->bus->self;
116+ }
117+ *bridge = dev;
118+ return pin;
119+}
120+
121+/**
122+ * pci_common_swizzle - swizzle INTx all the way to root bridge
123+ * @dev: the PCI device
124+ * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
125+ *
126+ * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
127+ * bridges all the way up to a PCI root bus.
128+ */
129+u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
130+{
131+ u8 pin = *pinp;
132+
133+ while (!pci_is_root_bus(dev->bus)) {
134+ pin = pci_swizzle_interrupt_pin(dev, pin);
135+ dev = dev->bus->self;
136+ }
137+ *pinp = pin;
138+ return PCI_SLOT(dev->devfn);
139+}
140+EXPORT_SYMBOL_GPL(pci_common_swizzle);
141+
142+void pci_assign_irq(struct pci_dev *dev)
143+{
144+ u8 pin;
145+ u8 slot = -1;
146+ int irq = 0;
147+ struct pci_host_bridge *hbrg = pci_find_host_bridge(dev->bus);
148+
149+ if (!(hbrg->map_irq)) {
150+ pci_dbg(dev, "runtime IRQ mapping not provided by arch\n");
151+ return;
152+ }
153+
154+ /*
155+ * If this device is not on the primary bus, we need to figure out
156+ * which interrupt pin it will come in on. We know which slot it
157+ * will come in on because that slot is where the bridge is. Each
158+ * time the interrupt line passes through a PCI-PCI bridge we must
159+ * apply the swizzle function.
160+ */
161+ pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
162+ /* Cope with illegal. */
163+ if (pin > 4)
164+ pin = 1;
165+
166+ if (pin) {
167+ /* Follow the chain of bridges, swizzling as we go. */
168+ if (hbrg->swizzle_irq)
169+ slot = (*(hbrg->swizzle_irq))(dev, &pin);
170+
171+ /*
172+ * If a swizzling function is not used, map_irq() must
173+ * ignore slot.
174+ */
175+ irq = (*(hbrg->map_irq))(dev, slot, pin);
176+ if (irq == -1)
177+ irq = 0;
178+ }
179+ dev->irq = irq;
180+
181+ pci_dbg(dev, "assign IRQ: got %d\n", dev->irq);
182+
183+ /*
184+ * Always tell the device, so the driver knows what is the real IRQ
185+ * to use; the device does not use it.
186+ */
187+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
188+}
189+
190+static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
191+{
192+ struct pci_bus *bus = dev->bus;
193+ bool mask_updated = true;
194+ u32 cmd_status_dword;
195+ u16 origcmd, newcmd;
196+ unsigned long flags;
197+ bool irq_pending;
198+
199+ /*
200+ * We do a single dword read to retrieve both command and status.
201+ * Document assumptions that make this possible.
202+ */
203+ BUILD_BUG_ON(PCI_COMMAND % 4);
204+ BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
205+
206+ raw_spin_lock_irqsave(&pci_lock, flags);
207+
208+ bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
209+
210+ irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
211+
212+ /*
213+ * Check interrupt status register to see whether our device
214+ * triggered the interrupt (when masking) or the next IRQ is
215+ * already pending (when unmasking).
216+ */
217+ if (mask != irq_pending) {
218+ mask_updated = false;
219+ goto done;
220+ }
221+
222+ origcmd = cmd_status_dword;
223+ newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
224+ if (mask)
225+ newcmd |= PCI_COMMAND_INTX_DISABLE;
226+ if (newcmd != origcmd)
227+ bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
228+
229+done:
230+ raw_spin_unlock_irqrestore(&pci_lock, flags);
231+
232+ return mask_updated;
233+}
234+
235+/**
236+ * pci_check_and_mask_intx - mask INTx on pending interrupt
237+ * @dev: the PCI device to operate on
238+ *
239+ * Check if the device dev has its INTx line asserted, mask it and return
240+ * true in that case. False is returned if no interrupt was pending.
241+ */
242+bool pci_check_and_mask_intx(struct pci_dev *dev)
243+{
244+ return pci_check_and_set_intx_mask(dev, true);
245+}
246+EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
247+
248+/**
249+ * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
250+ * @dev: the PCI device to operate on
251+ *
252+ * Check if the device dev has its INTx line asserted, unmask it if not and
253+ * return true. False is returned and the mask remains active if there was
254+ * still an interrupt pending.
255+ */
256+bool pci_check_and_unmask_intx(struct pci_dev *dev)
257+{
258+ return pci_check_and_set_intx_mask(dev, false);
259+}
260+EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
261+
262+/**
263+ * pcibios_penalize_isa_irq - penalize an ISA IRQ
264+ * @irq: ISA IRQ to penalize
265+ * @active: IRQ active or not
266+ *
267+ * Permits the platform to provide architecture-specific functionality when
268+ * penalizing ISA IRQs. This is the default implementation. Architecture
269+ * implementations can override this.
270+ */
271+void __weak pcibios_penalize_isa_irq(int irq, int active) {}
272+
273+int __weak pcibios_alloc_irq(struct pci_dev *dev)
274+{
275+ return 0;
276+}
277+
278+void __weak pcibios_free_irq(struct pci_dev *dev)
279+{
280+}
drivers/pci/mmap.c+29−0
@@ -11,6 +11,8 @@ · 10 unmodified lines
1111 #include <linux/mm.h>
1212 #include <linux/pci.h>
1313
14+#include "pci.h"
15+
1416 #ifdef ARCH_GENERIC_PCI_MMAP_RESOURCE
1517
1618 static const struct vm_operations_struct pci_phys_vm_ops = {
@@ -50,3 +52,30 @@ int pci_mmap_resource_range(struct pci_dev *pdev, int bar, · 33 unmodified lines
5052 }
5153
5254 #endif
55+
56+#if (defined(CONFIG_SYSFS) || defined(CONFIG_PROC_FS)) && \
57+ (defined(HAVE_PCI_MMAP) || defined(ARCH_GENERIC_PCI_MMAP_RESOURCE))
58+
59+int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vma,
60+ enum pci_mmap_api mmap_api)
61+{
62+ resource_size_t pci_start = 0, pci_end;
63+ unsigned long nr, start, size;
64+
65+ if (pci_resource_len(pdev, resno) == 0)
66+ return 0;
67+ nr = vma_pages(vma);
68+ start = vma->vm_pgoff;
69+ size = ((pci_resource_len(pdev, resno) - 1) >> PAGE_SHIFT) + 1;
70+ if (mmap_api == PCI_MMAP_PROCFS) {
71+ pci_resource_to_user(pdev, resno, &pdev->resource[resno],
72+ &pci_start, &pci_end);
73+ pci_start >>= PAGE_SHIFT;
74+ }
75+ if (start >= pci_start && start < pci_start + size &&
76+ start + nr <= pci_start + size)
77+ return 1;
78+ return 0;
79+}
80+
81+#endif
drivers/pci/p2pdma.c+1−1
@@ -661,7 +661,7 @@ done: · 660 unmodified lines
661661 p2pdma = rcu_dereference(provider->p2pdma);
662662 if (p2pdma)
663663 xa_store(&p2pdma->map_types, map_types_idx(client),
664− xa_mk_value(map_type), GFP_KERNEL);
664+ xa_mk_value(map_type), GFP_ATOMIC);
665665 rcu_read_unlock();
666666 return map_type;
667667 }
drivers/pci/pci-driver.c+9−14
@@ -419,15 +419,6 @@ static int __pci_device_probe(struct pci_driver *drv, struct pci_dev *pci_dev) · 418 unmodified lines
419419 return error;
420420 }
421421
422−int __weak pcibios_alloc_irq(struct pci_dev *dev)
423−{
424− return 0;
425−}
426−
427−void __weak pcibios_free_irq(struct pci_dev *dev)
428−{
429−}
430−
431422 #ifdef CONFIG_PCI_IOV
432423 static inline bool pci_device_can_probe(struct pci_dev *pdev)
433424 {
@@ -473,6 +464,13 @@ static void pci_device_remove(struct device *dev) · 39 unmodified lines
473464
474465 if (drv->remove) {
475466 pm_runtime_get_sync(dev);
467+ /*
468+ * If the driver provides a .runtime_idle() callback and it has
469+ * started to run already, it may continue to run in parallel
470+ * with the code below, so wait until all of the runtime PM
471+ * activity has completed.
472+ */
473+ pm_runtime_barrier(dev);
476474 drv->remove(pci_dev);
477475 pm_runtime_put_noidle(dev);
478476 }
@@ -1382,10 +1380,7 @@ static int pci_pm_runtime_idle(struct device *dev) · 903 unmodified lines
13821380 if (!pci_dev->driver)
13831381 return 0;
13841382
1385− if (!pm)
1386− return -ENOSYS;
1387−
1388− if (pm->runtime_idle)
1383+ if (pm && pm->runtime_idle)
13891384 return pm->runtime_idle(dev);
13901385
13911386 return 0;
@@ -1714,7 +1709,7 @@ static int pcie_port_bus_match(struct device *dev, struct device_driver *drv) · 322 unmodified lines
17141709 return 1;
17151710 }
17161711
1717−struct bus_type pcie_port_bus_type = {
1712+const struct bus_type pcie_port_bus_type = {
17181713 .name = "pci_express",
17191714 .match = pcie_port_bus_match,
17201715 };
drivers/pci/pci-sysfs.c+75−92
@@ -1022,29 +1022,6 @@ void pci_remove_legacy_files(struct pci_bus *b) · 1021 unmodified lines
10221022 #endif /* HAVE_PCI_LEGACY */
10231023
10241024 #if defined(HAVE_PCI_MMAP) || defined(ARCH_GENERIC_PCI_MMAP_RESOURCE)
1025−
1026−int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vma,
1027− enum pci_mmap_api mmap_api)
1028−{
1029− unsigned long nr, start, size;
1030− resource_size_t pci_start = 0, pci_end;
1031−
1032− if (pci_resource_len(pdev, resno) == 0)
1033− return 0;
1034− nr = vma_pages(vma);
1035− start = vma->vm_pgoff;
1036− size = ((pci_resource_len(pdev, resno) - 1) >> PAGE_SHIFT) + 1;
1037− if (mmap_api == PCI_MMAP_PROCFS) {
1038− pci_resource_to_user(pdev, resno, &pdev->resource[resno],
1039− &pci_start, &pci_end);
1040− pci_start >>= PAGE_SHIFT;
1041− }
1042− if (start >= pci_start && start < pci_start + size &&
1043− start + nr <= pci_start + size)
1044− return 1;
1045− return 0;
1046−}
1047−
10481025 /**
10491026 * pci_mmap_resource - map a PCI resource into user memory space
10501027 * @kobj: kobject for mapping
@@ -1410,79 +1387,89 @@ static const struct attribute_group pci_dev_reset_attr_group = { · 359 unmodified lines
14101387 .is_visible = pci_dev_reset_attr_is_visible,
14111388 };
14121389
1390+static ssize_t __resource_resize_show(struct device *dev, int n, char *buf)
1391+{
1392+ struct pci_dev *pdev = to_pci_dev(dev);
1393+ ssize_t ret;
1394+
1395+ pci_config_pm_runtime_get(pdev);
1396+
1397+ ret = sysfs_emit(buf, "%016llx\n",
1398+ (u64)pci_rebar_get_possible_sizes(pdev, n));
1399+
1400+ pci_config_pm_runtime_put(pdev);
1401+
1402+ return ret;
1403+}
1404+
1405+static ssize_t __resource_resize_store(struct device *dev, int n,
1406+ const char *buf, size_t count)
1407+{
1408+ struct pci_dev *pdev = to_pci_dev(dev);
1409+ unsigned long size, flags;
1410+ int ret, i;
1411+ u16 cmd;
1412+
1413+ if (kstrtoul(buf, 0, &size) < 0)
1414+ return -EINVAL;
1415+
1416+ device_lock(dev);
1417+ if (dev->driver) {
1418+ ret = -EBUSY;
1419+ goto unlock;
1420+ }
1421+
1422+ pci_config_pm_runtime_get(pdev);
1423+
1424+ if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
1425+ ret = aperture_remove_conflicting_pci_devices(pdev,
1426+ "resourceN_resize");
1427+ if (ret)
1428+ goto pm_put;
1429+ }
1430+
1431+ pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1432+ pci_write_config_word(pdev, PCI_COMMAND,
1433+ cmd & ~PCI_COMMAND_MEMORY);
1434+
1435+ flags = pci_resource_flags(pdev, n);
1436+
1437+ pci_remove_resource_files(pdev);
1438+
1439+ for (i = 0; i < PCI_STD_NUM_BARS; i++) {
1440+ if (pci_resource_len(pdev, i) &&
1441+ pci_resource_flags(pdev, i) == flags)
1442+ pci_release_resource(pdev, i);
1443+ }
1444+
1445+ ret = pci_resize_resource(pdev, n, size);
1446+
1447+ pci_assign_unassigned_bus_resources(pdev->bus);
1448+
1449+ if (pci_create_resource_files(pdev))
1450+ pci_warn(pdev, "Failed to recreate resource files after BAR resizing\n");
1451+
1452+ pci_write_config_word(pdev, PCI_COMMAND, cmd);
1453+pm_put:
1454+ pci_config_pm_runtime_put(pdev);
1455+unlock:
1456+ device_unlock(dev);
1457+
1458+ return ret ? ret : count;
1459+}
1460+
14131461 #define pci_dev_resource_resize_attr(n) \
14141462 static ssize_t resource##n##_resize_show(struct device *dev, \
14151463 struct device_attribute *attr, \
1416− char * buf) \
1464+ char *buf) \
14171465 { \
1418− struct pci_dev *pdev = to_pci_dev(dev); \
1419− ssize_t ret; \
1420− \
1421− pci_config_pm_runtime_get(pdev); \
1422− \
1423− ret = sysfs_emit(buf, "%016llx\n", \
1424− (u64)pci_rebar_get_possible_sizes(pdev, n)); \
1425− \
1426− pci_config_pm_runtime_put(pdev); \
1427− \
1428− return ret; \
1466+ return __resource_resize_show(dev, n, buf); \
14291467 } \
1430− \
14311468 static ssize_t resource##n##_resize_store(struct device *dev, \
14321469 struct device_attribute *attr,\
14331470 const char *buf, size_t count)\
14341471 { \
1435− struct pci_dev *pdev = to_pci_dev(dev); \
1436− unsigned long size, flags; \
1437− int ret, i; \
1438− u16 cmd; \
1439− \
1440− if (kstrtoul(buf, 0, &size) < 0) \
1441− return -EINVAL; \
1442− \
1443− device_lock(dev); \
1444− if (dev->driver) { \
1445− ret = -EBUSY; \
1446− goto unlock; \
1447− } \
1448− \
1449− pci_config_pm_runtime_get(pdev); \
1450− \
1451− if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { \
1452− ret = aperture_remove_conflicting_pci_devices(pdev, \
1453− "resourceN_resize"); \
1454− if (ret) \
1455− goto pm_put; \
1456− } \
1457− \
1458− pci_read_config_word(pdev, PCI_COMMAND, &cmd); \
1459− pci_write_config_word(pdev, PCI_COMMAND, \
1460− cmd & ~PCI_COMMAND_MEMORY); \
1461− \
1462− flags = pci_resource_flags(pdev, n); \
1463− \
1464− pci_remove_resource_files(pdev); \
1465− \
1466− for (i = 0; i < PCI_STD_NUM_BARS; i++) { \
1467− if (pci_resource_len(pdev, i) && \
1468− pci_resource_flags(pdev, i) == flags) \
1469− pci_release_resource(pdev, i); \
1470− } \
1471− \
1472− ret = pci_resize_resource(pdev, n, size); \
1473− \
1474− pci_assign_unassigned_bus_resources(pdev->bus); \
1475− \
1476− if (pci_create_resource_files(pdev)) \
1477− pci_warn(pdev, "Failed to recreate resource files after BAR resizing\n");\
1478− \
1479− pci_write_config_word(pdev, PCI_COMMAND, cmd); \
1480−pm_put: \
1481− pci_config_pm_runtime_put(pdev); \
1482−unlock: \
1483− device_unlock(dev); \
1484− \
1485− return ret ? ret : count; \
1472+ return __resource_resize_store(dev, n, buf, count); \
14861473 } \
14871474 static DEVICE_ATTR_RW(resource##n##_resize)
14881475
@@ -1660,7 +1647,7 @@ static const struct attribute_group pcie_dev_attr_group = { · 171 unmodified lines
16601647 .is_visible = pcie_dev_attrs_are_visible,
16611648 };
16621649
1663−static const struct attribute_group *pci_dev_attr_groups[] = {
1650+const struct attribute_group *pci_dev_attr_groups[] = {
16641651 &pci_dev_attr_group,
16651652 &pci_dev_hp_attr_group,
16661653 #ifdef CONFIG_PCI_IOV
@@ -1677,7 +1664,3 @@ static const struct attribute_group *pci_dev_attr_groups[] = { · 10 unmodified lines
16771664 #endif
16781665 NULL,
16791666 };
1680−
1681−const struct device_type pci_dev_type = {
1682− .groups = pci_dev_attr_groups,
1683−};
drivers/pci/pci.c+38−458
@@ -24,7 +24,6 @@ · 23 unmodified lines
2424 #include <linux/log2.h>
2525 #include <linux/logic_pio.h>
2626 #include <linux/pm_wakeup.h>
27−#include <linux/interrupt.h>
2827 #include <linux/device.h>
2928 #include <linux/pm_runtime.h>
3029 #include <linux/pci_hotplug.h>
@@ -1067,6 +1066,34 @@ disable_acs_redir: · 1036 unmodified lines
10671066 pci_disable_acs_redir(dev);
10681067 }
10691068
1069+/**
1070+ * pcie_read_tlp_log - read TLP Header Log
1071+ * @dev: PCIe device
1072+ * @where: PCI Config offset of TLP Header Log
1073+ * @tlp_log: TLP Log structure to fill
1074+ *
1075+ * Fill @tlp_log from TLP Header Log registers, e.g., AER or DPC.
1076+ *
1077+ * Return: 0 on success and filled TLP Log structure, <0 on error.
1078+ */
1079+int pcie_read_tlp_log(struct pci_dev *dev, int where,
1080+ struct pcie_tlp_log *tlp_log)
1081+{
1082+ int i, ret;
1083+
1084+ memset(tlp_log, 0, sizeof(*tlp_log));
1085+
1086+ for (i = 0; i < 4; i++) {
1087+ ret = pci_read_config_dword(dev, where + i * 4,
1088+ &tlp_log->dw[i]);
1089+ if (ret)
1090+ return pcibios_err_to_errno(ret);
1091+ }
1092+
1093+ return 0;
1094+}
1095+EXPORT_SYMBOL_GPL(pcie_read_tlp_log);
1096+
10701097 /**
10711098 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
10721099 * @dev: PCI device to have its BARs restored
@@ -1649,25 +1676,10 @@ static int pci_save_pcie_state(struct pci_dev *dev) · 576 unmodified lines
16491676 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
16501677 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
16511678
1652− return 0;
1653−}
1654−
1655−void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1656−{
1657−#ifdef CONFIG_PCIEASPM
1658− struct pci_dev *bridge;
1659− u32 ctl;
1679+ pci_save_aspm_l1ss_state(dev);
1680+ pci_save_ltr_state(dev);
16601681
1661− bridge = pci_upstream_bridge(dev);
1662− if (bridge && bridge->ltr_path) {
1663− pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1664− if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1665− pci_dbg(bridge, "re-enabling LTR\n");
1666− pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1667− PCI_EXP_DEVCTL2_LTR_EN);
1668− }
1669− }
1670−#endif
1682+ return 0;
16711683 }
16721684
16731685 static void pci_restore_pcie_state(struct pci_dev *dev)
@@ -1676,6 +1688,13 @@ static void pci_restore_pcie_state(struct pci_dev *dev) · 2 unmodified lines
16761688 struct pci_cap_saved_state *save_state;
16771689 u16 *cap;
16781690
1691+ /*
1692+ * Restore max latencies (in the LTR capability) before enabling
1693+ * LTR itself in PCI_EXP_DEVCTL2.
1694+ */
1695+ pci_restore_ltr_state(dev);
1696+ pci_restore_aspm_l1ss_state(dev);
1697+
16791698 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
16801699 if (!save_state)
16811700 return;
@@ -1733,46 +1752,6 @@ static void pci_restore_pcix_state(struct pci_dev *dev) · 51 unmodified lines
17331752 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
17341753 }
17351754
1736−static void pci_save_ltr_state(struct pci_dev *dev)
1737−{
1738− int ltr;
1739− struct pci_cap_saved_state *save_state;
1740− u32 *cap;
1741−
1742− if (!pci_is_pcie(dev))
1743− return;
1744−
1745− ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1746− if (!ltr)
1747− return;
1748−
1749− save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1750− if (!save_state) {
1751− pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1752− return;
1753− }
1754−
1755− /* Some broken devices only support dword access to LTR */
1756− cap = &save_state->cap.data[0];
1757− pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
1758−}
1759−
1760−static void pci_restore_ltr_state(struct pci_dev *dev)
1761−{
1762− struct pci_cap_saved_state *save_state;
1763− int ltr;
1764− u32 *cap;
1765−
1766− save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1767− ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1768− if (!save_state || !ltr)
1769− return;
1770−
1771− /* Some broken devices only support dword access to LTR */
1772− cap = &save_state->cap.data[0];
1773− pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
1774−}
1775−
17761755 /**
17771756 * pci_save_state - save the PCI configuration space of a device before
17781757 * suspending
@@ -1797,7 +1776,6 @@ int pci_save_state(struct pci_dev *dev) · 18 unmodified lines
17971776 if (i != 0)
17981777 return i;
17991778
1800− pci_save_ltr_state(dev);
18011779 pci_save_dpc_state(dev);
18021780 pci_save_aer_state(dev);
18031781 pci_save_ptm_state(dev);
@@ -1898,12 +1876,6 @@ void pci_restore_state(struct pci_dev *dev) · 94 unmodified lines
18981876 if (!dev->state_saved)
18991877 return;
19001878
1901− /*
1902− * Restore max latencies (in the LTR capability) before enabling
1903− * LTR itself (in the PCIe capability).
1904− */
1905− pci_restore_ltr_state(dev);
1906−
19071879 pci_restore_pcie_state(dev);
19081880 pci_restore_pasid_state(dev);
19091881 pci_restore_pri_state(dev);
@@ -2183,107 +2155,6 @@ int pci_enable_device(struct pci_dev *dev) · 273 unmodified lines
21832155 }
21842156 EXPORT_SYMBOL(pci_enable_device);
21852157
2186−/*
2187− * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2188− * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2189− * there's no need to track it separately. pci_devres is initialized
2190− * when a device is enabled using managed PCI device enable interface.
2191− */
2192−struct pci_devres {
2193− unsigned int enabled:1;
2194− unsigned int pinned:1;
2195− unsigned int orig_intx:1;
2196− unsigned int restore_intx:1;
2197− unsigned int mwi:1;
2198− u32 region_mask;
2199−};
2200−
2201−static void pcim_release(struct device *gendev, void *res)
2202−{
2203− struct pci_dev *dev = to_pci_dev(gendev);
2204− struct pci_devres *this = res;
2205− int i;
2206−
2207− for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2208− if (this->region_mask & (1 << i))
2209− pci_release_region(dev, i);
2210−
2211− if (this->mwi)
2212− pci_clear_mwi(dev);
2213−
2214− if (this->restore_intx)
2215− pci_intx(dev, this->orig_intx);
2216−
2217− if (this->enabled && !this->pinned)
2218− pci_disable_device(dev);
2219−}
2220−
2221−static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2222−{
2223− struct pci_devres *dr, *new_dr;
2224−
2225− dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2226− if (dr)
2227− return dr;
2228−
2229− new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2230− if (!new_dr)
2231− return NULL;
2232− return devres_get(&pdev->dev, new_dr, NULL, NULL);
2233−}
2234−
2235−static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2236−{
2237− if (pci_is_managed(pdev))
2238− return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2239− return NULL;
2240−}
2241−
2242−/**
2243− * pcim_enable_device - Managed pci_enable_device()
2244− * @pdev: PCI device to be initialized
2245− *
2246− * Managed pci_enable_device().
2247− */
2248−int pcim_enable_device(struct pci_dev *pdev)
2249−{
2250− struct pci_devres *dr;
2251− int rc;
2252−
2253− dr = get_pci_dr(pdev);
2254− if (unlikely(!dr))
2255− return -ENOMEM;
2256− if (dr->enabled)
2257− return 0;
2258−
2259− rc = pci_enable_device(pdev);
2260− if (!rc) {
2261− pdev->is_managed = 1;
2262− dr->enabled = 1;
2263− }
2264− return rc;
2265−}
2266−EXPORT_SYMBOL(pcim_enable_device);
2267−
2268−/**
2269− * pcim_pin_device - Pin managed PCI device
2270− * @pdev: PCI device to pin
2271− *
2272− * Pin managed PCI device @pdev. Pinned device won't be disabled on
2273− * driver detach. @pdev must have been enabled with
2274− * pcim_enable_device().
2275− */
2276−void pcim_pin_device(struct pci_dev *pdev)
2277−{
2278− struct pci_devres *dr;
2279−
2280− dr = find_pci_dr(pdev);
2281− WARN_ON(!dr || !dr->enabled);
2282− if (dr)
2283− dr->pinned = 1;
2284−}
2285−EXPORT_SYMBOL(pcim_pin_device);
2286−
22872158 /*
22882159 * pcibios_device_add - provide arch specific hooks when adding device dev
22892160 * @dev: the PCI device being added
@@ -2318,17 +2189,6 @@ void __weak pcibios_release_device(struct pci_dev *dev) {} · 28 unmodified lines
23182189 */
23192190 void __weak pcibios_disable_device(struct pci_dev *dev) {}
23202191
2321−/**
2322− * pcibios_penalize_isa_irq - penalize an ISA IRQ
2323− * @irq: ISA IRQ to penalize
2324− * @active: IRQ active or not
2325− *
2326− * Permits the platform to provide architecture-specific functionality when
2327− * penalizing ISA IRQs. This is the default implementation. Architecture
2328− * implementations can override this.
2329− */
2330−void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2331−
23322192 static void do_pci_disable_device(struct pci_dev *dev)
23332193 {
23342194 u16 pci_command;
@@ -3997,66 +3857,6 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) · 1662 unmodified lines
39973857 }
39983858 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
39993859
4000−/**
4001− * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
4002− * @dev: the PCI device
4003− * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
4004− *
4005− * Perform INTx swizzling for a device behind one level of bridge. This is
4006− * required by section 9.1 of the PCI-to-PCI bridge specification for devices
4007− * behind bridges on add-in cards. For devices with ARI enabled, the slot
4008− * number is always 0 (see the Implementation Note in section 2.2.8.1 of
4009− * the PCI Express Base Specification, Revision 2.1)
4010− */
4011−u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
4012−{
4013− int slot;
4014−
4015− if (pci_ari_enabled(dev->bus))
4016− slot = 0;
4017− else
4018− slot = PCI_SLOT(dev->devfn);
4019−
4020− return (((pin - 1) + slot) % 4) + 1;
4021−}
4022−
4023−int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
4024−{
4025− u8 pin;
4026−
4027− pin = dev->pin;
4028− if (!pin)
4029− return -1;
4030−
4031− while (!pci_is_root_bus(dev->bus)) {
4032− pin = pci_swizzle_interrupt_pin(dev, pin);
4033− dev = dev->bus->self;
4034− }
4035− *bridge = dev;
4036− return pin;
4037−}
4038−
4039−/**
4040− * pci_common_swizzle - swizzle INTx all the way to root bridge
4041− * @dev: the PCI device
4042− * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
4043− *
4044− * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
4045− * bridges all the way up to a PCI root bus.
4046− */
4047−u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
4048−{
4049− u8 pin = *pinp;
4050−
4051− while (!pci_is_root_bus(dev->bus)) {
4052− pin = pci_swizzle_interrupt_pin(dev, pin);
4053− dev = dev->bus->self;
4054− }
4055− *pinp = pin;
4056− return PCI_SLOT(dev->devfn);
4057−}
4058−EXPORT_SYMBOL_GPL(pci_common_swizzle);
4059−
40603860 /**
40613861 * pci_release_region - Release a PCI bar
40623862 * @pdev: PCI device whose resources were previously reserved by
@@ -4385,133 +4185,6 @@ void pci_unmap_iospace(struct resource *res) · 322 unmodified lines
43854185 }
43864186 EXPORT_SYMBOL(pci_unmap_iospace);
43874187
4388−static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4389−{
4390− struct resource **res = ptr;
4391−
4392− pci_unmap_iospace(*res);
4393−}
4394−
4395−/**
4396− * devm_pci_remap_iospace - Managed pci_remap_iospace()
4397− * @dev: Generic device to remap IO address for
4398− * @res: Resource describing the I/O space
4399− * @phys_addr: physical address of range to be mapped
4400− *
4401− * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4402− * detach.
4403− */
4404−int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4405− phys_addr_t phys_addr)
4406−{
4407− const struct resource **ptr;
4408− int error;
4409−
4410− ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4411− if (!ptr)
4412− return -ENOMEM;
4413−
4414− error = pci_remap_iospace(res, phys_addr);
4415− if (error) {
4416− devres_free(ptr);
4417− } else {
4418− *ptr = res;
4419− devres_add(dev, ptr);
4420− }
4421−
4422− return error;
4423−}
4424−EXPORT_SYMBOL(devm_pci_remap_iospace);
4425−
4426−/**
4427− * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4428− * @dev: Generic device to remap IO address for
4429− * @offset: Resource address to map
4430− * @size: Size of map
4431− *
4432− * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4433− * detach.
4434− */
4435−void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4436− resource_size_t offset,
4437− resource_size_t size)
4438−{
4439− void __iomem **ptr, *addr;
4440−
4441− ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4442− if (!ptr)
4443− return NULL;
4444−
4445− addr = pci_remap_cfgspace(offset, size);
4446− if (addr) {
4447− *ptr = addr;
4448− devres_add(dev, ptr);
4449− } else
4450− devres_free(ptr);
4451−
4452− return addr;
4453−}
4454−EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4455−
4456−/**
4457− * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4458− * @dev: generic device to handle the resource for
4459− * @res: configuration space resource to be handled
4460− *
4461− * Checks that a resource is a valid memory region, requests the memory
4462− * region and ioremaps with pci_remap_cfgspace() API that ensures the
4463− * proper PCI configuration space memory attributes are guaranteed.
4464− *
4465− * All operations are managed and will be undone on driver detach.
4466− *
4467− * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4468− * on failure. Usage example::
4469− *
4470− * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4471− * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4472− * if (IS_ERR(base))
4473− * return PTR_ERR(base);
4474− */
4475−void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4476− struct resource *res)
4477−{
4478− resource_size_t size;
4479− const char *name;
4480− void __iomem *dest_ptr;
4481−
4482− BUG_ON(!dev);
4483−
4484− if (!res || resource_type(res) != IORESOURCE_MEM) {
4485− dev_err(dev, "invalid resource\n");
4486− return IOMEM_ERR_PTR(-EINVAL);
4487− }
4488−
4489− size = resource_size(res);
4490−
4491− if (res->name)
4492− name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4493− res->name);
4494− else
4495− name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4496− if (!name)
4497− return IOMEM_ERR_PTR(-ENOMEM);
4498−
4499− if (!devm_request_mem_region(dev, res->start, size, name)) {
4500− dev_err(dev, "can't request region for resource %pR\n", res);
4501− return IOMEM_ERR_PTR(-EBUSY);
4502− }
4503−
4504− dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4505− if (!dest_ptr) {
4506− dev_err(dev, "ioremap failed for resource %pR\n", res);
4507− devm_release_mem_region(dev, res->start, size);
4508− dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4509− }
4510−
4511− return dest_ptr;
4512−}
4513−EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4514−
45154188 static void __pci_set_master(struct pci_dev *dev, bool enable)
45164189 {
45174190 u16 old_cmd, cmd;
@@ -4661,27 +4334,6 @@ int pci_set_mwi(struct pci_dev *dev) · 143 unmodified lines
46614334 }
46624335 EXPORT_SYMBOL(pci_set_mwi);
46634336
4664−/**
4665− * pcim_set_mwi - a device-managed pci_set_mwi()
4666− * @dev: the PCI device for which MWI is enabled
4667− *
4668− * Managed pci_set_mwi().
4669− *
4670− * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4671− */
4672−int pcim_set_mwi(struct pci_dev *dev)
4673−{
4674− struct pci_devres *dr;
4675−
4676− dr = find_pci_dr(dev);
4677− if (!dr)
4678− return -ENOMEM;
4679−
4680− dr->mwi = 1;
4681− return pci_set_mwi(dev);
4682−}
4683−EXPORT_SYMBOL(pcim_set_mwi);
4684−
46854337 /**
46864338 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
46874339 * @dev: the PCI device for which MWI is enabled
@@ -4770,78 +4422,6 @@ void pci_intx(struct pci_dev *pdev, int enable) · 82 unmodified lines
47704422 }
47714423 EXPORT_SYMBOL_GPL(pci_intx);
47724424
4773−static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4774−{
4775− struct pci_bus *bus = dev->bus;
4776− bool mask_updated = true;
4777− u32 cmd_status_dword;
4778− u16 origcmd, newcmd;
4779− unsigned long flags;
4780− bool irq_pending;
4781−
4782− /*
4783− * We do a single dword read to retrieve both command and status.
4784− * Document assumptions that make this possible.
4785− */
4786− BUILD_BUG_ON(PCI_COMMAND % 4);
4787− BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4788−
4789− raw_spin_lock_irqsave(&pci_lock, flags);
4790−
4791− bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4792−
4793− irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4794−
4795− /*
4796− * Check interrupt status register to see whether our device
4797− * triggered the interrupt (when masking) or the next IRQ is
4798− * already pending (when unmasking).
4799− */
4800− if (mask != irq_pending) {
4801− mask_updated = false;
4802− goto done;
4803− }
4804−
4805− origcmd = cmd_status_dword;
4806− newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4807− if (mask)
4808− newcmd |= PCI_COMMAND_INTX_DISABLE;
4809− if (newcmd != origcmd)
4810− bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4811−
4812−done:
4813− raw_spin_unlock_irqrestore(&pci_lock, flags);
4814−
4815− return mask_updated;
4816−}
4817−
4818−/**
4819− * pci_check_and_mask_intx - mask INTx on pending interrupt
4820− * @dev: the PCI device to operate on
4821− *
4822− * Check if the device dev has its INTx line asserted, mask it and return
4823− * true in that case. False is returned if no interrupt was pending.
4824− */
4825−bool pci_check_and_mask_intx(struct pci_dev *dev)
4826−{
4827− return pci_check_and_set_intx_mask(dev, true);
4828−}
4829−EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4830−
4831−/**
4832− * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4833− * @dev: the PCI device to operate on
4834− *
4835− * Check if the device dev has its INTx line asserted, unmask it if not and
4836− * return true. False is returned and the mask remains active if there was
4837− * still an interrupt pending.
4838− */
4839−bool pci_check_and_unmask_intx(struct pci_dev *dev)
4840−{
4841− return pci_check_and_set_intx_mask(dev, false);
4842−}
4843−EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4844−
48454425 /**
48464426 * pci_wait_for_pending_transaction - wait for pending transaction
48474427 * @dev: the PCI device to operate on
drivers/pci/pci.h+48−7
@@ -31,9 +31,6 @@ bool pcie_cap_has_rtctl(const struct pci_dev *dev); · 30 unmodified lines
3131
3232 /* Functions internal to the PCI core code */
3333
34−int pci_create_sysfs_dev_files(struct pci_dev *pdev);
35−void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
36−void pci_cleanup_rom(struct pci_dev *dev);
3734 #ifdef CONFIG_DMI
3835 extern const struct attribute_group pci_dev_smbios_attr_group;
3936 #endif
@@ -97,7 +94,6 @@ void pci_msi_init(struct pci_dev *dev); · 57 unmodified lines
9794 void pci_msix_init(struct pci_dev *dev);
9895 bool pci_bridge_d3_possible(struct pci_dev *dev);
9996 void pci_bridge_d3_update(struct pci_dev *dev);
100−void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
10197 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
10298
10399 static inline void pci_wakeup_event(struct pci_dev *dev)
@@ -152,7 +148,7 @@ static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } · 48 unmodified lines
152148 /* Functions for PCI Hotplug drivers to use */
153149 int pci_hp_add_bridge(struct pci_dev *dev);
154150
155−#ifdef HAVE_PCI_LEGACY
151+#if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY)
156152 void pci_create_legacy_files(struct pci_bus *bus);
157153 void pci_remove_legacy_files(struct pci_bus *bus);
158154 #else
@@ -185,10 +181,22 @@ static inline int pci_no_d1d2(struct pci_dev *dev) · 26 unmodified lines
185181 return (dev->no_d1d2 || parent_dstates);
186182
187183 }
184+
185+#ifdef CONFIG_SYSFS
186+int pci_create_sysfs_dev_files(struct pci_dev *pdev);
187+void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
188188 extern const struct attribute_group *pci_dev_groups[];
189+extern const struct attribute_group *pci_dev_attr_groups[];
189190 extern const struct attribute_group *pcibus_groups[];
190−extern const struct device_type pci_dev_type;
191191 extern const struct attribute_group *pci_bus_groups[];
192+#else
193+static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; }
194+static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { }
195+#define pci_dev_groups NULL
196+#define pci_dev_attr_groups NULL
197+#define pcibus_groups NULL
198+#define pci_bus_groups NULL
199+#endif
192200
193201 extern unsigned long pci_hotplug_io_size;
194202 extern unsigned long pci_hotplug_mmio_size;
@@ -404,7 +412,7 @@ struct aer_err_info { · 209 unmodified lines
404412
405413 unsigned int status; /* COR/UNCOR Error Status */
406414 unsigned int mask; /* COR/UNCOR Error Mask */
407− struct aer_header_log_regs tlp; /* TLP Header */
415+ struct pcie_tlp_log tlp; /* TLP Header */
408416 };
409417
410418 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
@@ -563,16 +571,28 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, · 152 unmodified lines
563571
564572 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
565573 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
574+
575+/* ASPM-related functionality we need even without CONFIG_PCIEASPM */
576+void pci_save_ltr_state(struct pci_dev *dev);
577+void pci_restore_ltr_state(struct pci_dev *dev);
578+void pci_configure_aspm_l1ss(struct pci_dev *dev);
579+void pci_save_aspm_l1ss_state(struct pci_dev *dev);
580+void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
581+
566582 #ifdef CONFIG_PCIEASPM
567583 void pcie_aspm_init_link_state(struct pci_dev *pdev);
568584 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
569585 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
570586 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
587+void pci_configure_ltr(struct pci_dev *pdev);
588+void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);
571589 #else
572590 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
573591 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
574592 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
575593 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
594+static inline void pci_configure_ltr(struct pci_dev *pdev) { }
595+static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }
576596 #endif
577597
578598 #ifdef CONFIG_PCIE_ECRC
@@ -792,6 +812,27 @@ static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) · 213 unmodified lines
792812 }
793813 #endif
794814
815+/*
816+ * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
817+ * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
818+ * there's no need to track it separately. pci_devres is initialized
819+ * when a device is enabled using managed PCI device enable interface.
820+ *
821+ * TODO: Struct pci_devres and find_pci_dr() only need to be here because
822+ * they're used in pci.c. Port or move these functions to devres.c and
823+ * then remove them from here.
824+ */
825+struct pci_devres {
826+ unsigned int enabled:1;
827+ unsigned int pinned:1;
828+ unsigned int orig_intx:1;
829+ unsigned int restore_intx:1;
830+ unsigned int mwi:1;
831+ u32 region_mask;
832+};
833+
834+struct pci_devres *find_pci_dr(struct pci_dev *pdev);
835+
795836 /*
796837 * Config Address for PCI Configuration Mechanism #1
797838 *
drivers/pci/pcie/Makefile+1−1
@@ -6,7 +6,7 @@ pcieportdrv-y := portdrv.o rcec.o · 5 unmodified lines
66
77 obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o
88
9−obj-$(CONFIG_PCIEASPM) += aspm.o
9+obj-y += aspm.o
1010 obj-$(CONFIG_PCIEAER) += aer.o err.o
1111 obj-$(CONFIG_PCIEAER_INJECT) += aer_inject.o
1212 obj-$(CONFIG_PCIE_PME) += pme.o
drivers/pci/pcie/aer.c+6−14
@@ -664,11 +664,10 @@ static void pci_rootport_aer_stats_incr(struct pci_dev *pdev, · 663 unmodified lines
664664 }
665665 }
666666
667−static void __print_tlp_header(struct pci_dev *dev,
668− struct aer_header_log_regs *t)
667+static void __print_tlp_header(struct pci_dev *dev, struct pcie_tlp_log *t)
669668 {
670669 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n",
671− t->dw0, t->dw1, t->dw2, t->dw3);
670+ t->dw[0], t->dw[1], t->dw[2], t->dw[3]);
672671 }
673672
674673 static void __aer_print_error(struct pci_dev *dev,
@@ -1210,7 +1209,7 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) · 535 unmodified lines
12101209 {
12111210 int type = pci_pcie_type(dev);
12121211 int aer = dev->aer_cap;
1213− int temp;
1212+ u32 aercc;
12141213
12151214 /* Must reset in this function */
12161215 info->status = 0;
@@ -1241,19 +1240,12 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) · 24 unmodified lines
12411240 return 0;
12421241
12431242 /* Get First Error Pointer */
1244− pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);
1245− info->first_error = PCI_ERR_CAP_FEP(temp);
1243+ pci_read_config_dword(dev, aer + PCI_ERR_CAP, &aercc);
1244+ info->first_error = PCI_ERR_CAP_FEP(aercc);
12461245
12471246 if (info->status & AER_LOG_TLP_MASKS) {
12481247 info->tlp_header_valid = 1;
1249− pci_read_config_dword(dev,
1250− aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
1251− pci_read_config_dword(dev,
1252− aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
1253− pci_read_config_dword(dev,
1254− aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
1255− pci_read_config_dword(dev,
1256− aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
1248+ pcie_read_tlp_log(dev, aer + PCI_ERR_HEADER_LOG, &info->tlp);
12571249 }
12581250 }
12591251
drivers/pci/pcie/aspm.c+267−1
@@ -24,6 +24,166 @@ · 23 unmodified lines
2424
2525 #include "../pci.h"
2626
27+void pci_save_ltr_state(struct pci_dev *dev)
28+{
29+ int ltr;
30+ struct pci_cap_saved_state *save_state;
31+ u32 *cap;
32+
33+ if (!pci_is_pcie(dev))
34+ return;
35+
36+ ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
37+ if (!ltr)
38+ return;
39+
40+ save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
41+ if (!save_state) {
42+ pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
43+ return;
44+ }
45+
46+ /* Some broken devices only support dword access to LTR */
47+ cap = &save_state->cap.data[0];
48+ pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
49+}
50+
51+void pci_restore_ltr_state(struct pci_dev *dev)
52+{
53+ struct pci_cap_saved_state *save_state;
54+ int ltr;
55+ u32 *cap;
56+
57+ save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
58+ ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
59+ if (!save_state || !ltr)
60+ return;
61+
62+ /* Some broken devices only support dword access to LTR */
63+ cap = &save_state->cap.data[0];
64+ pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
65+}
66+
67+void pci_configure_aspm_l1ss(struct pci_dev *pdev)
68+{
69+ int rc;
70+
71+ pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
72+
73+ rc = pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_L1SS,
74+ 2 * sizeof(u32));
75+ if (rc)
76+ pci_err(pdev, "unable to allocate ASPM L1SS save buffer (%pe)\n",
77+ ERR_PTR(rc));
78+}
79+
80+void pci_save_aspm_l1ss_state(struct pci_dev *pdev)
81+{
82+ struct pci_cap_saved_state *save_state;
83+ u16 l1ss = pdev->l1ss;
84+ u32 *cap;
85+
86+ /*
87+ * Save L1 substate configuration. The ASPM L0s/L1 configuration
88+ * in PCI_EXP_LNKCTL_ASPMC is saved by pci_save_pcie_state().
89+ */
90+ if (!l1ss)
91+ return;
92+
93+ save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS);
94+ if (!save_state)
95+ return;
96+
97+ cap = &save_state->cap.data[0];
98+ pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL2, cap++);
99+ pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, cap++);
100+}
101+
102+void pci_restore_aspm_l1ss_state(struct pci_dev *pdev)
103+{
104+ struct pci_cap_saved_state *pl_save_state, *cl_save_state;
105+ struct pci_dev *parent = pdev->bus->self;
106+ u32 *cap, pl_ctl1, pl_ctl2, pl_l1_2_enable;
107+ u32 cl_ctl1, cl_ctl2, cl_l1_2_enable;
108+ u16 clnkctl, plnkctl;
109+
110+ /*
111+ * In case BIOS enabled L1.2 when resuming, we need to disable it first
112+ * on the downstream component before the upstream. So, don't attempt to
113+ * restore either until we are at the downstream component.
114+ */
115+ if (pcie_downstream_port(pdev) || !parent)
116+ return;
117+
118+ if (!pdev->l1ss || !parent->l1ss)
119+ return;
120+
121+ cl_save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS);
122+ pl_save_state = pci_find_saved_ext_cap(parent, PCI_EXT_CAP_ID_L1SS);
123+ if (!cl_save_state || !pl_save_state)
124+ return;
125+
126+ cap = &cl_save_state->cap.data[0];
127+ cl_ctl2 = *cap++;
128+ cl_ctl1 = *cap;
129+ cap = &pl_save_state->cap.data[0];
130+ pl_ctl2 = *cap++;
131+ pl_ctl1 = *cap;
132+
133+ /* Make sure L0s/L1 are disabled before updating L1SS config */
134+ pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &clnkctl);
135+ pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &plnkctl);
136+ if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, clnkctl) ||
137+ FIELD_GET(PCI_EXP_LNKCTL_ASPMC, plnkctl)) {
138+ pcie_capability_write_word(pdev, PCI_EXP_LNKCTL,
139+ clnkctl & ~PCI_EXP_LNKCTL_ASPMC);
140+ pcie_capability_write_word(parent, PCI_EXP_LNKCTL,
141+ plnkctl & ~PCI_EXP_LNKCTL_ASPMC);
142+ }
143+
144+ /*
145+ * Disable L1.2 on this downstream endpoint device first, followed
146+ * by the upstream
147+ */
148+ pci_clear_and_set_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1,
149+ PCI_L1SS_CTL1_L1_2_MASK, 0);
150+ pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
151+ PCI_L1SS_CTL1_L1_2_MASK, 0);
152+
153+ /*
154+ * In addition, Common_Mode_Restore_Time and LTR_L1.2_THRESHOLD
155+ * in PCI_L1SS_CTL1 must be programmed *before* setting the L1.2
156+ * enable bits, even though they're all in PCI_L1SS_CTL1.
157+ */
158+ pl_l1_2_enable = pl_ctl1 & PCI_L1SS_CTL1_L1_2_MASK;
159+ pl_ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;
160+ cl_l1_2_enable = cl_ctl1 & PCI_L1SS_CTL1_L1_2_MASK;
161+ cl_ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;
162+
163+ /* Write back without enables first (above we cleared them in ctl1) */
164+ pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, pl_ctl2);
165+ pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cl_ctl2);
166+ pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, pl_ctl1);
167+ pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cl_ctl1);
168+
169+ /* Then write back the enables */
170+ if (pl_l1_2_enable || cl_l1_2_enable) {
171+ pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
172+ pl_ctl1 | pl_l1_2_enable);
173+ pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1,
174+ cl_ctl1 | cl_l1_2_enable);
175+ }
176+
177+ /* Restore L0s/L1 if they were enabled */
178+ if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, clnkctl) ||
179+ FIELD_GET(PCI_EXP_LNKCTL_ASPMC, plnkctl)) {
180+ pcie_capability_write_word(parent, PCI_EXP_LNKCTL, clnkctl);
181+ pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, plnkctl);
182+ }
183+}
184+
185+#ifdef CONFIG_PCIEASPM
186+
27187 #ifdef MODULE_PARAM_PREFIX
28188 #undef MODULE_PARAM_PREFIX
29189 #endif
@@ -141,16 +301,42 @@ static int policy_to_clkpm_state(struct pcie_link_state *link) · 111 unmodified lines
141301 return 0;
142302 }
143303
304+static void pci_update_aspm_saved_state(struct pci_dev *dev)
305+{
306+ struct pci_cap_saved_state *save_state;
307+ u16 *cap, lnkctl, aspm_ctl;
308+
309+ save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
310+ if (!save_state)
311+ return;
312+
313+ pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &lnkctl);
314+
315+ /*
316+ * Update ASPM and CLKREQ bits of LNKCTL in save_state. We only
317+ * write PCI_EXP_LNKCTL_CCC during enumeration, so it shouldn't
318+ * change after being captured in save_state.
319+ */
320+ aspm_ctl = lnkctl & (PCI_EXP_LNKCTL_ASPMC | PCI_EXP_LNKCTL_CLKREQ_EN);
321+ lnkctl &= ~(PCI_EXP_LNKCTL_ASPMC | PCI_EXP_LNKCTL_CLKREQ_EN);
322+
323+ /* Depends on pci_save_pcie_state(): cap[1] is LNKCTL */
324+ cap = (u16 *)&save_state->cap.data[0];
325+ cap[1] = lnkctl | aspm_ctl;
326+}
327+
144328 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
145329 {
146330 struct pci_dev *child;
147331 struct pci_bus *linkbus = link->pdev->subordinate;
148332 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
149333
150− list_for_each_entry(child, &linkbus->devices, bus_list)
334+ list_for_each_entry(child, &linkbus->devices, bus_list) {
151335 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
152336 PCI_EXP_LNKCTL_CLKREQ_EN,
153337 val);
338+ pci_update_aspm_saved_state(child);
339+ }
154340 link->clkpm_enabled = !!enable;
155341 }
156342
@@ -769,6 +955,12 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) · 612 unmodified lines
769955 pcie_config_aspm_dev(parent, upstream);
770956
771957 link->aspm_enabled = state;
958+
959+ /* Update latest ASPM configuration in saved context */
960+ pci_save_aspm_l1ss_state(link->downstream);
961+ pci_update_aspm_saved_state(link->downstream);
962+ pci_save_aspm_l1ss_state(parent);
963+ pci_update_aspm_saved_state(parent);
772964 }
773965
774966 static void pcie_config_aspm_path(struct pcie_link_state *link)
@@ -938,6 +1130,78 @@ out: · 163 unmodified lines
9381130 up_read(&pci_bus_sem);
9391131 }
9401132
1133+void pci_bridge_reconfigure_ltr(struct pci_dev *pdev)
1134+{
1135+ struct pci_dev *bridge;
1136+ u32 ctl;
1137+
1138+ bridge = pci_upstream_bridge(pdev);
1139+ if (bridge && bridge->ltr_path) {
1140+ pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1141+ if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1142+ pci_dbg(bridge, "re-enabling LTR\n");
1143+ pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1144+ PCI_EXP_DEVCTL2_LTR_EN);
1145+ }
1146+ }
1147+}
1148+
1149+void pci_configure_ltr(struct pci_dev *pdev)
1150+{
1151+ struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
1152+ struct pci_dev *bridge;
1153+ u32 cap, ctl;
1154+
1155+ if (!pci_is_pcie(pdev))
1156+ return;
1157+
1158+ pcie_capability_read_dword(pdev, PCI_EXP_DEVCAP2, &cap);
1159+ if (!(cap & PCI_EXP_DEVCAP2_LTR))
1160+ return;
1161+
1162+ pcie_capability_read_dword(pdev, PCI_EXP_DEVCTL2, &ctl);
1163+ if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
1164+ if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) {
1165+ pdev->ltr_path = 1;
1166+ return;
1167+ }
1168+
1169+ bridge = pci_upstream_bridge(pdev);
1170+ if (bridge && bridge->ltr_path)
1171+ pdev->ltr_path = 1;
1172+
1173+ return;
1174+ }
1175+
1176+ if (!host->native_ltr)
1177+ return;
1178+
1179+ /*
1180+ * Software must not enable LTR in an Endpoint unless the Root
1181+ * Complex and all intermediate Switches indicate support for LTR.
1182+ * PCIe r4.0, sec 6.18.
1183+ */
1184+ if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) {
1185+ pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
1186+ PCI_EXP_DEVCTL2_LTR_EN);
1187+ pdev->ltr_path = 1;
1188+ return;
1189+ }
1190+
1191+ /*
1192+ * If we're configuring a hot-added device, LTR was likely
1193+ * disabled in the upstream bridge, so re-enable it before enabling
1194+ * it in the new device.
1195+ */
1196+ bridge = pci_upstream_bridge(pdev);
1197+ if (bridge && bridge->ltr_path) {
1198+ pci_bridge_reconfigure_ltr(pdev);
1199+ pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
1200+ PCI_EXP_DEVCTL2_LTR_EN);
1201+ pdev->ltr_path = 1;
1202+ }
1203+}
1204+
9411205 /* Recheck latencies and update aspm_capable for links under the root */
9421206 static void pcie_update_aspm_capable(struct pcie_link_state *root)
9431207 {
@@ -1447,3 +1711,5 @@ bool pcie_aspm_support_enabled(void) · 503 unmodified lines
14471711 {
14481712 return aspm_support_enabled;
14491713 }
1714+
1715+#endif /* CONFIG_PCIEASPM */
drivers/pci/pcie/dpc.c+65−11
@@ -190,7 +190,8 @@ out: · 189 unmodified lines
190190 static void dpc_process_rp_pio_error(struct pci_dev *pdev)
191191 {
192192 u16 cap = pdev->dpc_cap, dpc_status, first_error;
193− u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
193+ u32 status, mask, sev, syserr, exc, log, prefix;
194+ struct pcie_tlp_log tlp_log;
194195 int i;
195196
196197 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
@@ -216,16 +217,9 @@ static void dpc_process_rp_pio_error(struct pci_dev *pdev) · 19 unmodified lines
216217
217218 if (pdev->dpc_rp_log_size < 4)
218219 goto clear_status;
219− pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
220− &dw0);
221− pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
222− &dw1);
223− pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
224− &dw2);
225− pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
226− &dw3);
220+ pcie_read_tlp_log(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG, &tlp_log);
227221 pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
228− dw0, dw1, dw2, dw3);
222+ tlp_log.dw[0], tlp_log.dw[1], tlp_log.dw[2], tlp_log.dw[3]);
229223
230224 if (pdev->dpc_rp_log_size < 5)
231225 goto clear_status;
@@ -234,7 +228,7 @@ static void dpc_process_rp_pio_error(struct pci_dev *pdev) · 2 unmodified lines
234228
235229 for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) {
236230 pci_read_config_dword(pdev,
237− cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
231+ cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG + i * 4, &prefix);
238232 pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
239233 }
240234 clear_status:
@@ -303,10 +297,70 @@ void dpc_process_error(struct pci_dev *pdev) · 62 unmodified lines
303297 }
304298 }
305299
300+static void pci_clear_surpdn_errors(struct pci_dev *pdev)
301+{
302+ if (pdev->dpc_rp_extensions)
303+ pci_write_config_dword(pdev, pdev->dpc_cap +
304+ PCI_EXP_DPC_RP_PIO_STATUS, ~0);
305+
306+ /*
307+ * In practice, Surprise Down errors have been observed to also set
308+ * error bits in the Status Register as well as the Fatal Error
309+ * Detected bit in the Device Status Register.
310+ */
311+ pci_write_config_word(pdev, PCI_STATUS, 0xffff);
312+
313+ pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_FED);
314+}
315+
316+static void dpc_handle_surprise_removal(struct pci_dev *pdev)
317+{
318+ if (!pcie_wait_for_link(pdev, false)) {
319+ pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
320+ goto out;
321+ }
322+
323+ if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev))
324+ goto out;
325+
326+ pci_aer_raw_clear_status(pdev);
327+ pci_clear_surpdn_errors(pdev);
328+
329+ pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS,
330+ PCI_EXP_DPC_STATUS_TRIGGER);
331+
332+out:
333+ clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
334+ wake_up_all(&dpc_completed_waitqueue);
335+}
336+
337+static bool dpc_is_surprise_removal(struct pci_dev *pdev)
338+{
339+ u16 status;
340+
341+ if (!pdev->is_hotplug_bridge)
342+ return false;
343+
344+ if (pci_read_config_word(pdev, pdev->aer_cap + PCI_ERR_UNCOR_STATUS,
345+ &status))
346+ return false;
347+
348+ return status & PCI_ERR_UNC_SURPDN;
349+}
350+
306351 static irqreturn_t dpc_handler(int irq, void *context)
307352 {
308353 struct pci_dev *pdev = context;
309354
355+ /*
356+ * According to PCIe r6.0 sec 6.7.6, errors are an expected side effect
357+ * of async removal and should be ignored by software.
358+ */
359+ if (dpc_is_surprise_removal(pdev)) {
360+ dpc_handle_surprise_removal(pdev);
361+ return IRQ_HANDLED;
362+ }
363+
310364 dpc_process_error(pdev);
311365
312366 /* We configure DPC so it only triggers on ERR_FATAL */
drivers/pci/pcie/err.c+20−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #define dev_fmt(fmt) "AER: " fmt
1414
1515 #include <linux/pci.h>
16+#include <linux/pm_runtime.h>
1617 #include <linux/module.h>
1718 #include <linux/kernel.h>
1819 #include <linux/errno.h>
@@ -85,6 +86,18 @@ static int report_error_detected(struct pci_dev *dev, · 66 unmodified lines
8586 return 0;
8687 }
8788
89+static int pci_pm_runtime_get_sync(struct pci_dev *pdev, void *data)
90+{
91+ pm_runtime_get_sync(&pdev->dev);
92+ return 0;
93+}
94+
95+static int pci_pm_runtime_put(struct pci_dev *pdev, void *data)
96+{
97+ pm_runtime_put(&pdev->dev);
98+ return 0;
99+}
100+
88101 static int report_frozen_detected(struct pci_dev *dev, void *data)
89102 {
90103 return report_error_detected(dev, pci_channel_io_frozen, data);
@@ -207,6 +220,8 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, · 116 unmodified lines
207220 else
208221 bridge = pci_upstream_bridge(dev);
209222
223+ pci_walk_bridge(bridge, pci_pm_runtime_get_sync, NULL);
224+
210225 pci_dbg(bridge, "broadcast error_detected message\n");
211226 if (state == pci_channel_io_frozen) {
212227 pci_walk_bridge(bridge, report_frozen_detected, &status);
@@ -251,10 +266,15 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, · 38 unmodified lines
251266 pcie_clear_device_status(dev);
252267 pci_aer_clear_nonfatal_status(dev);
253268 }
269+
270+ pci_walk_bridge(bridge, pci_pm_runtime_put, NULL);
271+
254272 pci_info(bridge, "device recovery successful\n");
255273 return status;
256274
257275 failed:
276+ pci_walk_bridge(bridge, pci_pm_runtime_put, NULL);
277+
258278 pci_uevent_ers(bridge, PCI_ERS_RESULT_DISCONNECT);
259279
260280 /* TODO: Should kernel panic here? */
drivers/pci/pcie/portdrv.h+1−1
@@ -96,7 +96,7 @@ struct pcie_port_service_driver { · 95 unmodified lines
9696 int pcie_port_service_register(struct pcie_port_service_driver *new);
9797 void pcie_port_service_unregister(struct pcie_port_service_driver *new);
9898
99−extern struct bus_type pcie_port_bus_type;
99+extern const struct bus_type pcie_port_bus_type;
100100
101101 struct pci_dev;
102102
drivers/pci/probe.c+5−61
@@ -2209,67 +2209,6 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev) · 2208 unmodified lines
22092209 }
22102210 }
22112211
2212−static void pci_configure_ltr(struct pci_dev *dev)
2213−{
2214−#ifdef CONFIG_PCIEASPM
2215− struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2216− struct pci_dev *bridge;
2217− u32 cap, ctl;
2218−
2219− if (!pci_is_pcie(dev))
2220− return;
2221−
2222− /* Read L1 PM substate capabilities */
2223− dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2224−
2225− pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2226− if (!(cap & PCI_EXP_DEVCAP2_LTR))
2227− return;
2228−
2229− pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2230− if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2231− if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2232− dev->ltr_path = 1;
2233− return;
2234− }
2235−
2236− bridge = pci_upstream_bridge(dev);
2237− if (bridge && bridge->ltr_path)
2238− dev->ltr_path = 1;
2239−
2240− return;
2241− }
2242−
2243− if (!host->native_ltr)
2244− return;
2245−
2246− /*
2247− * Software must not enable LTR in an Endpoint unless the Root
2248− * Complex and all intermediate Switches indicate support for LTR.
2249− * PCIe r4.0, sec 6.18.
2250− */
2251− if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2252− pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2253− PCI_EXP_DEVCTL2_LTR_EN);
2254− dev->ltr_path = 1;
2255− return;
2256− }
2257−
2258− /*
2259− * If we're configuring a hot-added device, LTR was likely
2260− * disabled in the upstream bridge, so re-enable it before enabling
2261− * it in the new device.
2262− */
2263− bridge = pci_upstream_bridge(dev);
2264− if (bridge && bridge->ltr_path) {
2265− pci_bridge_reconfigure_ltr(dev);
2266− pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2267− PCI_EXP_DEVCTL2_LTR_EN);
2268− dev->ltr_path = 1;
2269− }
2270−#endif
2271−}
2272−
22732212 static void pci_configure_eetlp_prefix(struct pci_dev *dev)
22742213 {
22752214 #ifdef CONFIG_PCI_PASID
@@ -2320,6 +2259,7 @@ static void pci_configure_device(struct pci_dev *dev) · 44 unmodified lines
23202259 pci_configure_extended_tags(dev, NULL);
23212260 pci_configure_relaxed_ordering(dev);
23222261 pci_configure_ltr(dev);
2262+ pci_configure_aspm_l1ss(dev);
23232263 pci_configure_eetlp_prefix(dev);
23242264 pci_configure_serr(dev);
23252265
@@ -2357,6 +2297,10 @@ static void pci_release_dev(struct device *dev) · 31 unmodified lines
23572297 kfree(pci_dev);
23582298 }
23592299
2300+static const struct device_type pci_dev_type = {
2301+ .groups = pci_dev_attr_groups,
2302+};
2303+
23602304 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
23612305 {
23622306 struct pci_dev *dev;
drivers/pci/quirks.c+11−0
@@ -3765,6 +3765,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); · 3764 unmodified lines
37653765 */
37663766 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
37673767
3768+/*
3769+ * Apparently the LSI / Agere FW643 can't recover after a Secondary Bus
3770+ * Reset and requires a power-off or suspend/resume and rescan. Prevent
3771+ * use of that reset.
3772+ */
3773+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATT, 0x5900, quirk_no_bus_reset);
3774+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATT, 0x5901, quirk_no_bus_reset);
3775+
37683776 /*
37693777 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
37703778 * automatically disables LTSSM when Secondary Bus Reset is received and
@@ -5527,6 +5535,7 @@ static void quirk_no_ext_tags(struct pci_dev *pdev) · 1756 unmodified lines
55275535
55285536 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
55295537 }
5538+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags);
55305539 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
55315540 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
55325541 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
@@ -6225,6 +6234,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); · 692 unmodified lines
62256234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
62266235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
62276236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
6237+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size);
6238+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size);
62286239 #endif
62296240
62306241 /*
drivers/pci/setup-irq.c+0−64
@@ -1,64 +0,0 @@
1−// SPDX-License-Identifier: GPL-2.0
2−/*
3− * Support routines for initializing a PCI subsystem
4− *
5− * Extruded from code written by
6− * Dave Rusling (david.rusling@reo.mts.dec.com)
7− * David Mosberger (davidm@cs.arizona.edu)
8− * David Miller (davem@redhat.com)
9− */
10−
11−#include <linux/kernel.h>
12−#include <linux/pci.h>
13−#include <linux/errno.h>
14−#include <linux/ioport.h>
15−#include <linux/cache.h>
16−#include "pci.h"
17−
18−void pci_assign_irq(struct pci_dev *dev)
19−{
20− u8 pin;
21− u8 slot = -1;
22− int irq = 0;
23− struct pci_host_bridge *hbrg = pci_find_host_bridge(dev->bus);
24−
25− if (!(hbrg->map_irq)) {
26− pci_dbg(dev, "runtime IRQ mapping not provided by arch\n");
27− return;
28− }
29−
30− /*
31− * If this device is not on the primary bus, we need to figure out
32− * which interrupt pin it will come in on. We know which slot it
33− * will come in on because that slot is where the bridge is. Each
34− * time the interrupt line passes through a PCI-PCI bridge we must
35− * apply the swizzle function.
36− */
37− pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
38− /* Cope with illegal. */
39− if (pin > 4)
40− pin = 1;
41−
42− if (pin) {
43− /* Follow the chain of bridges, swizzling as we go. */
44− if (hbrg->swizzle_irq)
45− slot = (*(hbrg->swizzle_irq))(dev, &pin);
46−
47− /*
48− * If a swizzling function is not used, map_irq() must
49− * ignore slot.
50− */
51− irq = (*(hbrg->map_irq))(dev, slot, pin);
52− if (irq == -1)
53− irq = 0;
54− }
55− dev->irq = irq;
56−
57− pci_dbg(dev, "assign IRQ: got %d\n", dev->irq);
58−
59− /*
60− * Always tell the device, so the driver knows what is the real IRQ
61− * to use; the device does not use it.
62− */
63− pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
64−}
drivers/pci/switch/switchtec.c+3−1
@@ -1672,7 +1672,7 @@ static int switchtec_pci_probe(struct pci_dev *pdev, · 1671 unmodified lines
16721672 rc = switchtec_init_isr(stdev);
16731673 if (rc) {
16741674 dev_err(&stdev->dev, "failed to init isr.\n");
1675− goto err_put;
1675+ goto err_exit_pci;
16761676 }
16771677
16781678 iowrite32(SWITCHTEC_EVENT_CLEAR |
@@ -1693,6 +1693,8 @@ static int switchtec_pci_probe(struct pci_dev *pdev, · 14 unmodified lines
16931693
16941694 err_devadd:
16951695 stdev_kill(stdev);
1696+err_exit_pci:
1697+ switchtec_exit_pci(stdev);
16961698 err_put:
16971699 ida_free(&switchtec_minor_ida, MINOR(stdev->dev.devt));
16981700 put_device(&stdev->dev);
include/linux/aer.h+5−6
@@ -18,11 +18,8 @@ · 17 unmodified lines
1818
1919 struct pci_dev;
2020
21−struct aer_header_log_regs {
22− u32 dw0;
23− u32 dw1;
24− u32 dw2;
25− u32 dw3;
21+struct pcie_tlp_log {
22+ u32 dw[4];
2623 };
2724
2825 struct aer_capability_regs {
@@ -33,13 +30,15 @@ struct aer_capability_regs { · 4 unmodified lines
3330 u32 cor_status;
3431 u32 cor_mask;
3532 u32 cap_control;
36− struct aer_header_log_regs header_log;
33+ struct pcie_tlp_log header_log;
3734 u32 root_command;
3835 u32 root_status;
3936 u16 cor_err_source;
4037 u16 uncor_err_source;
4138 };
4239
40+int pcie_read_tlp_log(struct pci_dev *dev, int where, struct pcie_tlp_log *log);
41+
4342 #if defined(CONFIG_PCIEAER)
4443 int pci_aer_clear_nonfatal_status(struct pci_dev *dev);
4544 int pcie_aer_is_native(struct pci_dev *dev);
include/linux/pci-epc.h+33−6
@@ -145,6 +145,37 @@ struct pci_epc { · 144 unmodified lines
145145 unsigned long function_num_map;
146146 };
147147
148+/**
149+ * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC.
150+ * @BAR_FIXED: The BAR mask is fixed by the hardware.
151+ * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
152+ */
153+enum pci_epc_bar_type {
154+ BAR_PROGRAMMABLE = 0,
155+ BAR_FIXED,
156+ BAR_RESERVED,
157+};
158+
159+/**
160+ * struct pci_epc_bar_desc - hardware description for a BAR
161+ * @type: the type of the BAR
162+ * @fixed_size: the fixed size, only applicable if type is BAR_FIXED_MASK.
163+ * @only_64bit: if true, an EPF driver is not allowed to choose if this BAR
164+ * should be configured as 32-bit or 64-bit, the EPF driver must
165+ * configure this BAR as 64-bit. Additionally, the BAR succeeding
166+ * this BAR must be set to type BAR_RESERVED.
167+ *
168+ * only_64bit should not be set on a BAR of type BAR_RESERVED.
169+ * (If BARx is a 64-bit BAR that an EPF driver is not allowed to
170+ * touch, then both BARx and BARx+1 must be set to type
171+ * BAR_RESERVED.)
172+ */
173+struct pci_epc_bar_desc {
174+ enum pci_epc_bar_type type;
175+ u64 fixed_size;
176+ bool only_64bit;
177+};
178+
148179 /**
149180 * struct pci_epc_features - features supported by a EPC device per function
150181 * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
@@ -152,9 +183,7 @@ struct pci_epc { · 1 unmodified line
152183 * for initialization
153184 * @msi_capable: indicate if the endpoint function has MSI capability
154185 * @msix_capable: indicate if the endpoint function has MSI-X capability
155− * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
156− * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
157− * @bar_fixed_size: Array specifying the size supported by each BAR
186+ * @bar: array specifying the hardware description for each BAR
158187 * @align: alignment size required for BAR buffer allocation
159188 */
160189 struct pci_epc_features {
@@ -162,9 +191,7 @@ struct pci_epc_features { · 1 unmodified line
162191 unsigned int core_init_notifier : 1;
163192 unsigned int msi_capable : 1;
164193 unsigned int msix_capable : 1;
165− u8 reserved_bar;
166− u8 bar_fixed_64bit;
167− u64 bar_fixed_size[PCI_STD_NUM_BARS];
194+ struct pci_epc_bar_desc bar[PCI_STD_NUM_BARS];
168195 size_t align;
169196 };
170197
include/linux/pci-epf.h+3−1
@@ -15,6 +15,7 @@ · 14 unmodified lines
1515 #include <linux/pci.h>
1616
1717 struct pci_epf;
18+struct pci_epc_features;
1819 enum pci_epc_interface_type;
1920
2021 enum pci_barno {
@@ -216,7 +217,8 @@ int __pci_epf_register_driver(struct pci_epf_driver *driver, · 195 unmodified lines
216217 struct module *owner);
217218 void pci_epf_unregister_driver(struct pci_epf_driver *driver);
218219 void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar,
219− size_t align, enum pci_epc_interface_type type);
220+ const struct pci_epc_features *epc_features,
221+ enum pci_epc_interface_type type);
220222 void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar,
221223 enum pci_epc_interface_type type);
222224 int pci_epf_bind(struct pci_epf *epf);
include/linux/pci.h+1−1
@@ -390,9 +390,9 @@ struct pci_dev { · 389 unmodified lines
390390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
391391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
392392
393+ u16 l1ss; /* L1SS Capability pointer */
393394 #ifdef CONFIG_PCIEASPM
394395 struct pcie_link_state *link_state; /* ASPM link state */
395− u16 l1ss; /* L1SS Capability pointer */
396396 unsigned int ltr_path:1; /* Latency Tolerance Reporting
397397 supported from root to here */
398398 #endif
include/ras/ras_event.h+5−5
@@ -300,7 +300,7 @@ TRACE_EVENT(aer_event, · 299 unmodified lines
300300 const u32 status,
301301 const u8 severity,
302302 const u8 tlp_header_valid,
303− struct aer_header_log_regs *tlp),
303+ struct pcie_tlp_log *tlp),
304304
305305 TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp),
306306
@@ -318,10 +318,10 @@ TRACE_EVENT(aer_event, · 11 unmodified lines
318318 __entry->severity = severity;
319319 __entry->tlp_header_valid = tlp_header_valid;
320320 if (tlp_header_valid) {
321− __entry->tlp_header[0] = tlp->dw0;
322− __entry->tlp_header[1] = tlp->dw1;
323− __entry->tlp_header[2] = tlp->dw2;
324− __entry->tlp_header[3] = tlp->dw3;
321+ __entry->tlp_header[0] = tlp->dw[0];
322+ __entry->tlp_header[1] = tlp->dw[1];
323+ __entry->tlp_header[2] = tlp->dw[2];
324+ __entry->tlp_header[3] = tlp->dw[3];
325325 }
326326 ),
327327
lib/Kconfig+0−3
@@ -70,9 +70,6 @@ source "lib/math/Kconfig" · 69 unmodified lines
7070 config NO_GENERIC_PCI_IOPORT_MAP
7171 bool
7272
73−config GENERIC_PCI_IOMAP
74− bool
75−
7673 config GENERIC_IOMAP
7774 bool
7875 select GENERIC_PCI_IOMAP
lib/Makefile+0−1
@@ -152,7 +152,6 @@ CFLAGS_debug_info.o += $(call cc-option, -femit-struct-debug-detailed=any) · 151 unmodified lines
152152 obj-y += math/ crypto/
153153
154154 obj-$(CONFIG_GENERIC_IOMAP) += iomap.o
155−obj-$(CONFIG_GENERIC_PCI_IOMAP) += pci_iomap.o
156155 obj-$(CONFIG_HAS_IOMEM) += iomap_copy.o devres.o
157156 obj-$(CONFIG_CHECK_SIGNATURE) += check_signature.o
158157 obj-$(CONFIG_DEBUG_LOCKING_API_SELFTESTS) += locking-selftest.o
lib/devres.c+1−207
@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0
2+#include <linux/device.h>
23 #include <linux/err.h>
3−#include <linux/pci.h>
44 #include <linux/io.h>
55 #include <linux/gfp.h>
66 #include <linux/export.h>
@@ -311,212 +311,6 @@ void devm_ioport_unmap(struct device *dev, void __iomem *addr) · 304 unmodified lines
311311 EXPORT_SYMBOL(devm_ioport_unmap);
312312 #endif /* CONFIG_HAS_IOPORT_MAP */
313313
314−#ifdef CONFIG_PCI
315−/*
316− * PCI iomap devres
317− */
318−#define PCIM_IOMAP_MAX PCI_STD_NUM_BARS
319−
320−struct pcim_iomap_devres {
321− void __iomem *table[PCIM_IOMAP_MAX];
322−};
323−
324−static void pcim_iomap_release(struct device *gendev, void *res)
325−{
326− struct pci_dev *dev = to_pci_dev(gendev);
327− struct pcim_iomap_devres *this = res;
328− int i;
329−
330− for (i = 0; i < PCIM_IOMAP_MAX; i++)
331− if (this->table[i])
332− pci_iounmap(dev, this->table[i]);
333−}
334−
335−/**
336− * pcim_iomap_table - access iomap allocation table
337− * @pdev: PCI device to access iomap table for
338− *
339− * Access iomap allocation table for @dev. If iomap table doesn't
340− * exist and @pdev is managed, it will be allocated. All iomaps
341− * recorded in the iomap table are automatically unmapped on driver
342− * detach.
343− *
344− * This function might sleep when the table is first allocated but can
345− * be safely called without context and guaranteed to succeed once
346− * allocated.
347− */
348−void __iomem * const *pcim_iomap_table(struct pci_dev *pdev)
349−{
350− struct pcim_iomap_devres *dr, *new_dr;
351−
352− dr = devres_find(&pdev->dev, pcim_iomap_release, NULL, NULL);
353− if (dr)
354− return dr->table;
355−
356− new_dr = devres_alloc_node(pcim_iomap_release, sizeof(*new_dr), GFP_KERNEL,
357− dev_to_node(&pdev->dev));
358− if (!new_dr)
359− return NULL;
360− dr = devres_get(&pdev->dev, new_dr, NULL, NULL);
361− return dr->table;
362−}
363−EXPORT_SYMBOL(pcim_iomap_table);
364−
365−/**
366− * pcim_iomap - Managed pcim_iomap()
367− * @pdev: PCI device to iomap for
368− * @bar: BAR to iomap
369− * @maxlen: Maximum length of iomap
370− *
371− * Managed pci_iomap(). Map is automatically unmapped on driver
372− * detach.
373− */
374−void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen)
375−{
376− void __iomem **tbl;
377−
378− BUG_ON(bar >= PCIM_IOMAP_MAX);
379−
380− tbl = (void __iomem **)pcim_iomap_table(pdev);
381− if (!tbl || tbl[bar]) /* duplicate mappings not allowed */
382− return NULL;
383−
384− tbl[bar] = pci_iomap(pdev, bar, maxlen);
385− return tbl[bar];
386−}
387−EXPORT_SYMBOL(pcim_iomap);
388−
389−/**
390− * pcim_iounmap - Managed pci_iounmap()
391− * @pdev: PCI device to iounmap for
392− * @addr: Address to unmap
393− *
394− * Managed pci_iounmap(). @addr must have been mapped using pcim_iomap().
395− */
396−void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr)
397−{
398− void __iomem **tbl;
399− int i;
400−
401− pci_iounmap(pdev, addr);
402−
403− tbl = (void __iomem **)pcim_iomap_table(pdev);
404− BUG_ON(!tbl);
405−
406− for (i = 0; i < PCIM_IOMAP_MAX; i++)
407− if (tbl[i] == addr) {
408− tbl[i] = NULL;
409− return;
410− }
411− WARN_ON(1);
412−}
413−EXPORT_SYMBOL(pcim_iounmap);
414−
415−/**
416− * pcim_iomap_regions - Request and iomap PCI BARs
417− * @pdev: PCI device to map IO resources for
418− * @mask: Mask of BARs to request and iomap
419− * @name: Name used when requesting regions
420− *
421− * Request and iomap regions specified by @mask.
422− */
423−int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name)
424−{
425− void __iomem * const *iomap;
426− int i, rc;
427−
428− iomap = pcim_iomap_table(pdev);
429− if (!iomap)
430− return -ENOMEM;
431−
432− for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
433− unsigned long len;
434−
435− if (!(mask & (1 << i)))
436− continue;
437−
438− rc = -EINVAL;
439− len = pci_resource_len(pdev, i);
440− if (!len)
441− goto err_inval;
442−
443− rc = pci_request_region(pdev, i, name);
444− if (rc)
445− goto err_inval;
446−
447− rc = -ENOMEM;
448− if (!pcim_iomap(pdev, i, 0))
449− goto err_region;
450− }
451−
452− return 0;
453−
454− err_region:
455− pci_release_region(pdev, i);
456− err_inval:
457− while (--i >= 0) {
458− if (!(mask & (1 << i)))
459− continue;
460− pcim_iounmap(pdev, iomap[i]);
461− pci_release_region(pdev, i);
462− }
463−
464− return rc;
465−}
466−EXPORT_SYMBOL(pcim_iomap_regions);
467−
468−/**
469− * pcim_iomap_regions_request_all - Request all BARs and iomap specified ones
470− * @pdev: PCI device to map IO resources for
471− * @mask: Mask of BARs to iomap
472− * @name: Name used when requesting regions
473− *
474− * Request all PCI BARs and iomap regions specified by @mask.
475− */
476−int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
477− const char *name)
478−{
479− int request_mask = ((1 << 6) - 1) & ~mask;
480− int rc;
481−
482− rc = pci_request_selected_regions(pdev, request_mask, name);
483− if (rc)
484− return rc;
485−
486− rc = pcim_iomap_regions(pdev, mask, name);
487− if (rc)
488− pci_release_selected_regions(pdev, request_mask);
489− return rc;
490−}
491−EXPORT_SYMBOL(pcim_iomap_regions_request_all);
492−
493−/**
494− * pcim_iounmap_regions - Unmap and release PCI BARs
495− * @pdev: PCI device to map IO resources for
496− * @mask: Mask of BARs to unmap and release
497− *
498− * Unmap and release regions specified by @mask.
499− */
500−void pcim_iounmap_regions(struct pci_dev *pdev, int mask)
501−{
502− void __iomem * const *iomap;
503− int i;
504−
505− iomap = pcim_iomap_table(pdev);
506− if (!iomap)
507− return;
508−
509− for (i = 0; i < PCIM_IOMAP_MAX; i++) {
510− if (!(mask & (1 << i)))
511− continue;
512−
513− pcim_iounmap(pdev, iomap[i]);
514− pci_release_region(pdev, i);
515− }
516−}
517−EXPORT_SYMBOL(pcim_iounmap_regions);
518−#endif /* CONFIG_PCI */
519−
520314 static void devm_arch_phys_ac_add_release(struct device *dev, void *res)
521315 {
522316 arch_phys_wc_del(*((int *)res));

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