lael-labs/linux

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml+5−18

     const: dma-mem
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      A ports node with endpoint definitions as defined in
-      Documentation/devicetree/bindings/media/video-interfaces.txt.
     properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
-        description: |
+        description:
           Input endpoints of the controller.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
-        description: |
+        description:
           Output endpoints of the controller.
     required:
-      - "#address-cells"
-      - "#size-cells"
       - port@0
       - port@1
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-frontend.yaml+3−16

     maxItems: 1
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      A ports node with endpoint definitions as defined in
-      Documentation/devicetree/bindings/media/video-interfaces.txt.
     properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Input endpoints of the controller.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Output endpoints of the controller.
     required:
-      - "#address-cells"
-      - "#size-cells"
       - port@1
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml+3−16

       - const: audio-tx
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      A ports node with endpoint definitions as defined in
-      Documentation/devicetree/bindings/media/video-interfaces.txt.
     properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Input endpoints of the controller.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Output endpoints of the controller. Usually an HDMI
           connector.
     required:
-      - "#address-cells"
-      - "#size-cells"
       - port@0
       - port@1
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml+6−19

           - const: lvds
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      A ports node with endpoint definitions as defined in
-      Documentation/devicetree/bindings/media/video-interfaces.txt.
     properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Input endpoints of the controller.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
         description: |
           Output endpoints of the controller.
         patternProperties:
           "^endpoint(@[0-9])$":
-            type: object
+            $ref: /schemas/graph.yaml#/$defs/endpoint-base
+            unevaluatedProperties: false
             properties:
               allwinner,tcon-channel:
                   property is not present, the endpoint number will be
                   used as the channel number.
-            unevaluatedProperties: true
     required:
-      - "#address-cells"
-      - "#size-cells"
       - port@0
       - port@1
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tv-encoder.yaml+2−4

     maxItems: 1
   port:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/port
     description:
-      A port node with endpoint definitions as defined in
+      The first port should be the input endpoint, usually coming from the
-      Documentation/devicetree/bindings/media/video-interfaces.txt. The
-      first port should be the input endpoint, usually coming from the
       associated TCON.
 required:

Documentation/devicetree/bindings/display/allwinner,sun6i-a31-drc.yaml+3−16

     maxItems: 1
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      A ports node with endpoint definitions as defined in
-      Documentation/devicetree/bindings/media/video-interfaces.txt.
     properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Input endpoints of the controller.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Output endpoints of the controller.
     required:
-      - "#address-cells"
-      - "#size-cells"
       - port@0
       - port@1
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml+2−4

     const: dphy
   port:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/port
     description:
-      A port node with endpoint definitions as defined in
+      The port should be the input endpoint, usually coming from the
-      Documentation/devicetree/bindings/media/video-interfaces.txt. That
-      port should be the input endpoint, usually coming from the
       associated TCON.
 required:

Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml+3−16

     maxItems: 1
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      A ports node with endpoint definitions as defined in
-      Documentation/devicetree/bindings/media/video-interfaces.txt.
     properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Input endpoints of the controller.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Output endpoints of the controller.
     required:
-      - "#address-cells"
-      - "#size-cells"
       - port@1
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml+3−16

       The VCC power supply of the controller
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      A ports node with endpoint definitions as defined in
-      Documentation/devicetree/bindings/media/video-interfaces.txt.
     properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Input endpoints of the controller. Usually the associated
           TCON.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Output endpoints of the controller. Usually an HDMI
           connector.
     required:
-      - "#address-cells"
-      - "#size-cells"
       - port@0
       - port@1
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml+7−103

@@ -80,141 +80,45 @@ properties: · 79 unmodified lines
80	maxItems: 1	80	maxItems: 1
81		81
82	ports:	82	ports:
83	type: object	83	$ref: /schemas/graph.yaml#/properties/ports
84	description: \|
85	A ports node with endpoint definitions as defined in
86	Documentation/devicetree/bindings/media/video-interfaces.txt.
87	All ports should have only one endpoint connected to
88	remote endpoint.
89		84
90	properties:	85	properties:
91	"#address-cells":
92	const: 1
93
94	"#size-cells":
95	const: 0
96
97	port@0:	86	port@0:
98	type: object	87	$ref: /schemas/graph.yaml#/properties/port
99	description: \|	88	description: \|
100	Input endpoint for Mixer 0 mux.	89	Input endpoint for Mixer 0 mux.
101		90
102	port@1:	91	port@1:
103	type: object	92	$ref: /schemas/graph.yaml#/properties/port
104	description: \|	93	description: \|
105	Output endpoint for Mixer 0 mux	94	Output endpoint for Mixer 0 mux
106		95
107	properties:
108	"#address-cells":
109	const: 1
110
111	"#size-cells":
112	const: 0
113
114	reg: true
115
116	patternProperties:
117	"^endpoint@[0-9]$":
118	type: object
119
120	properties:
121	reg:
122	description: \|
123	ID of the target TCON
124
125	required:
126	- reg
127
128	required:
129	- "#address-cells"
130	- "#size-cells"
131
132	additionalProperties: false
133
134	port@2:	96	port@2:
135	type: object	97	$ref: /schemas/graph.yaml#/properties/port
136	description: \|	98	description: \|
137	Input endpoint for Mixer 1 mux.	99	Input endpoint for Mixer 1 mux.
138		100
139	port@3:	101	port@3:
140	type: object	102	$ref: /schemas/graph.yaml#/properties/port
141	description: \|	103	description: \|
142	Output endpoint for Mixer 1 mux	104	Output endpoint for Mixer 1 mux
143		105
144	properties:
145	"#address-cells":
146	const: 1
147
148	"#size-cells":
149	const: 0
150
151	reg: true
152
153	patternProperties:
154	"^endpoint@[0-9]$":
155	type: object
156
157	properties:
158	reg:
159	description: \|
160	ID of the target TCON
161
162	required:
163	- reg
164
165	required:
166	- "#address-cells"
167	- "#size-cells"
168
169	additionalProperties: false
170
171	port@4:	106	port@4:
172	type: object	107	$ref: /schemas/graph.yaml#/properties/port
173	description: \|	108	description: \|
174	Input endpoint for HDMI mux.	109	Input endpoint for HDMI mux.
175		110
176	properties:
177	"#address-cells":
178	const: 1
179
180	"#size-cells":
181	const: 0
182
183	reg: true
184
185	patternProperties:
186	"^endpoint@[0-9]$":
187	type: object
188
189	properties:
190	reg:
191	description: \|
192	ID of the target TCON
193
194	required:
195	- reg
196
197	required:
198	- "#address-cells"
199	- "#size-cells"
200
201	additionalProperties: false
202
203	port@5:	111	port@5:
204	type: object	112	$ref: /schemas/graph.yaml#/properties/port
205	description: \|	113	description: \|
206	Output endpoint for HDMI mux	114	Output endpoint for HDMI mux
207		115
208	required:	116	required:
209	- "#address-cells"
210	- "#size-cells"
211	- port@0	117	- port@0
212	- port@1	118	- port@1
213	- port@4	119	- port@4
214	- port@5	120	- port@5
215		121
216	additionalProperties: false
217
218	required:	122	required:
219	- "#clock-cells"	123	- "#clock-cells"
220	- compatible	124	- compatible

Documentation/devicetree/bindings/display/allwinner,sun9i-a80-deu.yaml+3−16

     maxItems: 1
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      A ports node with endpoint definitions as defined in
-      Documentation/devicetree/bindings/media/video-interfaces.txt.
     properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Input endpoints of the controller.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Output endpoints of the controller.
     required:
-      - "#address-cells"
-      - "#size-cells"
       - port@0
       - port@1
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml+2−2

@@ -81,12 +81,12 @@ properties: · 80 unmodified lines
81	description: phandle to an external 5V regulator to power the HDMI logic	81	description: phandle to an external 5V regulator to power the HDMI logic
82		82
83	port@0:	83	port@0:
84	type: object	84	$ref: /schemas/graph.yaml#/properties/port
85	description:	85	description:
86	A port node pointing to the VENC Input port node.	86	A port node pointing to the VENC Input port node.
87		87
88	port@1:	88	port@1:
89	type: object	89	$ref: /schemas/graph.yaml#/properties/port
90	description:	90	description:
91	A port node pointing to the TMDS Output port node.	91	A port node pointing to the TMDS Output port node.
92		92

Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml+2−2

@@ -83,12 +83,12 @@ properties: · 82 unmodified lines
83	description: phandle to the associated power domain	83	description: phandle to the associated power domain
84		84
85	port@0:	85	port@0:
86	type: object	86	$ref: /schemas/graph.yaml#/properties/port
87	description:	87	description:
88	A port node pointing to the CVBS VDAC port node.	88	A port node pointing to the CVBS VDAC port node.
89		89
90	port@1:	90	port@1:
91	type: object	91	$ref: /schemas/graph.yaml#/properties/port
92	description:	92	description:
93	A port node pointing to the HDMI-TX port node.	93	A port node pointing to the HDMI-TX port node.
94		94

Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml+3−4

       - const: pixel
   port:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/port
-    description: >
+    description:
-      Port node with a single endpoint connecting to the panel, as
+      Port node with a single endpoint connecting to the panel.
-      defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
 required:
   - compatible

Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml+3−3

@@ -35,16 +35,16 @@ properties: · 34 unmodified lines
35	maxItems: 1	35	maxItems: 1
36		36
37	ports:	37	ports:
38	type: object	38	$ref: /schemas/graph.yaml#/properties/ports
39		39
40	properties:	40	properties:
41	port@0:	41	port@0:
42	type: object	42	$ref: /schemas/graph.yaml#/properties/port
43	description:	43	description:
44	Video port for MIPI DSI input.	44	Video port for MIPI DSI input.
45		45
46	port@1:	46	port@1:
47	type: object	47	$ref: /schemas/graph.yaml#/properties/port
48	description:	48	description:
49	Video port for panel or connector.	49	Video port for panel or connector.
50		50

Documentation/devicetree/bindings/display/bridge/analogix,anx7814.yaml+3−16

     description: Regulator for 1.0V digital core power.
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description:
-      A node containing input and output port nodes with endpoint
-      definitions as documented in
-      Documentation/devicetree/bindings/media/video-interfaces.txt
-      Documentation/devicetree/bindings/graph.txt
     properties:
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: Video port for HDMI input.
-        properties:
-          reg:
-            const: 0
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           Video port for SlimPort, DisplayPort, eDP or MyDP output.
-        properties:
-          reg:
-            const: 1
     required:
       - port@0
       - port@1

Documentation/devicetree/bindings/display/bridge/anx6345.yaml+5−13

     description: Regulator for 2.5V digital core power.
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
     properties:
-      '#address-cells':
-        const: 1
-      '#size-cells':
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
-        description: |
+        description:
           Video port for LVTTL input
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
-        description: |
+        description:
           Video port for eDP output (panel or connector).
           May be omitted if EDID works reliably.
     required:
       - port@0
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml+6−16

     maxItems: 1
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description:
-      Ports as described in Documentation/devicetree/bindings/graph.txt.
     properties:
-      '#address-cells':
-        const: 1
-      '#size-cells':
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           First input port representing the DP bridge input.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           Second input port representing the DP bridge input.
       port@2:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           Third input port representing the DP bridge input.
       port@3:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           Fourth input port representing the DP bridge input.
       port@4:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           Output port representing the DP bridge output.
     required:
       - port@0
       - port@4
-      - '#address-cells'
-      - '#size-cells'
 allOf:
   - if:

Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml+3−3

@@ -19,16 +19,16 @@ properties: · 18 unmodified lines
19	description: I2C address of the device	19	description: I2C address of the device
20		20
21	ports:	21	ports:
22	type: object	22	$ref: /schemas/graph.yaml#/properties/ports
23		23
24	properties:	24	properties:
25	port@0:	25	port@0:
26	type: object	26	$ref: /schemas/graph.yaml#/properties/port
27	description: \|	27	description: \|
28	Video port for RGB input.	28	Video port for RGB input.
29		29
30	port@1:	30	port@1:
31	type: object	31	$ref: /schemas/graph.yaml#/properties/port
32	description: \|	32	description: \|
33	DVI port, should be connected to a node compatible with the	33	DVI port, should be connected to a node compatible with the
34	dvi-connector binding.	34	dvi-connector binding.

Documentation/devicetree/bindings/display/bridge/intel,keembay-dsi.yaml+3−11

       - const: clk_mipi_cfg
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
     properties:
-      '#address-cells':
-        const: 1
-      '#size-cells':
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: MIPI DSI input port.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: DSI output port.
     required:
       - port@0
       - port@1
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml+1−1

@@ -53,7 +53,7 @@ properties: · 52 unmodified lines
53	description: extcon specifier for the Power Delivery	53	description: extcon specifier for the Power Delivery
54		54
55	port:	55	port:
56	type: object	56	$ref: /schemas/graph.yaml#/properties/port
57	description: A port node pointing to DPI host port node	57	description: A port node pointing to DPI host port node
58		58
59	required:	59	required:

Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml+7−63

@@ -38,82 +38,26 @@ properties: · 37 unmodified lines
38	description: Regulator for 3.3V IO power.	38	description: Regulator for 3.3V IO power.
39		39
40	ports:	40	ports:
41	type: object	41	$ref: /schemas/graph.yaml#/properties/ports
42		42
43	properties:	43	properties:
44	"#address-cells":
45	const: 1
46
47	"#size-cells":
48	const: 0
49
50	port@0:	44	port@0:
51	type: object	45	$ref: /schemas/graph.yaml#/properties/port
52	description: \|	46	description:
53	Primary MIPI port-1 for MIPI input	47	Primary MIPI port-1 for MIPI input
54		48
55	properties:
56	reg:
57	const: 0
58
59	patternProperties:
60	"^endpoint(@[0-9])$":
61	type: object
62	additionalProperties: false
63
64	properties:
65	remote-endpoint:
66	$ref: /schemas/types.yaml#/definitions/phandle
67
68	required:
69	- reg
70
71	port@1:	49	port@1:
72	type: object	50	$ref: /schemas/graph.yaml#/properties/port
73	description: \|	51	description:
74	Additional MIPI port-2 for MIPI input, used in combination	52	Additional MIPI port-2 for MIPI input, used in combination
75	with primary MIPI port-1 to drive higher resolution displays	53	with primary MIPI port-1 to drive higher resolution displays
76		54
77	properties:
78	reg:
79	const: 1
80
81	patternProperties:
82	"^endpoint(@[0-9])$":
83	type: object
84	additionalProperties: false
85
86	properties:
87	remote-endpoint:
88	$ref: /schemas/types.yaml#/definitions/phandle
89
90	required:
91	- reg
92
93	port@2:	55	port@2:
94	type: object	56	$ref: /schemas/graph.yaml#/properties/port
95	description: \|	57	description:
96	HDMI port for HDMI output	58	HDMI port for HDMI output
97		59
98	properties:
99	reg:
100	const: 2
101
102	patternProperties:
103	"^endpoint(@[0-9])$":
104	type: object
105	additionalProperties: false
106
107	properties:
108	remote-endpoint:
109	$ref: /schemas/types.yaml#/definitions/phandle
110
111	required:
112	- reg
113
114	required:	60	required:
115	- "#address-cells"
116	- "#size-cells"
117	- port@0	61	- port@0
118	- port@2	62	- port@2
119		63

Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml+4−14

           - thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      This device has two video ports. Their connections are modeled using the
-      OF graph bindings specified in Documentation/devicetree/bindings/graph.txt
-    properties:
-      '#address-cells':
-        const: 1
-      '#size-cells':
-        const: 0
+    properties:
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           For LVDS encoders, port 0 is the parallel input
           For LVDS decoders, port 0 is the LVDS input
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           For LVDS encoders, port 1 is the LVDS output
           For LVDS decoders, port 1 is the parallel output
       - port@0
       - port@1
-    additionalProperties: false
   powerdown-gpios:
     description:
       The GPIO used to control the power down line of this device.

Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml+7−34

@@ -84,40 +84,23 @@ properties: · 83 unmodified lines
84	- const: pclk	84	- const: pclk
85		85
86	ports:	86	ports:
87	type: object	87	$ref: /schemas/graph.yaml#/properties/ports
88	description:	88
89	A node containing DSI input & output port nodes with endpoint
90	definitions as documented in
91	Documentation/devicetree/bindings/graph.txt.
92	properties:	89	properties:
93	port@0:	90	port@0:
94	type: object	91	$ref: /schemas/graph.yaml#/$defs/port-base
95	description:	92	description:
96	Input port node to receive pixel data from the	93	Input port node to receive pixel data from the
97	display controller. Exactly one endpoint must be	94	display controller. Exactly one endpoint must be
98	specified.	95	specified.
99	properties:	96	properties:
100	'#address-cells':
101	const: 1
102
103	'#size-cells':
104	const: 0
105
106	endpoint@0:	97	endpoint@0:
		98	$ref: /schemas/graph.yaml#/properties/endpoint
107	description: sub-node describing the input from LCDIF	99	description: sub-node describing the input from LCDIF
108	type: object
109		100
110	endpoint@1:	101	endpoint@1:
		102	$ref: /schemas/graph.yaml#/properties/endpoint
111	description: sub-node describing the input from DCSS	103	description: sub-node describing the input from DCSS
112	type: object
113
114	reg:
115	const: 0
116
117	required:
118	- '#address-cells'
119	- '#size-cells'
120	- reg
121		104
122	oneOf:	105	oneOf:
123	- required:	106	- required:
@@ -125,28 +108,18 @@ properties: · 1 unmodified line
125	- required:	108	- required:
126	- endpoint@1	109	- endpoint@1
127		110
128	additionalProperties: false	111	unevaluatedProperties: false
129		112
130	port@1:	113	port@1:
131	type: object	114	$ref: /schemas/graph.yaml#/properties/port
132	description:	115	description:
133	DSI output port node to the panel or the next bridge	116	DSI output port node to the panel or the next bridge
134	in the chain	117	in the chain
135		118
136	'#address-cells':
137	const: 1
138
139	'#size-cells':
140	const: 0
141
142	required:	119	required:
143	- '#address-cells'
144	- '#size-cells'
145	- port@0	120	- port@0
146	- port@1	121	- port@1
147		122
148	additionalProperties: false
149
150	required:	123	required:
151	- '#address-cells'	124	- '#address-cells'
152	- '#size-cells'	125	- '#size-cells'

Documentation/devicetree/bindings/display/bridge/ps8640.yaml+6−18

     description: Regulator for 3.3V digital core power.
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description:
-      A node containing DSI input & output port nodes with endpoint
-      definitions as documented in
-      Documentation/devicetree/bindings/media/video-interfaces.txt
-      Documentation/devicetree/bindings/graph.txt
-    properties:
-      '#address-cells':
-        const: 1
-      '#size-cells':
-        const: 0
+    properties:
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
-        description: |
+        description:
           Video port for DSI input
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
-        description: |
+        description:
           Video port for eDP output (panel or connector).
     required:
       - port@0
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml+3−15

     maxItems: 1
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      This device has two video ports. Their connections are modelled using the
-      OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
-      Each port shall have a single endpoint.
     properties:
-      '#address-cells':
-        const: 1
-      '#size-cells':
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: Parallel RGB input port
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: LVDS output port
     required:
       - port@0
       - port@1
-    additionalProperties: false
   power-domains:
     maxItems: 1

Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml+4−14

           - ti,ths8135
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description: |
-      This device has two video ports. Their connections are modeled using the
-      OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
-    properties:
-      '#address-cells':
-        const: 1
-      '#size-cells':
-        const: 0
+    properties:
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: The bridge input
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: The bridge output
     required:
       - port@0
       - port@1
-    additionalProperties: false
   enable-gpios:
     maxItems: 1
     description: GPIO controlling bridge enable

Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml+4−3

@@ -47,14 +47,15 @@ properties: · 46 unmodified lines
47	const: apb	47	const: apb
48		48
49	ports:	49	ports:
50	type: object	50	$ref: /schemas/graph.yaml#/properties/ports
51		51
52	properties:	52	properties:
53	port@0:	53	port@0:
54	type: object	54	$ref: /schemas/graph.yaml#/properties/port
55	description: Input node to receive pixel data.	55	description: Input node to receive pixel data.
		56
56	port@1:	57	port@1:
57	type: object	58	$ref: /schemas/graph.yaml#/properties/port
58	description: DSI output node to panel.	59	description: DSI output node to panel.
59		60
60	required:	61	required:

Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.yaml+5−16

     const: thine,thc63lvd1024
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
     description: |
-      This device has four video ports. Their connections are modeled using the
-      OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
       The device can operate in single or dual input and output modes.
       When operating in single input mode, all pixels are received on port@0,
       port@3 shall contain endpoints.
     properties:
-      '#address-cells':
-        const: 1
-      '#size-cells':
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: First LVDS input port
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: Second LVDS input port
       port@2:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: First digital CMOS/TTL parallel output
       port@3:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: Second digital CMOS/TTL parallel output
     required:
       - port@0
       - port@2
-    additionalProperties: false
   oe-gpios:
     maxItems: 1
     description: Output enable GPIO signal, pin name "OE", active high.

Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml+6−39

     description: See ../../pwm/pwm.yaml for description of the cell formats.
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    additionalProperties: false
     properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
-        additionalProperties: false
         description:
           Video port for MIPI DSI input
-        properties:
-          reg:
-            const: 0
-          endpoint:
-            type: object
-            additionalProperties: false
-            properties:
-              remote-endpoint: true
-        required:
-          - reg
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/$defs/port-base
-        additionalProperties: false
+        unevaluatedProperties: false
         description:
           Video port for eDP output (panel or connector).
         properties:
-          reg:
-            const: 1
           endpoint:
-            type: object
+            $ref: /schemas/graph.yaml#/$defs/endpoint-base
-            additionalProperties: false
+            unevaluatedProperties: false
             properties:
-              remote-endpoint: true
               data-lanes:
                 oneOf:
                   - minItems: 1
             dependencies:
               lane-polarities: [data-lanes]
-        required:
-          - reg
     required:
-      - "#address-cells"
-      - "#size-cells"
       - port@0
       - port@1

Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml+6−18

     maximum: 7
   ports:
-    description:
+    $ref: /schemas/graph.yaml#/properties/ports
-      A node containing input and output port nodes with endpoint
-      definitions as documented in
-      Documentation/devicetree/bindings/media/video-interfaces.txt
-    type: object
     properties:
       port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
         description: DPI input port.
-        type: object
         properties:
-          reg:
-            const: 0
           endpoint:
-            type: object
+            $ref: /schemas/graph.yaml#/$defs/endpoint-base
+            unevaluatedProperties: false
             properties:
               pclk-sample:
                 default: 24
       port@1:
+        $ref: /schemas/graph.yaml#/properties/port
         description: DVI output port.
-        type: object
-        properties:
-          reg:
-            const: 1
-          endpoint:
-            type: object
     required:
       - port@0

Documentation/devicetree/bindings/display/bridge/toshiba,tc358762.yaml+5−47

@@ -25,62 +25,20 @@ properties: · 24 unmodified lines
25	description: Regulator for 1.2V internal core power.	25	description: Regulator for 1.2V internal core power.
26		26
27	ports:	27	ports:
28	type: object	28	$ref: /schemas/graph.yaml#/properties/ports
29		29
30	properties:	30	properties:
31	"#address-cells":
32	const: 1
33
34	"#size-cells":
35	const: 0
36
37	port@0:	31	port@0:
38	type: object	32	$ref: /schemas/graph.yaml#/properties/port
39	additionalProperties: false	33	description:
40
41	description: \|
42	Video port for MIPI DSI input	34	Video port for MIPI DSI input
43		35
44	properties:
45	reg:
46	const: 0
47
48	patternProperties:
49	endpoint:
50	type: object
51	additionalProperties: false
52
53	properties:
54	remote-endpoint: true
55
56	required:
57	- reg
58
59	port@1:	36	port@1:
60	type: object	37	$ref: /schemas/graph.yaml#/properties/port
61	additionalProperties: false	38	description:
62
63	description: \|
64	Video port for MIPI DPI output (panel or connector).	39	Video port for MIPI DPI output (panel or connector).
65		40
66	properties:
67	reg:
68	const: 1
69
70	patternProperties:
71	endpoint:
72	type: object
73	additionalProperties: false
74
75	properties:
76	remote-endpoint: true
77
78	required:
79	- reg
80
81	required:	41	required:
82	- "#address-cells"
83	- "#size-cells"
84	- port@0	42	- port@0
85	- port@1	43	- port@1
86		44

Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml+6−42

@@ -42,65 +42,30 @@ properties: · 41 unmodified lines
42	const: refclk	42	const: refclk
43		43
44	ports:	44	ports:
45	type: object	45	$ref: /schemas/graph.yaml#/properties/ports
46		46
47	properties:	47	properties:
48	"#address-cells":
49	const: 1
50
51	"#size-cells":
52	const: 0
53
54	port@0:	48	port@0:
55	type: object	49	$ref: /schemas/graph.yaml#/$defs/port-base
56	additionalProperties: false	50	unevaluatedProperties: false
57
58	description: \|	51	description: \|
59	Video port for RGB input	52	Video port for RGB input
60		53
61	properties:	54	properties:
62	reg:
63	const: 0
64
65	patternProperties:
66	endpoint:	55	endpoint:
67	type: object	56	$ref: /schemas/graph.yaml#/$defs/endpoint-base
68	additionalProperties: false	57	unevaluatedProperties: false
69		58
70	properties:	59	properties:
71	data-lines:	60	data-lines:
72	enum: [ 16, 18, 24 ]	61	enum: [ 16, 18, 24 ]
73		62
74	remote-endpoint: true
75
76	required:
77	- reg
78
79	port@1:	63	port@1:
80	type: object	64	$ref: /schemas/graph.yaml#/properties/port
81	additionalProperties: false
82
83	description: \|	65	description: \|
84	Video port for DSI output (panel or connector).	66	Video port for DSI output (panel or connector).
85		67
86	properties:
87	reg:
88	const: 1
89
90	patternProperties:
91	endpoint:
92	type: object
93	additionalProperties: false
94
95	properties:
96	remote-endpoint: true
97
98	required:
99	- reg
100
101	required:	68	required:
102	- "#address-cells"
103	- "#size-cells"
104	- port@0	69	- port@0
105	- port@1	70	- port@1
106		71
@@ -156,4 +121,3 @@ examples: · 49 unmodified lines
156	};	121	};
157	};	122	};
158	};	123	};
159

Documentation/devicetree/bindings/display/bridge/toshiba,tc358775.yaml+5−14

     description: Hardware reset, Low active
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description:
-      A node containing input and output port nodes with endpoint definitions
-      as documented in
-      Documentation/devicetree/bindings/media/video-interfaces.txt
-    properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
+    properties:
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           DSI Input. The remote endpoint phandle should be a
           reference to a valid mipi_dsi_host device node.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Video port for LVDS output (panel or connector).
       port@2:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description: |
           Video port for Dual link LVDS output (panel or connector).

Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml+1−0

@@ -25,6 +25,7 @@ properties: · 24 unmodified lines
25	$ref: /schemas/types.yaml#/definitions/uint32	25	$ref: /schemas/types.yaml#/definitions/uint32
26		26
27	port:	27	port:
		28	$ref: /schemas/graph.yaml#/properties/port
28	description: Connection to controller providing analog TV signals	29	description: Connection to controller providing analog TV signals
29		30
30	required:	31	required:

Documentation/devicetree/bindings/display/connector/dvi-connector.yaml+1−0

@@ -36,6 +36,7 @@ properties: · 35 unmodified lines
36	description: the connector has pins for DVI dual-link	36	description: the connector has pins for DVI dual-link
37		37
38	port:	38	port:
		39	$ref: /schemas/graph.yaml#/properties/port
39	description: Connection to controller providing DVI signals	40	description: Connection to controller providing DVI signals
40		41
41	required:	42	required:

Documentation/devicetree/bindings/display/connector/hdmi-connector.yaml+1−0

@@ -37,6 +37,7 @@ properties: · 36 unmodified lines
37	maxItems: 1	37	maxItems: 1
38		38
39	port:	39	port:
		40	$ref: /schemas/graph.yaml#/properties/port
40	description: Connection to controller providing HDMI signals	41	description: Connection to controller providing HDMI signals
41		42
42	required:	43	required:

Documentation/devicetree/bindings/display/connector/vga-connector.yaml+1−0

@@ -20,6 +20,7 @@ properties: · 19 unmodified lines
20	$ref: /schemas/types.yaml#/definitions/phandle	20	$ref: /schemas/types.yaml#/definitions/phandle
21		21
22	port:	22	port:
		23	$ref: /schemas/graph.yaml#/properties/port
23	description: Connection to controller providing VGA signals	24	description: Connection to controller providing VGA signals
24		25
25	required:	26	required:

Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml+1−1

@@ -74,7 +74,7 @@ properties: · 73 unmodified lines
74	- description: Must be 400 MHz	74	- description: Must be 400 MHz
75		75
76	port:	76	port:
77	type: object	77	$ref: /schemas/graph.yaml#/properties/port
78	description:	78	description:
79	A port node pointing to the input port of a HDMI/DP or MIPI display bridge.	79	A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
80		80

Documentation/devicetree/bindings/display/ingenic,ipu.yaml+2−3

@@ -31,9 +31,8 @@ properties: · 30 unmodified lines
31	clock-names:	31	clock-names:
32	const: ipu	32	const: ipu
33		33
34	patternProperties:	34	port:
35	"^ports?$":	35	$ref: /schemas/graph.yaml#/properties/port
36	description: OF graph bindings (specified in bindings/graph.txt).
37		36
38	required:	37	required:
39	- compatible	38	- compatible

Documentation/devicetree/bindings/display/ingenic,lcd.yaml+5−5

@@ -39,18 +39,18 @@ properties: · 38 unmodified lines
39	minItems: 1	39	minItems: 1
40		40
41	port:	41	port:
42	description: OF graph bindings (specified in bindings/graph.txt).	42	$ref: /schemas/graph.yaml#/properties/port
43		43
44	ports:	44	ports:
45	description: OF graph bindings (specified in bindings/graph.txt).	45	$ref: /schemas/graph.yaml#/properties/ports
46	type: object	46
47	properties:	47	properties:
48	port@0:	48	port@0:
49	type: object	49	$ref: /schemas/graph.yaml#/properties/port
50	description: DPI output, to interface with TFT panels.	50	description: DPI output, to interface with TFT panels.
51		51
52	port@8:	52	port@8:
53	type: object	53	$ref: /schemas/graph.yaml#/properties/port
54	description: Link to the Image Processing Unit (IPU).	54	description: Link to the Image Processing Unit (IPU).
55	(See ingenic,ipu.yaml).	55	(See ingenic,ipu.yaml).
56		56

Documentation/devicetree/bindings/display/intel,keembay-display.yaml+1−1

@@ -36,7 +36,7 @@ properties: · 35 unmodified lines
36	maxItems: 1	36	maxItems: 1
37		37
38	port:	38	port:
39	type: object	39	$ref: /schemas/graph.yaml#/properties/port
40	description: Display output node to DSI.	40	description: Display output node to DSI.
41		41
42	required:	42	required:

Documentation/devicetree/bindings/display/panel/advantech,idk-2121wr.yaml+10−11

   panel-timing: true
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
     properties:
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
         description: The sink for odd pixels.
         properties:
-          reg:
-            const: 0
           dual-lvds-odd-pixels: true
         required:
-          - reg
           - dual-lvds-odd-pixels
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
         description: The sink for even pixels.
         properties:
-          reg:
-            const: 1
           dual-lvds-even-pixels: true
         required:
-          - reg
           - dual-lvds-even-pixels
+    required:
+      - port@0
+      - port@1
 additionalProperties: false
 required:

Documentation/devicetree/bindings/display/panel/panel-common.yaml+1−10

@@ -68,16 +68,7 @@ properties: · 67 unmodified lines
68		68
69	# Connectivity	69	# Connectivity
70	port:	70	port:
71	type: object	71	$ref: /schemas/graph.yaml#/properties/port
72
73	ports:
74	type: object
75	description:
76	Panels receive video data through one or multiple connections. While
77	the nature of those connections is specific to the panel type, the
78	connectivity is expressed in a standard fashion using ports as specified
79	in the device graph bindings defined in
80	Documentation/devicetree/bindings/graph.txt.
81		72
82	ddc-i2c-bus:	73	ddc-i2c-bus:
83	$ref: /schemas/types.yaml#/definitions/phandle	74	$ref: /schemas/types.yaml#/definitions/phandle

Documentation/devicetree/bindings/display/panel/samsung,s6e63m0.yaml+3−1

 allOf:
   - $ref: panel-common.yaml#
+  - $ref: /schemas/leds/backlight/common.yaml#
 properties:
   compatible:
   reg: true
   reset-gpios: true
   port: true
+  default-brightness: true
+  max-brightness: true
   vdd3-supply:
     description: VDD regulator
   - reset-gpios
   - vdd3-supply
   - vci-supply
-  - port
 unevaluatedProperties: false

Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml+3−13

       This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1.
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
     properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           Port node with two endpoints, numbered 0 and 1,
           connected respectively to vop0 and vop1.
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           Port node with one endpoint connected to a hdmi-connector node.
     required:
-      - "#address-cells"
-      - "#size-cells"
       - port@0
       - port@1
-    additionalProperties: false
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml+1−4

       - const: dclk
   port:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/port
-    description:
-      A port node with endpoint definitions as defined in
-      Documentation/devicetree/bindings/media/video-interfaces.txt.
   assigned-clocks:
     maxItems: 2

Documentation/devicetree/bindings/display/st,stm32-dsi.yaml+4−8

@@ -51,20 +51,16 @@ properties: · 50 unmodified lines
51	Phandle of the regulator that provides the supply voltage.	51	Phandle of the regulator that provides the supply voltage.
52		52
53	ports:	53	ports:
54	type: object	54	$ref: /schemas/graph.yaml#/properties/ports
55	description:	55
56	A node containing DSI input & output port nodes with endpoint
57	definitions as documented in
58	Documentation/devicetree/bindings/media/video-interfaces.txt
59	Documentation/devicetree/bindings/graph.txt
60	properties:	56	properties:
61	port@0:	57	port@0:
62	type: object	58	$ref: /schemas/graph.yaml#/properties/port
63	description:	59	description:
64	DSI input port node, connected to the ltdc rgb output port.	60	DSI input port node, connected to the ltdc rgb output port.
65		61
66	port@1:	62	port@1:
67	type: object	63	$ref: /schemas/graph.yaml#/properties/port
68	description:	64	description:
69	DSI output port node, connected to a panel or a bridge input port"	65	DSI output port node, connected to a panel or a bridge input port"
70		66

Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml+3−5

     maxItems: 1
   port:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/port
-    description:
+    description: |
-      "Video port for DPI RGB output.
+      Video port for DPI RGB output.
       ltdc has one video port with up to 2 endpoints:
       - for external dpi rgb panel or bridge, using gpios.
       - for internal dpi input of the MIPI DSI host controller.
       Note: These 2 endpoints cannot be activated simultaneously.
-      Please refer to the bindings defined in
-      Documentation/devicetree/bindings/media/video-interfaces.txt."
 required:
   - compatible

Documentation/devicetree/bindings/display/ste,mcde.yaml+2−3

     description: a phandle to the analog voltage regulator
   port:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/port
     description:
-      A DPI port node with endpoint definitions as defined in
+      A DPI port node
-      Documentation/devicetree/bindings/media/video-interfaces.txt
   "#address-cells":
     const: 1

Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml+4−15

     type: boolean
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description:
-      Ports as described in Documentation/devicetree/bindings/graph.txt
-    properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
+    properties:
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           The DSS OLDI output port node form video port 1
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           The DSS DPI output port node from video port 2
-    required:
-      - "#address-cells"
-      - "#size-cells"
   ti,am65x-oldi-io-ctrl:
     $ref: "/schemas/types.yaml#/definitions/phandle-array"
     maxItems: 1

Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml+6−17

     type: boolean
   ports:
-    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
-    description:
-      Ports as described in Documentation/devicetree/bindings/graph.txt
-    properties:
-      "#address-cells":
-        const: 1
-      "#size-cells":
-        const: 0
+    properties:
       port@0:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           The output port node form video port 1
       port@1:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           The output port node from video port 2
       port@2:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           The output port node from video port 3
       port@3:
-        type: object
+        $ref: /schemas/graph.yaml#/properties/port
         description:
           The output port node from video port 4
-    required:
-      - "#address-cells"
-      - "#size-cells"
   max-memory-bandwidth:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:

Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml+1−2

@@ -54,9 +54,8 @@ properties: · 53 unmodified lines
54	description: phandle to the associated power domain	54	description: phandle to the associated power domain
55		55
56	port:	56	port:
57	type: object	57	$ref: /schemas/graph.yaml#/properties/port
58	description:	58	description:
59	Port as described in Documentation/devicetree/bindings/graph.txt.
60	The DSS DPI output port node	59	The DSS DPI output port node
61		60
62	max-memory-bandwidth:	61	max-memory-bandwidth:

Documentation/gpu/vkms.rst+12−0

@@ -35,6 +35,18 @@ Now, to load the driver, use:: · 34 unmodified lines
35	On running the lsmod command now, the VKMS driver will appear listed.	35	On running the lsmod command now, the VKMS driver will appear listed.
36	You can also observe the driver being loaded in the dmesg logs.	36	You can also observe the driver being loaded in the dmesg logs.
37		37
		38	The VKMS driver has optional features to simulate different kinds of hardware,
		39	which are exposed as module options. You can use the `modinfo` command
		40	to see the module options for vkms::
		41
		42	modinfo vkms
		43
		44	Module options are helpful when testing, and enabling modules
		45	can be done while loading vkms. For example, to load vkms with cursor enabled,
		46	use::
		47
		48	sudo modprobe vkms enable_cursor=1
		49
38	To disable the driver, use ::	50	To disable the driver, use ::
39		51
40	sudo modprobe -r vkms	52	sudo modprobe -r vkms

MAINTAINERS+1−0

@@ -5784,6 +5784,7 @@ F: drivers/gpu/drm/vboxvideo/ · 5783 unmodified lines
5784	DRM DRIVER FOR VMWARE VIRTUAL GPU	5784	DRM DRIVER FOR VMWARE VIRTUAL GPU
5785	M: "VMware Graphics" <linux-graphics-maintainer@vmware.com>	5785	M: "VMware Graphics" <linux-graphics-maintainer@vmware.com>
5786	M: Roland Scheidegger <sroland@vmware.com>	5786	M: Roland Scheidegger <sroland@vmware.com>
		5787	M: Zack Rusin <zackr@vmware.com>
5787	L: dri-devel@lists.freedesktop.org	5788	L: dri-devel@lists.freedesktop.org
5788	S: Supported	5789	S: Supported
5789	T: git git://people.freedesktop.org/~sroland/linux	5790	T: git git://people.freedesktop.org/~sroland/linux

drivers/dma-buf/Kconfig+8−0

@@ -50,6 +50,14 @@ config DMABUF_MOVE_NOTIFY · 49 unmodified lines
50	This is marked experimental because we don't yet have a consistent	50	This is marked experimental because we don't yet have a consistent
51	execution context and memory management between drivers.	51	execution context and memory management between drivers.
52		52
		53	config DMABUF_DEBUG
		54	bool "DMA-BUF debug checks"
		55	default y if DMA_API_DEBUG
		56	help
		57	This option enables additional checks for DMA-BUF importers and
		58	exporters. Specifically it validates that importers do not peek at the
		59	underlying struct page when they import a buffer.
		60
53	config DMABUF_SELFTESTS	61	config DMABUF_SELFTESTS
54	tristate "Selftests for the dma-buf interfaces"	62	tristate "Selftests for the dma-buf interfaces"
55	default n	63	default n

drivers/dma-buf/dma-buf.c+42−4

 }
 EXPORT_SYMBOL_GPL(dma_buf_put);
+static void mangle_sg_table(struct sg_table *sg_table)
+{
+#ifdef CONFIG_DMABUF_DEBUG
+	int i;
+	struct scatterlist *sg;
+	/* To catch abuse of the underlying struct page by importers mix
+	 * up the bits, but take care to preserve the low SG_ bits to
+	 * not corrupt the sgt. The mixing is undone in __unmap_dma_buf
+	 * before passing the sgt back to the exporter. */
+	for_each_sgtable_sg(sg_table, sg, i)
+		sg->page_link ^= ~0xffUL;
+#endif
+}
+static struct sg_table * __map_dma_buf(struct dma_buf_attachment *attach,
+				       enum dma_data_direction direction)
+{
+	struct sg_table *sg_table;
+	sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction);
+	if (!IS_ERR_OR_NULL(sg_table))
+		mangle_sg_table(sg_table);
+	return sg_table;
+}
 /**
  * dma_buf_dynamic_attach - Add the device to dma_buf's attachments list
  * @dmabuf:		[in]	buffer to attach device to.
 				goto err_unlock;
 		}
-		sgt = dmabuf->ops->map_dma_buf(attach, DMA_BIDIRECTIONAL);
+		sgt = __map_dma_buf(attach, DMA_BIDIRECTIONAL);
 		if (!sgt)
 			sgt = ERR_PTR(-ENOMEM);
 		if (IS_ERR(sgt)) {
 }
 EXPORT_SYMBOL_GPL(dma_buf_attach);
+static void __unmap_dma_buf(struct dma_buf_attachment *attach,
+			    struct sg_table *sg_table,
+			    enum dma_data_direction direction)
+{
+	/* uses XOR, hence this unmangles */
+	mangle_sg_table(sg_table);
+	attach->dmabuf->ops->unmap_dma_buf(attach, sg_table, direction);
+}
 /**
  * dma_buf_detach - Remove the given attachment from dmabuf's attachments list
  * @dmabuf:	[in]	buffer to detach from.
 		if (dma_buf_is_dynamic(attach->dmabuf))
 			dma_resv_lock(attach->dmabuf->resv, NULL);
-		dmabuf->ops->unmap_dma_buf(attach, attach->sgt, attach->dir);
+		__unmap_dma_buf(attach, attach->sgt, attach->dir);
 		if (dma_buf_is_dynamic(attach->dmabuf)) {
 			dma_buf_unpin(attach);
 		}
 	}
-	sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction);
+	sg_table = __map_dma_buf(attach, direction);
 	if (!sg_table)
 		sg_table = ERR_PTR(-ENOMEM);
 	if (dma_buf_is_dynamic(attach->dmabuf))
 		dma_resv_assert_held(attach->dmabuf->resv);
-	attach->dmabuf->ops->unmap_dma_buf(attach, sg_table, direction);
+	__unmap_dma_buf(attach, sg_table, direction);
 	if (dma_buf_is_dynamic(attach->dmabuf) &&
 	    !IS_ENABLED(CONFIG_DMABUF_MOVE_NOTIFY))

drivers/gpu/drm/Kconfig+0−5

 	help
 	  Choose this if you need the GEM shmem helper functions
-config DRM_VM
-	bool
-	depends on DRM && MMU
 config DRM_SCHED
 	tristate
 	depends on DRM
 menuconfig DRM_LEGACY
 	bool "Enable legacy drivers (DANGEROUS)"
 	depends on DRM && MMU
-	select DRM_VM
 	help
 	  Enable legacy DRI1 drivers. Those drivers expose unsafe and dangerous
 	  APIs to user-space, which can be used to circumvent access

drivers/gpu/drm/Makefile+3−3

 drm-y       :=	drm_auth.o drm_cache.o \
 		drm_file.o drm_gem.o drm_ioctl.o drm_irq.o \
-		drm_memory.o drm_drv.o \
+		drm_drv.o \
 		drm_sysfs.o drm_hashtab.o drm_mm.o \
 		drm_crtc.o drm_fourcc.o drm_modes.o drm_edid.o \
 		drm_encoder_slave.o \
 		drm_client_modeset.o drm_atomic_uapi.o drm_hdcp.o \
 		drm_managed.o drm_vblank_work.o
-drm-$(CONFIG_DRM_LEGACY) += drm_legacy_misc.o drm_bufs.o drm_context.o drm_dma.o drm_scatter.o drm_lock.o
+drm-$(CONFIG_DRM_LEGACY) += drm_bufs.o drm_context.o drm_dma.o drm_legacy_misc.o drm_lock.o \
+		drm_memory.o drm_scatter.o drm_vm.o
 drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
-drm-$(CONFIG_DRM_VM) += drm_vm.o
 drm-$(CONFIG_COMPAT) += drm_ioc32.o
 drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o
 drm-$(CONFIG_DRM_GEM_SHMEM_HELPER) += drm_gem_shmem_helper.o

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+16−14

  */
 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 {
-	u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
+	int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
-	u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 	struct pci_bus *root;
 	struct resource *res;
 	unsigned i;
 	if (!res)
 		return 0;
+	/* Limit the BAR size to what is available */
+	rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
+			rbar_size);
 	/* Disable memory decoding while we change the BAR addresses and size */
 	pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 	pci_write_config_word(adev->pdev, PCI_COMMAND,
 		/* don't suspend or resume card normally */
 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
-		pci_set_power_state(dev->pdev, PCI_D0);
+		pci_set_power_state(pdev, PCI_D0);
-		amdgpu_device_load_pci_state(dev->pdev);
+		amdgpu_device_load_pci_state(pdev);
-		r = pci_enable_device(dev->pdev);
+		r = pci_enable_device(pdev);
 		if (r)
 			DRM_WARN("pci_enable_device failed (%d)\n", r);
 		amdgpu_device_resume(dev, true);
 		drm_kms_helper_poll_disable(dev);
 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 		amdgpu_device_suspend(dev, true);
-		amdgpu_device_cache_pci_state(dev->pdev);
+		amdgpu_device_cache_pci_state(pdev);
 		/* Shut down the device */
-		pci_disable_device(dev->pdev);
+		pci_disable_device(pdev);
-		pci_set_power_state(dev->pdev, PCI_D3cold);
+		pci_set_power_state(pdev, PCI_D3cold);
 		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 	}
 }
 	adev->enable_virtual_display = false;
 	if (amdgpu_virtual_display) {
-		struct drm_device *ddev = adev_to_drm(adev);
+		const char *pci_address_name = pci_name(adev->pdev);
-		const char *pci_address_name = pci_name(ddev->pdev);
 		char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
 		pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
 		}
 	}
-	pci_enable_pcie_error_reporting(adev->ddev.pdev);
+	pci_enable_pcie_error_reporting(adev->pdev);
 	/* Post card if necessary */
 	if (amdgpu_device_need_post(adev)) {
 	case pci_channel_io_normal:
 		return PCI_ERS_RESULT_CAN_RECOVER;
 	/* Fatal error, prepare for slot reset */
 	case pci_channel_io_frozen:
 		/*
 		 * Cancel and wait for all TDRs in progress if failing to
 		 * set  adev->in_gpu_reset in amdgpu_device_lock_adev
 		 *
 		goto out;
 	}
 	adev->in_pci_err_recovery = true;
 	r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset);
 	adev->in_pci_err_recovery = false;
 	if (r)

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+0−1

@@ -1204,7 +1204,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, · 1203 unmodified lines
1204	if (ret)	1204	if (ret)
1205	return ret;	1205	return ret;
1206		1206
1207	ddev->pdev = pdev;
1208	pci_set_drvdata(pdev, ddev);	1207	pci_set_drvdata(pdev, ddev);
1209		1208
1210	ret = amdgpu_driver_load_kms(adev, ent->driver_data);	1209	ret = amdgpu_driver_load_kms(adev, ent->driver_data);

drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c+1−1

@@ -271,7 +271,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, · 270 unmodified lines
271	DRM_INFO("fb depth is %d\n", fb->format->depth);	271	DRM_INFO("fb depth is %d\n", fb->format->depth);
272	DRM_INFO(" pitch is %d\n", fb->pitches[0]);	272	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
273		273
274	vga_switcheroo_client_fb_set(adev_to_drm(adev)->pdev, info);	274	vga_switcheroo_client_fb_set(adev->pdev, info);
275	return 0;	275	return 0;
276		276
277	out:	277	out:

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+5−5

@@ -619,7 +619,7 @@ int amdgpu_gem_va_ioctl(struct drm_device dev, void data, · 618 unmodified lines
619	int r = 0;	619	int r = 0;
620		620
621	if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {	621	if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
622	dev_dbg(&dev->pdev->dev,	622	dev_dbg(dev->dev,
623	"va_address 0x%LX is in reserved area 0x%LX\n",	623	"va_address 0x%LX is in reserved area 0x%LX\n",
624	args->va_address, AMDGPU_VA_RESERVED_SIZE);	624	args->va_address, AMDGPU_VA_RESERVED_SIZE);
625	return -EINVAL;	625	return -EINVAL;
@@ -627,7 +627,7 @@ int amdgpu_gem_va_ioctl(struct drm_device dev, void data, · 1 unmodified line
627		627
628	if (args->va_address >= AMDGPU_GMC_HOLE_START &&	628	if (args->va_address >= AMDGPU_GMC_HOLE_START &&
629	args->va_address < AMDGPU_GMC_HOLE_END) {	629	args->va_address < AMDGPU_GMC_HOLE_END) {
630	dev_dbg(&dev->pdev->dev,	630	dev_dbg(dev->dev,
631	"va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",	631	"va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
632	args->va_address, AMDGPU_GMC_HOLE_START,	632	args->va_address, AMDGPU_GMC_HOLE_START,
633	AMDGPU_GMC_HOLE_END);	633	AMDGPU_GMC_HOLE_END);
@@ -639,14 +639,14 @@ int amdgpu_gem_va_ioctl(struct drm_device dev, void data, · 5 unmodified lines
639	vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;	639	vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
640	vm_size -= AMDGPU_VA_RESERVED_SIZE;	640	vm_size -= AMDGPU_VA_RESERVED_SIZE;
641	if (args->va_address + args->map_size > vm_size) {	641	if (args->va_address + args->map_size > vm_size) {
642	dev_dbg(&dev->pdev->dev,	642	dev_dbg(dev->dev,
643	"va_address 0x%llx is in top reserved area 0x%llx\n",	643	"va_address 0x%llx is in top reserved area 0x%llx\n",
644	args->va_address + args->map_size, vm_size);	644	args->va_address + args->map_size, vm_size);
645	return -EINVAL;	645	return -EINVAL;
646	}	646	}
647		647
648	if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {	648	if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
649	dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",	649	dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
650	args->flags);	650	args->flags);
651	return -EINVAL;	651	return -EINVAL;
652	}	652	}
@@ -658,7 +658,7 @@ int amdgpu_gem_va_ioctl(struct drm_device dev, void data, · 5 unmodified lines
658	case AMDGPU_VA_OP_REPLACE:	658	case AMDGPU_VA_OP_REPLACE:
659	break;	659	break;
660	default:	660	default:
661	dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",	661	dev_dbg(dev->dev, "unsupported operation %d\n",
662	args->operation);	662	args->operation);
663	return -EINVAL;	663	return -EINVAL;
664	}	664	}

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c+1−1

@@ -176,7 +176,7 @@ struct amdgpu_i2c_chan amdgpu_i2c_create(struct drm_device dev, · 175 unmodified lines
176	i2c->rec = *rec;	176	i2c->rec = *rec;
177	i2c->adapter.owner = THIS_MODULE;	177	i2c->adapter.owner = THIS_MODULE;
178	i2c->adapter.class = I2C_CLASS_DDC;	178	i2c->adapter.class = I2C_CLASS_DDC;
179	i2c->adapter.dev.parent = &dev->pdev->dev;	179	i2c->adapter.dev.parent = dev->dev;
180	i2c->dev = dev;	180	i2c->dev = dev;
181	i2c_set_adapdata(&i2c->adapter, i2c);	181	i2c_set_adapdata(&i2c->adapter, i2c);
182	mutex_init(&i2c->mutex);	182	mutex_init(&i2c->mutex);

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+5−5

@@ -142,7 +142,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) · 141 unmodified lines
142	(amdgpu_is_atpx_hybrid() \|\|	142	(amdgpu_is_atpx_hybrid() \|\|
143	amdgpu_has_atpx_dgpu_power_cntl()) &&	143	amdgpu_has_atpx_dgpu_power_cntl()) &&
144	((flags & AMD_IS_APU) == 0) &&	144	((flags & AMD_IS_APU) == 0) &&
145	!pci_is_thunderbolt_attached(dev->pdev))	145	!pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
146	flags \|= AMD_IS_PX;	146	flags \|= AMD_IS_PX;
147		147
148	parent = pci_upstream_bridge(adev->pdev);	148	parent = pci_upstream_bridge(adev->pdev);
@@ -156,7 +156,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) · 7 unmodified lines
156	*/	156	*/
157	r = amdgpu_device_init(adev, flags);	157	r = amdgpu_device_init(adev, flags);
158	if (r) {	158	if (r) {
159	dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");	159	dev_err(dev->dev, "Fatal error during GPU init\n");
160	goto out;	160	goto out;
161	}	161	}
162		162
@@ -199,7 +199,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) · 36 unmodified lines
199		199
200	acpi_status = amdgpu_acpi_init(adev);	200	acpi_status = amdgpu_acpi_init(adev);
201	if (acpi_status)	201	if (acpi_status)
202	dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");	202	dev_dbg(dev->dev, "Error during ACPI methods call\n");
203		203
204	if (adev->runpm) {	204	if (adev->runpm) {
205	/* only need to skip on ATPX */	205	/* only need to skip on ATPX */
@@ -735,10 +735,10 @@ int amdgpu_info_ioctl(struct drm_device dev, void data, struct drm_file *filp) · 529 unmodified lines
735	if (!dev_info)	735	if (!dev_info)
736	return -ENOMEM;	736	return -ENOMEM;
737		737
738	dev_info->device_id = dev->pdev->device;	738	dev_info->device_id = adev->pdev->device;
739	dev_info->chip_rev = adev->rev_id;	739	dev_info->chip_rev = adev->rev_id;
740	dev_info->external_rev = adev->external_rev_id;	740	dev_info->external_rev = adev->external_rev_id;
741	dev_info->pci_rev = dev->pdev->revision;	741	dev_info->pci_rev = adev->pdev->revision;
742	dev_info->family = adev->family;	742	dev_info->family = adev->family;
743	dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;	743	dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
744	dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;	744	dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;

drivers/gpu/drm/ast/ast_drv.c+2−2

@@ -147,7 +147,7 @@ static int ast_drm_freeze(struct drm_device *dev) · 146 unmodified lines
147	error = drm_mode_config_helper_suspend(dev);	147	error = drm_mode_config_helper_suspend(dev);
148	if (error)	148	if (error)
149	return error;	149	return error;
150	pci_save_state(dev->pdev);	150	pci_save_state(to_pci_dev(dev->dev));
151	return 0;	151	return 0;
152	}	152	}
153		153
@@ -162,7 +162,7 @@ static int ast_drm_resume(struct drm_device *dev) · 8 unmodified lines
162	{	162	{
163	int ret;	163	int ret;
164		164
165	if (pci_enable_device(dev->pdev))	165	if (pci_enable_device(to_pci_dev(dev->dev)))
166	return -EIO;	166	return -EIO;
167		167
168	ret = ast_drm_thaw(dev);	168	ret = ast_drm_thaw(dev);

drivers/gpu/drm/ast/ast_main.c+13−12

 static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
 {
-	struct device_node *np = dev->pdev->dev.of_node;
+	struct device_node *np = dev->dev->of_node;
 	struct ast_private *ast = to_ast_private(dev);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	uint32_t data, jregd0, jregd1;
 	/* Defaults */
 	}
 	/* Not all families have a P2A bridge */
-	if (dev->pdev->device != PCI_CHIP_AST2000)
+	if (pdev->device != PCI_CHIP_AST2000)
 		return;
 	/*
 static int ast_detect_chip(struct drm_device *dev, bool *need_post)
 {
 	struct ast_private *ast = to_ast_private(dev);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	uint32_t jreg, scu_rev;
 	/*
 	ast_detect_config_mode(dev, &scu_rev);
 	/* Identify chipset */
-	if (dev->pdev->revision >= 0x50) {
+	if (pdev->revision >= 0x50) {
 		ast->chip = AST2600;
 		drm_info(dev, "AST 2600 detected\n");
-	} else if (dev->pdev->revision >= 0x40) {
+	} else if (pdev->revision >= 0x40) {
 		ast->chip = AST2500;
 		drm_info(dev, "AST 2500 detected\n");
-	} else if (dev->pdev->revision >= 0x30) {
+	} else if (pdev->revision >= 0x30) {
 		ast->chip = AST2400;
 		drm_info(dev, "AST 2400 detected\n");
-	} else if (dev->pdev->revision >= 0x20) {
+	} else if (pdev->revision >= 0x20) {
 		ast->chip = AST2300;
 		drm_info(dev, "AST 2300 detected\n");
-	} else if (dev->pdev->revision >= 0x10) {
+	} else if (pdev->revision >= 0x10) {
 		switch (scu_rev & 0x0300) {
 		case 0x0200:
 			ast->chip = AST1100;
 static int ast_get_dram_info(struct drm_device *dev)
 {
-	struct device_node *np = dev->pdev->dev.of_node;
+	struct device_node *np = dev->dev->of_node;
 	struct ast_private *ast = to_ast_private(dev);
 	uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
 	uint32_t denum, num, div, ref_pll, dsel;
 		return ast;
 	dev = &ast->base;
-	dev->pdev = pdev;
 	pci_set_drvdata(pdev, dev);
-	ast->regs = pci_iomap(dev->pdev, 1, 0);
+	ast->regs = pci_iomap(pdev, 1, 0);
 	if (!ast->regs)
 		return ERR_PTR(-EIO);
 	 * assume the chip has MMIO enabled by default (rev 0x20
 	 * and higher).
 	 */
-	if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
+	if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
 		drm_info(dev, "platform has no IO space, trying MMIO\n");
 		ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
 	}
 	/* "map" IO regs if the above hasn't done so already */
 	if (!ast->ioregs) {
-		ast->ioregs = pci_iomap(dev->pdev, 2, 0);
+		ast->ioregs = pci_iomap(pdev, 2, 0);
 		if (!ast->ioregs)
 			return ERR_PTR(-EIO);
 	}

drivers/gpu/drm/ast/ast_mm.c+9−8

 static void ast_mm_release(struct drm_device *dev, void *ptr)
 {
 	struct ast_private *ast = to_ast_private(dev);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	arch_phys_wc_del(ast->fb_mtrr);
-	arch_io_free_memtype_wc(pci_resource_start(dev->pdev, 0),
+	arch_io_free_memtype_wc(pci_resource_start(pdev, 0),
-				pci_resource_len(dev->pdev, 0));
+				pci_resource_len(pdev, 0));
 }
 int ast_mm_init(struct ast_private *ast)
 {
 	struct drm_device *dev = &ast->base;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	u32 vram_size;
 	int ret;
 	vram_size = ast_get_vram_size(ast);
-	ret = drmm_vram_helper_init(dev, pci_resource_start(dev->pdev, 0),
+	ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0), vram_size);
-				    vram_size);
 	if (ret) {
 		drm_err(dev, "Error initializing VRAM MM; %d\n", ret);
 		return ret;
 	}
-	arch_io_reserve_memtype_wc(pci_resource_start(dev->pdev, 0),
+	arch_io_reserve_memtype_wc(pci_resource_start(pdev, 0),
-				   pci_resource_len(dev->pdev, 0));
+				   pci_resource_len(pdev, 0));
-	ast->fb_mtrr = arch_phys_wc_add(pci_resource_start(dev->pdev, 0),
+	ast->fb_mtrr = arch_phys_wc_add(pci_resource_start(pdev, 0),
-					pci_resource_len(dev->pdev, 0));
+					pci_resource_len(pdev, 0));
 	return drmm_add_action_or_reset(dev, ast_mm_release, NULL);
 }

drivers/gpu/drm/ast/ast_mode.c+3−2

 int ast_mode_config_init(struct ast_private *ast)
 {
 	struct drm_device *dev = &ast->base;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	int ret;
 	ret = ast_cursor_init(ast);
 	dev->mode_config.min_height = 0;
 	dev->mode_config.preferred_depth = 24;
 	dev->mode_config.prefer_shadow = 1;
-	dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
+	dev->mode_config.fb_base = pci_resource_start(pdev, 0);
 	if (ast->chip == AST2100 ||
 	    ast->chip == AST2200 ||
 	i2c->adapter.owner = THIS_MODULE;
 	i2c->adapter.class = I2C_CLASS_DDC;
-	i2c->adapter.dev.parent = &dev->pdev->dev;
+	i2c->adapter.dev.parent = dev->dev;
 	i2c->dev = dev;
 	i2c_set_adapdata(&i2c->adapter, i2c);
 	snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),

drivers/gpu/drm/ast/ast_post.c+5−3

 ast_set_def_ext_reg(struct drm_device *dev)
 {
 	struct ast_private *ast = to_ast_private(dev);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	u8 i, index, reg;
 	const u8 *ext_reg_info;
 	if (ast->chip == AST2300 || ast->chip == AST2400 ||
 	    ast->chip == AST2500) {
-		if (dev->pdev->revision >= 0x20)
+		if (pdev->revision >= 0x20)
 			ext_reg_info = extreginfo_ast2300;
 		else
 			ext_reg_info = extreginfo_ast2300a0;
 void ast_post_gpu(struct drm_device *dev)
 {
 	struct ast_private *ast = to_ast_private(dev);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	u32 reg;
-	pci_read_config_dword(dev->pdev, 0x04, &reg);
+	pci_read_config_dword(pdev, 0x04, &reg);
 	reg |= 0x3;
-	pci_write_config_dword(dev->pdev, 0x04, reg);
+	pci_write_config_dword(pdev, 0x04, reg);
 	ast_enable_vga(dev);
 	ast_open_key(ast);

drivers/gpu/drm/bochs/bochs_drv.c+0−1

@@ -121,7 +121,6 @@ static int bochs_pci_probe(struct pci_dev *pdev, · 120 unmodified lines
121	if (ret)	121	if (ret)
122	goto err_free_dev;	122	goto err_free_dev;
123		123
124	dev->pdev = pdev;
125	pci_set_drvdata(pdev, dev);	124	pci_set_drvdata(pdev, dev);
126		125
127	ret = bochs_load(dev);	126	ret = bochs_load(dev);

drivers/gpu/drm/bochs/bochs_hw.c+2−2

@@ -110,7 +110,7 @@ int bochs_hw_load_edid(struct bochs_device *bochs) · 109 unmodified lines
110	int bochs_hw_init(struct drm_device *dev)	110	int bochs_hw_init(struct drm_device *dev)
111	{	111	{
112	struct bochs_device *bochs = dev->dev_private;	112	struct bochs_device *bochs = dev->dev_private;
113	struct pci_dev *pdev = dev->pdev;	113	struct pci_dev *pdev = to_pci_dev(dev->dev);
114	unsigned long addr, size, mem, ioaddr, iosize;	114	unsigned long addr, size, mem, ioaddr, iosize;
115	u16 id;	115	u16 id;
116		116
@@ -201,7 +201,7 @@ void bochs_hw_fini(struct drm_device *dev) · 84 unmodified lines
201	release_region(VBE_DISPI_IOPORT_INDEX, 2);	201	release_region(VBE_DISPI_IOPORT_INDEX, 2);
202	if (bochs->fb_map)	202	if (bochs->fb_map)
203	iounmap(bochs->fb_map);	203	iounmap(bochs->fb_map);
204	pci_release_regions(dev->pdev);	204	pci_release_regions(to_pci_dev(dev->dev));
205	kfree(bochs->edid);	205	kfree(bochs->edid);
206	}	206	}
207		207

drivers/gpu/drm/drm_agpsupport.c+23−44

 #include "drm_legacy.h"
-/**
+/*
  * Get AGP information.
  *
- * \param inode device inode.
- * \param file_priv DRM file private.
- * \param cmd command.
- * \param arg pointer to a (output) drm_agp_info structure.
  * \return zero on success or a negative number on failure.
  *
  * Verifies the AGP device has been initialized and acquired and fills in the
 	return 0;
 }
-/**
+/*
  * Acquire the AGP device.
  *
  * \param dev DRM device that is to acquire AGP.
  */
 int drm_agp_acquire(struct drm_device *dev)
 {
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	if (!dev->agp)
 		return -ENODEV;
 	if (dev->agp->acquired)
 		return -EBUSY;
-	dev->agp->bridge = agp_backend_acquire(dev->pdev);
+	dev->agp->bridge = agp_backend_acquire(pdev);
 	if (!dev->agp->bridge)
 		return -ENODEV;
 	dev->agp->acquired = 1;
 }
 EXPORT_SYMBOL(drm_agp_acquire);
-/**
+/*
  * Acquire the AGP device (ioctl).
  *
- * \param inode device inode.
- * \param file_priv DRM file private.
- * \param cmd command.
- * \param arg user argument.
  * \return zero on success or a negative number on failure.
  *
  * Verifies the AGP device hasn't been acquired before and calls
 	return drm_agp_acquire((struct drm_device *) file_priv->minor->dev);
 }
-/**
+/*
  * Release the AGP device.
  *
  * \param dev DRM device that is to release AGP.
 	return drm_agp_release(dev);
 }
-/**
+/*
  * Enable the AGP bus.
  *
  * \param dev DRM device that has previously acquired AGP.
 	return drm_agp_enable(dev, *mode);
 }
-/**
+/*
  * Allocate AGP memory.
  *
- * \param inode device inode.
- * \param file_priv file private pointer.
- * \param cmd command.
- * \param arg pointer to a drm_agp_buffer structure.
  * \return zero on success or a negative number on failure.
  *
  * Verifies the AGP device is present and has been acquired, allocates the
 	return drm_agp_alloc(dev, request);
 }
-/**
+/*
  * Search for the AGP memory entry associated with a handle.
  *
  * \param dev DRM device structure.
 	return NULL;
 }
-/**
+/*
  * Unbind AGP memory from the GATT (ioctl).
  *
- * \param inode device inode.
- * \param file_priv DRM file private.
- * \param cmd command.
- * \param arg pointer to a drm_agp_binding structure.
  * \return zero on success or a negative number on failure.
  *
  * Verifies the AGP device is present and acquired, looks-up the AGP memory
 	entry = drm_agp_lookup_entry(dev, request->handle);
 	if (!entry || !entry->bound)
 		return -EINVAL;
-	ret = drm_unbind_agp(entry->memory);
+	ret = agp_unbind_memory(entry->memory);
 	if (ret == 0)
 		entry->bound = 0;
 	return ret;
 	return drm_agp_unbind(dev, request);
 }
-/**
+/*
  * Bind AGP memory into the GATT (ioctl)
  *
- * \param inode device inode.
- * \param file_priv DRM file private.
- * \param cmd command.
- * \param arg pointer to a drm_agp_binding structure.
  * \return zero on success or a negative number on failure.
  *
  * Verifies the AGP device is present and has been acquired and that no memory
 	if (!entry || entry->bound)
 		return -EINVAL;
 	page = DIV_ROUND_UP(request->offset, PAGE_SIZE);
-	retcode = drm_bind_agp(entry->memory, page);
+	retcode = agp_bind_memory(entry->memory, page);
 	if (retcode)
 		return retcode;
 	entry->bound = dev->agp->base + (page << PAGE_SHIFT);
 	return drm_agp_bind(dev, request);
 }
-/**
+/*
  * Free AGP memory (ioctl).
  *
- * \param inode device inode.
- * \param file_priv DRM file private.
- * \param cmd command.
- * \param arg pointer to a drm_agp_buffer structure.
  * \return zero on success or a negative number on failure.
  *
  * Verifies the AGP device is present and has been acquired and looks up the
 	if (!entry)
 		return -EINVAL;
 	if (entry->bound)
-		drm_unbind_agp(entry->memory);
+		agp_unbind_memory(entry->memory);
 	list_del(&entry->head);
-	drm_free_agp(entry->memory, entry->pages);
+	agp_free_memory(entry->memory);
 	kfree(entry);
 	return 0;
 }
 	return drm_agp_free(dev, request);
 }
-/**
+/*
  * Initialize the AGP resources.
  *
  * \return pointer to a drm_agp_head structure.
  */
 struct drm_agp_head *drm_agp_init(struct drm_device *dev)
 {
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct drm_agp_head *head = NULL;
 	head = kzalloc(sizeof(*head), GFP_KERNEL);
 	if (!head)
 		return NULL;
-	head->bridge = agp_find_bridge(dev->pdev);
+	head->bridge = agp_find_bridge(pdev);
 	if (!head->bridge) {
-		head->bridge = agp_backend_acquire(dev->pdev);
+		head->bridge = agp_backend_acquire(pdev);
 		if (!head->bridge) {
 			kfree(head);
 			return NULL;
 	list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
 		if (entry->bound)
-			drm_unbind_agp(entry->memory);
+			agp_unbind_memory(entry->memory);
-		drm_free_agp(entry->memory, entry->pages);
+		agp_free_memory(entry->memory);
 		kfree(entry);
 	}
 	INIT_LIST_HEAD(&dev->agp->memory);

drivers/gpu/drm/drm_bufs.c+2−2

@@ -326,7 +326,7 @@ static int drm_addmap_core(struct drm_device *dev, resource_size_t offset, · 325 unmodified lines
326	* As we're limiting the address to 2^32-1 (or less),	326	* As we're limiting the address to 2^32-1 (or less),
327	* casting it down to 32 bits is no problem, but we	327	* casting it down to 32 bits is no problem, but we
328	* need to point to a 64bit variable first. */	328	* need to point to a 64bit variable first. */
329	map->handle = dma_alloc_coherent(&dev->pdev->dev,	329	map->handle = dma_alloc_coherent(dev->dev,
330	map->size,	330	map->size,
331	&map->offset,	331	&map->offset,
332	GFP_KERNEL);	332	GFP_KERNEL);
@@ -556,7 +556,7 @@ int drm_legacy_rmmap_locked(struct drm_device dev, struct drm_local_map map) · 223 unmodified lines
556	case _DRM_SCATTER_GATHER:	556	case _DRM_SCATTER_GATHER:
557	break;	557	break;
558	case _DRM_CONSISTENT:	558	case _DRM_CONSISTENT:
559	dma_free_coherent(&dev->pdev->dev,	559	dma_free_coherent(dev->dev,
560	map->size,	560	map->size,
561	map->handle,	561	map->handle,
562	map->offset);	562	map->offset);

drivers/gpu/drm/drm_cache.c+33−0

@@ -30,6 +30,8 @@ · 29 unmodified lines
30		30
31	#include <linux/export.h>	31	#include <linux/export.h>
32	#include <linux/highmem.h>	32	#include <linux/highmem.h>
		33	#include <linux/mem_encrypt.h>
		34	#include <xen/xen.h>
33		35
34	#include <drm/drm_cache.h>	36	#include <drm/drm_cache.h>
35		37
@@ -176,3 +178,34 @@ drm_clflush_virt_range(void *addr, unsigned long length) · 140 unmodified lines
176	#endif	178	#endif
177	}	179	}
178	EXPORT_SYMBOL(drm_clflush_virt_range);	180	EXPORT_SYMBOL(drm_clflush_virt_range);
		181
		182	bool drm_need_swiotlb(int dma_bits)
		183	{
		184	struct resource *tmp;
		185	resource_size_t max_iomem = 0;
		186
		187	/*
		188	* Xen paravirtual hosts require swiotlb regardless of requested dma
		189	* transfer size.
		190	*
		191	* NOTE: Really, what it requires is use of the dma_alloc_coherent
		192	* allocator used in ttm_dma_populate() instead of
		193	* ttm_populate_and_map_pages(), which bounce buffers so much in
		194	* Xen it leads to swiotlb buffer exhaustion.
		195	*/
		196	if (xen_pv_domain())
		197	return true;
		198
		199	/*
		200	* Enforce dma_alloc_coherent when memory encryption is active as well
		201	* for the same reasons as for Xen paravirtual hosts.
		202	*/
		203	if (mem_encrypt_active())
		204	return true;
		205
		206	for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling)
		207	max_iomem = max(max_iomem, tmp->end);
		208
		209	return max_iomem > ((u64)1 << dma_bits);
		210	}
		211	EXPORT_SYMBOL(drm_need_swiotlb);

drivers/gpu/drm/drm_dp_helper.c+2−1

  *                                               RGB->YCbCr conversion capability
  * @dpcd: DisplayPort configuration data
  * @port_cap: downstream facing port capabilities
- * @colorspc: Colorspace for which conversion cap is sought
+ * @color_spc: Colorspace for which conversion cap is sought
  *
  * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
  * colorspace.
 /**
  * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
  * @aux: DisplayPort AUX channel
+ * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
  *
  * Returns 0 if success, else returns negative error code.
  */

drivers/gpu/drm/drm_dp_mst_topology.c+1−1

@@ -2751,7 +2751,7 @@ static void drm_dp_mst_link_probe_work(struct work_struct *work) · 2750 unmodified lines
2751	drm_dp_mst_topology_put_mstb(mstb);	2751	drm_dp_mst_topology_put_mstb(mstb);
2752		2752
2753	mutex_unlock(&mgr->probe_lock);	2753	mutex_unlock(&mgr->probe_lock);
2754	if (ret)	2754	if (ret > 0)
2755	drm_kms_helper_hotplug_event(dev);	2755	drm_kms_helper_hotplug_event(dev);
2756	}	2756	}
2757		2757

drivers/gpu/drm/drm_drv.c+3−0

@@ -469,6 +469,9 @@ void drm_dev_unplug(struct drm_device *dev) · 468 unmodified lines
469	synchronize_srcu(&drm_unplug_srcu);	469	synchronize_srcu(&drm_unplug_srcu);
470		470
471	drm_dev_unregister(dev);	471	drm_dev_unregister(dev);
		472
		473	/* Clear all CPU mappings pointing to this device */
		474	unmap_mapping_range(dev->anon_inode->i_mapping, 0, 0, 1);
472	}	475	}
473	EXPORT_SYMBOL(drm_dev_unplug);	476	EXPORT_SYMBOL(drm_dev_unplug);
474		477

drivers/gpu/drm/drm_edid.c+6−1

 #include <linux/i2c.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/pci.h>
 #include <linux/slab.h>
 #include <linux/vga_switcheroo.h>
 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
 				     struct i2c_adapter *adapter)
 {
-	struct pci_dev *pdev = connector->dev->pdev;
+	struct drm_device *dev = connector->dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct edid *edid;
+	if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
+		return NULL;
 	vga_switcheroo_lock_ddc(pdev);
 	edid = drm_get_edid(connector, adapter);
 	vga_switcheroo_unlock_ddc(pdev);

drivers/gpu/drm/drm_file.c+2−3

  * before calling this.
  *
  * If NULL is passed, this is a no-op.
- *
- * RETURNS:
- * 0 on success, or error code on failure.
  */
 void drm_file_free(struct drm_file *file)
 {
 	list_add(&priv->lhead, &dev->filelist);
 	mutex_unlock(&dev->filelist_mutex);
+#ifdef CONFIG_DRM_LEGACY
 #ifdef __alpha__
 	/*
 	 * Default the hose
 				dev->hose = b->sysdata;
 		}
 	}
+#endif
 #endif
 	return 0;

drivers/gpu/drm/drm_gem.c+10−9

 	drm_gem_object_get(obj);
 	vma->vm_private_data = obj;
+	vma->vm_ops = obj->funcs->vm_ops;
 	if (obj->funcs->mmap) {
 		ret = obj->funcs->mmap(obj, vma);
-		if (ret) {
+		if (ret)
-			drm_gem_object_put(obj);
+			goto err_drm_gem_object_put;
-			return ret;
-		}
 		WARN_ON(!(vma->vm_flags & VM_DONTEXPAND));
 	} else {
-		if (obj->funcs->vm_ops)
+		if (!vma->vm_ops) {
-			vma->vm_ops = obj->funcs->vm_ops;
+			ret = -EINVAL;
-		else {
+			goto err_drm_gem_object_put;
-			drm_gem_object_put(obj);
-			return -EINVAL;
 		}
 		vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
 	}
 	return 0;
+err_drm_gem_object_put:
+	drm_gem_object_put(obj);
+	return ret;
 }
 EXPORT_SYMBOL(drm_gem_mmap_obj);

drivers/gpu/drm/drm_irq.c+7−5

 		dev->driver->irq_preinstall(dev);
 	/* PCI devices require shared interrupts. */
-	if (dev->pdev)
+	if (dev_is_pci(dev->dev))
 		sh_flags = IRQF_SHARED;
 	ret = request_irq(irq, dev->driver->irq_handler,
 	if (ret < 0) {
 		dev->irq_enabled = false;
 		if (drm_core_check_feature(dev, DRIVER_LEGACY))
-			vga_client_register(dev->pdev, NULL, NULL, NULL);
+			vga_client_register(to_pci_dev(dev->dev), NULL, NULL, NULL);
 		free_irq(irq, dev);
 	} else {
 		dev->irq = irq;
 	DRM_DEBUG("irq=%d\n", dev->irq);
 	if (drm_core_check_feature(dev, DRIVER_LEGACY))
-		vga_client_register(dev->pdev, NULL, NULL, NULL);
+		vga_client_register(to_pci_dev(dev->dev), NULL, NULL, NULL);
 	if (dev->driver->irq_uninstall)
 		dev->driver->irq_uninstall(dev);
 {
 	struct drm_control *ctl = data;
 	int ret = 0, irq;
+	struct pci_dev *pdev;
 	/* if we haven't irq we fallback for compatibility reasons -
 	 * this used to be a separate function in drm_dma.h
 	if (!drm_core_check_feature(dev, DRIVER_LEGACY))
 		return 0;
 	/* UMS was only ever supported on pci devices. */
-	if (WARN_ON(!dev->pdev))
+	if (WARN_ON(!dev_is_pci(dev->dev)))
 		return -EINVAL;
 	switch (ctl->func) {
 	case DRM_INST_HANDLER:
-		irq = dev->pdev->irq;
+		pdev = to_pci_dev(dev->dev);
+		irq = pdev->irq;
 		if (dev->if_version < DRM_IF_VERSION(1, 2) &&
 		    ctl->irq != irq)

drivers/gpu/drm/drm_legacy.h+1−1

@@ -127,7 +127,7 @@ static inline void drm_legacy_master_rmmaps(struct drm_device *dev, · 126 unmodified lines
127	static inline void drm_legacy_rmmaps(struct drm_device *dev) {}	127	static inline void drm_legacy_rmmaps(struct drm_device *dev) {}
128	#endif	128	#endif
129		129
130	#if IS_ENABLED(CONFIG_DRM_VM) && IS_ENABLED(CONFIG_DRM_LEGACY)	130	#if IS_ENABLED(CONFIG_DRM_LEGACY)
131	void drm_legacy_vma_flush(struct drm_device *d);	131	void drm_legacy_vma_flush(struct drm_device *d);
132	#else	132	#else
133	static inline void drm_legacy_vma_flush(struct drm_device *d)	133	static inline void drm_legacy_vma_flush(struct drm_device *d)

drivers/gpu/drm/drm_memory.c+0−51

@@ -37,7 +37,6 @@ · 36 unmodified lines
37	#include <linux/highmem.h>	37	#include <linux/highmem.h>
38	#include <linux/pci.h>	38	#include <linux/pci.h>
39	#include <linux/vmalloc.h>	39	#include <linux/vmalloc.h>
40	#include <xen/xen.h>
41		40
42	#include <drm/drm_agpsupport.h>	41	#include <drm/drm_agpsupport.h>
43	#include <drm/drm_cache.h>	42	#include <drm/drm_cache.h>
@@ -100,24 +99,6 @@ static void *agp_remap(unsigned long offset, unsigned long size, · 56 unmodified lines
100	return addr;	99	return addr;
101	}	100	}
102		101
103	/** Wrapper around agp_free_memory() */
104	void drm_free_agp(struct agp_memory *handle, int pages)
105	{
106	agp_free_memory(handle);
107	}
108
109	/** Wrapper around agp_bind_memory() */
110	int drm_bind_agp(struct agp_memory *handle, unsigned int start)
111	{
112	return agp_bind_memory(handle, start);
113	}
114
115	/** Wrapper around agp_unbind_memory() */
116	int drm_unbind_agp(struct agp_memory *handle)
117	{
118	return agp_unbind_memory(handle);
119	}
120
121	#else /* CONFIG_AGP */	102	#else /* CONFIG_AGP */
122	static inline void *agp_remap(unsigned long offset, unsigned long size,	103	static inline void *agp_remap(unsigned long offset, unsigned long size,
123	struct drm_device *dev)	104	struct drm_device *dev)
@@ -156,35 +137,3 @@ void drm_legacy_ioremapfree(struct drm_local_map map, struct drm_device dev) · 32 unmodified lines
156	iounmap(map->handle);	137	iounmap(map->handle);
157	}	138	}
158	EXPORT_SYMBOL(drm_legacy_ioremapfree);	139	EXPORT_SYMBOL(drm_legacy_ioremapfree);
159
160	bool drm_need_swiotlb(int dma_bits)
161	{
162	struct resource *tmp;
163	resource_size_t max_iomem = 0;
164
165	/*
166	* Xen paravirtual hosts require swiotlb regardless of requested dma
167	* transfer size.
168	*
169	* NOTE: Really, what it requires is use of the dma_alloc_coherent
170	* allocator used in ttm_dma_populate() instead of
171	* ttm_populate_and_map_pages(), which bounce buffers so much in
172	* Xen it leads to swiotlb buffer exhaustion.
173	*/
174	if (xen_pv_domain())
175	return true;
176
177	/*
178	* Enforce dma_alloc_coherent when memory encryption is active as well
179	* for the same reasons as for Xen paravirtual hosts.
180	*/
181	if (mem_encrypt_active())
182	return true;
183
184	for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
185	max_iomem = max(max_iomem, tmp->end);
186	}
187
188	return max_iomem > ((u64)1 << dma_bits);
189	}
190	EXPORT_SYMBOL(drm_need_swiotlb);

drivers/gpu/drm/drm_modes.c+2−2

@@ -762,7 +762,7 @@ int drm_mode_vrefresh(const struct drm_display_mode *mode) · 761 unmodified lines
762	if (mode->htotal == 0 \|\| mode->vtotal == 0)	762	if (mode->htotal == 0 \|\| mode->vtotal == 0)
763	return 0;	763	return 0;
764		764
765	num = mode->clock * 1000;	765	num = mode->clock;
766	den = mode->htotal * mode->vtotal;	766	den = mode->htotal * mode->vtotal;
767		767
768	if (mode->flags & DRM_MODE_FLAG_INTERLACE)	768	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -772,7 +772,7 @@ int drm_mode_vrefresh(const struct drm_display_mode *mode) · 3 unmodified lines
772	if (mode->vscan > 1)	772	if (mode->vscan > 1)
773	den *= mode->vscan;	773	den *= mode->vscan;
774		774
775	return DIV_ROUND_CLOSEST(num, den);	775	return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(num, 1000), den);
776	}	776	}
777	EXPORT_SYMBOL(drm_mode_vrefresh);	777	EXPORT_SYMBOL(drm_mode_vrefresh);
778		778

drivers/gpu/drm/drm_pci.c+15−11

 		return NULL;
 	dmah->size = size;
-	dmah->vaddr = dma_alloc_coherent(&dev->pdev->dev, size,
+	dmah->vaddr = dma_alloc_coherent(dev->dev, size,
 					 &dmah->busaddr,
 					 GFP_KERNEL);
  */
 void drm_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
 {
-	dma_free_coherent(&dev->pdev->dev, dmah->size, dmah->vaddr,
+	dma_free_coherent(dev->dev, dmah->size, dmah->vaddr,
 			  dmah->busaddr);
 	kfree(dmah);
 }
 		return 0;
 #endif /* __alpha__ */
-	return pci_domain_nr(dev->pdev->bus);
+	return pci_domain_nr(to_pci_dev(dev->dev)->bus);
 }
 int drm_pci_set_busid(struct drm_device *dev, struct drm_master *master)
 {
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	master->unique = kasprintf(GFP_KERNEL, "pci:%04x:%02x:%02x.%d",
 					drm_get_pci_domain(dev),
-					dev->pdev->bus->number,
+					pdev->bus->number,
-					PCI_SLOT(dev->pdev->devfn),
+					PCI_SLOT(pdev->devfn),
-					PCI_FUNC(dev->pdev->devfn));
+					PCI_FUNC(pdev->devfn));
 	if (!master->unique)
 		return -ENOMEM;
 static int drm_pci_irq_by_busid(struct drm_device *dev, struct drm_irq_busid *p)
 {
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	if ((p->busnum >> 8) != drm_get_pci_domain(dev) ||
-	    (p->busnum & 0xff) != dev->pdev->bus->number ||
+	    (p->busnum & 0xff) != pdev->bus->number ||
-	    p->devnum != PCI_SLOT(dev->pdev->devfn) || p->funcnum != PCI_FUNC(dev->pdev->devfn))
+	    p->devnum != PCI_SLOT(pdev->devfn) || p->funcnum != PCI_FUNC(pdev->devfn))
 		return -EINVAL;
-	p->irq = dev->pdev->irq;
+	p->irq = pdev->irq;
 	DRM_DEBUG("%d:%d:%d => IRQ %d\n", p->busnum, p->devnum, p->funcnum,
 		  p->irq);
 		return -EOPNOTSUPP;
 	/* UMS was only ever support on PCI devices. */
-	if (WARN_ON(!dev->pdev))
+	if (WARN_ON(!dev_is_pci(dev->dev)))
 		return -EINVAL;
 	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
 static void drm_pci_agp_init(struct drm_device *dev)
 {
 	if (drm_core_check_feature(dev, DRIVER_USE_AGP)) {
-		if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP))
+		if (pci_find_capability(to_pci_dev(dev->dev), PCI_CAP_ID_AGP))
 			dev->agp = drm_agp_init(dev);
 		if (dev->agp) {
 			dev->agp->agp_mtrr = arch_phys_wc_add(

drivers/gpu/drm/drm_prime.c+2−0

@@ -717,6 +717,8 @@ int drm_gem_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma) · 716 unmodified lines
717	vma->vm_pgoff += drm_vma_node_start(&obj->vma_node);	717	vma->vm_pgoff += drm_vma_node_start(&obj->vma_node);
718		718
719	if (obj->funcs && obj->funcs->mmap) {	719	if (obj->funcs && obj->funcs->mmap) {
		720	vma->vm_ops = obj->funcs->vm_ops;
		721
720	ret = obj->funcs->mmap(obj, vma);	722	ret = obj->funcs->mmap(obj, vma);
721	if (ret)	723	if (ret)
722	return ret;	724	return ret;

drivers/gpu/drm/drm_vblank.c+1−1

@@ -74,7 +74,7 @@ · 73 unmodified lines
74	* \|↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓\| updates the	74	* \|↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓\| updates the
75	* \| \| frame as it	75	* \| \| frame as it
76	* \| \| travels down	76	* \| \| travels down
77	* \| \| ("sacn out")	77	* \| \| ("scan out")
78	* \| Old frame \|	78	* \| Old frame \|
79	* \| \|	79	* \| \|
80	* \| \|	80	* \| \|

drivers/gpu/drm/drm_vm.c+1−1

@@ -278,7 +278,7 @@ static void drm_vm_shm_close(struct vm_area_struct *vma) · 277 unmodified lines
278	case _DRM_SCATTER_GATHER:	278	case _DRM_SCATTER_GATHER:
279	break;	279	break;
280	case _DRM_CONSISTENT:	280	case _DRM_CONSISTENT:
281	dma_free_coherent(&dev->pdev->dev,	281	dma_free_coherent(dev->dev,
282	map->size,	282	map->size,
283	map->handle,	283	map->handle,
284	map->offset);	284	map->offset);

drivers/gpu/drm/gma500/cdv_device.c+19−11

 static int cdv_get_brightness(struct backlight_device *bd)
 {
 	struct drm_device *dev = bl_get_data(bd);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
 	if (cdv_backlight_combination_mode(dev)) {
 		u8 lbpc;
 		val &= ~1;
-		pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
+		pci_read_config_byte(pdev, 0xF4, &lbpc);
 		val *= lbpc;
 	}
 	return (val * 100)/cdv_get_max_backlight(dev);
 static int cdv_set_brightness(struct backlight_device *bd)
 {
 	struct drm_device *dev = bl_get_data(bd);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	int level = bd->props.brightness;
 	u32 blc_pwm_ctl;
 		lbpc = level * 0xfe / max + 1;
 		level /= lbpc;
-		pci_write_config_byte(dev->pdev, 0xF4, lbpc);
+		pci_write_config_byte(pdev, 0xF4, lbpc);
 	}
 	blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
 static void cdv_init_pm(struct drm_device *dev)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	u32 pwr_cnt;
-	int domain = pci_domain_nr(dev->pdev->bus);
+	int domain = pci_domain_nr(pdev->bus);
 	int i;
 	dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
 static void cdv_errata(struct drm_device *dev)
 {
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	/* Disable bonus launch.
 	 *	CPU and GPU competes for memory and display misses updates and
 	 *	flickers. Worst with dual core, dual displays.
 	 *	Bonus Launch to work around the issue, by degrading
 	 *	performance.
 	 */
-	 CDV_MSG_WRITE32(pci_domain_nr(dev->pdev->bus), 3, 0x30, 0x08027108);
+	 CDV_MSG_WRITE32(pci_domain_nr(pdev->bus), 3, 0x30, 0x08027108);
 }
 /**
 static int cdv_save_display_registers(struct drm_device *dev)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct psb_save_area *regs = &dev_priv->regs;
 	struct drm_connector *connector;
 	dev_dbg(dev->dev, "Saving GPU registers.\n");
-	pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);
+	pci_read_config_byte(pdev, 0xF4, &regs->cdv.saveLBB);
 	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
 	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
 static int cdv_restore_display_registers(struct drm_device *dev)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct psb_save_area *regs = &dev_priv->regs;
 	struct drm_connector *connector;
 	u32 temp;
-	pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);
+	pci_write_config_byte(pdev, 0xF4, regs->cdv.saveLBB);
 	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
 	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
 static void cdv_hotplug_work_func(struct work_struct *work)
 {
         struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,
 							hotplug_work);
         struct drm_device *dev = dev_priv->dev;
         /* Just fire off a uevent and let userspace tell us what to do */
         drm_helper_hpd_irq_event(dev);
 }
 /* The core driver has received a hotplug IRQ. We are in IRQ context
    so extract the needed information and kick off queued processing */
 static int cdv_hotplug_event(struct drm_device *dev)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
 	}  else {
 		REG_WRITE(PORT_HOTPLUG_EN, 0);
 		REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
 	}
 }
 static const char *force_audio_names[] = {
 static int cdv_chip_setup(struct drm_device *dev)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
-	if (pci_enable_msi(dev->pdev))
+	if (pci_enable_msi(pdev))
 		dev_warn(dev->dev, "Enabling MSI failed!\n");
 	dev_priv->regmap = cdv_regmap;
 	gma_get_core_freq(dev);

drivers/gpu/drm/gma500/cdv_intel_crt.c+2−3

 }
-/**
+/*
  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  *
  * \return true if CRT is connected.
 	gma_encoder->ddc_bus = psb_intel_i2c_create(dev,
 							  i2c_reg, "CRTDDC_A");
 	if (!gma_encoder->ddc_bus) {
-		dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
+		dev_printk(KERN_ERR, dev->dev, "DDC bus registration failed.\n");
-			   "failed.\n");
 		goto failed_ddc;
 	}

drivers/gpu/drm/gma500/cdv_intel_display.c+1−1

@@ -551,7 +551,7 @@ void cdv_update_wm(struct drm_device dev, struct drm_crtc crtc) · 550 unmodified lines
551	}	551	}
552	}	552	}
553		553
554	/**	554	/*
555	* Return the pipe currently connected to the panel fitter,	555	* Return the pipe currently connected to the panel fitter,
556	* or -1 if the panel fitter is not present or not in use	556	* or -1 if the panel fitter is not present or not in use
557	*/	557	*/

drivers/gpu/drm/gma500/cdv_intel_dp.c+2−2

@@ -306,7 +306,7 @@ static uint32_t dp_vswing_premph_table[] = { · 305 unmodified lines
306	};	306	};
307	/**	307	/**
308	* is_edp - is the given port attached to an eDP panel (either CPU or PCH)	308	* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
309	* @intel_dp: DP struct	309	* @encoder: GMA encoder struct
310	*	310	*
311	* If a CPU or PCH DP output is attached to an eDP panel, this function	311	* If a CPU or PCH DP output is attached to an eDP panel, this function
312	* will return true, and false otherwise.	312	* will return true, and false otherwise.
@@ -1687,7 +1687,7 @@ static enum drm_connector_status cdv_dp_detect(struct gma_encoder *encoder) · 1374 unmodified lines
1687	return status;	1687	return status;
1688	}	1688	}
1689		1689
1690	/**	1690	/*
1691	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.	1691	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1692	*	1692	*
1693	* \return true if DP port is connected.	1693	* \return true if DP port is connected.

drivers/gpu/drm/gma500/cdv_intel_lvds.c+6−5

 	return retval;
 }
-/**
+/*
  * Sets the backlight level.
  *
  * level backlight level, from 0 to cdv_intel_lvds_get_max_backlight().
 	}
 }
-/**
+/*
  * Sets the power state for the panel.
  */
 static void cdv_intel_lvds_set_power(struct drm_device *dev,
 	REG_WRITE(PFIT_CONTROL, pfit_control);
 }
-/**
+/*
  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
  */
 static int cdv_intel_lvds_get_modes(struct drm_connector *connector)
 /**
  * cdv_intel_lvds_init - setup LVDS connectors on this device
  * @dev: drm device
+ * @mode_dev: PSB mode device
  *
  * Create the connector, register the LVDS DDC bus, and try to figure out what
  * modes we can display on the LVDS panel (if present).
 							 "LVDSBLC_B");
 	if (!gma_encoder->i2c_bus) {
 		dev_printk(KERN_ERR,
-			&dev->pdev->dev, "I2C bus registration failed.\n");
+			dev->dev, "I2C bus registration failed.\n");
 		goto failed_blc_i2c;
 	}
 	gma_encoder->i2c_bus->slave_addr = 0x2C;
 							 GPIOC,
 							 "LVDSDDC_C");
 	if (!gma_encoder->ddc_bus) {
-		dev_printk(KERN_ERR, &dev->pdev->dev,
+		dev_printk(KERN_ERR, dev->dev,
 			   "DDC bus registration " "failed.\n");
 		goto failed_ddc;
 	}

drivers/gpu/drm/gma500/framebuffer.c+8−7

  *	@dev: our DRM device
  *	@fb: framebuffer to set up
  *	@mode_cmd: mode description
- *	@gt: backing object
+ *	@obj: backing object
  *
  *	Configure and fill in the boilerplate for our frame buffer. Return
  *	0 on success or an error code if we fail.
  *	psb_framebuffer_create	-	create a framebuffer backed by gt
  *	@dev: our DRM device
  *	@mode_cmd: the description of the requested mode
- *	@gt: the backing object
+ *	@obj: the backing object
  *
  *	Create a framebuffer object backed by the gt, and fill in the
  *	boilerplate required
 /**
  *	psbfb_create		-	create a framebuffer
- *	@fbdev: the framebuffer device
+ *	@fb_helper: the framebuffer helper
  *	@sizes: specification of the layout
  *
  *	Create a framebuffer to the specifications provided
 {
 	struct drm_device *dev = fb_helper->dev;
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct fb_info *info;
 	struct drm_framebuffer *fb;
 	struct drm_mode_fb_cmd2 mode_cmd;
 	drm_fb_helper_fill_info(info, fb_helper, sizes);
-	info->fix.mmio_start = pci_resource_start(dev->pdev, 0);
+	info->fix.mmio_start = pci_resource_start(pdev, 0);
-	info->fix.mmio_len = pci_resource_len(dev->pdev, 0);
+	info->fix.mmio_len = pci_resource_len(pdev, 0);
 	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
 	struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	int i;
 	drm_mode_config_init(dev);
 	/* set memory base */
 	/* Oaktrail and Poulsbo should use BAR 2*/
-	pci_read_config_dword(dev->pdev, PSB_BSM, (u32 *)
+	pci_read_config_dword(pdev, PSB_BSM, (u32 *)&(dev->mode_config.fb_base));
-					&(dev->mode_config.fb_base));
 	/* num pipes is 2 for PSB but 1 for Mrst */
 	for (i = 0; i < dev_priv->num_pipe; i++)

drivers/gpu/drm/gma500/gem.c+4−2

 #include <drm/drm.h>
 #include <drm/drm_vma_manager.h>
+#include "gem.h"
 #include "psb_drv.h"
 static vm_fault_t psb_gem_fault(struct vm_fault *vmf);
  *	@dev: our device
  *	@size: the size requested
  *	@handlep: returned handle (opaque number)
+ *	@stolen: unused
+ *	@align: unused
  *
  *	Create a GEM object, fill in the boilerplate and attach a handle to
  *	it so that userspace can speak about it. This does the core work
 /**
  *	psb_gem_dumb_create	-	create a dumb buffer
- *	@drm_file: our client file
+ *	@file: our client file
  *	@dev: our device
  *	@args: the requested arguments copied from userspace
  *
 /**
  *	psb_gem_fault		-	pagefault handler for GEM objects
- *	@vma: the VMA of the GEM object
  *	@vmf: fault detail
  *
  *	Invoked when a fault occurs on an mmap of a GEM managed area. GEM

drivers/gpu/drm/gma500/gem.h+2−0

@@ -8,6 +8,8 @@ · 7 unmodified lines
8	#ifndef _GEM_H	8	#ifndef _GEM_H
9	#define _GEM_H	9	#define _GEM_H
10		10
		11	struct drm_device;
		12
11	extern const struct drm_gem_object_funcs psb_gem_object_funcs;	13	extern const struct drm_gem_object_funcs psb_gem_object_funcs;
12		14
13	extern int psb_gem_create(struct drm_file file, struct drm_device dev,	15	extern int psb_gem_create(struct drm_file file, struct drm_device dev,

drivers/gpu/drm/gma500/gma_device.c+3−1

  **************************************************************************/
 #include "psb_drv.h"
+#include "gma_device.h"
 void gma_get_core_freq(struct drm_device *dev)
 {
 	uint32_t clock;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct pci_dev *pci_root =
-		pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
+		pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
 					    0, 0);
 	struct drm_psb_private *dev_priv = dev->dev_private;

drivers/gpu/drm/gma500/gma_display.c+6−6

@@ -20,7 +20,7 @@ · 19 unmodified lines
20	#include "psb_intel_drv.h"	20	#include "psb_intel_drv.h"
21	#include "psb_intel_reg.h"	21	#include "psb_intel_reg.h"
22		22
23	/**	23	/*
24	* Returns whether any output on the specified pipe is of the specified type	24	* Returns whether any output on the specified pipe is of the specified type
25	*/	25	*/
26	bool gma_pipe_has_type(struct drm_crtc *crtc, int type)	26	bool gma_pipe_has_type(struct drm_crtc *crtc, int type)
@@ -180,7 +180,7 @@ int gma_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 green, u16 blue, · 153 unmodified lines
180	return 0;	180	return 0;
181	}	181	}
182		182
183	/**	183	/*
184	* Sets the power management mode of the pipe and plane.	184	* Sets the power management mode of the pipe and plane.
185	*	185	*
186	* This code should probably grow support for turning the cursor off and back	186	* This code should probably grow support for turning the cursor off and back
@@ -559,14 +559,14 @@ int gma_crtc_set_config(struct drm_mode_set *set, · 372 unmodified lines
559	if (!dev_priv->rpm_enabled)	559	if (!dev_priv->rpm_enabled)
560	return drm_crtc_helper_set_config(set, ctx);	560	return drm_crtc_helper_set_config(set, ctx);
561		561
562	pm_runtime_forbid(&dev->pdev->dev);	562	pm_runtime_forbid(dev->dev);
563	ret = drm_crtc_helper_set_config(set, ctx);	563	ret = drm_crtc_helper_set_config(set, ctx);
564	pm_runtime_allow(&dev->pdev->dev);	564	pm_runtime_allow(dev->dev);
565		565
566	return ret;	566	return ret;
567	}	567	}
568		568
569	/**	569	/*
570	* Save HW states of given crtc	570	* Save HW states of given crtc
571	*/	571	*/
572	void gma_crtc_save(struct drm_crtc *crtc)	572	void gma_crtc_save(struct drm_crtc *crtc)
@@ -609,7 +609,7 @@ void gma_crtc_save(struct drm_crtc *crtc) · 36 unmodified lines
609	crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2));	609	crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2));
610	}	610	}
611		611
612	/**	612	/*
613	* Restore HW states of given crtc	613	* Restore HW states of given crtc
614	*/	614	*/
615	void gma_crtc_restore(struct drm_crtc *crtc)	615	void gma_crtc_restore(struct drm_crtc *crtc)

drivers/gpu/drm/gma500/gtt.c+11−9

 void psb_gtt_takedown(struct drm_device *dev)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	if (dev_priv->gtt_map) {
 		iounmap(dev_priv->gtt_map);
 		dev_priv->gtt_map = NULL;
 	}
 	if (dev_priv->gtt_initialized) {
-		pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
+		pci_write_config_word(pdev, PSB_GMCH_CTRL,
 				      dev_priv->gmch_ctrl);
 		PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL);
 		(void) PSB_RVDC32(PSB_PGETBL_CTL);
 int psb_gtt_init(struct drm_device *dev, int resume)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	unsigned gtt_pages;
 	unsigned long stolen_size, vram_stolen_size;
 	unsigned i, num_pages;
 	pg = &dev_priv->gtt;
 	/* Enable the GTT */
-	pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl);
+	pci_read_config_word(pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl);
-	pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
+	pci_write_config_word(pdev, PSB_GMCH_CTRL,
 			      dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED);
 	dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL);
 	 */
 	pg->mmu_gatt_start = 0xE0000000;
-	pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE);
+	pg->gtt_start = pci_resource_start(pdev, PSB_GTT_RESOURCE);
-	gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE)
+	gtt_pages = pci_resource_len(pdev, PSB_GTT_RESOURCE)
 								>> PAGE_SHIFT;
 	/* CDV doesn't report this. In which case the system has 64 gtt pages */
 	if (pg->gtt_start == 0 || gtt_pages == 0) {
 		pg->gtt_start = dev_priv->pge_ctl;
 	}
-	pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE);
+	pg->gatt_start = pci_resource_start(pdev, PSB_GATT_RESOURCE);
-	pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE)
+	pg->gatt_pages = pci_resource_len(pdev, PSB_GATT_RESOURCE)
 								>> PAGE_SHIFT;
-	dev_priv->gtt_mem = &dev->pdev->resource[PSB_GATT_RESOURCE];
+	dev_priv->gtt_mem = &pdev->resource[PSB_GATT_RESOURCE];
 	if (pg->gatt_pages == 0 || pg->gatt_start == 0) {
 		static struct resource fudge;	/* Preferably peppermint */
 		dev_priv->gtt_mem = &fudge;
 	}
-	pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base);
+	pci_read_config_dword(pdev, PSB_BSM, &dev_priv->stolen_base);
 	vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base
 								- PAGE_SIZE;

drivers/gpu/drm/gma500/intel_bios.c+4−4

@@ -50,7 +50,7 @@ parse_edp(struct drm_psb_private dev_priv, struct bdb_header bdb) · 49 unmodified lines
50	uint8_t panel_type;	50	uint8_t panel_type;
51		51
52	edp = find_section(bdb, BDB_EDP);	52	edp = find_section(bdb, BDB_EDP);
53		53
54	dev_priv->edp.bpp = 18;	54	dev_priv->edp.bpp = 18;
55	if (!edp) {	55	if (!edp) {
56	if (dev_priv->edp.support) {	56	if (dev_priv->edp.support) {
@@ -80,7 +80,7 @@ parse_edp(struct drm_psb_private dev_priv, struct bdb_header bdb) · 23 unmodified lines
80	dev_priv->edp.pps = *edp_pps;	80	dev_priv->edp.pps = *edp_pps;
81		81
82	DRM_DEBUG_KMS("EDP timing in vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",	82	DRM_DEBUG_KMS("EDP timing in vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
83	dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8,	83	dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8,
84	dev_priv->edp.pps.t9, dev_priv->edp.pps.t10,	84	dev_priv->edp.pps.t9, dev_priv->edp.pps.t10,
85	dev_priv->edp.pps.t11_t12);	85	dev_priv->edp.pps.t11_t12);
86		86
@@ -516,7 +516,7 @@ parse_device_mapping(struct drm_psb_private *dev_priv, · 429 unmodified lines
516	int psb_intel_init_bios(struct drm_device *dev)	516	int psb_intel_init_bios(struct drm_device *dev)
517	{	517	{
518	struct drm_psb_private *dev_priv = dev->dev_private;	518	struct drm_psb_private *dev_priv = dev->dev_private;
519	struct pci_dev *pdev = dev->pdev;	519	struct pci_dev *pdev = to_pci_dev(dev->dev);
520	struct vbt_header *vbt = NULL;	520	struct vbt_header *vbt = NULL;
521	struct bdb_header *bdb = NULL;	521	struct bdb_header *bdb = NULL;
522	u8 __iomem *bios = NULL;	522	u8 __iomem *bios = NULL;
@@ -574,7 +574,7 @@ int psb_intel_init_bios(struct drm_device *dev) · 51 unmodified lines
574	return 0;	574	return 0;
575	}	575	}
576		576
577	/**	577	/*
578	* Destroy and free VBT data	578	* Destroy and free VBT data
579	*/	579	*/
580	void psb_intel_destroy_bios(struct drm_device *dev)	580	void psb_intel_destroy_bios(struct drm_device *dev)

drivers/gpu/drm/gma500/intel_gmbus.c+2−2

@@ -196,7 +196,7 @@ intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin) · 195 unmodified lines
196	"gma500 GPIO%c", "?BACDE?F"[pin]);	196	"gma500 GPIO%c", "?BACDE?F"[pin]);
197	gpio->adapter.owner = THIS_MODULE;	197	gpio->adapter.owner = THIS_MODULE;
198	gpio->adapter.algo_data = &gpio->algo;	198	gpio->adapter.algo_data = &gpio->algo;
199	gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;	199	gpio->adapter.dev.parent = dev_priv->dev->dev;
200	gpio->algo.setsda = set_data;	200	gpio->algo.setsda = set_data;
201	gpio->algo.setscl = set_clock;	201	gpio->algo.setscl = set_clock;
202	gpio->algo.getsda = get_data;	202	gpio->algo.getsda = get_data;
@@ -417,7 +417,7 @@ int gma_intel_setup_gmbus(struct drm_device *dev) · 214 unmodified lines
417	"gma500 gmbus %s",	417	"gma500 gmbus %s",
418	names[i]);	418	names[i]);
419		419
420	bus->adapter.dev.parent = &dev->pdev->dev;	420	bus->adapter.dev.parent = dev->dev;
421	bus->adapter.algo_data = dev_priv;	421	bus->adapter.algo_data = dev_priv;
422		422
423	bus->adapter.algo = &gmbus_algorithm;	423	bus->adapter.algo = &gmbus_algorithm;

drivers/gpu/drm/gma500/intel_i2c.c+2−3

 /**
  * psb_intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg
  * @dev: DRM device
- * @output: driver specific output device
  * @reg: GPIO reg to use
  * @name: name for this bus
  *
 	snprintf(chan->adapter.name, I2C_NAME_SIZE, "intel drm %s", name);
 	chan->adapter.owner = THIS_MODULE;
 	chan->adapter.algo_data = &chan->algo;
-	chan->adapter.dev.parent = &dev->pdev->dev;
+	chan->adapter.dev.parent = dev->dev;
 	chan->algo.setsda = set_data;
 	chan->algo.setscl = set_clock;
 	chan->algo.getsda = get_data;
 /**
  * psb_intel_i2c_destroy - unregister and free i2c bus resources
- * @output: channel to free
+ * @chan: channel to free
  *
  * Unregister the adapter from the i2c layer, then free the structure.
  */

drivers/gpu/drm/gma500/mdfld_device.c+3−1

@@ -523,7 +523,9 @@ static struct gpiod_lookup_table mdfld_dsi_pipe_gpio_table = { · 522 unmodified lines
523	static int mdfld_chip_setup(struct drm_device *dev)	523	static int mdfld_chip_setup(struct drm_device *dev)
524	{	524	{
525	struct drm_psb_private *dev_priv = dev->dev_private;	525	struct drm_psb_private *dev_priv = dev->dev_private;
526	if (pci_enable_msi(dev->pdev))	526	struct pci_dev *pdev = to_pci_dev(dev->dev);
		527
		528	if (pci_enable_msi(pdev))
527	dev_warn(dev->dev, "Enabling MSI failed!\n");	529	dev_warn(dev->dev, "Enabling MSI failed!\n");
528	dev_priv->regmap = mdfld_regmap;	530	dev_priv->regmap = mdfld_regmap;
529		531

drivers/gpu/drm/gma500/mdfld_dsi_dpi.c+4−4

@@ -138,7 +138,7 @@ static void dsi_set_pipe_plane_enable_state(struct drm_device *dev, · 137 unmodified lines
138	REG_WRITE(pipeconf_reg, BIT(31));	138	REG_WRITE(pipeconf_reg, BIT(31));
139		139
140	if (REG_BIT_WAIT(pipeconf_reg, 1, 30))	140	if (REG_BIT_WAIT(pipeconf_reg, 1, 30))
141	dev_err(&dev->pdev->dev, "%s: Pipe enable timeout\n",	141	dev_err(dev->dev, "%s: Pipe enable timeout\n",
142	__func__);	142	__func__);
143		143
144	/Set up display plane /	144	/Set up display plane /
@@ -165,11 +165,11 @@ static void dsi_set_pipe_plane_enable_state(struct drm_device *dev, · 20 unmodified lines
165	REG_FLD_MOD(pipeconf_reg, 0, 31, 31);	165	REG_FLD_MOD(pipeconf_reg, 0, 31, 31);
166		166
167	if (REG_BIT_WAIT(pipeconf_reg, 0, 30))	167	if (REG_BIT_WAIT(pipeconf_reg, 0, 30))
168	dev_err(&dev->pdev->dev, "%s: Pipe disable timeout\n",	168	dev_err(dev->dev, "%s: Pipe disable timeout\n",
169	__func__);	169	__func__);
170		170
171	if (REG_BIT_WAIT(MIPI_GEN_FIFO_STAT_REG(pipe), 1, 28))	171	if (REG_BIT_WAIT(MIPI_GEN_FIFO_STAT_REG(pipe), 1, 28))
172	dev_err(&dev->pdev->dev, "%s: FIFO not empty\n",	172	dev_err(dev->dev, "%s: FIFO not empty\n",
173	__func__);	173	__func__);
174	}	174	}
175	}	175	}
@@ -867,7 +867,7 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, · 691 unmodified lines
867	REG_WRITE(MRST_DPLL_A, 0x80800000);	867	REG_WRITE(MRST_DPLL_A, 0x80800000);
868		868
869	if (REG_BIT_WAIT(pipeconf_reg, 1, 29))	869	if (REG_BIT_WAIT(pipeconf_reg, 1, 29))
870	dev_err(&dev->pdev->dev, "%s: DSI PLL lock timeout\n",	870	dev_err(dev->dev, "%s: DSI PLL lock timeout\n",
871	__func__);	871	__func__);
872		872
873	REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008);	873	REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008);

drivers/gpu/drm/gma500/mdfld_dsi_output.c+2−2

@@ -63,7 +63,7 @@ static int __init parse_LABC_control(char *arg) · 62 unmodified lines
63	early_param("LABC", parse_LABC_control);	63	early_param("LABC", parse_LABC_control);
64	#endif	64	#endif
65		65
66	/**	66	/*
67	* Check and see if the generic control or data buffer is empty and ready.	67	* Check and see if the generic control or data buffer is empty and ready.
68	*/	68	*/
69	void mdfld_dsi_gen_fifo_ready(struct drm_device *dev, u32 gen_fifo_stat_reg,	69	void mdfld_dsi_gen_fifo_ready(struct drm_device *dev, u32 gen_fifo_stat_reg,
@@ -85,7 +85,7 @@ void mdfld_dsi_gen_fifo_ready(struct drm_device *dev, u32 gen_fifo_stat_reg, · 15 unmodified lines
85	gen_fifo_stat_reg);	85	gen_fifo_stat_reg);
86	}	86	}
87		87
88	/**	88	/*
89	* Manage the DSI MIPI keyboard and display brightness.	89	* Manage the DSI MIPI keyboard and display brightness.
90	* FIXME: this is exported to OSPM code. should work out an specific	90	* FIXME: this is exported to OSPM code. should work out an specific
91	* display interface to OSPM.	91	* display interface to OSPM.

drivers/gpu/drm/gma500/mdfld_intel_display.c+3−3

@@ -95,7 +95,7 @@ void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe) · 94 unmodified lines
95	}	95	}
96	}	96	}
97		97
98	/**	98	/*
99	* Return the pipe currently connected to the panel fitter,	99	* Return the pipe currently connected to the panel fitter,
100	* or -1 if the panel fitter is not present or not in use	100	* or -1 if the panel fitter is not present or not in use
101	*/	101	*/
@@ -263,7 +263,7 @@ void mdfld_disable_crtc(struct drm_device *dev, int pipe) · 161 unmodified lines
263		263
264	}	264	}
265		265
266	/**	266	/*
267	* Sets the power management mode of the pipe and plane.	267	* Sets the power management mode of the pipe and plane.
268	*	268	*
269	* This code should probably grow support for turning the cursor off and back	269	* This code should probably grow support for turning the cursor off and back
@@ -599,7 +599,7 @@ static void mdfld_clock(int refclk, struct mrst_clock_t *clock) · 329 unmodified lines
599	clock->dot = (refclk * clock->m) / clock->p1;	599	clock->dot = (refclk * clock->m) / clock->p1;
600	}	600	}
601		601
602	/**	602	/*
603	* Returns a set of divisors for the desired target clock with the given refclk,	603	* Returns a set of divisors for the desired target clock with the given refclk,
604	* or FALSE. Divisor values are the actual divisors for	604	* or FALSE. Divisor values are the actual divisors for
605	*/	605	*/

drivers/gpu/drm/gma500/mid_bios.c+6−3

 static void mid_get_fuse_settings(struct drm_device *dev)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct pci_dev *pci_root =
-		pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
+		pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
 					    0, 0);
 	uint32_t fuse_value = 0;
 	uint32_t fuse_value_tmp = 0;
 static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
 {
 	uint32_t platform_rev_id = 0;
-	int domain = pci_domain_nr(dev_priv->dev->pdev->bus);
+	struct pci_dev *pdev = to_pci_dev(dev_priv->dev->dev);
+	int domain = pci_domain_nr(pdev->bus);
 	struct pci_dev *pci_gfx_root =
 		pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
 static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
 {
 	struct drm_device *dev = dev_priv->dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	u32 addr;
 	u8 __iomem *vbt_virtual;
 	struct mid_vbt_header vbt_header;
 	struct pci_dev *pci_gfx_root =
-		pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
+		pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
 					    0, PCI_DEVFN(2, 0));
 	int ret = -1;

drivers/gpu/drm/gma500/mmu.c+3−12

 	return pt;
 }
-struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
+static struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
-					     unsigned long addr)
+						    unsigned long addr)
 {
 	uint32_t index = psb_mmu_pd_index(addr);
 	struct psb_mmu_pt *pt;
 	return pd;
 }
-/* Returns the physical address of the PD shared by sgx/msvdx */
-uint32_t psb_get_default_pd_addr(struct psb_mmu_driver *driver)
-{
-	struct psb_mmu_pd *pd;
-	pd = psb_mmu_get_default_pd(driver);
-	return page_to_pfn(pd->p) << PAGE_SHIFT;
-}
 void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
 {
 	struct drm_device *dev = driver->dev;
 	if (pd->hw_context != -1)
 		psb_mmu_flush(pd->driver);
-	return 0;
+	return ret;
 }
 int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,

drivers/gpu/drm/gma500/oaktrail_crtc.c+3−3

@@ -174,7 +174,7 @@ static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, · 173 unmodified lines
174	return min_error == 0;	174	return min_error == 0;
175	}	175	}
176		176
177	/**	177	/*
178	* Returns a set of divisors for the desired target clock with the given refclk,	178	* Returns a set of divisors for the desired target clock with the given refclk,
179	* or FALSE. Divisor values are the actual divisors for	179	* or FALSE. Divisor values are the actual divisors for
180	*/	180	*/
@@ -205,7 +205,7 @@ static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, · 24 unmodified lines
205	return err != target;	205	return err != target;
206	}	206	}
207		207
208	/**	208	/*
209	* Sets the power management mode of the pipe and plane.	209	* Sets the power management mode of the pipe and plane.
210	*	210	*
211	* This code should probably grow support for turning the cursor off and back	211	* This code should probably grow support for turning the cursor off and back
@@ -337,7 +337,7 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) · 125 unmodified lines
337	gma_power_end(dev);	337	gma_power_end(dev);
338	}	338	}
339		339
340	/**	340	/*
341	* Return the pipe currently connected to the panel fitter,	341	* Return the pipe currently connected to the panel fitter,
342	* or -1 if the panel fitter is not present or not in use	342	* or -1 if the panel fitter is not present or not in use
343	*/	343	*/

drivers/gpu/drm/gma500/oaktrail_device.c+3−2

 static int oaktrail_chip_setup(struct drm_device *dev)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	int ret;
-	if (pci_enable_msi(dev->pdev))
+	if (pci_enable_msi(pdev))
 		dev_warn(dev->dev, "Enabling MSI failed!\n");
 	dev_priv->regmap = oaktrail_regmap;

drivers/gpu/drm/gma500/oaktrail_lvds.c+3−2

 #define MRST_BLC_MAX_PWM_REG_FREQ	    0xFFFF
 #define BRIGHTNESS_MAX_LEVEL 100
-/**
+/*
  * Sets the power state for the panel.
  */
 static void oaktrail_lvds_set_power(struct drm_device *dev,
 			pp_status = REG_READ(PP_STATUS);
 		} while (pp_status & PP_ON);
 		dev_priv->is_lvds_on = false;
-		pm_request_idle(&dev->pdev->dev);
+		pm_request_idle(dev->dev);
 	}
 	gma_power_end(dev);
 }
 /**
  * oaktrail_lvds_init - setup LVDS connectors on this device
  * @dev: drm device
+ * @mode_dev: PSB mode device
  *
  * Create the connector, register the LVDS DDC bus, and try to figure out what
  * modes we can display on the LVDS panel (if present).

drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c+5−5

@@ -66,12 +66,12 @@ · 65 unmodified lines
66	static int get_clock(void *data)	66	static int get_clock(void *data)
67	{	67	{
68	struct psb_intel_i2c_chan *chan = data;	68	struct psb_intel_i2c_chan *chan = data;
69	u32 val, tmp;	69	u32 val;
70		70
71	val = LPC_READ_REG(chan, RGIO);	71	val = LPC_READ_REG(chan, RGIO);
72	val \|= GPIO_CLOCK;	72	val \|= GPIO_CLOCK;
73	LPC_WRITE_REG(chan, RGIO, val);	73	LPC_WRITE_REG(chan, RGIO, val);
74	tmp = LPC_READ_REG(chan, RGLVL);	74	LPC_READ_REG(chan, RGLVL);
75	val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0;	75	val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0;
76		76
77	return val;	77	return val;
@@ -80,12 +80,12 @@ static int get_clock(void *data) · 2 unmodified lines
80	static int get_data(void *data)	80	static int get_data(void *data)
81	{	81	{
82	struct psb_intel_i2c_chan *chan = data;	82	struct psb_intel_i2c_chan *chan = data;
83	u32 val, tmp;	83	u32 val;
84		84
85	val = LPC_READ_REG(chan, RGIO);	85	val = LPC_READ_REG(chan, RGIO);
86	val \|= GPIO_DATA;	86	val \|= GPIO_DATA;
87	LPC_WRITE_REG(chan, RGIO, val);	87	LPC_WRITE_REG(chan, RGIO, val);
88	tmp = LPC_READ_REG(chan, RGLVL);	88	LPC_READ_REG(chan, RGLVL);
89	val = (LPC_READ_REG(chan, RGLVL) & GPIO_DATA) ? 1 : 0;	89	val = (LPC_READ_REG(chan, RGLVL) & GPIO_DATA) ? 1 : 0;
90		90
91	return val;	91	return val;
@@ -145,7 +145,7 @@ void oaktrail_lvds_i2c_init(struct drm_encoder *encoder) · 53 unmodified lines
145	strncpy(chan->adapter.name, "gma500 LPC", I2C_NAME_SIZE - 1);	145	strncpy(chan->adapter.name, "gma500 LPC", I2C_NAME_SIZE - 1);
146	chan->adapter.owner = THIS_MODULE;	146	chan->adapter.owner = THIS_MODULE;
147	chan->adapter.algo_data = &chan->algo;	147	chan->adapter.algo_data = &chan->algo;
148	chan->adapter.dev.parent = &dev->pdev->dev;	148	chan->adapter.dev.parent = dev->dev;
149	chan->algo.setsda = set_data;	149	chan->algo.setsda = set_data;
150	chan->algo.setscl = set_clock;	150	chan->algo.setscl = set_clock;
151	chan->algo.getsda = get_data;	151	chan->algo.getsda = get_data;

drivers/gpu/drm/gma500/opregion.c+2−1

 int psb_intel_opregion_setup(struct drm_device *dev)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct psb_intel_opregion *opregion = &dev_priv->opregion;
 	u32 opregion_phy, mboxes;
 	void __iomem *base;
 	int err = 0;
-	pci_read_config_dword(dev->pdev, PCI_ASLS, &opregion_phy);
+	pci_read_config_dword(pdev, PCI_ASLS, &opregion_phy);
 	if (opregion_phy == 0) {
 		DRM_DEBUG_DRIVER("ACPI Opregion not supported\n");
 		return -ENOTSUPP;

drivers/gpu/drm/gma500/power.c+11−10

  */
 void gma_power_uninit(struct drm_device *dev)
 {
-	pm_runtime_disable(&dev->pdev->dev);
+	pm_runtime_disable(dev->dev);
-	pm_runtime_set_suspended(&dev->pdev->dev);
+	pm_runtime_set_suspended(dev->dev);
 }
 /**
 /**
  *	gma_resume_display	-	resume display side logic
+ *	@pdev: PCI device
  *
  *	Resume the display hardware restoring state and enabling
  *	as necessary.
 /**
  *	gma_resume_pci		-	resume helper
- *	@dev: our PCI device
+ *	@pdev: our PCI device
  *
  *	Perform the resume processing on our PCI device state - rewrite
  *	register state and re-enable the PCI device
 /**
  *	gma_power_suspend		-	bus callback for suspend
- *	@pdev: our PCI device
+ *	@_dev: our device
- *	@state: suspend type
  *
  *	Called back by the PCI layer during a suspend of the system. We
  *	perform the necessary shut down steps and save enough state that
 /**
  *	gma_power_resume		-	resume power
- *	@pdev: PCI device
+ *	@_dev: our device
  *
  *	Resume the PCI side of the graphics and then the displays
  */
 bool gma_power_begin(struct drm_device *dev, bool force_on)
 {
 	struct drm_psb_private *dev_priv = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	int ret;
 	unsigned long flags;
 	/* Power already on ? */
 	if (dev_priv->display_power) {
 		dev_priv->display_count++;
-		pm_runtime_get(&dev->pdev->dev);
+		pm_runtime_get(dev->dev);
 		spin_unlock_irqrestore(&power_ctrl_lock, flags);
 		return true;
 	}
 		goto out_false;
 	/* Ok power up needed */
-	ret = gma_resume_pci(dev->pdev);
+	ret = gma_resume_pci(pdev);
 	if (ret == 0) {
 		psb_irq_preinstall(dev);
 		psb_irq_postinstall(dev);
-		pm_runtime_get(&dev->pdev->dev);
+		pm_runtime_get(dev->dev);
 		dev_priv->display_count++;
 		spin_unlock_irqrestore(&power_ctrl_lock, flags);
 		return true;
 	dev_priv->display_count--;
 	WARN_ON(dev_priv->display_count < 0);
 	spin_unlock_irqrestore(&power_ctrl_lock, flags);
-	pm_runtime_put(&dev->pdev->dev);
+	pm_runtime_put(dev->dev);
 }
 int psb_runtime_suspend(struct device *dev)

drivers/gpu/drm/gma500/psb_drv.c+8−8

 static int psb_driver_load(struct drm_device *dev, unsigned long flags)
 {
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct drm_psb_private *dev_priv;
 	unsigned long resource_start, resource_len;
 	unsigned long irqflags;
 	pg = &dev_priv->gtt;
-	pci_set_master(dev->pdev);
+	pci_set_master(pdev);
 	dev_priv->num_pipe = dev_priv->ops->pipes;
-	resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
+	resource_start = pci_resource_start(pdev, PSB_MMIO_RESOURCE);
 	dev_priv->vdc_reg =
 	    ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
 		goto out_err;
 	if (IS_MRST(dev)) {
-		int domain = pci_domain_nr(dev->pdev->bus);
+		int domain = pci_domain_nr(pdev->bus);
 		dev_priv->aux_pdev =
 			pci_get_domain_bus_and_slot(domain, 0,
 	PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
 	spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
-	drm_irq_install(dev, dev->pdev->irq);
+	drm_irq_install(dev, pdev->irq);
 	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 	psb_intel_opregion_enable_asle(dev);
 #if 0
 	/* Enable runtime pm at last */
-	pm_runtime_enable(&dev->pdev->dev);
+	pm_runtime_enable(dev->dev);
-	pm_runtime_set_active(&dev->pdev->dev);
+	pm_runtime_set_active(dev->dev);
 #endif
 	/* Intel drm driver load is done, continue doing pvr load */
 	return 0;
 	if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
 		runtime_allowed++;
-		pm_runtime_allow(&dev->pdev->dev);
+		pm_runtime_allow(dev->dev);
 		dev_priv->rpm_enabled = 1;
 	}
 	return drm_ioctl(filp, cmd, arg);
 		goto err_pci_disable_device;
 	}
-	dev->pdev = pdev;
 	pci_set_drvdata(pdev, dev);
 	ret = psb_driver_load(dev, ent->driver_data);

drivers/gpu/drm/gma500/psb_drv.h+4−4

@@ -43,10 +43,10 @@ enum { · 42 unmodified lines
43	CHIP_MFLD_0130 = 3, /* Medfield */	43	CHIP_MFLD_0130 = 3, /* Medfield */
44	};	44	};
45		45
46	#define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108)	46	#define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
47	#define IS_MRST(dev) (((dev)->pdev->device & 0xfff0) == 0x4100)	47	#define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
48	#define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130)	48	#define IS_MFLD(drm) ((to_pci_dev((drm)->dev)->device & 0xfff8) == 0x0130)
49	#define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0)	49	#define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
50		50
51	/* Hardware offsets */	51	/* Hardware offsets */
52	#define PSB_VDC_OFFSET 0x00000000	52	#define PSB_VDC_OFFSET 0x00000000

drivers/gpu/drm/gma500/psb_intel_display.c+1−1

@@ -71,7 +71,7 @@ static void psb_intel_clock(int refclk, struct gma_clock_t *clock) · 70 unmodified lines
71	clock->dot = clock->vco / clock->p;	71	clock->dot = clock->vco / clock->p;
72	}	72	}
73		73
74	/**	74	/*
75	* Return the pipe currently connected to the panel fitter,	75	* Return the pipe currently connected to the panel fitter,
76	* or -1 if the panel fitter is not present or not in use	76	* or -1 if the panel fitter is not present or not in use
77	*/	77	*/

drivers/gpu/drm/gma500/psb_intel_lvds.c+4−3

 	        dev_err(dev->dev, "set power, chip off!\n");
 		return;
         }
 	if (on) {
 		REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
 			  POWER_TARGET_ON);
 /**
  * psb_intel_lvds_init - setup LVDS connectors on this device
  * @dev: drm device
+ * @mode_dev: mode device
  *
  * Create the connector, register the LVDS DDC bus, and try to figure out what
  * modes we can display on the LVDS panel (if present).
 	lvds_priv->i2c_bus = psb_intel_i2c_create(dev, GPIOB, "LVDSBLC_B");
 	if (!lvds_priv->i2c_bus) {
 		dev_printk(KERN_ERR,
-			&dev->pdev->dev, "I2C bus registration failed.\n");
+			dev->dev, "I2C bus registration failed.\n");
 		goto failed_blc_i2c;
 	}
 	lvds_priv->i2c_bus->slave_addr = 0x2C;
 	/* Set up the DDC bus. */
 	lvds_priv->ddc_bus = psb_intel_i2c_create(dev, GPIOC, "LVDSDDC_C");
 	if (!lvds_priv->ddc_bus) {
-		dev_printk(KERN_ERR, &dev->pdev->dev,
+		dev_printk(KERN_ERR, dev->dev,
 			   "DDC bus registration " "failed.\n");
 		goto failed_ddc;
 	}

drivers/gpu/drm/gma500/psb_intel_modes.c+2−1

 /**
  * psb_intel_ddc_probe
- *
+ * @adapter:   Associated I2C adaptor
  */
 bool psb_intel_ddc_probe(struct i2c_adapter *adapter)
 {
 /**
  * psb_intel_ddc_get_modes - get modelist from monitor
  * @connector: DRM connector device to use
+ * @adapter:   Associated I2C adaptor
  *
  * Fetch the EDID information from @connector using the DDC bus.
  */

drivers/gpu/drm/gma500/psb_intel_sdvo.c+4−4

@@ -221,7 +221,7 @@ static bool · 220 unmodified lines
221	psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,	221	psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
222	struct psb_intel_sdvo_connector *psb_intel_sdvo_connector);	222	struct psb_intel_sdvo_connector *psb_intel_sdvo_connector);
223		223
224	/**	224	/*
225	* Writes the SDVOB or SDVOC with the given value, but always writes both	225	* Writes the SDVOB or SDVOC with the given value, but always writes both
226	* SDVOB and SDVOC to work around apparent hardware issues (according to	226	* SDVOB and SDVOC to work around apparent hardware issues (according to
227	* comments in the BIOS).	227	* comments in the BIOS).
@@ -588,7 +588,7 @@ static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdv · 360 unmodified lines
588	&targets, sizeof(targets));	588	&targets, sizeof(targets));
589	}	589	}
590		590
591	/**	591	/*
592	* Return whether each input is trained.	592	* Return whether each input is trained.
593	*	593	*
594	* This function is making an assumption about the layout of the response,	594	* This function is making an assumption about the layout of the response,
@@ -1818,7 +1818,7 @@ psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo) · 1223 unmodified lines
1818	#endif	1818	#endif
1819	}	1819	}
1820		1820
1821	/**	1821	/*
1822	* Choose the appropriate DDC bus for control bus switch command for this	1822	* Choose the appropriate DDC bus for control bus switch command for this
1823	* SDVO output based on the controlled output.	1823	* SDVO output based on the controlled output.
1824	*	1824	*
@@ -2406,7 +2406,7 @@ psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo, · 581 unmodified lines
2406	sdvo->ddc.owner = THIS_MODULE;	2406	sdvo->ddc.owner = THIS_MODULE;
2407	sdvo->ddc.class = I2C_CLASS_DDC;	2407	sdvo->ddc.class = I2C_CLASS_DDC;
2408	snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");	2408	snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2409	sdvo->ddc.dev.parent = &dev->pdev->dev;	2409	sdvo->ddc.dev.parent = dev->dev;
2410	sdvo->ddc.algo_data = sdvo;	2410	sdvo->ddc.algo_data = sdvo;
2411	sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;	2411	sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;
2412		2412

drivers/gpu/drm/gma500/psb_irq.c+1−2

 	}
 }
-/**
+/*
  * Display controller interrupt handler for pipe event.
- *
  */
 static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
 {

drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c+18−18

@@ -454,13 +454,13 @@ static void tc35876x_brightness_init(struct drm_device *dev) · 453 unmodified lines
454	ret = intel_scu_ipc_ioread8(GPIOPWMCTRL, &pwmctrl);	454	ret = intel_scu_ipc_ioread8(GPIOPWMCTRL, &pwmctrl);
455	if (ret \|\| pwmctrl != 0x01) {	455	if (ret \|\| pwmctrl != 0x01) {
456	if (ret)	456	if (ret)
457	dev_err(&dev->pdev->dev, "GPIOPWMCTRL read failed\n");	457	dev_err(dev->dev, "GPIOPWMCTRL read failed\n");
458	else	458	else
459	dev_warn(&dev->pdev->dev, "GPIOPWMCTRL was not set to system clock (pwmctrl = 0x%02x)\n", pwmctrl);	459	dev_warn(dev->dev, "GPIOPWMCTRL was not set to system clock (pwmctrl = 0x%02x)\n", pwmctrl);
460		460
461	ret = intel_scu_ipc_iowrite8(GPIOPWMCTRL, 0x01);	461	ret = intel_scu_ipc_iowrite8(GPIOPWMCTRL, 0x01);
462	if (ret)	462	if (ret)
463	dev_err(&dev->pdev->dev, "GPIOPWMCTRL set failed\n");	463	dev_err(dev->dev, "GPIOPWMCTRL set failed\n");
464	}	464	}
465		465
466	clkdiv = calc_clkdiv(SYSTEMCLK, PWM_FREQUENCY);	466	clkdiv = calc_clkdiv(SYSTEMCLK, PWM_FREQUENCY);
@@ -470,9 +470,9 @@ static void tc35876x_brightness_init(struct drm_device *dev) · 3 unmodified lines
470	ret = intel_scu_ipc_iowrite8(PWM0CLKDIV0, clkdiv & 0xff);	470	ret = intel_scu_ipc_iowrite8(PWM0CLKDIV0, clkdiv & 0xff);
471		471
472	if (ret)	472	if (ret)
473	dev_err(&dev->pdev->dev, "PWM0CLKDIV set failed\n");	473	dev_err(dev->dev, "PWM0CLKDIV set failed\n");
474	else	474	else
475	dev_dbg(&dev->pdev->dev, "PWM0CLKDIV set to 0x%04x (%d Hz)\n",	475	dev_dbg(dev->dev, "PWM0CLKDIV set to 0x%04x (%d Hz)\n",
476	clkdiv, PWM_FREQUENCY);	476	clkdiv, PWM_FREQUENCY);
477	}	477	}
478		478
@@ -575,7 +575,7 @@ static struct drm_display_mode tc35876x_get_config_mode(struct drm_device dev) · 96 unmodified lines
575	{	575	{
576	struct drm_display_mode *mode;	576	struct drm_display_mode *mode;
577		577
578	dev_dbg(&dev->pdev->dev, "%s\n", __func__);	578	dev_dbg(dev->dev, "%s\n", __func__);
579		579
580	mode = kzalloc(sizeof(*mode), GFP_KERNEL);	580	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
581	if (!mode)	581	if (!mode)
@@ -592,15 +592,15 @@ static struct drm_display_mode tc35876x_get_config_mode(struct drm_device dev) · 10 unmodified lines
592	mode->vtotal = 838;	592	mode->vtotal = 838;
593	mode->clock = 33324 << 1;	593	mode->clock = 33324 << 1;
594		594
595	dev_info(&dev->pdev->dev, "hdisplay(w) = %d\n", mode->hdisplay);	595	dev_info(dev->dev, "hdisplay(w) = %d\n", mode->hdisplay);
596	dev_info(&dev->pdev->dev, "vdisplay(h) = %d\n", mode->vdisplay);	596	dev_info(dev->dev, "vdisplay(h) = %d\n", mode->vdisplay);
597	dev_info(&dev->pdev->dev, "HSS = %d\n", mode->hsync_start);	597	dev_info(dev->dev, "HSS = %d\n", mode->hsync_start);
598	dev_info(&dev->pdev->dev, "HSE = %d\n", mode->hsync_end);	598	dev_info(dev->dev, "HSE = %d\n", mode->hsync_end);
599	dev_info(&dev->pdev->dev, "htotal = %d\n", mode->htotal);	599	dev_info(dev->dev, "htotal = %d\n", mode->htotal);
600	dev_info(&dev->pdev->dev, "VSS = %d\n", mode->vsync_start);	600	dev_info(dev->dev, "VSS = %d\n", mode->vsync_start);
601	dev_info(&dev->pdev->dev, "VSE = %d\n", mode->vsync_end);	601	dev_info(dev->dev, "VSE = %d\n", mode->vsync_end);
602	dev_info(&dev->pdev->dev, "vtotal = %d\n", mode->vtotal);	602	dev_info(dev->dev, "vtotal = %d\n", mode->vtotal);
603	dev_info(&dev->pdev->dev, "clock = %d\n", mode->clock);	603	dev_info(dev->dev, "clock = %d\n", mode->clock);
604		604
605	drm_mode_set_name(mode);	605	drm_mode_set_name(mode);
606	drm_mode_set_crtcinfo(mode, 0);	606	drm_mode_set_crtcinfo(mode, 0);
@@ -775,19 +775,19 @@ void tc35876x_init(struct drm_device *dev) · 168 unmodified lines
775	{	775	{
776	int r;	776	int r;
777		777
778	dev_dbg(&dev->pdev->dev, "%s\n", __func__);	778	dev_dbg(dev->dev, "%s\n", __func__);
779		779
780	cmi_lcd_hack_create_device();	780	cmi_lcd_hack_create_device();
781		781
782	r = i2c_add_driver(&cmi_lcd_i2c_driver);	782	r = i2c_add_driver(&cmi_lcd_i2c_driver);
783	if (r < 0)	783	if (r < 0)
784	dev_err(&dev->pdev->dev,	784	dev_err(dev->dev,
785	"%s: i2c_add_driver() for %s failed (%d)\n",	785	"%s: i2c_add_driver() for %s failed (%d)\n",
786	__func__, cmi_lcd_i2c_driver.driver.name, r);	786	__func__, cmi_lcd_i2c_driver.driver.name, r);
787		787
788	r = i2c_add_driver(&tc35876x_bridge_i2c_driver);	788	r = i2c_add_driver(&tc35876x_bridge_i2c_driver);
789	if (r < 0)	789	if (r < 0)
790	dev_err(&dev->pdev->dev,	790	dev_err(dev->dev,
791	"%s: i2c_add_driver() for %s failed (%d)\n",	791	"%s: i2c_add_driver() for %s failed (%d)\n",
792	__func__, tc35876x_bridge_i2c_driver.driver.name, r);	792	__func__, tc35876x_bridge_i2c_driver.driver.name, r);
793		793

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c+6−7

 static int hibmc_hw_map(struct hibmc_drm_private *priv)
 {
 	struct drm_device *dev = &priv->dev;
-	struct pci_dev *pdev = dev->pdev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	resource_size_t addr, size, ioaddr, iosize;
 	ioaddr = pci_resource_start(pdev, 1);
 	if (dev->irq_enabled)
 		drm_irq_uninstall(dev);
-	pci_disable_msi(dev->pdev);
+	pci_disable_msi(to_pci_dev(dev->dev));
 	return 0;
 }
 static int hibmc_load(struct drm_device *dev)
 {
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
 	int ret;
 	if (ret)
 		goto err;
-	ret = drmm_vram_helper_init(dev, pci_resource_start(dev->pdev, 0),
+	ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0), priv->fb_size);
-				    priv->fb_size);
 	if (ret) {
 		drm_err(dev, "Error initializing VRAM MM; %d\n", ret);
 		goto err;
 		goto err;
 	}
-	ret = pci_enable_msi(dev->pdev);
+	ret = pci_enable_msi(pdev);
 	if (ret) {
 		drm_warn(dev, "enabling MSI failed: %d\n", ret);
 	} else {
-		ret = drm_irq_install(dev, dev->pdev->irq);
+		ret = drm_irq_install(dev, pdev->irq);
 		if (ret)
 			drm_warn(dev, "install irq failed: %d\n", ret);
 	}
 	}
 	dev = &priv->dev;
-	dev->pdev = pdev;
 	pci_set_drvdata(pdev, dev);
 	ret = pcim_enable_device(pdev);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c+1−1

@@ -83,7 +83,7 @@ int hibmc_ddc_create(struct drm_device *drm_dev, · 82 unmodified lines
83	connector->adapter.owner = THIS_MODULE;	83	connector->adapter.owner = THIS_MODULE;
84	connector->adapter.class = I2C_CLASS_DDC;	84	connector->adapter.class = I2C_CLASS_DDC;
85	snprintf(connector->adapter.name, I2C_NAME_SIZE, "HIS i2c bit bus");	85	snprintf(connector->adapter.name, I2C_NAME_SIZE, "HIS i2c bit bus");
86	connector->adapter.dev.parent = &drm_dev->pdev->dev;	86	connector->adapter.dev.parent = drm_dev->dev;
87	i2c_set_adapdata(&connector->adapter, connector);	87	i2c_set_adapdata(&connector->adapter, connector);
88	connector->adapter.algo_data = &connector->bit_data;	88	connector->adapter.algo_data = &connector->bit_data;
89		89

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c+4−14

 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_probe_helper.h>
 #include <drm/drm_print.h>
+#include <drm/drm_simple_kms_helper.h>
 #include "hibmc_drm_drv.h"
 #include "hibmc_drm_regs.h"
 	return count;
 }
-static enum drm_mode_status hibmc_connector_mode_valid(struct drm_connector *connector,
-						       struct drm_display_mode *mode)
-{
-	return MODE_OK;
-}
 static void hibmc_connector_destroy(struct drm_connector *connector)
 {
 	struct hibmc_connector *hibmc_connector = to_hibmc_connector(connector);
 static const struct drm_connector_helper_funcs
 	hibmc_connector_helper_funcs = {
 	.get_modes = hibmc_connector_get_modes,
-	.mode_valid = hibmc_connector_mode_valid,
 };
 static const struct drm_connector_funcs hibmc_connector_funcs = {
 	.mode_set = hibmc_encoder_mode_set,
 };
-static const struct drm_encoder_funcs hibmc_encoder_funcs = {
-	.destroy = drm_encoder_cleanup,
-};
 int hibmc_vdac_init(struct hibmc_drm_private *priv)
 {
 	struct drm_device *dev = &priv->dev;
 	struct hibmc_connector *hibmc_connector = &priv->connector;
 	struct drm_encoder *encoder = &priv->encoder;
+	struct drm_crtc *crtc = &priv->crtc;
 	struct drm_connector *connector = &hibmc_connector->base;
 	int ret;
 		return ret;
 	}
-	encoder->possible_crtcs = 0x1;
+	encoder->possible_crtcs = drm_crtc_mask(crtc);
-	ret = drm_encoder_init(dev, encoder, &hibmc_encoder_funcs,
+	ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
-			       DRM_MODE_ENCODER_DAC, NULL);
 	if (ret) {
 		drm_err(dev, "failed to init encoder: %d\n", ret);
 		return ret;

drivers/gpu/drm/mga/mga_ioc32.c+7−7

@@ -1,4 +1,4 @@
1	/**	1	/*
2	* \file mga_ioc32.c	2	* \file mga_ioc32.c
3	*	3	*
4	* 32-bit ioctl compatibility routines for the MGA DRM.	4	* 32-bit ioctl compatibility routines for the MGA DRM.
@@ -159,13 +159,13 @@ static struct { · 154 unmodified lines
159	};	159	};
160		160
161	/**	161	/**
162	* Called whenever a 32-bit process running under a 64-bit kernel	162	* mga_compat_ioctl - Called whenever a 32-bit process running under
163	* performs an ioctl on /dev/dri/card<n>.	163	* a 64-bit kernel performs an ioctl on /dev/dri/card<n>.
164	*	164	*
165	* \param filp file pointer.	165	* @filp: file pointer.
166	* \param cmd command.	166	* @cmd: command.
167	* \param arg user argument.	167	* @arg: user argument.
168	* \return zero on success or negative number on failure.	168	* return: zero on success or negative number on failure.
169	*/	169	*/
170	long mga_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)	170	long mga_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
171	{	171	{

drivers/gpu/drm/mgag200/mgag200_drv.c+11−9

 static bool mgag200_has_sgram(struct mga_device *mdev)
 {
 	struct drm_device *dev = &mdev->base;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	u32 option;
 	int ret;
-	ret = pci_read_config_dword(dev->pdev, PCI_MGA_OPTION, &option);
+	ret = pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
 	if (drm_WARN(dev, ret, "failed to read PCI config dword: %d\n", ret))
 		return false;
 static int mgag200_regs_init(struct mga_device *mdev)
 {
 	struct drm_device *dev = &mdev->base;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	u32 option, option2;
 	u8 crtcext3;
 	}
 	if (option)
-		pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
+		pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
 	if (option2)
-		pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
+		pci_write_config_dword(pdev, PCI_MGA_OPTION2, option2);
 	/* BAR 1 contains registers */
-	mdev->rmmio_base = pci_resource_start(dev->pdev, 1);
+	mdev->rmmio_base = pci_resource_start(pdev, 1);
-	mdev->rmmio_size = pci_resource_len(dev->pdev, 1);
+	mdev->rmmio_size = pci_resource_len(pdev, 1);
 	if (!devm_request_mem_region(dev->dev, mdev->rmmio_base,
 				     mdev->rmmio_size, "mgadrmfb_mmio")) {
 		return -ENOMEM;
 	}
-	mdev->rmmio = pcim_iomap(dev->pdev, 1, 0);
+	mdev->rmmio = pcim_iomap(pdev, 1, 0);
 	if (mdev->rmmio == NULL)
 		return -ENOMEM;
 static void mgag200_g200_init_refclk(struct mga_device *mdev)
 {
 	struct drm_device *dev = &mdev->base;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	unsigned char __iomem *rom;
 	unsigned char *bios;
 	size_t size;
 	mdev->model.g200.pclk_max = 230000;
 	mdev->model.g200.ref_clk = 27050;
-	rom = pci_map_rom(dev->pdev, &size);
+	rom = pci_map_rom(pdev, &size);
 	if (!rom)
 		return;
 	vfree(bios);
 out:
-	pci_unmap_rom(dev->pdev, rom);
+	pci_unmap_rom(pdev, rom);
 }
 static void mgag200_g200se_init_unique_id(struct mga_device *mdev)
 		return mdev;
 	dev = &mdev->base;
-	dev->pdev = pdev;
 	pci_set_drvdata(pdev, dev);
 	ret = mgag200_device_init(mdev, flags);

drivers/gpu/drm/mgag200/mgag200_i2c.c+1−1

@@ -126,7 +126,7 @@ struct mga_i2c_chan mgag200_i2c_create(struct drm_device dev) · 125 unmodified lines
126	i2c->clock = clock;	126	i2c->clock = clock;
127	i2c->adapter.owner = THIS_MODULE;	127	i2c->adapter.owner = THIS_MODULE;
128	i2c->adapter.class = I2C_CLASS_DDC;	128	i2c->adapter.class = I2C_CLASS_DDC;
129	i2c->adapter.dev.parent = &dev->pdev->dev;	129	i2c->adapter.dev.parent = dev->dev;
130	i2c->dev = dev;	130	i2c->dev = dev;
131	i2c_set_adapdata(&i2c->adapter, i2c);	131	i2c_set_adapdata(&i2c->adapter, i2c);
132	snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), "mga i2c");	132	snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), "mga i2c");

drivers/gpu/drm/mgag200/mgag200_mm.c+6−4

 static void mgag200_mm_release(struct drm_device *dev, void *ptr)
 {
 	struct mga_device *mdev = to_mga_device(dev);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	mdev->vram_fb_available = 0;
 	iounmap(mdev->vram);
-	arch_io_free_memtype_wc(pci_resource_start(dev->pdev, 0),
+	arch_io_free_memtype_wc(pci_resource_start(pdev, 0),
-				pci_resource_len(dev->pdev, 0));
+				pci_resource_len(pdev, 0));
 	arch_phys_wc_del(mdev->fb_mtrr);
 	mdev->fb_mtrr = 0;
 }
 int mgag200_mm_init(struct mga_device *mdev)
 {
 	struct drm_device *dev = &mdev->base;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	u8 misc;
 	resource_size_t start, len;
 	int ret;
 	WREG8(MGA_MISC_OUT, misc);
 	/* BAR 0 is VRAM */
-	start = pci_resource_start(dev->pdev, 0);
+	start = pci_resource_start(pdev, 0);
-	len = pci_resource_len(dev->pdev, 0);
+	len = pci_resource_len(pdev, 0);
 	if (!devm_request_mem_region(dev->dev, start, len, "mgadrmfb_vram")) {
 		drm_err(dev, "can't reserve VRAM\n");

drivers/gpu/drm/nouveau/dispnv04/arb.c+7−5

 	int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
 	int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
 	uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	sim_data.pclk_khz = VClk;
 	sim_data.mclk_khz = MClk;
 	sim_data.nvclk_khz = NVClk;
 	sim_data.bpp = bpp;
 	sim_data.two_heads = nv_two_heads(dev);
-	if ((dev->pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
+	if ((pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
-	    (dev->pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
+	    (pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
 		uint32_t type;
-		int domain = pci_domain_nr(dev->pdev->bus);
+		int domain = pci_domain_nr(pdev->bus);
 		pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
 				      0x7c, &type);
 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN)
 		nv04_update_arb(dev, vclk, bpp, burst, lwm);
-	else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
+	else if ((pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
-		 (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
+		 (pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
 		*burst = 128;
 		*lwm = 0x0480;
 	} else

drivers/gpu/drm/nouveau/dispnv04/dfp.c+3−2

 #ifdef __powerpc__
 	struct drm_device *dev = encoder->dev;
 	struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	/* BIOS scripts usually take care of the backlight, thanks
 	 * Apple for your consistency.
 	 */
-	if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 ||
+	if (pdev->device == 0x0174 || pdev->device == 0x0179 ||
-	    dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) {
+	    pdev->device == 0x0189 || pdev->device == 0x0329) {
 		if (mode == DRM_MODE_DPMS_ON) {
 			nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
 			nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);

drivers/gpu/drm/nouveau/dispnv04/disp.h+8−6

@@ -130,7 +130,7 @@ static inline bool · 129 unmodified lines
130	nv_two_heads(struct drm_device *dev)	130	nv_two_heads(struct drm_device *dev)
131	{	131	{
132	struct nouveau_drm *drm = nouveau_drm(dev);	132	struct nouveau_drm *drm = nouveau_drm(dev);
133	const int impl = dev->pdev->device & 0x0ff0;	133	const int impl = to_pci_dev(dev->dev)->device & 0x0ff0;
134		134
135	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&	135	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&
136	impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)	136	impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
@@ -142,14 +142,14 @@ nv_two_heads(struct drm_device *dev) · 5 unmodified lines
142	static inline bool	142	static inline bool
143	nv_gf4_disp_arch(struct drm_device *dev)	143	nv_gf4_disp_arch(struct drm_device *dev)
144	{	144	{
145	return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110;	145	return nv_two_heads(dev) && (to_pci_dev(dev->dev)->device & 0x0ff0) != 0x0110;
146	}	146	}
147		147
148	static inline bool	148	static inline bool
149	nv_two_reg_pll(struct drm_device *dev)	149	nv_two_reg_pll(struct drm_device *dev)
150	{	150	{
151	struct nouveau_drm *drm = nouveau_drm(dev);	151	struct nouveau_drm *drm = nouveau_drm(dev);
152	const int impl = dev->pdev->device & 0x0ff0;	152	const int impl = to_pci_dev(dev->dev)->device & 0x0ff0;
153		153
154	if (impl == 0x0310 \|\| impl == 0x0340 \|\| drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE)	154	if (impl == 0x0310 \|\| impl == 0x0340 \|\| drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE)
155	return true;	155	return true;
@@ -160,9 +160,11 @@ static inline bool · 4 unmodified lines
160	nv_match_device(struct drm_device *dev, unsigned device,	160	nv_match_device(struct drm_device *dev, unsigned device,
161	unsigned sub_vendor, unsigned sub_device)	161	unsigned sub_vendor, unsigned sub_device)
162	{	162	{
163	return dev->pdev->device == device &&	163	struct pci_dev *pdev = to_pci_dev(dev->dev);
164	dev->pdev->subsystem_vendor == sub_vendor &&	164
165	dev->pdev->subsystem_device == sub_device;	165	return pdev->device == device &&
		166	pdev->subsystem_vendor == sub_vendor &&
		167	pdev->subsystem_device == sub_device;
166	}	168	}
167		169
168	#include <subdev/bios/init.h>	170	#include <subdev/bios/init.h>

drivers/gpu/drm/nouveau/dispnv04/hw.c+6−4

 int
 nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
 {
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct nvkm_pll_vals pllvals;
 	int ret;
 	int domain;
-	domain = pci_domain_nr(dev->pdev->bus);
+	domain = pci_domain_nr(pdev->bus);
 	if (plltype == PLL_MEMORY &&
-	    (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
+	    (pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
 		uint32_t mpllP;
 		pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
 				      0x6c, &mpllP);
 		return 400000 / mpllP;
 	} else
 	if (plltype == PLL_MEMORY &&
-	    (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) {
+	    (pdev->device & 0xff0) == CHIPSET_NFORCE2) {
 		uint32_t clock;
 		pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5),
 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	uint8_t misc, gr4, gr5, gr6, seq2, seq4;
 	bool graphicsmode;
 	unsigned plane;
 	NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor");
 	/* map first 64KiB of VRAM, holds VGA fonts etc */
-	iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536);
+	iovram = ioremap(pci_resource_start(pdev, 1), 65536);
 	if (!iovram) {
 		NV_ERROR(drm, "Failed to map VRAM, "
 					"cannot save/restore VGA fonts.\n");

drivers/gpu/drm/nouveau/nouveau_abi16.c+4−3

 	struct nvif_device *device = &drm->client.device;
 	struct nvkm_gr *gr = nvxx_gr(device);
 	struct drm_nouveau_getparam *getparam = data;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	switch (getparam->param) {
 	case NOUVEAU_GETPARAM_CHIPSET_ID:
 		break;
 	case NOUVEAU_GETPARAM_PCI_VENDOR:
 		if (device->info.platform != NV_DEVICE_INFO_V0_SOC)
-			getparam->value = dev->pdev->vendor;
+			getparam->value = pdev->vendor;
 		else
 			getparam->value = 0;
 		break;
 	case NOUVEAU_GETPARAM_PCI_DEVICE:
 		if (device->info.platform != NV_DEVICE_INFO_V0_SOC)
-			getparam->value = dev->pdev->device;
+			getparam->value = pdev->device;
 		else
 			getparam->value = 0;
 		break;
 		case NV_DEVICE_INFO_V0_PCIE: getparam->value = 2; break;
 		case NV_DEVICE_INFO_V0_SOC : getparam->value = 3; break;
 		case NV_DEVICE_INFO_V0_IGP :
-			if (!pci_is_pcie(dev->pdev))
+			if (!pci_is_pcie(pdev))
 				getparam->value = 1;
 			else
 				getparam->value = 2;

drivers/gpu/drm/nouveau/nouveau_acpi.c+1−1

@@ -377,7 +377,7 @@ nouveau_acpi_edid(struct drm_device dev, struct drm_connector connector) · 376 unmodified lines
377	return NULL;	377	return NULL;
378	}	378	}
379		379
380	handle = ACPI_HANDLE(&dev->pdev->dev);	380	handle = ACPI_HANDLE(dev->dev);
381	if (!handle)	381	if (!handle)
382	return NULL;	382	return NULL;
383		383

drivers/gpu/drm/nouveau/nouveau_bios.c+8−3

 	struct nvbios *bios = &drm->vbios;
 	uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & DCB_OUTPUT_C ? 1 : 0);
 	uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
+#ifdef __powerpc__
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
+#endif
 	if (!bios->fp.xlated_entry || !sub || !scriptofs)
 		return -EINVAL;
 #ifdef __powerpc__
 	/* Powerbook specific quirks */
 	if (script == LVDS_RESET &&
-	    (dev->pdev->device == 0x0179 || dev->pdev->device == 0x0189 ||
+	    (pdev->device == 0x0179 || pdev->device == 0x0189 ||
-	     dev->pdev->device == 0x0329))
+	     pdev->device == 0x0329))
 		nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
 #endif
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nvbios *bios = &drm->vbios;
+	struct pci_dev *pdev;
 	int ret;
 	/* only relevant for PCI devices */
-	if (!dev->pdev)
+	if (!dev_is_pci(dev->dev))
 		return 0;
+	pdev = to_pci_dev(dev->dev);
 	if (!NVInitVBIOS(dev))
 		return -ENODEV;

drivers/gpu/drm/nouveau/nouveau_connector.c+6−4

 nouveau_connector_ddc_detect(struct drm_connector *connector)
 {
 	struct drm_device *dev = connector->dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct nouveau_encoder *nv_encoder = NULL, *found = NULL;
 	struct drm_encoder *encoder;
 	int ret;
 				break;
 			if (switcheroo_ddc)
-				vga_switcheroo_lock_ddc(dev->pdev);
+				vga_switcheroo_lock_ddc(pdev);
 			if (nvkm_probe_i2c(nv_encoder->i2c, 0x50))
 				found = nv_encoder;
 			if (switcheroo_ddc)
-				vga_switcheroo_unlock_ddc(dev->pdev);
+				vga_switcheroo_unlock_ddc(pdev);
 			break;
 		}
 	struct nouveau_connector *nv_connector = nouveau_connector(connector);
 	struct nouveau_drm *drm = nouveau_drm(connector->dev);
 	struct drm_device *dev = connector->dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	if (nv_connector->detected_encoder == nv_encoder)
 		return;
 		connector->doublescan_allowed = true;
 		if (drm->client.device.info.family == NV_DEVICE_INFO_V0_KELVIN ||
 		    (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
-		     (dev->pdev->device & 0x0ff0) != 0x0100 &&
+		     (pdev->device & 0x0ff0) != 0x0100 &&
-		     (dev->pdev->device & 0x0ff0) != 0x0150))
+		     (pdev->device & 0x0ff0) != 0x0150))
 			/* HW is broken */
 			connector->interlace_allowed = false;
 		else

drivers/gpu/drm/nouveau/nouveau_drm.c+2−3

 static u64
 nouveau_name(struct drm_device *dev)
 {
-	if (dev->pdev)
+	if (dev_is_pci(dev->dev))
-		return nouveau_pci_name(dev->pdev);
+		return nouveau_pci_name(to_pci_dev(dev->dev));
 	else
 		return nouveau_platform_name(to_platform_device(dev->dev));
 }
 	if (ret)
 		goto fail_drm;
-	drm_dev->pdev = pdev;
 	pci_set_drvdata(pdev, drm_dev);
 	ret = nouveau_drm_device_init(drm_dev);

drivers/gpu/drm/nouveau/nouveau_fbcon.c+4−2

 	NV_INFO(drm, "allocated %dx%d fb: 0x%llx, bo %p\n",
 		fb->width, fb->height, nvbo->offset, nvbo);
-	vga_switcheroo_client_fb_set(dev->pdev, info);
+	if (dev_is_pci(dev->dev))
+		vga_switcheroo_client_fb_set(to_pci_dev(dev->dev), info);
 	return 0;
 out_unlock:
 	int ret;
 	if (!dev->mode_config.num_crtc ||
-	    (dev->pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
+	    (to_pci_dev(dev->dev)->class >> 8) != PCI_CLASS_DISPLAY_VGA)
 		return 0;
 	fbcon = kzalloc(sizeof(struct nouveau_fbdev), GFP_KERNEL);

drivers/gpu/drm/nouveau/nouveau_vga.c+12−8

 {
 	struct drm_device *dev = drm->dev;
 	bool runtime = nouveau_pmops_runtime();
+	struct pci_dev *pdev;
 	/* only relevant for PCI devices */
-	if (!dev->pdev)
+	if (!dev_is_pci(dev->dev))
 		return;
+	pdev = to_pci_dev(dev->dev);
-	vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
+	vga_client_register(pdev, dev, NULL, nouveau_vga_set_decode);
 	/* don't register Thunderbolt eGPU with vga_switcheroo */
-	if (pci_is_thunderbolt_attached(dev->pdev))
+	if (pci_is_thunderbolt_attached(pdev))
 		return;
-	vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops, runtime);
+	vga_switcheroo_register_client(pdev, &nouveau_switcheroo_ops, runtime);
 	if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus())
 		vga_switcheroo_init_domain_pm_ops(drm->dev->dev, &drm->vga_pm_domain);
 {
 	struct drm_device *dev = drm->dev;
 	bool runtime = nouveau_pmops_runtime();
+	struct pci_dev *pdev;
 	/* only relevant for PCI devices */
-	if (!dev->pdev)
+	if (!dev_is_pci(dev->dev))
 		return;
+	pdev = to_pci_dev(dev->dev);
-	vga_client_register(dev->pdev, NULL, NULL, NULL);
+	vga_client_register(pdev, NULL, NULL, NULL);
-	if (pci_is_thunderbolt_attached(dev->pdev))
+	if (pci_is_thunderbolt_attached(pdev))
 		return;
-	vga_switcheroo_unregister_client(dev->pdev);
+	vga_switcheroo_unregister_client(pdev);
 	if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus())
 		vga_switcheroo_fini_domain_pm_ops(drm->dev->dev);
 }

drivers/gpu/drm/panel/panel-simple.c+2−0

@@ -2399,6 +2399,8 @@ static const struct panel_desc innolux_n116bge = { · 2398 unmodified lines
2399	.width = 256,	2399	.width = 256,
2400	.height = 144,	2400	.height = 144,
2401	},	2401	},
		2402	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
		2403	.connector_type = DRM_MODE_CONNECTOR_eDP,
2402	};	2404	};
2403		2405
2404	static const struct drm_display_mode innolux_n125hce_gn1_mode = {	2406	static const struct drm_display_mode innolux_n125hce_gn1_mode = {

drivers/gpu/drm/panfrost/panfrost_devfreq.c+1−0

@@ -76,6 +76,7 @@ static int panfrost_devfreq_get_dev_status(struct device *dev, · 75 unmodified lines
76	}	76	}
77		77
78	static struct devfreq_dev_profile panfrost_devfreq_profile = {	78	static struct devfreq_dev_profile panfrost_devfreq_profile = {
		79	.timer = DEVFREQ_TIMER_DELAYED,
79	.polling_ms = 50, /* ~3 frames */	80	.polling_ms = 50, /* ~3 frames */
80	.target = panfrost_devfreq_target,	81	.target = panfrost_devfreq_target,
81	.get_dev_status = panfrost_devfreq_get_dev_status,	82	.get_dev_status = panfrost_devfreq_get_dev_status,

drivers/gpu/drm/qxl/qxl_drv.c+1−1

@@ -163,7 +163,7 @@ DEFINE_DRM_GEM_FOPS(qxl_fops); · 162 unmodified lines
163		163
164	static int qxl_drm_freeze(struct drm_device *dev)	164	static int qxl_drm_freeze(struct drm_device *dev)
165	{	165	{
166	struct pci_dev *pdev = dev->pdev;	166	struct pci_dev *pdev = to_pci_dev(dev->dev);
167	struct qxl_device *qdev = to_qxl(dev);	167	struct qxl_device *qdev = to_qxl(dev);
168	int ret;	168	int ret;
169		169

drivers/gpu/drm/qxl/qxl_ioctl.c+2−1

 				  struct drm_file *file_priv)
 {
 	struct qxl_device *qdev = to_qxl(dev);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct drm_qxl_clientcap *param = data;
 	int byte, idx;
 	byte = param->index / 8;
 	idx = param->index % 8;
-	if (dev->pdev->revision < 4)
+	if (pdev->revision < 4)
 		return -ENOSYS;
 	if (byte >= 58)

drivers/gpu/drm/qxl/qxl_irq.c+2−1

 int qxl_irq_init(struct qxl_device *qdev)
 {
+	struct pci_dev *pdev = to_pci_dev(qdev->ddev.dev);
 	int ret;
 	init_waitqueue_head(&qdev->display_event);
 	atomic_set(&qdev->irq_received_cursor, 0);
 	atomic_set(&qdev->irq_received_io_cmd, 0);
 	qdev->irq_received_error = 0;
-	ret = drm_irq_install(&qdev->ddev, qdev->ddev.pdev->irq);
+	ret = drm_irq_install(&qdev->ddev, pdev->irq);
 	qdev->ram_header->int_mask = QXL_INTERRUPT_MASK;
 	if (unlikely(ret != 0)) {
 		DRM_ERROR("Failed installing irq: %d\n", ret);

drivers/gpu/drm/qxl/qxl_kms.c+0−1

@@ -111,7 +111,6 @@ int qxl_device_init(struct qxl_device *qdev, · 110 unmodified lines
111	{	111	{
112	int r, sb;	112	int r, sb;
113		113
114	qdev->ddev.pdev = pdev;
115	pci_set_drvdata(pdev, &qdev->ddev);	114	pci_set_drvdata(pdev, &qdev->ddev);
116		115
117	mutex_init(&qdev->gem.mutex);	116	mutex_init(&qdev->gem.mutex);

drivers/gpu/drm/r128/r128_ioc32.c+7−7

@@ -1,4 +1,4 @@
1	/**	1	/*
2	* \file r128_ioc32.c	2	* \file r128_ioc32.c
3	*	3	*
4	* 32-bit ioctl compatibility routines for the R128 DRM.	4	* 32-bit ioctl compatibility routines for the R128 DRM.
@@ -170,13 +170,13 @@ drm_ioctl_compat_t *r128_compat_ioctls[] = { · 165 unmodified lines
170	};	170	};
171		171
172	/**	172	/**
173	* Called whenever a 32-bit process running under a 64-bit kernel	173	* r128_compat_ioctl - Called whenever a 32-bit process running under
174	* performs an ioctl on /dev/dri/card<n>.	174	* a 64-bit kernel performs an ioctl on /dev/dri/card<n>.
175	*	175	*
176	* \param filp file pointer.	176	* @filp: file pointer.
177	* \param cmd command.	177	* @cmd: command.
178	* \param arg user argument.	178	* @arg: user argument.
179	* \return zero on success or negative number on failure.	179	* return: zero on success or negative number on failure.
180	*/	180	*/
181	long r128_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)	181	long r128_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
182	{	182	{

drivers/gpu/drm/radeon/atombios_encoders.c+3−3

@@ -2062,9 +2062,9 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder, · 2061 unmodified lines
2062	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);	2062	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2063		2063
2064	/* Funky macbooks */	2064	/* Funky macbooks */
2065	if ((dev->pdev->device == 0x71C5) &&	2065	if ((rdev->pdev->device == 0x71C5) &&
2066	(dev->pdev->subsystem_vendor == 0x106b) &&	2066	(rdev->pdev->subsystem_vendor == 0x106b) &&
2067	(dev->pdev->subsystem_device == 0x0080)) {	2067	(rdev->pdev->subsystem_device == 0x0080)) {
2068	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {	2068	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2069	uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);	2069	uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2070		2070

drivers/gpu/drm/radeon/r100.c+13−14

 void r100_set_common_regs(struct radeon_device *rdev)
 {
-	struct drm_device *dev = rdev->ddev;
 	bool force_dac2 = false;
 	u32 tmp;
 	 * don't report it in the bios connector
 	 * table.
 	 */
-	switch (dev->pdev->device) {
+	switch (rdev->pdev->device) {
 		/* RN50 */
 	case 0x515e:
 	case 0x5969:
 	case 0x5159:
 	case 0x515a:
 		/* DELL triple head servers */
-		if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
+		if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
-		    ((dev->pdev->subsystem_device == 0x016c) ||
+		    ((rdev->pdev->subsystem_device == 0x016c) ||
-		     (dev->pdev->subsystem_device == 0x016d) ||
+		     (rdev->pdev->subsystem_device == 0x016d) ||
-		     (dev->pdev->subsystem_device == 0x016e) ||
+		     (rdev->pdev->subsystem_device == 0x016e) ||
-		     (dev->pdev->subsystem_device == 0x016f) ||
+		     (rdev->pdev->subsystem_device == 0x016f) ||
-		     (dev->pdev->subsystem_device == 0x0170) ||
+		     (rdev->pdev->subsystem_device == 0x0170) ||
-		     (dev->pdev->subsystem_device == 0x017d) ||
+		     (rdev->pdev->subsystem_device == 0x017d) ||
-		     (dev->pdev->subsystem_device == 0x017e) ||
+		     (rdev->pdev->subsystem_device == 0x017e) ||
-		     (dev->pdev->subsystem_device == 0x0183) ||
+		     (rdev->pdev->subsystem_device == 0x0183) ||
-		     (dev->pdev->subsystem_device == 0x018a) ||
+		     (rdev->pdev->subsystem_device == 0x018a) ||
-		     (dev->pdev->subsystem_device == 0x019a)))
+		     (rdev->pdev->subsystem_device == 0x019a)))
 			force_dac2 = true;
 		break;
 	}
 			rdev->mc.real_vram_size = 8192 * 1024;
 			WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 		}
 		/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
 		 * Novell bug 204882 + along with lots of ubuntu ones
 		 */
 		if (rdev->mc.aper_size > config_aper_size)

drivers/gpu/drm/radeon/radeon.h+19−16

@@ -2313,6 +2313,9 @@ struct radeon_device { · 2312 unmodified lines
2313	struct device *dev;	2313	struct device *dev;
2314	struct drm_device *ddev;	2314	struct drm_device *ddev;
2315	struct pci_dev *pdev;	2315	struct pci_dev *pdev;
		2316	#ifdef __alpha__
		2317	struct pci_controller *hose;
		2318	#endif
2316	struct rw_semaphore exclusive_lock;	2319	struct rw_semaphore exclusive_lock;
2317	/* ASIC */	2320	/* ASIC */
2318	union radeon_asic_config config;	2321	union radeon_asic_config config;
@@ -2622,14 +2625,14 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); · 303 unmodified lines
2622	(rdev->family == CHIP_RV410) \|\| \	2625	(rdev->family == CHIP_RV410) \|\| \
2623	(rdev->family == CHIP_RS400) \|\| \	2626	(rdev->family == CHIP_RS400) \|\| \
2624	(rdev->family == CHIP_RS480))	2627	(rdev->family == CHIP_RS480))
2625	#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) \|\| \	2628	#define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) \|\| \
2626	(rdev->ddev->pdev->device == 0x9443) \|\| \	2629	(rdev->pdev->device == 0x9443) \|\| \
2627	(rdev->ddev->pdev->device == 0x944B) \|\| \	2630	(rdev->pdev->device == 0x944B) \|\| \
2628	(rdev->ddev->pdev->device == 0x9506) \|\| \	2631	(rdev->pdev->device == 0x9506) \|\| \
2629	(rdev->ddev->pdev->device == 0x9509) \|\| \	2632	(rdev->pdev->device == 0x9509) \|\| \
2630	(rdev->ddev->pdev->device == 0x950F) \|\| \	2633	(rdev->pdev->device == 0x950F) \|\| \
2631	(rdev->ddev->pdev->device == 0x689C) \|\| \	2634	(rdev->pdev->device == 0x689C) \|\| \
2632	(rdev->ddev->pdev->device == 0x689D))	2635	(rdev->pdev->device == 0x689D))
2633	#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))	2636	#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2634	#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) \|\| \	2637	#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) \|\| \
2635	(rdev->family == CHIP_RS690) \|\| \	2638	(rdev->family == CHIP_RS690) \|\| \
@@ -2652,14 +2655,14 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); · 16 unmodified lines
2652	#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) \|\| \	2655	#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) \|\| \
2653	(rdev->family == CHIP_MULLINS))	2656	(rdev->family == CHIP_MULLINS))
2654		2657
2655	#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) \|\| \	2658	#define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) \|\| \
2656	(rdev->ddev->pdev->device == 0x6850) \|\| \	2659	(rdev->pdev->device == 0x6850) \|\| \
2657	(rdev->ddev->pdev->device == 0x6858) \|\| \	2660	(rdev->pdev->device == 0x6858) \|\| \
2658	(rdev->ddev->pdev->device == 0x6859) \|\| \	2661	(rdev->pdev->device == 0x6859) \|\| \
2659	(rdev->ddev->pdev->device == 0x6840) \|\| \	2662	(rdev->pdev->device == 0x6840) \|\| \
2660	(rdev->ddev->pdev->device == 0x6841) \|\| \	2663	(rdev->pdev->device == 0x6841) \|\| \
2661	(rdev->ddev->pdev->device == 0x6842) \|\| \	2664	(rdev->pdev->device == 0x6842) \|\| \
2662	(rdev->ddev->pdev->device == 0x6843))	2665	(rdev->pdev->device == 0x6843))
2663		2666
2664	/*	2667	/*
2665	* BIOS helpers.	2668	* BIOS helpers.

drivers/gpu/drm/radeon/radeon_atombios.c+45−44

 				     uint16_t *line_mux,
 				     struct radeon_hpd *hpd)
 {
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
-	if ((dev->pdev->device == 0x791e) &&
+	if ((pdev->device == 0x791e) &&
-	    (dev->pdev->subsystem_vendor == 0x1043) &&
+	    (pdev->subsystem_vendor == 0x1043) &&
-	    (dev->pdev->subsystem_device == 0x826d)) {
+	    (pdev->subsystem_device == 0x826d)) {
 		if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 		    (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 			*connector_type = DRM_MODE_CONNECTOR_DVID;
 	}
 	/* Asrock RS600 board lists the DVI port as HDMI */
-	if ((dev->pdev->device == 0x7941) &&
+	if ((pdev->device == 0x7941) &&
-	    (dev->pdev->subsystem_vendor == 0x1849) &&
+	    (pdev->subsystem_vendor == 0x1849) &&
-	    (dev->pdev->subsystem_device == 0x7941)) {
+	    (pdev->subsystem_device == 0x7941)) {
 		if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 		    (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 			*connector_type = DRM_MODE_CONNECTOR_DVID;
 	}
 	/* MSI K9A2GM V2/V3 board has no HDMI or DVI */
-	if ((dev->pdev->device == 0x796e) &&
+	if ((pdev->device == 0x796e) &&
-	    (dev->pdev->subsystem_vendor == 0x1462) &&
+	    (pdev->subsystem_vendor == 0x1462) &&
-	    (dev->pdev->subsystem_device == 0x7302)) {
+	    (pdev->subsystem_device == 0x7302)) {
 		if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 		    (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 			return false;
 	}
 	/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
-	if ((dev->pdev->device == 0x7941) &&
+	if ((pdev->device == 0x7941) &&
-	    (dev->pdev->subsystem_vendor == 0x147b) &&
+	    (pdev->subsystem_vendor == 0x147b) &&
-	    (dev->pdev->subsystem_device == 0x2412)) {
+	    (pdev->subsystem_device == 0x2412)) {
 		if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 			return false;
 	}
 	/* Falcon NW laptop lists vga ddc line for LVDS */
-	if ((dev->pdev->device == 0x5653) &&
+	if ((pdev->device == 0x5653) &&
-	    (dev->pdev->subsystem_vendor == 0x1462) &&
+	    (pdev->subsystem_vendor == 0x1462) &&
-	    (dev->pdev->subsystem_device == 0x0291)) {
+	    (pdev->subsystem_device == 0x0291)) {
 		if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 			i2c_bus->valid = false;
 			*line_mux = 53;
 	}
 	/* HIS X1300 is DVI+VGA, not DVI+DVI */
-	if ((dev->pdev->device == 0x7146) &&
+	if ((pdev->device == 0x7146) &&
-	    (dev->pdev->subsystem_vendor == 0x17af) &&
+	    (pdev->subsystem_vendor == 0x17af) &&
-	    (dev->pdev->subsystem_device == 0x2058)) {
+	    (pdev->subsystem_device == 0x2058)) {
 		if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 			return false;
 	}
 	/* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
-	if ((dev->pdev->device == 0x7142) &&
+	if ((pdev->device == 0x7142) &&
-	    (dev->pdev->subsystem_vendor == 0x1458) &&
+	    (pdev->subsystem_vendor == 0x1458) &&
-	    (dev->pdev->subsystem_device == 0x2134)) {
+	    (pdev->subsystem_device == 0x2134)) {
 		if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 			return false;
 	}
 	/* Funky macbooks */
-	if ((dev->pdev->device == 0x71C5) &&
+	if ((pdev->device == 0x71C5) &&
-	    (dev->pdev->subsystem_vendor == 0x106b) &&
+	    (pdev->subsystem_vendor == 0x106b) &&
-	    (dev->pdev->subsystem_device == 0x0080)) {
+	    (pdev->subsystem_device == 0x0080)) {
 		if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 		    (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 			return false;
 	}
 	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
-	if ((dev->pdev->device == 0x9598) &&
+	if ((pdev->device == 0x9598) &&
-	    (dev->pdev->subsystem_vendor == 0x1043) &&
+	    (pdev->subsystem_vendor == 0x1043) &&
-	    (dev->pdev->subsystem_device == 0x01da)) {
+	    (pdev->subsystem_device == 0x01da)) {
 		if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 			*connector_type = DRM_MODE_CONNECTOR_DVII;
 		}
 	}
 	/* ASUS HD 3600 board lists the DVI port as HDMI */
-	if ((dev->pdev->device == 0x9598) &&
+	if ((pdev->device == 0x9598) &&
-	    (dev->pdev->subsystem_vendor == 0x1043) &&
+	    (pdev->subsystem_vendor == 0x1043) &&
-	    (dev->pdev->subsystem_device == 0x01e4)) {
+	    (pdev->subsystem_device == 0x01e4)) {
 		if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 			*connector_type = DRM_MODE_CONNECTOR_DVII;
 		}
 	}
 	/* ASUS HD 3450 board lists the DVI port as HDMI */
-	if ((dev->pdev->device == 0x95C5) &&
+	if ((pdev->device == 0x95C5) &&
-	    (dev->pdev->subsystem_vendor == 0x1043) &&
+	    (pdev->subsystem_vendor == 0x1043) &&
-	    (dev->pdev->subsystem_device == 0x01e2)) {
+	    (pdev->subsystem_device == 0x01e2)) {
 		if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 			*connector_type = DRM_MODE_CONNECTOR_DVII;
 		}
 	 * with different crtcs which isn't possible on the hardware
 	 * side and leaves no crtcs for LVDS or VGA.
 	 */
-	if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
+	if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
-	    (dev->pdev->subsystem_vendor == 0x1025) &&
+	    (pdev->subsystem_vendor == 0x1025) &&
-	    (dev->pdev->subsystem_device == 0x013c)) {
+	    (pdev->subsystem_device == 0x013c)) {
 		if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 		    (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 			/* actually it's a DVI-D port not DVI-I */
 	/* XFX Pine Group device rv730 reports no VGA DDC lines
 	 * even though they are wired up to record 0x93
 	 */
-	if ((dev->pdev->device == 0x9498) &&
+	if ((pdev->device == 0x9498) &&
-	    (dev->pdev->subsystem_vendor == 0x1682) &&
+	    (pdev->subsystem_vendor == 0x1682) &&
-	    (dev->pdev->subsystem_device == 0x2452) &&
+	    (pdev->subsystem_device == 0x2452) &&
 	    (i2c_bus->valid == false) &&
 	    !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 		struct radeon_device *rdev = dev->dev_private;
 	}
 	/* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
-	if (((dev->pdev->device == 0x9802) ||
+	if (((pdev->device == 0x9802) ||
-	     (dev->pdev->device == 0x9805) ||
+	     (pdev->device == 0x9805) ||
-	     (dev->pdev->device == 0x9806)) &&
+	     (pdev->device == 0x9806)) &&
-	    (dev->pdev->subsystem_vendor == 0x1734) &&
+	    (pdev->subsystem_vendor == 0x1734) &&
-	    (dev->pdev->subsystem_device == 0x11bd)) {
+	    (pdev->subsystem_device == 0x11bd)) {
 		if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 			*connector_type = DRM_MODE_CONNECTOR_DVII;
 			*line_mux = 0x3103;

drivers/gpu/drm/radeon/radeon_bios.c+3−3

@@ -528,7 +528,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) · 527 unmodified lines
528	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);	528	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
529	fp2_gen_cntl = 0;	529	fp2_gen_cntl = 0;
530		530
531	if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {	531	if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
532	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);	532	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
533	}	533	}
534		534
@@ -565,7 +565,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) · 30 unmodified lines
565	(RADEON_CRTC_SYNC_TRISTAT \|	565	(RADEON_CRTC_SYNC_TRISTAT \|
566	RADEON_CRTC_DISPLAY_DIS)));	566	RADEON_CRTC_DISPLAY_DIS)));
567		567
568	if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {	568	if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
569	WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));	569	WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
570	}	570	}
571		571
@@ -583,7 +583,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) · 11 unmodified lines
583	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);	583	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
584	}	584	}
585	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);	585	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
586	if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {	586	if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
587	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);	587	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
588	}	588	}
589	return r;	589	return r;

drivers/gpu/drm/radeon/radeon_combios.c+29−26

 	/* quirks */
 	/* Radeon 7000 (RV100) */
-	if (((dev->pdev->device == 0x5159) &&
+	if (((rdev->pdev->device == 0x5159) &&
-	    (dev->pdev->subsystem_vendor == 0x174B) &&
+	    (rdev->pdev->subsystem_vendor == 0x174B) &&
-	    (dev->pdev->subsystem_device == 0x7c28)) ||
+	    (rdev->pdev->subsystem_device == 0x7c28)) ||
 	/* Radeon 9100 (R200) */
-	   ((dev->pdev->device == 0x514D) &&
+	   ((rdev->pdev->device == 0x514D) &&
-	    (dev->pdev->subsystem_vendor == 0x174B) &&
+	    (rdev->pdev->subsystem_vendor == 0x174B) &&
-	    (dev->pdev->subsystem_device == 0x7149))) {
+	    (rdev->pdev->subsystem_device == 0x7149))) {
 		/* vbios value is bad, use the default */
 		found = 0;
 	}
 				       struct radeon_i2c_bus_rec *ddc_i2c,
 				       struct radeon_hpd *hpd)
 {
+	struct radeon_device *rdev = dev->dev_private;
 	/* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
 	   one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
-	if (dev->pdev->device == 0x515e &&
+	if (rdev->pdev->device == 0x515e &&
-	    dev->pdev->subsystem_vendor == 0x1014) {
+	    rdev->pdev->subsystem_vendor == 0x1014) {
 		if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
 		    ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
 			return false;
 	}
 	/* X300 card with extra non-existent DVI port */
-	if (dev->pdev->device == 0x5B60 &&
+	if (rdev->pdev->device == 0x5B60 &&
-	    dev->pdev->subsystem_vendor == 0x17af &&
+	    rdev->pdev->subsystem_vendor == 0x17af &&
-	    dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
+	    rdev->pdev->subsystem_device == 0x201e && bios_index == 2) {
 		if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
 			return false;
 	}
 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
 {
+	struct radeon_device *rdev = dev->dev_private;
 	/* Acer 5102 has non-existent TV port */
-	if (dev->pdev->device == 0x5975 &&
+	if (rdev->pdev->device == 0x5975 &&
-	    dev->pdev->subsystem_vendor == 0x1025 &&
+	    rdev->pdev->subsystem_vendor == 0x1025 &&
-	    dev->pdev->subsystem_device == 0x009f)
+	    rdev->pdev->subsystem_device == 0x009f)
 		return false;
 	/* HP dc5750 has non-existent TV port */
-	if (dev->pdev->device == 0x5974 &&
+	if (rdev->pdev->device == 0x5974 &&
-	    dev->pdev->subsystem_vendor == 0x103c &&
+	    rdev->pdev->subsystem_vendor == 0x103c &&
-	    dev->pdev->subsystem_device == 0x280a)
+	    rdev->pdev->subsystem_device == 0x280a)
 		return false;
 	/* MSI S270 has non-existent TV port */
-	if (dev->pdev->device == 0x5955 &&
+	if (rdev->pdev->device == 0x5955 &&
-	    dev->pdev->subsystem_vendor == 0x1462 &&
+	    rdev->pdev->subsystem_vendor == 0x1462 &&
-	    dev->pdev->subsystem_device == 0x0131)
+	    rdev->pdev->subsystem_device == 0x0131)
 		return false;
 	return true;
 				/* RV100 board with external TDMS bit mis-set.
 				 * Actually uses internal TMDS, clear the bit.
 				 */
-				if (dev->pdev->device == 0x5159 &&
+				if (rdev->pdev->device == 0x5159 &&
-				    dev->pdev->subsystem_vendor == 0x1014 &&
+				    rdev->pdev->subsystem_vendor == 0x1014 &&
-				    dev->pdev->subsystem_device == 0x029A) {
+				    rdev->pdev->subsystem_device == 0x029A) {
 					tmp &= ~(1 << 4);
 				}
 				if ((tmp >> 4) & 0x1) {
 		/* boards with a thermal chip, but no overdrive table */
 		/* Asus 9600xt has an f75375 on the monid bus */
-		if ((dev->pdev->device == 0x4152) &&
+		if ((rdev->pdev->device == 0x4152) &&
-		    (dev->pdev->subsystem_vendor == 0x1043) &&
+		    (rdev->pdev->subsystem_vendor == 0x1043) &&
-		    (dev->pdev->subsystem_device == 0xc002)) {
+		    (rdev->pdev->subsystem_device == 0xc002)) {
 			i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 			rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
 			if (rdev->pm.i2c_bus) {

drivers/gpu/drm/radeon/radeon_cs.c+1−2

@@ -130,8 +130,7 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) · 129 unmodified lines
130	* IGP chips to avoid image corruptions	130	* IGP chips to avoid image corruptions
131	*/	131	*/
132	if (p->ring == R600_RING_TYPE_UVD_INDEX &&	132	if (p->ring == R600_RING_TYPE_UVD_INDEX &&
133	(i <= 0 \|\| pci_find_capability(p->rdev->ddev->pdev,	133	(i <= 0 \|\| pci_find_capability(p->rdev->pdev, PCI_CAP_ID_AGP) \|\|
134	PCI_CAP_ID_AGP) \|\|
135	p->rdev->family == CHIP_RS780 \|\|	134	p->rdev->family == CHIP_RS780 \|\|
136	p->rdev->family == CHIP_RS880)) {	135	p->rdev->family == CHIP_RS880)) {
137		136

drivers/gpu/drm/radeon/radeon_device.c+10−7

 		       bool fbcon, bool freeze)
 {
 	struct radeon_device *rdev;
+	struct pci_dev *pdev;
 	struct drm_crtc *crtc;
 	struct drm_connector *connector;
 	int i, r;
 	}
 	rdev = dev->dev_private;
+	pdev = to_pci_dev(dev->dev);
 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 	radeon_agp_suspend(rdev);
-	pci_save_state(dev->pdev);
+	pci_save_state(pdev);
 	if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
 		rdev->asic->asic_reset(rdev, true);
-		pci_restore_state(dev->pdev);
+		pci_restore_state(pdev);
 	} else if (suspend) {
 		/* Shut down the device */
-		pci_disable_device(dev->pdev);
+		pci_disable_device(pdev);
-		pci_set_power_state(dev->pdev, PCI_D3hot);
+		pci_set_power_state(pdev, PCI_D3hot);
 	}
 	if (fbcon) {
 {
 	struct drm_connector *connector;
 	struct radeon_device *rdev = dev->dev_private;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct drm_crtc *crtc;
 	int r;
 		console_lock();
 	}
 	if (resume) {
-		pci_set_power_state(dev->pdev, PCI_D0);
+		pci_set_power_state(pdev, PCI_D0);
-		pci_restore_state(dev->pdev);
+		pci_restore_state(pdev);
-		if (pci_enable_device(dev->pdev)) {
+		if (pci_enable_device(pdev)) {
 			if (fbcon)
 				console_unlock();
 			return -1;

drivers/gpu/drm/radeon/radeon_display.c+1−1

@@ -1317,7 +1317,7 @@ radeon_user_framebuffer_create(struct drm_device *dev, · 1316 unmodified lines
1317		1317
1318	obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);	1318	obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1319	if (obj == NULL) {	1319	if (obj == NULL) {
1320	dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "	1320	dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1321	"can't create framebuffer\n", mode_cmd->handles[0]);	1321	"can't create framebuffer\n", mode_cmd->handles[0]);
1322	return ERR_PTR(-ENOENT);	1322	return ERR_PTR(-ENOENT);
1323	}	1323	}

drivers/gpu/drm/radeon/radeon_drv.c+1−6

 	if (ret)
 		goto err_free;
-	dev->pdev = pdev;
-#ifdef __alpha__
-	dev->hose = pdev->sysdata;
-#endif
 	pci_set_drvdata(pdev, dev);
-	if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP))
+	if (pci_find_capability(pdev, PCI_CAP_ID_AGP))
 		dev->agp = drm_agp_init(dev);
 	if (dev->agp) {
 		dev->agp->agp_mtrr = arch_phys_wc_add(

drivers/gpu/drm/radeon/radeon_fb.c+1−1

@@ -290,7 +290,7 @@ static int radeonfb_create(struct drm_fb_helper *helper, · 289 unmodified lines
290	DRM_INFO("fb depth is %d\n", fb->format->depth);	290	DRM_INFO("fb depth is %d\n", fb->format->depth);
291	DRM_INFO(" pitch is %d\n", fb->pitches[0]);	291	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
292		292
293	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);	293	vga_switcheroo_client_fb_set(rdev->pdev, info);
294	return 0;	294	return 0;
295		295
296	out:	296	out:

drivers/gpu/drm/radeon/radeon_gem.c+3−3

@@ -651,7 +651,7 @@ int radeon_gem_va_ioctl(struct drm_device dev, void data, · 650 unmodified lines
651	}	651	}
652		652
653	if (args->offset < RADEON_VA_RESERVED_SIZE) {	653	if (args->offset < RADEON_VA_RESERVED_SIZE) {
654	dev_err(&dev->pdev->dev,	654	dev_err(dev->dev,
655	"offset 0x%lX is in reserved area 0x%X\n",	655	"offset 0x%lX is in reserved area 0x%X\n",
656	(unsigned long)args->offset,	656	(unsigned long)args->offset,
657	RADEON_VA_RESERVED_SIZE);	657	RADEON_VA_RESERVED_SIZE);
@@ -665,7 +665,7 @@ int radeon_gem_va_ioctl(struct drm_device dev, void data, · 7 unmodified lines
665	*/	665	*/
666	invalid_flags = RADEON_VM_PAGE_VALID \| RADEON_VM_PAGE_SYSTEM;	666	invalid_flags = RADEON_VM_PAGE_VALID \| RADEON_VM_PAGE_SYSTEM;
667	if ((args->flags & invalid_flags)) {	667	if ((args->flags & invalid_flags)) {
668	dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",	668	dev_err(dev->dev, "invalid flags 0x%08X vs 0x%08X\n",
669	args->flags, invalid_flags);	669	args->flags, invalid_flags);
670	args->operation = RADEON_VA_RESULT_ERROR;	670	args->operation = RADEON_VA_RESULT_ERROR;
671	return -EINVAL;	671	return -EINVAL;
@@ -676,7 +676,7 @@ int radeon_gem_va_ioctl(struct drm_device dev, void data, · 4 unmodified lines
676	case RADEON_VA_UNMAP:	676	case RADEON_VA_UNMAP:
677	break;	677	break;
678	default:	678	default:
679	dev_err(&dev->pdev->dev, "unsupported operation %d\n",	679	dev_err(dev->dev, "unsupported operation %d\n",
680	args->operation);	680	args->operation);
681	args->operation = RADEON_VA_RESULT_ERROR;	681	args->operation = RADEON_VA_RESULT_ERROR;
682	return -EINVAL;	682	return -EINVAL;

drivers/gpu/drm/radeon/radeon_i2c.c+1−1

@@ -919,7 +919,7 @@ struct radeon_i2c_chan radeon_i2c_create(struct drm_device dev, · 918 unmodified lines
919	i2c->rec = *rec;	919	i2c->rec = *rec;
920	i2c->adapter.owner = THIS_MODULE;	920	i2c->adapter.owner = THIS_MODULE;
921	i2c->adapter.class = I2C_CLASS_DDC;	921	i2c->adapter.class = I2C_CLASS_DDC;
922	i2c->adapter.dev.parent = &dev->pdev->dev;	922	i2c->adapter.dev.parent = dev->dev;
923	i2c->dev = dev;	923	i2c->dev = dev;
924	i2c_set_adapdata(&i2c->adapter, i2c);	924	i2c_set_adapdata(&i2c->adapter, i2c);
925	mutex_init(&i2c->mutex);	925	mutex_init(&i2c->mutex);

drivers/gpu/drm/radeon/radeon_irq_kms.c+1−1

@@ -314,7 +314,7 @@ int radeon_irq_kms_init(struct radeon_device *rdev) · 313 unmodified lines
314	INIT_WORK(&rdev->audio_work, r600_audio_update_hdmi);	314	INIT_WORK(&rdev->audio_work, r600_audio_update_hdmi);
315		315
316	rdev->irq.installed = true;	316	rdev->irq.installed = true;
317	r = drm_irq_install(rdev->ddev, rdev->ddev->pdev->irq);	317	r = drm_irq_install(rdev->ddev, rdev->pdev->irq);
318	if (r) {	318	if (r) {
319	rdev->irq.installed = false;	319	rdev->irq.installed = false;
320	flush_delayed_work(&rdev->hotplug_work);	320	flush_delayed_work(&rdev->hotplug_work);

drivers/gpu/drm/radeon/radeon_kms.c+14−10

 	}
 	radeon_acpi_fini(rdev);
 	radeon_modeset_fini(rdev);
 	radeon_device_fini(rdev);
  */
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
 {
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct radeon_device *rdev;
 	int r, acpi_status;
 	}
 	dev->dev_private = (void *)rdev;
+#ifdef __alpha__
+	rdev->hose = pdev->sysdata;
+#endif
 	/* update BUS flag */
-	if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) {
+	if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) {
 		flags |= RADEON_IS_AGP;
-	} else if (pci_is_pcie(dev->pdev)) {
+	} else if (pci_is_pcie(pdev)) {
 		flags |= RADEON_IS_PCIE;
 	} else {
 		flags |= RADEON_IS_PCI;
 	if ((radeon_runtime_pm != 0) &&
 	    radeon_has_atpx() &&
 	    ((flags & RADEON_IS_IGP) == 0) &&
-	    !pci_is_thunderbolt_attached(dev->pdev))
+	    !pci_is_thunderbolt_attached(pdev))
 		flags |= RADEON_IS_PX;
 	/* radeon_device_init should report only fatal error
 	 * properly initialize the GPU MC controller and permit
 	 * VRAM allocation
 	 */
-	r = radeon_device_init(rdev, dev, dev->pdev, flags);
+	r = radeon_device_init(rdev, dev, pdev, flags);
 	if (r) {
-		dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
+		dev_err(dev->dev, "Fatal error during GPU init\n");
 		goto out;
 	}
 	 */
 	r = radeon_modeset_init(rdev);
 	if (r)
-		dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
+		dev_err(dev->dev, "Fatal error during modeset init\n");
 	/* Call ACPI methods: require modeset init
 	 * but failure is not fatal
 	if (!r) {
 		acpi_status = radeon_acpi_init(rdev);
 		if (acpi_status)
-		dev_dbg(&dev->pdev->dev,
+		dev_dbg(dev->dev, "Error during ACPI methods call\n");
-				"Error during ACPI methods call\n");
 	}
 	if (radeon_is_px(dev)) {
 	switch (info->request) {
 	case RADEON_INFO_DEVICE_ID:
-		*value = dev->pdev->device;
+		*value = to_pci_dev(dev->dev)->device;
 		break;
 	case RADEON_INFO_NUM_GB_PIPES:
 		*value = rdev->num_gb_pipes;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c+3−3

@@ -974,9 +974,9 @@ static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, · 973 unmodified lines
974		974
975	/* XXX: these are oem specific */	975	/* XXX: these are oem specific */
976	if (ASIC_IS_R300(rdev)) {	976	if (ASIC_IS_R300(rdev)) {
977	if ((dev->pdev->device == 0x4850) &&	977	if ((rdev->pdev->device == 0x4850) &&
978	(dev->pdev->subsystem_vendor == 0x1028) &&	978	(rdev->pdev->subsystem_vendor == 0x1028) &&
979	(dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */	979	(rdev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
980	fp2_gen_cntl \|= R300_FP2_DVO_CLOCK_MODE_SINGLE;	980	fp2_gen_cntl \|= R300_FP2_DVO_CLOCK_MODE_SINGLE;
981	else	981	else
982	fp2_gen_cntl \|= RADEON_FP2_PAD_FLOP_EN \| R300_FP2_DVO_CLOCK_MODE_SINGLE;	982	fp2_gen_cntl \|= RADEON_FP2_PAD_FLOP_EN \| R300_FP2_DVO_CLOCK_MODE_SINGLE;

drivers/gpu/drm/radeon/radeon_ttm.c+1−1

@@ -324,7 +324,7 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso · 323 unmodified lines
324	* access, as done in ttm_bo_vm_fault().	324	* access, as done in ttm_bo_vm_fault().
325	*/	325	*/
326	mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) +	326	mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) +
327	rdev->ddev->hose->dense_mem_base;	327	rdev->hose->dense_mem_base;
328	#endif	328	#endif
329	break;	329	break;
330	default:	330	default:

drivers/gpu/drm/radeon/rs780_dpm.c+3−4

 static void rs780_voltage_scaling_init(struct radeon_device *rdev)
 {
 	struct igp_power_info *pi = rs780_get_pi(rdev);
-	struct drm_device *dev = rdev->ddev;
 	u32 fv_throt_pwm_fb_div_range[3];
 	u32 fv_throt_pwm_range[4];
-	if (dev->pdev->device == 0x9614) {
+	if (rdev->pdev->device == 0x9614) {
 		fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
 		fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
 		fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
-	} else if ((dev->pdev->device == 0x9714) ||
+	} else if ((rdev->pdev->device == 0x9714) ||
-		   (dev->pdev->device == 0x9715)) {
+		   (rdev->pdev->device == 0x9715)) {
 		fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
 		fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
 		fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;

drivers/gpu/drm/scheduler/sched_main.c+3−0

@@ -899,6 +899,9 @@ void drm_sched_fini(struct drm_gpu_scheduler *sched) · 898 unmodified lines
899	if (sched->thread)	899	if (sched->thread)
900	kthread_stop(sched->thread);	900	kthread_stop(sched->thread);
901		901
		902	/* Confirm no work left behind accessing device structures */
		903	cancel_delayed_work_sync(&sched->work_tdr);
		904
902	sched->ready = false;	905	sched->ready = false;
903	}	906	}
904	EXPORT_SYMBOL(drm_sched_fini);	907	EXPORT_SYMBOL(drm_sched_fini);

drivers/gpu/drm/sun4i/sun4i_tcon.c+2−19

@@ -569,30 +569,13 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, · 568 unmodified lines
569	if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)	569	if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
570	val \|= SUN4I_TCON0_IO_POL_DE_NEGATIVE;	570	val \|= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
571		571
572	/*
573	* On A20 and similar SoCs, the only way to achieve Positive Edge
574	* (Rising Edge), is setting dclk clock phase to 2/3(240°).
575	* By default TCON works in Negative Edge(Falling Edge),
576	* this is why phase is set to 0 in that case.
577	* Unfortunately there's no way to logically invert dclk through
578	* IO_POL register.
579	* The only acceptable way to work, triple checked with scope,
580	* is using clock phase set to 0° for Negative Edge and set to 240°
581	* for Positive Edge.
582	* On A33 and similar SoCs there would be a 90° phase option,
583	* but it divides also dclk by 2.
584	* Following code is a way to avoid quirks all around TCON
585	* and DOTCLOCK drivers.
586	*/
587	if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
588	clk_set_phase(tcon->dclk, 240);
589
590	if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)	572	if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
591	clk_set_phase(tcon->dclk, 0);	573	val \|= SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE;
592		574
593	regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,	575	regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
594	SUN4I_TCON0_IO_POL_HSYNC_POSITIVE \|	576	SUN4I_TCON0_IO_POL_HSYNC_POSITIVE \|
595	SUN4I_TCON0_IO_POL_VSYNC_POSITIVE \|	577	SUN4I_TCON0_IO_POL_VSYNC_POSITIVE \|
		578	SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE \|
596	SUN4I_TCON0_IO_POL_DE_NEGATIVE,	579	SUN4I_TCON0_IO_POL_DE_NEGATIVE,
597	val);	580	val);
598		581

drivers/gpu/drm/sun4i/sun4i_tcon.h+1−0

@@ -113,6 +113,7 @@ · 112 unmodified lines
113	#define SUN4I_TCON0_IO_POL_REG 0x88	113	#define SUN4I_TCON0_IO_POL_REG 0x88
114	#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)	114	#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
115	#define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)	115	#define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
		116	#define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE BIT(26)
116	#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)	117	#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
117	#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)	118	#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
118		119

drivers/gpu/drm/sun4i/sun8i_csc.c+44−65

 	},
 };
-static const u32 yvu2rgb[2][2][12] = {
-	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
-		[DRM_COLOR_YCBCR_BT601] = {
-			0x000004A8, 0x00000662, 0x00000000, 0xFFFC8451,
-			0x000004A8, 0xFFFFFCC0, 0xFFFFFE6F, 0x00021E4D,
-			0x000004A8, 0x00000000, 0x00000811, 0xFFFBACA9,
-		},
-		[DRM_COLOR_YCBCR_BT709] = {
-			0x000004A8, 0x0000072B, 0x00000000, 0xFFFC1F99,
-			0x000004A8, 0xFFFFFDDF, 0xFFFFFF26, 0x00013383,
-			0x000004A8, 0x00000000, 0x00000873, 0xFFFB7BEF,
-		}
-	},
-	[DRM_COLOR_YCBCR_FULL_RANGE] = {
-		[DRM_COLOR_YCBCR_BT601] = {
-			0x00000400, 0x0000059B, 0x00000000, 0xFFFD322E,
-			0x00000400, 0xFFFFFD25, 0xFFFFFEA0, 0x00021DD5,
-			0x00000400, 0x00000000, 0x00000716, 0xFFFC74BD,
-		},
-		[DRM_COLOR_YCBCR_BT709] = {
-			0x00000400, 0x0000064C, 0x00000000, 0xFFFCD9B4,
-			0x00000400, 0xFFFFFE21, 0xFFFFFF41, 0x00014F96,
-			0x00000400, 0x00000000, 0x0000076C, 0xFFFC49EF,
-		}
-	},
-};
 /*
  * DE3 has a bit different CSC units. Factors are in two's complement format.
  * First three factors in a row are multiplication factors which have 17 bits
  * c20 c21 c22 [d2 const2]
  */
-static const u32 yuv2rgb_de3[2][2][12] = {
+static const u32 yuv2rgb_de3[2][3][12] = {
 	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 		[DRM_COLOR_YCBCR_BT601] = {
 			0x0002542A, 0x00000000, 0x0003312A, 0xFFC00000,
 			0x0002542A, 0x00000000, 0x000395E2, 0xFFC00000,
 			0x0002542A, 0xFFFF92D2, 0xFFFEEF27, 0xFE000000,
 			0x0002542A, 0x0004398C, 0x00000000, 0xFE000000,
+		},
+		[DRM_COLOR_YCBCR_BT2020] = {
+			0x0002542A, 0x00000000, 0x00035B7B, 0xFFC00000,
+			0x0002542A, 0xFFFFA017, 0xFFFEB2FC, 0xFE000000,
+			0x0002542A, 0x00044896, 0x00000000, 0xFE000000,
 		}
 	},
 	[DRM_COLOR_YCBCR_FULL_RANGE] = {
 			0x00020000, 0x00000000, 0x0003264C, 0x00000000,
 			0x00020000, 0xFFFFA018, 0xFFFF1053, 0xFE000000,
 			0x00020000, 0x0003B611, 0x00000000, 0xFE000000,
-		}
-	},
-};
-static const u32 yvu2rgb_de3[2][2][12] = {
-	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
-		[DRM_COLOR_YCBCR_BT601] = {
-			0x0002542A, 0x0003312A, 0x00000000, 0xFFC00000,
-			0x0002542A, 0xFFFE5FC3, 0xFFFF376B, 0xFE000000,
-			0x0002542A, 0x00000000, 0x000408D2, 0xFE000000,
 		},
-		[DRM_COLOR_YCBCR_BT709] = {
+		[DRM_COLOR_YCBCR_BT2020] = {
-			0x0002542A, 0x000395E2, 0x00000000, 0xFFC00000,
+			0x00020000, 0x00000000, 0x0002F2FE, 0x00000000,
-			0x0002542A, 0xFFFEEF27, 0xFFFF92D2, 0xFE000000,
+			0x00020000, 0xFFFFABC0, 0xFFFEDB78, 0xFE000000,
-			0x0002542A, 0x00000000, 0x0004398C, 0xFE000000,
+			0x00020000, 0x0003C346, 0x00000000, 0xFE000000,
-		}
-	},
-	[DRM_COLOR_YCBCR_FULL_RANGE] = {
-		[DRM_COLOR_YCBCR_BT601] = {
-			0x00020000, 0x0002CDD2, 0x00000000, 0x00000000,
-			0x00020000, 0xFFFE925D, 0xFFFF4FCE, 0xFE000000,
-			0x00020000, 0x00000000, 0x00038B43, 0xFE000000,
-		},
-		[DRM_COLOR_YCBCR_BT709] = {
-			0x00020000, 0x0003264C, 0x00000000, 0x00000000,
-			0x00020000, 0xFFFF1053, 0xFFFFA018, 0xFE000000,
-			0x00020000, 0x00000000, 0x0003B611, 0xFE000000,
 		}
 	},
 };
 {
 	const u32 *table;
 	u32 base_reg;
+	int i;
+	table = yuv2rgb[range][encoding];
 	switch (mode) {
 	case SUN8I_CSC_MODE_YUV2RGB:
-		table = yuv2rgb[range][encoding];
+		base_reg = SUN8I_CSC_COEFF(base, 0);
+		regmap_bulk_write(map, base_reg, table, 12);
 		break;
 	case SUN8I_CSC_MODE_YVU2RGB:
-		table = yvu2rgb[range][encoding];
+		for (i = 0; i < 12; i++) {
+			if ((i & 3) == 1)
+				base_reg = SUN8I_CSC_COEFF(base, i + 1);
+			else if ((i & 3) == 2)
+				base_reg = SUN8I_CSC_COEFF(base, i - 1);
+			else
+				base_reg = SUN8I_CSC_COEFF(base, i);
+			regmap_write(map, base_reg, table[i]);
+		}
 		break;
 	default:
 		DRM_WARN("Wrong CSC mode specified.\n");
 		return;
 	}
-	base_reg = SUN8I_CSC_COEFF(base, 0);
-	regmap_bulk_write(map, base_reg, table, 12);
 }
 static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
 					    enum drm_color_range range)
 {
 	const u32 *table;
-	u32 base_reg;
+	u32 addr;
+	int i;
+	table = yuv2rgb_de3[range][encoding];
 	switch (mode) {
 	case SUN8I_CSC_MODE_YUV2RGB:
-		table = yuv2rgb_de3[range][encoding];
+		addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0);
+		regmap_bulk_write(map, addr, table, 12);
 		break;
 	case SUN8I_CSC_MODE_YVU2RGB:
-		table = yvu2rgb_de3[range][encoding];
+		for (i = 0; i < 12; i++) {
+			if ((i & 3) == 1)
+				addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE,
+								    layer,
+								    i + 1);
+			else if ((i & 3) == 2)
+				addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE,
+								    layer,
+								    i - 1);
+			else
+				addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE,
+								    layer, i);
+			regmap_write(map, addr, table[i]);
+		}
 		break;
 	default:
 		DRM_WARN("Wrong CSC mode specified.\n");
 		return;
 	}
-	base_reg = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0, 0);
-	regmap_bulk_write(map, base_reg, table, 12);
 }
 static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable)

drivers/gpu/drm/sun4i/sun8i_mixer.h+2−4

 #define SUN8I_MIXER_BLEND_CK_MIN(base, x)	((base) + 0xe0 + 0x04 * (x))
 #define SUN8I_MIXER_BLEND_OUTCTL(base)		((base) + 0xfc)
 #define SUN50I_MIXER_BLEND_CSC_CTL(base)	((base) + 0x100)
-#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \
+#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x) \
-	((base) + 0x110 + (layer) * 0x30 +  (x) * 0x10 + 4 * (y))
+	((base) + 0x110 + (layer) * 0x30 +  (x) * 4)
-#define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \
-	((base) + 0x110 + (layer) * 0x30 +  (i) * 0x10 + 0x0c)
 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK	GENMASK(12, 8)
 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe)	BIT(8 + pipe)

drivers/gpu/drm/sun4i/sun8i_vi_layer.c+2−0

@@ -543,6 +543,8 @@ struct sun8i_vi_layer sun8i_vi_layer_init_one(struct drm_device drm, · 542 unmodified lines
543		543
544	supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) \|	544	supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) \|
545	BIT(DRM_COLOR_YCBCR_BT709);	545	BIT(DRM_COLOR_YCBCR_BT709);
		546	if (mixer->cfg->is_de3)
		547	supported_encodings \|= BIT(DRM_COLOR_YCBCR_BT2020);
546		548
547	supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) \|	549	supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) \|
548	BIT(DRM_COLOR_YCBCR_FULL_RANGE);	550	BIT(DRM_COLOR_YCBCR_FULL_RANGE);

drivers/gpu/drm/tiny/cirrus.c+0−1

@@ -602,7 +602,6 @@ static int cirrus_pci_probe(struct pci_dev *pdev, · 601 unmodified lines
602		602
603	drm_mode_config_reset(dev);	603	drm_mode_config_reset(dev);
604		604
605	dev->pdev = pdev;
606	pci_set_drvdata(pdev, dev);	605	pci_set_drvdata(pdev, dev);
607	ret = drm_dev_register(dev, 0);	606	ret = drm_dev_register(dev, 0);
608	if (ret)	607	if (ret)

drivers/gpu/drm/ttm/ttm_bo.c+3−1

@@ -138,8 +138,10 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo, · 137 unmodified lines
138		138
139	dma_resv_assert_held(bo->base.resv);	139	dma_resv_assert_held(bo->base.resv);
140		140
141	if (bo->pin_count)	141	if (bo->pin_count) {
		142	ttm_bo_del_from_lru(bo);
142	return;	143	return;
		144	}
143		145
144	man = ttm_manager_type(bdev, mem->mem_type);	146	man = ttm_manager_type(bdev, mem->mem_type);
145	list_move_tail(&bo->lru, &man->lru[bo->priority]);	147	list_move_tail(&bo->lru, &man->lru[bo->priority]);

drivers/gpu/drm/v3d/v3d_drv.c+2−2

@@ -232,8 +232,8 @@ static int v3d_platform_drm_probe(struct platform_device *pdev) · 231 unmodified lines
232	return ret;	232	return ret;
233		233
234	mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);	234	mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
235	dev->coherent_dma_mask =	235	dma_set_mask_and_coherent(dev,
236	DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));	236	DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)));
237	v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);	237	v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
238		238
239	ident1 = V3D_READ(V3D_HUB_IDENT1);	239	ident1 = V3D_READ(V3D_HUB_IDENT1);

drivers/gpu/drm/v3d/v3d_irq.c+2−5

 		};
 		const char *client = "?";
-		V3D_WRITE(V3D_MMU_CTL,
+		V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
-			  V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |
-						   V3D_MMU_CTL_PT_INVALID |
-						   V3D_MMU_CTL_WRITE_VIOLATION));
 		if (v3d->ver >= 41) {
 			axi_id = axi_id >> 5;
 		V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
 	V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
-	irq1 = platform_get_irq(v3d_to_pdev(v3d), 1);
+	irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);
 	if (irq1 == -EPROBE_DEFER)
 		return irq1;
 	if (irq1 > 0) {

drivers/gpu/drm/vboxvideo/vbox_drv.c+6−5

 	if (IS_ERR(vbox))
 		return PTR_ERR(vbox);
-	vbox->ddev.pdev = pdev;
 	pci_set_drvdata(pdev, vbox);
 	mutex_init(&vbox->hw_mutex);
 static int vbox_pm_suspend(struct device *dev)
 {
 	struct vbox_private *vbox = dev_get_drvdata(dev);
+	struct pci_dev *pdev = to_pci_dev(dev);
 	int error;
 	error = drm_mode_config_helper_suspend(&vbox->ddev);
 	if (error)
 		return error;
-	pci_save_state(vbox->ddev.pdev);
+	pci_save_state(pdev);
-	pci_disable_device(vbox->ddev.pdev);
+	pci_disable_device(pdev);
-	pci_set_power_state(vbox->ddev.pdev, PCI_D3hot);
+	pci_set_power_state(pdev, PCI_D3hot);
 	return 0;
 }
 static int vbox_pm_resume(struct device *dev)
 {
 	struct vbox_private *vbox = dev_get_drvdata(dev);
+	struct pci_dev *pdev = to_pci_dev(dev);
-	if (pci_enable_device(vbox->ddev.pdev))
+	if (pci_enable_device(pdev))
 		return -EIO;
 	return drm_mode_config_helper_resume(&vbox->ddev);

drivers/gpu/drm/vboxvideo/vbox_irq.c+3−1

 int vbox_irq_init(struct vbox_private *vbox)
 {
+	struct pci_dev *pdev = to_pci_dev(vbox->ddev.dev);
 	INIT_WORK(&vbox->hotplug_work, vbox_hotplug_worker);
 	vbox_update_mode_hints(vbox);
-	return drm_irq_install(&vbox->ddev, vbox->ddev.pdev->irq);
+	return drm_irq_install(&vbox->ddev, pdev->irq);
 }
 void vbox_irq_fini(struct vbox_private *vbox)

drivers/gpu/drm/vboxvideo/vbox_main.c+6−2

  *          Hans de Goede <hdegoede@redhat.com>
  */
+#include <linux/pci.h>
 #include <linux/vbox_err.h>
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_damage_helper.h>
 static int vbox_accel_init(struct vbox_private *vbox)
 {
+	struct pci_dev *pdev = to_pci_dev(vbox->ddev.dev);
 	struct vbva_buffer *vbva;
 	unsigned int i;
 	/* Take a command buffer for each screen from the end of usable VRAM. */
 	vbox->available_vram_size -= vbox->num_crtcs * VBVA_MIN_BUFFER_SIZE;
-	vbox->vbva_buffers = pci_iomap_range(vbox->ddev.pdev, 0,
+	vbox->vbva_buffers = pci_iomap_range(pdev, 0,
 					     vbox->available_vram_size,
 					     vbox->num_crtcs *
 					     VBVA_MIN_BUFFER_SIZE);
 int vbox_hw_init(struct vbox_private *vbox)
 {
+	struct pci_dev *pdev = to_pci_dev(vbox->ddev.dev);
 	int ret = -ENOMEM;
 	vbox->full_vram_size = inl(VBE_DISPI_IOPORT_DATA);
 	/* Map guest-heap at end of vram */
 	vbox->guest_heap =
-	    pci_iomap_range(vbox->ddev.pdev, 0, GUEST_HEAP_OFFSET(vbox),
+	    pci_iomap_range(pdev, 0, GUEST_HEAP_OFFSET(vbox),
 			    GUEST_HEAP_SIZE);
 	if (!vbox->guest_heap)
 		return -ENOMEM;

drivers/gpu/drm/vboxvideo/vbox_ttm.c+4−3

 	struct drm_vram_mm *vmm;
 	int ret;
 	struct drm_device *dev = &vbox->ddev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
-	vmm = drm_vram_helper_alloc_mm(dev, pci_resource_start(dev->pdev, 0),
+	vmm = drm_vram_helper_alloc_mm(dev, pci_resource_start(pdev, 0),
 				       vbox->available_vram_size);
 	if (IS_ERR(vmm)) {
 		ret = PTR_ERR(vmm);
 		return ret;
 	}
-	vbox->fb_mtrr = arch_phys_wc_add(pci_resource_start(dev->pdev, 0),
+	vbox->fb_mtrr = arch_phys_wc_add(pci_resource_start(pdev, 0),
-					 pci_resource_len(dev->pdev, 0));
+					 pci_resource_len(pdev, 0));
 	return 0;
 }

drivers/gpu/drm/vc4/vc4_bo.c+19−92

@@ -21,7 +21,7 @@ · 20 unmodified lines
21	#include "vc4_drv.h"	21	#include "vc4_drv.h"
22	#include "uapi/drm/vc4_drm.h"	22	#include "uapi/drm/vc4_drm.h"
23		23
24	static vm_fault_t vc4_fault(struct vm_fault *vmf);	24	static const struct drm_gem_object_funcs vc4_gem_object_funcs;
25		25
26	static const char * const bo_type_names[] = {	26	static const char * const bo_type_names[] = {
27	"kernel",	27	"kernel",
@@ -376,20 +376,6 @@ out: · 348 unmodified lines
376	return bo;	376	return bo;
377	}	377	}
378		378
379	static const struct vm_operations_struct vc4_vm_ops = {
380	.fault = vc4_fault,
381	.open = drm_gem_vm_open,
382	.close = drm_gem_vm_close,
383	};
384
385	static const struct drm_gem_object_funcs vc4_gem_object_funcs = {
386	.free = vc4_free_object,
387	.export = vc4_prime_export,
388	.get_sg_table = drm_gem_cma_get_sg_table,
389	.vmap = vc4_prime_vmap,
390	.vm_ops = &vc4_vm_ops,
391	};
392
393	/**	379	/**
394	* vc4_create_object - Implementation of driver->gem_create_object.	380	* vc4_create_object - Implementation of driver->gem_create_object.
395	* @dev: DRM device	381	* @dev: DRM device
@@ -538,7 +524,7 @@ static void vc4_bo_cache_free_old(struct drm_device *dev) · 142 unmodified lines
538	/* Called on the last userspace/kernel unreference of the BO. Returns	524	/* Called on the last userspace/kernel unreference of the BO. Returns
539	* it to the BO cache if possible, otherwise frees it.	525	* it to the BO cache if possible, otherwise frees it.
540	*/	526	*/
541	void vc4_free_object(struct drm_gem_object *gem_bo)	527	static void vc4_free_object(struct drm_gem_object *gem_bo)
542	{	528	{
543	struct drm_device *dev = gem_bo->dev;	529	struct drm_device *dev = gem_bo->dev;
544	struct vc4_dev *vc4 = to_vc4_dev(dev);	530	struct vc4_dev *vc4 = to_vc4_dev(dev);
@@ -673,7 +659,7 @@ static void vc4_bo_cache_time_timer(struct timer_list *t) · 128 unmodified lines
673	schedule_work(&vc4->bo_cache.time_work);	659	schedule_work(&vc4->bo_cache.time_work);
674	}	660	}
675		661
676	struct dma_buf * vc4_prime_export(struct drm_gem_object *obj, int flags)	662	static struct dma_buf vc4_prime_export(struct drm_gem_object obj, int flags)
677	{	663	{
678	struct vc4_bo *bo = to_vc4_bo(obj);	664	struct vc4_bo *bo = to_vc4_bo(obj);
679	struct dma_buf *dmabuf;	665	struct dma_buf *dmabuf;
@@ -718,19 +704,9 @@ static vm_fault_t vc4_fault(struct vm_fault *vmf) · 38 unmodified lines
718	return VM_FAULT_SIGBUS;	704	return VM_FAULT_SIGBUS;
719	}	705	}
720		706
721	int vc4_mmap(struct file filp, struct vm_area_struct vma)	707	static int vc4_gem_object_mmap(struct drm_gem_object obj, struct vm_area_struct vma)
722	{	708	{
723	struct drm_gem_object *gem_obj;	709	struct vc4_bo *bo = to_vc4_bo(obj);
724	unsigned long vm_pgoff;
725	struct vc4_bo *bo;
726	int ret;
727
728	ret = drm_gem_mmap(filp, vma);
729	if (ret)
730	return ret;
731
732	gem_obj = vma->vm_private_data;
733	bo = to_vc4_bo(gem_obj);
734		710
735	if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {	711	if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
736	DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");	712	DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");
@@ -744,72 +720,23 @@ int vc4_mmap(struct file filp, struct vm_area_struct vma) · 7 unmodified lines
744	return -EINVAL;	720	return -EINVAL;
745	}	721	}
746		722
747	/*	723	return drm_gem_cma_mmap(obj, vma);
748	* Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the
749	* vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map
750	* the whole buffer.
751	*/
752	vma->vm_flags &= ~VM_PFNMAP;
753
754	/* This ->vm_pgoff dance is needed to make all parties happy:
755	* - dma_mmap_wc() uses ->vm_pgoff as an offset within the allocated
756	* mem-region, hence the need to set it to zero (the value set by
757	* the DRM core is a virtual offset encoding the GEM object-id)
758	* - the mmap() core logic needs ->vm_pgoff to be restored to its
759	* initial value before returning from this function because it
760	* encodes the offset of this GEM in the dev->anon_inode pseudo-file
761	* and this information will be used when we invalidate userspace
762	* mappings with drm_vma_node_unmap() (called from vc4_gem_purge()).
763	*/
764	vm_pgoff = vma->vm_pgoff;
765	vma->vm_pgoff = 0;
766	ret = dma_mmap_wc(bo->base.base.dev->dev, vma, bo->base.vaddr,
767	bo->base.paddr, vma->vm_end - vma->vm_start);
768	vma->vm_pgoff = vm_pgoff;
769
770	if (ret)
771	drm_gem_vm_close(vma);
772
773	return ret;
774	}
775
776	int vc4_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma)
777	{
778	struct vc4_bo *bo = to_vc4_bo(obj);
779
780	if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
781	DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");
782	return -EINVAL;
783	}
784
785	return drm_gem_prime_mmap(obj, vma);
786	}	724	}
787		725
788	int vc4_prime_vmap(struct drm_gem_object obj, struct dma_buf_map map)	726	static const struct vm_operations_struct vc4_vm_ops = {
789	{	727	.fault = vc4_fault,
790	struct vc4_bo *bo = to_vc4_bo(obj);	728	.open = drm_gem_vm_open,
791		729	.close = drm_gem_vm_close,
792	if (bo->validated_shader) {	730	};
793	DRM_DEBUG("mmaping of shader BOs not allowed.\n");
794	return -EINVAL;
795	}
796
797	return drm_gem_cma_vmap(obj, map);
798	}
799
800	struct drm_gem_object *
801	vc4_prime_import_sg_table(struct drm_device *dev,
802	struct dma_buf_attachment *attach,
803	struct sg_table *sgt)
804	{
805	struct drm_gem_object *obj;
806
807	obj = drm_gem_cma_prime_import_sg_table(dev, attach, sgt);
808	if (IS_ERR(obj))
809	return obj;
810		731
811	return obj;	732	static const struct drm_gem_object_funcs vc4_gem_object_funcs = {
812	}	733	.free = vc4_free_object,
		734	.export = vc4_prime_export,
		735	.get_sg_table = drm_gem_cma_get_sg_table,
		736	.vmap = drm_gem_cma_vmap,
		737	.mmap = vc4_gem_object_mmap,
		738	.vm_ops = &vc4_vm_ops,
		739	};
813		740
814	static int vc4_grab_bin_bo(struct vc4_dev vc4, struct vc4_file vc4file)	741	static int vc4_grab_bin_bo(struct vc4_dev vc4, struct vc4_file vc4file)
815	{	742	{

drivers/gpu/drm/vc4/vc4_drv.c+2−17

@@ -140,17 +140,7 @@ static void vc4_close(struct drm_device dev, struct drm_file file) · 139 unmodified lines
140	kfree(vc4file);	140	kfree(vc4file);
141	}	141	}
142		142
143	static const struct file_operations vc4_drm_fops = {	143	DEFINE_DRM_GEM_FOPS(vc4_drm_fops);
144	.owner = THIS_MODULE,
145	.open = drm_open,
146	.release = drm_release,
147	.unlocked_ioctl = drm_ioctl,
148	.mmap = vc4_mmap,
149	.poll = drm_poll,
150	.read = drm_read,
151	.compat_ioctl = drm_compat_ioctl,
152	.llseek = noop_llseek,
153	};
154		144
155	static const struct drm_ioctl_desc vc4_drm_ioctls[] = {	145	static const struct drm_ioctl_desc vc4_drm_ioctls[] = {
156	DRM_IOCTL_DEF_DRV(VC4_SUBMIT_CL, vc4_submit_cl_ioctl, DRM_RENDER_ALLOW),	146	DRM_IOCTL_DEF_DRV(VC4_SUBMIT_CL, vc4_submit_cl_ioctl, DRM_RENDER_ALLOW),
@@ -190,12 +180,7 @@ static struct drm_driver vc4_drm_driver = { · 33 unmodified lines
190		180
191	.gem_create_object = vc4_create_object,	181	.gem_create_object = vc4_create_object,
192		182
193	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,	183	DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(vc4_dumb_create),
194	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
195	.gem_prime_import_sg_table = vc4_prime_import_sg_table,
196	.gem_prime_mmap = vc4_prime_mmap,
197
198	.dumb_create = vc4_dumb_create,
199		184
200	.ioctls = vc4_drm_ioctls,	185	.ioctls = vc4_drm_ioctls,
201	.num_ioctls = ARRAY_SIZE(vc4_drm_ioctls),	186	.num_ioctls = ARRAY_SIZE(vc4_drm_ioctls),

drivers/gpu/drm/vc4/vc4_drv.h+0−8

 /* vc4_bo.c */
 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
-void vc4_free_object(struct drm_gem_object *gem_obj);
 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
 			     bool from_cache, enum vc4_kernel_bo_type type);
 int vc4_dumb_create(struct drm_file *file_priv,
 		    struct drm_device *dev,
 		    struct drm_mode_create_dumb *args);
-struct dma_buf *vc4_prime_export(struct drm_gem_object *obj, int flags);
 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
 			     struct drm_file *file_priv);
 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
 		       struct drm_file *file_priv);
-int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
-int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
-struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
-						 struct dma_buf_attachment *attach,
-						 struct sg_table *sgt);
-int vc4_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
 int vc4_bo_cache_init(struct drm_device *dev);
 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
 void vc4_bo_dec_usecnt(struct vc4_bo *bo);

drivers/gpu/drm/virtio/virtgpu_drv.c+0−1

@@ -54,7 +54,6 @@ static int virtio_gpu_pci_quirk(struct drm_device dev, struct virtio_device vd · 53 unmodified lines
54	DRM_INFO("pci: %s detected at %s\n",	54	DRM_INFO("pci: %s detected at %s\n",
55	vga ? "virtio-vga" : "virtio-gpu-pci",	55	vga ? "virtio-vga" : "virtio-gpu-pci",
56	pname);	56	pname);
57	dev->pdev = pdev;
58	if (vga)	57	if (vga)
59	drm_fb_helper_remove_conflicting_pci_framebuffers(pdev,	58	drm_fb_helper_remove_conflicting_pci_framebuffers(pdev,
60	"virtiodrmfb");	59	"virtiodrmfb");

drivers/gpu/drm/virtio/virtgpu_gem.c+5−3

 	int ret;
 	u32 handle;
-	if (vgdev->has_virgl_3d)
-		virtio_gpu_create_context(dev, file);
 	ret = virtio_gpu_object_create(vgdev, params, &obj, NULL);
 	if (ret < 0)
 		return ret;
 	if (!vgdev->has_virgl_3d)
 		goto out_notify;
+	/* the context might still be missing when the first ioctl is
+	 * DRM_IOCTL_MODE_CREATE_DUMB or DRM_IOCTL_PRIME_FD_TO_HANDLE
+	 */
+	virtio_gpu_create_context(obj->dev, file);
 	objs = virtio_gpu_array_alloc(1);
 	if (!objs)
 		return -ENOMEM;

drivers/gpu/drm/virtio/virtgpu_vram.c+1−0

@@ -69,6 +69,7 @@ static const struct drm_gem_object_funcs virtio_gpu_vram_funcs = { · 68 unmodified lines
69	.close = virtio_gpu_gem_object_close,	69	.close = virtio_gpu_gem_object_close,
70	.free = virtio_gpu_vram_free,	70	.free = virtio_gpu_vram_free,
71	.mmap = virtio_gpu_vram_mmap,	71	.mmap = virtio_gpu_vram_mmap,
		72	.export = virtgpu_gem_prime_export,
72	};	73	};
73		74
74	bool virtio_gpu_is_vram(struct virtio_gpu_object *bo)	75	bool virtio_gpu_is_vram(struct virtio_gpu_object *bo)

drivers/gpu/drm/vkms/vkms_drv.c+41−8

 #define DRIVER_MAJOR	1
 #define DRIVER_MINOR	0
-static struct vkms_device *vkms_device;
+static struct vkms_config *default_config;
-bool enable_cursor = true;
+static bool enable_cursor = true;
 module_param_named(enable_cursor, enable_cursor, bool, 0444);
 MODULE_PARM_DESC(enable_cursor, "Enable/Disable cursor support");
+static bool enable_writeback = true;
+module_param_named(enable_writeback, enable_writeback, bool, 0444);
+MODULE_PARM_DESC(enable_writeback, "Enable/Disable writeback connector support");
 DEFINE_DRM_GEM_FOPS(vkms_driver_fops);
 static void vkms_release(struct drm_device *dev)
 	return vkms_output_init(vkmsdev, 0);
 }
-static int __init vkms_init(void)
+static int vkms_create(struct vkms_config *config)
 {
 	int ret;
 	struct platform_device *pdev;
+	struct vkms_device *vkms_device;
 	pdev = platform_device_register_simple(DRIVER_NAME, -1, NULL, 0);
 	if (IS_ERR(pdev))
 		goto out_devres;
 	}
 	vkms_device->platform = pdev;
+	vkms_device->config = config;
+	config->dev = vkms_device;
 	ret = dma_coerce_mask_and_coherent(vkms_device->drm.dev,
 					   DMA_BIT_MASK(64));
 	return ret;
 }
-static void __exit vkms_exit(void)
+static int __init vkms_init(void)
+{
+	struct vkms_config *config;
+	config = kmalloc(sizeof(*config), GFP_KERNEL);
+	if (!config)
+		return -ENOMEM;
+	default_config = config;
+	config->cursor = enable_cursor;
+	config->writeback = enable_writeback;
+	return vkms_create(config);
+}
+static void vkms_destroy(struct vkms_config *config)
 {
 	struct platform_device *pdev;
-	if (!vkms_device) {
+	if (!config->dev) {
 		DRM_INFO("vkms_device is NULL.\n");
 		return;
 	}
-	pdev = vkms_device->platform;
+	pdev = config->dev->platform;
-	drm_dev_unregister(&vkms_device->drm);
+	drm_dev_unregister(&config->dev->drm);
-	drm_atomic_helper_shutdown(&vkms_device->drm);
+	drm_atomic_helper_shutdown(&config->dev->drm);
 	devres_release_group(&pdev->dev, NULL);
 	platform_device_unregister(pdev);
+	config->dev = NULL;
+}
+static void __exit vkms_exit(void)
+{
+	if (default_config->dev)
+		vkms_destroy(default_config);
+	kfree(default_config);
 }
 module_init(vkms_init);

drivers/gpu/drm/vkms/vkms_drv.h+10−2

 #define XRES_MAX  8192
 #define YRES_MAX  8192
-extern bool enable_cursor;
 struct vkms_composer {
 	struct drm_framebuffer fb;
 	struct drm_rect src, dst;
 	spinlock_t composer_lock;
 };
+struct vkms_device;
+struct vkms_config {
+	bool writeback;
+	bool cursor;
+	/* only set when instantiated */
+	struct vkms_device *dev;
+};
 struct vkms_device {
 	struct drm_device drm;
 	struct platform_device *platform;
 	struct vkms_output output;
+	const struct vkms_config *config;
 };
 #define drm_crtc_to_vkms_output(target) \

drivers/gpu/drm/vkms/vkms_output.c+8−5

 	struct drm_crtc *crtc = &output->crtc;
 	struct drm_plane *primary, *cursor = NULL;
 	int ret;
+	int writeback;
 	primary = vkms_plane_init(vkmsdev, DRM_PLANE_TYPE_PRIMARY, index);
 	if (IS_ERR(primary))
 		return PTR_ERR(primary);
-	if (enable_cursor) {
+	if (vkmsdev->config->cursor) {
 		cursor = vkms_plane_init(vkmsdev, DRM_PLANE_TYPE_CURSOR, index);
 		if (IS_ERR(cursor)) {
 			ret = PTR_ERR(cursor);
 		goto err_attach;
 	}
-	ret = vkms_enable_writeback_connector(vkmsdev);
+	if (vkmsdev->config->writeback) {
-	if (ret)
+		writeback = vkms_enable_writeback_connector(vkmsdev);
-		DRM_ERROR("Failed to init writeback connector\n");
+		if (writeback)
+			DRM_ERROR("Failed to init writeback connector\n");
+	}
 	drm_mode_config_reset(dev);
 	drm_crtc_cleanup(crtc);
 err_crtc:
-	if (enable_cursor)
+	if (vkmsdev->config->cursor)
 		drm_plane_cleanup(cursor);
 err_cursor:

drivers/gpu/drm/vmwgfx/Makefile+3−3

@@ -1,9 +1,9 @@
1	# SPDX-License-Identifier: GPL-2.0	1	# SPDX-License-Identifier: GPL-2.0
2	vmwgfx-y := vmwgfx_execbuf.o vmwgfx_gmr.o vmwgfx_kms.o vmwgfx_drv.o \	2	vmwgfx-y := vmwgfx_execbuf.o vmwgfx_gmr.o vmwgfx_kms.o vmwgfx_drv.o \
3	vmwgfx_fb.o vmwgfx_ioctl.o vmwgfx_resource.o vmwgfx_ttm_buffer.o \	3	vmwgfx_fb.o vmwgfx_ioctl.o vmwgfx_resource.o vmwgfx_ttm_buffer.o \
4	vmwgfx_fifo.o vmwgfx_irq.o vmwgfx_ldu.o vmwgfx_ttm_glue.o \	4	vmwgfx_cmd.o vmwgfx_irq.o vmwgfx_ldu.o vmwgfx_ttm_glue.o \
5	vmwgfx_overlay.o vmwgfx_marker.o vmwgfx_gmrid_manager.o \	5	vmwgfx_overlay.o vmwgfx_gmrid_manager.o vmwgfx_fence.o \
6	vmwgfx_fence.o vmwgfx_bo.o vmwgfx_scrn.o vmwgfx_context.o \	6	vmwgfx_bo.o vmwgfx_scrn.o vmwgfx_context.o \
7	vmwgfx_surface.o vmwgfx_prime.o vmwgfx_mob.o vmwgfx_shader.o \	7	vmwgfx_surface.o vmwgfx_prime.o vmwgfx_mob.o vmwgfx_shader.o \
8	vmwgfx_cmdbuf_res.o vmwgfx_cmdbuf.o vmwgfx_stdu.o \	8	vmwgfx_cmdbuf_res.o vmwgfx_cmdbuf.o vmwgfx_stdu.o \
9	vmwgfx_cotable.o vmwgfx_so.o vmwgfx_binding.o vmwgfx_msg.o \	9	vmwgfx_cotable.o vmwgfx_so.o vmwgfx_binding.o vmwgfx_msg.o \

drivers/gpu/drm/vmwgfx/vmwgfx_binding.c+26−26

@@ -555,7 +555,7 @@ static int vmw_binding_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind) · 554 unmodified lines
555	SVGA3dCmdSetShader body;	555	SVGA3dCmdSetShader body;
556	} *cmd;	556	} *cmd;
557		557
558	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	558	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
559	if (unlikely(cmd == NULL))	559	if (unlikely(cmd == NULL))
560	return -ENOMEM;	560	return -ENOMEM;
561		561
@@ -564,7 +564,7 @@ static int vmw_binding_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind) · 2 unmodified lines
564	cmd->body.cid = bi->ctx->id;	564	cmd->body.cid = bi->ctx->id;
565	cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;	565	cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
566	cmd->body.shid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);	566	cmd->body.shid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
567	vmw_fifo_commit(dev_priv, sizeof(*cmd));	567	vmw_cmd_commit(dev_priv, sizeof(*cmd));
568		568
569	return 0;	569	return 0;
570	}	570	}
@@ -587,7 +587,7 @@ static int vmw_binding_scrub_render_target(struct vmw_ctx_bindinfo *bi, · 16 unmodified lines
587	SVGA3dCmdSetRenderTarget body;	587	SVGA3dCmdSetRenderTarget body;
588	} *cmd;	588	} *cmd;
589		589
590	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	590	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
591	if (unlikely(cmd == NULL))	591	if (unlikely(cmd == NULL))
592	return -ENOMEM;	592	return -ENOMEM;
593		593
@@ -598,7 +598,7 @@ static int vmw_binding_scrub_render_target(struct vmw_ctx_bindinfo *bi, · 4 unmodified lines
598	cmd->body.target.sid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);	598	cmd->body.target.sid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
599	cmd->body.target.face = 0;	599	cmd->body.target.face = 0;
600	cmd->body.target.mipmap = 0;	600	cmd->body.target.mipmap = 0;
601	vmw_fifo_commit(dev_priv, sizeof(*cmd));	601	vmw_cmd_commit(dev_priv, sizeof(*cmd));
602		602
603	return 0;	603	return 0;
604	}	604	}
@@ -626,7 +626,7 @@ static int vmw_binding_scrub_texture(struct vmw_ctx_bindinfo *bi, · 21 unmodified lines
626	} body;	626	} body;
627	} *cmd;	627	} *cmd;
628		628
629	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	629	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
630	if (unlikely(cmd == NULL))	630	if (unlikely(cmd == NULL))
631	return -ENOMEM;	631	return -ENOMEM;
632		632
@@ -636,7 +636,7 @@ static int vmw_binding_scrub_texture(struct vmw_ctx_bindinfo *bi, · 3 unmodified lines
636	cmd->body.s1.stage = binding->texture_stage;	636	cmd->body.s1.stage = binding->texture_stage;
637	cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE;	637	cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE;
638	cmd->body.s1.value = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);	638	cmd->body.s1.value = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
639	vmw_fifo_commit(dev_priv, sizeof(*cmd));	639	vmw_cmd_commit(dev_priv, sizeof(*cmd));
640		640
641	return 0;	641	return 0;
642	}	642	}
@@ -657,7 +657,7 @@ static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi, bool rebind) · 14 unmodified lines
657	SVGA3dCmdDXSetShader body;	657	SVGA3dCmdDXSetShader body;
658	} *cmd;	658	} *cmd;
659		659
660	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);	660	cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
661	if (unlikely(cmd == NULL))	661	if (unlikely(cmd == NULL))
662	return -ENOMEM;	662	return -ENOMEM;
663		663
@@ -665,7 +665,7 @@ static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi, bool rebind) · 1 unmodified line
665	cmd->header.size = sizeof(cmd->body);	665	cmd->header.size = sizeof(cmd->body);
666	cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;	666	cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
667	cmd->body.shaderId = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);	667	cmd->body.shaderId = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
668	vmw_fifo_commit(dev_priv, sizeof(*cmd));	668	vmw_cmd_commit(dev_priv, sizeof(*cmd));
669		669
670	return 0;	670	return 0;
671	}	671	}
@@ -686,7 +686,7 @@ static int vmw_binding_scrub_cb(struct vmw_ctx_bindinfo *bi, bool rebind) · 14 unmodified lines
686	SVGA3dCmdDXSetSingleConstantBuffer body;	686	SVGA3dCmdDXSetSingleConstantBuffer body;
687	} *cmd;	687	} *cmd;
688		688
689	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);	689	cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
690	if (unlikely(cmd == NULL))	690	if (unlikely(cmd == NULL))
691	return -ENOMEM;	691	return -ENOMEM;
692		692
@@ -703,7 +703,7 @@ static int vmw_binding_scrub_cb(struct vmw_ctx_bindinfo *bi, bool rebind) · 10 unmodified lines
703	cmd->body.sizeInBytes = 0;	703	cmd->body.sizeInBytes = 0;
704	cmd->body.sid = SVGA3D_INVALID_ID;	704	cmd->body.sid = SVGA3D_INVALID_ID;
705	}	705	}
706	vmw_fifo_commit(dev_priv, sizeof(*cmd));	706	vmw_cmd_commit(dev_priv, sizeof(*cmd));
707		707
708	return 0;	708	return 0;
709	}	709	}
@@ -810,7 +810,7 @@ static int vmw_emit_set_sr(struct vmw_ctx_binding_state *cbs, · 100 unmodified lines
810		810
811	view_id_size = cbs->bind_cmd_count*sizeof(uint32);	811	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
812	cmd_size = sizeof(*cmd) + view_id_size;	812	cmd_size = sizeof(*cmd) + view_id_size;
813	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);	813	cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
814	if (unlikely(cmd == NULL))	814	if (unlikely(cmd == NULL))
815	return -ENOMEM;	815	return -ENOMEM;
816		816
@@ -821,7 +821,7 @@ static int vmw_emit_set_sr(struct vmw_ctx_binding_state *cbs, · 4 unmodified lines
821		821
822	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);	822	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
823		823
824	vmw_fifo_commit(ctx->dev_priv, cmd_size);	824	vmw_cmd_commit(ctx->dev_priv, cmd_size);
825	bitmap_clear(cbs->per_shader[shader_slot].dirty_sr,	825	bitmap_clear(cbs->per_shader[shader_slot].dirty_sr,
826	cbs->bind_first_slot, cbs->bind_cmd_count);	826	cbs->bind_first_slot, cbs->bind_cmd_count);
827		827
@@ -846,7 +846,7 @@ static int vmw_emit_set_rt(struct vmw_ctx_binding_state *cbs) · 18 unmodified lines
846	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS);	846	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS);
847	view_id_size = cbs->bind_cmd_count*sizeof(uint32);	847	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
848	cmd_size = sizeof(*cmd) + view_id_size;	848	cmd_size = sizeof(*cmd) + view_id_size;
849	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);	849	cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
850	if (unlikely(cmd == NULL))	850	if (unlikely(cmd == NULL))
851	return -ENOMEM;	851	return -ENOMEM;
852		852
@@ -860,7 +860,7 @@ static int vmw_emit_set_rt(struct vmw_ctx_binding_state *cbs) · 7 unmodified lines
860		860
861	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);	861	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
862		862
863	vmw_fifo_commit(ctx->dev_priv, cmd_size);	863	vmw_cmd_commit(ctx->dev_priv, cmd_size);
864		864
865	return 0;	865	return 0;
866		866
@@ -930,7 +930,7 @@ static int vmw_emit_set_so_target(struct vmw_ctx_binding_state *cbs) · 63 unmodified lines
930		930
931	so_target_size = cbs->bind_cmd_count*sizeof(SVGA3dSoTarget);	931	so_target_size = cbs->bind_cmd_count*sizeof(SVGA3dSoTarget);
932	cmd_size = sizeof(*cmd) + so_target_size;	932	cmd_size = sizeof(*cmd) + so_target_size;
933	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);	933	cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
934	if (unlikely(cmd == NULL))	934	if (unlikely(cmd == NULL))
935	return -ENOMEM;	935	return -ENOMEM;
936		936
@@ -938,7 +938,7 @@ static int vmw_emit_set_so_target(struct vmw_ctx_binding_state *cbs) · 1 unmodified line
938	cmd->header.size = sizeof(cmd->body) + so_target_size;	938	cmd->header.size = sizeof(cmd->body) + so_target_size;
939	memcpy(&cmd[1], cbs->bind_cmd_buffer, so_target_size);	939	memcpy(&cmd[1], cbs->bind_cmd_buffer, so_target_size);
940		940
941	vmw_fifo_commit(ctx->dev_priv, cmd_size);	941	vmw_cmd_commit(ctx->dev_priv, cmd_size);
942		942
943	return 0;	943	return 0;
944		944
@@ -1044,7 +1044,7 @@ static int vmw_emit_set_vb(struct vmw_ctx_binding_state *cbs) · 99 unmodified lines
1044		1044
1045	set_vb_size = cbs->bind_cmd_count*sizeof(SVGA3dVertexBuffer);	1045	set_vb_size = cbs->bind_cmd_count*sizeof(SVGA3dVertexBuffer);
1046	cmd_size = sizeof(*cmd) + set_vb_size;	1046	cmd_size = sizeof(*cmd) + set_vb_size;
1047	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);	1047	cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
1048	if (unlikely(cmd == NULL))	1048	if (unlikely(cmd == NULL))
1049	return -ENOMEM;	1049	return -ENOMEM;
1050		1050
@@ -1054,7 +1054,7 @@ static int vmw_emit_set_vb(struct vmw_ctx_binding_state *cbs) · 3 unmodified lines
1054		1054
1055	memcpy(&cmd[1], cbs->bind_cmd_buffer, set_vb_size);	1055	memcpy(&cmd[1], cbs->bind_cmd_buffer, set_vb_size);
1056		1056
1057	vmw_fifo_commit(ctx->dev_priv, cmd_size);	1057	vmw_cmd_commit(ctx->dev_priv, cmd_size);
1058	bitmap_clear(cbs->dirty_vb,	1058	bitmap_clear(cbs->dirty_vb,
1059	cbs->bind_first_slot, cbs->bind_cmd_count);	1059	cbs->bind_first_slot, cbs->bind_cmd_count);
1060		1060
@@ -1074,7 +1074,7 @@ static int vmw_emit_set_uav(struct vmw_ctx_binding_state *cbs) · 13 unmodified lines
1074	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);	1074	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);
1075	view_id_size = cbs->bind_cmd_count*sizeof(uint32);	1075	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
1076	cmd_size = sizeof(*cmd) + view_id_size;	1076	cmd_size = sizeof(*cmd) + view_id_size;
1077	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);	1077	cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
1078	if (!cmd)	1078	if (!cmd)
1079	return -ENOMEM;	1079	return -ENOMEM;
1080		1080
@@ -1086,7 +1086,7 @@ static int vmw_emit_set_uav(struct vmw_ctx_binding_state *cbs) · 5 unmodified lines
1086		1086
1087	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);	1087	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
1088		1088
1089	vmw_fifo_commit(ctx->dev_priv, cmd_size);	1089	vmw_cmd_commit(ctx->dev_priv, cmd_size);
1090		1090
1091	return 0;	1091	return 0;
1092	}	1092	}
@@ -1104,7 +1104,7 @@ static int vmw_emit_set_cs_uav(struct vmw_ctx_binding_state *cbs) · 11 unmodified lines
1104	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);	1104	vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);
1105	view_id_size = cbs->bind_cmd_count*sizeof(uint32);	1105	view_id_size = cbs->bind_cmd_count*sizeof(uint32);
1106	cmd_size = sizeof(*cmd) + view_id_size;	1106	cmd_size = sizeof(*cmd) + view_id_size;
1107	cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id);	1107	cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
1108	if (!cmd)	1108	if (!cmd)
1109	return -ENOMEM;	1109	return -ENOMEM;
1110		1110
@@ -1116,7 +1116,7 @@ static int vmw_emit_set_cs_uav(struct vmw_ctx_binding_state *cbs) · 5 unmodified lines
1116		1116
1117	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);	1117	memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
1118		1118
1119	vmw_fifo_commit(ctx->dev_priv, cmd_size);	1119	vmw_cmd_commit(ctx->dev_priv, cmd_size);
1120		1120
1121	return 0;	1121	return 0;
1122	}	1122	}
@@ -1263,7 +1263,7 @@ static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind) · 140 unmodified lines
1263	SVGA3dCmdDXSetIndexBuffer body;	1263	SVGA3dCmdDXSetIndexBuffer body;
1264	} *cmd;	1264	} *cmd;
1265		1265
1266	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);	1266	cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
1267	if (unlikely(cmd == NULL))	1267	if (unlikely(cmd == NULL))
1268	return -ENOMEM;	1268	return -ENOMEM;
1269		1269
@@ -1279,7 +1279,7 @@ static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind) · 9 unmodified lines
1279	cmd->body.offset = 0;	1279	cmd->body.offset = 0;
1280	}	1280	}
1281		1281
1282	vmw_fifo_commit(dev_priv, sizeof(*cmd));	1282	vmw_cmd_commit(dev_priv, sizeof(*cmd));
1283		1283
1284	return 0;	1284	return 0;
1285	}	1285	}
@@ -1315,14 +1315,14 @@ static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind) · 29 unmodified lines
1315	SVGA3dCmdDXSetStreamOutput body;	1315	SVGA3dCmdDXSetStreamOutput body;
1316	} *cmd;	1316	} *cmd;
1317		1317
1318	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id);	1318	cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
1319	if (!cmd)	1319	if (!cmd)
1320	return -ENOMEM;	1320	return -ENOMEM;
1321		1321
1322	cmd->header.id = SVGA_3D_CMD_DX_SET_STREAMOUTPUT;	1322	cmd->header.id = SVGA_3D_CMD_DX_SET_STREAMOUTPUT;
1323	cmd->header.size = sizeof(cmd->body);	1323	cmd->header.size = sizeof(cmd->body);
1324	cmd->body.soid = rebind ? bi->res->id : SVGA3D_INVALID_ID;	1324	cmd->body.soid = rebind ? bi->res->id : SVGA3D_INVALID_ID;
1325	vmw_fifo_commit(dev_priv, sizeof(*cmd));	1325	vmw_cmd_commit(dev_priv, sizeof(*cmd));
1326		1326
1327	return 0;	1327	return 0;
1328	}	1328	}

drivers/gpu/drm/vmwgfx/vmwgfx_cmd.crenamed from drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c+59−67

 // SPDX-License-Identifier: GPL-2.0 OR MIT
 /**************************************************************************
  *
- * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA
+ * Copyright 2009-2020 VMware, Inc., Palo Alto, CA., USA
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the
 	SVGA3dCmdDXTempSetContext body;
 };
-bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
+bool vmw_supports_3d(struct vmw_private *dev_priv)
 {
-	u32 *fifo_mem = dev_priv->mmio_virt;
 	uint32_t fifo_min, hwversion;
 	const struct vmw_fifo_state *fifo = &dev_priv->fifo;
 	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
 		return false;
-	fifo_min = vmw_mmio_read(fifo_mem  + SVGA_FIFO_MIN);
+	fifo_min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
 	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
 		return false;
-	hwversion = vmw_mmio_read(fifo_mem +
+	hwversion = vmw_fifo_mem_read(dev_priv,
-				  ((fifo->capabilities &
+				      ((fifo->capabilities &
-				    SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
+					SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
-				   SVGA_FIFO_3D_HWVERSION_REVISED :
+					       SVGA_FIFO_3D_HWVERSION_REVISED :
-				   SVGA_FIFO_3D_HWVERSION));
+					       SVGA_FIFO_3D_HWVERSION));
 	if (hwversion == 0)
 		return false;
 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
 {
-	u32  *fifo_mem = dev_priv->mmio_virt;
 	uint32_t caps;
 	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
 		return false;
-	caps = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
+	caps = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CAPABILITIES);
 	if (caps & SVGA_FIFO_CAP_PITCHLOCK)
 		return true;
 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
 {
-	u32  *fifo_mem = dev_priv->mmio_virt;
 	uint32_t max;
 	uint32_t min;
 	vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
 		  SVGA_REG_ENABLE_HIDE);
 	vmw_write(dev_priv, SVGA_REG_TRACES, 0);
 	min = 4;
 	if (min < PAGE_SIZE)
 		min = PAGE_SIZE;
-	vmw_mmio_write(min, fifo_mem + SVGA_FIFO_MIN);
+	vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MIN, min);
-	vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
+	vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MAX, dev_priv->fifo_mem_size);
 	wmb();
-	vmw_mmio_write(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
+	vmw_fifo_mem_write(dev_priv, SVGA_FIFO_NEXT_CMD, min);
-	vmw_mmio_write(min,  fifo_mem + SVGA_FIFO_STOP);
+	vmw_fifo_mem_write(dev_priv, SVGA_FIFO_STOP, min);
-	vmw_mmio_write(0, fifo_mem + SVGA_FIFO_BUSY);
+	vmw_fifo_mem_write(dev_priv, SVGA_FIFO_BUSY, 0);
 	mb();
 	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
-	max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
+	max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
-	min = vmw_mmio_read(fifo_mem  + SVGA_FIFO_MIN);
+	min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
-	fifo->capabilities = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
+	fifo->capabilities = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CAPABILITIES);
 	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
 		 (unsigned int) max,
 		 (unsigned int) fifo->capabilities);
 	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
-	vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
+	vmw_fifo_mem_write(dev_priv, SVGA_FIFO_FENCE, dev_priv->last_read_seqno);
-	vmw_marker_queue_init(&fifo->marker_queue);
 	return 0;
 }
 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
 {
-	u32 *fifo_mem = dev_priv->mmio_virt;
+	u32 *fifo_mem = dev_priv->fifo_mem;
 	if (cmpxchg(fifo_mem + SVGA_FIFO_BUSY, 0, 1) == 0)
 		vmw_write(dev_priv, SVGA_REG_SYNC, reason);
 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
 {
-	u32  *fifo_mem = dev_priv->mmio_virt;
 	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
 	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
 		;
-	dev_priv->last_read_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
+	dev_priv->last_read_seqno = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_FENCE);
 	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
 		  dev_priv->config_done_state);
 	vmw_write(dev_priv, SVGA_REG_TRACES,
 		  dev_priv->traces_state);
-	vmw_marker_queue_takedown(&fifo->marker_queue);
 	if (likely(fifo->static_buffer != NULL)) {
 		vfree(fifo->static_buffer);
 		fifo->static_buffer = NULL;
 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
 {
-	u32  *fifo_mem = dev_priv->mmio_virt;
+	uint32_t max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
-	uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
+	uint32_t next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);
-	uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
+	uint32_t min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
-	uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
+	uint32_t stop = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_STOP);
-	uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
 	return ((max - next_cmd) + (stop - min) <= bytes);
 }
 				    uint32_t bytes)
 {
 	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
-	u32  *fifo_mem = dev_priv->mmio_virt;
+	u32  *fifo_mem = dev_priv->fifo_mem;
 	uint32_t max;
 	uint32_t min;
 	uint32_t next_cmd;
 	int ret;
 	mutex_lock(&fifo_state->fifo_mutex);
-	max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
+	max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
-	min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
+	min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
-	next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
+	next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);
 	if (unlikely(bytes >= (max - min)))
 		goto out_err;
 	fifo_state->reserved_size = bytes;
 	while (1) {
-		uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
+		uint32_t stop = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_STOP);
 		bool need_bounce = false;
 		bool reserve_in_place = false;
 				fifo_state->using_bounce_buffer = false;
 				if (reserveable)
-					vmw_mmio_write(bytes, fifo_mem +
+					vmw_fifo_mem_write(dev_priv,
-						       SVGA_FIFO_RESERVED);
+							   SVGA_FIFO_RESERVED,
+							   bytes);
 				return (void __force *) (fifo_mem +
 							 (next_cmd >> 2));
 			} else {
 	return NULL;
 }
-void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes,
+void *vmw_cmd_ctx_reserve(struct vmw_private *dev_priv, uint32_t bytes,
 			  int ctx_id)
 {
 	void *ret;
 }
 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
-			      u32  *fifo_mem,
+			      struct vmw_private *vmw,
 			      uint32_t next_cmd,
 			      uint32_t max, uint32_t min, uint32_t bytes)
 {
+	u32 *fifo_mem = vmw->fifo_mem;
 	uint32_t chunk_size = max - next_cmd;
 	uint32_t rest;
 	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 	if (bytes < chunk_size)
 		chunk_size = bytes;
-	vmw_mmio_write(bytes, fifo_mem + SVGA_FIFO_RESERVED);
+	vmw_fifo_mem_write(vmw, SVGA_FIFO_RESERVED, bytes);
 	mb();
 	memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
 	rest = bytes - chunk_size;
 }
 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
-			       u32  *fifo_mem,
+			       struct vmw_private *vmw,
 			       uint32_t next_cmd,
 			       uint32_t max, uint32_t min, uint32_t bytes)
 {
 	    fifo_state->dynamic_buffer : fifo_state->static_buffer;
 	while (bytes > 0) {
-		vmw_mmio_write(*buffer++, fifo_mem + (next_cmd >> 2));
+		vmw_fifo_mem_write(vmw, (next_cmd >> 2), *buffer++);
 		next_cmd += sizeof(uint32_t);
 		if (unlikely(next_cmd == max))
 			next_cmd = min;
 		mb();
-		vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
+		vmw_fifo_mem_write(vmw, SVGA_FIFO_NEXT_CMD, next_cmd);
 		mb();
 		bytes -= sizeof(uint32_t);
 	}
 static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
 {
 	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
-	u32  *fifo_mem = dev_priv->mmio_virt;
+	uint32_t next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);
-	uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
+	uint32_t max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
-	uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
+	uint32_t min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
-	uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
 	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 	if (fifo_state->dx)
 	if (fifo_state->using_bounce_buffer) {
 		if (reserveable)
-			vmw_fifo_res_copy(fifo_state, fifo_mem,
+			vmw_fifo_res_copy(fifo_state, dev_priv,
 					  next_cmd, max, min, bytes);
 		else
-			vmw_fifo_slow_copy(fifo_state, fifo_mem,
+			vmw_fifo_slow_copy(fifo_state, dev_priv,
 					   next_cmd, max, min, bytes);
 		if (fifo_state->dynamic_buffer) {
 		if (next_cmd >= max)
 			next_cmd -= max - min;
 		mb();
-		vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
+		vmw_fifo_mem_write(dev_priv, SVGA_FIFO_NEXT_CMD, next_cmd);
 	}
 	if (reserveable)
-		vmw_mmio_write(0, fifo_mem + SVGA_FIFO_RESERVED);
+		vmw_fifo_mem_write(dev_priv, SVGA_FIFO_RESERVED, 0);
 	mb();
 	up_write(&fifo_state->rwsem);
 	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
 	mutex_unlock(&fifo_state->fifo_mutex);
 }
-void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
+void vmw_cmd_commit(struct vmw_private *dev_priv, uint32_t bytes)
 {
 	if (dev_priv->cman)
 		vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false);
  * @dev_priv: Pointer to device private structure.
  * @bytes: Number of bytes to commit.
  */
-void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)
+void vmw_cmd_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)
 {
 	if (dev_priv->cman)
 		vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true);
  * @dev_priv: Pointer to device private structure.
  * @interruptible: Whether to wait interruptible if function needs to sleep.
  */
-int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible)
+int vmw_cmd_flush(struct vmw_private *dev_priv, bool interruptible)
 {
 	might_sleep();
 		return 0;
 }
-int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
+int vmw_cmd_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
 {
 	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 	struct svga_fifo_cmd_fence *cmd_fence;
 	int ret = 0;
 	uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence);
-	fm = VMW_FIFO_RESERVE(dev_priv, bytes);
+	fm = VMW_CMD_RESERVE(dev_priv, bytes);
 	if (unlikely(fm == NULL)) {
 		*seqno = atomic_read(&dev_priv->marker_seq);
 		ret = -ENOMEM;
 		 * waiting code in vmwgfx_irq.c will emulate this.
 		 */
-		vmw_fifo_commit(dev_priv, 0);
+		vmw_cmd_commit(dev_priv, 0);
 		return 0;
 	}
 	*fm++ = SVGA_CMD_FENCE;
 	cmd_fence = (struct svga_fifo_cmd_fence *) fm;
 	cmd_fence->fence = *seqno;
-	vmw_fifo_commit_flush(dev_priv, bytes);
+	vmw_cmd_commit_flush(dev_priv, bytes);
-	(void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
 	vmw_update_seqno(dev_priv, fifo_state);
 out_err:
 		SVGA3dCmdWaitForQuery body;
 	} *cmd;
-	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
+	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
 	if (unlikely(cmd == NULL))
 		return -ENOMEM;
 		cmd->body.guestResult.offset = 0;
 	}
-	vmw_fifo_commit(dev_priv, sizeof(*cmd));
+	vmw_cmd_commit(dev_priv, sizeof(*cmd));
 	return 0;
 }
 		SVGA3dCmdWaitForGBQuery body;
 	} *cmd;
-	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
+	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
 	if (unlikely(cmd == NULL))
 		return -ENOMEM;
 	cmd->body.mobid = bo->mem.start;
 	cmd->body.offset = 0;
-	vmw_fifo_commit(dev_priv, sizeof(*cmd));
+	vmw_cmd_commit(dev_priv, sizeof(*cmd));
 	return 0;
 }
  *
  * Returns -ENOMEM on failure to reserve fifo space.
  */
-int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
+int vmw_cmd_emit_dummy_query(struct vmw_private *dev_priv,
 			      uint32_t cid)
 {
 	if (dev_priv->has_mob)

drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c+9−13

 	/* Send a new fence in case one was removed */
 	if (send_fence) {
-		vmw_fifo_send_fence(man->dev_priv, &dummy);
+		vmw_cmd_send_fence(man->dev_priv, &dummy);
 		wake_up_all(&man->idle_queue);
 	}
  *
  * @man: The command buffer manager.
  * @size: The size of the main space pool.
- * @default_size: The default size of the command buffer for small kernel
- * submissions.
  *
- * Set the size and allocate the main command buffer space pool,
+ * Set the size and allocate the main command buffer space pool.
- * as well as the default size of the command buffer for
+ * If successful, this enables large command submissions.
- * small kernel submissions. If successful, this enables large command
+ * Note that this function requires that rudimentary command
- * submissions. Note that this function requires that rudimentary command
  * submission is already available and that the MOB memory manager is alive.
  * Returns 0 on success. Negative error code on failure.
  */
-int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man,
+int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man, size_t size)
-			     size_t size, size_t default_size)
 {
 	struct vmw_private *dev_priv = man->dev_priv;
 	bool dummy;
 	/* First, try to allocate a huge chunk of DMA memory */
 	size = PAGE_ALIGN(size);
-	man->map = dma_alloc_coherent(&dev_priv->dev->pdev->dev, size,
+	man->map = dma_alloc_coherent(dev_priv->drm.dev, size,
 				      &man->handle, GFP_KERNEL);
 	if (man->map) {
 		man->using_mob = false;
 	man->num_contexts = (dev_priv->capabilities & SVGA_CAP_HP_CMD_QUEUE) ?
 		2 : 1;
 	man->headers = dma_pool_create("vmwgfx cmdbuf",
-				       &dev_priv->dev->pdev->dev,
+				       dev_priv->drm.dev,
 				       sizeof(SVGACBHeader),
 				       64, PAGE_SIZE);
 	if (!man->headers) {
 	}
 	man->dheaders = dma_pool_create("vmwgfx inline cmdbuf",
-					&dev_priv->dev->pdev->dev,
+					dev_priv->drm.dev,
 					sizeof(struct vmw_cmdbuf_dheader),
 					64, PAGE_SIZE);
 	if (!man->dheaders) {
 		ttm_bo_put(man->cmd_space);
 		man->cmd_space = NULL;
 	} else {
-		dma_free_coherent(&man->dev_priv->dev->pdev->dev,
+		dma_free_coherent(man->dev_priv->drm.dev,
 				  man->size, man->map, man->handle);
 	}
 }

drivers/gpu/drm/vmwgfx/vmwgfx_context.c+20−20

@@ -163,7 +163,7 @@ static void vmw_hw_context_destroy(struct vmw_resource *res) · 162 unmodified lines
163	}	163	}
164		164
165	vmw_execbuf_release_pinned_bo(dev_priv);	165	vmw_execbuf_release_pinned_bo(dev_priv);
166	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	166	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
167	if (unlikely(cmd == NULL))	167	if (unlikely(cmd == NULL))
168	return;	168	return;
169		169
@@ -171,7 +171,7 @@ static void vmw_hw_context_destroy(struct vmw_resource *res) · 1 unmodified line
171	cmd->header.size = sizeof(cmd->body);	171	cmd->header.size = sizeof(cmd->body);
172	cmd->body.cid = res->id;	172	cmd->body.cid = res->id;
173		173
174	vmw_fifo_commit(dev_priv, sizeof(*cmd));	174	vmw_cmd_commit(dev_priv, sizeof(*cmd));
175	vmw_fifo_resource_dec(dev_priv);	175	vmw_fifo_resource_dec(dev_priv);
176	}	176	}
177		177
@@ -265,7 +265,7 @@ static int vmw_context_init(struct vmw_private *dev_priv, · 87 unmodified lines
265	return -ENOMEM;	265	return -ENOMEM;
266	}	266	}
267		267
268	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	268	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
269	if (unlikely(cmd == NULL)) {	269	if (unlikely(cmd == NULL)) {
270	vmw_resource_unreference(&res);	270	vmw_resource_unreference(&res);
271	return -ENOMEM;	271	return -ENOMEM;
@@ -275,7 +275,7 @@ static int vmw_context_init(struct vmw_private *dev_priv, · 3 unmodified lines
275	cmd->header.size = sizeof(cmd->body);	275	cmd->header.size = sizeof(cmd->body);
276	cmd->body.cid = res->id;	276	cmd->body.cid = res->id;
277		277
278	vmw_fifo_commit(dev_priv, sizeof(*cmd));	278	vmw_cmd_commit(dev_priv, sizeof(*cmd));
279	vmw_fifo_resource_inc(dev_priv);	279	vmw_fifo_resource_inc(dev_priv);
280	res->hw_destroy = vmw_hw_context_destroy;	280	res->hw_destroy = vmw_hw_context_destroy;
281	return 0;	281	return 0;
@@ -316,7 +316,7 @@ static int vmw_gb_context_create(struct vmw_resource *res) · 34 unmodified lines
316	goto out_no_fifo;	316	goto out_no_fifo;
317	}	317	}
318		318
319	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	319	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
320	if (unlikely(cmd == NULL)) {	320	if (unlikely(cmd == NULL)) {
321	ret = -ENOMEM;	321	ret = -ENOMEM;
322	goto out_no_fifo;	322	goto out_no_fifo;
@@ -325,7 +325,7 @@ static int vmw_gb_context_create(struct vmw_resource *res) · 2 unmodified lines
325	cmd->header.id = SVGA_3D_CMD_DEFINE_GB_CONTEXT;	325	cmd->header.id = SVGA_3D_CMD_DEFINE_GB_CONTEXT;
326	cmd->header.size = sizeof(cmd->body);	326	cmd->header.size = sizeof(cmd->body);
327	cmd->body.cid = res->id;	327	cmd->body.cid = res->id;
328	vmw_fifo_commit(dev_priv, sizeof(*cmd));	328	vmw_cmd_commit(dev_priv, sizeof(*cmd));
329	vmw_fifo_resource_inc(dev_priv);	329	vmw_fifo_resource_inc(dev_priv);
330		330
331	return 0;	331	return 0;
@@ -348,7 +348,7 @@ static int vmw_gb_context_bind(struct vmw_resource *res, · 16 unmodified lines
348		348
349	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);	349	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
350		350
351	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	351	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
352	if (unlikely(cmd == NULL))	352	if (unlikely(cmd == NULL))
353	return -ENOMEM;	353	return -ENOMEM;
354		354
@@ -358,7 +358,7 @@ static int vmw_gb_context_bind(struct vmw_resource *res, · 3 unmodified lines
358	cmd->body.mobid = bo->mem.start;	358	cmd->body.mobid = bo->mem.start;
359	cmd->body.validContents = res->backup_dirty;	359	cmd->body.validContents = res->backup_dirty;
360	res->backup_dirty = false;	360	res->backup_dirty = false;
361	vmw_fifo_commit(dev_priv, sizeof(*cmd));	361	vmw_cmd_commit(dev_priv, sizeof(*cmd));
362		362
363	return 0;	363	return 0;
364	}	364	}
@@ -392,7 +392,7 @@ static int vmw_gb_context_unbind(struct vmw_resource *res, · 27 unmodified lines
392		392
393	submit_size = sizeof(cmd2) + (readback ? sizeof(cmd1) : 0);	393	submit_size = sizeof(cmd2) + (readback ? sizeof(cmd1) : 0);
394		394
395	cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);	395	cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
396	if (unlikely(cmd == NULL)) {	396	if (unlikely(cmd == NULL)) {
397	mutex_unlock(&dev_priv->binding_mutex);	397	mutex_unlock(&dev_priv->binding_mutex);
398	return -ENOMEM;	398	return -ENOMEM;
@@ -411,7 +411,7 @@ static int vmw_gb_context_unbind(struct vmw_resource *res, · 12 unmodified lines
411	cmd2->body.cid = res->id;	411	cmd2->body.cid = res->id;
412	cmd2->body.mobid = SVGA3D_INVALID_ID;	412	cmd2->body.mobid = SVGA3D_INVALID_ID;
413		413
414	vmw_fifo_commit(dev_priv, submit_size);	414	vmw_cmd_commit(dev_priv, submit_size);
415	mutex_unlock(&dev_priv->binding_mutex);	415	mutex_unlock(&dev_priv->binding_mutex);
416		416
417	/*	417	/*
@@ -440,14 +440,14 @@ static int vmw_gb_context_destroy(struct vmw_resource *res) · 22 unmodified lines
440	if (likely(res->id == -1))	440	if (likely(res->id == -1))
441	return 0;	441	return 0;
442		442
443	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	443	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
444	if (unlikely(cmd == NULL))	444	if (unlikely(cmd == NULL))
445	return -ENOMEM;	445	return -ENOMEM;
446		446
447	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_CONTEXT;	447	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_CONTEXT;
448	cmd->header.size = sizeof(cmd->body);	448	cmd->header.size = sizeof(cmd->body);
449	cmd->body.cid = res->id;	449	cmd->body.cid = res->id;
450	vmw_fifo_commit(dev_priv, sizeof(*cmd));	450	vmw_cmd_commit(dev_priv, sizeof(*cmd));
451	if (dev_priv->query_cid == res->id)	451	if (dev_priv->query_cid == res->id)
452	dev_priv->query_cid_valid = false;	452	dev_priv->query_cid_valid = false;
453	vmw_resource_release_id(res);	453	vmw_resource_release_id(res);
@@ -483,7 +483,7 @@ static int vmw_dx_context_create(struct vmw_resource *res) · 29 unmodified lines
483	goto out_no_fifo;	483	goto out_no_fifo;
484	}	484	}
485		485
486	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	486	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
487	if (unlikely(cmd == NULL)) {	487	if (unlikely(cmd == NULL)) {
488	ret = -ENOMEM;	488	ret = -ENOMEM;
489	goto out_no_fifo;	489	goto out_no_fifo;
@@ -492,7 +492,7 @@ static int vmw_dx_context_create(struct vmw_resource *res) · 2 unmodified lines
492	cmd->header.id = SVGA_3D_CMD_DX_DEFINE_CONTEXT;	492	cmd->header.id = SVGA_3D_CMD_DX_DEFINE_CONTEXT;
493	cmd->header.size = sizeof(cmd->body);	493	cmd->header.size = sizeof(cmd->body);
494	cmd->body.cid = res->id;	494	cmd->body.cid = res->id;
495	vmw_fifo_commit(dev_priv, sizeof(*cmd));	495	vmw_cmd_commit(dev_priv, sizeof(*cmd));
496	vmw_fifo_resource_inc(dev_priv);	496	vmw_fifo_resource_inc(dev_priv);
497		497
498	return 0;	498	return 0;
@@ -515,7 +515,7 @@ static int vmw_dx_context_bind(struct vmw_resource *res, · 16 unmodified lines
515		515
516	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);	516	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
517		517
518	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	518	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
519	if (unlikely(cmd == NULL))	519	if (unlikely(cmd == NULL))
520	return -ENOMEM;	520	return -ENOMEM;
521		521
@@ -525,7 +525,7 @@ static int vmw_dx_context_bind(struct vmw_resource *res, · 3 unmodified lines
525	cmd->body.mobid = bo->mem.start;	525	cmd->body.mobid = bo->mem.start;
526	cmd->body.validContents = res->backup_dirty;	526	cmd->body.validContents = res->backup_dirty;
527	res->backup_dirty = false;	527	res->backup_dirty = false;
528	vmw_fifo_commit(dev_priv, sizeof(*cmd));	528	vmw_cmd_commit(dev_priv, sizeof(*cmd));
529		529
530		530
531	return 0;	531	return 0;
@@ -608,7 +608,7 @@ static int vmw_dx_context_unbind(struct vmw_resource *res, · 76 unmodified lines
608		608
609	submit_size = sizeof(cmd2) + (readback ? sizeof(cmd1) : 0);	609	submit_size = sizeof(cmd2) + (readback ? sizeof(cmd1) : 0);
610		610
611	cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);	611	cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
612	if (unlikely(cmd == NULL)) {	612	if (unlikely(cmd == NULL)) {
613	mutex_unlock(&dev_priv->binding_mutex);	613	mutex_unlock(&dev_priv->binding_mutex);
614	return -ENOMEM;	614	return -ENOMEM;
@@ -627,7 +627,7 @@ static int vmw_dx_context_unbind(struct vmw_resource *res, · 12 unmodified lines
627	cmd2->body.cid = res->id;	627	cmd2->body.cid = res->id;
628	cmd2->body.mobid = SVGA3D_INVALID_ID;	628	cmd2->body.mobid = SVGA3D_INVALID_ID;
629		629
630	vmw_fifo_commit(dev_priv, submit_size);	630	vmw_cmd_commit(dev_priv, submit_size);
631	mutex_unlock(&dev_priv->binding_mutex);	631	mutex_unlock(&dev_priv->binding_mutex);
632		632
633	/*	633	/*
@@ -656,14 +656,14 @@ static int vmw_dx_context_destroy(struct vmw_resource *res) · 22 unmodified lines
656	if (likely(res->id == -1))	656	if (likely(res->id == -1))
657	return 0;	657	return 0;
658		658
659	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	659	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
660	if (unlikely(cmd == NULL))	660	if (unlikely(cmd == NULL))
661	return -ENOMEM;	661	return -ENOMEM;
662		662
663	cmd->header.id = SVGA_3D_CMD_DX_DESTROY_CONTEXT;	663	cmd->header.id = SVGA_3D_CMD_DX_DESTROY_CONTEXT;
664	cmd->header.size = sizeof(cmd->body);	664	cmd->header.size = sizeof(cmd->body);
665	cmd->body.cid = res->id;	665	cmd->body.cid = res->id;
666	vmw_fifo_commit(dev_priv, sizeof(*cmd));	666	vmw_cmd_commit(dev_priv, sizeof(*cmd));
667	if (dev_priv->query_cid == res->id)	667	if (dev_priv->query_cid == res->id)
668	dev_priv->query_cid_valid = false;	668	dev_priv->query_cid_valid = false;
669	vmw_resource_release_id(res);	669	vmw_resource_release_id(res);

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c+6−6

@@ -175,7 +175,7 @@ static int vmw_cotable_unscrub(struct vmw_resource *res) · 174 unmodified lines
175	WARN_ON_ONCE(bo->mem.mem_type != VMW_PL_MOB);	175	WARN_ON_ONCE(bo->mem.mem_type != VMW_PL_MOB);
176	dma_resv_assert_held(bo->base.resv);	176	dma_resv_assert_held(bo->base.resv);
177		177
178	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	178	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
179	if (!cmd)	179	if (!cmd)
180	return -ENOMEM;	180	return -ENOMEM;
181		181
@@ -188,7 +188,7 @@ static int vmw_cotable_unscrub(struct vmw_resource *res) · 6 unmodified lines
188	cmd->body.mobid = bo->mem.start;	188	cmd->body.mobid = bo->mem.start;
189	cmd->body.validSizeInBytes = vcotbl->size_read_back;	189	cmd->body.validSizeInBytes = vcotbl->size_read_back;
190		190
191	vmw_fifo_commit_flush(dev_priv, sizeof(*cmd));	191	vmw_cmd_commit_flush(dev_priv, sizeof(*cmd));
192	vcotbl->scrubbed = false;	192	vcotbl->scrubbed = false;
193		193
194	return 0;	194	return 0;
@@ -263,7 +263,7 @@ int vmw_cotable_scrub(struct vmw_resource *res, bool readback) · 68 unmodified lines
263	if (readback)	263	if (readback)
264	submit_size += sizeof(*cmd0);	264	submit_size += sizeof(*cmd0);
265		265
266	cmd1 = VMW_FIFO_RESERVE(dev_priv, submit_size);	266	cmd1 = VMW_CMD_RESERVE(dev_priv, submit_size);
267	if (!cmd1)	267	if (!cmd1)
268	return -ENOMEM;	268	return -ENOMEM;
269		269
@@ -283,7 +283,7 @@ int vmw_cotable_scrub(struct vmw_resource *res, bool readback) · 13 unmodified lines
283	cmd1->body.type = vcotbl->type;	283	cmd1->body.type = vcotbl->type;
284	cmd1->body.mobid = SVGA3D_INVALID_ID;	284	cmd1->body.mobid = SVGA3D_INVALID_ID;
285	cmd1->body.validSizeInBytes = 0;	285	cmd1->body.validSizeInBytes = 0;
286	vmw_fifo_commit_flush(dev_priv, submit_size);	286	vmw_cmd_commit_flush(dev_priv, submit_size);
287	vcotbl->scrubbed = true;	287	vcotbl->scrubbed = true;
288		288
289	/* Trigger a create() on next validate. */	289	/* Trigger a create() on next validate. */
@@ -349,7 +349,7 @@ static int vmw_cotable_readback(struct vmw_resource *res) · 59 unmodified lines
349	struct vmw_fence_obj *fence;	349	struct vmw_fence_obj *fence;
350		350
351	if (!vcotbl->scrubbed) {	351	if (!vcotbl->scrubbed) {
352	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	352	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
353	if (!cmd)	353	if (!cmd)
354	return -ENOMEM;	354	return -ENOMEM;
355		355
@@ -358,7 +358,7 @@ static int vmw_cotable_readback(struct vmw_resource *res) · 2 unmodified lines
358	cmd->body.cid = vcotbl->ctx->id;	358	cmd->body.cid = vcotbl->ctx->id;
359	cmd->body.type = vcotbl->type;	359	cmd->body.type = vcotbl->type;
360	vcotbl->size_read_back = res->backup_size;	360	vcotbl->size_read_back = res->backup_size;
361	vmw_fifo_commit(dev_priv, sizeof(*cmd));	361	vmw_cmd_commit(dev_priv, sizeof(*cmd));
362	}	362	}
363		363
364	(void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);	364	(void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c+113−122

 #include <linux/mem_encrypt.h>
 #include <drm/drm_drv.h>
+#include <drm/drm_fb_helper.h>
 #include <drm/drm_ioctl.h>
 #include <drm/drm_sysfs.h>
 #include <drm/ttm/ttm_bo_driver.h>
 #include "vmwgfx_drv.h"
 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
-#define VMWGFX_CHIP_SVGAII 0
-#define VMW_FB_RESERVATION 0
 #define VMW_MIN_INITIAL_WIDTH 800
 #define VMW_MIN_INITIAL_HEIGHT 600
 };
 static const struct pci_device_id vmw_pci_id_list[] = {
-	{0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
+	{ PCI_DEVICE(0x15ad, VMWGFX_PCI_ID_SVGA2) },
-	{0, 0, 0}
+	{ }
 };
 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
 	}
 	if (dev_priv->cman) {
-		ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
+		ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096);
-					       256*4096, 2*4096);
 		if (ret) {
 			struct vmw_cmdbuf_man *man = dev_priv->cman;
  */
 static int vmw_dma_masks(struct vmw_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
+	struct drm_device *dev = &dev_priv->drm;
 	int ret = 0;
 	ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
 #endif
 }
-static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
+static int vmw_setup_pci_resources(struct vmw_private *dev,
+				   unsigned long pci_id)
 {
-	struct vmw_private *dev_priv;
+	resource_size_t fifo_start;
+	resource_size_t fifo_size;
 	int ret;
+	struct pci_dev *pdev = to_pci_dev(dev->drm.dev);
+	pci_set_master(pdev);
+	ret = pci_request_regions(pdev, "vmwgfx probe");
+	if (ret)
+		return ret;
+	dev->io_start = pci_resource_start(pdev, 0);
+	dev->vram_start = pci_resource_start(pdev, 1);
+	dev->vram_size = pci_resource_len(pdev, 1);
+	fifo_start = pci_resource_start(pdev, 2);
+	fifo_size = pci_resource_len(pdev, 2);
+	DRM_INFO("FIFO at %pa size is %llu kiB\n",
+		 &fifo_start, (uint64_t)fifo_size / 1024);
+	dev->fifo_mem = devm_memremap(dev->drm.dev,
+				      fifo_start,
+				      fifo_size,
+				      MEMREMAP_WB);
+	if (unlikely(dev->fifo_mem == NULL)) {
+		DRM_ERROR("Failed mapping FIFO memory.\n");
+		return -ENOMEM;
+	}
+	/*
+	 * This is approximate size of the vram, the exact size will only
+	 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource
+	 * size will be equal to or bigger than the size reported by
+	 * SVGA_REG_VRAM_SIZE.
+	 */
+	DRM_INFO("VRAM at %pa size is %llu kiB\n",
+		 &dev->vram_start, (uint64_t)dev->vram_size / 1024);
+	return 0;
+}
+static int vmw_detect_version(struct vmw_private *dev)
+{
 	uint32_t svga_id;
+	vmw_write(dev, SVGA_REG_ID, SVGA_ID_2);
+	svga_id = vmw_read(dev, SVGA_REG_ID);
+	if (svga_id != SVGA_ID_2) {
+		DRM_ERROR("Unsupported SVGA ID 0x%x on chipset 0x%x\n",
+			  svga_id, dev->vmw_chipset);
+		return -ENOSYS;
+	}
+	return 0;
+}
+static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
+{
+	int ret;
 	enum vmw_res_type i;
 	bool refuse_dma = false;
 	char host_log[100] = {0};
+	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
-	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
+	dev_priv->vmw_chipset = pci_id;
-	if (unlikely(!dev_priv)) {
+	dev_priv->last_read_seqno = (uint32_t) -100;
-		DRM_ERROR("Failed allocating a device private struct.\n");
+	dev_priv->drm.dev_private = dev_priv;
-		return -ENOMEM;
-	}
-	pci_set_master(dev->pdev);
+	ret = vmw_setup_pci_resources(dev_priv, pci_id);
+	if (ret)
+		return ret;
+	ret = vmw_detect_version(dev_priv);
+	if (ret)
+		return ret;
-	dev_priv->dev = dev;
-	dev_priv->vmw_chipset = chipset;
-	dev_priv->last_read_seqno = (uint32_t) -100;
 	mutex_init(&dev_priv->cmdbuf_mutex);
 	mutex_init(&dev_priv->release_mutex);
 	mutex_init(&dev_priv->binding_mutex);
 	spin_lock_init(&dev_priv->hw_lock);
 	spin_lock_init(&dev_priv->waiter_lock);
 	spin_lock_init(&dev_priv->cap_lock);
-	spin_lock_init(&dev_priv->svga_lock);
 	spin_lock_init(&dev_priv->cursor_lock);
 	for (i = vmw_res_context; i < vmw_res_max; ++i) {
 	dev_priv->used_memory_size = 0;
-	dev_priv->io_start = pci_resource_start(dev->pdev, 0);
-	dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
-	dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 	dev_priv->assume_16bpp = !!vmw_assume_16bpp;
 	dev_priv->enable_fb = enable_fbdev;
-	vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
-	svga_id = vmw_read(dev_priv, SVGA_REG_ID);
-	if (svga_id != SVGA_ID_2) {
-		ret = -ENOSYS;
-		DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
-		goto out_err0;
-	}
 	dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 	}
 	dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
-	dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
+	dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 	dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 	dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 	if (unlikely(ret != 0))
 		goto out_err0;
-	dma_set_max_seg_size(dev->dev, U32_MAX);
+	dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);
 	if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 		DRM_INFO("Max GMR ids is %u\n",
 		DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 			 (unsigned)dev_priv->memory_size / 1024);
 	}
-	DRM_INFO("Maximum display memory size is %u kiB\n",
+	DRM_INFO("Maximum display memory size is %llu kiB\n",
-		 dev_priv->prim_bb_mem / 1024);
+		 (uint64_t)dev_priv->prim_bb_mem / 1024);
-	DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
-		 dev_priv->vram_start, dev_priv->vram_size / 1024);
-	DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
-		 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
-	dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
-				       dev_priv->mmio_size, MEMREMAP_WB);
-	if (unlikely(dev_priv->mmio_virt == NULL)) {
-		ret = -ENOMEM;
-		DRM_ERROR("Failed mapping MMIO.\n");
-		goto out_err0;
-	}
 	/* Need mmio memory to check for fifo pitchlock cap. */
 	if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 	    !vmw_fifo_have_pitchlock(dev_priv)) {
 		ret = -ENOSYS;
 		DRM_ERROR("Hardware has no pitchlock\n");
-		goto out_err4;
+		goto out_err0;
 	}
 	dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12,
 	if (unlikely(dev_priv->tdev == NULL)) {
 		DRM_ERROR("Unable to initialize TTM object management.\n");
 		ret = -ENOMEM;
-		goto out_err4;
+		goto out_err0;
-	}
-	dev->dev_private = dev_priv;
-	ret = pci_request_regions(dev->pdev, "vmwgfx probe");
-	dev_priv->stealth = (ret != 0);
-	if (dev_priv->stealth) {
-		/**
-		 * Request at least the mmio PCI resource.
-		 */
-		DRM_INFO("It appears like vesafb is loaded. "
-			 "Ignore above error if any.\n");
-		ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
-		if (unlikely(ret != 0)) {
-			DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
-			goto out_no_device;
-		}
 	}
 	if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
-		ret = vmw_irq_install(dev, dev->pdev->irq);
+		ret = vmw_irq_install(&dev_priv->drm, pdev->irq);
 		if (ret != 0) {
 			DRM_ERROR("Failed installing irq: %d\n", ret);
 			goto out_no_irq;
 				    DRM_FILE_PAGE_OFFSET_START,
 				    DRM_FILE_PAGE_OFFSET_SIZE);
 	ret = ttm_bo_device_init(&dev_priv->bdev, &vmw_bo_driver,
-				 dev_priv->dev->dev,
+				 dev_priv->drm.dev,
-				 dev->anon_inode->i_mapping,
+				 dev_priv->drm.anon_inode->i_mapping,
 				 &dev_priv->vma_manager,
 				 dev_priv->map_mode == vmw_dma_alloc_coherent,
 				 false);
 	if (ret)
 		goto out_no_fifo;
-	DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC)
+	DRM_INFO("Atomic: %s\n", (dev_priv->drm.driver->driver_features & DRIVER_ATOMIC)
 		 ? "yes." : "no.");
 	if (dev_priv->sm_type == VMW_SM_5)
 		DRM_INFO("SM5 support available.\n");
 	vmw_fence_manager_takedown(dev_priv->fman);
 out_no_fman:
 	if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
-		vmw_irq_uninstall(dev_priv->dev);
+		vmw_irq_uninstall(&dev_priv->drm);
 out_no_irq:
-	if (dev_priv->stealth)
+	pci_release_regions(pdev);
-		pci_release_region(dev->pdev, 2);
-	else
-		pci_release_regions(dev->pdev);
-out_no_device:
 	ttm_object_device_release(&dev_priv->tdev);
-out_err4:
-	memunmap(dev_priv->mmio_virt);
 out_err0:
 	for (i = vmw_res_context; i < vmw_res_max; ++i)
 		idr_destroy(&dev_priv->res_idr[i]);
 static void vmw_driver_unload(struct drm_device *dev)
 {
 	struct vmw_private *dev_priv = vmw_priv(dev);
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	enum vmw_res_type i;
 	unregister_pm_notifier(&dev_priv->pm_nb);
 	vmw_release_device_late(dev_priv);
 	vmw_fence_manager_takedown(dev_priv->fman);
 	if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
-		vmw_irq_uninstall(dev_priv->dev);
+		vmw_irq_uninstall(&dev_priv->drm);
-	if (dev_priv->stealth)
+	pci_release_regions(pdev);
-		pci_release_region(dev->pdev, 2);
-	else
-		pci_release_regions(dev->pdev);
 	ttm_object_device_release(&dev_priv->tdev);
-	memunmap(dev_priv->mmio_virt);
 	if (dev_priv->ctx.staged_bindings)
 		vmw_binding_state_free(dev_priv->ctx.staged_bindings);
 {
 	struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
-	spin_lock(&dev_priv->svga_lock);
 	if (!ttm_resource_manager_used(man)) {
 		vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
 		ttm_resource_manager_set_used(man, true);
 	}
-	spin_unlock(&dev_priv->svga_lock);
 }
 /**
 {
 	struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
-	spin_lock(&dev_priv->svga_lock);
 	if (ttm_resource_manager_used(man)) {
 		ttm_resource_manager_set_used(man, false);
 		vmw_write(dev_priv, SVGA_REG_ENABLE,
 			  SVGA_REG_ENABLE_HIDE |
 			  SVGA_REG_ENABLE_ENABLE);
 	}
-	spin_unlock(&dev_priv->svga_lock);
 }
 /**
 	 * to be inconsistent with the device, causing modesetting problems.
 	 *
 	 */
-	vmw_kms_lost_device(dev_priv->dev);
+	vmw_kms_lost_device(&dev_priv->drm);
 	ttm_write_lock(&dev_priv->reservation_sem, false);
-	spin_lock(&dev_priv->svga_lock);
 	if (ttm_resource_manager_used(man)) {
-		ttm_resource_manager_set_used(man, false);
-		spin_unlock(&dev_priv->svga_lock);
 		if (ttm_resource_manager_evict_all(&dev_priv->bdev, man))
 			DRM_ERROR("Failed evicting VRAM buffers.\n");
+		ttm_resource_manager_set_used(man, false);
 		vmw_write(dev_priv, SVGA_REG_ENABLE,
 			  SVGA_REG_ENABLE_HIDE |
 			  SVGA_REG_ENABLE_ENABLE);
-	} else
+	}
-		spin_unlock(&dev_priv->svga_lock);
 	ttm_write_unlock(&dev_priv->reservation_sem);
 }
 	drm_dev_unregister(dev);
 	vmw_driver_unload(dev);
-	drm_dev_put(dev);
-	pci_disable_device(pdev);
 }
 static unsigned long
 	 * No user-space processes should be running now.
 	 */
 	ttm_suspend_unlock(&dev_priv->reservation_sem);
-	ret = vmw_kms_suspend(dev_priv->dev);
+	ret = vmw_kms_suspend(&dev_priv->drm);
 	if (ret) {
 		ttm_suspend_lock(&dev_priv->reservation_sem);
 		DRM_ERROR("Failed to freeze modesetting.\n");
 	vmw_fence_fifo_down(dev_priv->fman);
 	__vmw_svga_disable(dev_priv);
 	vmw_release_device_late(dev_priv);
 	return 0;
 }
 	dev_priv->suspend_locked = false;
 	ttm_suspend_unlock(&dev_priv->reservation_sem);
 	if (dev_priv->suspend_state)
-		vmw_kms_resume(dev_priv->dev);
+		vmw_kms_resume(&dev_priv->drm);
 	if (dev_priv->enable_fb)
 		vmw_fb_on(dev_priv);
 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
-	struct drm_device *dev;
+	struct vmw_private *vmw;
 	int ret;
-	ret = pci_enable_device(pdev);
+	ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "svgadrmfb");
 	if (ret)
 		return ret;
-	dev = drm_dev_alloc(&driver, &pdev->dev);
+	ret = pcim_enable_device(pdev);
-	if (IS_ERR(dev)) {
+	if (ret)
-		ret = PTR_ERR(dev);
+		return ret;
-		goto err_pci_disable_device;
-	}
-	dev->pdev = pdev;
+	vmw = devm_drm_dev_alloc(&pdev->dev, &driver,
-	pci_set_drvdata(pdev, dev);
+				 struct vmw_private, drm);
+	if (IS_ERR(vmw))
+		return PTR_ERR(vmw);
-	ret = vmw_driver_load(dev, ent->driver_data);
+	vmw->drm.pdev = pdev;
-	if (ret)
+	pci_set_drvdata(pdev, &vmw->drm);
-		goto err_drm_dev_put;
-	ret = drm_dev_register(dev, ent->driver_data);
+	ret = vmw_driver_load(vmw, ent->device);
 	if (ret)
-		goto err_vmw_driver_unload;
+		return ret;
-	return 0;
+	ret = drm_dev_register(&vmw->drm, 0);
+	if (ret) {
+		vmw_driver_unload(&vmw->drm);
+		return ret;
+	}
-err_vmw_driver_unload:
+	return 0;
-	vmw_driver_unload(dev);
-err_drm_dev_put:
-	drm_dev_put(dev);
-err_pci_disable_device:
-	pci_disable_device(pdev);
-	return ret;
 }
 static int __init vmwgfx_init(void)

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h+33−60

 #define VMWGFX_CMD_BOUNCE_INIT_SIZE 32768
 #define VMWGFX_ENABLE_SCREEN_TARGET_OTABLE 1
+#define VMWGFX_PCI_ID_SVGA2              0x0405
 /*
  * Perhaps we should have sysfs entries for these.
  */
 	struct list_head view_list;
 };
-struct vmw_marker_queue {
-	struct list_head head;
-	u64 lag;
-	u64 lag_time;
-	spinlock_t lock;
-};
 struct vmw_fifo_state {
 	unsigned long reserved_size;
 	u32 *dynamic_buffer;
 	uint32_t capabilities;
 	struct mutex fifo_mutex;
 	struct rw_semaphore rwsem;
-	struct vmw_marker_queue marker_queue;
 	bool dx;
 };
 };
 struct vmw_private {
+	struct drm_device drm;
 	struct ttm_bo_device bdev;
 	struct vmw_fifo_state fifo;
-	struct drm_device *dev;
 	struct drm_vma_offset_manager vma_manager;
-	unsigned long vmw_chipset;
+	u32 vmw_chipset;
-	unsigned int io_start;
+	resource_size_t io_start;
-	uint32_t vram_start;
+	resource_size_t vram_start;
-	uint32_t vram_size;
+	resource_size_t vram_size;
-	uint32_t prim_bb_mem;
+	resource_size_t prim_bb_mem;
-	uint32_t mmio_start;
+	u32 *fifo_mem;
-	uint32_t mmio_size;
+	resource_size_t fifo_mem_size;
 	uint32_t fb_max_width;
 	uint32_t fb_max_height;
 	uint32_t texture_max_width;
 	uint32_t stdu_max_height;
 	uint32_t initial_width;
 	uint32_t initial_height;
-	u32 *mmio_virt;
 	uint32_t capabilities;
 	uint32_t capabilities2;
 	uint32_t max_gmr_ids;
 	struct mutex cmdbuf_mutex;
 	struct mutex binding_mutex;
-	/**
-	 * Operating mode.
-	 */
-	bool stealth;
 	bool enable_fb;
-	spinlock_t svga_lock;
 	/**
 	 * PM management.
 extern void vmw_fifo_release(struct vmw_private *dev_priv,
 			     struct vmw_fifo_state *fifo);
 extern void *
-vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes, int ctx_id);
+vmw_cmd_ctx_reserve(struct vmw_private *dev_priv, uint32_t bytes, int ctx_id);
-extern void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes);
+extern void vmw_cmd_commit(struct vmw_private *dev_priv, uint32_t bytes);
-extern void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes);
+extern void vmw_cmd_commit_flush(struct vmw_private *dev_priv, uint32_t bytes);
-extern int vmw_fifo_send_fence(struct vmw_private *dev_priv,
+extern int vmw_cmd_send_fence(struct vmw_private *dev_priv, uint32_t *seqno);
-			       uint32_t *seqno);
+extern bool vmw_supports_3d(struct vmw_private *dev_priv);
 extern void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason);
-extern bool vmw_fifo_have_3d(struct vmw_private *dev_priv);
 extern bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv);
-extern int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
+extern int vmw_cmd_emit_dummy_query(struct vmw_private *dev_priv,
-				     uint32_t cid);
+				    uint32_t cid);
-extern int vmw_fifo_flush(struct vmw_private *dev_priv,
+extern int vmw_cmd_flush(struct vmw_private *dev_priv,
-			  bool interruptible);
+			 bool interruptible);
-#define VMW_FIFO_RESERVE_DX(__priv, __bytes, __ctx_id)                        \
+#define VMW_CMD_CTX_RESERVE(__priv, __bytes, __ctx_id)                        \
 ({                                                                            \
-	vmw_fifo_reserve_dx(__priv, __bytes, __ctx_id) ? : ({                 \
+	vmw_cmd_ctx_reserve(__priv, __bytes, __ctx_id) ? : ({                 \
 		DRM_ERROR("FIFO reserve failed at %s for %u bytes\n",         \
 			  __func__, (unsigned int) __bytes);                  \
 		NULL;                                                         \
 	});                                                                   \
 })
-#define VMW_FIFO_RESERVE(__priv, __bytes)                                     \
+#define VMW_CMD_RESERVE(__priv, __bytes)                                     \
-	VMW_FIFO_RESERVE_DX(__priv, __bytes, SVGA3D_INVALID_ID)
+	VMW_CMD_CTX_RESERVE(__priv, __bytes, SVGA3D_INVALID_ID)
 /**
  * TTM glue - vmwgfx_ttm_glue.c
 extern void vmw_generic_waiter_remove(struct vmw_private *dev_priv,
 				      u32 flag, int *waiter_count);
-/**
- * Rudimentary fence-like objects currently used only for throttling -
- * vmwgfx_marker.c
- */
-extern void vmw_marker_queue_init(struct vmw_marker_queue *queue);
-extern void vmw_marker_queue_takedown(struct vmw_marker_queue *queue);
-extern int vmw_marker_push(struct vmw_marker_queue *queue,
-			   uint32_t seqno);
-extern int vmw_marker_pull(struct vmw_marker_queue *queue,
-			   uint32_t signaled_seqno);
-extern int vmw_wait_lag(struct vmw_private *dev_priv,
-			struct vmw_marker_queue *queue, uint32_t us);
 /**
  * Kernel framebuffer - vmwgfx_fb.c
 extern struct vmw_cmdbuf_man *
 vmw_cmdbuf_man_create(struct vmw_private *dev_priv);
-extern int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man,
+extern int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man, size_t size);
-				    size_t size, size_t default_size);
 extern void vmw_cmdbuf_remove_pool(struct vmw_cmdbuf_man *man);
 extern void vmw_cmdbuf_man_destroy(struct vmw_cmdbuf_man *man);
 extern int vmw_cmdbuf_idle(struct vmw_cmdbuf_man *man, bool interruptible,
 }
 /**
- * vmw_mmio_read - Perform a MMIO read from volatile memory
+ * vmw_fifo_mem_read - Perform a MMIO read from the fifo memory
  *
- * @addr: The address to read from
+ * @fifo_reg: The fifo register to read from
  *
  * This function is intended to be equivalent to ioread32() on
  * memremap'd memory, but without byteswapping.
  */
-static inline u32 vmw_mmio_read(u32 *addr)
+static inline u32 vmw_fifo_mem_read(struct vmw_private *vmw, uint32 fifo_reg)
 {
-	return READ_ONCE(*addr);
+	return READ_ONCE(*(vmw->fifo_mem + fifo_reg));
 }
 /**
- * vmw_mmio_write - Perform a MMIO write to volatile memory
+ * vmw_fifo_mem_write - Perform a MMIO write to volatile memory
  *
- * @addr: The address to write to
+ * @addr: The fifo register to write to
  *
  * This function is intended to be equivalent to iowrite32 on
  * memremap'd memory, but without byteswapping.
  */
-static inline void vmw_mmio_write(u32 value, u32 *addr)
+static inline void vmw_fifo_mem_write(struct vmw_private *vmw, u32 fifo_reg,
+				      u32 value)
 {
-	WRITE_ONCE(*addr, value);
+	WRITE_ONCE(*(vmw->fifo_mem + fifo_reg), value);
 }
 #endif

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c+9−13

 	if (!dx_query_mob || dx_query_mob->dx_query_ctx)
 		return 0;
-	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), ctx_res->id);
+	cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), ctx_res->id);
 	if (cmd == NULL)
 		return -ENOMEM;
 	cmd->header.size = sizeof(cmd->body);
 	cmd->body.cid = ctx_res->id;
 	cmd->body.mobid = dx_query_mob->base.mem.start;
-	vmw_fifo_commit(dev_priv, sizeof(*cmd));
+	vmw_cmd_commit(dev_priv, sizeof(*cmd));
 	vmw_context_bind_dx_query(ctx_res, dx_query_mob);
 		BUG_ON(!ctx_entry->valid);
 		ctx = ctx_entry->res;
-		ret = vmw_fifo_emit_dummy_query(dev_priv, ctx->id);
+		ret = vmw_cmd_emit_dummy_query(dev_priv, ctx->id);
 		if (unlikely(ret != 0))
 			VMW_DEBUG_USER("Out of fifo space for dummy query.\n");
 	/* p_handle implies file_priv. */
 	BUG_ON(p_handle != NULL && file_priv == NULL);
-	ret = vmw_fifo_send_fence(dev_priv, &sequence);
+	ret = vmw_cmd_send_fence(dev_priv, &sequence);
 	if (unlikely(ret != 0)) {
 		VMW_DEBUG_USER("Fence submission error. Syncing.\n");
 		synced = true;
 	void *cmd;
 	if (sw_context->dx_ctx_node)
-		cmd = VMW_FIFO_RESERVE_DX(dev_priv, command_size,
+		cmd = VMW_CMD_CTX_RESERVE(dev_priv, command_size,
 					  sw_context->dx_ctx_node->ctx->id);
 	else
-		cmd = VMW_FIFO_RESERVE(dev_priv, command_size);
+		cmd = VMW_CMD_RESERVE(dev_priv, command_size);
 	if (!cmd)
 		return -ENOMEM;
 	memcpy(cmd, kernel_commands, command_size);
 	vmw_resource_relocations_apply(cmd, &sw_context->res_relocations);
 	vmw_resource_relocations_free(&sw_context->res_relocations);
-	vmw_fifo_commit(dev_priv, command_size);
+	vmw_cmd_commit(dev_priv, command_size);
 	return 0;
 }
 	}
 	if (throttle_us) {
-		ret = vmw_wait_lag(dev_priv, &dev_priv->fifo.marker_queue,
+		VMW_DEBUG_USER("Throttling is no longer supported.\n");
-				   throttle_us);
-		if (ret)
-			goto out_free_fence_fd;
 	}
 	kernel_commands = vmw_execbuf_cmdbuf(dev_priv, user_commands,
 	if (dev_priv->query_cid_valid) {
 		BUG_ON(fence != NULL);
-		ret = vmw_fifo_emit_dummy_query(dev_priv, dev_priv->query_cid);
+		ret = vmw_cmd_emit_dummy_query(dev_priv, dev_priv->query_cid);
 		if (ret)
 			goto out_no_emit;
 		dev_priv->query_cid_valid = false;

drivers/gpu/drm/vmwgfx/vmwgfx_fb.c+6−6

@@ -258,7 +258,7 @@ out_unreserve: · 257 unmodified lines
258	if (w && h) {	258	if (w && h) {
259	WARN_ON_ONCE(par->set_fb->funcs->dirty(cur_fb, NULL, 0, 0,	259	WARN_ON_ONCE(par->set_fb->funcs->dirty(cur_fb, NULL, 0, 0,
260	&clip, 1));	260	&clip, 1));
261	vmw_fifo_flush(vmw_priv, false);	261	vmw_cmd_flush(vmw_priv, false);
262	}	262	}
263	out_unlock:	263	out_unlock:
264	mutex_unlock(&par->bo_mutex);	264	mutex_unlock(&par->bo_mutex);
@@ -481,7 +481,7 @@ static int vmw_fb_kms_detach(struct vmw_fb_par *par, · 216 unmodified lines
481	DRM_ERROR("Could not unset a mode.\n");	481	DRM_ERROR("Could not unset a mode.\n");
482	return ret;	482	return ret;
483	}	483	}
484	drm_mode_destroy(par->vmw_priv->dev, par->set_mode);	484	drm_mode_destroy(&par->vmw_priv->drm, par->set_mode);
485	par->set_mode = NULL;	485	par->set_mode = NULL;
486	}	486	}
487		487
@@ -567,7 +567,7 @@ static int vmw_fb_set_par(struct fb_info *info) · 79 unmodified lines
567	struct drm_display_mode *mode;	567	struct drm_display_mode *mode;
568	int ret;	568	int ret;
569		569
570	mode = drm_mode_duplicate(vmw_priv->dev, &new_mode);	570	mode = drm_mode_duplicate(&vmw_priv->drm, &new_mode);
571	if (!mode) {	571	if (!mode) {
572	DRM_ERROR("Could not create new fb mode.\n");	572	DRM_ERROR("Could not create new fb mode.\n");
573	return -ENOMEM;	573	return -ENOMEM;
@@ -581,7 +581,7 @@ static int vmw_fb_set_par(struct fb_info *info) · 7 unmodified lines
581	mode->hdisplay *	581	mode->hdisplay *
582	DIV_ROUND_UP(var->bits_per_pixel, 8),	582	DIV_ROUND_UP(var->bits_per_pixel, 8),
583	mode->vdisplay)) {	583	mode->vdisplay)) {
584	drm_mode_destroy(vmw_priv->dev, mode);	584	drm_mode_destroy(&vmw_priv->drm, mode);
585	return -EINVAL;	585	return -EINVAL;
586	}	586	}
587		587
@@ -615,7 +615,7 @@ static int vmw_fb_set_par(struct fb_info *info) · 27 unmodified lines
615		615
616	out_unlock:	616	out_unlock:
617	if (par->set_mode)	617	if (par->set_mode)
618	drm_mode_destroy(vmw_priv->dev, par->set_mode);	618	drm_mode_destroy(&vmw_priv->drm, par->set_mode);
619	par->set_mode = mode;	619	par->set_mode = mode;
620		620
621	mutex_unlock(&par->bo_mutex);	621	mutex_unlock(&par->bo_mutex);
@@ -638,7 +638,7 @@ static const struct fb_ops vmw_fb_ops = { · 16 unmodified lines
638		638
639	int vmw_fb_init(struct vmw_private *vmw_priv)	639	int vmw_fb_init(struct vmw_private *vmw_priv)
640	{	640	{
641	struct device *device = &vmw_priv->dev->pdev->dev;	641	struct device *device = vmw_priv->drm.dev;
642	struct vmw_fb_par *par;	642	struct vmw_fb_par *par;
643	struct fb_info *info;	643	struct fb_info *info;
644	unsigned fb_width, fb_height;	644	unsigned fb_width, fb_height;

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c+12−16

 	struct vmw_fence_manager *fman = fman_from_fence(fence);
 	struct vmw_private *dev_priv = fman->dev_priv;
-	u32 *fifo_mem = dev_priv->mmio_virt;
+	u32 seqno = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_FENCE);
-	u32 seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
 	if (seqno - fence->base.seqno < VMW_FENCE_WRAP)
 		return false;
 				      u32 passed_seqno)
 {
 	u32 goal_seqno;
-	u32 *fifo_mem;
 	struct vmw_fence_obj *fence;
 	if (likely(!fman->seqno_valid))
 		return false;
-	fifo_mem = fman->dev_priv->mmio_virt;
+	goal_seqno = vmw_fifo_mem_read(fman->dev_priv, SVGA_FIFO_FENCE_GOAL);
-	goal_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE_GOAL);
 	if (likely(passed_seqno - goal_seqno >= VMW_FENCE_WRAP))
 		return false;
 	list_for_each_entry(fence, &fman->fence_list, head) {
 		if (!list_empty(&fence->seq_passed_actions)) {
 			fman->seqno_valid = true;
-			vmw_mmio_write(fence->base.seqno,
+			vmw_fifo_mem_write(fman->dev_priv,
-				       fifo_mem + SVGA_FIFO_FENCE_GOAL);
+					   SVGA_FIFO_FENCE_GOAL,
+					   fence->base.seqno);
 			break;
 		}
 	}
 {
 	struct vmw_fence_manager *fman = fman_from_fence(fence);
 	u32 goal_seqno;
-	u32 *fifo_mem;
 	if (dma_fence_is_signaled_locked(&fence->base))
 		return false;
-	fifo_mem = fman->dev_priv->mmio_virt;
+	goal_seqno = vmw_fifo_mem_read(fman->dev_priv, SVGA_FIFO_FENCE_GOAL);
-	goal_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE_GOAL);
 	if (likely(fman->seqno_valid &&
 		   goal_seqno - fence->base.seqno < VMW_FENCE_WRAP))
 		return false;
-	vmw_mmio_write(fence->base.seqno, fifo_mem + SVGA_FIFO_FENCE_GOAL);
+	vmw_fifo_mem_write(fman->dev_priv, SVGA_FIFO_FENCE_GOAL,
+			   fence->base.seqno);
 	fman->seqno_valid = true;
 	return true;
 	struct list_head action_list;
 	bool needs_rerun;
 	uint32_t seqno, new_seqno;
-	u32 *fifo_mem = fman->dev_priv->mmio_virt;
-	seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
+	seqno = vmw_fifo_mem_read(fman->dev_priv, SVGA_FIFO_FENCE);
 rerun:
 	list_for_each_entry_safe(fence, next_fence, &fman->fence_list, head) {
 		if (seqno - fence->base.seqno < VMW_FENCE_WRAP) {
 	needs_rerun = vmw_fence_goal_new_locked(fman, seqno);
 	if (unlikely(needs_rerun)) {
-		new_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
+		new_seqno = vmw_fifo_mem_read(fman->dev_priv, SVGA_FIFO_FENCE);
 		if (new_seqno != seqno) {
 			seqno = new_seqno;
 			goto rerun;
 	eaction->action.type = VMW_ACTION_EVENT;
 	eaction->fence = vmw_fence_obj_reference(fence);
-	eaction->dev = fman->dev_priv->dev;
+	eaction->dev = &fman->dev_priv->drm;
 	eaction->tv_sec = tv_sec;
 	eaction->tv_usec = tv_usec;
 {
 	struct vmw_event_fence_pending *event;
 	struct vmw_fence_manager *fman = fman_from_fence(fence);
-	struct drm_device *dev = fman->dev_priv->dev;
+	struct drm_device *dev = &fman->dev_priv->drm;
 	int ret;
 	event = kzalloc(sizeof(*event), GFP_KERNEL);

drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c+4−4

@@ -51,7 +51,7 @@ static int vmw_gmr2_bind(struct vmw_private *dev_priv, · 50 unmodified lines
51	uint32_t cmd_size = define_size + remap_size;	51	uint32_t cmd_size = define_size + remap_size;
52	uint32_t i;	52	uint32_t i;
53		53
54	cmd_orig = cmd = VMW_FIFO_RESERVE(dev_priv, cmd_size);	54	cmd_orig = cmd = VMW_CMD_RESERVE(dev_priv, cmd_size);
55	if (unlikely(cmd == NULL))	55	if (unlikely(cmd == NULL))
56	return -ENOMEM;	56	return -ENOMEM;
57		57
@@ -98,7 +98,7 @@ static int vmw_gmr2_bind(struct vmw_private *dev_priv, · 40 unmodified lines
98		98
99	BUG_ON(cmd != cmd_orig + cmd_size / sizeof(*cmd));	99	BUG_ON(cmd != cmd_orig + cmd_size / sizeof(*cmd));
100		100
101	vmw_fifo_commit(dev_priv, cmd_size);	101	vmw_cmd_commit(dev_priv, cmd_size);
102		102
103	return 0;	103	return 0;
104	}	104	}
@@ -110,7 +110,7 @@ static void vmw_gmr2_unbind(struct vmw_private *dev_priv, · 5 unmodified lines
110	uint32_t define_size = sizeof(define_cmd) + 4;	110	uint32_t define_size = sizeof(define_cmd) + 4;
111	uint32_t *cmd;	111	uint32_t *cmd;
112		112
113	cmd = VMW_FIFO_RESERVE(dev_priv, define_size);	113	cmd = VMW_CMD_RESERVE(dev_priv, define_size);
114	if (unlikely(cmd == NULL))	114	if (unlikely(cmd == NULL))
115	return;	115	return;
116		116
@@ -120,7 +120,7 @@ static void vmw_gmr2_unbind(struct vmw_private *dev_priv, · 3 unmodified lines
120	*cmd++ = SVGA_CMD_DEFINE_GMR2;	120	*cmd++ = SVGA_CMD_DEFINE_GMR2;
121	memcpy(cmd, &define_cmd, sizeof(define_cmd));	121	memcpy(cmd, &define_cmd, sizeof(define_cmd));
122		122
123	vmw_fifo_commit(dev_priv, define_size);	123	vmw_cmd_commit(dev_priv, define_size);
124	}	124	}
125		125
126		126

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c+7−8

 		param->value = vmw_overlay_num_free_overlays(dev_priv);
 		break;
 	case DRM_VMW_PARAM_3D:
-		param->value = vmw_fifo_have_3d(dev_priv) ? 1 : 0;
+		param->value = vmw_supports_3d(dev_priv) ? 1 : 0;
 		break;
 	case DRM_VMW_PARAM_HW_CAPS:
 		param->value = dev_priv->capabilities;
 		break;
 	case DRM_VMW_PARAM_FIFO_HW_VERSION:
 	{
-		u32 *fifo_mem = dev_priv->mmio_virt;
 		const struct vmw_fifo_state *fifo = &dev_priv->fifo;
 		if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS)) {
 		}
 		param->value =
-			vmw_mmio_read(fifo_mem +
+			vmw_fifo_mem_read(dev_priv,
-				      ((fifo->capabilities &
+					  ((fifo->capabilities &
-					SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
+					    SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
-				       SVGA_FIFO_3D_HWVERSION_REVISED :
+						   SVGA_FIFO_3D_HWVERSION_REVISED :
-				       SVGA_FIFO_3D_HWVERSION));
+						   SVGA_FIFO_3D_HWVERSION));
 		break;
 	}
 	case DRM_VMW_PARAM_MAX_SURF_MEMORY:
 		if (unlikely(ret != 0))
 			goto out_err;
 	} else {
-		fifo_mem = dev_priv->mmio_virt;
+		fifo_mem = dev_priv->fifo_mem;
 		memcpy(bounce, &fifo_mem[SVGA_FIFO_3D_CAPS], size);
 	}

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c+3−7

 void vmw_update_seqno(struct vmw_private *dev_priv,
 			 struct vmw_fifo_state *fifo_state)
 {
-	u32 *fifo_mem = dev_priv->mmio_virt;
+	uint32_t seqno = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_FENCE);
-	uint32_t seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
 	if (dev_priv->last_read_seqno != seqno) {
 		dev_priv->last_read_seqno = seqno;
-		vmw_marker_pull(&fifo_state->marker_queue, seqno);
 		vmw_fences_update(dev_priv->fman);
 	}
 }
 		}
 	}
 	finish_wait(&dev_priv->fence_queue, &__wait);
-	if (ret == 0 && fifo_idle) {
+	if (ret == 0 && fifo_idle)
-		u32 *fifo_mem = dev_priv->mmio_virt;
+		vmw_fifo_mem_write(dev_priv, SVGA_FIFO_FENCE, signal_seq);
-		vmw_mmio_write(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
-	}
 	wake_up_all(&dev_priv->fence_queue);
 out_err:
 	if (fifo_idle)

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c+35−39

 #include "vmwgfx_kms.h"
-/* Might need a hrtimer here? */
-#define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
 void vmw_du_cleanup(struct vmw_display_unit *du)
 {
 	drm_plane_cleanup(&du->primary);
 	if (!image)
 		return -EINVAL;
-	cmd = VMW_FIFO_RESERVE(dev_priv, cmd_size);
+	cmd = VMW_CMD_RESERVE(dev_priv, cmd_size);
 	if (unlikely(cmd == NULL))
 		return -ENOMEM;
 	cmd->cursor.hotspotX = hotspotX;
 	cmd->cursor.hotspotY = hotspotY;
-	vmw_fifo_commit_flush(dev_priv, cmd_size);
+	vmw_cmd_commit_flush(dev_priv, cmd_size);
 	return 0;
 }
 static void vmw_cursor_update_position(struct vmw_private *dev_priv,
 				       bool show, int x, int y)
 {
-	u32 *fifo_mem = dev_priv->mmio_virt;
 	uint32_t count;
 	spin_lock(&dev_priv->cursor_lock);
-	vmw_mmio_write(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
+	vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_ON, show ? 1 : 0);
-	vmw_mmio_write(x, fifo_mem + SVGA_FIFO_CURSOR_X);
+	vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_X, x);
-	vmw_mmio_write(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
+	vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_Y, y);
-	count = vmw_mmio_read(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
+	count = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CURSOR_COUNT);
-	vmw_mmio_write(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
+	vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_COUNT, ++count);
 	spin_unlock(&dev_priv->cursor_lock);
 }
  */
 void vmw_kms_legacy_hotspot_clear(struct vmw_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
+	struct drm_device *dev = &dev_priv->drm;
 	struct vmw_display_unit *du;
 	struct drm_crtc *crtc;
 void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
+	struct drm_device *dev = &dev_priv->drm;
 	struct vmw_display_unit *du;
 	struct drm_crtc *crtc;
 					   bool is_bo_proxy)
 {
-	struct drm_device *dev = dev_priv->dev;
+	struct drm_device *dev = &dev_priv->drm;
 	struct vmw_framebuffer_surface *vfbs;
 	enum SVGA3dSurfaceFormat format;
 	int ret;
 	struct drm_clip_rect norect;
 	int ret, increment = 1;
-	drm_modeset_lock_all(dev_priv->dev);
+	drm_modeset_lock_all(&dev_priv->drm);
 	ret = ttm_read_lock(&dev_priv->reservation_sem, true);
 	if (unlikely(ret != 0)) {
-		drm_modeset_unlock_all(dev_priv->dev);
+		drm_modeset_unlock_all(&dev_priv->drm);
 		return ret;
 	}
 		break;
 	}
-	vmw_fifo_flush(dev_priv, false);
+	vmw_cmd_flush(dev_priv, false);
 	ttm_read_unlock(&dev_priv->reservation_sem);
-	drm_modeset_unlock_all(dev_priv->dev);
+	drm_modeset_unlock_all(&dev_priv->drm);
 	return ret;
 }
 				      *mode_cmd)
 {
-	struct drm_device *dev = dev_priv->dev;
+	struct drm_device *dev = &dev_priv->drm;
 	struct vmw_framebuffer_bo *vfbd;
 	unsigned int requested_size;
 	struct drm_format_name_buf format_name;
 	    bo && only_2d &&
 	    mode_cmd->width > 64 &&  /* Don't create a proxy for cursor */
 	    dev_priv->active_display_unit == vmw_du_screen_target) {
-		ret = vmw_create_bo_proxy(dev_priv->dev, mode_cmd,
+		ret = vmw_create_bo_proxy(&dev_priv->drm, mode_cmd,
 					  bo, &surface);
 		if (ret)
 			return ERR_PTR(ret);
 	if (ret)
 		return ret;
-	vmw_fifo_flush(dev_priv, false);
+	vmw_cmd_flush(dev_priv, false);
 	return 0;
 }
 		return;
 	dev_priv->hotplug_mode_update_property =
-		drm_property_create_range(dev_priv->dev,
+		drm_property_create_range(&dev_priv->drm,
 					  DRM_MODE_PROP_IMMUTABLE,
 					  "hotplug_mode_update", 0, 1);
 int vmw_kms_init(struct vmw_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
+	struct drm_device *dev = &dev_priv->drm;
 	int ret;
 	drm_mode_config_init(dev);
 	 * but since it destroys encoders and our destructor calls
 	 * drm_encoder_cleanup which takes the lock we deadlock.
 	 */
-	drm_mode_config_cleanup(dev_priv->dev);
+	drm_mode_config_cleanup(&dev_priv->drm);
 	if (dev_priv->active_display_unit == vmw_du_legacy)
 		ret = vmw_kms_ldu_close_display(dev_priv);
 	if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
 		vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
 	else if (vmw_fifo_have_pitchlock(vmw_priv))
-		vmw_mmio_write(pitch, vmw_priv->mmio_virt +
+		vmw_fifo_mem_write(vmw_priv, SVGA_FIFO_PITCHLOCK, pitch);
-			       SVGA_FIFO_PITCHLOCK);
 	vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
 	vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
-	vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
+	if ((vmw_priv->capabilities & SVGA_CAP_8BIT_EMULATION) != 0)
+		vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
 	if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
 		DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
 static int vmw_du_update_layout(struct vmw_private *dev_priv,
 				unsigned int num_rects, struct drm_rect *rects)
 {
-	struct drm_device *dev = dev_priv->dev;
+	struct drm_device *dev = &dev_priv->drm;
 	struct vmw_display_unit *du;
 	struct drm_connector *con;
 	struct drm_connector_list_iter conn_iter;
 	if (dirty->crtc) {
 		units[num_units++] = vmw_crtc_to_du(dirty->crtc);
 	} else {
-		list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
+		list_for_each_entry(crtc, &dev_priv->drm.mode_config.crtc_list,
 				    head) {
 			struct drm_plane *plane = crtc->primary;
 		dirty->unit = unit;
 		if (dirty->fifo_reserve_size > 0) {
-			dirty->cmd = VMW_FIFO_RESERVE(dev_priv,
+			dirty->cmd = VMW_CMD_RESERVE(dev_priv,
 						      dirty->fifo_reserve_size);
 			if (!dirty->cmd)
 				return -ENOMEM;
 	if (!clips)
 		return 0;
-	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd) * num_clips);
+	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd) * num_clips);
 	if (!cmd)
 		return -ENOMEM;
 		copy_size += sizeof(*cmd);
 	}
-	vmw_fifo_commit(dev_priv, copy_size);
+	vmw_cmd_commit(dev_priv, copy_size);
 	return 0;
 }
 	int i = 0;
 	int ret = 0;
-	mutex_lock(&dev_priv->dev->mode_config.mutex);
+	mutex_lock(&dev_priv->drm.mode_config.mutex);
-	list_for_each_entry(con, &dev_priv->dev->mode_config.connector_list,
+	list_for_each_entry(con, &dev_priv->drm.mode_config.connector_list,
 			    head) {
 		if (i == unit)
 			break;
 		++i;
 	}
-	if (&con->head == &dev_priv->dev->mode_config.connector_list) {
+	if (&con->head == &dev_priv->drm.mode_config.connector_list) {
 		DRM_ERROR("Could not find initial display unit.\n");
 		ret = -EINVAL;
 		goto out_unlock;
 	}
  out_unlock:
-	mutex_unlock(&dev_priv->dev->mode_config.mutex);
+	mutex_unlock(&dev_priv->drm.mode_config.mutex);
 	return ret;
 }
 		return;
 	dev_priv->implicit_placement_property =
-		drm_property_create_range(dev_priv->dev,
+		drm_property_create_range(&dev_priv->drm,
 					  DRM_MODE_PROP_IMMUTABLE,
 					  "implicit_placement", 0, 1);
 }
 		goto out_unref;
 	reserved_size = update->calc_fifo_size(update, num_hits);
-	cmd_start = VMW_FIFO_RESERVE(update->dev_priv, reserved_size);
+	cmd_start = VMW_CMD_RESERVE(update->dev_priv, reserved_size);
 	if (!cmd_start) {
 		ret = -ENOMEM;
 		goto out_revert;
 	if (reserved_size < submit_size)
 		submit_size = 0;
-	vmw_fifo_commit(update->dev_priv, submit_size);
+	vmw_cmd_commit(update->dev_priv, submit_size);
 	vmw_kms_helper_validation_finish(update->dev_priv, NULL, &val_ctx,
 					 update->out_fence, NULL);

drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c+4−5

 		vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, crtc->y);
 		vmw_write(dev_priv, SVGA_REG_DISPLAY_WIDTH, crtc->mode.hdisplay);
 		vmw_write(dev_priv, SVGA_REG_DISPLAY_HEIGHT, crtc->mode.vdisplay);
-		vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
 		i++;
 	}
 static int vmw_ldu_init(struct vmw_private *dev_priv, unsigned unit)
 {
 	struct vmw_legacy_display_unit *ldu;
-	struct drm_device *dev = dev_priv->dev;
+	struct drm_device *dev = &dev_priv->drm;
 	struct drm_connector *connector;
 	struct drm_encoder *encoder;
 	struct drm_plane *primary, *cursor;
 int vmw_kms_ldu_init_display(struct vmw_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
+	struct drm_device *dev = &dev_priv->drm;
 	int i, ret;
 	if (dev_priv->ldu_priv) {
 	} *cmd;
 	fifo_size = sizeof(*cmd) * num_clips;
-	cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size);
+	cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);
 	if (unlikely(cmd == NULL))
 		return -ENOMEM;
 		cmd[i].body.height = clips->y2 - clips->y1;
 	}
-	vmw_fifo_commit(dev_priv, fifo_size);
+	vmw_cmd_commit(dev_priv, fifo_size);
 	return 0;
 }

drivers/gpu/drm/vmwgfx/vmwgfx_marker.c+0−155

@@ -1,155 +0,0 @@
1	// SPDX-License-Identifier: GPL-2.0 OR MIT
2	/**************************************************************************
3	*
4	* Copyright 2010 VMware, Inc., Palo Alto, CA., USA
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the
8	* "Software"), to deal in the Software without restriction, including
9	* without limitation the rights to use, copy, modify, merge, publish,
10	* distribute, sub license, and/or sell copies of the Software, and to
11	* permit persons to whom the Software is furnished to do so, subject to
12	* the following conditions:
13	*
14	* The above copyright notice and this permission notice (including the
15	* next paragraph) shall be included in all copies or substantial portions
16	* of the Software.
17	*
18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
25	*
26	**************************************************************************/
27
28
29	#include "vmwgfx_drv.h"
30
31	struct vmw_marker {
32	struct list_head head;
33	uint32_t seqno;
34	u64 submitted;
35	};
36
37	void vmw_marker_queue_init(struct vmw_marker_queue *queue)
38	{
39	INIT_LIST_HEAD(&queue->head);
40	queue->lag = 0;
41	queue->lag_time = ktime_get_raw_ns();
42	spin_lock_init(&queue->lock);
43	}
44
45	void vmw_marker_queue_takedown(struct vmw_marker_queue *queue)
46	{
47	struct vmw_marker marker, next;
48
49	spin_lock(&queue->lock);
50	list_for_each_entry_safe(marker, next, &queue->head, head) {
51	kfree(marker);
52	}
53	spin_unlock(&queue->lock);
54	}
55
56	int vmw_marker_push(struct vmw_marker_queue *queue,
57	uint32_t seqno)
58	{
59	struct vmw_marker marker = kmalloc(sizeof(marker), GFP_KERNEL);
60
61	if (unlikely(!marker))
62	return -ENOMEM;
63
64	marker->seqno = seqno;
65	marker->submitted = ktime_get_raw_ns();
66	spin_lock(&queue->lock);
67	list_add_tail(&marker->head, &queue->head);
68	spin_unlock(&queue->lock);
69
70	return 0;
71	}
72
73	int vmw_marker_pull(struct vmw_marker_queue *queue,
74	uint32_t signaled_seqno)
75	{
76	struct vmw_marker marker, next;
77	bool updated = false;
78	u64 now;
79
80	spin_lock(&queue->lock);
81	now = ktime_get_raw_ns();
82
83	if (list_empty(&queue->head)) {
84	queue->lag = 0;
85	queue->lag_time = now;
86	updated = true;
87	goto out_unlock;
88	}
89
90	list_for_each_entry_safe(marker, next, &queue->head, head) {
91	if (signaled_seqno - marker->seqno > (1 << 30))
92	continue;
93
94	queue->lag = now - marker->submitted;
95	queue->lag_time = now;
96	updated = true;
97	list_del(&marker->head);
98	kfree(marker);
99	}
100
101	out_unlock:
102	spin_unlock(&queue->lock);
103
104	return (updated) ? 0 : -EBUSY;
105	}
106
107	static u64 vmw_fifo_lag(struct vmw_marker_queue *queue)
108	{
109	u64 now;
110
111	spin_lock(&queue->lock);
112	now = ktime_get_raw_ns();
113	queue->lag += now - queue->lag_time;
114	queue->lag_time = now;
115	spin_unlock(&queue->lock);
116	return queue->lag;
117	}
118
119
120	static bool vmw_lag_lt(struct vmw_marker_queue *queue,
121	uint32_t us)
122	{
123	u64 cond = (u64) us * NSEC_PER_USEC;
124
125	return vmw_fifo_lag(queue) <= cond;
126	}
127
128	int vmw_wait_lag(struct vmw_private *dev_priv,
129	struct vmw_marker_queue *queue, uint32_t us)
130	{
131	struct vmw_marker *marker;
132	uint32_t seqno;
133	int ret;
134
135	while (!vmw_lag_lt(queue, us)) {
136	spin_lock(&queue->lock);
137	if (list_empty(&queue->head))
138	seqno = atomic_read(&dev_priv->marker_seq);
139	else {
140	marker = list_first_entry(&queue->head,
141	struct vmw_marker, head);
142	seqno = marker->seqno;
143	}
144	spin_unlock(&queue->lock);
145
146	ret = vmw_wait_seqno(dev_priv, false, seqno, true,
147	3*HZ);
148
149	if (unlikely(ret != 0))
150	return ret;
151
152	(void) vmw_marker_pull(queue, seqno);
153	}
154	return 0;
155	}

drivers/gpu/drm/vmwgfx/vmwgfx_mob.c+8−8

@@ -148,7 +148,7 @@ static int vmw_setup_otable_base(struct vmw_private *dev_priv, · 147 unmodified lines
148	mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PTDEPTH_1;	148	mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PTDEPTH_1;
149	}	149	}
150		150
151	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	151	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
152	if (unlikely(cmd == NULL)) {	152	if (unlikely(cmd == NULL)) {
153	ret = -ENOMEM;	153	ret = -ENOMEM;
154	goto out_no_fifo;	154	goto out_no_fifo;
@@ -170,7 +170,7 @@ static int vmw_setup_otable_base(struct vmw_private *dev_priv, · 15 unmodified lines
170	*/	170	*/
171	BUG_ON(mob->pt_level == VMW_MOBFMT_PTDEPTH_2);	171	BUG_ON(mob->pt_level == VMW_MOBFMT_PTDEPTH_2);
172		172
173	vmw_fifo_commit(dev_priv, sizeof(*cmd));	173	vmw_cmd_commit(dev_priv, sizeof(*cmd));
174	otable->page_table = mob;	174	otable->page_table = mob;
175		175
176	return 0;	176	return 0;
@@ -203,7 +203,7 @@ static void vmw_takedown_otable_base(struct vmw_private *dev_priv, · 26 unmodified lines
203	return;	203	return;
204		204
205	bo = otable->page_table->pt_bo;	205	bo = otable->page_table->pt_bo;
206	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	206	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
207	if (unlikely(cmd == NULL))	207	if (unlikely(cmd == NULL))
208	return;	208	return;
209		209
@@ -215,7 +215,7 @@ static void vmw_takedown_otable_base(struct vmw_private *dev_priv, · 5 unmodified lines
215	cmd->body.sizeInBytes = 0;	215	cmd->body.sizeInBytes = 0;
216	cmd->body.validSizeInBytes = 0;	216	cmd->body.validSizeInBytes = 0;
217	cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID;	217	cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID;
218	vmw_fifo_commit(dev_priv, sizeof(*cmd));	218	vmw_cmd_commit(dev_priv, sizeof(*cmd));
219		219
220	if (bo) {	220	if (bo) {
221	int ret;	221	int ret;
@@ -558,12 +558,12 @@ void vmw_mob_unbind(struct vmw_private *dev_priv, · 336 unmodified lines
558	BUG_ON(ret != 0);	558	BUG_ON(ret != 0);
559	}	559	}
560		560
561	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	561	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
562	if (cmd) {	562	if (cmd) {
563	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB;	563	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB;
564	cmd->header.size = sizeof(cmd->body);	564	cmd->header.size = sizeof(cmd->body);
565	cmd->body.mobid = mob->id;	565	cmd->body.mobid = mob->id;
566	vmw_fifo_commit(dev_priv, sizeof(*cmd));	566	vmw_cmd_commit(dev_priv, sizeof(*cmd));
567	}	567	}
568		568
569	if (bo) {	569	if (bo) {
@@ -625,7 +625,7 @@ int vmw_mob_bind(struct vmw_private *dev_priv, · 55 unmodified lines
625		625
626	vmw_fifo_resource_inc(dev_priv);	626	vmw_fifo_resource_inc(dev_priv);
627		627
628	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	628	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
629	if (unlikely(cmd == NULL))	629	if (unlikely(cmd == NULL))
630	goto out_no_cmd_space;	630	goto out_no_cmd_space;
631		631
@@ -636,7 +636,7 @@ int vmw_mob_bind(struct vmw_private *dev_priv, · 4 unmodified lines
636	cmd->body.base = mob->pt_root_page >> PAGE_SHIFT;	636	cmd->body.base = mob->pt_root_page >> PAGE_SHIFT;
637	cmd->body.sizeInBytes = num_data_pages * PAGE_SIZE;	637	cmd->body.sizeInBytes = num_data_pages * PAGE_SIZE;
638		638
639	vmw_fifo_commit(dev_priv, sizeof(*cmd));	639	vmw_cmd_commit(dev_priv, sizeof(*cmd));
640		640
641	return 0;	641	return 0;
642		642

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c+4−4

@@ -122,7 +122,7 @@ static int vmw_overlay_send_put(struct vmw_private *dev_priv, · 121 unmodified lines
122		122
123	fifo_size = sizeof(cmds) + sizeof(flush) + sizeof(items) num_items;	123	fifo_size = sizeof(cmds) + sizeof(flush) + sizeof(items) num_items;
124		124
125	cmds = VMW_FIFO_RESERVE(dev_priv, fifo_size);	125	cmds = VMW_CMD_RESERVE(dev_priv, fifo_size);
126	/* hardware has hung, can't do anything here */	126	/* hardware has hung, can't do anything here */
127	if (!cmds)	127	if (!cmds)
128	return -ENOMEM;	128	return -ENOMEM;
@@ -169,7 +169,7 @@ static int vmw_overlay_send_put(struct vmw_private *dev_priv, · 40 unmodified lines
169		169
170	fill_flush(flush, arg->stream_id);	170	fill_flush(flush, arg->stream_id);
171		171
172	vmw_fifo_commit(dev_priv, fifo_size);	172	vmw_cmd_commit(dev_priv, fifo_size);
173		173
174	return 0;	174	return 0;
175	}	175	}
@@ -192,7 +192,7 @@ static int vmw_overlay_send_stop(struct vmw_private *dev_priv, · 16 unmodified lines
192	int ret;	192	int ret;
193		193
194	for (;;) {	194	for (;;) {
195	cmds = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmds));	195	cmds = VMW_CMD_RESERVE(dev_priv, sizeof(*cmds));
196	if (cmds)	196	if (cmds)
197	break;	197	break;
198		198
@@ -211,7 +211,7 @@ static int vmw_overlay_send_stop(struct vmw_private *dev_priv, · 12 unmodified lines
211	cmds->body.items[0].value = false;	211	cmds->body.items[0].value = false;
212	fill_flush(&cmds->flush, stream_id);	212	fill_flush(&cmds->flush, stream_id);
213		213
214	vmw_fifo_commit(dev_priv, sizeof(*cmds));	214	vmw_cmd_commit(dev_priv, sizeof(*cmds));
215		215
216	return 0;	216	return 0;
217	}	217	}

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c+2−2

@@ -827,7 +827,7 @@ int vmw_query_readback_all(struct vmw_buffer_object *dx_query_mob) · 826 unmodified lines
827	dx_query_ctx = dx_query_mob->dx_query_ctx;	827	dx_query_ctx = dx_query_mob->dx_query_ctx;
828	dev_priv = dx_query_ctx->dev_priv;	828	dev_priv = dx_query_ctx->dev_priv;
829		829
830	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), dx_query_ctx->id);	830	cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), dx_query_ctx->id);
831	if (unlikely(cmd == NULL))	831	if (unlikely(cmd == NULL))
832	return -ENOMEM;	832	return -ENOMEM;
833		833
@@ -835,7 +835,7 @@ int vmw_query_readback_all(struct vmw_buffer_object *dx_query_mob) · 1 unmodified line
835	cmd->header.size = sizeof(cmd->body);	835	cmd->header.size = sizeof(cmd->body);
836	cmd->body.cid = dx_query_ctx->id;	836	cmd->body.cid = dx_query_ctx->id;
837		837
838	vmw_fifo_commit(dev_priv, sizeof(*cmd));	838	vmw_cmd_commit(dev_priv, sizeof(*cmd));
839		839
840	/* Triggers a rebind the next time affected context is bound */	840	/* Triggers a rebind the next time affected context is bound */
841	dx_query_mob->dx_query_ctx = NULL;	841	dx_query_mob->dx_query_ctx = NULL;

drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c+14−14

@@ -132,7 +132,7 @@ static int vmw_sou_fifo_create(struct vmw_private *dev_priv, · 131 unmodified lines
132	BUG_ON(!sou->buffer);	132	BUG_ON(!sou->buffer);
133		133
134	fifo_size = sizeof(*cmd);	134	fifo_size = sizeof(*cmd);
135	cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size);	135	cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);
136	if (unlikely(cmd == NULL))	136	if (unlikely(cmd == NULL))
137	return -ENOMEM;	137	return -ENOMEM;
138		138
@@ -153,7 +153,7 @@ static int vmw_sou_fifo_create(struct vmw_private *dev_priv, · 14 unmodified lines
153	vmw_bo_get_guest_ptr(&sou->buffer->base, &cmd->obj.backingStore.ptr);	153	vmw_bo_get_guest_ptr(&sou->buffer->base, &cmd->obj.backingStore.ptr);
154	cmd->obj.backingStore.pitch = mode->hdisplay * 4;	154	cmd->obj.backingStore.pitch = mode->hdisplay * 4;
155		155
156	vmw_fifo_commit(dev_priv, fifo_size);	156	vmw_cmd_commit(dev_priv, fifo_size);
157		157
158	sou->defined = true;	158	sou->defined = true;
159		159
@@ -181,7 +181,7 @@ static int vmw_sou_fifo_destroy(struct vmw_private *dev_priv, · 21 unmodified lines
181	return 0;	181	return 0;
182		182
183	fifo_size = sizeof(*cmd);	183	fifo_size = sizeof(*cmd);
184	cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size);	184	cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);
185	if (unlikely(cmd == NULL))	185	if (unlikely(cmd == NULL))
186	return -ENOMEM;	186	return -ENOMEM;
187		187
@@ -189,7 +189,7 @@ static int vmw_sou_fifo_destroy(struct vmw_private *dev_priv, · 1 unmodified line
189	cmd->header.cmdType = SVGA_CMD_DESTROY_SCREEN;	189	cmd->header.cmdType = SVGA_CMD_DESTROY_SCREEN;
190	cmd->body.screenId = sou->base.unit;	190	cmd->body.screenId = sou->base.unit;
191		191
192	vmw_fifo_commit(dev_priv, fifo_size);	192	vmw_cmd_commit(dev_priv, fifo_size);
193		193
194	/* Force sync */	194	/* Force sync */
195	ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);	195	ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
@@ -829,7 +829,7 @@ static const struct drm_crtc_helper_funcs vmw_sou_crtc_helper_funcs = { · 633 unmodified lines
829	static int vmw_sou_init(struct vmw_private *dev_priv, unsigned unit)	829	static int vmw_sou_init(struct vmw_private *dev_priv, unsigned unit)
830	{	830	{
831	struct vmw_screen_object_unit *sou;	831	struct vmw_screen_object_unit *sou;
832	struct drm_device *dev = dev_priv->dev;	832	struct drm_device *dev = &dev_priv->drm;
833	struct drm_connector *connector;	833	struct drm_connector *connector;
834	struct drm_encoder *encoder;	834	struct drm_encoder *encoder;
835	struct drm_plane primary, cursor;	835	struct drm_plane primary, cursor;
@@ -946,7 +946,7 @@ err_free: · 110 unmodified lines
946		946
947	int vmw_kms_sou_init_display(struct vmw_private *dev_priv)	947	int vmw_kms_sou_init_display(struct vmw_private *dev_priv)
948	{	948	{
949	struct drm_device *dev = dev_priv->dev;	949	struct drm_device *dev = &dev_priv->drm;
950	int i, ret;	950	int i, ret;
951		951
952	if (!(dev_priv->capabilities & SVGA_CAP_SCREEN_OBJECT_2)) {	952	if (!(dev_priv->capabilities & SVGA_CAP_SCREEN_OBJECT_2)) {
@@ -992,7 +992,7 @@ static int do_bo_define_gmrfb(struct vmw_private *dev_priv, · 39 unmodified lines
992	if (depth == 32)	992	if (depth == 32)
993	depth = 24;	993	depth = 24;
994		994
995	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	995	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
996	if (!cmd)	996	if (!cmd)
997	return -ENOMEM;	997	return -ENOMEM;
998		998
@@ -1003,7 +1003,7 @@ static int do_bo_define_gmrfb(struct vmw_private *dev_priv, · 4 unmodified lines
1003	cmd->body.bytesPerLine = framebuffer->base.pitches[0];	1003	cmd->body.bytesPerLine = framebuffer->base.pitches[0];
1004	/* Buffer is reserved in vram or GMR */	1004	/* Buffer is reserved in vram or GMR */
1005	vmw_bo_get_guest_ptr(&buf->base, &cmd->body.ptr);	1005	vmw_bo_get_guest_ptr(&buf->base, &cmd->body.ptr);
1006	vmw_fifo_commit(dev_priv, sizeof(*cmd));	1006	vmw_cmd_commit(dev_priv, sizeof(*cmd));
1007		1007
1008	return 0;	1008	return 0;
1009	}	1009	}
@@ -1029,7 +1029,7 @@ static void vmw_sou_surface_fifo_commit(struct vmw_kms_dirty *dirty) · 19 unmodified lines
1029	int i;	1029	int i;
1030		1030
1031	if (!dirty->num_hits) {	1031	if (!dirty->num_hits) {
1032	vmw_fifo_commit(dirty->dev_priv, 0);	1032	vmw_cmd_commit(dirty->dev_priv, 0);
1033	return;	1033	return;
1034	}	1034	}
1035		1035
@@ -1061,7 +1061,7 @@ static void vmw_sou_surface_fifo_commit(struct vmw_kms_dirty *dirty) · 25 unmodified lines
1061	blit->bottom -= sdirty->top;	1061	blit->bottom -= sdirty->top;
1062	}	1062	}
1063		1063
1064	vmw_fifo_commit(dirty->dev_priv, region_size + sizeof(*cmd));	1064	vmw_cmd_commit(dirty->dev_priv, region_size + sizeof(*cmd));
1065		1065
1066	sdirty->left = sdirty->top = S32_MAX;	1066	sdirty->left = sdirty->top = S32_MAX;
1067	sdirty->right = sdirty->bottom = S32_MIN;	1067	sdirty->right = sdirty->bottom = S32_MIN;
@@ -1185,11 +1185,11 @@ out_unref: · 117 unmodified lines
1185	static void vmw_sou_bo_fifo_commit(struct vmw_kms_dirty *dirty)	1185	static void vmw_sou_bo_fifo_commit(struct vmw_kms_dirty *dirty)
1186	{	1186	{
1187	if (!dirty->num_hits) {	1187	if (!dirty->num_hits) {
1188	vmw_fifo_commit(dirty->dev_priv, 0);	1188	vmw_cmd_commit(dirty->dev_priv, 0);
1189	return;	1189	return;
1190	}	1190	}
1191		1191
1192	vmw_fifo_commit(dirty->dev_priv,	1192	vmw_cmd_commit(dirty->dev_priv,
1193	sizeof(struct vmw_kms_sou_bo_blit) *	1193	sizeof(struct vmw_kms_sou_bo_blit) *
1194	dirty->num_hits);	1194	dirty->num_hits);
1195	}	1195	}
@@ -1295,11 +1295,11 @@ out_unref: · 99 unmodified lines
1295	static void vmw_sou_readback_fifo_commit(struct vmw_kms_dirty *dirty)	1295	static void vmw_sou_readback_fifo_commit(struct vmw_kms_dirty *dirty)
1296	{	1296	{
1297	if (!dirty->num_hits) {	1297	if (!dirty->num_hits) {
1298	vmw_fifo_commit(dirty->dev_priv, 0);	1298	vmw_cmd_commit(dirty->dev_priv, 0);
1299	return;	1299	return;
1300	}	1300	}
1301		1301
1302	vmw_fifo_commit(dirty->dev_priv,	1302	vmw_cmd_commit(dirty->dev_priv,
1303	sizeof(struct vmw_kms_sou_readback_blit) *	1303	sizeof(struct vmw_kms_sou_readback_blit) *
1304	dirty->num_hits);	1304	dirty->num_hits);
1305	}	1305	}

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c+12−12

@@ -222,7 +222,7 @@ static int vmw_gb_shader_create(struct vmw_resource *res) · 221 unmodified lines
222	goto out_no_fifo;	222	goto out_no_fifo;
223	}	223	}
224		224
225	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	225	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
226	if (unlikely(cmd == NULL)) {	226	if (unlikely(cmd == NULL)) {
227	ret = -ENOMEM;	227	ret = -ENOMEM;
228	goto out_no_fifo;	228	goto out_no_fifo;
@@ -233,7 +233,7 @@ static int vmw_gb_shader_create(struct vmw_resource *res) · 4 unmodified lines
233	cmd->body.shid = res->id;	233	cmd->body.shid = res->id;
234	cmd->body.type = shader->type;	234	cmd->body.type = shader->type;
235	cmd->body.sizeInBytes = shader->size;	235	cmd->body.sizeInBytes = shader->size;
236	vmw_fifo_commit(dev_priv, sizeof(*cmd));	236	vmw_cmd_commit(dev_priv, sizeof(*cmd));
237	vmw_fifo_resource_inc(dev_priv);	237	vmw_fifo_resource_inc(dev_priv);
238		238
239	return 0;	239	return 0;
@@ -256,7 +256,7 @@ static int vmw_gb_shader_bind(struct vmw_resource *res, · 16 unmodified lines
256		256
257	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);	257	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
258		258
259	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	259	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
260	if (unlikely(cmd == NULL))	260	if (unlikely(cmd == NULL))
261	return -ENOMEM;	261	return -ENOMEM;
262		262
@@ -266,7 +266,7 @@ static int vmw_gb_shader_bind(struct vmw_resource *res, · 3 unmodified lines
266	cmd->body.mobid = bo->mem.start;	266	cmd->body.mobid = bo->mem.start;
267	cmd->body.offsetInBytes = res->backup_offset;	267	cmd->body.offsetInBytes = res->backup_offset;
268	res->backup_dirty = false;	268	res->backup_dirty = false;
269	vmw_fifo_commit(dev_priv, sizeof(*cmd));	269	vmw_cmd_commit(dev_priv, sizeof(*cmd));
270		270
271	return 0;	271	return 0;
272	}	272	}
@@ -284,7 +284,7 @@ static int vmw_gb_shader_unbind(struct vmw_resource *res, · 11 unmodified lines
284		284
285	BUG_ON(res->backup->base.mem.mem_type != VMW_PL_MOB);	285	BUG_ON(res->backup->base.mem.mem_type != VMW_PL_MOB);
286		286
287	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	287	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
288	if (unlikely(cmd == NULL))	288	if (unlikely(cmd == NULL))
289	return -ENOMEM;	289	return -ENOMEM;
290		290
@@ -293,7 +293,7 @@ static int vmw_gb_shader_unbind(struct vmw_resource *res, · 2 unmodified lines
293	cmd->body.shid = res->id;	293	cmd->body.shid = res->id;
294	cmd->body.mobid = SVGA3D_INVALID_ID;	294	cmd->body.mobid = SVGA3D_INVALID_ID;
295	cmd->body.offsetInBytes = 0;	295	cmd->body.offsetInBytes = 0;
296	vmw_fifo_commit(dev_priv, sizeof(*cmd));	296	vmw_cmd_commit(dev_priv, sizeof(*cmd));
297		297
298	/*	298	/*
299	* Create a fence object and fence the backup buffer.	299	* Create a fence object and fence the backup buffer.
@@ -324,7 +324,7 @@ static int vmw_gb_shader_destroy(struct vmw_resource *res) · 24 unmodified lines
324	mutex_lock(&dev_priv->binding_mutex);	324	mutex_lock(&dev_priv->binding_mutex);
325	vmw_binding_res_list_scrub(&res->binding_head);	325	vmw_binding_res_list_scrub(&res->binding_head);
326		326
327	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	327	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
328	if (unlikely(cmd == NULL)) {	328	if (unlikely(cmd == NULL)) {
329	mutex_unlock(&dev_priv->binding_mutex);	329	mutex_unlock(&dev_priv->binding_mutex);
330	return -ENOMEM;	330	return -ENOMEM;
@@ -333,7 +333,7 @@ static int vmw_gb_shader_destroy(struct vmw_resource *res) · 2 unmodified lines
333	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SHADER;	333	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SHADER;
334	cmd->header.size = sizeof(cmd->body);	334	cmd->header.size = sizeof(cmd->body);
335	cmd->body.shid = res->id;	335	cmd->body.shid = res->id;
336	vmw_fifo_commit(dev_priv, sizeof(*cmd));	336	vmw_cmd_commit(dev_priv, sizeof(*cmd));
337	mutex_unlock(&dev_priv->binding_mutex);	337	mutex_unlock(&dev_priv->binding_mutex);
338	vmw_resource_release_id(res);	338	vmw_resource_release_id(res);
339	vmw_fifo_resource_dec(dev_priv);	339	vmw_fifo_resource_dec(dev_priv);
@@ -394,7 +394,7 @@ static int vmw_dx_shader_unscrub(struct vmw_resource *res) · 54 unmodified lines
394	if (!list_empty(&shader->cotable_head) \|\| !shader->committed)	394	if (!list_empty(&shader->cotable_head) \|\| !shader->committed)
395	return 0;	395	return 0;
396		396
397	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), shader->ctx->id);	397	cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), shader->ctx->id);
398	if (unlikely(cmd == NULL))	398	if (unlikely(cmd == NULL))
399	return -ENOMEM;	399	return -ENOMEM;
400		400
@@ -404,7 +404,7 @@ static int vmw_dx_shader_unscrub(struct vmw_resource *res) · 3 unmodified lines
404	cmd->body.shid = shader->id;	404	cmd->body.shid = shader->id;
405	cmd->body.mobid = res->backup->base.mem.start;	405	cmd->body.mobid = res->backup->base.mem.start;
406	cmd->body.offsetInBytes = res->backup_offset;	406	cmd->body.offsetInBytes = res->backup_offset;
407	vmw_fifo_commit(dev_priv, sizeof(*cmd));	407	vmw_cmd_commit(dev_priv, sizeof(*cmd));
408		408
409	vmw_cotable_add_resource(shader->cotable, &shader->cotable_head);	409	vmw_cotable_add_resource(shader->cotable, &shader->cotable_head);
410		410
@@ -481,7 +481,7 @@ static int vmw_dx_shader_scrub(struct vmw_resource *res) · 70 unmodified lines
481	return 0;	481	return 0;
482		482
483	WARN_ON_ONCE(!shader->committed);	483	WARN_ON_ONCE(!shader->committed);
484	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	484	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
485	if (unlikely(cmd == NULL))	485	if (unlikely(cmd == NULL))
486	return -ENOMEM;	486	return -ENOMEM;
487		487
@@ -491,7 +491,7 @@ static int vmw_dx_shader_scrub(struct vmw_resource *res) · 3 unmodified lines
491	cmd->body.shid = res->id;	491	cmd->body.shid = res->id;
492	cmd->body.mobid = SVGA3D_INVALID_ID;	492	cmd->body.mobid = SVGA3D_INVALID_ID;
493	cmd->body.offsetInBytes = 0;	493	cmd->body.offsetInBytes = 0;
494	vmw_fifo_commit(dev_priv, sizeof(*cmd));	494	vmw_cmd_commit(dev_priv, sizeof(*cmd));
495	res->id = -1;	495	res->id = -1;
496	list_del_init(&shader->cotable_head);	496	list_del_init(&shader->cotable_head);
497		497

drivers/gpu/drm/vmwgfx/vmwgfx_so.c+4−4

@@ -170,7 +170,7 @@ static int vmw_view_create(struct vmw_resource *res) · 169 unmodified lines
170	return 0;	170	return 0;
171	}	171	}
172		172
173	cmd = VMW_FIFO_RESERVE_DX(res->dev_priv, view->cmd_size, view->ctx->id);	173	cmd = VMW_CMD_CTX_RESERVE(res->dev_priv, view->cmd_size, view->ctx->id);
174	if (!cmd) {	174	if (!cmd) {
175	mutex_unlock(&dev_priv->binding_mutex);	175	mutex_unlock(&dev_priv->binding_mutex);
176	return -ENOMEM;	176	return -ENOMEM;
@@ -181,7 +181,7 @@ static int vmw_view_create(struct vmw_resource *res) · 4 unmodified lines
181	/* Sid may have changed due to surface eviction. */	181	/* Sid may have changed due to surface eviction. */
182	WARN_ON(view->srf->id == SVGA3D_INVALID_ID);	182	WARN_ON(view->srf->id == SVGA3D_INVALID_ID);
183	cmd->body.sid = view->srf->id;	183	cmd->body.sid = view->srf->id;
184	vmw_fifo_commit(res->dev_priv, view->cmd_size);	184	vmw_cmd_commit(res->dev_priv, view->cmd_size);
185	res->id = view->view_id;	185	res->id = view->view_id;
186	list_add_tail(&view->srf_head, &srf->view_list);	186	list_add_tail(&view->srf_head, &srf->view_list);
187	vmw_cotable_add_resource(view->cotable, &view->cotable_head);	187	vmw_cotable_add_resource(view->cotable, &view->cotable_head);
@@ -213,14 +213,14 @@ static int vmw_view_destroy(struct vmw_resource *res) · 25 unmodified lines
213	if (!view->committed \|\| res->id == -1)	213	if (!view->committed \|\| res->id == -1)
214	return 0;	214	return 0;
215		215
216	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), view->ctx->id);	216	cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), view->ctx->id);
217	if (!cmd)	217	if (!cmd)
218	return -ENOMEM;	218	return -ENOMEM;
219		219
220	cmd->header.id = vmw_view_destroy_cmds[view->view_type];	220	cmd->header.id = vmw_view_destroy_cmds[view->view_type];
221	cmd->header.size = sizeof(cmd->body);	221	cmd->header.size = sizeof(cmd->body);
222	cmd->body.view_id = view->view_id;	222	cmd->body.view_id = view->view_id;
223	vmw_fifo_commit(dev_priv, sizeof(*cmd));	223	vmw_cmd_commit(dev_priv, sizeof(*cmd));
224	res->id = -1;	224	res->id = -1;
225	list_del_init(&view->cotable_head);	225	list_del_init(&view->cotable_head);
226	list_del_init(&view->srf_head);	226	list_del_init(&view->srf_head);

drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c+16−16

@@ -170,7 +170,7 @@ static int vmw_stdu_define_st(struct vmw_private *dev_priv, · 169 unmodified lines
170	SVGA3dCmdDefineGBScreenTarget body;	170	SVGA3dCmdDefineGBScreenTarget body;
171	} *cmd;	171	} *cmd;
172		172
173	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	173	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
174	if (unlikely(cmd == NULL))	174	if (unlikely(cmd == NULL))
175	return -ENOMEM;	175	return -ENOMEM;
176		176
@@ -188,7 +188,7 @@ static int vmw_stdu_define_st(struct vmw_private *dev_priv, · 11 unmodified lines
188	stdu->base.set_gui_x = cmd->body.xRoot;	188	stdu->base.set_gui_x = cmd->body.xRoot;
189	stdu->base.set_gui_y = cmd->body.yRoot;	189	stdu->base.set_gui_y = cmd->body.yRoot;
190		190
191	vmw_fifo_commit(dev_priv, sizeof(*cmd));	191	vmw_cmd_commit(dev_priv, sizeof(*cmd));
192		192
193	stdu->defined = true;	193	stdu->defined = true;
194	stdu->display_width = mode->hdisplay;	194	stdu->display_width = mode->hdisplay;
@@ -229,7 +229,7 @@ static int vmw_stdu_bind_st(struct vmw_private *dev_priv, · 34 unmodified lines
229	memset(&image, 0, sizeof(image));	229	memset(&image, 0, sizeof(image));
230	image.sid = res ? res->id : SVGA3D_INVALID_ID;	230	image.sid = res ? res->id : SVGA3D_INVALID_ID;
231		231
232	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	232	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
233	if (unlikely(cmd == NULL))	233	if (unlikely(cmd == NULL))
234	return -ENOMEM;	234	return -ENOMEM;
235		235
@@ -239,7 +239,7 @@ static int vmw_stdu_bind_st(struct vmw_private *dev_priv, · 3 unmodified lines
239	cmd->body.stid = stdu->base.unit;	239	cmd->body.stid = stdu->base.unit;
240	cmd->body.image = image;	240	cmd->body.image = image;
241		241
242	vmw_fifo_commit(dev_priv, sizeof(*cmd));	242	vmw_cmd_commit(dev_priv, sizeof(*cmd));
243		243
244	return 0;	244	return 0;
245	}	245	}
@@ -293,7 +293,7 @@ static int vmw_stdu_update_st(struct vmw_private *dev_priv, · 47 unmodified lines
293	return -EINVAL;	293	return -EINVAL;
294	}	294	}
295		295
296	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	296	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
297	if (unlikely(cmd == NULL))	297	if (unlikely(cmd == NULL))
298	return -ENOMEM;	298	return -ENOMEM;
299		299
@@ -301,7 +301,7 @@ static int vmw_stdu_update_st(struct vmw_private *dev_priv, · 1 unmodified line
301	0, stdu->display_width,	301	0, stdu->display_width,
302	0, stdu->display_height);	302	0, stdu->display_height);
303		303
304	vmw_fifo_commit(dev_priv, sizeof(*cmd));	304	vmw_cmd_commit(dev_priv, sizeof(*cmd));
305		305
306	return 0;	306	return 0;
307	}	307	}
@@ -329,7 +329,7 @@ static int vmw_stdu_destroy_st(struct vmw_private *dev_priv, · 21 unmodified lines
329	if (unlikely(!stdu->defined))	329	if (unlikely(!stdu->defined))
330	return 0;	330	return 0;
331		331
332	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	332	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
333	if (unlikely(cmd == NULL))	333	if (unlikely(cmd == NULL))
334	return -ENOMEM;	334	return -ENOMEM;
335		335
@@ -338,7 +338,7 @@ static int vmw_stdu_destroy_st(struct vmw_private *dev_priv, · 2 unmodified lines
338		338
339	cmd->body.stid = stdu->base.unit;	339	cmd->body.stid = stdu->base.unit;
340		340
341	vmw_fifo_commit(dev_priv, sizeof(*cmd));	341	vmw_cmd_commit(dev_priv, sizeof(*cmd));
342		342
343	/* Force sync */	343	/* Force sync */
344	ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);	344	ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
@@ -499,7 +499,7 @@ static void vmw_stdu_bo_fifo_commit(struct vmw_kms_dirty *dirty) · 154 unmodified lines
499	size_t blit_size = sizeof(blit) dirty->num_hits + sizeof(*suffix);	499	size_t blit_size = sizeof(blit) dirty->num_hits + sizeof(*suffix);
500		500
501	if (!dirty->num_hits) {	501	if (!dirty->num_hits) {
502	vmw_fifo_commit(dirty->dev_priv, 0);	502	vmw_cmd_commit(dirty->dev_priv, 0);
503	return;	503	return;
504	}	504	}
505		505
@@ -522,7 +522,7 @@ static void vmw_stdu_bo_fifo_commit(struct vmw_kms_dirty *dirty) · 16 unmodified lines
522	ddirty->top, ddirty->bottom);	522	ddirty->top, ddirty->bottom);
523	}	523	}
524		524
525	vmw_fifo_commit(dirty->dev_priv, sizeof(*cmd) + blit_size);	525	vmw_cmd_commit(dirty->dev_priv, sizeof(*cmd) + blit_size);
526		526
527	stdu->display_srf->res.res_dirty = true;	527	stdu->display_srf->res.res_dirty = true;
528	ddirty->left = ddirty->top = S32_MAX;	528	ddirty->left = ddirty->top = S32_MAX;
@@ -628,7 +628,7 @@ static void vmw_stdu_bo_cpu_commit(struct vmw_kms_dirty *dirty) · 99 unmodified lines
628		628
629		629
630	dev_priv = vmw_priv(stdu->base.crtc.dev);	630	dev_priv = vmw_priv(stdu->base.crtc.dev);
631	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	631	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
632	if (!cmd)	632	if (!cmd)
633	goto out_cleanup;	633	goto out_cleanup;
634		634
@@ -636,7 +636,7 @@ static void vmw_stdu_bo_cpu_commit(struct vmw_kms_dirty *dirty) · 1 unmodified line
636	region.x1, region.x2,	636	region.x1, region.x2,
637	region.y1, region.y2);	637	region.y1, region.y2);
638		638
639	vmw_fifo_commit(dev_priv, sizeof(*cmd));	639	vmw_cmd_commit(dev_priv, sizeof(*cmd));
640	}	640	}
641		641
642	out_cleanup:	642	out_cleanup:
@@ -795,7 +795,7 @@ static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty) · 152 unmodified lines
795	size_t commit_size;	795	size_t commit_size;
796		796
797	if (!dirty->num_hits) {	797	if (!dirty->num_hits) {
798	vmw_fifo_commit(dirty->dev_priv, 0);	798	vmw_cmd_commit(dirty->dev_priv, 0);
799	return;	799	return;
800	}	800	}
801		801
@@ -817,7 +817,7 @@ static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty) · 15 unmodified lines
817	vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left,	817	vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left,
818	sdirty->right, sdirty->top, sdirty->bottom);	818	sdirty->right, sdirty->top, sdirty->bottom);
819		819
820	vmw_fifo_commit(dirty->dev_priv, commit_size);	820	vmw_cmd_commit(dirty->dev_priv, commit_size);
821		821
822	sdirty->left = sdirty->top = S32_MAX;	822	sdirty->left = sdirty->top = S32_MAX;
823	sdirty->right = sdirty->bottom = S32_MIN;	823	sdirty->right = sdirty->bottom = S32_MIN;
@@ -1713,7 +1713,7 @@ static const struct drm_crtc_helper_funcs vmw_stdu_crtc_helper_funcs = { · 889 unmodified lines
1713	static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit)	1713	static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit)
1714	{	1714	{
1715	struct vmw_screen_target_display_unit *stdu;	1715	struct vmw_screen_target_display_unit *stdu;
1716	struct drm_device *dev = dev_priv->dev;	1716	struct drm_device *dev = &dev_priv->drm;
1717	struct drm_connector *connector;	1717	struct drm_connector *connector;
1718	struct drm_encoder *encoder;	1718	struct drm_encoder *encoder;
1719	struct drm_plane primary, cursor;	1719	struct drm_plane primary, cursor;
@@ -1861,7 +1861,7 @@ static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu) · 141 unmodified lines
1861	*/	1861	*/
1862	int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)	1862	int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)
1863	{	1863	{
1864	struct drm_device *dev = dev_priv->dev;	1864	struct drm_device *dev = &dev_priv->drm;
1865	int i, ret;	1865	int i, ret;
1866		1866
1867		1867

drivers/gpu/drm/vmwgfx/vmwgfx_streamoutput.c+4−4

@@ -99,7 +99,7 @@ static int vmw_dx_streamoutput_unscrub(struct vmw_resource *res) · 98 unmodified lines
99	if (!list_empty(&so->cotable_head) \|\| !so->committed )	99	if (!list_empty(&so->cotable_head) \|\| !so->committed )
100	return 0;	100	return 0;
101		101
102	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), so->ctx->id);	102	cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), so->ctx->id);
103	if (!cmd)	103	if (!cmd)
104	return -ENOMEM;	104	return -ENOMEM;
105		105
@@ -109,7 +109,7 @@ static int vmw_dx_streamoutput_unscrub(struct vmw_resource *res) · 3 unmodified lines
109	cmd->body.mobid = res->backup->base.mem.start;	109	cmd->body.mobid = res->backup->base.mem.start;
110	cmd->body.offsetInBytes = res->backup_offset;	110	cmd->body.offsetInBytes = res->backup_offset;
111	cmd->body.sizeInBytes = so->size;	111	cmd->body.sizeInBytes = so->size;
112	vmw_fifo_commit(dev_priv, sizeof(*cmd));	112	vmw_cmd_commit(dev_priv, sizeof(*cmd));
113		113
114	vmw_cotable_add_resource(so->cotable, &so->cotable_head);	114	vmw_cotable_add_resource(so->cotable, &so->cotable_head);
115		115
@@ -172,7 +172,7 @@ static int vmw_dx_streamoutput_scrub(struct vmw_resource *res) · 56 unmodified lines
172		172
173	WARN_ON_ONCE(!so->committed);	173	WARN_ON_ONCE(!so->committed);
174		174
175	cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), so->ctx->id);	175	cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), so->ctx->id);
176	if (!cmd)	176	if (!cmd)
177	return -ENOMEM;	177	return -ENOMEM;
178		178
@@ -182,7 +182,7 @@ static int vmw_dx_streamoutput_scrub(struct vmw_resource *res) · 3 unmodified lines
182	cmd->body.mobid = SVGA3D_INVALID_ID;	182	cmd->body.mobid = SVGA3D_INVALID_ID;
183	cmd->body.offsetInBytes = 0;	183	cmd->body.offsetInBytes = 0;
184	cmd->body.sizeInBytes = so->size;	184	cmd->body.sizeInBytes = so->size;
185	vmw_fifo_commit(dev_priv, sizeof(*cmd));	185	vmw_cmd_commit(dev_priv, sizeof(*cmd));
186		186
187	res->id = -1;	187	res->id = -1;
188	list_del_init(&so->cotable_head);	188	list_del_init(&so->cotable_head);

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c+20−20

@@ -372,12 +372,12 @@ static void vmw_hw_surface_destroy(struct vmw_resource *res) · 371 unmodified lines
372		372
373	if (res->id != -1) {	373	if (res->id != -1) {
374		374
375	cmd = VMW_FIFO_RESERVE(dev_priv, vmw_surface_destroy_size());	375	cmd = VMW_CMD_RESERVE(dev_priv, vmw_surface_destroy_size());
376	if (unlikely(!cmd))	376	if (unlikely(!cmd))
377	return;	377	return;
378		378
379	vmw_surface_destroy_encode(res->id, cmd);	379	vmw_surface_destroy_encode(res->id, cmd);
380	vmw_fifo_commit(dev_priv, vmw_surface_destroy_size());	380	vmw_cmd_commit(dev_priv, vmw_surface_destroy_size());
381		381
382	/*	382	/*
383	* used_memory_size_atomic, or separate lock	383	* used_memory_size_atomic, or separate lock
@@ -440,14 +440,14 @@ static int vmw_legacy_srf_create(struct vmw_resource *res) · 56 unmodified lines
440	*/	440	*/
441		441
442	submit_size = vmw_surface_define_size(srf);	442	submit_size = vmw_surface_define_size(srf);
443	cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);	443	cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
444	if (unlikely(!cmd)) {	444	if (unlikely(!cmd)) {
445	ret = -ENOMEM;	445	ret = -ENOMEM;
446	goto out_no_fifo;	446	goto out_no_fifo;
447	}	447	}
448		448
449	vmw_surface_define_encode(srf, cmd);	449	vmw_surface_define_encode(srf, cmd);
450	vmw_fifo_commit(dev_priv, submit_size);	450	vmw_cmd_commit(dev_priv, submit_size);
451	vmw_fifo_resource_inc(dev_priv);	451	vmw_fifo_resource_inc(dev_priv);
452		452
453	/*	453	/*
@@ -492,14 +492,14 @@ static int vmw_legacy_srf_dma(struct vmw_resource *res, · 38 unmodified lines
492		492
493	BUG_ON(!val_buf->bo);	493	BUG_ON(!val_buf->bo);
494	submit_size = vmw_surface_dma_size(srf);	494	submit_size = vmw_surface_dma_size(srf);
495	cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);	495	cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
496	if (unlikely(!cmd))	496	if (unlikely(!cmd))
497	return -ENOMEM;	497	return -ENOMEM;
498		498
499	vmw_bo_get_guest_ptr(val_buf->bo, &ptr);	499	vmw_bo_get_guest_ptr(val_buf->bo, &ptr);
500	vmw_surface_dma_encode(srf, cmd, &ptr, bind);	500	vmw_surface_dma_encode(srf, cmd, &ptr, bind);
501		501
502	vmw_fifo_commit(dev_priv, submit_size);	502	vmw_cmd_commit(dev_priv, submit_size);
503		503
504	/*	504	/*
505	* Create a fence object and fence the backup buffer.	505	* Create a fence object and fence the backup buffer.
@@ -578,12 +578,12 @@ static int vmw_legacy_srf_destroy(struct vmw_resource *res) · 72 unmodified lines
578	*/	578	*/
579		579
580	submit_size = vmw_surface_destroy_size();	580	submit_size = vmw_surface_destroy_size();
581	cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);	581	cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
582	if (unlikely(!cmd))	582	if (unlikely(!cmd))
583	return -ENOMEM;	583	return -ENOMEM;
584		584
585	vmw_surface_destroy_encode(res->id, cmd);	585	vmw_surface_destroy_encode(res->id, cmd);
586	vmw_fifo_commit(dev_priv, submit_size);	586	vmw_cmd_commit(dev_priv, submit_size);
587		587
588	/*	588	/*
589	* Surface memory usage accounting.	589	* Surface memory usage accounting.
@@ -1121,7 +1121,7 @@ static int vmw_gb_surface_create(struct vmw_resource *res) · 531 unmodified lines
1121	submit_len = sizeof(*cmd);	1121	submit_len = sizeof(*cmd);
1122	}	1122	}
1123		1123
1124	cmd = VMW_FIFO_RESERVE(dev_priv, submit_len);	1124	cmd = VMW_CMD_RESERVE(dev_priv, submit_len);
1125	cmd2 = (typeof(cmd2))cmd;	1125	cmd2 = (typeof(cmd2))cmd;
1126	cmd3 = (typeof(cmd3))cmd;	1126	cmd3 = (typeof(cmd3))cmd;
1127	cmd4 = (typeof(cmd4))cmd;	1127	cmd4 = (typeof(cmd4))cmd;
@@ -1188,7 +1188,7 @@ static int vmw_gb_surface_create(struct vmw_resource *res) · 60 unmodified lines
1188	cmd->body.size.depth = metadata->base_size.depth;	1188	cmd->body.size.depth = metadata->base_size.depth;
1189	}	1189	}
1190		1190
1191	vmw_fifo_commit(dev_priv, submit_len);	1191	vmw_cmd_commit(dev_priv, submit_len);
1192		1192
1193	return 0;	1193	return 0;
1194		1194
@@ -1219,7 +1219,7 @@ static int vmw_gb_surface_bind(struct vmw_resource *res, · 24 unmodified lines
1219		1219
1220	submit_size = sizeof(cmd1) + (res->backup_dirty ? sizeof(cmd2) : 0);	1220	submit_size = sizeof(cmd1) + (res->backup_dirty ? sizeof(cmd2) : 0);
1221		1221
1222	cmd1 = VMW_FIFO_RESERVE(dev_priv, submit_size);	1222	cmd1 = VMW_CMD_RESERVE(dev_priv, submit_size);
1223	if (unlikely(!cmd1))	1223	if (unlikely(!cmd1))
1224	return -ENOMEM;	1224	return -ENOMEM;
1225		1225
@@ -1233,7 +1233,7 @@ static int vmw_gb_surface_bind(struct vmw_resource *res, · 7 unmodified lines
1233	cmd2->header.size = sizeof(cmd2->body);	1233	cmd2->header.size = sizeof(cmd2->body);
1234	cmd2->body.sid = res->id;	1234	cmd2->body.sid = res->id;
1235	}	1235	}
1236	vmw_fifo_commit(dev_priv, submit_size);	1236	vmw_cmd_commit(dev_priv, submit_size);
1237		1237
1238	if (res->backup->dirty && res->backup_dirty) {	1238	if (res->backup->dirty && res->backup_dirty) {
1239	/* We've just made a full upload. Cear dirty regions. */	1239	/* We've just made a full upload. Cear dirty regions. */
@@ -1272,7 +1272,7 @@ static int vmw_gb_surface_unbind(struct vmw_resource *res, · 32 unmodified lines
1272	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);	1272	BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
1273		1273
1274	submit_size = sizeof(cmd3) + (readback ? sizeof(cmd1) : sizeof(*cmd2));	1274	submit_size = sizeof(cmd3) + (readback ? sizeof(cmd1) : sizeof(*cmd2));
1275	cmd = VMW_FIFO_RESERVE(dev_priv, submit_size);	1275	cmd = VMW_CMD_RESERVE(dev_priv, submit_size);
1276	if (unlikely(!cmd))	1276	if (unlikely(!cmd))
1277	return -ENOMEM;	1277	return -ENOMEM;
1278		1278
@@ -1295,7 +1295,7 @@ static int vmw_gb_surface_unbind(struct vmw_resource *res, · 16 unmodified lines
1295	cmd3->body.sid = res->id;	1295	cmd3->body.sid = res->id;
1296	cmd3->body.mobid = SVGA3D_INVALID_ID;	1296	cmd3->body.mobid = SVGA3D_INVALID_ID;
1297		1297
1298	vmw_fifo_commit(dev_priv, submit_size);	1298	vmw_cmd_commit(dev_priv, submit_size);
1299		1299
1300	/*	1300	/*
1301	* Create a fence object and fence the backup buffer.	1301	* Create a fence object and fence the backup buffer.
@@ -1328,7 +1328,7 @@ static int vmw_gb_surface_destroy(struct vmw_resource *res) · 26 unmodified lines
1328	vmw_view_surface_list_destroy(dev_priv, &srf->view_list);	1328	vmw_view_surface_list_destroy(dev_priv, &srf->view_list);
1329	vmw_binding_res_list_scrub(&res->binding_head);	1329	vmw_binding_res_list_scrub(&res->binding_head);
1330		1330
1331	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));	1331	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
1332	if (unlikely(!cmd)) {	1332	if (unlikely(!cmd)) {
1333	mutex_unlock(&dev_priv->binding_mutex);	1333	mutex_unlock(&dev_priv->binding_mutex);
1334	return -ENOMEM;	1334	return -ENOMEM;
@@ -1337,7 +1337,7 @@ static int vmw_gb_surface_destroy(struct vmw_resource *res) · 2 unmodified lines
1337	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SURFACE;	1337	cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SURFACE;
1338	cmd->header.size = sizeof(cmd->body);	1338	cmd->header.size = sizeof(cmd->body);
1339	cmd->body.sid = res->id;	1339	cmd->body.sid = res->id;
1340	vmw_fifo_commit(dev_priv, sizeof(*cmd));	1340	vmw_cmd_commit(dev_priv, sizeof(*cmd));
1341	mutex_unlock(&dev_priv->binding_mutex);	1341	mutex_unlock(&dev_priv->binding_mutex);
1342	vmw_resource_release_id(res);	1342	vmw_resource_release_id(res);
1343	vmw_fifo_resource_dec(dev_priv);	1343	vmw_fifo_resource_dec(dev_priv);
@@ -1895,7 +1895,7 @@ static int vmw_surface_dirty_sync(struct vmw_resource *res) · 551 unmodified lines
1895	goto out;	1895	goto out;
1896		1896
1897	alloc_size = num_dirty * ((has_dx) ? sizeof(cmd1) : sizeof(cmd2));	1897	alloc_size = num_dirty * ((has_dx) ? sizeof(cmd1) : sizeof(cmd2));
1898	cmd = VMW_FIFO_RESERVE(dev_priv, alloc_size);	1898	cmd = VMW_CMD_RESERVE(dev_priv, alloc_size);
1899	if (!cmd)	1899	if (!cmd)
1900	return -ENOMEM;	1900	return -ENOMEM;
1901		1901
@@ -1931,7 +1931,7 @@ static int vmw_surface_dirty_sync(struct vmw_resource *res) · 29 unmodified lines
1931	}	1931	}
1932		1932
1933	}	1933	}
1934	vmw_fifo_commit(dev_priv, alloc_size);	1934	vmw_cmd_commit(dev_priv, alloc_size);
1935	out:	1935	out:
1936	memset(&dirty->boxes[0], 0, sizeof(dirty->boxes[0]) *	1936	memset(&dirty->boxes[0], 0, sizeof(dirty->boxes[0]) *
1937	dirty->num_subres);	1937	dirty->num_subres);
@@ -2031,14 +2031,14 @@ static int vmw_surface_clean(struct vmw_resource *res) · 93 unmodified lines
2031	} *cmd;	2031	} *cmd;
2032		2032
2033	alloc_size = sizeof(*cmd);	2033	alloc_size = sizeof(*cmd);
2034	cmd = VMW_FIFO_RESERVE(dev_priv, alloc_size);	2034	cmd = VMW_CMD_RESERVE(dev_priv, alloc_size);
2035	if (!cmd)	2035	if (!cmd)
2036	return -ENOMEM;	2036	return -ENOMEM;
2037		2037
2038	cmd->header.id = SVGA_3D_CMD_READBACK_GB_SURFACE;	2038	cmd->header.id = SVGA_3D_CMD_READBACK_GB_SURFACE;
2039	cmd->header.size = sizeof(cmd->body);	2039	cmd->header.size = sizeof(cmd->body);
2040	cmd->body.sid = res->id;	2040	cmd->body.sid = res->id;
2041	vmw_fifo_commit(dev_priv, alloc_size);	2041	vmw_cmd_commit(dev_priv, alloc_size);
2042		2042
2043	return 0;	2043	return 0;
2044	}	2044	}

drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c+3−3

@@ -309,7 +309,7 @@ void vmw_piter_start(struct vmw_piter viter, const struct vmw_sg_table vsgt, · 308 unmodified lines
309	*/	309	*/
310	static void vmw_ttm_unmap_from_dma(struct vmw_ttm_tt *vmw_tt)	310	static void vmw_ttm_unmap_from_dma(struct vmw_ttm_tt *vmw_tt)
311	{	311	{
312	struct device *dev = vmw_tt->dev_priv->dev->dev;	312	struct device *dev = vmw_tt->dev_priv->drm.dev;
313		313
314	dma_unmap_sgtable(dev, &vmw_tt->sgt, DMA_BIDIRECTIONAL, 0);	314	dma_unmap_sgtable(dev, &vmw_tt->sgt, DMA_BIDIRECTIONAL, 0);
315	vmw_tt->sgt.nents = vmw_tt->sgt.orig_nents;	315	vmw_tt->sgt.nents = vmw_tt->sgt.orig_nents;
@@ -330,7 +330,7 @@ static void vmw_ttm_unmap_from_dma(struct vmw_ttm_tt *vmw_tt) · 14 unmodified lines
330	*/	330	*/
331	static int vmw_ttm_map_for_dma(struct vmw_ttm_tt *vmw_tt)	331	static int vmw_ttm_map_for_dma(struct vmw_ttm_tt *vmw_tt)
332	{	332	{
333	struct device *dev = vmw_tt->dev_priv->dev->dev;	333	struct device *dev = vmw_tt->dev_priv->drm.dev;
334		334
335	return dma_map_sgtable(dev, &vmw_tt->sgt, DMA_BIDIRECTIONAL, 0);	335	return dma_map_sgtable(dev, &vmw_tt->sgt, DMA_BIDIRECTIONAL, 0);
336	}	336	}
@@ -385,7 +385,7 @@ static int vmw_ttm_map_dma(struct vmw_ttm_tt *vmw_tt) · 48 unmodified lines
385	sg = __sg_alloc_table_from_pages(&vmw_tt->sgt, vsgt->pages,	385	sg = __sg_alloc_table_from_pages(&vmw_tt->sgt, vsgt->pages,
386	vsgt->num_pages, 0,	386	vsgt->num_pages, 0,
387	(unsigned long) vsgt->num_pages << PAGE_SHIFT,	387	(unsigned long) vsgt->num_pages << PAGE_SHIFT,
388	dma_get_max_seg_size(dev_priv->dev->dev),	388	dma_get_max_seg_size(dev_priv->drm.dev),
389	NULL, 0, GFP_KERNEL);	389	NULL, 0, GFP_KERNEL);
390	if (IS_ERR(sg)) {	390	if (IS_ERR(sg)) {
391	ret = PTR_ERR(sg);	391	ret = PTR_ERR(sg);

drivers/pci/pci.c+10−2

 		pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
 		bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
 		res = pdev->resource + bar_idx;
-		size = ilog2(resource_size(res)) - 20;
+		size = pci_rebar_bytes_to_size(resource_size(res));
 		ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
 		ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
 		pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
 		return 0;
 	pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
-	return (cap & PCI_REBAR_CAP_SIZES) >> 4;
+	cap &= PCI_REBAR_CAP_SIZES;
+	/* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
+	if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
+	    bar == 0 && cap == 0x7000)
+		cap = 0x3f000;
+	return cap >> 4;
 }
+EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
 /**
  * pci_rebar_get_current_size - get the current size of a BAR

drivers/pci/pci.h+0−1

@@ -630,7 +630,6 @@ int acpi_get_rc_resources(struct device dev, const char hid, u16 segment, · 629 unmodified lines
630	struct resource *res);	630	struct resource *res);
631	#endif	631	#endif
632		632
633	u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
634	int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);	633	int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
635	int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);	634	int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
636	static inline u64 pci_rebar_size_to_bytes(int size)	635	static inline u64 pci_rebar_size_to_bytes(int size)

drivers/video/fbdev/omap2/omapfb/displays/Kconfig+1−0

@@ -43,6 +43,7 @@ config FB_OMAP2_PANEL_DPI · 42 unmodified lines
43	config FB_OMAP2_PANEL_DSI_CM	43	config FB_OMAP2_PANEL_DSI_CM
44	tristate "Generic DSI Command Mode Panel"	44	tristate "Generic DSI Command Mode Panel"
45	depends on BACKLIGHT_CLASS_DEVICE	45	depends on BACKLIGHT_CLASS_DEVICE
		46	depends on DRM_PANEL_DSI_CM = n
46	help	47	help
47	Driver for generic DSI command mode panels.	48	Driver for generic DSI command mode panels.
48		49

include/drm/drm_agpsupport.h+0−18

@@ -28,10 +28,6 @@ struct drm_agp_head { · 27 unmodified lines
28		28
29	#if IS_ENABLED(CONFIG_AGP)	29	#if IS_ENABLED(CONFIG_AGP)
30		30
31	void drm_free_agp(struct agp_memory * handle, int pages);
32	int drm_bind_agp(struct agp_memory * handle, unsigned int start);
33	int drm_unbind_agp(struct agp_memory * handle);
34
35	struct drm_agp_head drm_agp_init(struct drm_device dev);	31	struct drm_agp_head drm_agp_init(struct drm_device dev);
36	void drm_legacy_agp_clear(struct drm_device *dev);	32	void drm_legacy_agp_clear(struct drm_device *dev);
37	int drm_agp_acquire(struct drm_device *dev);	33	int drm_agp_acquire(struct drm_device *dev);
@@ -61,20 +57,6 @@ int drm_agp_bind_ioctl(struct drm_device dev, void data, · 23 unmodified lines
61		57
62	#else /* CONFIG_AGP */	58	#else /* CONFIG_AGP */
63		59
64	static inline void drm_free_agp(struct agp_memory * handle, int pages)
65	{
66	}
67
68	static inline int drm_bind_agp(struct agp_memory * handle, unsigned int start)
69	{
70	return -ENODEV;
71	}
72
73	static inline int drm_unbind_agp(struct agp_memory * handle)
74	{
75	return -ENODEV;
76	}
77
78	static inline struct drm_agp_head drm_agp_init(struct drm_device dev)	60	static inline struct drm_agp_head drm_agp_init(struct drm_device dev)
79	{	61	{
80	return NULL;	62	return NULL;

include/drm/drm_crtc.h+1−1

@@ -1232,7 +1232,7 @@ void __drmm_crtc_alloc_with_planes(struct drm_device dev, · 1231 unmodified lines
1232	const char *name, ...);	1232	const char *name, ...);
1233		1233
1234	/**	1234	/**
1235	* drm_crtc_alloc_with_planes - Allocate and initialize a new CRTC object with	1235	* drmm_crtc_alloc_with_planes - Allocate and initialize a new CRTC object with
1236	* specified primary and cursor planes.	1236	* specified primary and cursor planes.
1237	* @dev: DRM device	1237	* @dev: DRM device
1238	* @type: the type of the struct which contains struct &drm_crtc	1238	* @type: the type of the struct which contains struct &drm_crtc

include/drm/drm_device.h+5−4

 	/** @pdev: PCI device structure */
 	struct pci_dev *pdev;
-#ifdef __alpha__
-	/** @hose: PCI hose, only used on ALPHA platforms. */
-	struct pci_controller *hose;
-#endif
 	/** @num_crtcs: Number of CRTCs on this device */
 	unsigned int num_crtcs;
 	/* List of devices per driver for stealth attach cleanup */
 	struct list_head legacy_dev_list;
+#ifdef __alpha__
+	/** @hose: PCI hose, only used on ALPHA platforms. */
+	struct pci_controller *hose;
+#endif
 	/* Context handle management - linked list of context handles */
 	struct list_head ctxlist;

include/drm/drm_mipi_dbi.h+1−1

@@ -172,7 +172,7 @@ int mipi_dbi_buf_copy(void dst, struct drm_framebuffer fb, · 171 unmodified lines
172	* mipi_dbi_command - MIPI DCS command with optional parameter(s)	172	* mipi_dbi_command - MIPI DCS command with optional parameter(s)
173	* @dbi: MIPI DBI structure	173	* @dbi: MIPI DBI structure
174	* @cmd: Command	174	* @cmd: Command
175	* @seq...: Optional parameter(s)	175	* @seq: Optional parameter(s)
176	*	176	*
177	* Send MIPI DCS command to the controller. Use mipi_dbi_command_read() for	177	* Send MIPI DCS command to the controller. Use mipi_dbi_command_read() for
178	* get/read.	178	* get/read.

include/drm/drm_property.h+1−1

@@ -114,7 +114,7 @@ struct drm_property { · 113 unmodified lines
114	* by the property. Bitmask properties are created using	114	* by the property. Bitmask properties are created using
115	* drm_property_create_bitmask().	115	* drm_property_create_bitmask().
116	*	116	*
117	* DRM_MODE_PROB_OBJECT	117	* DRM_MODE_PROP_OBJECT
118	* Object properties are used to link modeset objects. This is used	118	* Object properties are used to link modeset objects. This is used
119	* extensively in the atomic support to create the display pipeline,	119	* extensively in the atomic support to create the display pipeline,
120	* by linking &drm_framebuffer to &drm_plane, &drm_plane to	120	* by linking &drm_framebuffer to &drm_plane, &drm_plane to

include/drm/ttm/ttm_resource.h+4−0

 static inline void
 ttm_resource_manager_set_used(struct ttm_resource_manager *man, bool used)
 {
+	int i;
+	for (i = 0; i < TTM_MAX_BO_PRIORITY; i++)
+		WARN_ON(!list_empty(&man->lru[i]));
 	man->use_type = used;
 }

include/linux/dma-buf.h+6−0

 	 * On failure, returns a negative error value wrapped into a pointer.
 	 * May also return -EINTR when a signal was received while being
 	 * blocked.
+	 *
+	 * Note that exporters should not try to cache the scatter list, or
+	 * return the same one for multiple calls. Caching is done either by the
+	 * DMA-BUF code (for non-dynamic importers) or the importer. Ownership
+	 * of the scatter list is transferred to the caller, and returned by
+	 * @unmap_dma_buf.
 	 */
 	struct sg_table * (*map_dma_buf)(struct dma_buf_attachment *,
 					 enum dma_data_direction);

include/linux/pci.h+9−0

@@ -1232,6 +1232,15 @@ void pci_update_resource(struct pci_dev *dev, int resno); · 1231 unmodified lines
1232	int __must_check pci_assign_resource(struct pci_dev *dev, int i);	1232	int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1233	int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);	1233	int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1234	void pci_release_resource(struct pci_dev *dev, int resno);	1234	void pci_release_resource(struct pci_dev *dev, int resno);
		1235	static inline int pci_rebar_bytes_to_size(u64 bytes)
		1236	{
		1237	bytes = roundup_pow_of_two(bytes);
		1238
		1239	/* Return BAR size as defined in the resizable BAR specification */
		1240	return max(ilog2(bytes), 20) - 20;
		1241	}
		1242
		1243	u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1235	int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);	1244	int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1236	int pci_select_bars(struct pci_dev *dev, unsigned long flags);	1245	int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1237	bool pci_device_is_present(struct pci_dev *pdev);	1246	bool pci_device_is_present(struct pci_dev *pdev);

include/linux/vgaarb.h+3−3

@@ -121,9 +121,9 @@ extern struct pci_dev *vga_default_device(void); · 120 unmodified lines
121	extern void vga_set_default_device(struct pci_dev *pdev);	121	extern void vga_set_default_device(struct pci_dev *pdev);
122	extern int vga_remove_vgacon(struct pci_dev *pdev);	122	extern int vga_remove_vgacon(struct pci_dev *pdev);
123	#else	123	#else
124	static inline struct pci_dev *vga_default_device(void) { return NULL; };	124	static inline struct pci_dev *vga_default_device(void) { return NULL; }
125	static inline void vga_set_default_device(struct pci_dev *pdev) { };	125	static inline void vga_set_default_device(struct pci_dev *pdev) { }
126	static inline int vga_remove_vgacon(struct pci_dev *pdev) { return 0; };	126	static inline int vga_remove_vgacon(struct pci_dev *pdev) { return 0; }
127	#endif	127	#endif
128		128
129	/*	129	/*

include/uapi/drm/drm_fourcc.h+2−2

@@ -1036,9 +1036,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 1035 unmodified lines
1036	* Not all combinations are valid, and different SoCs may support different	1036	* Not all combinations are valid, and different SoCs may support different
1037	* combinations of layout and options.	1037	* combinations of layout and options.
1038	*/	1038	*/
1039	#define __fourcc_mod_amlogic_layout_mask 0xf	1039	#define __fourcc_mod_amlogic_layout_mask 0xff
1040	#define __fourcc_mod_amlogic_options_shift 8	1040	#define __fourcc_mod_amlogic_options_shift 8
1041	#define __fourcc_mod_amlogic_options_mask 0xf	1041	#define __fourcc_mod_amlogic_options_mask 0xff
1042		1042
1043	#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \	1043	#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1044	fourcc_mod_code(AMLOGIC, \	1044	fourcc_mod_code(AMLOGIC, \