History

Merge tag 'intel-gpio-v5.19-2' of gitolite.kernel.org:pub/scm/linux/kernel/git/andy/linux-gpio-intel into gpio/for-current

intel-gpio for v5.19-2 * Convert IRQ chips in Diolan and Intel GPIO drivers to be immutable

Bartosz Golaszewski committed 4 years ago

Commit 7219b822 parents f2906aa b93a8b25 files · +96 −64Browse files

Unified · Split

5 files
  1. drivers/gpio/gpio-crystalcove.c +37 −33
  2. drivers/gpio/gpio-dln2.c +14 −9
  3. drivers/gpio/gpio-merrifield.c +15 −7
  4. drivers/gpio/gpio-sch.c +22 −13
  5. drivers/gpio/gpio-wcove.c +8 −2
drivers/gpio/gpio-crystalcove.c+37−33
@@ -15,6 +15,7 @@ · 14 unmodified lines
15#include <linux/platform_device.h>15#include <linux/platform_device.h>
16#include <linux/regmap.h>16#include <linux/regmap.h>
17#include <linux/seq_file.h>17#include <linux/seq_file.h>
18#include <linux/types.h>
18 19
19#define CRYSTALCOVE_GPIO_NUM 1620#define CRYSTALCOVE_GPIO_NUM 16
20#define CRYSTALCOVE_VGPIO_NUM 9521#define CRYSTALCOVE_VGPIO_NUM 95
@@ -110,8 +111,7 @@ static inline int to_reg(int gpio, enum ctrl_register reg_type) · 89 unmodified lines
110 return reg + gpio % 8;111 return reg + gpio % 8;
111}112}
112 113
113static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,114static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)
114 int gpio)
115{115{
116 u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;116 u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
117 int mask = BIT(gpio % 8);117 int mask = BIT(gpio % 8);
@@ -140,8 +140,7 @@ static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) · 22 unmodified lines
140 return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);140 return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
141}141}
142 142
143static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,143static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value)
144 int value)
145{144{
146 struct crystalcove_gpio *cg = gpiochip_get_data(chip);145 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
147 int reg = to_reg(gpio, CTRL_OUT);146 int reg = to_reg(gpio, CTRL_OUT);
@@ -168,8 +167,7 @@ static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) · 20 unmodified lines
168 return val & 0x1;167 return val & 0x1;
169}168}
170 169
171static void crystalcove_gpio_set(struct gpio_chip *chip,170static void crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
172 unsigned int gpio, int value)
173{171{
174 struct crystalcove_gpio *cg = gpiochip_get_data(chip);172 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
175 int reg = to_reg(gpio, CTRL_OUT);173 int reg = to_reg(gpio, CTRL_OUT);
@@ -185,10 +183,10 @@ static void crystalcove_gpio_set(struct gpio_chip *chip, · 9 unmodified lines
185 183
186static int crystalcove_irq_type(struct irq_data *data, unsigned int type)184static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
187{185{
188 struct crystalcove_gpio *cg =186 struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
189 gpiochip_get_data(irq_data_get_irq_chip_data(data));187 irq_hw_number_t hwirq = irqd_to_hwirq(data);
190 188
191 if (data->hwirq >= CRYSTALCOVE_GPIO_NUM)189 if (hwirq >= CRYSTALCOVE_GPIO_NUM)
192 return 0;190 return 0;
193 191
194 switch (type) {192 switch (type) {
@@ -215,22 +213,20 @@ static int crystalcove_irq_type(struct irq_data *data, unsigned int type) · 20 unmodified lines
215 213
216static void crystalcove_bus_lock(struct irq_data *data)214static void crystalcove_bus_lock(struct irq_data *data)
217{215{
218 struct crystalcove_gpio *cg =216 struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
219 gpiochip_get_data(irq_data_get_irq_chip_data(data));
220 217
221 mutex_lock(&cg->buslock);218 mutex_lock(&cg->buslock);
222}219}
223 220
224static void crystalcove_bus_sync_unlock(struct irq_data *data)221static void crystalcove_bus_sync_unlock(struct irq_data *data)
225{222{
226 struct crystalcove_gpio *cg =223 struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
227 gpiochip_get_data(irq_data_get_irq_chip_data(data));224 irq_hw_number_t hwirq = irqd_to_hwirq(data);
228 int gpio = data->hwirq;
229 225
230 if (cg->update & UPDATE_IRQ_TYPE)226 if (cg->update & UPDATE_IRQ_TYPE)
231 crystalcove_update_irq_ctrl(cg, gpio);227 crystalcove_update_irq_ctrl(cg, hwirq);
232 if (cg->update & UPDATE_IRQ_MASK)228 if (cg->update & UPDATE_IRQ_MASK)
233 crystalcove_update_irq_mask(cg, gpio);229 crystalcove_update_irq_mask(cg, hwirq);
234 cg->update = 0;230 cg->update = 0;
235 231
236 mutex_unlock(&cg->buslock);232 mutex_unlock(&cg->buslock);
@@ -238,34 +234,43 @@ static void crystalcove_bus_sync_unlock(struct irq_data *data) · 1 unmodified line
238 234
239static void crystalcove_irq_unmask(struct irq_data *data)235static void crystalcove_irq_unmask(struct irq_data *data)
240{236{
241 struct crystalcove_gpio *cg =237 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
242 gpiochip_get_data(irq_data_get_irq_chip_data(data));238 struct crystalcove_gpio *cg = gpiochip_get_data(gc);
239 irq_hw_number_t hwirq = irqd_to_hwirq(data);
243 240
244 if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {241 if (hwirq >= CRYSTALCOVE_GPIO_NUM)
245 cg->set_irq_mask = false;242 return;
246 cg->update |= UPDATE_IRQ_MASK;243
247 }244 gpiochip_enable_irq(gc, hwirq);
245
246 cg->set_irq_mask = false;
247 cg->update |= UPDATE_IRQ_MASK;
248}248}
249 249
250static void crystalcove_irq_mask(struct irq_data *data)250static void crystalcove_irq_mask(struct irq_data *data)
251{251{
252 struct crystalcove_gpio *cg =252 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
253 gpiochip_get_data(irq_data_get_irq_chip_data(data));253 struct crystalcove_gpio *cg = gpiochip_get_data(gc);
254 irq_hw_number_t hwirq = irqd_to_hwirq(data);
254 255
255 if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {256 if (hwirq >= CRYSTALCOVE_GPIO_NUM)
256 cg->set_irq_mask = true;257 return;
257 cg->update |= UPDATE_IRQ_MASK;258
258 }259 cg->set_irq_mask = true;
260 cg->update |= UPDATE_IRQ_MASK;
261
262 gpiochip_disable_irq(gc, hwirq);
259}263}
260 264
261static struct irq_chip crystalcove_irqchip = {265static const struct irq_chip crystalcove_irqchip = {
262 .name = "Crystal Cove",266 .name = "Crystal Cove",
263 .irq_mask = crystalcove_irq_mask,267 .irq_mask = crystalcove_irq_mask,
264 .irq_unmask = crystalcove_irq_unmask,268 .irq_unmask = crystalcove_irq_unmask,
265 .irq_set_type = crystalcove_irq_type,269 .irq_set_type = crystalcove_irq_type,
266 .irq_bus_lock = crystalcove_bus_lock,270 .irq_bus_lock = crystalcove_bus_lock,
267 .irq_bus_sync_unlock = crystalcove_bus_sync_unlock,271 .irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
268 .flags = IRQCHIP_SKIP_SET_WAKE,272 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
273 GPIOCHIP_IRQ_RESOURCE_HELPERS,
269};274};
270 275
271static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)276static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
@@ -293,8 +298,7 @@ static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data) · 21 unmodified lines
293 return IRQ_HANDLED;298 return IRQ_HANDLED;
294}299}
295 300
296static void crystalcove_gpio_dbg_show(struct seq_file *s,301static void crystalcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
297 struct gpio_chip *chip)
298{302{
299 struct crystalcove_gpio *cg = gpiochip_get_data(chip);303 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
300 int gpio, offset;304 int gpio, offset;
@@ -353,7 +357,7 @@ static int crystalcove_gpio_probe(struct platform_device *pdev) · 52 unmodified lines
353 cg->regmap = pmic->regmap;357 cg->regmap = pmic->regmap;
354 358
355 girq = &cg->chip.irq;359 girq = &cg->chip.irq;
356 girq->chip = &crystalcove_irqchip;360 gpio_irq_chip_set_chip(girq, &crystalcove_irqchip);
357 /* This will let us handle the parent IRQ in the driver */361 /* This will let us handle the parent IRQ in the driver */
358 girq->parent_handler = NULL;362 girq->parent_handler = NULL;
359 girq->num_parents = 0;363 girq->num_parents = 0;
drivers/gpio/gpio-dln2.c+14−9
@@ -46,7 +46,6 @@ · 45 unmodified lines
46struct dln2_gpio {46struct dln2_gpio {
47 struct platform_device *pdev;47 struct platform_device *pdev;
48 struct gpio_chip gpio;48 struct gpio_chip gpio;
49 struct irq_chip irqchip;
50 49
51 /*50 /*
52 * Cache pin direction to save us one transfer, since the hardware has51 * Cache pin direction to save us one transfer, since the hardware has
@@ -306,6 +305,7 @@ static void dln2_irq_unmask(struct irq_data *irqd) · 253 unmodified lines
306 struct dln2_gpio *dln2 = gpiochip_get_data(gc);305 struct dln2_gpio *dln2 = gpiochip_get_data(gc);
307 int pin = irqd_to_hwirq(irqd);306 int pin = irqd_to_hwirq(irqd);
308 307
308 gpiochip_enable_irq(gc, pin);
309 set_bit(pin, dln2->unmasked_irqs);309 set_bit(pin, dln2->unmasked_irqs);
310}310}
311 311
@@ -316,6 +316,7 @@ static void dln2_irq_mask(struct irq_data *irqd) · 4 unmodified lines
316 int pin = irqd_to_hwirq(irqd);316 int pin = irqd_to_hwirq(irqd);
317 317
318 clear_bit(pin, dln2->unmasked_irqs);318 clear_bit(pin, dln2->unmasked_irqs);
319 gpiochip_disable_irq(gc, pin);
319}320}
320 321
321static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)322static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
@@ -384,6 +385,17 @@ static void dln2_irq_bus_unlock(struct irq_data *irqd) · 62 unmodified lines
384 mutex_unlock(&dln2->irq_lock);385 mutex_unlock(&dln2->irq_lock);
385}386}
386 387
388static const struct irq_chip dln2_irqchip = {
389 .name = "dln2-irq",
390 .irq_mask = dln2_irq_mask,
391 .irq_unmask = dln2_irq_unmask,
392 .irq_set_type = dln2_irq_set_type,
393 .irq_bus_lock = dln2_irq_bus_lock,
394 .irq_bus_sync_unlock = dln2_irq_bus_unlock,
395 .flags = IRQCHIP_IMMUTABLE,
396 GPIOCHIP_IRQ_RESOURCE_HELPERS,
397};
398
387static void dln2_gpio_event(struct platform_device *pdev, u16 echo,399static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
388 const void *data, int len)400 const void *data, int len)
389{401{
@@ -465,15 +477,8 @@ static int dln2_gpio_probe(struct platform_device *pdev) · 75 unmodified lines
465 dln2->gpio.direction_output = dln2_gpio_direction_output;477 dln2->gpio.direction_output = dln2_gpio_direction_output;
466 dln2->gpio.set_config = dln2_gpio_set_config;478 dln2->gpio.set_config = dln2_gpio_set_config;
467 479
468 dln2->irqchip.name = "dln2-irq",
469 dln2->irqchip.irq_mask = dln2_irq_mask,
470 dln2->irqchip.irq_unmask = dln2_irq_unmask,
471 dln2->irqchip.irq_set_type = dln2_irq_set_type,
472 dln2->irqchip.irq_bus_lock = dln2_irq_bus_lock,
473 dln2->irqchip.irq_bus_sync_unlock = dln2_irq_bus_unlock,
474
475 girq = &dln2->gpio.irq;480 girq = &dln2->gpio.irq;
476 girq->chip = &dln2->irqchip;481 gpio_irq_chip_set_chip(girq, &dln2_irqchip);
477 /* The event comes from the outside so no parent handler */482 /* The event comes from the outside so no parent handler */
478 girq->parent_handler = NULL;483 girq->parent_handler = NULL;
479 girq->num_parents = 0;484 girq->num_parents = 0;
drivers/gpio/gpio-merrifield.c+15−7
@@ -220,10 +220,8 @@ static void mrfld_irq_ack(struct irq_data *d) · 219 unmodified lines
220 raw_spin_unlock_irqrestore(&priv->lock, flags);220 raw_spin_unlock_irqrestore(&priv->lock, flags);
221}221}
222 222
223static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask)223static void mrfld_irq_unmask_mask(struct mrfld_gpio *priv, u32 gpio, bool unmask)
224{224{
225 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
226 u32 gpio = irqd_to_hwirq(d);
227 void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);225 void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
228 unsigned long flags;226 unsigned long flags;
229 u32 value;227 u32 value;
@@ -241,12 +239,20 @@ static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask) · 11 unmodified lines
241 239
242static void mrfld_irq_mask(struct irq_data *d)240static void mrfld_irq_mask(struct irq_data *d)
243{241{
244 mrfld_irq_unmask_mask(d, false);242 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
243 u32 gpio = irqd_to_hwirq(d);
244
245 mrfld_irq_unmask_mask(priv, gpio, false);
246 gpiochip_disable_irq(&priv->chip, gpio);
245}247}
246 248
247static void mrfld_irq_unmask(struct irq_data *d)249static void mrfld_irq_unmask(struct irq_data *d)
248{250{
249 mrfld_irq_unmask_mask(d, true);251 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
252 u32 gpio = irqd_to_hwirq(d);
253
254 gpiochip_enable_irq(&priv->chip, gpio);
255 mrfld_irq_unmask_mask(priv, gpio, true);
250}256}
251 257
252static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)258static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
@@ -329,13 +335,15 @@ static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on) · 76 unmodified lines
329 return 0;335 return 0;
330}336}
331 337
332static struct irq_chip mrfld_irqchip = {338static const struct irq_chip mrfld_irqchip = {
333 .name = "gpio-merrifield",339 .name = "gpio-merrifield",
334 .irq_ack = mrfld_irq_ack,340 .irq_ack = mrfld_irq_ack,
335 .irq_mask = mrfld_irq_mask,341 .irq_mask = mrfld_irq_mask,
336 .irq_unmask = mrfld_irq_unmask,342 .irq_unmask = mrfld_irq_unmask,
337 .irq_set_type = mrfld_irq_set_type,343 .irq_set_type = mrfld_irq_set_type,
338 .irq_set_wake = mrfld_irq_set_wake,344 .irq_set_wake = mrfld_irq_set_wake,
345 .flags = IRQCHIP_IMMUTABLE,
346 GPIOCHIP_IRQ_RESOURCE_HELPERS,
339};347};
340 348
341static void mrfld_irq_handler(struct irq_desc *desc)349static void mrfld_irq_handler(struct irq_desc *desc)
@@ -482,7 +490,7 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id · 140 unmodified lines
482 return retval;490 return retval;
483 491
484 girq = &priv->chip.irq;492 girq = &priv->chip.irq;
485 girq->chip = &mrfld_irqchip;493 gpio_irq_chip_set_chip(girq, &mrfld_irqchip);
486 girq->init_hw = mrfld_irq_init_hw;494 girq->init_hw = mrfld_irq_init_hw;
487 girq->parent_handler = mrfld_irq_handler;495 girq->parent_handler = mrfld_irq_handler;
488 girq->num_parents = 1;496 girq->num_parents = 1;
drivers/gpio/gpio-sch.c+22−13
@@ -38,7 +38,6 @@ · 37 unmodified lines
38 38
39struct sch_gpio {39struct sch_gpio {
40 struct gpio_chip chip;40 struct gpio_chip chip;
41 struct irq_chip irqchip;
42 spinlock_t lock;41 spinlock_t lock;
43 unsigned short iobase;42 unsigned short iobase;
44 unsigned short resume_base;43 unsigned short resume_base;
@@ -218,11 +217,9 @@ static void sch_irq_ack(struct irq_data *d) · 173 unmodified lines
218 spin_unlock_irqrestore(&sch->lock, flags);217 spin_unlock_irqrestore(&sch->lock, flags);
219}218}
220 219
221static void sch_irq_mask_unmask(struct irq_data *d, int val)220static void sch_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t gpio_num, int val)
222{221{
223 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
224 struct sch_gpio *sch = gpiochip_get_data(gc);222 struct sch_gpio *sch = gpiochip_get_data(gc);
225 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
226 unsigned long flags;223 unsigned long flags;
227 224
228 spin_lock_irqsave(&sch->lock, flags);225 spin_lock_irqsave(&sch->lock, flags);
@@ -232,14 +229,32 @@ static void sch_irq_mask_unmask(struct irq_data *d, int val) · 3 unmodified lines
232 229
233static void sch_irq_mask(struct irq_data *d)230static void sch_irq_mask(struct irq_data *d)
234{231{
235 sch_irq_mask_unmask(d, 0);232 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
233 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
234
235 sch_irq_mask_unmask(gc, gpio_num, 0);
236 gpiochip_disable_irq(gc, gpio_num);
236}237}
237 238
238static void sch_irq_unmask(struct irq_data *d)239static void sch_irq_unmask(struct irq_data *d)
239{240{
240 sch_irq_mask_unmask(d, 1);241 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
242 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
243
244 gpiochip_enable_irq(gc, gpio_num);
245 sch_irq_mask_unmask(gc, gpio_num, 1);
241}246}
242 247
248static const struct irq_chip sch_irqchip = {
249 .name = "sch_gpio",
250 .irq_ack = sch_irq_ack,
251 .irq_mask = sch_irq_mask,
252 .irq_unmask = sch_irq_unmask,
253 .irq_set_type = sch_irq_type,
254 .flags = IRQCHIP_IMMUTABLE,
255 GPIOCHIP_IRQ_RESOURCE_HELPERS,
256};
257
243static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)258static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)
244{259{
245 struct sch_gpio *sch = context;260 struct sch_gpio *sch = context;
@@ -367,14 +382,8 @@ static int sch_gpio_probe(struct platform_device *pdev) · 121 unmodified lines
367 382
368 platform_set_drvdata(pdev, sch);383 platform_set_drvdata(pdev, sch);
369 384
370 sch->irqchip.name = "sch_gpio";
371 sch->irqchip.irq_ack = sch_irq_ack;
372 sch->irqchip.irq_mask = sch_irq_mask;
373 sch->irqchip.irq_unmask = sch_irq_unmask;
374 sch->irqchip.irq_set_type = sch_irq_type;
375
376 girq = &sch->chip.irq;385 girq = &sch->chip.irq;
377 girq->chip = &sch->irqchip;386 gpio_irq_chip_set_chip(girq, &sch_irqchip);
378 girq->num_parents = 0;387 girq->num_parents = 0;
379 girq->parents = NULL;388 girq->parents = NULL;
380 girq->parent_handler = NULL;389 girq->parent_handler = NULL;
drivers/gpio/gpio-wcove.c+8−2
@@ -299,6 +299,8 @@ static void wcove_irq_unmask(struct irq_data *data) · 298 unmodified lines
299 if (gpio >= WCOVE_GPIO_NUM)299 if (gpio >= WCOVE_GPIO_NUM)
300 return;300 return;
301 301
302 gpiochip_enable_irq(chip, gpio);
303
302 wg->set_irq_mask = false;304 wg->set_irq_mask = false;
303 wg->update |= UPDATE_IRQ_MASK;305 wg->update |= UPDATE_IRQ_MASK;
304}306}
@@ -314,15 +316,19 @@ static void wcove_irq_mask(struct irq_data *data) · 9 unmodified lines
314 316
315 wg->set_irq_mask = true;317 wg->set_irq_mask = true;
316 wg->update |= UPDATE_IRQ_MASK;318 wg->update |= UPDATE_IRQ_MASK;
319
320 gpiochip_disable_irq(chip, gpio);
317}321}
318 322
319static struct irq_chip wcove_irqchip = {323static const struct irq_chip wcove_irqchip = {
320 .name = "Whiskey Cove",324 .name = "Whiskey Cove",
321 .irq_mask = wcove_irq_mask,325 .irq_mask = wcove_irq_mask,
322 .irq_unmask = wcove_irq_unmask,326 .irq_unmask = wcove_irq_unmask,
323 .irq_set_type = wcove_irq_type,327 .irq_set_type = wcove_irq_type,
324 .irq_bus_lock = wcove_bus_lock,328 .irq_bus_lock = wcove_bus_lock,
325 .irq_bus_sync_unlock = wcove_bus_sync_unlock,329 .irq_bus_sync_unlock = wcove_bus_sync_unlock,
330 .flags = IRQCHIP_IMMUTABLE,
331 GPIOCHIP_IRQ_RESOURCE_HELPERS,
326};332};
327 333
328static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)334static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
@@ -452,7 +458,7 @@ static int wcove_gpio_probe(struct platform_device *pdev) · 123 unmodified lines
452 }458 }
453 459
454 girq = &wg->chip.irq;460 girq = &wg->chip.irq;
455 girq->chip = &wcove_irqchip;461 gpio_irq_chip_set_chip(girq, &wcove_irqchip);
456 /* This will let us handle the parent IRQ in the driver */462 /* This will let us handle the parent IRQ in the driver */
457 girq->parent_handler = NULL;463 girq->parent_handler = NULL;
458 girq->num_parents = 0;464 girq->num_parents = 0;

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