drm/radeon: add a GPU reset counter queryable by userspace

Userspace will be able to tell whether a GPU reset occured by comparing an old referece value of the counter with a new value.

Marek Olšák committed 11 years ago

Commit 72b90761 parent c6e7e4b5 files · +9 −1Browse files

Unified · Split

5 files

@@ -2435,6 +2435,7 @@ struct radeon_device { · 2434 unmodified lines
2435	2435	atomic64_t vram_usage;
2436	2436	atomic64_t gtt_usage;
2437	2437	atomic64_t num_bytes_moved;
	2438	+ atomic_t gpu_reset_counter;
2438	2439	/* ACPI interface */
2439	2440	struct radeon_atif atif;
2440	2441	struct radeon_atcs atcs;

@@ -1725,6 +1725,8 @@ int radeon_gpu_reset(struct radeon_device *rdev) · 1724 unmodified lines
1725	1725	return 0;
1726	1726	}
1727	1727
	1728	+ atomic_inc(&rdev->gpu_reset_counter);
	1729	+
1728	1730	radeon_save_bios_scratch_regs(rdev);
1729	1731	/* block TTM */
1730	1732	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);

@@ -90,9 +90,10 @@ · 89 unmodified lines
90	90	* CS to GPU on >= r600
91	91	* 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
92	92	* 2.42.0 - Add VCE/VUI (Video Usability Information) support
	93	+ * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
93	94	*/
94	95	#define KMS_DRIVER_MAJOR 2
95		−#define KMS_DRIVER_MINOR 42
	96	+#define KMS_DRIVER_MINOR 43
96	97	#define KMS_DRIVER_PATCHLEVEL 0
97	98	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
98	99	int radeon_driver_unload_kms(struct drm_device *dev);

@@ -576,6 +576,9 @@ static int radeon_info_ioctl(struct drm_device dev, void data, struct drm_file · 575 unmodified lines
576	576	if (radeon_get_allowed_info_register(rdev, *value, value))
577	577	return -EINVAL;
578	578	break;
	579	+ case RADEON_INFO_GPU_RESET_COUNTER:
	580	+ *value = atomic_read(&rdev->gpu_reset_counter);
	581	+ break;
579	582	default:
580	583	DRM_DEBUG_KMS("Invalid request %d\n", info->request);
581	584	return -EINVAL;

@@ -1038,6 +1038,7 @@ struct drm_radeon_cs { · 1037 unmodified lines
1038	1038	#define RADEON_INFO_CURRENT_GPU_SCLK 0x22
1039	1039	#define RADEON_INFO_CURRENT_GPU_MCLK 0x23
1040	1040	#define RADEON_INFO_READ_REG 0x24
	1041	+#define RADEON_INFO_GPU_RESET_COUNTER 0x25
1041	1042
1042	1043	struct drm_radeon_info {
1043	1044	uint32_t request;