Pull networking updates from David Miller: "Highlights (1721 non-merge commits, this has to be a record of some sort): 1) Add 'random' mode to team driver, from Jiri Pirko and Eric Dumazet. 2) Make it so that any driver that supports configuration of multiple MAC addresses can provide the forwarding database add and del calls by providing a default implementation and hooking that up if the driver doesn't have an explicit set of handlers. From Vlad Yasevich. 3) Support GSO segmentation over tunnels and other encapsulating devices such as VXLAN, from Pravin B Shelar. 4) Support L2 GRE tunnels in the flow dissector, from Michael Dalton. 5) Implement Tail Loss Probe (TLP) detection in TCP, from Nandita Dukkipati. 6) In the PHY layer, allow supporting wake-on-lan in situations where the PHY registers have to be written for it to be configured. Use it to support wake-on-lan in mv643xx_eth. From Michael Stapelberg. 7) Significantly improve firewire IPV6 support, from YOSHIFUJI Hideaki. 8) Allow multiple packets to be sent in a single transmission using network coding in batman-adv, from Martin Hundebøll. 9) Add support for T5 cxgb4 chips, from Santosh Rastapur. 10) Generalize the VXLAN forwarding tables so that there is more flexibility in configurating various aspects of the endpoints. From David Stevens. 11) Support RSS and TSO in hardware over GRE tunnels in bxn2x driver, from Dmitry Kravkov. 12) Zero copy support in nfnelink_queue, from Eric Dumazet and Pablo Neira Ayuso. 13) Start adding networking selftests. 14) In situations of overload on the same AF_PACKET fanout socket, or per-cpu packet receive queue, minimize drop by distributing the load to other cpus/fanouts. From Willem de Bruijn and Eric Dumazet. 15) Add support for new payload offset BPF instruction, from Daniel Borkmann. 16) Convert several drivers over to mdoule_platform_driver(), from Sachin Kamat. 17) Provide a minimal BPF JIT image disassembler userspace tool, from Daniel Borkmann. 18) Rewrite F-RTO implementation in TCP to match the final specification of it in RFC4138 and RFC5682. From Yuchung Cheng. 19) Provide netlink socket diag of netlink sockets ("Yo dawg, I hear you like netlink, so I implemented netlink dumping of netlink sockets.") From Andrey Vagin. 20) Remove ugly passing of rtnetlink attributes into rtnl_doit functions, from Thomas Graf. 21) Allow userspace to be able to see if a configuration change occurs in the middle of an address or device list dump, from Nicolas Dichtel. 22) Support RFC3168 ECN protection for ipv6 fragments, from Hannes Frederic Sowa. 23) Increase accuracy of packet length used by packet scheduler, from Jason Wang. 24) Beginning set of changes to make ipv4/ipv6 fragment handling more scalable and less susceptible to overload and locking contention, from Jesper Dangaard Brouer. 25) Get rid of using non-type-safe NLMSG_* macros and use nlmsg_*() instead. From Hong Zhiguo. 26) Optimize route usage in IPVS by avoiding reference counting where possible, from Julian Anastasov. 27) Convert IPVS schedulers to RCU, also from Julian Anastasov. 28) Support cpu fanouts in xt_NFQUEUE netfilter target, from Holger Eitzenberger. 29) Network namespace support for nf_log, ebt_log, xt_LOG, ipt_ULOG, nfnetlink_log, and nfnetlink_queue. From Gao feng. 30) Implement RFC3168 ECN protection, from Hannes Frederic Sowa. 31) Support several new r8169 chips, from Hayes Wang. 32) Support tokenized interface identifiers in ipv6, from Daniel Borkmann. 33) Use usbnet_link_change() helper in USB net driver, from Ming Lei. 34) Add 802.1ad vlan offload support, from Patrick McHardy. 35) Support mmap() based netlink communication, also from Patrick McHardy. 36) Support HW timestamping in mlx4 driver, from Amir Vadai. 37) Rationalize AF_PACKET packet timestamping when transmitting, from Willem de Bruijn and Daniel Borkmann. 38) Bring parity to what's provided by /proc/net/packet socket dumping and the info provided by netlink socket dumping of AF_PACKET sockets. From Nicolas Dichtel. 39) Fix peeking beyond zero sized SKBs in AF_UNIX, from Benjamin Poirier" * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1722 commits) filter: fix va_list build error af_unix: fix a fatal race with bit fields bnx2x: Prevent memory leak when cnic is absent bnx2x: correct reading of speed capabilities net: sctp: attribute printl with __printf for gcc fmt checks netlink: kconfig: move mmap i/o into netlink kconfig netpoll: convert mutex into a semaphore netlink: Fix skb ref counting. net_sched: act_ipt forward compat with xtables mlx4_en: fix a build error on 32bit arches Revert "bnx2x: allow nvram test to run when device is down" bridge: avoid OOPS if root port not found drivers: net: cpsw: fix kernel warn on cpsw irq enable sh_eth: use random MAC address if no valid one supplied 3c509.c: call SET_NETDEV_DEV for all device types (ISA/ISAPnP/EISA) tg3: fix to append hardware time stamping flags unix/stream: fix peeking with an offset larger than data in queue unix/dgram: fix peeking with an offset larger than data in queue unix/dgram: peek beyond 0-sized skbs openvswitch: Remove unneeded ovs_netdev_get_ifindex() ...
Unified · Split
| @@ -67,6 +67,14 @@ Description: · 66 unmodified lines | |||
| 67 | Defines the penalty which will be applied to an | 67 | Defines the penalty which will be applied to an |
| 68 | originator message's tq-field on every hop. | 68 | originator message's tq-field on every hop. |
| 69 | 69 | ||
| 70 | What: /sys/class/net/<mesh_iface>/mesh/network_coding | ||
| 71 | Date: Nov 2012 | ||
| 72 | Contact: Martin Hundeboll <martin@hundeboll.net> | ||
| 73 | Description: | ||
| 74 | Controls whether Network Coding (using some magic | ||
| 75 | to send fewer wifi packets but still the same | ||
| 76 | content) is enabled or not. | ||
| 77 | |||
| 70 | What: /sys/class/net/<mesh_iface>/mesh/orig_interval | 78 | What: /sys/class/net/<mesh_iface>/mesh/orig_interval |
| 71 | Date: May 2010 | 79 | Date: May 2010 |
| 72 | Contact: Marek Lindner <lindner_marek@yahoo.de> | 80 | Contact: Marek Lindner <lindner_marek@yahoo.de> |
| @@ -437,7 +437,7 @@ · 436 unmodified lines | |||
| 437 | </section> | 437 | </section> |
| 438 | !Finclude/net/mac80211.h ieee80211_get_buffered_bc | 438 | !Finclude/net/mac80211.h ieee80211_get_buffered_bc |
| 439 | !Finclude/net/mac80211.h ieee80211_beacon_get | 439 | !Finclude/net/mac80211.h ieee80211_beacon_get |
| 440 | !Finclude/net/mac80211.h ieee80211_sta_eosp_irqsafe | 440 | !Finclude/net/mac80211.h ieee80211_sta_eosp |
| 441 | !Finclude/net/mac80211.h ieee80211_frame_release_type | 441 | !Finclude/net/mac80211.h ieee80211_frame_release_type |
| 442 | !Finclude/net/mac80211.h ieee80211_sta_ps_transition | 442 | !Finclude/net/mac80211.h ieee80211_sta_ps_transition |
| 443 | !Finclude/net/mac80211.h ieee80211_sta_ps_transition_ni | 443 | !Finclude/net/mac80211.h ieee80211_sta_ps_transition_ni |
| @@ -18,6 +18,8 @@ memcg_test.txt · 17 unmodified lines | |||
| 18 | - Memory Resource Controller; implementation details. | 18 | - Memory Resource Controller; implementation details. |
| 19 | memory.txt | 19 | memory.txt |
| 20 | - Memory Resource Controller; design, accounting, interface, testing. | 20 | - Memory Resource Controller; design, accounting, interface, testing. |
| 21 | net_cls.txt | ||
| 22 | - Network classifier cgroups details and usages. | ||
| 21 | net_prio.txt | 23 | net_prio.txt |
| 22 | - Network priority cgroups details and usages. | 24 | - Network priority cgroups details and usages. |
| 23 | resource_counter.txt | 25 | resource_counter.txt |
| @@ -0,0 +1,34 @@ | |||
| 1 | Network classifier cgroup | ||
| 2 | ------------------------- | ||
| 3 | |||
| 4 | The Network classifier cgroup provides an interface to | ||
| 5 | tag network packets with a class identifier (classid). | ||
| 6 | |||
| 7 | The Traffic Controller (tc) can be used to assign | ||
| 8 | different priorities to packets from different cgroups. | ||
| 9 | |||
| 10 | Creating a net_cls cgroups instance creates a net_cls.classid file. | ||
| 11 | This net_cls.classid value is initialized to 0. | ||
| 12 | |||
| 13 | You can write hexadecimal values to net_cls.classid; the format for these | ||
| 14 | values is 0xAAAABBBB; AAAA is the major handle number and BBBB | ||
| 15 | is the minor handle number. | ||
| 16 | Reading net_cls.classid yields a decimal result. | ||
| 17 | |||
| 18 | Example: | ||
| 19 | mkdir /sys/fs/cgroup/net_cls | ||
| 20 | mount -t cgroup -onet_cls net_cls /sys/fs/cgroup/net_cls | ||
| 21 | mkdir /sys/fs/cgroup/net_cls/0 | ||
| 22 | echo 0x100001 > /sys/fs/cgroup/net_cls/0/net_cls.classid | ||
| 23 | - setting a 10:1 handle. | ||
| 24 | |||
| 25 | cat /sys/fs/cgroup/net_cls/0/net_cls.classid | ||
| 26 | 1048577 | ||
| 27 | |||
| 28 | configuring tc: | ||
| 29 | tc qdisc add dev eth0 root handle 10: htb | ||
| 30 | |||
| 31 | tc class add dev eth0 parent 10: classid 10:1 htb rate 40mbit | ||
| 32 | - creating traffic class 10:1 | ||
| 33 | |||
| 34 | tc filter add dev eth0 parent 10: protocol ip prio 10 handle 1: cgroup | ||
| @@ -115,6 +115,9 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd. · 114 unmodified lines | |||
| 115 | - compatible : "marvell,mv64360-eth-block" | 115 | - compatible : "marvell,mv64360-eth-block" |
| 116 | - reg : Offset and length of the register set for this block | 116 | - reg : Offset and length of the register set for this block |
| 117 | 117 | ||
| 118 | Optional properties: | ||
| 119 | - clocks : Phandle to the clock control device and gate bit | ||
| 120 | |||
| 118 | Example Discovery Ethernet block node: | 121 | Example Discovery Ethernet block node: |
| 119 | ethernet-block@2000 { | 122 | ethernet-block@2000 { |
| 120 | #address-cells = <1>; | 123 | #address-cells = <1>; |
| @@ -0,0 +1,14 @@ | |||
| 1 | * AT91 CAN * | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: Should be "atmel,at91sam9263-can" or "atmel,at91sam9x5-can" | ||
| 5 | - reg: Should contain CAN controller registers location and length | ||
| 6 | - interrupts: Should contain IRQ line for the CAN controller | ||
| 7 | |||
| 8 | Example: | ||
| 9 | |||
| 10 | can0: can@f000c000 { | ||
| 11 | compatbile = "atmel,at91sam9x5-can"; | ||
| 12 | reg = <0xf000c000 0x300>; | ||
| 13 | interrupts = <40 4 5> | ||
| 14 | }; | ||
| @@ -15,16 +15,22 @@ Required properties: · 14 unmodified lines | |||
| 15 | - mac_control : Specifies Default MAC control register content | 15 | - mac_control : Specifies Default MAC control register content |
| 16 | for the specific platform | 16 | for the specific platform |
| 17 | - slaves : Specifies number for slaves | 17 | - slaves : Specifies number for slaves |
| 18 | - cpts_active_slave : Specifies the slave to use for time stamping | 18 | - active_slave : Specifies the slave to use for time stamping, |
| 19 | ethtool and SIOCGMIIPHY | ||
| 19 | - cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds | 20 | - cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds |
| 20 | - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds | 21 | - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds |
| 21 | - phy_id : Specifies slave phy id | ||
| 22 | - mac-address : Specifies slave MAC address | ||
| 23 | 22 | ||
| 24 | Optional properties: | 23 | Optional properties: |
| 25 | - ti,hwmods : Must be "cpgmac0" | 24 | - ti,hwmods : Must be "cpgmac0" |
| 26 | - no_bd_ram : Must be 0 or 1 | 25 | - no_bd_ram : Must be 0 or 1 |
| 27 | - dual_emac : Specifies Switch to act as Dual EMAC | 26 | - dual_emac : Specifies Switch to act as Dual EMAC |
| 27 | |||
| 28 | Slave Properties: | ||
| 29 | Required properties: | ||
| 30 | - phy_id : Specifies slave phy id | ||
| 31 | - mac-address : Specifies slave MAC address | ||
| 32 | |||
| 33 | Optional properties: | ||
| 28 | - dual_emac_res_vlan : Specifies VID to be used to segregate the ports | 34 | - dual_emac_res_vlan : Specifies VID to be used to segregate the ports |
| 29 | 35 | ||
| 30 | Note: "ti,hwmods" field is used to fetch the base address and irq | 36 | Note: "ti,hwmods" field is used to fetch the base address and irq |
| @@ -47,7 +53,7 @@ Examples: · 16 unmodified lines | |||
| 47 | rx_descs = <64>; | 53 | rx_descs = <64>; |
| 48 | mac_control = <0x20>; | 54 | mac_control = <0x20>; |
| 49 | slaves = <2>; | 55 | slaves = <2>; |
| 50 | cpts_active_slave = <0>; | 56 | active_slave = <0>; |
| 51 | cpts_clock_mult = <0x80000000>; | 57 | cpts_clock_mult = <0x80000000>; |
| 52 | cpts_clock_shift = <29>; | 58 | cpts_clock_shift = <29>; |
| 53 | cpsw_emac0: slave@0 { | 59 | cpsw_emac0: slave@0 { |
| @@ -73,7 +79,7 @@ Examples: · 19 unmodified lines | |||
| 73 | rx_descs = <64>; | 79 | rx_descs = <64>; |
| 74 | mac_control = <0x20>; | 80 | mac_control = <0x20>; |
| 75 | slaves = <2>; | 81 | slaves = <2>; |
| 76 | cpts_active_slave = <0>; | 82 | active_slave = <0>; |
| 77 | cpts_clock_mult = <0x80000000>; | 83 | cpts_clock_mult = <0x80000000>; |
| 78 | cpts_clock_shift = <29>; | 84 | cpts_clock_shift = <29>; |
| 79 | cpsw_emac0: slave@0 { | 85 | cpsw_emac0: slave@0 { |
| @@ -0,0 +1,91 @@ | |||
| 1 | Marvell Distributed Switch Architecture Device Tree Bindings | ||
| 2 | ------------------------------------------------------------ | ||
| 3 | |||
| 4 | Required properties: | ||
| 5 | - compatible : Should be "marvell,dsa" | ||
| 6 | - #address-cells : Must be 2, first cell is the address on the MDIO bus | ||
| 7 | and second cell is the address in the switch tree. | ||
| 8 | Second cell is used only when cascading/chaining. | ||
| 9 | - #size-cells : Must be 0 | ||
| 10 | - dsa,ethernet : Should be a phandle to a valid Ethernet device node | ||
| 11 | - dsa,mii-bus : Should be a phandle to a valid MDIO bus device node | ||
| 12 | |||
| 13 | Optionnal properties: | ||
| 14 | - interrupts : property with a value describing the switch | ||
| 15 | interrupt number (not supported by the driver) | ||
| 16 | |||
| 17 | A DSA node can contain multiple switch chips which are therefore child nodes of | ||
| 18 | the parent DSA node. The maximum number of allowed child nodes is 4 | ||
| 19 | (DSA_MAX_SWITCHES). | ||
| 20 | Each of these switch child nodes should have the following required properties: | ||
| 21 | |||
| 22 | - reg : Describes the switch address on the MII bus | ||
| 23 | - #address-cells : Must be 1 | ||
| 24 | - #size-cells : Must be 0 | ||
| 25 | |||
| 26 | A switch may have multiple "port" children nodes | ||
| 27 | |||
| 28 | Each port children node must have the following mandatory properties: | ||
| 29 | - reg : Describes the port address in the switch | ||
| 30 | - label : Describes the label associated with this port, special | ||
| 31 | labels are "cpu" to indicate a CPU port and "dsa" to | ||
| 32 | indicate an uplink/downlink port. | ||
| 33 | |||
| 34 | Note that a port labelled "dsa" will imply checking for the uplink phandle | ||
| 35 | described below. | ||
| 36 | |||
| 37 | Optionnal property: | ||
| 38 | - link : Should be a phandle to another switch's DSA port. | ||
| 39 | This property is only used when switches are being | ||
| 40 | chained/cascaded together. | ||
| 41 | |||
| 42 | Example: | ||
| 43 | |||
| 44 | dsa@0 { | ||
| 45 | compatible = "marvell,dsa"; | ||
| 46 | #address-cells = <2>; | ||
| 47 | #size-cells = <0>; | ||
| 48 | |||
| 49 | interrupts = <10>; | ||
| 50 | dsa,ethernet = <ðernet0>; | ||
| 51 | dsa,mii-bus = <&mii_bus0>; | ||
| 52 | |||
| 53 | switch@0 { | ||
| 54 | #address-cells = <1>; | ||
| 55 | #size-cells = <0>; | ||
| 56 | reg = <16 0>; /* MDIO address 16, switch 0 in tree */ | ||
| 57 | |||
| 58 | port@0 { | ||
| 59 | reg = <0>; | ||
| 60 | label = "lan1"; | ||
| 61 | }; | ||
| 62 | |||
| 63 | port@1 { | ||
| 64 | reg = <1>; | ||
| 65 | label = "lan2"; | ||
| 66 | }; | ||
| 67 | |||
| 68 | port@5 { | ||
| 69 | reg = <5>; | ||
| 70 | label = "cpu"; | ||
| 71 | }; | ||
| 72 | |||
| 73 | switch0uplink: port@6 { | ||
| 74 | reg = <6>; | ||
| 75 | label = "dsa"; | ||
| 76 | link = <&switch1uplink>; | ||
| 77 | }; | ||
| 78 | }; | ||
| 79 | |||
| 80 | switch@1 { | ||
| 81 | #address-cells = <1>; | ||
| 82 | #size-cells = <0>; | ||
| 83 | reg = <17 1>; /* MDIO address 17, switch 1 in tree */ | ||
| 84 | |||
| 85 | switch1uplink: port@0 { | ||
| 86 | reg = <0>; | ||
| 87 | label = "dsa"; | ||
| 88 | link = <&switch0uplink>; | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | }; | ||
| @@ -9,6 +9,10 @@ Required properties: · 8 unmodified lines | |||
| 9 | - compatible: "marvell,orion-mdio" | 9 | - compatible: "marvell,orion-mdio" |
| 10 | - reg: address and length of the SMI register | 10 | - reg: address and length of the SMI register |
| 11 | 11 | ||
| 12 | Optional properties: | ||
| 13 | - interrupts: interrupt line number for the SMI error/done interrupt | ||
| 14 | - clocks: Phandle to the clock control device and gate bit | ||
| 15 | |||
| 12 | The child nodes of the MDIO driver are the individual PHY devices | 16 | The child nodes of the MDIO driver are the individual PHY devices |
| 13 | connected to this MDIO bus. They must have a "reg" property given the | 17 | connected to this MDIO bus. They must have a "reg" property given the |
| 14 | PHY address on the MDIO bus. | 18 | PHY address on the MDIO bus. |
| @@ -71,8 +71,9 @@ submits skb to qdisc), so if you need something from that cb later, you should · 70 unmodified lines | |||
| 71 | store info in the skb->data on your own. | 71 | store info in the skb->data on your own. |
| 72 | 72 | ||
| 73 | To hook the MLME interface you have to populate the ml_priv field of your | 73 | To hook the MLME interface you have to populate the ml_priv field of your |
| 74 | net_device with a pointer to struct ieee802154_mlme_ops instance. All fields are | 74 | net_device with a pointer to struct ieee802154_mlme_ops instance. The fields |
| 75 | required. | 75 | assoc_req, assoc_resp, disassoc_req, start_req, and scan_req are optional. |
| 76 | All other fields are required. | ||
| 76 | 77 | ||
| 77 | We provide an example of simple HardMAC driver at drivers/ieee802154/fakehard.c | 78 | We provide an example of simple HardMAC driver at drivers/ieee802154/fakehard.c |
| 78 | 79 | ||
| @@ -29,7 +29,7 @@ route/max_size - INTEGER · 28 unmodified lines | |||
| 29 | neigh/default/gc_thresh1 - INTEGER | 29 | neigh/default/gc_thresh1 - INTEGER |
| 30 | Minimum number of entries to keep. Garbage collector will not | 30 | Minimum number of entries to keep. Garbage collector will not |
| 31 | purge entries if there are fewer than this number. | 31 | purge entries if there are fewer than this number. |
| 32 | Default: 256 | 32 | Default: 128 |
| 33 | 33 | ||
| 34 | neigh/default/gc_thresh3 - INTEGER | 34 | neigh/default/gc_thresh3 - INTEGER |
| 35 | Maximum number of neighbor entries allowed. Increase this | 35 | Maximum number of neighbor entries allowed. Increase this |
| @@ -175,14 +175,6 @@ tcp_congestion_control - STRING · 139 unmodified lines | |||
| 175 | is inherited. | 175 | is inherited. |
| 176 | [see setsockopt(listenfd, SOL_TCP, TCP_CONGESTION, "name" ...) ] | 176 | [see setsockopt(listenfd, SOL_TCP, TCP_CONGESTION, "name" ...) ] |
| 177 | 177 | ||
| 178 | tcp_cookie_size - INTEGER | ||
| 179 | Default size of TCP Cookie Transactions (TCPCT) option, that may be | ||
| 180 | overridden on a per socket basis by the TCPCT socket option. | ||
| 181 | Values greater than the maximum (16) are interpreted as the maximum. | ||
| 182 | Values greater than zero and less than the minimum (8) are interpreted | ||
| 183 | as the minimum. Odd values are interpreted as the next even value. | ||
| 184 | Default: 0 (off). | ||
| 185 | |||
| 186 | tcp_dsack - BOOLEAN | 178 | tcp_dsack - BOOLEAN |
| 187 | Allows TCP to send "duplicate" SACKs. | 179 | Allows TCP to send "duplicate" SACKs. |
| 188 | 180 | ||
| @@ -190,7 +182,9 @@ tcp_early_retrans - INTEGER · 1 unmodified line | |||
| 190 | Enable Early Retransmit (ER), per RFC 5827. ER lowers the threshold | 182 | Enable Early Retransmit (ER), per RFC 5827. ER lowers the threshold |
| 191 | for triggering fast retransmit when the amount of outstanding data is | 183 | for triggering fast retransmit when the amount of outstanding data is |
| 192 | small and when no previously unsent data can be transmitted (such | 184 | small and when no previously unsent data can be transmitted (such |
| 193 | that limited transmit could be used). | 185 | that limited transmit could be used). Also controls the use of |
| 186 | Tail loss probe (TLP) that converts RTOs occuring due to tail | ||
| 187 | losses into fast recovery (draft-dukkipati-tcpm-tcp-loss-probe-01). | ||
| 194 | Possible values: | 188 | Possible values: |
| 195 | 0 disables ER | 189 | 0 disables ER |
| 196 | 1 enables ER | 190 | 1 enables ER |
| @@ -198,7 +192,9 @@ tcp_early_retrans - INTEGER · 1 unmodified line | |||
| 198 | by a fourth of RTT. This mitigates connection falsely | 192 | by a fourth of RTT. This mitigates connection falsely |
| 199 | recovers when network has a small degree of reordering | 193 | recovers when network has a small degree of reordering |
| 200 | (less than 3 packets). | 194 | (less than 3 packets). |
| 201 | Default: 2 | 195 | 3 enables delayed ER and TLP. |
| 196 | 4 enables TLP only. | ||
| 197 | Default: 3 | ||
| 202 | 198 | ||
| 203 | tcp_ecn - INTEGER | 199 | tcp_ecn - INTEGER |
| 204 | Control use of Explicit Congestion Notification (ECN) by TCP. | 200 | Control use of Explicit Congestion Notification (ECN) by TCP. |
| @@ -229,36 +225,13 @@ tcp_fin_timeout - INTEGER · 24 unmodified lines | |||
| 229 | Default: 60 seconds | 225 | Default: 60 seconds |
| 230 | 226 | ||
| 231 | tcp_frto - INTEGER | 227 | tcp_frto - INTEGER |
| 232 | Enables Forward RTO-Recovery (F-RTO) defined in RFC4138. | 228 | Enables Forward RTO-Recovery (F-RTO) defined in RFC5682. |
| 233 | F-RTO is an enhanced recovery algorithm for TCP retransmission | 229 | F-RTO is an enhanced recovery algorithm for TCP retransmission |
| 234 | timeouts. It is particularly beneficial in wireless environments | 230 | timeouts. It is particularly beneficial in networks where the |
| 235 | where packet loss is typically due to random radio interference | 231 | RTT fluctuates (e.g., wireless). F-RTO is sender-side only |
| 236 | rather than intermediate router congestion. F-RTO is sender-side | 232 | modification. It does not require any support from the peer. |
| 237 | only modification. Therefore it does not require any support from | 233 | |
| 238 | the peer. | 234 | By default it's enabled with a non-zero value. 0 disables F-RTO. |
| 239 | |||
| 240 | If set to 1, basic version is enabled. 2 enables SACK enhanced | ||
| 241 | F-RTO if flow uses SACK. The basic version can be used also when | ||
| 242 | SACK is in use though scenario(s) with it exists where F-RTO | ||
| 243 | interacts badly with the packet counting of the SACK enabled TCP | ||
| 244 | flow. | ||
| 245 | |||
| 246 | tcp_frto_response - INTEGER | ||
| 247 | When F-RTO has detected that a TCP retransmission timeout was | ||
| 248 | spurious (i.e, the timeout would have been avoided had TCP set a | ||
| 249 | longer retransmission timeout), TCP has several options what to do | ||
| 250 | next. Possible values are: | ||
| 251 | 0 Rate halving based; a smooth and conservative response, | ||
| 252 | results in halved cwnd and ssthresh after one RTT | ||
| 253 | 1 Very conservative response; not recommended because even | ||
| 254 | though being valid, it interacts poorly with the rest of | ||
| 255 | Linux TCP, halves cwnd and ssthresh immediately | ||
| 256 | 2 Aggressive response; undoes congestion control measures | ||
| 257 | that are now known to be unnecessary (ignoring the | ||
| 258 | possibility of a lost retransmission that would require | ||
| 259 | TCP to be more cautious), cwnd and ssthresh are restored | ||
| 260 | to the values prior timeout | ||
| 261 | Default: 0 (rate halving based) | ||
| 262 | 235 | ||
| 263 | tcp_keepalive_time - INTEGER | 236 | tcp_keepalive_time - INTEGER |
| 264 | How often TCP sends out keepalive messages when keepalive is enabled. | 237 | How often TCP sends out keepalive messages when keepalive is enabled. |
| @@ -0,0 +1,339 @@ | |||
| 1 | This file documents how to use memory mapped I/O with netlink. | ||
| 2 | |||
| 3 | Author: Patrick McHardy <kaber@trash.net> | ||
| 4 | |||
| 5 | Overview | ||
| 6 | -------- | ||
| 7 | |||
| 8 | Memory mapped netlink I/O can be used to increase throughput and decrease | ||
| 9 | overhead of unicast receive and transmit operations. Some netlink subsystems | ||
| 10 | require high throughput, these are mainly the netfilter subsystems | ||
| 11 | nfnetlink_queue and nfnetlink_log, but it can also help speed up large | ||
| 12 | dump operations of f.i. the routing database. | ||
| 13 | |||
| 14 | Memory mapped netlink I/O used two circular ring buffers for RX and TX which | ||
| 15 | are mapped into the processes address space. | ||
| 16 | |||
| 17 | The RX ring is used by the kernel to directly construct netlink messages into | ||
| 18 | user-space memory without copying them as done with regular socket I/O, | ||
| 19 | additionally as long as the ring contains messages no recvmsg() or poll() | ||
| 20 | syscalls have to be issued by user-space to get more message. | ||
| 21 | |||
| 22 | The TX ring is used to process messages directly from user-space memory, the | ||
| 23 | kernel processes all messages contained in the ring using a single sendmsg() | ||
| 24 | call. | ||
| 25 | |||
| 26 | Usage overview | ||
| 27 | -------------- | ||
| 28 | |||
| 29 | In order to use memory mapped netlink I/O, user-space needs three main changes: | ||
| 30 | |||
| 31 | - ring setup | ||
| 32 | - conversion of the RX path to get messages from the ring instead of recvmsg() | ||
| 33 | - conversion of the TX path to construct messages into the ring | ||
| 34 | |||
| 35 | Ring setup is done using setsockopt() to provide the ring parameters to the | ||
| 36 | kernel, then a call to mmap() to map the ring into the processes address space: | ||
| 37 | |||
| 38 | - setsockopt(fd, SOL_NETLINK, NETLINK_RX_RING, ¶ms, sizeof(params)); | ||
| 39 | - setsockopt(fd, SOL_NETLINK, NETLINK_TX_RING, ¶ms, sizeof(params)); | ||
| 40 | - ring = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0) | ||
| 41 | |||
| 42 | Usage of either ring is optional, but even if only the RX ring is used the | ||
| 43 | mapping still needs to be writable in order to update the frame status after | ||
| 44 | processing. | ||
| 45 | |||
| 46 | Conversion of the reception path involves calling poll() on the file | ||
| 47 | descriptor, once the socket is readable the frames from the ring are | ||
| 48 | processsed in order until no more messages are available, as indicated by | ||
| 49 | a status word in the frame header. | ||
| 50 | |||
| 51 | On kernel side, in order to make use of memory mapped I/O on receive, the | ||
| 52 | originating netlink subsystem needs to support memory mapped I/O, otherwise | ||
| 53 | it will use an allocated socket buffer as usual and the contents will be | ||
| 54 | copied to the ring on transmission, nullifying most of the performance gains. | ||
| 55 | Dumps of kernel databases automatically support memory mapped I/O. | ||
| 56 | |||
| 57 | Conversion of the transmit path involves changing message contruction to | ||
| 58 | use memory from the TX ring instead of (usually) a buffer declared on the | ||
| 59 | stack and setting up the frame header approriately. Optionally poll() can | ||
| 60 | be used to wait for free frames in the TX ring. | ||
| 61 | |||
| 62 | Structured and definitions for using memory mapped I/O are contained in | ||
| 63 | <linux/netlink.h>. | ||
| 64 | |||
| 65 | RX and TX rings | ||
| 66 | ---------------- | ||
| 67 | |||
| 68 | Each ring contains a number of continous memory blocks, containing frames of | ||
| 69 | fixed size dependant on the parameters used for ring setup. | ||
| 70 | |||
| 71 | Ring: [ block 0 ] | ||
| 72 | [ frame 0 ] | ||
| 73 | [ frame 1 ] | ||
| 74 | [ block 1 ] | ||
| 75 | [ frame 2 ] | ||
| 76 | [ frame 3 ] | ||
| 77 | ... | ||
| 78 | [ block n ] | ||
| 79 | [ frame 2 * n ] | ||
| 80 | [ frame 2 * n + 1 ] | ||
| 81 | |||
| 82 | The blocks are only visible to the kernel, from the point of view of user-space | ||
| 83 | the ring just contains the frames in a continous memory zone. | ||
| 84 | |||
| 85 | The ring parameters used for setting up the ring are defined as follows: | ||
| 86 | |||
| 87 | struct nl_mmap_req { | ||
| 88 | unsigned int nm_block_size; | ||
| 89 | unsigned int nm_block_nr; | ||
| 90 | unsigned int nm_frame_size; | ||
| 91 | unsigned int nm_frame_nr; | ||
| 92 | }; | ||
| 93 | |||
| 94 | Frames are grouped into blocks, where each block is a continous region of memory | ||
| 95 | and holds nm_block_size / nm_frame_size frames. The total number of frames in | ||
| 96 | the ring is nm_frame_nr. The following invariants hold: | ||
| 97 | |||
| 98 | - frames_per_block = nm_block_size / nm_frame_size | ||
| 99 | |||
| 100 | - nm_frame_nr = frames_per_block * nm_block_nr | ||
| 101 | |||
| 102 | Some parameters are constrained, specifically: | ||
| 103 | |||
| 104 | - nm_block_size must be a multiple of the architectures memory page size. | ||
| 105 | The getpagesize() function can be used to get the page size. | ||
| 106 | |||
| 107 | - nm_frame_size must be equal or larger to NL_MMAP_HDRLEN, IOW a frame must be | ||
| 108 | able to hold at least the frame header | ||
| 109 | |||
| 110 | - nm_frame_size must be smaller or equal to nm_block_size | ||
| 111 | |||
| 112 | - nm_frame_size must be a multiple of NL_MMAP_MSG_ALIGNMENT | ||
| 113 | |||
| 114 | - nm_frame_nr must equal the actual number of frames as specified above. | ||
| 115 | |||
| 116 | When the kernel can't allocate phsyically continous memory for a ring block, | ||
| 117 | it will fall back to use physically discontinous memory. This might affect | ||
| 118 | performance negatively, in order to avoid this the nm_frame_size parameter | ||
| 119 | should be chosen to be as small as possible for the required frame size and | ||
| 120 | the number of blocks should be increased instead. | ||
| 121 | |||
| 122 | Ring frames | ||
| 123 | ------------ | ||
| 124 | |||
| 125 | Each frames contain a frame header, consisting of a synchronization word and some | ||
| 126 | meta-data, and the message itself. | ||
| 127 | |||
| 128 | Frame: [ header message ] | ||
| 129 | |||
| 130 | The frame header is defined as follows: | ||
| 131 | |||
| 132 | struct nl_mmap_hdr { | ||
| 133 | unsigned int nm_status; | ||
| 134 | unsigned int nm_len; | ||
| 135 | __u32 nm_group; | ||
| 136 | /* credentials */ | ||
| 137 | __u32 nm_pid; | ||
| 138 | __u32 nm_uid; | ||
| 139 | __u32 nm_gid; | ||
| 140 | }; | ||
| 141 | |||
| 142 | - nm_status is used for synchronizing processing between the kernel and user- | ||
| 143 | space and specifies ownership of the frame as well as the operation to perform | ||
| 144 | |||
| 145 | - nm_len contains the length of the message contained in the data area | ||
| 146 | |||
| 147 | - nm_group specified the destination multicast group of message | ||
| 148 | |||
| 149 | - nm_pid, nm_uid and nm_gid contain the netlink pid, UID and GID of the sending | ||
| 150 | process. These values correspond to the data available using SOCK_PASSCRED in | ||
| 151 | the SCM_CREDENTIALS cmsg. | ||
| 152 | |||
| 153 | The possible values in the status word are: | ||
| 154 | |||
| 155 | - NL_MMAP_STATUS_UNUSED: | ||
| 156 | RX ring: frame belongs to the kernel and contains no message | ||
| 157 | for user-space. Approriate action is to invoke poll() | ||
| 158 | to wait for new messages. | ||
| 159 | |||
| 160 | TX ring: frame belongs to user-space and can be used for | ||
| 161 | message construction. | ||
| 162 | |||
| 163 | - NL_MMAP_STATUS_RESERVED: | ||
| 164 | RX ring only: frame is currently used by the kernel for message | ||
| 165 | construction and contains no valid message yet. | ||
| 166 | Appropriate action is to invoke poll() to wait for | ||
| 167 | new messages. | ||
| 168 | |||
| 169 | - NL_MMAP_STATUS_VALID: | ||
| 170 | RX ring: frame contains a valid message. Approriate action is | ||
| 171 | to process the message and release the frame back to | ||
| 172 | the kernel by setting the status to | ||
| 173 | NL_MMAP_STATUS_UNUSED or queue the frame by setting the | ||
| 174 | status to NL_MMAP_STATUS_SKIP. | ||
| 175 | |||
| 176 | TX ring: the frame contains a valid message from user-space to | ||
| 177 | be processed by the kernel. After completing processing | ||
| 178 | the kernel will release the frame back to user-space by | ||
| 179 | setting the status to NL_MMAP_STATUS_UNUSED. | ||
| 180 | |||
| 181 | - NL_MMAP_STATUS_COPY: | ||
| 182 | RX ring only: a message is ready to be processed but could not be | ||
| 183 | stored in the ring, either because it exceeded the | ||
| 184 | frame size or because the originating subsystem does | ||
| 185 | not support memory mapped I/O. Appropriate action is | ||
| 186 | to invoke recvmsg() to receive the message and release | ||
| 187 | the frame back to the kernel by setting the status to | ||
| 188 | NL_MMAP_STATUS_UNUSED. | ||
| 189 | |||
| 190 | - NL_MMAP_STATUS_SKIP: | ||
| 191 | RX ring only: user-space queued the message for later processing, but | ||
| 192 | processed some messages following it in the ring. The | ||
| 193 | kernel should skip this frame when looking for unused | ||
| 194 | frames. | ||
| 195 | |||
| 196 | The data area of a frame begins at a offset of NL_MMAP_HDRLEN relative to the | ||
| 197 | frame header. | ||
| 198 | |||
| 199 | TX limitations | ||
| 200 | -------------- | ||
| 201 | |||
| 202 | Kernel processing usually involves validation of the message received by | ||
| 203 | user-space, then processing its contents. The kernel must assure that | ||
| 204 | userspace is not able to modify the message contents after they have been | ||
| 205 | validated. In order to do so, the message is copied from the ring frame | ||
| 206 | to an allocated buffer if either of these conditions is false: | ||
| 207 | |||
| 208 | - only a single mapping of the ring exists | ||
| 209 | - the file descriptor is not shared between processes | ||
| 210 | |||
| 211 | This means that for threaded programs, the kernel will fall back to copying. | ||
| 212 | |||
| 213 | Example | ||
| 214 | ------- | ||
| 215 | |||
| 216 | Ring setup: | ||
| 217 | |||
| 218 | unsigned int block_size = 16 * getpagesize(); | ||
| 219 | struct nl_mmap_req req = { | ||
| 220 | .nm_block_size = block_size, | ||
| 221 | .nm_block_nr = 64, | ||
| 222 | .nm_frame_size = 16384, | ||
| 223 | .nm_frame_nr = 64 * block_size / 16384, | ||
| 224 | }; | ||
| 225 | unsigned int ring_size; | ||
| 226 | void *rx_ring, *tx_ring; | ||
| 227 | |||
| 228 | /* Configure ring parameters */ | ||
| 229 | if (setsockopt(fd, NETLINK_RX_RING, &req, sizeof(req)) < 0) | ||
| 230 | exit(1); | ||
| 231 | if (setsockopt(fd, NETLINK_TX_RING, &req, sizeof(req)) < 0) | ||
| 232 | exit(1) | ||
| 233 | |||
| 234 | /* Calculate size of each invididual ring */ | ||
| 235 | ring_size = req.nm_block_nr * req.nm_block_size; | ||
| 236 | |||
| 237 | /* Map RX/TX rings. The TX ring is located after the RX ring */ | ||
| 238 | rx_ring = mmap(NULL, 2 * ring_size, PROT_READ | PROT_WRITE, | ||
| 239 | MAP_SHARED, fd, 0); | ||
| 240 | if ((long)rx_ring == -1L) | ||
| 241 | exit(1); | ||
| 242 | tx_ring = rx_ring + ring_size: | ||
| 243 | |||
| 244 | Message reception: | ||
| 245 | |||
| 246 | This example assumes some ring parameters of the ring setup are available. | ||
| 247 | |||
| 248 | unsigned int frame_offset = 0; | ||
| 249 | struct nl_mmap_hdr *hdr; | ||
| 250 | struct nlmsghdr *nlh; | ||
| 251 | unsigned char buf[16384]; | ||
| 252 | ssize_t len; | ||
| 253 | |||
| 254 | while (1) { | ||
| 255 | struct pollfd pfds[1]; | ||
| 256 | |||
| 257 | pfds[0].fd = fd; | ||
| 258 | pfds[0].events = POLLIN | POLLERR; | ||
| 259 | pfds[0].revents = 0; | ||
| 260 | |||
| 261 | if (poll(pfds, 1, -1) < 0 && errno != -EINTR) | ||
| 262 | exit(1); | ||
| 263 | |||
| 264 | /* Check for errors. Error handling omitted */ | ||
| 265 | if (pfds[0].revents & POLLERR) | ||
| 266 | <handle error> | ||
| 267 | |||
| 268 | /* If no new messages, poll again */ | ||
| 269 | if (!(pfds[0].revents & POLLIN)) | ||
| 270 | continue; | ||
| 271 | |||
| 272 | /* Process all frames */ | ||
| 273 | while (1) { | ||
| 274 | /* Get next frame header */ | ||
| 275 | hdr = rx_ring + frame_offset; | ||
| 276 | |||
| 277 | if (hdr->nm_status == NL_MMAP_STATUS_VALID) | ||
| 278 | /* Regular memory mapped frame */ | ||
| 279 | nlh = (void *hdr) + NL_MMAP_HDRLEN; | ||
| 280 | len = hdr->nm_len; | ||
| 281 | |||
| 282 | /* Release empty message immediately. May happen | ||
| 283 | * on error during message construction. | ||
| 284 | */ | ||
| 285 | if (len == 0) | ||
| 286 | goto release; | ||
| 287 | } else if (hdr->nm_status == NL_MMAP_STATUS_COPY) { | ||
| 288 | /* Frame queued to socket receive queue */ | ||
| 289 | len = recv(fd, buf, sizeof(buf), MSG_DONTWAIT); | ||
| 290 | if (len <= 0) | ||
| 291 | break; | ||
| 292 | nlh = buf; | ||
| 293 | } else | ||
| 294 | /* No more messages to process, continue polling */ | ||
| 295 | break; | ||
| 296 | |||
| 297 | process_msg(nlh); | ||
| 298 | release: | ||
| 299 | /* Release frame back to the kernel */ | ||
| 300 | hdr->nm_status = NL_MMAP_STATUS_UNUSED; | ||
| 301 | |||
| 302 | /* Advance frame offset to next frame */ | ||
| 303 | frame_offset = (frame_offset + frame_size) % ring_size; | ||
| 304 | } | ||
| 305 | } | ||
| 306 | |||
| 307 | Message transmission: | ||
| 308 | |||
| 309 | This example assumes some ring parameters of the ring setup are available. | ||
| 310 | A single message is constructed and transmitted, to send multiple messages | ||
| 311 | at once they would be constructed in consecutive frames before a final call | ||
| 312 | to sendto(). | ||
| 313 | |||
| 314 | unsigned int frame_offset = 0; | ||
| 315 | struct nl_mmap_hdr *hdr; | ||
| 316 | struct nlmsghdr *nlh; | ||
| 317 | struct sockaddr_nl addr = { | ||
| 318 | .nl_family = AF_NETLINK, | ||
| 319 | }; | ||
| 320 | |||
| 321 | hdr = tx_ring + frame_offset; | ||
| 322 | if (hdr->nm_status != NL_MMAP_STATUS_UNUSED) | ||
| 323 | /* No frame available. Use poll() to avoid. */ | ||
| 324 | exit(1); | ||
| 325 | |||
| 326 | nlh = (void *)hdr + NL_MMAP_HDRLEN; | ||
| 327 | |||
| 328 | /* Build message */ | ||
| 329 | build_message(nlh); | ||
| 330 | |||
| 331 | /* Fill frame header: length and status need to be set */ | ||
| 332 | hdr->nm_len = nlh->nlmsg_len; | ||
| 333 | hdr->nm_status = NL_MMAP_STATUS_VALID; | ||
| 334 | |||
| 335 | if (sendto(fd, NULL, 0, 0, &addr, sizeof(addr)) < 0) | ||
| 336 | exit(1); | ||
| 337 | |||
| 338 | /* Advance frame offset to next frame */ | ||
| 339 | frame_offset = (frame_offset + frame_size) % ring_size; | ||
| @@ -684,15 +684,343 @@ int main(int argc, char **argp) · 683 unmodified lines | |||
| 684 | return 0; | 684 | return 0; |
| 685 | } | 685 | } |
| 686 | 686 | ||
| 687 | ------------------------------------------------------------------------------- | ||
| 688 | + AF_PACKET TPACKET_V3 example | ||
| 689 | ------------------------------------------------------------------------------- | ||
| 690 | |||
| 691 | AF_PACKET's TPACKET_V3 ring buffer can be configured to use non-static frame | ||
| 692 | sizes by doing it's own memory management. It is based on blocks where polling | ||
| 693 | works on a per block basis instead of per ring as in TPACKET_V2 and predecessor. | ||
| 694 | |||
| 695 | It is said that TPACKET_V3 brings the following benefits: | ||
| 696 | *) ~15 - 20% reduction in CPU-usage | ||
| 697 | *) ~20% increase in packet capture rate | ||
| 698 | *) ~2x increase in packet density | ||
| 699 | *) Port aggregation analysis | ||
| 700 | *) Non static frame size to capture entire packet payload | ||
| 701 | |||
| 702 | So it seems to be a good candidate to be used with packet fanout. | ||
| 703 | |||
| 704 | Minimal example code by Daniel Borkmann based on Chetan Loke's lolpcap (compile | ||
| 705 | it with gcc -Wall -O2 blob.c, and try things like "./a.out eth0", etc.): | ||
| 706 | |||
| 707 | #include <stdio.h> | ||
| 708 | #include <stdlib.h> | ||
| 709 | #include <stdint.h> | ||
| 710 | #include <string.h> | ||
| 711 | #include <assert.h> | ||
| 712 | #include <net/if.h> | ||
| 713 | #include <arpa/inet.h> | ||
| 714 | #include <netdb.h> | ||
| 715 | #include <poll.h> | ||
| 716 | #include <unistd.h> | ||
| 717 | #include <signal.h> | ||
| 718 | #include <inttypes.h> | ||
| 719 | #include <sys/socket.h> | ||
| 720 | #include <sys/mman.h> | ||
| 721 | #include <linux/if_packet.h> | ||
| 722 | #include <linux/if_ether.h> | ||
| 723 | #include <linux/ip.h> | ||
| 724 | |||
| 725 | #define BLOCK_SIZE (1 << 22) | ||
| 726 | #define FRAME_SIZE 2048 | ||
| 727 | |||
| 728 | #define NUM_BLOCKS 64 | ||
| 729 | #define NUM_FRAMES ((BLOCK_SIZE * NUM_BLOCKS) / FRAME_SIZE) | ||
| 730 | |||
| 731 | #define BLOCK_RETIRE_TOV_IN_MS 64 | ||
| 732 | #define BLOCK_PRIV_AREA_SZ 13 | ||
| 733 | |||
| 734 | #define ALIGN_8(x) (((x) + 8 - 1) & ~(8 - 1)) | ||
| 735 | |||
| 736 | #define BLOCK_STATUS(x) ((x)->h1.block_status) | ||
| 737 | #define BLOCK_NUM_PKTS(x) ((x)->h1.num_pkts) | ||
| 738 | #define BLOCK_O2FP(x) ((x)->h1.offset_to_first_pkt) | ||
| 739 | #define BLOCK_LEN(x) ((x)->h1.blk_len) | ||
| 740 | #define BLOCK_SNUM(x) ((x)->h1.seq_num) | ||
| 741 | #define BLOCK_O2PRIV(x) ((x)->offset_to_priv) | ||
| 742 | #define BLOCK_PRIV(x) ((void *) ((uint8_t *) (x) + BLOCK_O2PRIV(x))) | ||
| 743 | #define BLOCK_HDR_LEN (ALIGN_8(sizeof(struct block_desc))) | ||
| 744 | #define BLOCK_PLUS_PRIV(sz_pri) (BLOCK_HDR_LEN + ALIGN_8((sz_pri))) | ||
| 745 | |||
| 746 | #ifndef likely | ||
| 747 | # define likely(x) __builtin_expect(!!(x), 1) | ||
| 748 | #endif | ||
| 749 | #ifndef unlikely | ||
| 750 | # define unlikely(x) __builtin_expect(!!(x), 0) | ||
| 751 | #endif | ||
| 752 | |||
| 753 | struct block_desc { | ||
| 754 | uint32_t version; | ||
| 755 | uint32_t offset_to_priv; | ||
| 756 | struct tpacket_hdr_v1 h1; | ||
| 757 | }; | ||
| 758 | |||
| 759 | struct ring { | ||
| 760 | struct iovec *rd; | ||
| 761 | uint8_t *map; | ||
| 762 | struct tpacket_req3 req; | ||
| 763 | }; | ||
| 764 | |||
| 765 | static unsigned long packets_total = 0, bytes_total = 0; | ||
| 766 | static sig_atomic_t sigint = 0; | ||
| 767 | |||
| 768 | void sighandler(int num) | ||
| 769 | { | ||
| 770 | sigint = 1; | ||
| 771 | } | ||
| 772 | |||
| 773 | static int setup_socket(struct ring *ring, char *netdev) | ||
| 774 | { | ||
| 775 | int err, i, fd, v = TPACKET_V3; | ||
| 776 | struct sockaddr_ll ll; | ||
| 777 | |||
| 778 | fd = socket(AF_PACKET, SOCK_RAW, htons(ETH_P_ALL)); | ||
| 779 | if (fd < 0) { | ||
| 780 | perror("socket"); | ||
| 781 | exit(1); | ||
| 782 | } | ||
| 783 | |||
| 784 | err = setsockopt(fd, SOL_PACKET, PACKET_VERSION, &v, sizeof(v)); | ||
| 785 | if (err < 0) { | ||
| 786 | perror("setsockopt"); | ||
| 787 | exit(1); | ||
| 788 | } | ||
| 789 | |||
| 790 | memset(&ring->req, 0, sizeof(ring->req)); | ||
| 791 | ring->req.tp_block_size = BLOCK_SIZE; | ||
| 792 | ring->req.tp_frame_size = FRAME_SIZE; | ||
| 793 | ring->req.tp_block_nr = NUM_BLOCKS; | ||
| 794 | ring->req.tp_frame_nr = NUM_FRAMES; | ||
| 795 | ring->req.tp_retire_blk_tov = BLOCK_RETIRE_TOV_IN_MS; | ||
| 796 | ring->req.tp_sizeof_priv = BLOCK_PRIV_AREA_SZ; | ||
| 797 | ring->req.tp_feature_req_word |= TP_FT_REQ_FILL_RXHASH; | ||
| 798 | |||
| 799 | err = setsockopt(fd, SOL_PACKET, PACKET_RX_RING, &ring->req, | ||
| 800 | sizeof(ring->req)); | ||
| 801 | if (err < 0) { | ||
| 802 | perror("setsockopt"); | ||
| 803 | exit(1); | ||
| 804 | } | ||
| 805 | |||
| 806 | ring->map = mmap(NULL, ring->req.tp_block_size * ring->req.tp_block_nr, | ||
| 807 | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_LOCKED, | ||
| 808 | fd, 0); | ||
| 809 | if (ring->map == MAP_FAILED) { | ||
| 810 | perror("mmap"); | ||
| 811 | exit(1); | ||
| 812 | } | ||
| 813 | |||
| 814 | ring->rd = malloc(ring->req.tp_block_nr * sizeof(*ring->rd)); | ||
| 815 | assert(ring->rd); | ||
| 816 | for (i = 0; i < ring->req.tp_block_nr; ++i) { | ||
| 817 | ring->rd[i].iov_base = ring->map + (i * ring->req.tp_block_size); | ||
| 818 | ring->rd[i].iov_len = ring->req.tp_block_size; | ||
| 819 | } | ||
| 820 | |||
| 821 | memset(&ll, 0, sizeof(ll)); | ||
| 822 | ll.sll_family = PF_PACKET; | ||
| 823 | ll.sll_protocol = htons(ETH_P_ALL); | ||
| 824 | ll.sll_ifindex = if_nametoindex(netdev); | ||
| 825 | ll.sll_hatype = 0; | ||
| 826 | ll.sll_pkttype = 0; | ||
| 827 | ll.sll_halen = 0; | ||
| 828 | |||
| 829 | err = bind(fd, (struct sockaddr *) &ll, sizeof(ll)); | ||
| 830 | if (err < 0) { | ||
| 831 | perror("bind"); | ||
| 832 | exit(1); | ||
| 833 | } | ||
| 834 | |||
| 835 | return fd; | ||
| 836 | } | ||
| 837 | |||
| 838 | #ifdef __checked | ||
| 839 | static uint64_t prev_block_seq_num = 0; | ||
| 840 | |||
| 841 | void assert_block_seq_num(struct block_desc *pbd) | ||
| 842 | { | ||
| 843 | if (unlikely(prev_block_seq_num + 1 != BLOCK_SNUM(pbd))) { | ||
| 844 | printf("prev_block_seq_num:%"PRIu64", expected seq:%"PRIu64" != " | ||
| 845 | "actual seq:%"PRIu64"\n", prev_block_seq_num, | ||
| 846 | prev_block_seq_num + 1, (uint64_t) BLOCK_SNUM(pbd)); | ||
| 847 | exit(1); | ||
| 848 | } | ||
| 849 | |||
| 850 | prev_block_seq_num = BLOCK_SNUM(pbd); | ||
| 851 | } | ||
| 852 | |||
| 853 | static void assert_block_len(struct block_desc *pbd, uint32_t bytes, int block_num) | ||
| 854 | { | ||
| 855 | if (BLOCK_NUM_PKTS(pbd)) { | ||
| 856 | if (unlikely(bytes != BLOCK_LEN(pbd))) { | ||
| 857 | printf("block:%u with %upackets, expected len:%u != actual len:%u\n", | ||
| 858 | block_num, BLOCK_NUM_PKTS(pbd), bytes, BLOCK_LEN(pbd)); | ||
| 859 | exit(1); | ||
| 860 | } | ||
| 861 | } else { | ||
| 862 | if (unlikely(BLOCK_LEN(pbd) != BLOCK_PLUS_PRIV(BLOCK_PRIV_AREA_SZ))) { | ||
| 863 | printf("block:%u, expected len:%lu != actual len:%u\n", | ||
| 864 | block_num, BLOCK_HDR_LEN, BLOCK_LEN(pbd)); | ||
| 865 | exit(1); | ||
| 866 | } | ||
| 867 | } | ||
| 868 | } | ||
| 869 | |||
| 870 | static void assert_block_header(struct block_desc *pbd, const int block_num) | ||
| 871 | { | ||
| 872 | uint32_t block_status = BLOCK_STATUS(pbd); | ||
| 873 | |||
| 874 | if (unlikely((block_status & TP_STATUS_USER) == 0)) { | ||
| 875 | printf("block:%u, not in TP_STATUS_USER\n", block_num); | ||
| 876 | exit(1); | ||
| 877 | } | ||
| 878 | |||
| 879 | assert_block_seq_num(pbd); | ||
| 880 | } | ||
| 881 | #else | ||
| 882 | static inline void assert_block_header(struct block_desc *pbd, const int block_num) | ||
| 883 | { | ||
| 884 | } | ||
| 885 | static void assert_block_len(struct block_desc *pbd, uint32_t bytes, int block_num) | ||
| 886 | { | ||
| 887 | } | ||
| 888 | #endif | ||
| 889 | |||
| 890 | static void display(struct tpacket3_hdr *ppd) | ||
| 891 | { | ||
| 892 | struct ethhdr *eth = (struct ethhdr *) ((uint8_t *) ppd + ppd->tp_mac); | ||
| 893 | struct iphdr *ip = (struct iphdr *) ((uint8_t *) eth + ETH_HLEN); | ||
| 894 | |||
| 895 | if (eth->h_proto == htons(ETH_P_IP)) { | ||
| 896 | struct sockaddr_in ss, sd; | ||
| 897 | char sbuff[NI_MAXHOST], dbuff[NI_MAXHOST]; | ||
| 898 | |||
| 899 | memset(&ss, 0, sizeof(ss)); | ||
| 900 | ss.sin_family = PF_INET; | ||
| 901 | ss.sin_addr.s_addr = ip->saddr; | ||
| 902 | getnameinfo((struct sockaddr *) &ss, sizeof(ss), | ||
| 903 | sbuff, sizeof(sbuff), NULL, 0, NI_NUMERICHOST); | ||
| 904 | |||
| 905 | memset(&sd, 0, sizeof(sd)); | ||
| 906 | sd.sin_family = PF_INET; | ||
| 907 | sd.sin_addr.s_addr = ip->daddr; | ||
| 908 | getnameinfo((struct sockaddr *) &sd, sizeof(sd), | ||
| 909 | dbuff, sizeof(dbuff), NULL, 0, NI_NUMERICHOST); | ||
| 910 | |||
| 911 | printf("%s -> %s, ", sbuff, dbuff); | ||
| 912 | } | ||
| 913 | |||
| 914 | printf("rxhash: 0x%x\n", ppd->hv1.tp_rxhash); | ||
| 915 | } | ||
| 916 | |||
| 917 | static void walk_block(struct block_desc *pbd, const int block_num) | ||
| 918 | { | ||
| 919 | int num_pkts = BLOCK_NUM_PKTS(pbd), i; | ||
| 920 | unsigned long bytes = 0; | ||
| 921 | unsigned long bytes_with_padding = BLOCK_PLUS_PRIV(BLOCK_PRIV_AREA_SZ); | ||
| 922 | struct tpacket3_hdr *ppd; | ||
| 923 | |||
| 924 | assert_block_header(pbd, block_num); | ||
| 925 | |||
| 926 | ppd = (struct tpacket3_hdr *) ((uint8_t *) pbd + BLOCK_O2FP(pbd)); | ||
| 927 | for (i = 0; i < num_pkts; ++i) { | ||
| 928 | bytes += ppd->tp_snaplen; | ||
| 929 | if (ppd->tp_next_offset) | ||
| 930 | bytes_with_padding += ppd->tp_next_offset; | ||
| 931 | else | ||
| 932 | bytes_with_padding += ALIGN_8(ppd->tp_snaplen + ppd->tp_mac); | ||
| 933 | |||
| 934 | display(ppd); | ||
| 935 | |||
| 936 | ppd = (struct tpacket3_hdr *) ((uint8_t *) ppd + ppd->tp_next_offset); | ||
| 937 | __sync_synchronize(); | ||
| 938 | } | ||
| 939 | |||
| 940 | assert_block_len(pbd, bytes_with_padding, block_num); | ||
| 941 | |||
| 942 | packets_total += num_pkts; | ||
| 943 | bytes_total += bytes; | ||
| 944 | } | ||
| 945 | |||
| 946 | void flush_block(struct block_desc *pbd) | ||
| 947 | { | ||
| 948 | BLOCK_STATUS(pbd) = TP_STATUS_KERNEL; | ||
| 949 | __sync_synchronize(); | ||
| 950 | } | ||
| 951 | |||
| 952 | static void teardown_socket(struct ring *ring, int fd) | ||
| 953 | { | ||
| 954 | munmap(ring->map, ring->req.tp_block_size * ring->req.tp_block_nr); | ||
| 955 | free(ring->rd); | ||
| 956 | close(fd); | ||
| 957 | } | ||
| 958 | |||
| 959 | int main(int argc, char **argp) | ||
| 960 | { | ||
| 961 | int fd, err; | ||
| 962 | socklen_t len; | ||
| 963 | struct ring ring; | ||
| 964 | struct pollfd pfd; | ||
| 965 | unsigned int block_num = 0; | ||
| 966 | struct block_desc *pbd; | ||
| 967 | struct tpacket_stats_v3 stats; | ||
| 968 | |||
| 969 | if (argc != 2) { | ||
| 970 | fprintf(stderr, "Usage: %s INTERFACE\n", argp[0]); | ||
| 971 | return EXIT_FAILURE; | ||
| 972 | } | ||
| 973 | |||
| 974 | signal(SIGINT, sighandler); | ||
| 975 | |||
| 976 | memset(&ring, 0, sizeof(ring)); | ||
| 977 | fd = setup_socket(&ring, argp[argc - 1]); | ||
| 978 | assert(fd > 0); | ||
| 979 | |||
| 980 | memset(&pfd, 0, sizeof(pfd)); | ||
| 981 | pfd.fd = fd; | ||
| 982 | pfd.events = POLLIN | POLLERR; | ||
| 983 | pfd.revents = 0; | ||
| 984 | |||
| 985 | while (likely(!sigint)) { | ||
| 986 | pbd = (struct block_desc *) ring.rd[block_num].iov_base; | ||
| 987 | retry_block: | ||
| 988 | if ((BLOCK_STATUS(pbd) & TP_STATUS_USER) == 0) { | ||
| 989 | poll(&pfd, 1, -1); | ||
| 990 | goto retry_block; | ||
| 991 | } | ||
| 992 | |||
| 993 | walk_block(pbd, block_num); | ||
| 994 | flush_block(pbd); | ||
| 995 | block_num = (block_num + 1) % NUM_BLOCKS; | ||
| 996 | } | ||
| 997 | |||
| 998 | len = sizeof(stats); | ||
| 999 | err = getsockopt(fd, SOL_PACKET, PACKET_STATISTICS, &stats, &len); | ||
| 1000 | if (err < 0) { | ||
| 1001 | perror("getsockopt"); | ||
| 1002 | exit(1); | ||
| 1003 | } | ||
| 1004 | |||
| 1005 | fflush(stdout); | ||
| 1006 | printf("\nReceived %u packets, %lu bytes, %u dropped, freeze_q_cnt: %u\n", | ||
| 1007 | stats.tp_packets, bytes_total, stats.tp_drops, | ||
| 1008 | stats.tp_freeze_q_cnt); | ||
| 1009 | |||
| 1010 | teardown_socket(&ring, fd); | ||
| 1011 | return 0; | ||
| 1012 | } | ||
| 1013 | |||
| 687 | ------------------------------------------------------------------------------- | 1014 | ------------------------------------------------------------------------------- |
| 688 | + PACKET_TIMESTAMP | 1015 | + PACKET_TIMESTAMP |
| 689 | ------------------------------------------------------------------------------- | 1016 | ------------------------------------------------------------------------------- |
| 690 | 1017 | ||
| 691 | The PACKET_TIMESTAMP setting determines the source of the timestamp in | 1018 | The PACKET_TIMESTAMP setting determines the source of the timestamp in |
| 692 | the packet meta information. If your NIC is capable of timestamping | 1019 | the packet meta information for mmap(2)ed RX_RING and TX_RINGs. If your |
| 693 | packets in hardware, you can request those hardware timestamps to used. | 1020 | NIC is capable of timestamping packets in hardware, you can request those |
| 694 | Note: you may need to enable the generation of hardware timestamps with | 1021 | hardware timestamps to be used. Note: you may need to enable the generation |
| 695 | SIOCSHWTSTAMP. | 1022 | of hardware timestamps with SIOCSHWTSTAMP (see related information from |
| 1023 | Documentation/networking/timestamping.txt). | ||
| 696 | 1024 | ||
| 697 | PACKET_TIMESTAMP accepts the same integer bit field as | 1025 | PACKET_TIMESTAMP accepts the same integer bit field as |
| 698 | SO_TIMESTAMPING. However, only the SOF_TIMESTAMPING_SYS_HARDWARE | 1026 | SO_TIMESTAMPING. However, only the SOF_TIMESTAMPING_SYS_HARDWARE |
| @@ -704,8 +1032,36 @@ SOF_TIMESTAMPING_RAW_HARDWARE if both bits are set. · 5 unmodified lines | |||
| 704 | req |= SOF_TIMESTAMPING_SYS_HARDWARE; | 1032 | req |= SOF_TIMESTAMPING_SYS_HARDWARE; |
| 705 | setsockopt(fd, SOL_PACKET, PACKET_TIMESTAMP, (void *) &req, sizeof(req)) | 1033 | setsockopt(fd, SOL_PACKET, PACKET_TIMESTAMP, (void *) &req, sizeof(req)) |
| 706 | 1034 | ||
| 707 | If PACKET_TIMESTAMP is not set, a software timestamp generated inside | 1035 | For the mmap(2)ed ring buffers, such timestamps are stored in the |
| 708 | the networking stack is used (the behavior before this setting was added). | 1036 | tpacket{,2,3}_hdr structure's tp_sec and tp_{n,u}sec members. To determine |
| 1037 | what kind of timestamp has been reported, the tp_status field is binary |'ed | ||
| 1038 | with the following possible bits ... | ||
| 1039 | |||
| 1040 | TP_STATUS_TS_SYS_HARDWARE | ||
| 1041 | TP_STATUS_TS_RAW_HARDWARE | ||
| 1042 | TP_STATUS_TS_SOFTWARE | ||
| 1043 | |||
| 1044 | ... that are equivalent to its SOF_TIMESTAMPING_* counterparts. For the | ||
| 1045 | RX_RING, if none of those 3 are set (i.e. PACKET_TIMESTAMP is not set), | ||
| 1046 | then this means that a software fallback was invoked *within* PF_PACKET's | ||
| 1047 | processing code (less precise). | ||
| 1048 | |||
| 1049 | Getting timestamps for the TX_RING works as follows: i) fill the ring frames, | ||
| 1050 | ii) call sendto() e.g. in blocking mode, iii) wait for status of relevant | ||
| 1051 | frames to be updated resp. the frame handed over to the application, iv) walk | ||
| 1052 | through the frames to pick up the individual hw/sw timestamps. | ||
| 1053 | |||
| 1054 | Only (!) if transmit timestamping is enabled, then these bits are combined | ||
| 1055 | with binary | with TP_STATUS_AVAILABLE, so you must check for that in your | ||
| 1056 | application (e.g. !(tp_status & (TP_STATUS_SEND_REQUEST | TP_STATUS_SENDING)) | ||
| 1057 | in a first step to see if the frame belongs to the application, and then | ||
| 1058 | one can extract the type of timestamp in a second step from tp_status)! | ||
| 1059 | |||
| 1060 | If you don't care about them, thus having it disabled, checking for | ||
| 1061 | TP_STATUS_AVAILABLE resp. TP_STATUS_WRONG_FORMAT is sufficient. If in the | ||
| 1062 | TX_RING part only TP_STATUS_AVAILABLE is set, then the tp_sec and tp_{n,u}sec | ||
| 1063 | members do not contain a valid value. For TX_RINGs, by default no timestamp | ||
| 1064 | is generated! | ||
| 709 | 1065 | ||
| 710 | See include/linux/net_tstamp.h and Documentation/networking/timestamping | 1066 | See include/linux/net_tstamp.h and Documentation/networking/timestamping |
| 711 | for more information on hardware timestamps. | 1067 | for more information on hardware timestamps. |
| @@ -1,6 +1,6 @@ | |||
| 1 | STMicroelectronics 10/100/1000 Synopsys Ethernet driver | 1 | STMicroelectronics 10/100/1000 Synopsys Ethernet driver |
| 2 | 2 | ||
| 3 | Copyright (C) 2007-2010 STMicroelectronics Ltd | 3 | Copyright (C) 2007-2013 STMicroelectronics Ltd |
| 4 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | 4 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
| 5 | 5 | ||
| 6 | This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers | 6 | This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers |
| @@ -10,7 +10,7 @@ Currently this network device driver is for all STM embedded MAC/GMAC · 3 unmodified lines | |||
| 10 | (i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000 | 10 | (i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000 |
| 11 | FF1152AMT0221 D1215994A VIRTEX FPGA board. | 11 | FF1152AMT0221 D1215994A VIRTEX FPGA board. |
| 12 | 12 | ||
| 13 | DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether | 13 | DWC Ether MAC 10/100/1000 Universal version 3.70a (and older) and DWC Ether |
| 14 | MAC 10/100 Universal version 4.0 have been used for developing this driver. | 14 | MAC 10/100 Universal version 4.0 have been used for developing this driver. |
| 15 | 15 | ||
| 16 | This driver supports both the platform bus and PCI. | 16 | This driver supports both the platform bus and PCI. |
| @@ -32,6 +32,8 @@ The kernel configuration option is STMMAC_ETH: · 15 unmodified lines | |||
| 32 | watchdog: transmit timeout (in milliseconds); | 32 | watchdog: transmit timeout (in milliseconds); |
| 33 | flow_ctrl: Flow control ability [on/off]; | 33 | flow_ctrl: Flow control ability [on/off]; |
| 34 | pause: Flow Control Pause Time; | 34 | pause: Flow Control Pause Time; |
| 35 | eee_timer: tx EEE timer; | ||
| 36 | chain_mode: select chain mode instead of ring. | ||
| 35 | 37 | ||
| 36 | 3) Command line options | 38 | 3) Command line options |
| 37 | Driver parameters can be also passed in command line by using: | 39 | Driver parameters can be also passed in command line by using: |
| @@ -164,12 +166,12 @@ Where: · 126 unmodified lines | |||
| 164 | o bus_setup: perform HW setup of the bus. For example, on some ST platforms | 166 | o bus_setup: perform HW setup of the bus. For example, on some ST platforms |
| 165 | this field is used to configure the AMBA bridge to generate more | 167 | this field is used to configure the AMBA bridge to generate more |
| 166 | efficient STBus traffic. | 168 | efficient STBus traffic. |
| 167 | o init/exit: callbacks used for calling a custom initialisation; | 169 | o init/exit: callbacks used for calling a custom initialization; |
| 168 | this is sometime necessary on some platforms (e.g. ST boxes) | 170 | this is sometime necessary on some platforms (e.g. ST boxes) |
| 169 | where the HW needs to have set some PIO lines or system cfg | 171 | where the HW needs to have set some PIO lines or system cfg |
| 170 | registers. | 172 | registers. |
| 171 | o custom_cfg/custom_data: this is a custom configuration that can be passed | 173 | o custom_cfg/custom_data: this is a custom configuration that can be passed |
| 172 | while initialising the resources. | 174 | while initializing the resources. |
| 173 | o bsp_priv: another private poiter. | 175 | o bsp_priv: another private poiter. |
| 174 | 176 | ||
| 175 | For MDIO bus The we have: | 177 | For MDIO bus The we have: |
| @@ -273,6 +275,8 @@ reset procedure etc). · 97 unmodified lines | |||
| 273 | o norm_desc.c: functions for handling normal descriptors; | 275 | o norm_desc.c: functions for handling normal descriptors; |
| 274 | o chain_mode.c/ring_mode.c:: functions to manage RING/CHAINED modes; | 276 | o chain_mode.c/ring_mode.c:: functions to manage RING/CHAINED modes; |
| 275 | o mmc_core.c/mmc.h: Management MAC Counters; | 277 | o mmc_core.c/mmc.h: Management MAC Counters; |
| 278 | o stmmac_hwtstamp.c: HW timestamp support for PTP | ||
| 279 | o stmmac_ptp.c: PTP 1588 clock | ||
| 276 | 280 | ||
| 277 | 5) Debug Information | 281 | 5) Debug Information |
| 278 | 282 | ||
| @@ -326,6 +330,35 @@ To enter in Tx LPI mode the driver needs to have a software timer · 47 unmodified lines | |||
| 326 | that enable and disable the LPI mode when there is nothing to be | 330 | that enable and disable the LPI mode when there is nothing to be |
| 327 | transmitted. | 331 | transmitted. |
| 328 | 332 | ||
| 329 | 7) TODO: | 333 | 7) Extended descriptors |
| 334 | The extended descriptors give us information about the receive Ethernet payload | ||
| 335 | when it is carrying PTP packets or TCP/UDP/ICMP over IP. | ||
| 336 | These are not available on GMAC Synopsys chips older than the 3.50. | ||
| 337 | At probe time the driver will decide if these can be actually used. | ||
| 338 | This support also is mandatory for PTPv2 because the extra descriptors 6 and 7 | ||
| 339 | are used for saving the hardware timestamps. | ||
| 340 | |||
| 341 | 8) Precision Time Protocol (PTP) | ||
| 342 | The driver supports the IEEE 1588-2002, Precision Time Protocol (PTP), | ||
| 343 | which enables precise synchronization of clocks in measurement and | ||
| 344 | control systems implemented with technologies such as network | ||
| 345 | communication. | ||
| 346 | |||
| 347 | In addition to the basic timestamp features mentioned in IEEE 1588-2002 | ||
| 348 | Timestamps, new GMAC cores support the advanced timestamp features. | ||
| 349 | IEEE 1588-2008 that can be enabled when configure the Kernel. | ||
| 350 | |||
| 351 | 9) SGMII/RGMII supports | ||
| 352 | New GMAC devices provide own way to manage RGMII/SGMII. | ||
| 353 | This information is available at run-time by looking at the | ||
| 354 | HW capability register. This means that the stmmac can manage | ||
| 355 | auto-negotiation and link status w/o using the PHYLIB stuff | ||
| 356 | In fact, the HW provides a subset of extended registers to | ||
| 357 | restart the ANE, verify Full/Half duplex mode and Speed. | ||
| 358 | Also thanks to these registers it is possible to look at the | ||
| 359 | Auto-negotiated Link Parter Ability. | ||
| 360 | |||
| 361 | 10) TODO: | ||
| 330 | o XGMAC is not supported. | 362 | o XGMAC is not supported. |
| 331 | o Add the PTP - precision time protocol | 363 | o Complete the TBI & RTBI support. |
| 364 | o extened VLAN support for 3.70a SYNP GMAC. | ||
| @@ -1767,7 +1767,7 @@ F: arch/arm/configs/bcm2835_defconfig · 1766 unmodified lines | |||
| 1767 | F: drivers/*/*bcm2835* | 1767 | F: drivers/*/*bcm2835* |
| 1768 | 1768 | ||
| 1769 | BROADCOM TG3 GIGABIT ETHERNET DRIVER | 1769 | BROADCOM TG3 GIGABIT ETHERNET DRIVER |
| 1770 | M: Matt Carlson <mcarlson@broadcom.com> | 1770 | M: Nithin Nayak Sujir <nsujir@broadcom.com> |
| 1771 | M: Michael Chan <mchan@broadcom.com> | 1771 | M: Michael Chan <mchan@broadcom.com> |
| 1772 | L: netdev@vger.kernel.org | 1772 | L: netdev@vger.kernel.org |
| 1773 | S: Supported | 1773 | S: Supported |
| @@ -1889,7 +1889,7 @@ F: Documentation/video4linux/cafe_ccic · 115 unmodified lines | |||
| 1889 | F: drivers/media/platform/marvell-ccic/ | 1889 | F: drivers/media/platform/marvell-ccic/ |
| 1890 | 1890 | ||
| 1891 | CAIF NETWORK LAYER | 1891 | CAIF NETWORK LAYER |
| 1892 | M: Sjur Braendeland <sjur.brandeland@stericsson.com> | 1892 | M: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> |
| 1893 | L: netdev@vger.kernel.org | 1893 | L: netdev@vger.kernel.org |
| 1894 | S: Supported | 1894 | S: Supported |
| 1895 | F: Documentation/networking/caif/ | 1895 | F: Documentation/networking/caif/ |
| @@ -6396,6 +6396,7 @@ F: drivers/acpi/apei/erst.c · 4500 unmodified lines | |||
| 6396 | 6396 | ||
| 6397 | PTP HARDWARE CLOCK SUPPORT | 6397 | PTP HARDWARE CLOCK SUPPORT |
| 6398 | M: Richard Cochran <richardcochran@gmail.com> | 6398 | M: Richard Cochran <richardcochran@gmail.com> |
| 6399 | L: netdev@vger.kernel.org | ||
| 6399 | S: Maintained | 6400 | S: Maintained |
| 6400 | W: http://linuxptp.sourceforge.net/ | 6401 | W: http://linuxptp.sourceforge.net/ |
| 6401 | F: Documentation/ABI/testing/sysfs-ptp | 6402 | F: Documentation/ABI/testing/sysfs-ptp |
| @@ -6527,6 +6528,7 @@ S: Supported · 125 unmodified lines | |||
| 6527 | F: drivers/net/ethernet/qlogic/qlcnic/ | 6528 | F: drivers/net/ethernet/qlogic/qlcnic/ |
| 6528 | 6529 | ||
| 6529 | QLOGIC QLGE 10Gb ETHERNET DRIVER | 6530 | QLOGIC QLGE 10Gb ETHERNET DRIVER |
| 6531 | M: Shahed Shaikh <shahed.shaikh@qlogic.com> | ||
| 6530 | M: Jitendra Kalsaria <jitendra.kalsaria@qlogic.com> | 6532 | M: Jitendra Kalsaria <jitendra.kalsaria@qlogic.com> |
| 6531 | M: Ron Mercer <ron.mercer@qlogic.com> | 6533 | M: Ron Mercer <ron.mercer@qlogic.com> |
| 6532 | M: linux-driver@qlogic.com | 6534 | M: linux-driver@qlogic.com |
| @@ -8627,7 +8629,7 @@ F: drivers/usb/gadget/*uvc*.c · 2094 unmodified lines | |||
| 8627 | F: drivers/usb/gadget/webcam.c | 8629 | F: drivers/usb/gadget/webcam.c |
| 8628 | 8630 | ||
| 8629 | USB WIRELESS RNDIS DRIVER (rndis_wlan) | 8631 | USB WIRELESS RNDIS DRIVER (rndis_wlan) |
| 8630 | M: Jussi Kivilinna <jussi.kivilinna@mbnet.fi> | 8632 | M: Jussi Kivilinna <jussi.kivilinna@iki.fi> |
| 8631 | L: linux-wireless@vger.kernel.org | 8633 | L: linux-wireless@vger.kernel.org |
| 8632 | S: Maintained | 8634 | S: Maintained |
| 8633 | F: drivers/net/wireless/rndis_wlan.c | 8635 | F: drivers/net/wireless/rndis_wlan.c |
| @@ -79,4 +79,6 @@ · 78 unmodified lines | |||
| 79 | 79 | ||
| 80 | #define SO_LOCK_FILTER 44 | 80 | #define SO_LOCK_FILTER 44 |
| 81 | 81 | ||
| 82 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 83 | |||
| 82 | #endif /* _UAPI_ASM_SOCKET_H */ | 84 | #endif /* _UAPI_ASM_SOCKET_H */ |
| @@ -349,7 +349,7 @@ · 348 unmodified lines | |||
| 349 | rx_descs = <64>; | 349 | rx_descs = <64>; |
| 350 | mac_control = <0x20>; | 350 | mac_control = <0x20>; |
| 351 | slaves = <2>; | 351 | slaves = <2>; |
| 352 | cpts_active_slave = <0>; | 352 | active_slave = <0>; |
| 353 | cpts_clock_mult = <0x80000000>; | 353 | cpts_clock_mult = <0x80000000>; |
| 354 | cpts_clock_shift = <29>; | 354 | cpts_clock_shift = <29>; |
| 355 | reg = <0x4a100000 0x800 | 355 | reg = <0x4a100000 0x800 |
| @@ -918,9 +918,8 @@ void bpf_jit_compile(struct sk_filter *fp) · 917 unmodified lines | |||
| 918 | #endif | 918 | #endif |
| 919 | 919 | ||
| 920 | if (bpf_jit_enable > 1) | 920 | if (bpf_jit_enable > 1) |
| 921 | print_hex_dump(KERN_INFO, "BPF JIT code: ", | 921 | /* there are 2 passes here */ |
| 922 | DUMP_PREFIX_ADDRESS, 16, 4, ctx.target, | 922 | bpf_jit_dump(fp->len, alloc_size, 2, ctx.target); |
| 923 | alloc_size, false); | ||
| 924 | 923 | ||
| 925 | fp->bpf_func = (void *)ctx.target; | 924 | fp->bpf_func = (void *)ctx.target; |
| 926 | out: | 925 | out: |
| @@ -238,6 +238,7 @@ static __init void ge_complete( · 237 unmodified lines | |||
| 238 | struct mv643xx_eth_shared_platform_data *orion_ge_shared_data, | 238 | struct mv643xx_eth_shared_platform_data *orion_ge_shared_data, |
| 239 | struct resource *orion_ge_resource, unsigned long irq, | 239 | struct resource *orion_ge_resource, unsigned long irq, |
| 240 | struct platform_device *orion_ge_shared, | 240 | struct platform_device *orion_ge_shared, |
| 241 | struct platform_device *orion_ge_mvmdio, | ||
| 241 | struct mv643xx_eth_platform_data *eth_data, | 242 | struct mv643xx_eth_platform_data *eth_data, |
| 242 | struct platform_device *orion_ge) | 243 | struct platform_device *orion_ge) |
| 243 | { | 244 | { |
| @@ -247,6 +248,8 @@ static __init void ge_complete( · 3 unmodified lines | |||
| 247 | orion_ge->dev.platform_data = eth_data; | 248 | orion_ge->dev.platform_data = eth_data; |
| 248 | 249 | ||
| 249 | platform_device_register(orion_ge_shared); | 250 | platform_device_register(orion_ge_shared); |
| 251 | if (orion_ge_mvmdio) | ||
| 252 | platform_device_register(orion_ge_mvmdio); | ||
| 250 | platform_device_register(orion_ge); | 253 | platform_device_register(orion_ge); |
| 251 | } | 254 | } |
| 252 | 255 | ||
| @@ -258,8 +261,6 @@ struct mv643xx_eth_shared_platform_data orion_ge00_shared_data; · 5 unmodified lines | |||
| 258 | static struct resource orion_ge00_shared_resources[] = { | 261 | static struct resource orion_ge00_shared_resources[] = { |
| 259 | { | 262 | { |
| 260 | .name = "ge00 base", | 263 | .name = "ge00 base", |
| 261 | }, { | ||
| 262 | .name = "ge00 err irq", | ||
| 263 | }, | 264 | }, |
| 264 | }; | 265 | }; |
| 265 | 266 | ||
| @@ -271,6 +272,19 @@ static struct platform_device orion_ge00_shared = { · 5 unmodified lines | |||
| 271 | }, | 272 | }, |
| 272 | }; | 273 | }; |
| 273 | 274 | ||
| 275 | static struct resource orion_ge_mvmdio_resources[] = { | ||
| 276 | { | ||
| 277 | .name = "ge00 mvmdio base", | ||
| 278 | }, { | ||
| 279 | .name = "ge00 mvmdio err irq", | ||
| 280 | }, | ||
| 281 | }; | ||
| 282 | |||
| 283 | static struct platform_device orion_ge_mvmdio = { | ||
| 284 | .name = "orion-mdio", | ||
| 285 | .id = -1, | ||
| 286 | }; | ||
| 287 | |||
| 274 | static struct resource orion_ge00_resources[] = { | 288 | static struct resource orion_ge00_resources[] = { |
| 275 | { | 289 | { |
| 276 | .name = "ge00 irq", | 290 | .name = "ge00 irq", |
| @@ -295,26 +309,25 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, · 18 unmodified lines | |||
| 295 | unsigned int tx_csum_limit) | 309 | unsigned int tx_csum_limit) |
| 296 | { | 310 | { |
| 297 | fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, | 311 | fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, |
| 298 | mapbase + 0x2000, SZ_16K - 1, irq_err); | 312 | mapbase + 0x2000, SZ_16K - 1, NO_IRQ); |
| 313 | fill_resources(&orion_ge_mvmdio, orion_ge_mvmdio_resources, | ||
| 314 | mapbase + 0x2004, 0x84 - 1, irq_err); | ||
| 299 | orion_ge00_shared_data.tx_csum_limit = tx_csum_limit; | 315 | orion_ge00_shared_data.tx_csum_limit = tx_csum_limit; |
| 300 | ge_complete(&orion_ge00_shared_data, | 316 | ge_complete(&orion_ge00_shared_data, |
| 301 | orion_ge00_resources, irq, &orion_ge00_shared, | 317 | orion_ge00_resources, irq, &orion_ge00_shared, |
| 318 | &orion_ge_mvmdio, | ||
| 302 | eth_data, &orion_ge00); | 319 | eth_data, &orion_ge00); |
| 303 | } | 320 | } |
| 304 | 321 | ||
| 305 | /***************************************************************************** | 322 | /***************************************************************************** |
| 306 | * GE01 | 323 | * GE01 |
| 307 | ****************************************************************************/ | 324 | ****************************************************************************/ |
| 308 | struct mv643xx_eth_shared_platform_data orion_ge01_shared_data = { | 325 | struct mv643xx_eth_shared_platform_data orion_ge01_shared_data; |
| 309 | .shared_smi = &orion_ge00_shared, | ||
| 310 | }; | ||
| 311 | 326 | ||
| 312 | static struct resource orion_ge01_shared_resources[] = { | 327 | static struct resource orion_ge01_shared_resources[] = { |
| 313 | { | 328 | { |
| 314 | .name = "ge01 base", | 329 | .name = "ge01 base", |
| 315 | }, { | 330 | } |
| 316 | .name = "ge01 err irq", | ||
| 317 | }, | ||
| 318 | }; | 331 | }; |
| 319 | 332 | ||
| 320 | static struct platform_device orion_ge01_shared = { | 333 | static struct platform_device orion_ge01_shared = { |
| @@ -349,26 +362,23 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, · 28 unmodified lines | |||
| 349 | unsigned int tx_csum_limit) | 362 | unsigned int tx_csum_limit) |
| 350 | { | 363 | { |
| 351 | fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, | 364 | fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, |
| 352 | mapbase + 0x2000, SZ_16K - 1, irq_err); | 365 | mapbase + 0x2000, SZ_16K - 1, NO_IRQ); |
| 353 | orion_ge01_shared_data.tx_csum_limit = tx_csum_limit; | 366 | orion_ge01_shared_data.tx_csum_limit = tx_csum_limit; |
| 354 | ge_complete(&orion_ge01_shared_data, | 367 | ge_complete(&orion_ge01_shared_data, |
| 355 | orion_ge01_resources, irq, &orion_ge01_shared, | 368 | orion_ge01_resources, irq, &orion_ge01_shared, |
| 369 | NULL, | ||
| 356 | eth_data, &orion_ge01); | 370 | eth_data, &orion_ge01); |
| 357 | } | 371 | } |
| 358 | 372 | ||
| 359 | /***************************************************************************** | 373 | /***************************************************************************** |
| 360 | * GE10 | 374 | * GE10 |
| 361 | ****************************************************************************/ | 375 | ****************************************************************************/ |
| 362 | struct mv643xx_eth_shared_platform_data orion_ge10_shared_data = { | 376 | struct mv643xx_eth_shared_platform_data orion_ge10_shared_data; |
| 363 | .shared_smi = &orion_ge00_shared, | ||
| 364 | }; | ||
| 365 | 377 | ||
| 366 | static struct resource orion_ge10_shared_resources[] = { | 378 | static struct resource orion_ge10_shared_resources[] = { |
| 367 | { | 379 | { |
| 368 | .name = "ge10 base", | 380 | .name = "ge10 base", |
| 369 | }, { | 381 | } |
| 370 | .name = "ge10 err irq", | ||
| 371 | }, | ||
| 372 | }; | 382 | }; |
| 373 | 383 | ||
| 374 | static struct platform_device orion_ge10_shared = { | 384 | static struct platform_device orion_ge10_shared = { |
| @@ -402,24 +412,21 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, · 27 unmodified lines | |||
| 402 | unsigned long irq_err) | 412 | unsigned long irq_err) |
| 403 | { | 413 | { |
| 404 | fill_resources(&orion_ge10_shared, orion_ge10_shared_resources, | 414 | fill_resources(&orion_ge10_shared, orion_ge10_shared_resources, |
| 405 | mapbase + 0x2000, SZ_16K - 1, irq_err); | 415 | mapbase + 0x2000, SZ_16K - 1, NO_IRQ); |
| 406 | ge_complete(&orion_ge10_shared_data, | 416 | ge_complete(&orion_ge10_shared_data, |
| 407 | orion_ge10_resources, irq, &orion_ge10_shared, | 417 | orion_ge10_resources, irq, &orion_ge10_shared, |
| 418 | NULL, | ||
| 408 | eth_data, &orion_ge10); | 419 | eth_data, &orion_ge10); |
| 409 | } | 420 | } |
| 410 | 421 | ||
| 411 | /***************************************************************************** | 422 | /***************************************************************************** |
| 412 | * GE11 | 423 | * GE11 |
| 413 | ****************************************************************************/ | 424 | ****************************************************************************/ |
| 414 | struct mv643xx_eth_shared_platform_data orion_ge11_shared_data = { | 425 | struct mv643xx_eth_shared_platform_data orion_ge11_shared_data; |
| 415 | .shared_smi = &orion_ge00_shared, | ||
| 416 | }; | ||
| 417 | 426 | ||
| 418 | static struct resource orion_ge11_shared_resources[] = { | 427 | static struct resource orion_ge11_shared_resources[] = { |
| 419 | { | 428 | { |
| 420 | .name = "ge11 base", | 429 | .name = "ge11 base", |
| 421 | }, { | ||
| 422 | .name = "ge11 err irq", | ||
| 423 | }, | 430 | }, |
| 424 | }; | 431 | }; |
| 425 | 432 | ||
| @@ -454,9 +461,10 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, · 28 unmodified lines | |||
| 454 | unsigned long irq_err) | 461 | unsigned long irq_err) |
| 455 | { | 462 | { |
| 456 | fill_resources(&orion_ge11_shared, orion_ge11_shared_resources, | 463 | fill_resources(&orion_ge11_shared, orion_ge11_shared_resources, |
| 457 | mapbase + 0x2000, SZ_16K - 1, irq_err); | 464 | mapbase + 0x2000, SZ_16K - 1, NO_IRQ); |
| 458 | ge_complete(&orion_ge11_shared_data, | 465 | ge_complete(&orion_ge11_shared_data, |
| 459 | orion_ge11_resources, irq, &orion_ge11_shared, | 466 | orion_ge11_resources, irq, &orion_ge11_shared, |
| 467 | NULL, | ||
| 460 | eth_data, &orion_ge11); | 468 | eth_data, &orion_ge11); |
| 461 | } | 469 | } |
| 462 | 470 | ||
| @@ -72,4 +72,6 @@ · 71 unmodified lines | |||
| 72 | 72 | ||
| 73 | #define SO_LOCK_FILTER 44 | 73 | #define SO_LOCK_FILTER 44 |
| 74 | 74 | ||
| 75 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 76 | |||
| 75 | #endif /* __ASM_AVR32_SOCKET_H */ | 77 | #endif /* __ASM_AVR32_SOCKET_H */ |
| @@ -74,6 +74,8 @@ · 73 unmodified lines | |||
| 74 | 74 | ||
| 75 | #define SO_LOCK_FILTER 44 | 75 | #define SO_LOCK_FILTER 44 |
| 76 | 76 | ||
| 77 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 78 | |||
| 77 | #endif /* _ASM_SOCKET_H */ | 79 | #endif /* _ASM_SOCKET_H */ |
| 78 | 80 | ||
| 79 | 81 | ||
| @@ -72,5 +72,7 @@ · 71 unmodified lines | |||
| 72 | 72 | ||
| 73 | #define SO_LOCK_FILTER 44 | 73 | #define SO_LOCK_FILTER 44 |
| 74 | 74 | ||
| 75 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 76 | |||
| 75 | #endif /* _ASM_SOCKET_H */ | 77 | #endif /* _ASM_SOCKET_H */ |
| 76 | 78 | ||
| @@ -72,4 +72,6 @@ · 71 unmodified lines | |||
| 72 | 72 | ||
| 73 | #define SO_LOCK_FILTER 44 | 73 | #define SO_LOCK_FILTER 44 |
| 74 | 74 | ||
| 75 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 76 | |||
| 75 | #endif /* _ASM_SOCKET_H */ | 77 | #endif /* _ASM_SOCKET_H */ |
| @@ -81,4 +81,6 @@ · 80 unmodified lines | |||
| 81 | 81 | ||
| 82 | #define SO_LOCK_FILTER 44 | 82 | #define SO_LOCK_FILTER 44 |
| 83 | 83 | ||
| 84 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 85 | |||
| 84 | #endif /* _ASM_IA64_SOCKET_H */ | 86 | #endif /* _ASM_IA64_SOCKET_H */ |
| @@ -72,4 +72,6 @@ · 71 unmodified lines | |||
| 72 | 72 | ||
| 73 | #define SO_LOCK_FILTER 44 | 73 | #define SO_LOCK_FILTER 44 |
| 74 | 74 | ||
| 75 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 76 | |||
| 75 | #endif /* _ASM_M32R_SOCKET_H */ | 77 | #endif /* _ASM_M32R_SOCKET_H */ |
| @@ -90,4 +90,6 @@ · 89 unmodified lines | |||
| 90 | 90 | ||
| 91 | #define SO_LOCK_FILTER 44 | 91 | #define SO_LOCK_FILTER 44 |
| 92 | 92 | ||
| 93 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 94 | |||
| 93 | #endif /* _UAPI_ASM_SOCKET_H */ | 95 | #endif /* _UAPI_ASM_SOCKET_H */ |
| @@ -72,4 +72,6 @@ · 71 unmodified lines | |||
| 72 | 72 | ||
| 73 | #define SO_LOCK_FILTER 44 | 73 | #define SO_LOCK_FILTER 44 |
| 74 | 74 | ||
| 75 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 76 | |||
| 75 | #endif /* _ASM_SOCKET_H */ | 77 | #endif /* _ASM_SOCKET_H */ |
| @@ -71,6 +71,8 @@ · 70 unmodified lines | |||
| 71 | 71 | ||
| 72 | #define SO_LOCK_FILTER 0x4025 | 72 | #define SO_LOCK_FILTER 0x4025 |
| 73 | 73 | ||
| 74 | #define SO_SELECT_ERR_QUEUE 0x4026 | ||
| 75 | |||
| 74 | /* O_NONBLOCK clashes with the bits used for socket types. Therefore we | 76 | /* O_NONBLOCK clashes with the bits used for socket types. Therefore we |
| 75 | * have to define SOCK_NONBLOCK to a different value here. | 77 | * have to define SOCK_NONBLOCK to a different value here. |
| 76 | */ | 78 | */ |
| @@ -79,4 +79,6 @@ · 78 unmodified lines | |||
| 79 | 79 | ||
| 80 | #define SO_LOCK_FILTER 44 | 80 | #define SO_LOCK_FILTER 44 |
| 81 | 81 | ||
| 82 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 83 | |||
| 82 | #endif /* _ASM_POWERPC_SOCKET_H */ | 84 | #endif /* _ASM_POWERPC_SOCKET_H */ |
| @@ -671,16 +671,12 @@ void bpf_jit_compile(struct sk_filter *fp) · 670 unmodified lines | |||
| 671 | } | 671 | } |
| 672 | 672 | ||
| 673 | if (bpf_jit_enable > 1) | 673 | if (bpf_jit_enable > 1) |
| 674 | pr_info("flen=%d proglen=%u pass=%d image=%p\n", | 674 | /* Note that we output the base address of the code_base |
| 675 | flen, proglen, pass, image); | 675 | * rather than image, since opcodes are in code_base. |
| 676 | */ | ||
| 677 | bpf_jit_dump(flen, proglen, pass, code_base); | ||
| 676 | 678 | ||
| 677 | if (image) { | 679 | if (image) { |
| 678 | if (bpf_jit_enable > 1) | ||
| 679 | print_hex_dump(KERN_ERR, "JIT code: ", | ||
| 680 | DUMP_PREFIX_ADDRESS, | ||
| 681 | 16, 1, code_base, | ||
| 682 | proglen, false); | ||
| 683 | |||
| 684 | bpf_flush_icache(code_base, code_base + (proglen/4)); | 680 | bpf_flush_icache(code_base, code_base + (proglen/4)); |
| 685 | /* Function descriptor nastiness: Address + TOC */ | 681 | /* Function descriptor nastiness: Address + TOC */ |
| 686 | ((u64 *)image)[0] = (u64)code_base; | 682 | ((u64 *)image)[0] = (u64)code_base; |
| @@ -47,6 +47,25 @@ static struct platform_device mv643xx_eth_shared_device = { · 46 unmodified lines | |||
| 47 | .resource = mv643xx_eth_shared_resources, | 47 | .resource = mv643xx_eth_shared_resources, |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | /* | ||
| 51 | * The orion mdio driver only covers shared + 0x4 up to shared + 0x84 - 1 | ||
| 52 | */ | ||
| 53 | static struct resource mv643xx_eth_mvmdio_resources[] = { | ||
| 54 | [0] = { | ||
| 55 | .name = "ethernet mdio base", | ||
| 56 | .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x4, | ||
| 57 | .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x83, | ||
| 58 | .flags = IORESOURCE_MEM, | ||
| 59 | }, | ||
| 60 | }; | ||
| 61 | |||
| 62 | static struct platform_device mv643xx_eth_mvmdio_device = { | ||
| 63 | .name = "orion-mdio", | ||
| 64 | .id = -1, | ||
| 65 | .num_resources = ARRAY_SIZE(mv643xx_eth_mvmdio_resources), | ||
| 66 | .resource = mv643xx_eth_shared_resources, | ||
| 67 | }; | ||
| 68 | |||
| 50 | static struct resource mv643xx_eth_port1_resources[] = { | 69 | static struct resource mv643xx_eth_port1_resources[] = { |
| 51 | [0] = { | 70 | [0] = { |
| 52 | .name = "eth port1 irq", | 71 | .name = "eth port1 irq", |
| @@ -82,6 +101,7 @@ static struct platform_device eth_port1_device = { · 29 unmodified lines | |||
| 82 | 101 | ||
| 83 | static struct platform_device *mv643xx_eth_pd_devs[] __initdata = { | 102 | static struct platform_device *mv643xx_eth_pd_devs[] __initdata = { |
| 84 | &mv643xx_eth_shared_device, | 103 | &mv643xx_eth_shared_device, |
| 104 | &mv643xx_eth_mvmdio_device, | ||
| 85 | ð_port1_device, | 105 | ð_port1_device, |
| 86 | }; | 106 | }; |
| 87 | 107 | ||
| @@ -214,15 +214,27 @@ static struct platform_device * __init mv64x60_eth_register_shared_pdev( · 213 unmodified lines | |||
| 214 | struct device_node *np, int id) | 214 | struct device_node *np, int id) |
| 215 | { | 215 | { |
| 216 | struct platform_device *pdev; | 216 | struct platform_device *pdev; |
| 217 | struct resource r[1]; | 217 | struct resource r[2]; |
| 218 | int err; | 218 | int err; |
| 219 | 219 | ||
| 220 | err = of_address_to_resource(np, 0, &r[0]); | 220 | err = of_address_to_resource(np, 0, &r[0]); |
| 221 | if (err) | 221 | if (err) |
| 222 | return ERR_PTR(err); | 222 | return ERR_PTR(err); |
| 223 | 223 | ||
| 224 | /* register an orion mdio bus driver */ | ||
| 225 | r[1].start = r[0].start + 0x4; | ||
| 226 | r[1].end = r[0].start + 0x84 - 1; | ||
| 227 | r[1].flags = IORESOURCE_MEM; | ||
| 228 | |||
| 229 | if (id == 0) { | ||
| 230 | pdev = platform_device_register_simple("orion-mdio", -1, &r[1], 1); | ||
| 231 | if (!pdev) | ||
| 232 | return pdev; | ||
| 233 | } | ||
| 234 | |||
| 224 | pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, id, | 235 | pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, id, |
| 225 | r, 1); | 236 | &r[0], 1); |
| 237 | |||
| 226 | return pdev; | 238 | return pdev; |
| 227 | } | 239 | } |
| 228 | 240 | ||
| @@ -78,4 +78,6 @@ · 77 unmodified lines | |||
| 78 | 78 | ||
| 79 | #define SO_LOCK_FILTER 44 | 79 | #define SO_LOCK_FILTER 44 |
| 80 | 80 | ||
| 81 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 82 | |||
| 81 | #endif /* _ASM_SOCKET_H */ | 83 | #endif /* _ASM_SOCKET_H */ |
| @@ -68,6 +68,8 @@ · 67 unmodified lines | |||
| 68 | 68 | ||
| 69 | #define SO_LOCK_FILTER 0x0028 | 69 | #define SO_LOCK_FILTER 0x0028 |
| 70 | 70 | ||
| 71 | #define SO_SELECT_ERR_QUEUE 0x0029 | ||
| 72 | |||
| 71 | /* Security levels - as per NRL IPv6 - don't actually do anything */ | 73 | /* Security levels - as per NRL IPv6 - don't actually do anything */ |
| 72 | #define SO_SECURITY_AUTHENTICATION 0x5001 | 74 | #define SO_SECURITY_AUTHENTICATION 0x5001 |
| 73 | #define SO_SECURITY_ENCRYPTION_TRANSPORT 0x5002 | 75 | #define SO_SECURITY_ENCRYPTION_TRANSPORT 0x5002 |
| @@ -795,13 +795,9 @@ cond_branch: f_offset = addrs[i + filter[i].jf]; · 794 unmodified lines | |||
| 795 | } | 795 | } |
| 796 | 796 | ||
| 797 | if (bpf_jit_enable > 1) | 797 | if (bpf_jit_enable > 1) |
| 798 | pr_err("flen=%d proglen=%u pass=%d image=%p\n", | 798 | bpf_jit_dump(flen, proglen, pass, image); |
| 799 | flen, proglen, pass, image); | ||
| 800 | 799 | ||
| 801 | if (image) { | 800 | if (image) { |
| 802 | if (bpf_jit_enable > 1) | ||
| 803 | print_hex_dump(KERN_ERR, "JIT code: ", DUMP_PREFIX_ADDRESS, | ||
| 804 | 16, 1, image, proglen, false); | ||
| 805 | bpf_flush_icache(image, image + proglen); | 801 | bpf_flush_icache(image, image + proglen); |
| 806 | fp->bpf_func = (void *)image; | 802 | fp->bpf_func = (void *)image; |
| 807 | } | 803 | } |
| @@ -725,17 +725,12 @@ cond_branch: f_offset = addrs[i + filter[i].jf] - addrs[i]; · 724 unmodified lines | |||
| 725 | } | 725 | } |
| 726 | oldproglen = proglen; | 726 | oldproglen = proglen; |
| 727 | } | 727 | } |
| 728 | |||
| 728 | if (bpf_jit_enable > 1) | 729 | if (bpf_jit_enable > 1) |
| 729 | pr_err("flen=%d proglen=%u pass=%d image=%p\n", | 730 | bpf_jit_dump(flen, proglen, pass, image); |
| 730 | flen, proglen, pass, image); | ||
| 731 | 731 | ||
| 732 | if (image) { | 732 | if (image) { |
| 733 | if (bpf_jit_enable > 1) | ||
| 734 | print_hex_dump(KERN_ERR, "JIT code: ", DUMP_PREFIX_ADDRESS, | ||
| 735 | 16, 1, image, proglen, false); | ||
| 736 | |||
| 737 | bpf_flush_icache(image, image + proglen); | 733 | bpf_flush_icache(image, image + proglen); |
| 738 | |||
| 739 | fp->bpf_func = (void *)image; | 734 | fp->bpf_func = (void *)image; |
| 740 | } | 735 | } |
| 741 | out: | 736 | out: |
| @@ -83,4 +83,6 @@ · 82 unmodified lines | |||
| 83 | 83 | ||
| 84 | #define SO_LOCK_FILTER 44 | 84 | #define SO_LOCK_FILTER 44 |
| 85 | 85 | ||
| 86 | #define SO_SELECT_ERR_QUEUE 45 | ||
| 87 | |||
| 86 | #endif /* _XTENSA_SOCKET_H */ | 88 | #endif /* _XTENSA_SOCKET_H */ |
| @@ -1055,7 +1055,7 @@ static int he_start(struct atm_dev *dev) · 1054 unmodified lines | |||
| 1055 | he_writel(he_dev, 0x0, RESET_CNTL); | 1055 | he_writel(he_dev, 0x0, RESET_CNTL); |
| 1056 | he_writel(he_dev, 0xff, RESET_CNTL); | 1056 | he_writel(he_dev, 0xff, RESET_CNTL); |
| 1057 | 1057 | ||
| 1058 | udelay(16*1000); /* 16 ms */ | 1058 | msleep(16); /* 16 ms */ |
| 1059 | status = he_readl(he_dev, RESET_CNTL); | 1059 | status = he_readl(he_dev, RESET_CNTL); |
| 1060 | if ((status & BOARD_RST_STATUS) == 0) { | 1060 | if ((status & BOARD_RST_STATUS) == 0) { |
| 1061 | hprintk("reset failed\n"); | 1061 | hprintk("reset failed\n"); |
| @@ -104,7 +104,13 @@ void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on) · 103 unmodified lines | |||
| 104 | if (i) | 104 | if (i) |
| 105 | bcma_err(core->bus, "PLL enable timeout\n"); | 105 | bcma_err(core->bus, "PLL enable timeout\n"); |
| 106 | } else { | 106 | } else { |
| 107 | bcma_warn(core->bus, "Disabling PLL not supported yet!\n"); | 107 | /* |
| 108 | * Mask the PLL but don't wait for it to be disabled. PLL may be | ||
| 109 | * shared between cores and will be still up if there is another | ||
| 110 | * core using it. | ||
| 111 | */ | ||
| 112 | bcma_mask32(core, BCMA_CLKCTLST, ~req); | ||
| 113 | bcma_read32(core, BCMA_CLKCTLST); | ||
| 108 | } | 114 | } |
| 109 | } | 115 | } |
| 110 | EXPORT_SYMBOL_GPL(bcma_core_pll_ctl); | 116 | EXPORT_SYMBOL_GPL(bcma_core_pll_ctl); |
| @@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, · 24 unmodified lines | |||
| 25 | return value; | 25 | return value; |
| 26 | } | 26 | } |
| 27 | 27 | ||
| 28 | static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) | 28 | u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) |
| 29 | { | 29 | { |
| 30 | if (cc->capabilities & BCMA_CC_CAP_PMU) | 30 | if (cc->capabilities & BCMA_CC_CAP_PMU) |
| 31 | return bcma_pmu_get_alp_clock(cc); | 31 | return bcma_pmu_get_alp_clock(cc); |
| 32 | 32 | ||
| 33 | return 20000000; | 33 | return 20000000; |
| 34 | } | 34 | } |
| 35 | EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); | ||
| 35 | 36 | ||
| 36 | static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) | 37 | static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) |
| 37 | { | 38 | { |
| @@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) · 175 unmodified lines | |||
| 213 | 214 | ||
| 214 | return res; | 215 | return res; |
| 215 | } | 216 | } |
| 217 | EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); | ||
| 216 | 218 | ||
| 217 | u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) | 219 | u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) |
| 218 | { | 220 | { |
| @@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) · 6 unmodified lines | |||
| 225 | 227 | ||
| 226 | return res; | 228 | return res; |
| 227 | } | 229 | } |
| 230 | EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); | ||
| 228 | 231 | ||
| 229 | /* | 232 | /* |
| 230 | * If the bit is set to 0, chipcommon controlls this GPIO, | 233 | * If the bit is set to 0, chipcommon controlls this GPIO, |
| @@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc) · 173 unmodified lines | |||
| 174 | struct bcma_bus *bus = cc->core->bus; | 174 | struct bcma_bus *bus = cc->core->bus; |
| 175 | 175 | ||
| 176 | switch (bus->chipinfo.id) { | 176 | switch (bus->chipinfo.id) { |
| 177 | case BCMA_CHIP_ID_BCM4313: | ||
| 178 | case BCMA_CHIP_ID_BCM43224: | ||
| 179 | case BCMA_CHIP_ID_BCM43225: | ||
| 180 | case BCMA_CHIP_ID_BCM43227: | ||
| 181 | case BCMA_CHIP_ID_BCM43228: | ||
| 182 | case BCMA_CHIP_ID_BCM4331: | ||
| 183 | case BCMA_CHIP_ID_BCM43421: | ||
| 184 | case BCMA_CHIP_ID_BCM43428: | ||
| 185 | case BCMA_CHIP_ID_BCM43431: | ||
| 177 | case BCMA_CHIP_ID_BCM4716: | 186 | case BCMA_CHIP_ID_BCM4716: |
| 178 | case BCMA_CHIP_ID_BCM4748: | ||
| 179 | case BCMA_CHIP_ID_BCM47162: | 187 | case BCMA_CHIP_ID_BCM47162: |
| 180 | case BCMA_CHIP_ID_BCM4313: | 188 | case BCMA_CHIP_ID_BCM4748: |
| 181 | case BCMA_CHIP_ID_BCM5357: | ||
| 182 | case BCMA_CHIP_ID_BCM4749: | 189 | case BCMA_CHIP_ID_BCM4749: |
| 190 | case BCMA_CHIP_ID_BCM5357: | ||
| 183 | case BCMA_CHIP_ID_BCM53572: | 191 | case BCMA_CHIP_ID_BCM53572: |
| 192 | case BCMA_CHIP_ID_BCM6362: | ||
| 184 | /* always 20Mhz */ | 193 | /* always 20Mhz */ |
| 185 | return 20000 * 1000; | 194 | return 20000 * 1000; |
| 186 | case BCMA_CHIP_ID_BCM5356: | ||
| 187 | case BCMA_CHIP_ID_BCM4706: | 195 | case BCMA_CHIP_ID_BCM4706: |
| 196 | case BCMA_CHIP_ID_BCM5356: | ||
| 188 | /* always 25Mhz */ | 197 | /* always 25Mhz */ |
| 189 | return 25000 * 1000; | 198 | return 25000 * 1000; |
| 199 | case BCMA_CHIP_ID_BCM43460: | ||
| 200 | case BCMA_CHIP_ID_BCM4352: | ||
| 201 | case BCMA_CHIP_ID_BCM4360: | ||
| 202 | if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) | ||
| 203 | return 40000 * 1000; | ||
| 204 | else | ||
| 205 | return 20000 * 1000; | ||
| 190 | default: | 206 | default: |
| 191 | bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", | 207 | bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", |
| 192 | bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); | 208 | bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); |
| @@ -373,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) · 180 unmodified lines | |||
| 373 | tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; | 389 | tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; |
| 374 | bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); | 390 | bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); |
| 375 | 391 | ||
| 376 | tmp = 1 << 10; | 392 | tmp = BCMA_CC_PMU_CTL_PLL_UPD; |
| 377 | break; | 393 | break; |
| 378 | 394 | ||
| 379 | case BCMA_CHIP_ID_BCM4331: | 395 | case BCMA_CHIP_ID_BCM4331: |
| @@ -394,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) · 14 unmodified lines | |||
| 394 | bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, | 410 | bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, |
| 395 | 0x03000a08); | 411 | 0x03000a08); |
| 396 | } | 412 | } |
| 397 | tmp = 1 << 10; | 413 | tmp = BCMA_CC_PMU_CTL_PLL_UPD; |
| 398 | break; | 414 | break; |
| 399 | 415 | ||
| 400 | case BCMA_CHIP_ID_BCM43224: | 416 | case BCMA_CHIP_ID_BCM43224: |
| @@ -427,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) · 26 unmodified lines | |||
| 427 | bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, | 443 | bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, |
| 428 | 0x88888815); | 444 | 0x88888815); |
| 429 | } | 445 | } |
| 430 | tmp = 1 << 10; | 446 | tmp = BCMA_CC_PMU_CTL_PLL_UPD; |
| 431 | break; | 447 | break; |
| 432 | 448 | ||
| 433 | case BCMA_CHIP_ID_BCM4716: | 449 | case BCMA_CHIP_ID_BCM4716: |
| @@ -461,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) · 27 unmodified lines | |||
| 461 | 0x88888815); | 477 | 0x88888815); |
| 462 | } | 478 | } |
| 463 | 479 | ||
| 464 | tmp = 3 << 9; | 480 | tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; |
| 465 | break; | 481 | break; |
| 466 | 482 | ||
| 467 | case BCMA_CHIP_ID_BCM43227: | 483 | case BCMA_CHIP_ID_BCM43227: |
| @@ -497,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) · 29 unmodified lines | |||
| 497 | bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, | 513 | bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, |
| 498 | 0x88888815); | 514 | 0x88888815); |
| 499 | } | 515 | } |
| 500 | tmp = 1 << 10; | 516 | tmp = BCMA_CC_PMU_CTL_PLL_UPD; |
| 501 | break; | 517 | break; |
| 502 | default: | 518 | default: |
| 503 | bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", | 519 | bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", |
| @@ -120,6 +120,11 @@ static int bcma_register_cores(struct bcma_bus *bus) · 119 unmodified lines | |||
| 120 | continue; | 120 | continue; |
| 121 | } | 121 | } |
| 122 | 122 | ||
| 123 | /* Only first GMAC core on BCM4706 is connected and working */ | ||
| 124 | if (core->id.id == BCMA_CORE_4706_MAC_GBIT && | ||
| 125 | core->core_unit > 0) | ||
| 126 | continue; | ||
| 127 | |||
| 123 | core->dev.release = bcma_release_core_dev; | 128 | core->dev.release = bcma_release_core_dev; |
| 124 | core->dev.bus = &bcma_bus_type; | 129 | core->dev.bus = &bcma_bus_type; |
| 125 | dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id); | 130 | dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id); |
| @@ -137,19 +137,19 @@ static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr) · 136 unmodified lines | |||
| 137 | addr); | 137 | addr); |
| 138 | } | 138 | } |
| 139 | 139 | ||
| 140 | static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr) | 140 | static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr) |
| 141 | { | 141 | { |
| 142 | u32 ent = readl(*eromptr); | 142 | u32 ent = readl(*eromptr); |
| 143 | (*eromptr)++; | 143 | (*eromptr)++; |
| 144 | return ent; | 144 | return ent; |
| 145 | } | 145 | } |
| 146 | 146 | ||
| 147 | static void bcma_erom_push_ent(u32 **eromptr) | 147 | static void bcma_erom_push_ent(u32 __iomem **eromptr) |
| 148 | { | 148 | { |
| 149 | (*eromptr)--; | 149 | (*eromptr)--; |
| 150 | } | 150 | } |
| 151 | 151 | ||
| 152 | static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr) | 152 | static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr) |
| 153 | { | 153 | { |
| 154 | u32 ent = bcma_erom_get_ent(bus, eromptr); | 154 | u32 ent = bcma_erom_get_ent(bus, eromptr); |
| 155 | if (!(ent & SCAN_ER_VALID)) | 155 | if (!(ent & SCAN_ER_VALID)) |
| @@ -159,14 +159,14 @@ static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr) · 3 unmodified lines | |||
| 159 | return ent; | 159 | return ent; |
| 160 | } | 160 | } |
| 161 | 161 | ||
| 162 | static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr) | 162 | static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr) |
| 163 | { | 163 | { |
| 164 | u32 ent = bcma_erom_get_ent(bus, eromptr); | 164 | u32 ent = bcma_erom_get_ent(bus, eromptr); |
| 165 | bcma_erom_push_ent(eromptr); | 165 | bcma_erom_push_ent(eromptr); |
| 166 | return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID)); | 166 | return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID)); |
| 167 | } | 167 | } |
| 168 | 168 | ||
| 169 | static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr) | 169 | static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr) |
| 170 | { | 170 | { |
| 171 | u32 ent = bcma_erom_get_ent(bus, eromptr); | 171 | u32 ent = bcma_erom_get_ent(bus, eromptr); |
| 172 | bcma_erom_push_ent(eromptr); | 172 | bcma_erom_push_ent(eromptr); |
| @@ -175,7 +175,7 @@ static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr) · 2 unmodified lines | |||
| 175 | ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE)); | 175 | ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE)); |
| 176 | } | 176 | } |
| 177 | 177 | ||
| 178 | static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr) | 178 | static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr) |
| 179 | { | 179 | { |
| 180 | u32 ent; | 180 | u32 ent; |
| 181 | while (1) { | 181 | while (1) { |
| @@ -189,7 +189,7 @@ static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr) · 7 unmodified lines | |||
| 189 | bcma_erom_push_ent(eromptr); | 189 | bcma_erom_push_ent(eromptr); |
| 190 | } | 190 | } |
| 191 | 191 | ||
| 192 | static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr) | 192 | static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr) |
| 193 | { | 193 | { |
| 194 | u32 ent = bcma_erom_get_ent(bus, eromptr); | 194 | u32 ent = bcma_erom_get_ent(bus, eromptr); |
| 195 | if (!(ent & SCAN_ER_VALID)) | 195 | if (!(ent & SCAN_ER_VALID)) |
| @@ -199,7 +199,7 @@ static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr) · 3 unmodified lines | |||
| 199 | return ent; | 199 | return ent; |
| 200 | } | 200 | } |
| 201 | 201 | ||
| 202 | static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr, | 202 | static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr, |
| 203 | u32 type, u8 port) | 203 | u32 type, u8 port) |
| 204 | { | 204 | { |
| 205 | u32 addrl, addrh, sizel, sizeh = 0; | 205 | u32 addrl, addrh, sizel, sizeh = 0; |
| @@ -217,6 +217,7 @@ static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom) · 216 unmodified lines | |||
| 217 | } | 217 | } |
| 218 | 218 | ||
| 219 | SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0); | 219 | SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0); |
| 220 | SPEX(board_type, SSB_SPROM1_SPID, ~0, 0); | ||
| 220 | 221 | ||
| 221 | SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0, | 222 | SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0, |
| 222 | SSB_SPROM4_TXPID2G0_SHIFT); | 223 | SSB_SPROM4_TXPID2G0_SHIFT); |
| @@ -90,6 +90,7 @@ static struct usb_device_id ath3k_table[] = { · 89 unmodified lines | |||
| 90 | { USB_DEVICE(0x13d3, 0x3393) }, | 90 | { USB_DEVICE(0x13d3, 0x3393) }, |
| 91 | { USB_DEVICE(0x0489, 0xe04e) }, | 91 | { USB_DEVICE(0x0489, 0xe04e) }, |
| 92 | { USB_DEVICE(0x0489, 0xe056) }, | 92 | { USB_DEVICE(0x0489, 0xe056) }, |
| 93 | { USB_DEVICE(0x0489, 0xe04d) }, | ||
| 93 | 94 | ||
| 94 | /* Atheros AR5BBU12 with sflash firmware */ | 95 | /* Atheros AR5BBU12 with sflash firmware */ |
| 95 | { USB_DEVICE(0x0489, 0xE02C) }, | 96 | { USB_DEVICE(0x0489, 0xE02C) }, |
| @@ -126,6 +127,7 @@ static struct usb_device_id ath3k_blist_tbl[] = { · 30 unmodified lines | |||
| 126 | { USB_DEVICE(0x13d3, 0x3393), .driver_info = BTUSB_ATH3012 }, | 127 | { USB_DEVICE(0x13d3, 0x3393), .driver_info = BTUSB_ATH3012 }, |
| 127 | { USB_DEVICE(0x0489, 0xe04e), .driver_info = BTUSB_ATH3012 }, | 128 | { USB_DEVICE(0x0489, 0xe04e), .driver_info = BTUSB_ATH3012 }, |
| 128 | { USB_DEVICE(0x0489, 0xe056), .driver_info = BTUSB_ATH3012 }, | 129 | { USB_DEVICE(0x0489, 0xe056), .driver_info = BTUSB_ATH3012 }, |
| 130 | { USB_DEVICE(0x0489, 0xe04d), .driver_info = BTUSB_ATH3012 }, | ||
| 129 | 131 | ||
| 130 | /* Atheros AR5BBU22 with sflash firmware */ | 132 | /* Atheros AR5BBU22 with sflash firmware */ |
| 131 | { USB_DEVICE(0x0489, 0xE03C), .driver_info = BTUSB_ATH3012 }, | 133 | { USB_DEVICE(0x0489, 0xE03C), .driver_info = BTUSB_ATH3012 }, |
| @@ -29,20 +29,6 @@ · 28 unmodified lines | |||
| 29 | struct btmrvl_debugfs_data { | 29 | struct btmrvl_debugfs_data { |
| 30 | struct dentry *config_dir; | 30 | struct dentry *config_dir; |
| 31 | struct dentry *status_dir; | 31 | struct dentry *status_dir; |
| 32 | |||
| 33 | /* config */ | ||
| 34 | struct dentry *psmode; | ||
| 35 | struct dentry *pscmd; | ||
| 36 | struct dentry *hsmode; | ||
| 37 | struct dentry *hscmd; | ||
| 38 | struct dentry *gpiogap; | ||
| 39 | struct dentry *hscfgcmd; | ||
| 40 | |||
| 41 | /* status */ | ||
| 42 | struct dentry *curpsmode; | ||
| 43 | struct dentry *hsstate; | ||
| 44 | struct dentry *psstate; | ||
| 45 | struct dentry *txdnldready; | ||
| 46 | }; | 32 | }; |
| 47 | 33 | ||
| 48 | static ssize_t btmrvl_hscfgcmd_write(struct file *file, | 34 | static ssize_t btmrvl_hscfgcmd_write(struct file *file, |
| @@ -91,47 +77,6 @@ static const struct file_operations btmrvl_hscfgcmd_fops = { · 42 unmodified lines | |||
| 91 | .llseek = default_llseek, | 77 | .llseek = default_llseek, |
| 92 | }; | 78 | }; |
| 93 | 79 | ||
| 94 | static ssize_t btmrvl_psmode_write(struct file *file, const char __user *ubuf, | ||
| 95 | size_t count, loff_t *ppos) | ||
| 96 | { | ||
| 97 | struct btmrvl_private *priv = file->private_data; | ||
| 98 | char buf[16]; | ||
| 99 | long result, ret; | ||
| 100 | |||
| 101 | memset(buf, 0, sizeof(buf)); | ||
| 102 | |||
| 103 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) | ||
| 104 | return -EFAULT; | ||
| 105 | |||
| 106 | ret = strict_strtol(buf, 10, &result); | ||
| 107 | if (ret) | ||
| 108 | return ret; | ||
| 109 | |||
| 110 | priv->btmrvl_dev.psmode = result; | ||
| 111 | |||
| 112 | return count; | ||
| 113 | } | ||
| 114 | |||
| 115 | static ssize_t btmrvl_psmode_read(struct file *file, char __user *userbuf, | ||
| 116 | size_t count, loff_t *ppos) | ||
| 117 | { | ||
| 118 | struct btmrvl_private *priv = file->private_data; | ||
| 119 | char buf[16]; | ||
| 120 | int ret; | ||
| 121 | |||
| 122 | ret = snprintf(buf, sizeof(buf) - 1, "%d\n", | ||
| 123 | priv->btmrvl_dev.psmode); | ||
| 124 | |||
| 125 | return simple_read_from_buffer(userbuf, count, ppos, buf, ret); | ||
| 126 | } | ||
| 127 | |||
| 128 | static const struct file_operations btmrvl_psmode_fops = { | ||
| 129 | .read = btmrvl_psmode_read, | ||
| 130 | .write = btmrvl_psmode_write, | ||
| 131 | .open = simple_open, | ||
| 132 | .llseek = default_llseek, | ||
| 133 | }; | ||
| 134 | |||
| 135 | static ssize_t btmrvl_pscmd_write(struct file *file, const char __user *ubuf, | 80 | static ssize_t btmrvl_pscmd_write(struct file *file, const char __user *ubuf, |
| 136 | size_t count, loff_t *ppos) | 81 | size_t count, loff_t *ppos) |
| 137 | { | 82 | { |
| @@ -178,47 +123,6 @@ static const struct file_operations btmrvl_pscmd_fops = { · 40 unmodified lines | |||
| 178 | .llseek = default_llseek, | 123 | .llseek = default_llseek, |
| 179 | }; | 124 | }; |
| 180 | 125 | ||
| 181 | static ssize_t btmrvl_gpiogap_write(struct file *file, const char __user *ubuf, | ||
| 182 | size_t count, loff_t *ppos) | ||
| 183 | { | ||
| 184 | struct btmrvl_private *priv = file->private_data; | ||
| 185 | char buf[16]; | ||
| 186 | long result, ret; | ||
| 187 | |||
| 188 | memset(buf, 0, sizeof(buf)); | ||
| 189 | |||
| 190 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) | ||
| 191 | return -EFAULT; | ||
| 192 | |||
| 193 | ret = strict_strtol(buf, 16, &result); | ||
| 194 | if (ret) | ||
| 195 | return ret; | ||
| 196 | |||
| 197 | priv->btmrvl_dev.gpio_gap = result; | ||
| 198 | |||
| 199 | return count; | ||
| 200 | } | ||
| 201 | |||
| 202 | static ssize_t btmrvl_gpiogap_read(struct file *file, char __user *userbuf, | ||
| 203 | size_t count, loff_t *ppos) | ||
| 204 | { | ||
| 205 | struct btmrvl_private *priv = file->private_data; | ||
| 206 | char buf[16]; | ||
| 207 | int ret; | ||
| 208 | |||
| 209 | ret = snprintf(buf, sizeof(buf) - 1, "0x%x\n", | ||
| 210 | priv->btmrvl_dev.gpio_gap); | ||
| 211 | |||
| 212 | return simple_read_from_buffer(userbuf, count, ppos, buf, ret); | ||
| 213 | } | ||
| 214 | |||
| 215 | static const struct file_operations btmrvl_gpiogap_fops = { | ||
| 216 | .read = btmrvl_gpiogap_read, | ||
| 217 | .write = btmrvl_gpiogap_write, | ||
| 218 | .open = simple_open, | ||
| 219 | .llseek = default_llseek, | ||
| 220 | }; | ||
| 221 | |||
| 222 | static ssize_t btmrvl_hscmd_write(struct file *file, const char __user *ubuf, | 126 | static ssize_t btmrvl_hscmd_write(struct file *file, const char __user *ubuf, |
| 223 | size_t count, loff_t *ppos) | 127 | size_t count, loff_t *ppos) |
| 224 | { | 128 | { |
| @@ -263,119 +167,6 @@ static const struct file_operations btmrvl_hscmd_fops = { · 38 unmodified lines | |||
| 263 | .llseek = default_llseek, | 167 | .llseek = default_llseek, |
| 264 | }; | 168 | }; |
| 265 | 169 | ||
| 266 | static ssize_t btmrvl_hsmode_write(struct file *file, const char __user *ubuf, | ||
| 267 | size_t count, loff_t *ppos) | ||
| 268 | { | ||
| 269 | struct btmrvl_private *priv = file->private_data; | ||
| 270 | char buf[16]; | ||
| 271 | long result, ret; | ||
| 272 | |||
| 273 | memset(buf, 0, sizeof(buf)); | ||
| 274 | |||
| 275 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) | ||
| 276 | return -EFAULT; | ||
| 277 | |||
| 278 | ret = strict_strtol(buf, 10, &result); | ||
| 279 | if (ret) | ||
| 280 | return ret; | ||
| 281 | |||
| 282 | priv->btmrvl_dev.hsmode = result; | ||
| 283 | |||
| 284 | return count; | ||
| 285 | } | ||
| 286 | |||
| 287 | static ssize_t btmrvl_hsmode_read(struct file *file, char __user * userbuf, | ||
| 288 | size_t count, loff_t *ppos) | ||
| 289 | { | ||
| 290 | struct btmrvl_private *priv = file->private_data; | ||
| 291 | char buf[16]; | ||
| 292 | int ret; | ||
| 293 | |||
| 294 | ret = snprintf(buf, sizeof(buf) - 1, "%d\n", priv->btmrvl_dev.hsmode); | ||
| 295 | |||
| 296 | return simple_read_from_buffer(userbuf, count, ppos, buf, ret); | ||
| 297 | } | ||
| 298 | |||
| 299 | static const struct file_operations btmrvl_hsmode_fops = { | ||
| 300 | .read = btmrvl_hsmode_read, | ||
| 301 | .write = btmrvl_hsmode_write, | ||
| 302 | .open = simple_open, | ||
| 303 | .llseek = default_llseek, | ||
| 304 | }; | ||
| 305 | |||
| 306 | static ssize_t btmrvl_curpsmode_read(struct file *file, char __user *userbuf, | ||
| 307 | size_t count, loff_t *ppos) | ||
| 308 | { | ||
| 309 | struct btmrvl_private *priv = file->private_data; | ||
| 310 | char buf[16]; | ||
| 311 | int ret; | ||
| 312 | |||
| 313 | ret = snprintf(buf, sizeof(buf) - 1, "%d\n", priv->adapter->psmode); | ||
| 314 | |||
| 315 | return simple_read_from_buffer(userbuf, count, ppos, buf, ret); | ||
| 316 | } | ||
| 317 | |||
| 318 | static const struct file_operations btmrvl_curpsmode_fops = { | ||
| 319 | .read = btmrvl_curpsmode_read, | ||
| 320 | .open = simple_open, | ||
| 321 | .llseek = default_llseek, | ||
| 322 | }; | ||
| 323 | |||
| 324 | static ssize_t btmrvl_psstate_read(struct file *file, char __user * userbuf, | ||
| 325 | size_t count, loff_t *ppos) | ||
| 326 | { | ||
| 327 | struct btmrvl_private *priv = file->private_data; | ||
| 328 | char buf[16]; | ||
| 329 | int ret; | ||
| 330 | |||
| 331 | ret = snprintf(buf, sizeof(buf) - 1, "%d\n", priv->adapter->ps_state); | ||
| 332 | |||
| 333 | return simple_read_from_buffer(userbuf, count, ppos, buf, ret); | ||
| 334 | } | ||
| 335 | |||
| 336 | static const struct file_operations btmrvl_psstate_fops = { | ||
| 337 | .read = btmrvl_psstate_read, | ||
| 338 | .open = simple_open, | ||
| 339 | .llseek = default_llseek, | ||
| 340 | }; | ||
| 341 | |||
| 342 | static ssize_t btmrvl_hsstate_read(struct file *file, char __user *userbuf, | ||
| 343 | size_t count, loff_t *ppos) | ||
| 344 | { | ||
| 345 | struct btmrvl_private *priv = file->private_data; | ||
| 346 | char buf[16]; | ||
| 347 | int ret; | ||
| 348 | |||
| 349 | ret = snprintf(buf, sizeof(buf) - 1, "%d\n", priv->adapter->hs_state); | ||
| 350 | |||
| 351 | return simple_read_from_buffer(userbuf, count, ppos, buf, ret); | ||
| 352 | } | ||
| 353 | |||
| 354 | static const struct file_operations btmrvl_hsstate_fops = { | ||
| 355 | .read = btmrvl_hsstate_read, | ||
| 356 | .open = simple_open, | ||
| 357 | .llseek = default_llseek, | ||
| 358 | }; | ||
| 359 | |||
| 360 | static ssize_t btmrvl_txdnldready_read(struct file *file, char __user *userbuf, | ||
| 361 | size_t count, loff_t *ppos) | ||
| 362 | { | ||
| 363 | struct btmrvl_private *priv = file->private_data; | ||
| 364 | char buf[16]; | ||
| 365 | int ret; | ||
| 366 | |||
| 367 | ret = snprintf(buf, sizeof(buf) - 1, "%d\n", | ||
| 368 | priv->btmrvl_dev.tx_dnld_rdy); | ||
| 369 | |||
| 370 | return simple_read_from_buffer(userbuf, count, ppos, buf, ret); | ||
| 371 | } | ||
| 372 | |||
| 373 | static const struct file_operations btmrvl_txdnldready_fops = { | ||
| 374 | .read = btmrvl_txdnldready_read, | ||
| 375 | .open = simple_open, | ||
| 376 | .llseek = default_llseek, | ||
| 377 | }; | ||
| 378 | |||
| 379 | void btmrvl_debugfs_init(struct hci_dev *hdev) | 170 | void btmrvl_debugfs_init(struct hci_dev *hdev) |
| 380 | { | 171 | { |
| 381 | struct btmrvl_private *priv = hci_get_drvdata(hdev); | 172 | struct btmrvl_private *priv = hci_get_drvdata(hdev); |
| @@ -394,30 +185,28 @@ void btmrvl_debugfs_init(struct hci_dev *hdev) · 12 unmodified lines | |||
| 394 | 185 | ||
| 395 | dbg->config_dir = debugfs_create_dir("config", hdev->debugfs); | 186 | dbg->config_dir = debugfs_create_dir("config", hdev->debugfs); |
| 396 | 187 | ||
| 397 | dbg->psmode = debugfs_create_file("psmode", 0644, dbg->config_dir, | 188 | debugfs_create_u8("psmode", 0644, dbg->config_dir, |
| 398 | priv, &btmrvl_psmode_fops); | 189 | &priv->btmrvl_dev.psmode); |
| 399 | dbg->pscmd = debugfs_create_file("pscmd", 0644, dbg->config_dir, | 190 | debugfs_create_file("pscmd", 0644, dbg->config_dir, |
| 400 | priv, &btmrvl_pscmd_fops); | 191 | priv, &btmrvl_pscmd_fops); |
| 401 | dbg->gpiogap = debugfs_create_file("gpiogap", 0644, dbg->config_dir, | 192 | debugfs_create_x16("gpiogap", 0644, dbg->config_dir, |
| 402 | priv, &btmrvl_gpiogap_fops); | 193 | &priv->btmrvl_dev.gpio_gap); |
| 403 | dbg->hsmode = debugfs_create_file("hsmode", 0644, dbg->config_dir, | 194 | debugfs_create_u8("hsmode", 0644, dbg->config_dir, |
| 404 | priv, &btmrvl_hsmode_fops); | 195 | &priv->btmrvl_dev.hsmode); |
| 405 | dbg->hscmd = debugfs_create_file("hscmd", 0644, dbg->config_dir, | 196 | debugfs_create_file("hscmd", 0644, dbg->config_dir, |
| 406 | priv, &btmrvl_hscmd_fops); | 197 | priv, &btmrvl_hscmd_fops); |
| 407 | dbg->hscfgcmd = debugfs_create_file("hscfgcmd", 0644, dbg->config_dir, | 198 | debugfs_create_file("hscfgcmd", 0644, dbg->config_dir, |
| 408 | priv, &btmrvl_hscfgcmd_fops); | 199 | priv, &btmrvl_hscfgcmd_fops); |
| 409 | 200 | ||
| 410 | dbg->status_dir = debugfs_create_dir("status", hdev->debugfs); | 201 | dbg->status_dir = debugfs_create_dir("status", hdev->debugfs); |
| 411 | dbg->curpsmode = debugfs_create_file("curpsmode", 0444, | 202 | debugfs_create_u8("curpsmode", 0444, dbg->status_dir, |
| 412 | dbg->status_dir, priv, | 203 | &priv->adapter->psmode); |
| 413 | &btmrvl_curpsmode_fops); | 204 | debugfs_create_u8("psstate", 0444, dbg->status_dir, |
| 414 | dbg->psstate = debugfs_create_file("psstate", 0444, dbg->status_dir, | 205 | &priv->adapter->ps_state); |
| 415 | priv, &btmrvl_psstate_fops); | 206 | debugfs_create_u8("hsstate", 0444, dbg->status_dir, |
| 416 | dbg->hsstate = debugfs_create_file("hsstate", 0444, dbg->status_dir, | 207 | &priv->adapter->hs_state); |
| 417 | priv, &btmrvl_hsstate_fops); | 208 | debugfs_create_u8("txdnldready", 0444, dbg->status_dir, |
| 418 | dbg->txdnldready = debugfs_create_file("txdnldready", 0444, | 209 | &priv->btmrvl_dev.tx_dnld_rdy); |
| 419 | dbg->status_dir, priv, | ||
| 420 | &btmrvl_txdnldready_fops); | ||
| 421 | } | 210 | } |
| 422 | 211 | ||
| 423 | void btmrvl_debugfs_remove(struct hci_dev *hdev) | 212 | void btmrvl_debugfs_remove(struct hci_dev *hdev) |
| @@ -428,19 +217,8 @@ void btmrvl_debugfs_remove(struct hci_dev *hdev) · 4 unmodified lines | |||
| 428 | if (!dbg) | 217 | if (!dbg) |
| 429 | return; | 218 | return; |
| 430 | 219 | ||
| 431 | debugfs_remove(dbg->psmode); | 220 | debugfs_remove_recursive(dbg->config_dir); |
| 432 | debugfs_remove(dbg->pscmd); | 221 | debugfs_remove_recursive(dbg->status_dir); |
| 433 | debugfs_remove(dbg->gpiogap); | ||
| 434 | debugfs_remove(dbg->hsmode); | ||
| 435 | debugfs_remove(dbg->hscmd); | ||
| 436 | debugfs_remove(dbg->hscfgcmd); | ||
| 437 | debugfs_remove(dbg->config_dir); | ||
| 438 | |||
| 439 | debugfs_remove(dbg->curpsmode); | ||
| 440 | debugfs_remove(dbg->psstate); | ||
| 441 | debugfs_remove(dbg->hsstate); | ||
| 442 | debugfs_remove(dbg->txdnldready); | ||
| 443 | debugfs_remove(dbg->status_dir); | ||
| 444 | 222 | ||
| 445 | kfree(dbg); | 223 | kfree(dbg); |
| 446 | } | 224 | } |
| @@ -83,8 +83,8 @@ static const struct btmrvl_sdio_card_reg btmrvl_reg_87xx = { · 82 unmodified lines | |||
| 83 | }; | 83 | }; |
| 84 | 84 | ||
| 85 | static const struct btmrvl_sdio_device btmrvl_sdio_sd8688 = { | 85 | static const struct btmrvl_sdio_device btmrvl_sdio_sd8688 = { |
| 86 | .helper = "sd8688_helper.bin", | 86 | .helper = "mrvl/sd8688_helper.bin", |
| 87 | .firmware = "sd8688.bin", | 87 | .firmware = "mrvl/sd8688.bin", |
| 88 | .reg = &btmrvl_reg_8688, | 88 | .reg = &btmrvl_reg_8688, |
| 89 | .sd_blksz_fw_dl = 64, | 89 | .sd_blksz_fw_dl = 64, |
| 90 | }; | 90 | }; |
| @@ -228,24 +228,24 @@ failed: · 137 unmodified lines | |||
| 228 | static int btmrvl_sdio_verify_fw_download(struct btmrvl_sdio_card *card, | 228 | static int btmrvl_sdio_verify_fw_download(struct btmrvl_sdio_card *card, |
| 229 | int pollnum) | 229 | int pollnum) |
| 230 | { | 230 | { |
| 231 | int ret = -ETIMEDOUT; | ||
| 232 | u16 firmwarestat; | 231 | u16 firmwarestat; |
| 233 | unsigned int tries; | 232 | int tries, ret; |
| 234 | 233 | ||
| 235 | /* Wait for firmware to become ready */ | 234 | /* Wait for firmware to become ready */ |
| 236 | for (tries = 0; tries < pollnum; tries++) { | 235 | for (tries = 0; tries < pollnum; tries++) { |
| 237 | if (btmrvl_sdio_read_fw_status(card, &firmwarestat) < 0) | 236 | sdio_claim_host(card->func); |
| 237 | ret = btmrvl_sdio_read_fw_status(card, &firmwarestat); | ||
| 238 | sdio_release_host(card->func); | ||
| 239 | if (ret < 0) | ||
| 238 | continue; | 240 | continue; |
| 239 | 241 | ||
| 240 | if (firmwarestat == FIRMWARE_READY) { | 242 | if (firmwarestat == FIRMWARE_READY) |
| 241 | ret = 0; | 243 | return 0; |
| 242 | break; | 244 | |
| 243 | } else { | 245 | msleep(10); |
| 244 | msleep(10); | ||
| 245 | } | ||
| 246 | } | 246 | } |
| 247 | 247 | ||
| 248 | return ret; | 248 | return -ETIMEDOUT; |
| 249 | } | 249 | } |
| 250 | 250 | ||
| 251 | static int btmrvl_sdio_download_helper(struct btmrvl_sdio_card *card) | 251 | static int btmrvl_sdio_download_helper(struct btmrvl_sdio_card *card) |
| @@ -874,7 +874,7 @@ exit: · 622 unmodified lines | |||
| 874 | 874 | ||
| 875 | static int btmrvl_sdio_download_fw(struct btmrvl_sdio_card *card) | 875 | static int btmrvl_sdio_download_fw(struct btmrvl_sdio_card *card) |
| 876 | { | 876 | { |
| 877 | int ret = 0; | 877 | int ret; |
| 878 | u8 fws0; | 878 | u8 fws0; |
| 879 | int pollnum = MAX_POLL_TRIES; | 879 | int pollnum = MAX_POLL_TRIES; |
| 880 | 880 | ||
| @@ -882,13 +882,14 @@ static int btmrvl_sdio_download_fw(struct btmrvl_sdio_card *card) · 1 unmodified line | |||
| 882 | BT_ERR("card or function is NULL!"); | 882 | BT_ERR("card or function is NULL!"); |
| 883 | return -EINVAL; | 883 | return -EINVAL; |
| 884 | } | 884 | } |
| 885 | sdio_claim_host(card->func); | ||
| 886 | 885 | ||
| 887 | if (!btmrvl_sdio_verify_fw_download(card, 1)) { | 886 | if (!btmrvl_sdio_verify_fw_download(card, 1)) { |
| 888 | BT_DBG("Firmware already downloaded!"); | 887 | BT_DBG("Firmware already downloaded!"); |
| 889 | goto done; | 888 | return 0; |
| 890 | } | 889 | } |
| 891 | 890 | ||
| 891 | sdio_claim_host(card->func); | ||
| 892 | |||
| 892 | /* Check if other function driver is downloading the firmware */ | 893 | /* Check if other function driver is downloading the firmware */ |
| 893 | fws0 = sdio_readb(card->func, card->reg->card_fw_status0, &ret); | 894 | fws0 = sdio_readb(card->func, card->reg->card_fw_status0, &ret); |
| 894 | if (ret) { | 895 | if (ret) { |
| @@ -918,15 +919,21 @@ static int btmrvl_sdio_download_fw(struct btmrvl_sdio_card *card) · 23 unmodified lines | |||
| 918 | } | 919 | } |
| 919 | } | 920 | } |
| 920 | 921 | ||
| 922 | sdio_release_host(card->func); | ||
| 923 | |||
| 924 | /* | ||
| 925 | * winner or not, with this test the FW synchronizes when the | ||
| 926 | * module can continue its initialization | ||
| 927 | */ | ||
| 921 | if (btmrvl_sdio_verify_fw_download(card, pollnum)) { | 928 | if (btmrvl_sdio_verify_fw_download(card, pollnum)) { |
| 922 | BT_ERR("FW failed to be active in time!"); | 929 | BT_ERR("FW failed to be active in time!"); |
| 923 | ret = -ETIMEDOUT; | 930 | return -ETIMEDOUT; |
| 924 | goto done; | ||
| 925 | } | 931 | } |
| 926 | 932 | ||
| 933 | return 0; | ||
| 934 | |||
| 927 | done: | 935 | done: |
| 928 | sdio_release_host(card->func); | 936 | sdio_release_host(card->func); |
| 929 | |||
| 930 | return ret; | 937 | return ret; |
| 931 | } | 938 | } |
| 932 | 939 | ||
| @@ -989,8 +996,6 @@ static int btmrvl_sdio_probe(struct sdio_func *func, · 56 unmodified lines | |||
| 989 | goto unreg_dev; | 996 | goto unreg_dev; |
| 990 | } | 997 | } |
| 991 | 998 | ||
| 992 | msleep(100); | ||
| 993 | |||
| 994 | btmrvl_sdio_enable_host_int(card); | 999 | btmrvl_sdio_enable_host_int(card); |
| 995 | 1000 | ||
| 996 | priv = btmrvl_add_card(card); | 1001 | priv = btmrvl_add_card(card); |
| @@ -1185,7 +1190,7 @@ MODULE_AUTHOR("Marvell International Ltd."); · 188 unmodified lines | |||
| 1185 | MODULE_DESCRIPTION("Marvell BT-over-SDIO driver ver " VERSION); | 1190 | MODULE_DESCRIPTION("Marvell BT-over-SDIO driver ver " VERSION); |
| 1186 | MODULE_VERSION(VERSION); | 1191 | MODULE_VERSION(VERSION); |
| 1187 | MODULE_LICENSE("GPL v2"); | 1192 | MODULE_LICENSE("GPL v2"); |
| 1188 | MODULE_FIRMWARE("sd8688_helper.bin"); | 1193 | MODULE_FIRMWARE("mrvl/sd8688_helper.bin"); |
| 1189 | MODULE_FIRMWARE("sd8688.bin"); | 1194 | MODULE_FIRMWARE("mrvl/sd8688.bin"); |
| 1190 | MODULE_FIRMWARE("mrvl/sd8787_uapsta.bin"); | 1195 | MODULE_FIRMWARE("mrvl/sd8787_uapsta.bin"); |
| 1191 | MODULE_FIRMWARE("mrvl/sd8797_uapsta.bin"); | 1196 | MODULE_FIRMWARE("mrvl/sd8797_uapsta.bin"); |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | |||
| 23 | 23 | ||
| 24 | #include <linux/module.h> | 24 | #include <linux/module.h> |
| 25 | #include <linux/usb.h> | 25 | #include <linux/usb.h> |
| 26 | #include <linux/firmware.h> | ||
| 26 | 27 | ||
| 27 | #include <net/bluetooth/bluetooth.h> | 28 | #include <net/bluetooth/bluetooth.h> |
| 28 | #include <net/bluetooth/hci_core.h> | 29 | #include <net/bluetooth/hci_core.h> |
| @@ -47,6 +48,7 @@ static struct usb_driver btusb_driver; · 18 unmodified lines | |||
| 47 | #define BTUSB_BROKEN_ISOC 0x20 | 48 | #define BTUSB_BROKEN_ISOC 0x20 |
| 48 | #define BTUSB_WRONG_SCO_MTU 0x40 | 49 | #define BTUSB_WRONG_SCO_MTU 0x40 |
| 49 | #define BTUSB_ATH3012 0x80 | 50 | #define BTUSB_ATH3012 0x80 |
| 51 | #define BTUSB_INTEL 0x100 | ||
| 50 | 52 | ||
| 51 | static struct usb_device_id btusb_table[] = { | 53 | static struct usb_device_id btusb_table[] = { |
| 52 | /* Generic Bluetooth USB device */ | 54 | /* Generic Bluetooth USB device */ |
| @@ -148,6 +150,7 @@ static struct usb_device_id blacklist_table[] = { · 95 unmodified lines | |||
| 148 | { USB_DEVICE(0x13d3, 0x3393), .driver_info = BTUSB_ATH3012 }, | 150 | { USB_DEVICE(0x13d3, 0x3393), .driver_info = BTUSB_ATH3012 }, |
| 149 | { USB_DEVICE(0x0489, 0xe04e), .driver_info = BTUSB_ATH3012 }, | 151 | { USB_DEVICE(0x0489, 0xe04e), .driver_info = BTUSB_ATH3012 }, |
| 150 | { USB_DEVICE(0x0489, 0xe056), .driver_info = BTUSB_ATH3012 }, | 152 | { USB_DEVICE(0x0489, 0xe056), .driver_info = BTUSB_ATH3012 }, |
| 153 | { USB_DEVICE(0x0489, 0xe04d), .driver_info = BTUSB_ATH3012 }, | ||
| 151 | 154 | ||
| 152 | /* Atheros AR5BBU12 with sflash firmware */ | 155 | /* Atheros AR5BBU12 with sflash firmware */ |
| 153 | { USB_DEVICE(0x0489, 0xe02c), .driver_info = BTUSB_IGNORE }, | 156 | { USB_DEVICE(0x0489, 0xe02c), .driver_info = BTUSB_IGNORE }, |
| @@ -206,6 +209,9 @@ static struct usb_device_id blacklist_table[] = { · 52 unmodified lines | |||
| 206 | /* Frontline ComProbe Bluetooth Sniffer */ | 209 | /* Frontline ComProbe Bluetooth Sniffer */ |
| 207 | { USB_DEVICE(0x16d3, 0x0002), .driver_info = BTUSB_SNIFFER }, | 210 | { USB_DEVICE(0x16d3, 0x0002), .driver_info = BTUSB_SNIFFER }, |
| 208 | 211 | ||
| 212 | /* Intel Bluetooth device */ | ||
| 213 | { USB_DEVICE(0x8087, 0x07dc), .driver_info = BTUSB_INTEL }, | ||
| 214 | |||
| 209 | { } /* Terminating entry */ | 215 | { } /* Terminating entry */ |
| 210 | }; | 216 | }; |
| 211 | 217 | ||
| @@ -926,6 +932,391 @@ static void btusb_waker(struct work_struct *work) · 714 unmodified lines | |||
| 926 | usb_autopm_put_interface(data->intf); | 932 | usb_autopm_put_interface(data->intf); |
| 927 | } | 933 | } |
| 928 | 934 | ||
| 935 | static int btusb_setup_bcm92035(struct hci_dev *hdev) | ||
| 936 | { | ||
| 937 | struct sk_buff *skb; | ||
| 938 | u8 val = 0x00; | ||
| 939 | |||
| 940 | BT_DBG("%s", hdev->name); | ||
| 941 | |||
| 942 | skb = __hci_cmd_sync(hdev, 0xfc3b, 1, &val, HCI_INIT_TIMEOUT); | ||
| 943 | if (IS_ERR(skb)) | ||
| 944 | BT_ERR("BCM92035 command failed (%ld)", -PTR_ERR(skb)); | ||
| 945 | else | ||
| 946 | kfree_skb(skb); | ||
| 947 | |||
| 948 | return 0; | ||
| 949 | } | ||
| 950 | |||
| 951 | struct intel_version { | ||
| 952 | u8 status; | ||
| 953 | u8 hw_platform; | ||
| 954 | u8 hw_variant; | ||
| 955 | u8 hw_revision; | ||
| 956 | u8 fw_variant; | ||
| 957 | u8 fw_revision; | ||
| 958 | u8 fw_build_num; | ||
| 959 | u8 fw_build_ww; | ||
| 960 | u8 fw_build_yy; | ||
| 961 | u8 fw_patch_num; | ||
| 962 | } __packed; | ||
| 963 | |||
| 964 | static const struct firmware *btusb_setup_intel_get_fw(struct hci_dev *hdev, | ||
| 965 | struct intel_version *ver) | ||
| 966 | { | ||
| 967 | const struct firmware *fw; | ||
| 968 | char fwname[64]; | ||
| 969 | int ret; | ||
| 970 | |||
| 971 | snprintf(fwname, sizeof(fwname), | ||
| 972 | "intel/ibt-hw-%x.%x.%x-fw-%x.%x.%x.%x.%x.bseq", | ||
| 973 | ver->hw_platform, ver->hw_variant, ver->hw_revision, | ||
| 974 | ver->fw_variant, ver->fw_revision, ver->fw_build_num, | ||
| 975 | ver->fw_build_ww, ver->fw_build_yy); | ||
| 976 | |||
| 977 | ret = request_firmware(&fw, fwname, &hdev->dev); | ||
| 978 | if (ret < 0) { | ||
| 979 | if (ret == -EINVAL) { | ||
| 980 | BT_ERR("%s Intel firmware file request failed (%d)", | ||
| 981 | hdev->name, ret); | ||
| 982 | return NULL; | ||
| 983 | } | ||
| 984 | |||
| 985 | BT_ERR("%s failed to open Intel firmware file: %s(%d)", | ||
| 986 | hdev->name, fwname, ret); | ||
| 987 | |||
| 988 | /* If the correct firmware patch file is not found, use the | ||
| 989 | * default firmware patch file instead | ||
| 990 | */ | ||
| 991 | snprintf(fwname, sizeof(fwname), "intel/ibt-hw-%x.%x.bseq", | ||
| 992 | ver->hw_platform, ver->hw_variant); | ||
| 993 | if (request_firmware(&fw, fwname, &hdev->dev) < 0) { | ||
| 994 | BT_ERR("%s failed to open default Intel fw file: %s", | ||
| 995 | hdev->name, fwname); | ||
| 996 | return NULL; | ||
| 997 | } | ||
| 998 | } | ||
| 999 | |||
| 1000 | BT_INFO("%s: Intel Bluetooth firmware file: %s", hdev->name, fwname); | ||
| 1001 | |||
| 1002 | return fw; | ||
| 1003 | } | ||
| 1004 | |||
| 1005 | static int btusb_setup_intel_patching(struct hci_dev *hdev, | ||
| 1006 | const struct firmware *fw, | ||
| 1007 | const u8 **fw_ptr, int *disable_patch) | ||
| 1008 | { | ||
| 1009 | struct sk_buff *skb; | ||
| 1010 | struct hci_command_hdr *cmd; | ||
| 1011 | const u8 *cmd_param; | ||
| 1012 | struct hci_event_hdr *evt = NULL; | ||
| 1013 | const u8 *evt_param = NULL; | ||
| 1014 | int remain = fw->size - (*fw_ptr - fw->data); | ||
| 1015 | |||
| 1016 | /* The first byte indicates the types of the patch command or event. | ||
| 1017 | * 0x01 means HCI command and 0x02 is HCI event. If the first bytes | ||
| 1018 | * in the current firmware buffer doesn't start with 0x01 or | ||
| 1019 | * the size of remain buffer is smaller than HCI command header, | ||
| 1020 | * the firmware file is corrupted and it should stop the patching | ||
| 1021 | * process. | ||
| 1022 | */ | ||
| 1023 | if (remain > HCI_COMMAND_HDR_SIZE && *fw_ptr[0] != 0x01) { | ||
| 1024 | BT_ERR("%s Intel fw corrupted: invalid cmd read", hdev->name); | ||
| 1025 | return -EINVAL; | ||
| 1026 | } | ||
| 1027 | (*fw_ptr)++; | ||
| 1028 | remain--; | ||
| 1029 | |||
| 1030 | cmd = (struct hci_command_hdr *)(*fw_ptr); | ||
| 1031 | *fw_ptr += sizeof(*cmd); | ||
| 1032 | remain -= sizeof(*cmd); | ||
| 1033 | |||
| 1034 | /* Ensure that the remain firmware data is long enough than the length | ||
| 1035 | * of command parameter. If not, the firmware file is corrupted. | ||
| 1036 | */ | ||
| 1037 | if (remain < cmd->plen) { | ||
| 1038 | BT_ERR("%s Intel fw corrupted: invalid cmd len", hdev->name); | ||
| 1039 | return -EFAULT; | ||
| 1040 | } | ||
| 1041 | |||
| 1042 | /* If there is a command that loads a patch in the firmware | ||
| 1043 | * file, then enable the patch upon success, otherwise just | ||
| 1044 | * disable the manufacturer mode, for example patch activation | ||
| 1045 | * is not required when the default firmware patch file is used | ||
| 1046 | * because there are no patch data to load. | ||
| 1047 | */ | ||
| 1048 | if (*disable_patch && le16_to_cpu(cmd->opcode) == 0xfc8e) | ||
| 1049 | *disable_patch = 0; | ||
| 1050 | |||
| 1051 | cmd_param = *fw_ptr; | ||
| 1052 | *fw_ptr += cmd->plen; | ||
| 1053 | remain -= cmd->plen; | ||
| 1054 | |||
| 1055 | /* This reads the expected events when the above command is sent to the | ||
| 1056 | * device. Some vendor commands expects more than one events, for | ||
| 1057 | * example command status event followed by vendor specific event. | ||
| 1058 | * For this case, it only keeps the last expected event. so the command | ||
| 1059 | * can be sent with __hci_cmd_sync_ev() which returns the sk_buff of | ||
| 1060 | * last expected event. | ||
| 1061 | */ | ||
| 1062 | while (remain > HCI_EVENT_HDR_SIZE && *fw_ptr[0] == 0x02) { | ||
| 1063 | (*fw_ptr)++; | ||
| 1064 | remain--; | ||
| 1065 | |||
| 1066 | evt = (struct hci_event_hdr *)(*fw_ptr); | ||
| 1067 | *fw_ptr += sizeof(*evt); | ||
| 1068 | remain -= sizeof(*evt); | ||
| 1069 | |||
| 1070 | if (remain < evt->plen) { | ||
| 1071 | BT_ERR("%s Intel fw corrupted: invalid evt len", | ||
| 1072 | hdev->name); | ||
| 1073 | return -EFAULT; | ||
| 1074 | } | ||
| 1075 | |||
| 1076 | evt_param = *fw_ptr; | ||
| 1077 | *fw_ptr += evt->plen; | ||
| 1078 | remain -= evt->plen; | ||
| 1079 | } | ||
| 1080 | |||
| 1081 | /* Every HCI commands in the firmware file has its correspond event. | ||
| 1082 | * If event is not found or remain is smaller than zero, the firmware | ||
| 1083 | * file is corrupted. | ||
| 1084 | */ | ||
| 1085 | if (!evt || !evt_param || remain < 0) { | ||
| 1086 | BT_ERR("%s Intel fw corrupted: invalid evt read", hdev->name); | ||
| 1087 | return -EFAULT; | ||
| 1088 | } | ||
| 1089 | |||
| 1090 | skb = __hci_cmd_sync_ev(hdev, le16_to_cpu(cmd->opcode), cmd->plen, | ||
| 1091 | cmd_param, evt->evt, HCI_INIT_TIMEOUT); | ||
| 1092 | if (IS_ERR(skb)) { | ||
| 1093 | BT_ERR("%s sending Intel patch command (0x%4.4x) failed (%ld)", | ||
| 1094 | hdev->name, cmd->opcode, PTR_ERR(skb)); | ||
| 1095 | return -PTR_ERR(skb); | ||
| 1096 | } | ||
| 1097 | |||
| 1098 | /* It ensures that the returned event matches the event data read from | ||
| 1099 | * the firmware file. At fist, it checks the length and then | ||
| 1100 | * the contents of the event. | ||
| 1101 | */ | ||
| 1102 | if (skb->len != evt->plen) { | ||
| 1103 | BT_ERR("%s mismatch event length (opcode 0x%4.4x)", hdev->name, | ||
| 1104 | le16_to_cpu(cmd->opcode)); | ||
| 1105 | kfree_skb(skb); | ||
| 1106 | return -EFAULT; | ||
| 1107 | } | ||
| 1108 | |||
| 1109 | if (memcmp(skb->data, evt_param, evt->plen)) { | ||
| 1110 | BT_ERR("%s mismatch event parameter (opcode 0x%4.4x)", | ||
| 1111 | hdev->name, le16_to_cpu(cmd->opcode)); | ||
| 1112 | kfree_skb(skb); | ||
| 1113 | return -EFAULT; | ||
| 1114 | } | ||
| 1115 | kfree_skb(skb); | ||
| 1116 | |||
| 1117 | return 0; | ||
| 1118 | } | ||
| 1119 | |||
| 1120 | static int btusb_setup_intel(struct hci_dev *hdev) | ||
| 1121 | { | ||
| 1122 | struct sk_buff *skb; | ||
| 1123 | const struct firmware *fw; | ||
| 1124 | const u8 *fw_ptr; | ||
| 1125 | int disable_patch; | ||
| 1126 | struct intel_version *ver; | ||
| 1127 | |||
| 1128 | const u8 mfg_enable[] = { 0x01, 0x00 }; | ||
| 1129 | const u8 mfg_disable[] = { 0x00, 0x00 }; | ||
| 1130 | const u8 mfg_reset_deactivate[] = { 0x00, 0x01 }; | ||
| 1131 | const u8 mfg_reset_activate[] = { 0x00, 0x02 }; | ||
| 1132 | |||
| 1133 | BT_DBG("%s", hdev->name); | ||
| 1134 | |||
| 1135 | /* The controller has a bug with the first HCI command sent to it | ||
| 1136 | * returning number of completed commands as zero. This would stall the | ||
| 1137 | * command processing in the Bluetooth core. | ||
| 1138 | * | ||
| 1139 | * As a workaround, send HCI Reset command first which will reset the | ||
| 1140 | * number of completed commands and allow normal command processing | ||
| 1141 | * from now on. | ||
| 1142 | */ | ||
| 1143 | skb = __hci_cmd_sync(hdev, HCI_OP_RESET, 0, NULL, HCI_INIT_TIMEOUT); | ||
| 1144 | if (IS_ERR(skb)) { | ||
| 1145 | BT_ERR("%s sending initial HCI reset command failed (%ld)", | ||
| 1146 | hdev->name, PTR_ERR(skb)); | ||
| 1147 | return -PTR_ERR(skb); | ||
| 1148 | } | ||
| 1149 | kfree_skb(skb); | ||
| 1150 | |||
| 1151 | /* Read Intel specific controller version first to allow selection of | ||
| 1152 | * which firmware file to load. | ||
| 1153 | * | ||
| 1154 | * The returned information are hardware variant and revision plus | ||
| 1155 | * firmware variant, revision and build number. | ||
| 1156 | */ | ||
| 1157 | skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_INIT_TIMEOUT); | ||
| 1158 | if (IS_ERR(skb)) { | ||
| 1159 | BT_ERR("%s reading Intel fw version command failed (%ld)", | ||
| 1160 | hdev->name, PTR_ERR(skb)); | ||
| 1161 | return -PTR_ERR(skb); | ||
| 1162 | } | ||
| 1163 | |||
| 1164 | if (skb->len != sizeof(*ver)) { | ||
| 1165 | BT_ERR("%s Intel version event length mismatch", hdev->name); | ||
| 1166 | kfree_skb(skb); | ||
| 1167 | return -EIO; | ||
| 1168 | } | ||
| 1169 | |||
| 1170 | ver = (struct intel_version *)skb->data; | ||
| 1171 | if (ver->status) { | ||
| 1172 | BT_ERR("%s Intel fw version event failed (%02x)", hdev->name, | ||
| 1173 | ver->status); | ||
| 1174 | kfree_skb(skb); | ||
| 1175 | return -bt_to_errno(ver->status); | ||
| 1176 | } | ||
| 1177 | |||
| 1178 | BT_INFO("%s: read Intel version: %02x%02x%02x%02x%02x%02x%02x%02x%02x", | ||
| 1179 | hdev->name, ver->hw_platform, ver->hw_variant, | ||
| 1180 | ver->hw_revision, ver->fw_variant, ver->fw_revision, | ||
| 1181 | ver->fw_build_num, ver->fw_build_ww, ver->fw_build_yy, | ||
| 1182 | ver->fw_patch_num); | ||
| 1183 | |||
| 1184 | /* fw_patch_num indicates the version of patch the device currently | ||
| 1185 | * have. If there is no patch data in the device, it is always 0x00. | ||
| 1186 | * So, if it is other than 0x00, no need to patch the deivce again. | ||
| 1187 | */ | ||
| 1188 | if (ver->fw_patch_num) { | ||
| 1189 | BT_INFO("%s: Intel device is already patched. patch num: %02x", | ||
| 1190 | hdev->name, ver->fw_patch_num); | ||
| 1191 | kfree_skb(skb); | ||
| 1192 | return 0; | ||
| 1193 | } | ||
| 1194 | |||
| 1195 | /* Opens the firmware patch file based on the firmware version read | ||
| 1196 | * from the controller. If it fails to open the matching firmware | ||
| 1197 | * patch file, it tries to open the default firmware patch file. | ||
| 1198 | * If no patch file is found, allow the device to operate without | ||
| 1199 | * a patch. | ||
| 1200 | */ | ||
| 1201 | fw = btusb_setup_intel_get_fw(hdev, ver); | ||
| 1202 | if (!fw) { | ||
| 1203 | kfree_skb(skb); | ||
| 1204 | return 0; | ||
| 1205 | } | ||
| 1206 | fw_ptr = fw->data; | ||
| 1207 | |||
| 1208 | /* This Intel specific command enables the manufacturer mode of the | ||
| 1209 | * controller. | ||
| 1210 | * | ||
| 1211 | * Only while this mode is enabled, the driver can download the | ||
| 1212 | * firmware patch data and configuration parameters. | ||
| 1213 | */ | ||
| 1214 | skb = __hci_cmd_sync(hdev, 0xfc11, 2, mfg_enable, HCI_INIT_TIMEOUT); | ||
| 1215 | if (IS_ERR(skb)) { | ||
| 1216 | BT_ERR("%s entering Intel manufacturer mode failed (%ld)", | ||
| 1217 | hdev->name, PTR_ERR(skb)); | ||
| 1218 | release_firmware(fw); | ||
| 1219 | return -PTR_ERR(skb); | ||
| 1220 | } | ||
| 1221 | |||
| 1222 | if (skb->data[0]) { | ||
| 1223 | u8 evt_status = skb->data[0]; | ||
| 1224 | BT_ERR("%s enable Intel manufacturer mode event failed (%02x)", | ||
| 1225 | hdev->name, evt_status); | ||
| 1226 | kfree_skb(skb); | ||
| 1227 | release_firmware(fw); | ||
| 1228 | return -bt_to_errno(evt_status); | ||
| 1229 | } | ||
| 1230 | kfree_skb(skb); | ||
| 1231 | |||
| 1232 | disable_patch = 1; | ||
| 1233 | |||
| 1234 | /* The firmware data file consists of list of Intel specific HCI | ||
| 1235 | * commands and its expected events. The first byte indicates the | ||
| 1236 | * type of the message, either HCI command or HCI event. | ||
| 1237 | * | ||
| 1238 | * It reads the command and its expected event from the firmware file, | ||
| 1239 | * and send to the controller. Once __hci_cmd_sync_ev() returns, | ||
| 1240 | * the returned event is compared with the event read from the firmware | ||
| 1241 | * file and it will continue until all the messages are downloaded to | ||
| 1242 | * the controller. | ||
| 1243 | * | ||
| 1244 | * Once the firmware patching is completed successfully, | ||
| 1245 | * the manufacturer mode is disabled with reset and activating the | ||
| 1246 | * downloaded patch. | ||
| 1247 | * | ||
| 1248 | * If the firmware patching fails, the manufacturer mode is | ||
| 1249 | * disabled with reset and deactivating the patch. | ||
| 1250 | * | ||
| 1251 | * If the default patch file is used, no reset is done when disabling | ||
| 1252 | * the manufacturer. | ||
| 1253 | */ | ||
| 1254 | while (fw->size > fw_ptr - fw->data) { | ||
| 1255 | int ret; | ||
| 1256 | |||
| 1257 | ret = btusb_setup_intel_patching(hdev, fw, &fw_ptr, | ||
| 1258 | &disable_patch); | ||
| 1259 | if (ret < 0) | ||
| 1260 | goto exit_mfg_deactivate; | ||
| 1261 | } | ||
| 1262 | |||
| 1263 | release_firmware(fw); | ||
| 1264 | |||
| 1265 | if (disable_patch) | ||
| 1266 | goto exit_mfg_disable; | ||
| 1267 | |||
| 1268 | /* Patching completed successfully and disable the manufacturer mode | ||
| 1269 | * with reset and activate the downloaded firmware patches. | ||
| 1270 | */ | ||
| 1271 | skb = __hci_cmd_sync(hdev, 0xfc11, sizeof(mfg_reset_activate), | ||
| 1272 | mfg_reset_activate, HCI_INIT_TIMEOUT); | ||
| 1273 | if (IS_ERR(skb)) { | ||
| 1274 | BT_ERR("%s exiting Intel manufacturer mode failed (%ld)", | ||
| 1275 | hdev->name, PTR_ERR(skb)); | ||
| 1276 | return -PTR_ERR(skb); | ||
| 1277 | } | ||
| 1278 | kfree_skb(skb); | ||
| 1279 | |||
| 1280 | BT_INFO("%s: Intel Bluetooth firmware patch completed and activated", | ||
| 1281 | hdev->name); | ||
| 1282 | |||
| 1283 | return 0; | ||
| 1284 | |||
| 1285 | exit_mfg_disable: | ||
| 1286 | /* Disable the manufacturer mode without reset */ | ||
| 1287 | skb = __hci_cmd_sync(hdev, 0xfc11, sizeof(mfg_disable), mfg_disable, | ||
| 1288 | HCI_INIT_TIMEOUT); | ||
| 1289 | if (IS_ERR(skb)) { | ||
| 1290 | BT_ERR("%s exiting Intel manufacturer mode failed (%ld)", | ||
| 1291 | hdev->name, PTR_ERR(skb)); | ||
| 1292 | return -PTR_ERR(skb); | ||
| 1293 | } | ||
| 1294 | kfree_skb(skb); | ||
| 1295 | |||
| 1296 | BT_INFO("%s: Intel Bluetooth firmware patch completed", hdev->name); | ||
| 1297 | return 0; | ||
| 1298 | |||
| 1299 | exit_mfg_deactivate: | ||
| 1300 | release_firmware(fw); | ||
| 1301 | |||
| 1302 | /* Patching failed. Disable the manufacturer mode with reset and | ||
| 1303 | * deactivate the downloaded firmware patches. | ||
| 1304 | */ | ||
| 1305 | skb = __hci_cmd_sync(hdev, 0xfc11, sizeof(mfg_reset_deactivate), | ||
| 1306 | mfg_reset_deactivate, HCI_INIT_TIMEOUT); | ||
| 1307 | if (IS_ERR(skb)) { | ||
| 1308 | BT_ERR("%s exiting Intel manufacturer mode failed (%ld)", | ||
| 1309 | hdev->name, PTR_ERR(skb)); | ||
| 1310 | return -PTR_ERR(skb); | ||
| 1311 | } | ||
| 1312 | kfree_skb(skb); | ||
| 1313 | |||
| 1314 | BT_INFO("%s: Intel Bluetooth firmware patch completed and deactivated", | ||
| 1315 | hdev->name); | ||
| 1316 | |||
| 1317 | return 0; | ||
| 1318 | } | ||
| 1319 | |||
| 929 | static int btusb_probe(struct usb_interface *intf, | 1320 | static int btusb_probe(struct usb_interface *intf, |
| 930 | const struct usb_device_id *id) | 1321 | const struct usb_device_id *id) |
| 931 | { | 1322 | { |
| @@ -1022,11 +1413,17 @@ static int btusb_probe(struct usb_interface *intf, · 90 unmodified lines | |||
| 1022 | 1413 | ||
| 1023 | SET_HCIDEV_DEV(hdev, &intf->dev); | 1414 | SET_HCIDEV_DEV(hdev, &intf->dev); |
| 1024 | 1415 | ||
| 1025 | hdev->open = btusb_open; | 1416 | hdev->open = btusb_open; |
| 1026 | hdev->close = btusb_close; | 1417 | hdev->close = btusb_close; |
| 1027 | hdev->flush = btusb_flush; | 1418 | hdev->flush = btusb_flush; |
| 1028 | hdev->send = btusb_send_frame; | 1419 | hdev->send = btusb_send_frame; |
| 1029 | hdev->notify = btusb_notify; | 1420 | hdev->notify = btusb_notify; |
| 1421 | |||
| 1422 | if (id->driver_info & BTUSB_BCM92035) | ||
| 1423 | hdev->setup = btusb_setup_bcm92035; | ||
| 1424 | |||
| 1425 | if (id->driver_info & BTUSB_INTEL) | ||
| 1426 | hdev->setup = btusb_setup_intel; | ||
| 1030 | 1427 | ||
| 1031 | /* Interface numbers are hardcoded in the specification */ | 1428 | /* Interface numbers are hardcoded in the specification */ |
| 1032 | data->isoc = usb_ifnum_to_if(data->udev, 1); | 1429 | data->isoc = usb_ifnum_to_if(data->udev, 1); |
| @@ -1065,17 +1462,6 @@ static int btusb_probe(struct usb_interface *intf, · 32 unmodified lines | |||
| 1065 | data->isoc = NULL; | 1462 | data->isoc = NULL; |
| 1066 | } | 1463 | } |
| 1067 | 1464 | ||
| 1068 | if (id->driver_info & BTUSB_BCM92035) { | ||
| 1069 | unsigned char cmd[] = { 0x3b, 0xfc, 0x01, 0x00 }; | ||
| 1070 | struct sk_buff *skb; | ||
| 1071 | |||
| 1072 | skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL); | ||
| 1073 | if (skb) { | ||
| 1074 | memcpy(skb_put(skb, sizeof(cmd)), cmd, sizeof(cmd)); | ||
| 1075 | skb_queue_tail(&hdev->driver_init, skb); | ||
| 1076 | } | ||
| 1077 | } | ||
| 1078 | |||
| 1079 | if (data->isoc) { | 1465 | if (data->isoc) { |
| 1080 | err = usb_driver_claim_interface(&btusb_driver, | 1466 | err = usb_driver_claim_interface(&btusb_driver, |
| 1081 | data->isoc, data); | 1467 | data->isoc, data); |
| @@ -153,6 +153,9 @@ static int h4_recv(struct hci_uart *hu, void *data, int count) · 152 unmodified lines | |||
| 153 | { | 153 | { |
| 154 | int ret; | 154 | int ret; |
| 155 | 155 | ||
| 156 | if (!test_bit(HCI_UART_REGISTERED, &hu->flags)) | ||
| 157 | return -EUNATCH; | ||
| 158 | |||
| 156 | ret = hci_recv_stream_fragment(hu->hdev, data, count); | 159 | ret = hci_recv_stream_fragment(hu->hdev, data, count); |
| 157 | if (ret < 0) { | 160 | if (ret < 0) { |
| 158 | BT_ERR("Frame Reassembly Failed"); | 161 | BT_ERR("Frame Reassembly Failed"); |
| @@ -260,12 +260,12 @@ static int hci_uart_send_frame(struct sk_buff *skb) · 259 unmodified lines | |||
| 260 | 260 | ||
| 261 | /* ------ LDISC part ------ */ | 261 | /* ------ LDISC part ------ */ |
| 262 | /* hci_uart_tty_open | 262 | /* hci_uart_tty_open |
| 263 | * | 263 | * |
| 264 | * Called when line discipline changed to HCI_UART. | 264 | * Called when line discipline changed to HCI_UART. |
| 265 | * | 265 | * |
| 266 | * Arguments: | 266 | * Arguments: |
| 267 | * tty pointer to tty info structure | 267 | * tty pointer to tty info structure |
| 268 | * Return Value: | 268 | * Return Value: |
| 269 | * 0 if success, otherwise error code | 269 | * 0 if success, otherwise error code |
| 270 | */ | 270 | */ |
| 271 | static int hci_uart_tty_open(struct tty_struct *tty) | 271 | static int hci_uart_tty_open(struct tty_struct *tty) |
| @@ -365,15 +365,15 @@ static void hci_uart_tty_wakeup(struct tty_struct *tty) · 93 unmodified lines | |||
| 365 | } | 365 | } |
| 366 | 366 | ||
| 367 | /* hci_uart_tty_receive() | 367 | /* hci_uart_tty_receive() |
| 368 | * | 368 | * |
| 369 | * Called by tty low level driver when receive data is | 369 | * Called by tty low level driver when receive data is |
| 370 | * available. | 370 | * available. |
| 371 | * | 371 | * |
| 372 | * Arguments: tty pointer to tty isntance data | 372 | * Arguments: tty pointer to tty isntance data |
| 373 | * data pointer to received data | 373 | * data pointer to received data |
| 374 | * flags pointer to flags for data | 374 | * flags pointer to flags for data |
| 375 | * count count of received data in bytes | 375 | * count count of received data in bytes |
| 376 | * | 376 | * |
| 377 | * Return Value: None | 377 | * Return Value: None |
| 378 | */ | 378 | */ |
| 379 | static void hci_uart_tty_receive(struct tty_struct *tty, const u8 *data, char *flags, int count) | 379 | static void hci_uart_tty_receive(struct tty_struct *tty, const u8 *data, char *flags, int count) |
| @@ -388,7 +388,10 @@ static void hci_uart_tty_receive(struct tty_struct *tty, const u8 *data, char *f · 8 unmodified lines | |||
| 388 | 388 | ||
| 389 | spin_lock(&hu->rx_lock); | 389 | spin_lock(&hu->rx_lock); |
| 390 | hu->proto->recv(hu, (void *) data, count); | 390 | hu->proto->recv(hu, (void *) data, count); |
| 391 | hu->hdev->stat.byte_rx += count; | 391 | |
| 392 | if (hu->hdev) | ||
| 393 | hu->hdev->stat.byte_rx += count; | ||
| 394 | |||
| 392 | spin_unlock(&hu->rx_lock); | 395 | spin_unlock(&hu->rx_lock); |
| 393 | 396 | ||
| 394 | tty_unthrottle(tty); | 397 | tty_unthrottle(tty); |
| @@ -232,6 +232,31 @@ void proc_comm_connector(struct task_struct *task) · 231 unmodified lines | |||
| 232 | cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL); | 232 | cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL); |
| 233 | } | 233 | } |
| 234 | 234 | ||
| 235 | void proc_coredump_connector(struct task_struct *task) | ||
| 236 | { | ||
| 237 | struct cn_msg *msg; | ||
| 238 | struct proc_event *ev; | ||
| 239 | __u8 buffer[CN_PROC_MSG_SIZE]; | ||
| 240 | struct timespec ts; | ||
| 241 | |||
| 242 | if (atomic_read(&proc_event_num_listeners) < 1) | ||
| 243 | return; | ||
| 244 | |||
| 245 | msg = (struct cn_msg *)buffer; | ||
| 246 | ev = (struct proc_event *)msg->data; | ||
| 247 | get_seq(&msg->seq, &ev->cpu); | ||
| 248 | ktime_get_ts(&ts); /* get high res monotonic timestamp */ | ||
| 249 | put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns); | ||
| 250 | ev->what = PROC_EVENT_COREDUMP; | ||
| 251 | ev->event_data.coredump.process_pid = task->pid; | ||
| 252 | ev->event_data.coredump.process_tgid = task->tgid; | ||
| 253 | |||
| 254 | memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id)); | ||
| 255 | msg->ack = 0; /* not used */ | ||
| 256 | msg->len = sizeof(*ev); | ||
| 257 | cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL); | ||
| 258 | } | ||
| 259 | |||
| 235 | void proc_exit_connector(struct task_struct *task) | 260 | void proc_exit_connector(struct task_struct *task) |
| 236 | { | 261 | { |
| 237 | struct cn_msg *msg; | 262 | struct cn_msg *msg; |
| @@ -23,7 +23,7 @@ · 22 unmodified lines | |||
| 23 | #include <linux/module.h> | 23 | #include <linux/module.h> |
| 24 | #include <linux/list.h> | 24 | #include <linux/list.h> |
| 25 | #include <linux/skbuff.h> | 25 | #include <linux/skbuff.h> |
| 26 | #include <linux/netlink.h> | 26 | #include <net/netlink.h> |
| 27 | #include <linux/moduleparam.h> | 27 | #include <linux/moduleparam.h> |
| 28 | #include <linux/connector.h> | 28 | #include <linux/connector.h> |
| 29 | #include <linux/slab.h> | 29 | #include <linux/slab.h> |
| @@ -95,13 +95,13 @@ int cn_netlink_send(struct cn_msg *msg, u32 __group, gfp_t gfp_mask) · 65 unmodified lines | |||
| 95 | if (!netlink_has_listeners(dev->nls, group)) | 95 | if (!netlink_has_listeners(dev->nls, group)) |
| 96 | return -ESRCH; | 96 | return -ESRCH; |
| 97 | 97 | ||
| 98 | size = NLMSG_SPACE(sizeof(*msg) + msg->len); | 98 | size = sizeof(*msg) + msg->len; |
| 99 | 99 | ||
| 100 | skb = alloc_skb(size, gfp_mask); | 100 | skb = nlmsg_new(size, gfp_mask); |
| 101 | if (!skb) | 101 | if (!skb) |
| 102 | return -ENOMEM; | 102 | return -ENOMEM; |
| 103 | 103 | ||
| 104 | nlh = nlmsg_put(skb, 0, msg->seq, NLMSG_DONE, size - sizeof(*nlh), 0); | 104 | nlh = nlmsg_put(skb, 0, msg->seq, NLMSG_DONE, size, 0); |
| 105 | if (!nlh) { | 105 | if (!nlh) { |
| 106 | kfree_skb(skb); | 106 | kfree_skb(skb); |
| 107 | return -EMSGSIZE; | 107 | return -EMSGSIZE; |
| @@ -124,7 +124,7 @@ static int cn_call_callback(struct sk_buff *skb) · 16 unmodified lines | |||
| 124 | { | 124 | { |
| 125 | struct cn_callback_entry *i, *cbq = NULL; | 125 | struct cn_callback_entry *i, *cbq = NULL; |
| 126 | struct cn_dev *dev = &cdev; | 126 | struct cn_dev *dev = &cdev; |
| 127 | struct cn_msg *msg = NLMSG_DATA(nlmsg_hdr(skb)); | 127 | struct cn_msg *msg = nlmsg_data(nlmsg_hdr(skb)); |
| 128 | struct netlink_skb_parms *nsp = &NETLINK_CB(skb); | 128 | struct netlink_skb_parms *nsp = &NETLINK_CB(skb); |
| 129 | int err = -ENODEV; | 129 | int err = -ENODEV; |
| 130 | 130 | ||
| @@ -162,7 +162,7 @@ static void cn_rx_skb(struct sk_buff *__skb) · 31 unmodified lines | |||
| 162 | 162 | ||
| 163 | skb = skb_get(__skb); | 163 | skb = skb_get(__skb); |
| 164 | 164 | ||
| 165 | if (skb->len >= NLMSG_SPACE(0)) { | 165 | if (skb->len >= NLMSG_HDRLEN) { |
| 166 | nlh = nlmsg_hdr(skb); | 166 | nlh = nlmsg_hdr(skb); |
| 167 | 167 | ||
| 168 | if (nlh->nlmsg_len < sizeof(struct cn_msg) || | 168 | if (nlh->nlmsg_len < sizeof(struct cn_msg) || |
| @@ -470,8 +470,10 @@ struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase) · 469 unmodified lines | |||
| 470 | } | 470 | } |
| 471 | 471 | ||
| 472 | if (!dca2_tag_map_valid(ioatdca->tag_map)) { | 472 | if (!dca2_tag_map_valid(ioatdca->tag_map)) { |
| 473 | dev_err(&pdev->dev, "APICID_TAG_MAP set incorrectly by BIOS, " | 473 | WARN_TAINT_ONCE(1, TAINT_FIRMWARE_WORKAROUND, |
| 474 | "disabling DCA\n"); | 474 | "%s %s: APICID_TAG_MAP set incorrectly by BIOS, disabling DCA\n", |
| 475 | dev_driver_string(&pdev->dev), | ||
| 476 | dev_name(&pdev->dev)); | ||
| 475 | free_dca_provider(dca); | 477 | free_dca_provider(dca); |
| 476 | return NULL; | 478 | return NULL; |
| 477 | } | 479 | } |
| @@ -689,7 +691,10 @@ struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase) · 211 unmodified lines | |||
| 689 | } | 691 | } |
| 690 | 692 | ||
| 691 | if (dca3_tag_map_invalid(ioatdca->tag_map)) { | 693 | if (dca3_tag_map_invalid(ioatdca->tag_map)) { |
| 692 | dev_err(&pdev->dev, "APICID_TAG_MAP set incorrectly by BIOS, disabling DCA\n"); | 694 | WARN_TAINT_ONCE(1, TAINT_FIRMWARE_WORKAROUND, |
| 695 | "%s %s: APICID_TAG_MAP set incorrectly by BIOS, disabling DCA\n", | ||
| 696 | dev_driver_string(&pdev->dev), | ||
| 697 | dev_name(&pdev->dev)); | ||
| 693 | free_dca_provider(dca); | 698 | free_dca_provider(dca); |
| 694 | return NULL; | 699 | return NULL; |
| 695 | } | 700 | } |
| @@ -47,9 +47,9 @@ config FIREWIRE_NET · 46 unmodified lines | |||
| 47 | tristate "IP networking over 1394" | 47 | tristate "IP networking over 1394" |
| 48 | depends on FIREWIRE && INET | 48 | depends on FIREWIRE && INET |
| 49 | help | 49 | help |
| 50 | This enables IPv4 over IEEE 1394, providing IP connectivity with | 50 | This enables IPv4/IPv6 over IEEE 1394, providing IP connectivity |
| 51 | other implementations of RFC 2734 as found on several operating | 51 | with other implementations of RFC 2734/3146 as found on several |
| 52 | systems. Multicast support is currently limited. | 52 | operating systems. Multicast support is currently limited. |
| 53 | 53 | ||
| 54 | To compile this driver as a module, say M here: The module will be | 54 | To compile this driver as a module, say M here: The module will be |
| 55 | called firewire-net. | 55 | called firewire-net. |
| @@ -1,5 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * IPv4 over IEEE 1394, per RFC 2734 | 2 | * IPv4 over IEEE 1394, per RFC 2734 |
| 3 | * IPv6 over IEEE 1394, per RFC 3146 | ||
| 3 | * | 4 | * |
| 4 | * Copyright (C) 2009 Jay Fenlason <fenlason@redhat.com> | 5 | * Copyright (C) 2009 Jay Fenlason <fenlason@redhat.com> |
| 5 | * | 6 | * |
| @@ -28,6 +29,7 @@ · 22 unmodified lines | |||
| 28 | 29 | ||
| 29 | #include <asm/unaligned.h> | 30 | #include <asm/unaligned.h> |
| 30 | #include <net/arp.h> | 31 | #include <net/arp.h> |
| 32 | #include <net/firewire.h> | ||
| 31 | 33 | ||
| 32 | /* rx limits */ | 34 | /* rx limits */ |
| 33 | #define FWNET_MAX_FRAGMENTS 30 /* arbitrary, > TX queue depth */ | 35 | #define FWNET_MAX_FRAGMENTS 30 /* arbitrary, > TX queue depth */ |
| @@ -45,6 +47,7 @@ · 11 unmodified lines | |||
| 45 | 47 | ||
| 46 | #define IANA_SPECIFIER_ID 0x00005eU | 48 | #define IANA_SPECIFIER_ID 0x00005eU |
| 47 | #define RFC2734_SW_VERSION 0x000001U | 49 | #define RFC2734_SW_VERSION 0x000001U |
| 50 | #define RFC3146_SW_VERSION 0x000002U | ||
| 48 | 51 | ||
| 49 | #define IEEE1394_GASP_HDR_SIZE 8 | 52 | #define IEEE1394_GASP_HDR_SIZE 8 |
| 50 | 53 | ||
| @@ -57,32 +60,10 @@ · 6 unmodified lines | |||
| 57 | #define RFC2374_HDR_LASTFRAG 2 /* last fragment */ | 60 | #define RFC2374_HDR_LASTFRAG 2 /* last fragment */ |
| 58 | #define RFC2374_HDR_INTFRAG 3 /* interior fragment */ | 61 | #define RFC2374_HDR_INTFRAG 3 /* interior fragment */ |
| 59 | 62 | ||
| 60 | #define RFC2734_HW_ADDR_LEN 16 | 63 | static bool fwnet_hwaddr_is_multicast(u8 *ha) |
| 61 | 64 | { | |
| 62 | struct rfc2734_arp { | 65 | return !!(*ha & 1); |
| 63 | __be16 hw_type; /* 0x0018 */ | 66 | } |
| 64 | __be16 proto_type; /* 0x0806 */ | ||
| 65 | u8 hw_addr_len; /* 16 */ | ||
| 66 | u8 ip_addr_len; /* 4 */ | ||
| 67 | __be16 opcode; /* ARP Opcode */ | ||
| 68 | /* Above is exactly the same format as struct arphdr */ | ||
| 69 | |||
| 70 | __be64 s_uniq_id; /* Sender's 64bit EUI */ | ||
| 71 | u8 max_rec; /* Sender's max packet size */ | ||
| 72 | u8 sspd; /* Sender's max speed */ | ||
| 73 | __be16 fifo_hi; /* hi 16bits of sender's FIFO addr */ | ||
| 74 | __be32 fifo_lo; /* lo 32bits of sender's FIFO addr */ | ||
| 75 | __be32 sip; /* Sender's IP Address */ | ||
| 76 | __be32 tip; /* IP Address of requested hw addr */ | ||
| 77 | } __packed; | ||
| 78 | |||
| 79 | /* This header format is specific to this driver implementation. */ | ||
| 80 | #define FWNET_ALEN 8 | ||
| 81 | #define FWNET_HLEN 10 | ||
| 82 | struct fwnet_header { | ||
| 83 | u8 h_dest[FWNET_ALEN]; /* destination address */ | ||
| 84 | __be16 h_proto; /* packet type ID field */ | ||
| 85 | } __packed; | ||
| 86 | 67 | ||
| 87 | /* IPv4 and IPv6 encapsulation header */ | 68 | /* IPv4 and IPv6 encapsulation header */ |
| 88 | struct rfc2734_header { | 69 | struct rfc2734_header { |
| @@ -191,8 +172,6 @@ struct fwnet_peer { · 102 unmodified lines | |||
| 191 | struct list_head peer_link; | 172 | struct list_head peer_link; |
| 192 | struct fwnet_device *dev; | 173 | struct fwnet_device *dev; |
| 193 | u64 guid; | 174 | u64 guid; |
| 194 | u64 fifo; | ||
| 195 | __be32 ip; | ||
| 196 | 175 | ||
| 197 | /* guarded by dev->lock */ | 176 | /* guarded by dev->lock */ |
| 198 | struct list_head pd_list; /* received partial datagrams */ | 177 | struct list_head pd_list; /* received partial datagrams */ |
| @@ -221,6 +200,15 @@ struct fwnet_packet_task { · 22 unmodified lines | |||
| 221 | u8 enqueued; | 200 | u8 enqueued; |
| 222 | }; | 201 | }; |
| 223 | 202 | ||
| 203 | /* | ||
| 204 | * Get fifo address embedded in hwaddr | ||
| 205 | */ | ||
| 206 | static __u64 fwnet_hwaddr_fifo(union fwnet_hwaddr *ha) | ||
| 207 | { | ||
| 208 | return (u64)get_unaligned_be16(&ha->uc.fifo_hi) << 32 | ||
| 209 | | get_unaligned_be32(&ha->uc.fifo_lo); | ||
| 210 | } | ||
| 211 | |||
| 224 | /* | 212 | /* |
| 225 | * saddr == NULL means use device source address. | 213 | * saddr == NULL means use device source address. |
| 226 | * daddr == NULL means leave destination address (eg unresolved arp). | 214 | * daddr == NULL means leave destination address (eg unresolved arp). |
| @@ -513,10 +501,20 @@ static int fwnet_finish_incoming_packet(struct net_device *net, · 286 unmodified lines | |||
| 513 | bool is_broadcast, u16 ether_type) | 501 | bool is_broadcast, u16 ether_type) |
| 514 | { | 502 | { |
| 515 | struct fwnet_device *dev; | 503 | struct fwnet_device *dev; |
| 516 | static const __be64 broadcast_hw = cpu_to_be64(~0ULL); | ||
| 517 | int status; | 504 | int status; |
| 518 | __be64 guid; | 505 | __be64 guid; |
| 519 | 506 | ||
| 507 | switch (ether_type) { | ||
| 508 | case ETH_P_ARP: | ||
| 509 | case ETH_P_IP: | ||
| 510 | #if IS_ENABLED(CONFIG_IPV6) | ||
| 511 | case ETH_P_IPV6: | ||
| 512 | #endif | ||
| 513 | break; | ||
| 514 | default: | ||
| 515 | goto err; | ||
| 516 | } | ||
| 517 | |||
| 520 | dev = netdev_priv(net); | 518 | dev = netdev_priv(net); |
| 521 | /* Write metadata, and then pass to the receive level */ | 519 | /* Write metadata, and then pass to the receive level */ |
| 522 | skb->dev = net; | 520 | skb->dev = net; |
| @@ -524,92 +522,11 @@ static int fwnet_finish_incoming_packet(struct net_device *net, · 1 unmodified line | |||
| 524 | 522 | ||
| 525 | /* | 523 | /* |
| 526 | * Parse the encapsulation header. This actually does the job of | 524 | * Parse the encapsulation header. This actually does the job of |
| 527 | * converting to an ethernet frame header, as well as arp | 525 | * converting to an ethernet-like pseudo frame header. |
| 528 | * conversion if needed. ARP conversion is easier in this | ||
| 529 | * direction, since we are using ethernet as our backend. | ||
| 530 | */ | 526 | */ |
| 531 | /* | ||
| 532 | * If this is an ARP packet, convert it. First, we want to make | ||
| 533 | * use of some of the fields, since they tell us a little bit | ||
| 534 | * about the sending machine. | ||
| 535 | */ | ||
| 536 | if (ether_type == ETH_P_ARP) { | ||
| 537 | struct rfc2734_arp *arp1394; | ||
| 538 | struct arphdr *arp; | ||
| 539 | unsigned char *arp_ptr; | ||
| 540 | u64 fifo_addr; | ||
| 541 | u64 peer_guid; | ||
| 542 | unsigned sspd; | ||
| 543 | u16 max_payload; | ||
| 544 | struct fwnet_peer *peer; | ||
| 545 | unsigned long flags; | ||
| 546 | |||
| 547 | arp1394 = (struct rfc2734_arp *)skb->data; | ||
| 548 | arp = (struct arphdr *)skb->data; | ||
| 549 | arp_ptr = (unsigned char *)(arp + 1); | ||
| 550 | peer_guid = get_unaligned_be64(&arp1394->s_uniq_id); | ||
| 551 | fifo_addr = (u64)get_unaligned_be16(&arp1394->fifo_hi) << 32 | ||
| 552 | | get_unaligned_be32(&arp1394->fifo_lo); | ||
| 553 | |||
| 554 | sspd = arp1394->sspd; | ||
| 555 | /* Sanity check. OS X 10.3 PPC reportedly sends 131. */ | ||
| 556 | if (sspd > SCODE_3200) { | ||
| 557 | dev_notice(&net->dev, "sspd %x out of range\n", sspd); | ||
| 558 | sspd = SCODE_3200; | ||
| 559 | } | ||
| 560 | max_payload = fwnet_max_payload(arp1394->max_rec, sspd); | ||
| 561 | |||
| 562 | spin_lock_irqsave(&dev->lock, flags); | ||
| 563 | peer = fwnet_peer_find_by_guid(dev, peer_guid); | ||
| 564 | if (peer) { | ||
| 565 | peer->fifo = fifo_addr; | ||
| 566 | |||
| 567 | if (peer->speed > sspd) | ||
| 568 | peer->speed = sspd; | ||
| 569 | if (peer->max_payload > max_payload) | ||
| 570 | peer->max_payload = max_payload; | ||
| 571 | |||
| 572 | peer->ip = arp1394->sip; | ||
| 573 | } | ||
| 574 | spin_unlock_irqrestore(&dev->lock, flags); | ||
| 575 | |||
| 576 | if (!peer) { | ||
| 577 | dev_notice(&net->dev, | ||
| 578 | "no peer for ARP packet from %016llx\n", | ||
| 579 | (unsigned long long)peer_guid); | ||
| 580 | goto no_peer; | ||
| 581 | } | ||
| 582 | |||
| 583 | /* | ||
| 584 | * Now that we're done with the 1394 specific stuff, we'll | ||
| 585 | * need to alter some of the data. Believe it or not, all | ||
| 586 | * that needs to be done is sender_IP_address needs to be | ||
| 587 | * moved, the destination hardware address get stuffed | ||
| 588 | * in and the hardware address length set to 8. | ||
| 589 | * | ||
| 590 | * IMPORTANT: The code below overwrites 1394 specific data | ||
| 591 | * needed above so keep the munging of the data for the | ||
| 592 | * higher level IP stack last. | ||
| 593 | */ | ||
| 594 | |||
| 595 | arp->ar_hln = 8; | ||
| 596 | /* skip over sender unique id */ | ||
| 597 | arp_ptr += arp->ar_hln; | ||
| 598 | /* move sender IP addr */ | ||
| 599 | put_unaligned(arp1394->sip, (u32 *)arp_ptr); | ||
| 600 | /* skip over sender IP addr */ | ||
| 601 | arp_ptr += arp->ar_pln; | ||
| 602 | |||
| 603 | if (arp->ar_op == htons(ARPOP_REQUEST)) | ||
| 604 | memset(arp_ptr, 0, sizeof(u64)); | ||
| 605 | else | ||
| 606 | memcpy(arp_ptr, net->dev_addr, sizeof(u64)); | ||
| 607 | } | ||
| 608 | |||
| 609 | /* Now add the ethernet header. */ | ||
| 610 | guid = cpu_to_be64(dev->card->guid); | 527 | guid = cpu_to_be64(dev->card->guid); |
| 611 | if (dev_hard_header(skb, net, ether_type, | 528 | if (dev_hard_header(skb, net, ether_type, |
| 612 | is_broadcast ? &broadcast_hw : &guid, | 529 | is_broadcast ? net->broadcast : net->dev_addr, |
| 613 | NULL, skb->len) >= 0) { | 530 | NULL, skb->len) >= 0) { |
| 614 | struct fwnet_header *eth; | 531 | struct fwnet_header *eth; |
| 615 | u16 *rawp; | 532 | u16 *rawp; |
| @@ -618,7 +535,7 @@ static int fwnet_finish_incoming_packet(struct net_device *net, · 2 unmodified lines | |||
| 618 | skb_reset_mac_header(skb); | 535 | skb_reset_mac_header(skb); |
| 619 | skb_pull(skb, sizeof(*eth)); | 536 | skb_pull(skb, sizeof(*eth)); |
| 620 | eth = (struct fwnet_header *)skb_mac_header(skb); | 537 | eth = (struct fwnet_header *)skb_mac_header(skb); |
| 621 | if (*eth->h_dest & 1) { | 538 | if (fwnet_hwaddr_is_multicast(eth->h_dest)) { |
| 622 | if (memcmp(eth->h_dest, net->broadcast, | 539 | if (memcmp(eth->h_dest, net->broadcast, |
| 623 | net->addr_len) == 0) | 540 | net->addr_len) == 0) |
| 624 | skb->pkt_type = PACKET_BROADCAST; | 541 | skb->pkt_type = PACKET_BROADCAST; |
| @@ -630,7 +547,7 @@ static int fwnet_finish_incoming_packet(struct net_device *net, · 5 unmodified lines | |||
| 630 | if (memcmp(eth->h_dest, net->dev_addr, net->addr_len)) | 547 | if (memcmp(eth->h_dest, net->dev_addr, net->addr_len)) |
| 631 | skb->pkt_type = PACKET_OTHERHOST; | 548 | skb->pkt_type = PACKET_OTHERHOST; |
| 632 | } | 549 | } |
| 633 | if (ntohs(eth->h_proto) >= 1536) { | 550 | if (ntohs(eth->h_proto) >= ETH_P_802_3_MIN) { |
| 634 | protocol = eth->h_proto; | 551 | protocol = eth->h_proto; |
| 635 | } else { | 552 | } else { |
| 636 | rawp = (u16 *)skb->data; | 553 | rawp = (u16 *)skb->data; |
| @@ -652,7 +569,7 @@ static int fwnet_finish_incoming_packet(struct net_device *net, · 15 unmodified lines | |||
| 652 | 569 | ||
| 653 | return 0; | 570 | return 0; |
| 654 | 571 | ||
| 655 | no_peer: | 572 | err: |
| 656 | net->stats.rx_errors++; | 573 | net->stats.rx_errors++; |
| 657 | net->stats.rx_dropped++; | 574 | net->stats.rx_dropped++; |
| 658 | 575 | ||
| @@ -856,7 +773,12 @@ static void fwnet_receive_broadcast(struct fw_iso_context *context, · 197 unmodified lines | |||
| 856 | ver = be32_to_cpu(buf_ptr[1]) & 0xffffff; | 773 | ver = be32_to_cpu(buf_ptr[1]) & 0xffffff; |
| 857 | source_node_id = be32_to_cpu(buf_ptr[0]) >> 16; | 774 | source_node_id = be32_to_cpu(buf_ptr[0]) >> 16; |
| 858 | 775 | ||
| 859 | if (specifier_id == IANA_SPECIFIER_ID && ver == RFC2734_SW_VERSION) { | 776 | if (specifier_id == IANA_SPECIFIER_ID && |
| 777 | (ver == RFC2734_SW_VERSION | ||
| 778 | #if IS_ENABLED(CONFIG_IPV6) | ||
| 779 | || ver == RFC3146_SW_VERSION | ||
| 780 | #endif | ||
| 781 | )) { | ||
| 860 | buf_ptr += 2; | 782 | buf_ptr += 2; |
| 861 | length -= IEEE1394_GASP_HDR_SIZE; | 783 | length -= IEEE1394_GASP_HDR_SIZE; |
| 862 | fwnet_incoming_packet(dev, buf_ptr, length, source_node_id, | 784 | fwnet_incoming_packet(dev, buf_ptr, length, source_node_id, |
| @@ -1059,16 +981,27 @@ static int fwnet_send_packet(struct fwnet_packet_task *ptask) · 196 unmodified lines | |||
| 1059 | u8 *p; | 981 | u8 *p; |
| 1060 | int generation; | 982 | int generation; |
| 1061 | int node_id; | 983 | int node_id; |
| 984 | unsigned int sw_version; | ||
| 1062 | 985 | ||
| 1063 | /* ptask->generation may not have been set yet */ | 986 | /* ptask->generation may not have been set yet */ |
| 1064 | generation = dev->card->generation; | 987 | generation = dev->card->generation; |
| 1065 | smp_rmb(); | 988 | smp_rmb(); |
| 1066 | node_id = dev->card->node_id; | 989 | node_id = dev->card->node_id; |
| 1067 | 990 | ||
| 991 | switch (ptask->skb->protocol) { | ||
| 992 | default: | ||
| 993 | sw_version = RFC2734_SW_VERSION; | ||
| 994 | break; | ||
| 995 | #if IS_ENABLED(CONFIG_IPV6) | ||
| 996 | case htons(ETH_P_IPV6): | ||
| 997 | sw_version = RFC3146_SW_VERSION; | ||
| 998 | #endif | ||
| 999 | } | ||
| 1000 | |||
| 1068 | p = skb_push(ptask->skb, IEEE1394_GASP_HDR_SIZE); | 1001 | p = skb_push(ptask->skb, IEEE1394_GASP_HDR_SIZE); |
| 1069 | put_unaligned_be32(node_id << 16 | IANA_SPECIFIER_ID >> 8, p); | 1002 | put_unaligned_be32(node_id << 16 | IANA_SPECIFIER_ID >> 8, p); |
| 1070 | put_unaligned_be32((IANA_SPECIFIER_ID & 0xff) << 24 | 1003 | put_unaligned_be32((IANA_SPECIFIER_ID & 0xff) << 24 |
| 1071 | | RFC2734_SW_VERSION, &p[4]); | 1004 | | sw_version, &p[4]); |
| 1072 | 1005 | ||
| 1073 | /* We should not transmit if broadcast_channel.valid == 0. */ | 1006 | /* We should not transmit if broadcast_channel.valid == 0. */ |
| 1074 | fw_send_request(dev->card, &ptask->transaction, | 1007 | fw_send_request(dev->card, &ptask->transaction, |
| @@ -1116,6 +1049,62 @@ static int fwnet_send_packet(struct fwnet_packet_task *ptask) · 41 unmodified lines | |||
| 1116 | return 0; | 1049 | return 0; |
| 1117 | } | 1050 | } |
| 1118 | 1051 | ||
| 1052 | static void fwnet_fifo_stop(struct fwnet_device *dev) | ||
| 1053 | { | ||
| 1054 | if (dev->local_fifo == FWNET_NO_FIFO_ADDR) | ||
| 1055 | return; | ||
| 1056 | |||
| 1057 | fw_core_remove_address_handler(&dev->handler); | ||
| 1058 | dev->local_fifo = FWNET_NO_FIFO_ADDR; | ||
| 1059 | } | ||
| 1060 | |||
| 1061 | static int fwnet_fifo_start(struct fwnet_device *dev) | ||
| 1062 | { | ||
| 1063 | int retval; | ||
| 1064 | |||
| 1065 | if (dev->local_fifo != FWNET_NO_FIFO_ADDR) | ||
| 1066 | return 0; | ||
| 1067 | |||
| 1068 | dev->handler.length = 4096; | ||
| 1069 | dev->handler.address_callback = fwnet_receive_packet; | ||
| 1070 | dev->handler.callback_data = dev; | ||
| 1071 | |||
| 1072 | retval = fw_core_add_address_handler(&dev->handler, | ||
| 1073 | &fw_high_memory_region); | ||
| 1074 | if (retval < 0) | ||
| 1075 | return retval; | ||
| 1076 | |||
| 1077 | dev->local_fifo = dev->handler.offset; | ||
| 1078 | |||
| 1079 | return 0; | ||
| 1080 | } | ||
| 1081 | |||
| 1082 | static void __fwnet_broadcast_stop(struct fwnet_device *dev) | ||
| 1083 | { | ||
| 1084 | unsigned u; | ||
| 1085 | |||
| 1086 | if (dev->broadcast_state != FWNET_BROADCAST_ERROR) { | ||
| 1087 | for (u = 0; u < FWNET_ISO_PAGE_COUNT; u++) | ||
| 1088 | kunmap(dev->broadcast_rcv_buffer.pages[u]); | ||
| 1089 | fw_iso_buffer_destroy(&dev->broadcast_rcv_buffer, dev->card); | ||
| 1090 | } | ||
| 1091 | if (dev->broadcast_rcv_context) { | ||
| 1092 | fw_iso_context_destroy(dev->broadcast_rcv_context); | ||
| 1093 | dev->broadcast_rcv_context = NULL; | ||
| 1094 | } | ||
| 1095 | kfree(dev->broadcast_rcv_buffer_ptrs); | ||
| 1096 | dev->broadcast_rcv_buffer_ptrs = NULL; | ||
| 1097 | dev->broadcast_state = FWNET_BROADCAST_ERROR; | ||
| 1098 | } | ||
| 1099 | |||
| 1100 | static void fwnet_broadcast_stop(struct fwnet_device *dev) | ||
| 1101 | { | ||
| 1102 | if (dev->broadcast_state == FWNET_BROADCAST_ERROR) | ||
| 1103 | return; | ||
| 1104 | fw_iso_context_stop(dev->broadcast_rcv_context); | ||
| 1105 | __fwnet_broadcast_stop(dev); | ||
| 1106 | } | ||
| 1107 | |||
| 1119 | static int fwnet_broadcast_start(struct fwnet_device *dev) | 1108 | static int fwnet_broadcast_start(struct fwnet_device *dev) |
| 1120 | { | 1109 | { |
| 1121 | struct fw_iso_context *context; | 1110 | struct fw_iso_context *context; |
| @@ -1124,60 +1113,47 @@ static int fwnet_broadcast_start(struct fwnet_device *dev) · 2 unmodified lines | |||
| 1124 | unsigned max_receive; | 1113 | unsigned max_receive; |
| 1125 | struct fw_iso_packet packet; | 1114 | struct fw_iso_packet packet; |
| 1126 | unsigned long offset; | 1115 | unsigned long offset; |
| 1116 | void **ptrptr; | ||
| 1127 | unsigned u; | 1117 | unsigned u; |
| 1128 | 1118 | ||
| 1129 | if (dev->local_fifo == FWNET_NO_FIFO_ADDR) { | 1119 | if (dev->broadcast_state != FWNET_BROADCAST_ERROR) |
| 1130 | dev->handler.length = 4096; | 1120 | return 0; |
| 1131 | dev->handler.address_callback = fwnet_receive_packet; | ||
| 1132 | dev->handler.callback_data = dev; | ||
| 1133 | |||
| 1134 | retval = fw_core_add_address_handler(&dev->handler, | ||
| 1135 | &fw_high_memory_region); | ||
| 1136 | if (retval < 0) | ||
| 1137 | goto failed_initial; | ||
| 1138 | |||
| 1139 | dev->local_fifo = dev->handler.offset; | ||
| 1140 | } | ||
| 1141 | 1121 | ||
| 1142 | max_receive = 1U << (dev->card->max_receive + 1); | 1122 | max_receive = 1U << (dev->card->max_receive + 1); |
| 1143 | num_packets = (FWNET_ISO_PAGE_COUNT * PAGE_SIZE) / max_receive; | 1123 | num_packets = (FWNET_ISO_PAGE_COUNT * PAGE_SIZE) / max_receive; |
| 1144 | 1124 | ||
| 1145 | if (!dev->broadcast_rcv_context) { | 1125 | ptrptr = kmalloc(sizeof(void *) * num_packets, GFP_KERNEL); |
| 1146 | void **ptrptr; | 1126 | if (!ptrptr) { |
| 1147 | 1127 | retval = -ENOMEM; | |
| 1148 | context = fw_iso_context_create(dev->card, | 1128 | goto failed; |
| 1149 | FW_ISO_CONTEXT_RECEIVE, IEEE1394_BROADCAST_CHANNEL, | 1129 | } |
| 1150 | dev->card->link_speed, 8, fwnet_receive_broadcast, dev); | 1130 | dev->broadcast_rcv_buffer_ptrs = ptrptr; |
| 1151 | if (IS_ERR(context)) { | 1131 | |
| 1152 | retval = PTR_ERR(context); | 1132 | context = fw_iso_context_create(dev->card, FW_ISO_CONTEXT_RECEIVE, |
| 1153 | goto failed_context_create; | 1133 | IEEE1394_BROADCAST_CHANNEL, |
| 1154 | } | 1134 | dev->card->link_speed, 8, |
| 1135 | fwnet_receive_broadcast, dev); | ||
| 1136 | if (IS_ERR(context)) { | ||
| 1137 | retval = PTR_ERR(context); | ||
| 1138 | goto failed; | ||
| 1139 | } | ||
| 1155 | 1140 | ||
| 1156 | retval = fw_iso_buffer_init(&dev->broadcast_rcv_buffer, | 1141 | retval = fw_iso_buffer_init(&dev->broadcast_rcv_buffer, dev->card, |
| 1157 | dev->card, FWNET_ISO_PAGE_COUNT, DMA_FROM_DEVICE); | 1142 | FWNET_ISO_PAGE_COUNT, DMA_FROM_DEVICE); |
| 1158 | if (retval < 0) | 1143 | if (retval < 0) |
| 1159 | goto failed_buffer_init; | 1144 | goto failed; |
| 1160 | 1145 | ||
| 1161 | ptrptr = kmalloc(sizeof(void *) * num_packets, GFP_KERNEL); | 1146 | dev->broadcast_state = FWNET_BROADCAST_STOPPED; |
| 1162 | if (!ptrptr) { | ||
| 1163 | retval = -ENOMEM; | ||
| 1164 | goto failed_ptrs_alloc; | ||
| 1165 | } | ||
| 1166 | 1147 | ||
| 1167 | dev->broadcast_rcv_buffer_ptrs = ptrptr; | 1148 | for (u = 0; u < FWNET_ISO_PAGE_COUNT; u++) { |
| 1168 | for (u = 0; u < FWNET_ISO_PAGE_COUNT; u++) { | 1149 | void *ptr; |
| 1169 | void *ptr; | 1150 | unsigned v; |
| 1170 | unsigned v; | ||
| 1171 | 1151 | ||
| 1172 | ptr = kmap(dev->broadcast_rcv_buffer.pages[u]); | 1152 | ptr = kmap(dev->broadcast_rcv_buffer.pages[u]); |
| 1173 | for (v = 0; v < num_packets / FWNET_ISO_PAGE_COUNT; v++) | 1153 | for (v = 0; v < num_packets / FWNET_ISO_PAGE_COUNT; v++) |
| 1174 | *ptrptr++ = (void *) | 1154 | *ptrptr++ = (void *) ((char *)ptr + v * max_receive); |
| 1175 | ((char *)ptr + v * max_receive); | ||
| 1176 | } | ||
| 1177 | dev->broadcast_rcv_context = context; | ||
| 1178 | } else { | ||
| 1179 | context = dev->broadcast_rcv_context; | ||
| 1180 | } | 1155 | } |
| 1156 | dev->broadcast_rcv_context = context; | ||
| 1181 | 1157 | ||
| 1182 | packet.payload_length = max_receive; | 1158 | packet.payload_length = max_receive; |
| 1183 | packet.interrupt = 1; | 1159 | packet.interrupt = 1; |
| @@ -1191,7 +1167,7 @@ static int fwnet_broadcast_start(struct fwnet_device *dev) · 7 unmodified lines | |||
| 1191 | retval = fw_iso_context_queue(context, &packet, | 1167 | retval = fw_iso_context_queue(context, &packet, |
| 1192 | &dev->broadcast_rcv_buffer, offset); | 1168 | &dev->broadcast_rcv_buffer, offset); |
| 1193 | if (retval < 0) | 1169 | if (retval < 0) |
| 1194 | goto failed_rcv_queue; | 1170 | goto failed; |
| 1195 | 1171 | ||
| 1196 | offset += max_receive; | 1172 | offset += max_receive; |
| 1197 | } | 1173 | } |
| @@ -1201,7 +1177,7 @@ static int fwnet_broadcast_start(struct fwnet_device *dev) · 3 unmodified lines | |||
| 1201 | retval = fw_iso_context_start(context, -1, 0, | 1177 | retval = fw_iso_context_start(context, -1, 0, |
| 1202 | FW_ISO_CONTEXT_MATCH_ALL_TAGS); /* ??? sync */ | 1178 | FW_ISO_CONTEXT_MATCH_ALL_TAGS); /* ??? sync */ |
| 1203 | if (retval < 0) | 1179 | if (retval < 0) |
| 1204 | goto failed_rcv_queue; | 1180 | goto failed; |
| 1205 | 1181 | ||
| 1206 | /* FIXME: adjust it according to the min. speed of all known peers? */ | 1182 | /* FIXME: adjust it according to the min. speed of all known peers? */ |
| 1207 | dev->broadcast_xmt_max_payload = IEEE1394_MAX_PAYLOAD_S100 | 1183 | dev->broadcast_xmt_max_payload = IEEE1394_MAX_PAYLOAD_S100 |
| @@ -1210,19 +1186,8 @@ static int fwnet_broadcast_start(struct fwnet_device *dev) · 2 unmodified lines | |||
| 1210 | 1186 | ||
| 1211 | return 0; | 1187 | return 0; |
| 1212 | 1188 | ||
| 1213 | failed_rcv_queue: | 1189 | failed: |
| 1214 | kfree(dev->broadcast_rcv_buffer_ptrs); | 1190 | __fwnet_broadcast_stop(dev); |
| 1215 | dev->broadcast_rcv_buffer_ptrs = NULL; | ||
| 1216 | failed_ptrs_alloc: | ||
| 1217 | fw_iso_buffer_destroy(&dev->broadcast_rcv_buffer, dev->card); | ||
| 1218 | failed_buffer_init: | ||
| 1219 | fw_iso_context_destroy(context); | ||
| 1220 | dev->broadcast_rcv_context = NULL; | ||
| 1221 | failed_context_create: | ||
| 1222 | fw_core_remove_address_handler(&dev->handler); | ||
| 1223 | failed_initial: | ||
| 1224 | dev->local_fifo = FWNET_NO_FIFO_ADDR; | ||
| 1225 | |||
| 1226 | return retval; | 1191 | return retval; |
| 1227 | } | 1192 | } |
| 1228 | 1193 | ||
| @@ -1240,11 +1205,10 @@ static int fwnet_open(struct net_device *net) · 11 unmodified lines | |||
| 1240 | struct fwnet_device *dev = netdev_priv(net); | 1205 | struct fwnet_device *dev = netdev_priv(net); |
| 1241 | int ret; | 1206 | int ret; |
| 1242 | 1207 | ||
| 1243 | if (dev->broadcast_state == FWNET_BROADCAST_ERROR) { | 1208 | ret = fwnet_broadcast_start(dev); |
| 1244 | ret = fwnet_broadcast_start(dev); | 1209 | if (ret) |
| 1245 | if (ret) | 1210 | return ret; |
| 1246 | return ret; | 1211 | |
| 1247 | } | ||
| 1248 | netif_start_queue(net); | 1212 | netif_start_queue(net); |
| 1249 | 1213 | ||
| 1250 | spin_lock_irq(&dev->lock); | 1214 | spin_lock_irq(&dev->lock); |
| @@ -1257,9 +1221,10 @@ static int fwnet_open(struct net_device *net) · 6 unmodified lines | |||
| 1257 | /* ifdown */ | 1221 | /* ifdown */ |
| 1258 | static int fwnet_stop(struct net_device *net) | 1222 | static int fwnet_stop(struct net_device *net) |
| 1259 | { | 1223 | { |
| 1260 | netif_stop_queue(net); | 1224 | struct fwnet_device *dev = netdev_priv(net); |
| 1261 | 1225 | ||
| 1262 | /* Deallocate iso context for use by other applications? */ | 1226 | netif_stop_queue(net); |
| 1227 | fwnet_broadcast_stop(dev); | ||
| 1263 | 1228 | ||
| 1264 | return 0; | 1229 | return 0; |
| 1265 | } | 1230 | } |
| @@ -1299,19 +1264,27 @@ static netdev_tx_t fwnet_tx(struct sk_buff *skb, struct net_device *net) · 33 unmodified lines | |||
| 1299 | * We might need to rebuild the header on tx failure. | 1264 | * We might need to rebuild the header on tx failure. |
| 1300 | */ | 1265 | */ |
| 1301 | memcpy(&hdr_buf, skb->data, sizeof(hdr_buf)); | 1266 | memcpy(&hdr_buf, skb->data, sizeof(hdr_buf)); |
| 1302 | skb_pull(skb, sizeof(hdr_buf)); | ||
| 1303 | |||
| 1304 | proto = hdr_buf.h_proto; | 1267 | proto = hdr_buf.h_proto; |
| 1268 | |||
| 1269 | switch (proto) { | ||
| 1270 | case htons(ETH_P_ARP): | ||
| 1271 | case htons(ETH_P_IP): | ||
| 1272 | #if IS_ENABLED(CONFIG_IPV6) | ||
| 1273 | case htons(ETH_P_IPV6): | ||
| 1274 | #endif | ||
| 1275 | break; | ||
| 1276 | default: | ||
| 1277 | goto fail; | ||
| 1278 | } | ||
| 1279 | |||
| 1280 | skb_pull(skb, sizeof(hdr_buf)); | ||
| 1305 | dg_size = skb->len; | 1281 | dg_size = skb->len; |
| 1306 | 1282 | ||
| 1307 | /* | 1283 | /* |
| 1308 | * Set the transmission type for the packet. ARP packets and IP | 1284 | * Set the transmission type for the packet. ARP packets and IP |
| 1309 | * broadcast packets are sent via GASP. | 1285 | * broadcast packets are sent via GASP. |
| 1310 | */ | 1286 | */ |
| 1311 | if (memcmp(hdr_buf.h_dest, net->broadcast, FWNET_ALEN) == 0 | 1287 | if (fwnet_hwaddr_is_multicast(hdr_buf.h_dest)) { |
| 1312 | || proto == htons(ETH_P_ARP) | ||
| 1313 | || (proto == htons(ETH_P_IP) | ||
| 1314 | && IN_MULTICAST(ntohl(ip_hdr(skb)->daddr)))) { | ||
| 1315 | max_payload = dev->broadcast_xmt_max_payload; | 1288 | max_payload = dev->broadcast_xmt_max_payload; |
| 1316 | datagram_label_ptr = &dev->broadcast_xmt_datagramlabel; | 1289 | datagram_label_ptr = &dev->broadcast_xmt_datagramlabel; |
| 1317 | 1290 | ||
| @@ -1320,11 +1293,12 @@ static netdev_tx_t fwnet_tx(struct sk_buff *skb, struct net_device *net) · 2 unmodified lines | |||
| 1320 | ptask->dest_node = IEEE1394_ALL_NODES; | 1293 | ptask->dest_node = IEEE1394_ALL_NODES; |
| 1321 | ptask->speed = SCODE_100; | 1294 | ptask->speed = SCODE_100; |
| 1322 | } else { | 1295 | } else { |
| 1323 | __be64 guid = get_unaligned((__be64 *)hdr_buf.h_dest); | 1296 | union fwnet_hwaddr *ha = (union fwnet_hwaddr *)hdr_buf.h_dest; |
| 1297 | __be64 guid = get_unaligned(&ha->uc.uniq_id); | ||
| 1324 | u8 generation; | 1298 | u8 generation; |
| 1325 | 1299 | ||
| 1326 | peer = fwnet_peer_find_by_guid(dev, be64_to_cpu(guid)); | 1300 | peer = fwnet_peer_find_by_guid(dev, be64_to_cpu(guid)); |
| 1327 | if (!peer || peer->fifo == FWNET_NO_FIFO_ADDR) | 1301 | if (!peer) |
| 1328 | goto fail; | 1302 | goto fail; |
| 1329 | 1303 | ||
| 1330 | generation = peer->generation; | 1304 | generation = peer->generation; |
| @@ -1332,32 +1306,12 @@ static netdev_tx_t fwnet_tx(struct sk_buff *skb, struct net_device *net) · 1 unmodified line | |||
| 1332 | max_payload = peer->max_payload; | 1306 | max_payload = peer->max_payload; |
| 1333 | datagram_label_ptr = &peer->datagram_label; | 1307 | datagram_label_ptr = &peer->datagram_label; |
| 1334 | 1308 | ||
| 1335 | ptask->fifo_addr = peer->fifo; | 1309 | ptask->fifo_addr = fwnet_hwaddr_fifo(ha); |
| 1336 | ptask->generation = generation; | 1310 | ptask->generation = generation; |
| 1337 | ptask->dest_node = dest_node; | 1311 | ptask->dest_node = dest_node; |
| 1338 | ptask->speed = peer->speed; | 1312 | ptask->speed = peer->speed; |
| 1339 | } | 1313 | } |
| 1340 | 1314 | ||
| 1341 | /* If this is an ARP packet, convert it */ | ||
| 1342 | if (proto == htons(ETH_P_ARP)) { | ||
| 1343 | struct arphdr *arp = (struct arphdr *)skb->data; | ||
| 1344 | unsigned char *arp_ptr = (unsigned char *)(arp + 1); | ||
| 1345 | struct rfc2734_arp *arp1394 = (struct rfc2734_arp *)skb->data; | ||
| 1346 | __be32 ipaddr; | ||
| 1347 | |||
| 1348 | ipaddr = get_unaligned((__be32 *)(arp_ptr + FWNET_ALEN)); | ||
| 1349 | |||
| 1350 | arp1394->hw_addr_len = RFC2734_HW_ADDR_LEN; | ||
| 1351 | arp1394->max_rec = dev->card->max_receive; | ||
| 1352 | arp1394->sspd = dev->card->link_speed; | ||
| 1353 | |||
| 1354 | put_unaligned_be16(dev->local_fifo >> 32, | ||
| 1355 | &arp1394->fifo_hi); | ||
| 1356 | put_unaligned_be32(dev->local_fifo & 0xffffffff, | ||
| 1357 | &arp1394->fifo_lo); | ||
| 1358 | put_unaligned(ipaddr, &arp1394->sip); | ||
| 1359 | } | ||
| 1360 | |||
| 1361 | ptask->hdr.w0 = 0; | 1315 | ptask->hdr.w0 = 0; |
| 1362 | ptask->hdr.w1 = 0; | 1316 | ptask->hdr.w1 = 0; |
| 1363 | ptask->skb = skb; | 1317 | ptask->skb = skb; |
| @@ -1472,8 +1426,6 @@ static int fwnet_add_peer(struct fwnet_device *dev, · 108 unmodified lines | |||
| 1472 | 1426 | ||
| 1473 | peer->dev = dev; | 1427 | peer->dev = dev; |
| 1474 | peer->guid = (u64)device->config_rom[3] << 32 | device->config_rom[4]; | 1428 | peer->guid = (u64)device->config_rom[3] << 32 | device->config_rom[4]; |
| 1475 | peer->fifo = FWNET_NO_FIFO_ADDR; | ||
| 1476 | peer->ip = 0; | ||
| 1477 | INIT_LIST_HEAD(&peer->pd_list); | 1429 | INIT_LIST_HEAD(&peer->pd_list); |
| 1478 | peer->pdg_size = 0; | 1430 | peer->pdg_size = 0; |
| 1479 | peer->datagram_label = 0; | 1431 | peer->datagram_label = 0; |
| @@ -1503,6 +1455,7 @@ static int fwnet_probe(struct device *_dev) · 23 unmodified lines | |||
| 1503 | struct fwnet_device *dev; | 1455 | struct fwnet_device *dev; |
| 1504 | unsigned max_mtu; | 1456 | unsigned max_mtu; |
| 1505 | int ret; | 1457 | int ret; |
| 1458 | union fwnet_hwaddr *ha; | ||
| 1506 | 1459 | ||
| 1507 | mutex_lock(&fwnet_device_mutex); | 1460 | mutex_lock(&fwnet_device_mutex); |
| 1508 | 1461 | ||
| @@ -1533,6 +1486,11 @@ static int fwnet_probe(struct device *_dev) · 24 unmodified lines | |||
| 1533 | dev->card = card; | 1486 | dev->card = card; |
| 1534 | dev->netdev = net; | 1487 | dev->netdev = net; |
| 1535 | 1488 | ||
| 1489 | ret = fwnet_fifo_start(dev); | ||
| 1490 | if (ret < 0) | ||
| 1491 | goto out; | ||
| 1492 | dev->local_fifo = dev->handler.offset; | ||
| 1493 | |||
| 1536 | /* | 1494 | /* |
| 1537 | * Use the RFC 2734 default 1500 octets or the maximum payload | 1495 | * Use the RFC 2734 default 1500 octets or the maximum payload |
| 1538 | * as initial MTU | 1496 | * as initial MTU |
| @@ -1542,24 +1500,31 @@ static int fwnet_probe(struct device *_dev) · 3 unmodified lines | |||
| 1542 | net->mtu = min(1500U, max_mtu); | 1500 | net->mtu = min(1500U, max_mtu); |
| 1543 | 1501 | ||
| 1544 | /* Set our hardware address while we're at it */ | 1502 | /* Set our hardware address while we're at it */ |
| 1545 | put_unaligned_be64(card->guid, net->dev_addr); | 1503 | ha = (union fwnet_hwaddr *)net->dev_addr; |
| 1546 | put_unaligned_be64(~0ULL, net->broadcast); | 1504 | put_unaligned_be64(card->guid, &ha->uc.uniq_id); |
| 1505 | ha->uc.max_rec = dev->card->max_receive; | ||
| 1506 | ha->uc.sspd = dev->card->link_speed; | ||
| 1507 | put_unaligned_be16(dev->local_fifo >> 32, &ha->uc.fifo_hi); | ||
| 1508 | put_unaligned_be32(dev->local_fifo & 0xffffffff, &ha->uc.fifo_lo); | ||
| 1509 | |||
| 1510 | memset(net->broadcast, -1, net->addr_len); | ||
| 1511 | |||
| 1547 | ret = register_netdev(net); | 1512 | ret = register_netdev(net); |
| 1548 | if (ret) | 1513 | if (ret) |
| 1549 | goto out; | 1514 | goto out; |
| 1550 | 1515 | ||
| 1551 | list_add_tail(&dev->dev_link, &fwnet_device_list); | 1516 | list_add_tail(&dev->dev_link, &fwnet_device_list); |
| 1552 | dev_notice(&net->dev, "IPv4 over IEEE 1394 on card %s\n", | 1517 | dev_notice(&net->dev, "IP over IEEE 1394 on card %s\n", |
| 1553 | dev_name(card->device)); | 1518 | dev_name(card->device)); |
| 1554 | have_dev: | 1519 | have_dev: |
| 1555 | ret = fwnet_add_peer(dev, unit, device); | 1520 | ret = fwnet_add_peer(dev, unit, device); |
| 1556 | if (ret && allocated_netdev) { | 1521 | if (ret && allocated_netdev) { |
| 1557 | unregister_netdev(net); | 1522 | unregister_netdev(net); |
| 1558 | list_del(&dev->dev_link); | 1523 | list_del(&dev->dev_link); |
| 1559 | } | ||
| 1560 | out: | 1524 | out: |
| 1561 | if (ret && allocated_netdev) | 1525 | fwnet_fifo_stop(dev); |
| 1562 | free_netdev(net); | 1526 | free_netdev(net); |
| 1527 | } | ||
| 1563 | 1528 | ||
| 1564 | mutex_unlock(&fwnet_device_mutex); | 1529 | mutex_unlock(&fwnet_device_mutex); |
| 1565 | 1530 | ||
| @@ -1592,22 +1557,14 @@ static int fwnet_remove(struct device *_dev) · 26 unmodified lines | |||
| 1592 | mutex_lock(&fwnet_device_mutex); | 1557 | mutex_lock(&fwnet_device_mutex); |
| 1593 | 1558 | ||
| 1594 | net = dev->netdev; | 1559 | net = dev->netdev; |
| 1595 | if (net && peer->ip) | ||
| 1596 | arp_invalidate(net, peer->ip); | ||
| 1597 | 1560 | ||
| 1598 | fwnet_remove_peer(peer, dev); | 1561 | fwnet_remove_peer(peer, dev); |
| 1599 | 1562 | ||
| 1600 | if (list_empty(&dev->peer_list)) { | 1563 | if (list_empty(&dev->peer_list)) { |
| 1601 | unregister_netdev(net); | 1564 | unregister_netdev(net); |
| 1602 | 1565 | ||
| 1603 | if (dev->local_fifo != FWNET_NO_FIFO_ADDR) | 1566 | fwnet_fifo_stop(dev); |
| 1604 | fw_core_remove_address_handler(&dev->handler); | 1567 | |
| 1605 | if (dev->broadcast_rcv_context) { | ||
| 1606 | fw_iso_context_stop(dev->broadcast_rcv_context); | ||
| 1607 | fw_iso_buffer_destroy(&dev->broadcast_rcv_buffer, | ||
| 1608 | dev->card); | ||
| 1609 | fw_iso_context_destroy(dev->broadcast_rcv_context); | ||
| 1610 | } | ||
| 1611 | for (i = 0; dev->queued_datagrams && i < 5; i++) | 1568 | for (i = 0; dev->queued_datagrams && i < 5; i++) |
| 1612 | ssleep(1); | 1569 | ssleep(1); |
| 1613 | WARN_ON(dev->queued_datagrams); | 1570 | WARN_ON(dev->queued_datagrams); |
| @@ -1646,6 +1603,14 @@ static const struct ieee1394_device_id fwnet_id_table[] = { · 32 unmodified lines | |||
| 1646 | .specifier_id = IANA_SPECIFIER_ID, | 1603 | .specifier_id = IANA_SPECIFIER_ID, |
| 1647 | .version = RFC2734_SW_VERSION, | 1604 | .version = RFC2734_SW_VERSION, |
| 1648 | }, | 1605 | }, |
| 1606 | #if IS_ENABLED(CONFIG_IPV6) | ||
| 1607 | { | ||
| 1608 | .match_flags = IEEE1394_MATCH_SPECIFIER_ID | | ||
| 1609 | IEEE1394_MATCH_VERSION, | ||
| 1610 | .specifier_id = IANA_SPECIFIER_ID, | ||
| 1611 | .version = RFC3146_SW_VERSION, | ||
| 1612 | }, | ||
| 1613 | #endif | ||
| 1649 | { } | 1614 | { } |
| 1650 | }; | 1615 | }; |
| 1651 | 1616 | ||
| @@ -1683,6 +1648,30 @@ static struct fw_descriptor rfc2374_unit_directory = { · 31 unmodified lines | |||
| 1683 | .data = rfc2374_unit_directory_data | 1648 | .data = rfc2374_unit_directory_data |
| 1684 | }; | 1649 | }; |
| 1685 | 1650 | ||
| 1651 | #if IS_ENABLED(CONFIG_IPV6) | ||
| 1652 | static const u32 rfc3146_unit_directory_data[] = { | ||
| 1653 | 0x00040000, /* directory_length */ | ||
| 1654 | 0x1200005e, /* unit_specifier_id: IANA */ | ||
| 1655 | 0x81000003, /* textual descriptor offset */ | ||
| 1656 | 0x13000002, /* unit_sw_version: RFC 3146 */ | ||
| 1657 | 0x81000005, /* textual descriptor offset */ | ||
| 1658 | 0x00030000, /* descriptor_length */ | ||
| 1659 | 0x00000000, /* text */ | ||
| 1660 | 0x00000000, /* minimal ASCII, en */ | ||
| 1661 | 0x49414e41, /* I A N A */ | ||
| 1662 | 0x00030000, /* descriptor_length */ | ||
| 1663 | 0x00000000, /* text */ | ||
| 1664 | 0x00000000, /* minimal ASCII, en */ | ||
| 1665 | 0x49507636, /* I P v 6 */ | ||
| 1666 | }; | ||
| 1667 | |||
| 1668 | static struct fw_descriptor rfc3146_unit_directory = { | ||
| 1669 | .length = ARRAY_SIZE(rfc3146_unit_directory_data), | ||
| 1670 | .key = (CSR_DIRECTORY | CSR_UNIT) << 24, | ||
| 1671 | .data = rfc3146_unit_directory_data | ||
| 1672 | }; | ||
| 1673 | #endif | ||
| 1674 | |||
| 1686 | static int __init fwnet_init(void) | 1675 | static int __init fwnet_init(void) |
| 1687 | { | 1676 | { |
| 1688 | int err; | 1677 | int err; |
| @@ -1691,11 +1680,17 @@ static int __init fwnet_init(void) · 2 unmodified lines | |||
| 1691 | if (err) | 1680 | if (err) |
| 1692 | return err; | 1681 | return err; |
| 1693 | 1682 | ||
| 1683 | #if IS_ENABLED(CONFIG_IPV6) | ||
| 1684 | err = fw_core_add_descriptor(&rfc3146_unit_directory); | ||
| 1685 | if (err) | ||
| 1686 | goto out; | ||
| 1687 | #endif | ||
| 1688 | |||
| 1694 | fwnet_packet_task_cache = kmem_cache_create("packet_task", | 1689 | fwnet_packet_task_cache = kmem_cache_create("packet_task", |
| 1695 | sizeof(struct fwnet_packet_task), 0, 0, NULL); | 1690 | sizeof(struct fwnet_packet_task), 0, 0, NULL); |
| 1696 | if (!fwnet_packet_task_cache) { | 1691 | if (!fwnet_packet_task_cache) { |
| 1697 | err = -ENOMEM; | 1692 | err = -ENOMEM; |
| 1698 | goto out; | 1693 | goto out2; |
| 1699 | } | 1694 | } |
| 1700 | 1695 | ||
| 1701 | err = driver_register(&fwnet_driver.driver); | 1696 | err = driver_register(&fwnet_driver.driver); |
| @@ -1703,7 +1698,11 @@ static int __init fwnet_init(void) · 1 unmodified line | |||
| 1703 | return 0; | 1698 | return 0; |
| 1704 | 1699 | ||
| 1705 | kmem_cache_destroy(fwnet_packet_task_cache); | 1700 | kmem_cache_destroy(fwnet_packet_task_cache); |
| 1701 | out2: | ||
| 1702 | #if IS_ENABLED(CONFIG_IPV6) | ||
| 1703 | fw_core_remove_descriptor(&rfc3146_unit_directory); | ||
| 1706 | out: | 1704 | out: |
| 1705 | #endif | ||
| 1707 | fw_core_remove_descriptor(&rfc2374_unit_directory); | 1706 | fw_core_remove_descriptor(&rfc2374_unit_directory); |
| 1708 | 1707 | ||
| 1709 | return err; | 1708 | return err; |
| @@ -1714,11 +1713,14 @@ static void __exit fwnet_cleanup(void) · 4 unmodified lines | |||
| 1714 | { | 1713 | { |
| 1715 | driver_unregister(&fwnet_driver.driver); | 1714 | driver_unregister(&fwnet_driver.driver); |
| 1716 | kmem_cache_destroy(fwnet_packet_task_cache); | 1715 | kmem_cache_destroy(fwnet_packet_task_cache); |
| 1716 | #if IS_ENABLED(CONFIG_IPV6) | ||
| 1717 | fw_core_remove_descriptor(&rfc3146_unit_directory); | ||
| 1718 | #endif | ||
| 1717 | fw_core_remove_descriptor(&rfc2374_unit_directory); | 1719 | fw_core_remove_descriptor(&rfc2374_unit_directory); |
| 1718 | } | 1720 | } |
| 1719 | module_exit(fwnet_cleanup); | 1721 | module_exit(fwnet_cleanup); |
| 1720 | 1722 | ||
| 1721 | MODULE_AUTHOR("Jay Fenlason <fenlason@redhat.com>"); | 1723 | MODULE_AUTHOR("Jay Fenlason <fenlason@redhat.com>"); |
| 1722 | MODULE_DESCRIPTION("IPv4 over IEEE1394 as per RFC 2734"); | 1724 | MODULE_DESCRIPTION("IP over IEEE1394 as per RFC 2734/3146"); |
| 1723 | MODULE_LICENSE("GPL"); | 1725 | MODULE_LICENSE("GPL"); |
| 1724 | MODULE_DEVICE_TABLE(ieee1394, fwnet_id_table); | 1726 | MODULE_DEVICE_TABLE(ieee1394, fwnet_id_table); |
| @@ -511,12 +511,16 @@ static unsigned int select_ntuple(struct c4iw_dev *dev, struct dst_entry *dst, · 510 unmodified lines | |||
| 511 | static int send_connect(struct c4iw_ep *ep) | 511 | static int send_connect(struct c4iw_ep *ep) |
| 512 | { | 512 | { |
| 513 | struct cpl_act_open_req *req; | 513 | struct cpl_act_open_req *req; |
| 514 | struct cpl_t5_act_open_req *t5_req; | ||
| 514 | struct sk_buff *skb; | 515 | struct sk_buff *skb; |
| 515 | u64 opt0; | 516 | u64 opt0; |
| 516 | u32 opt2; | 517 | u32 opt2; |
| 517 | unsigned int mtu_idx; | 518 | unsigned int mtu_idx; |
| 518 | int wscale; | 519 | int wscale; |
| 519 | int wrlen = roundup(sizeof *req, 16); | 520 | int size = is_t4(ep->com.dev->rdev.lldi.adapter_type) ? |
| 521 | sizeof(struct cpl_act_open_req) : | ||
| 522 | sizeof(struct cpl_t5_act_open_req); | ||
| 523 | int wrlen = roundup(size, 16); | ||
| 520 | 524 | ||
| 521 | PDBG("%s ep %p atid %u\n", __func__, ep, ep->atid); | 525 | PDBG("%s ep %p atid %u\n", __func__, ep, ep->atid); |
| 522 | 526 | ||
| @@ -552,17 +556,36 @@ static int send_connect(struct c4iw_ep *ep) · 29 unmodified lines | |||
| 552 | opt2 |= WND_SCALE_EN(1); | 556 | opt2 |= WND_SCALE_EN(1); |
| 553 | t4_set_arp_err_handler(skb, NULL, act_open_req_arp_failure); | 557 | t4_set_arp_err_handler(skb, NULL, act_open_req_arp_failure); |
| 554 | 558 | ||
| 555 | req = (struct cpl_act_open_req *) skb_put(skb, wrlen); | 559 | if (is_t4(ep->com.dev->rdev.lldi.adapter_type)) { |
| 556 | INIT_TP_WR(req, 0); | 560 | req = (struct cpl_act_open_req *) skb_put(skb, wrlen); |
| 557 | OPCODE_TID(req) = cpu_to_be32( | 561 | INIT_TP_WR(req, 0); |
| 558 | MK_OPCODE_TID(CPL_ACT_OPEN_REQ, ((ep->rss_qid<<14)|ep->atid))); | 562 | OPCODE_TID(req) = cpu_to_be32( |
| 559 | req->local_port = ep->com.local_addr.sin_port; | 563 | MK_OPCODE_TID(CPL_ACT_OPEN_REQ, |
| 560 | req->peer_port = ep->com.remote_addr.sin_port; | 564 | ((ep->rss_qid << 14) | ep->atid))); |
| 561 | req->local_ip = ep->com.local_addr.sin_addr.s_addr; | 565 | req->local_port = ep->com.local_addr.sin_port; |
| 562 | req->peer_ip = ep->com.remote_addr.sin_addr.s_addr; | 566 | req->peer_port = ep->com.remote_addr.sin_port; |
| 563 | req->opt0 = cpu_to_be64(opt0); | 567 | req->local_ip = ep->com.local_addr.sin_addr.s_addr; |
| 564 | req->params = cpu_to_be32(select_ntuple(ep->com.dev, ep->dst, ep->l2t)); | 568 | req->peer_ip = ep->com.remote_addr.sin_addr.s_addr; |
| 565 | req->opt2 = cpu_to_be32(opt2); | 569 | req->opt0 = cpu_to_be64(opt0); |
| 570 | req->params = cpu_to_be32(select_ntuple(ep->com.dev, | ||
| 571 | ep->dst, ep->l2t)); | ||
| 572 | req->opt2 = cpu_to_be32(opt2); | ||
| 573 | } else { | ||
| 574 | t5_req = (struct cpl_t5_act_open_req *) skb_put(skb, wrlen); | ||
| 575 | INIT_TP_WR(t5_req, 0); | ||
| 576 | OPCODE_TID(t5_req) = cpu_to_be32( | ||
| 577 | MK_OPCODE_TID(CPL_ACT_OPEN_REQ, | ||
| 578 | ((ep->rss_qid << 14) | ep->atid))); | ||
| 579 | t5_req->local_port = ep->com.local_addr.sin_port; | ||
| 580 | t5_req->peer_port = ep->com.remote_addr.sin_port; | ||
| 581 | t5_req->local_ip = ep->com.local_addr.sin_addr.s_addr; | ||
| 582 | t5_req->peer_ip = ep->com.remote_addr.sin_addr.s_addr; | ||
| 583 | t5_req->opt0 = cpu_to_be64(opt0); | ||
| 584 | t5_req->params = cpu_to_be64(V_FILTER_TUPLE( | ||
| 585 | select_ntuple(ep->com.dev, ep->dst, ep->l2t))); | ||
| 586 | t5_req->opt2 = cpu_to_be32(opt2); | ||
| 587 | } | ||
| 588 | |||
| 566 | set_bit(ACT_OPEN_REQ, &ep->com.history); | 589 | set_bit(ACT_OPEN_REQ, &ep->com.history); |
| 567 | return c4iw_l2t_send(&ep->com.dev->rdev, skb, ep->l2t); | 590 | return c4iw_l2t_send(&ep->com.dev->rdev, skb, ep->l2t); |
| 568 | } | 591 | } |
| @@ -1676,9 +1699,9 @@ static int act_open_rpl(struct c4iw_dev *dev, struct sk_buff *skb) · 1107 unmodified lines | |||
| 1676 | case CPL_ERR_CONN_TIMEDOUT: | 1699 | case CPL_ERR_CONN_TIMEDOUT: |
| 1677 | break; | 1700 | break; |
| 1678 | case CPL_ERR_TCAM_FULL: | 1701 | case CPL_ERR_TCAM_FULL: |
| 1702 | dev->rdev.stats.tcam_full++; | ||
| 1679 | if (dev->rdev.lldi.enable_fw_ofld_conn) { | 1703 | if (dev->rdev.lldi.enable_fw_ofld_conn) { |
| 1680 | mutex_lock(&dev->rdev.stats.lock); | 1704 | mutex_lock(&dev->rdev.stats.lock); |
| 1681 | dev->rdev.stats.tcam_full++; | ||
| 1682 | mutex_unlock(&dev->rdev.stats.lock); | 1705 | mutex_unlock(&dev->rdev.stats.lock); |
| 1683 | send_fw_act_open_req(ep, | 1706 | send_fw_act_open_req(ep, |
| 1684 | GET_TID_TID(GET_AOPEN_ATID( | 1707 | GET_TID_TID(GET_AOPEN_ATID( |
| @@ -2875,12 +2898,14 @@ static int deferred_fw6_msg(struct c4iw_dev *dev, struct sk_buff *skb) · 1190 unmodified lines | |||
| 2875 | static void build_cpl_pass_accept_req(struct sk_buff *skb, int stid , u8 tos) | 2898 | static void build_cpl_pass_accept_req(struct sk_buff *skb, int stid , u8 tos) |
| 2876 | { | 2899 | { |
| 2877 | u32 l2info; | 2900 | u32 l2info; |
| 2878 | u16 vlantag, len, hdr_len; | 2901 | u16 vlantag, len, hdr_len, eth_hdr_len; |
| 2879 | u8 intf; | 2902 | u8 intf; |
| 2880 | struct cpl_rx_pkt *cpl = cplhdr(skb); | 2903 | struct cpl_rx_pkt *cpl = cplhdr(skb); |
| 2881 | struct cpl_pass_accept_req *req; | 2904 | struct cpl_pass_accept_req *req; |
| 2882 | struct tcp_options_received tmp_opt; | 2905 | struct tcp_options_received tmp_opt; |
| 2906 | struct c4iw_dev *dev; | ||
| 2883 | 2907 | ||
| 2908 | dev = *((struct c4iw_dev **) (skb->cb + sizeof(void *))); | ||
| 2884 | /* Store values from cpl_rx_pkt in temporary location. */ | 2909 | /* Store values from cpl_rx_pkt in temporary location. */ |
| 2885 | vlantag = (__force u16) cpl->vlan; | 2910 | vlantag = (__force u16) cpl->vlan; |
| 2886 | len = (__force u16) cpl->len; | 2911 | len = (__force u16) cpl->len; |
| @@ -2896,7 +2921,7 @@ static void build_cpl_pass_accept_req(struct sk_buff *skb, int stid , u8 tos) · 9 unmodified lines | |||
| 2896 | */ | 2921 | */ |
| 2897 | memset(&tmp_opt, 0, sizeof(tmp_opt)); | 2922 | memset(&tmp_opt, 0, sizeof(tmp_opt)); |
| 2898 | tcp_clear_options(&tmp_opt); | 2923 | tcp_clear_options(&tmp_opt); |
| 2899 | tcp_parse_options(skb, &tmp_opt, NULL, 0, NULL); | 2924 | tcp_parse_options(skb, &tmp_opt, 0, NULL); |
| 2900 | 2925 | ||
| 2901 | req = (struct cpl_pass_accept_req *)__skb_push(skb, sizeof(*req)); | 2926 | req = (struct cpl_pass_accept_req *)__skb_push(skb, sizeof(*req)); |
| 2902 | memset(req, 0, sizeof(*req)); | 2927 | memset(req, 0, sizeof(*req)); |
| @@ -2904,14 +2929,16 @@ static void build_cpl_pass_accept_req(struct sk_buff *skb, int stid , u8 tos) · 1 unmodified line | |||
| 2904 | V_SYN_MAC_IDX(G_RX_MACIDX( | 2929 | V_SYN_MAC_IDX(G_RX_MACIDX( |
| 2905 | (__force int) htonl(l2info))) | | 2930 | (__force int) htonl(l2info))) | |
| 2906 | F_SYN_XACT_MATCH); | 2931 | F_SYN_XACT_MATCH); |
| 2932 | eth_hdr_len = is_t4(dev->rdev.lldi.adapter_type) ? | ||
| 2933 | G_RX_ETHHDR_LEN((__force int) htonl(l2info)) : | ||
| 2934 | G_RX_T5_ETHHDR_LEN((__force int) htonl(l2info)); | ||
| 2907 | req->hdr_len = cpu_to_be32(V_SYN_RX_CHAN(G_RX_CHAN( | 2935 | req->hdr_len = cpu_to_be32(V_SYN_RX_CHAN(G_RX_CHAN( |
| 2908 | (__force int) htonl(l2info))) | | 2936 | (__force int) htonl(l2info))) | |
| 2909 | V_TCP_HDR_LEN(G_RX_TCPHDR_LEN( | 2937 | V_TCP_HDR_LEN(G_RX_TCPHDR_LEN( |
| 2910 | (__force int) htons(hdr_len))) | | 2938 | (__force int) htons(hdr_len))) | |
| 2911 | V_IP_HDR_LEN(G_RX_IPHDR_LEN( | 2939 | V_IP_HDR_LEN(G_RX_IPHDR_LEN( |
| 2912 | (__force int) htons(hdr_len))) | | 2940 | (__force int) htons(hdr_len))) | |
| 2913 | V_ETH_HDR_LEN(G_RX_ETHHDR_LEN( | 2941 | V_ETH_HDR_LEN(G_RX_ETHHDR_LEN(eth_hdr_len))); |
| 2914 | (__force int) htonl(l2info)))); | ||
| 2915 | req->vlan = (__force __be16) vlantag; | 2942 | req->vlan = (__force __be16) vlantag; |
| 2916 | req->len = (__force __be16) len; | 2943 | req->len = (__force __be16) len; |
| 2917 | req->tos_stid = cpu_to_be32(PASS_OPEN_TID(stid) | | 2944 | req->tos_stid = cpu_to_be32(PASS_OPEN_TID(stid) | |
| @@ -2999,7 +3026,7 @@ static int rx_pkt(struct c4iw_dev *dev, struct sk_buff *skb) · 81 unmodified lines | |||
| 2999 | u16 window; | 3026 | u16 window; |
| 3000 | struct port_info *pi; | 3027 | struct port_info *pi; |
| 3001 | struct net_device *pdev; | 3028 | struct net_device *pdev; |
| 3002 | u16 rss_qid; | 3029 | u16 rss_qid, eth_hdr_len; |
| 3003 | int step; | 3030 | int step; |
| 3004 | u32 tx_chan; | 3031 | u32 tx_chan; |
| 3005 | struct neighbour *neigh; | 3032 | struct neighbour *neigh; |
| @@ -3028,7 +3055,10 @@ static int rx_pkt(struct c4iw_dev *dev, struct sk_buff *skb) · 22 unmodified lines | |||
| 3028 | goto reject; | 3055 | goto reject; |
| 3029 | } | 3056 | } |
| 3030 | 3057 | ||
| 3031 | if (G_RX_ETHHDR_LEN(ntohl(cpl->l2info)) == ETH_HLEN) { | 3058 | eth_hdr_len = is_t4(dev->rdev.lldi.adapter_type) ? |
| 3059 | G_RX_ETHHDR_LEN(htonl(cpl->l2info)) : | ||
| 3060 | G_RX_T5_ETHHDR_LEN(htonl(cpl->l2info)); | ||
| 3061 | if (eth_hdr_len == ETH_HLEN) { | ||
| 3032 | eh = (struct ethhdr *)(req + 1); | 3062 | eh = (struct ethhdr *)(req + 1); |
| 3033 | iph = (struct iphdr *)(eh + 1); | 3063 | iph = (struct iphdr *)(eh + 1); |
| 3034 | } else { | 3064 | } else { |
| @@ -41,10 +41,20 @@ · 40 unmodified lines | |||
| 41 | #define DRV_VERSION "0.1" | 41 | #define DRV_VERSION "0.1" |
| 42 | 42 | ||
| 43 | MODULE_AUTHOR("Steve Wise"); | 43 | MODULE_AUTHOR("Steve Wise"); |
| 44 | MODULE_DESCRIPTION("Chelsio T4 RDMA Driver"); | 44 | MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver"); |
| 45 | MODULE_LICENSE("Dual BSD/GPL"); | 45 | MODULE_LICENSE("Dual BSD/GPL"); |
| 46 | MODULE_VERSION(DRV_VERSION); | 46 | MODULE_VERSION(DRV_VERSION); |
| 47 | 47 | ||
| 48 | static int allow_db_fc_on_t5; | ||
| 49 | module_param(allow_db_fc_on_t5, int, 0644); | ||
| 50 | MODULE_PARM_DESC(allow_db_fc_on_t5, | ||
| 51 | "Allow DB Flow Control on T5 (default = 0)"); | ||
| 52 | |||
| 53 | static int allow_db_coalescing_on_t5; | ||
| 54 | module_param(allow_db_coalescing_on_t5, int, 0644); | ||
| 55 | MODULE_PARM_DESC(allow_db_coalescing_on_t5, | ||
| 56 | "Allow DB Coalescing on T5 (default = 0)"); | ||
| 57 | |||
| 48 | struct uld_ctx { | 58 | struct uld_ctx { |
| 49 | struct list_head entry; | 59 | struct list_head entry; |
| 50 | struct cxgb4_lld_info lldi; | 60 | struct cxgb4_lld_info lldi; |
| @@ -614,7 +624,7 @@ static int rdma_supported(const struct cxgb4_lld_info *infop) · 563 unmodified lines | |||
| 614 | { | 624 | { |
| 615 | return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 && | 625 | return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 && |
| 616 | infop->vr->rq.size > 0 && infop->vr->qp.size > 0 && | 626 | infop->vr->rq.size > 0 && infop->vr->qp.size > 0 && |
| 617 | infop->vr->cq.size > 0 && infop->vr->ocq.size > 0; | 627 | infop->vr->cq.size > 0; |
| 618 | } | 628 | } |
| 619 | 629 | ||
| 620 | static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop) | 630 | static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop) |
| @@ -627,6 +637,22 @@ static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop) · 6 unmodified lines | |||
| 627 | pci_name(infop->pdev)); | 637 | pci_name(infop->pdev)); |
| 628 | return ERR_PTR(-ENOSYS); | 638 | return ERR_PTR(-ENOSYS); |
| 629 | } | 639 | } |
| 640 | if (!ocqp_supported(infop)) | ||
| 641 | pr_info("%s: On-Chip Queues not supported on this device.\n", | ||
| 642 | pci_name(infop->pdev)); | ||
| 643 | |||
| 644 | if (!is_t4(infop->adapter_type)) { | ||
| 645 | if (!allow_db_fc_on_t5) { | ||
| 646 | db_fc_threshold = 100000; | ||
| 647 | pr_info("DB Flow Control Disabled.\n"); | ||
| 648 | } | ||
| 649 | |||
| 650 | if (!allow_db_coalescing_on_t5) { | ||
| 651 | db_coalescing_threshold = -1; | ||
| 652 | pr_info("DB Coalescing Disabled.\n"); | ||
| 653 | } | ||
| 654 | } | ||
| 655 | |||
| 630 | devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp)); | 656 | devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp)); |
| 631 | if (!devp) { | 657 | if (!devp) { |
| 632 | printk(KERN_ERR MOD "Cannot allocate ib device\n"); | 658 | printk(KERN_ERR MOD "Cannot allocate ib device\n"); |
| @@ -678,8 +704,8 @@ static void *c4iw_uld_add(const struct cxgb4_lld_info *infop) · 45 unmodified lines | |||
| 678 | int i; | 704 | int i; |
| 679 | 705 | ||
| 680 | if (!vers_printed++) | 706 | if (!vers_printed++) |
| 681 | printk(KERN_INFO MOD "Chelsio T4 RDMA Driver - version %s\n", | 707 | pr_info("Chelsio T4/T5 RDMA Driver - version %s\n", |
| 682 | DRV_VERSION); | 708 | DRV_VERSION); |
| 683 | 709 | ||
| 684 | ctx = kzalloc(sizeof *ctx, GFP_KERNEL); | 710 | ctx = kzalloc(sizeof *ctx, GFP_KERNEL); |
| 685 | if (!ctx) { | 711 | if (!ctx) { |
| @@ -162,7 +162,7 @@ static inline int c4iw_num_stags(struct c4iw_rdev *rdev) · 161 unmodified lines | |||
| 162 | return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5)); | 162 | return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5)); |
| 163 | } | 163 | } |
| 164 | 164 | ||
| 165 | #define C4IW_WR_TO (10*HZ) | 165 | #define C4IW_WR_TO (30*HZ) |
| 166 | 166 | ||
| 167 | struct c4iw_wr_wait { | 167 | struct c4iw_wr_wait { |
| 168 | struct completion completion; | 168 | struct completion completion; |
| @@ -369,7 +369,6 @@ struct c4iw_fr_page_list { · 200 unmodified lines | |||
| 369 | DEFINE_DMA_UNMAP_ADDR(mapping); | 369 | DEFINE_DMA_UNMAP_ADDR(mapping); |
| 370 | dma_addr_t dma_addr; | 370 | dma_addr_t dma_addr; |
| 371 | struct c4iw_dev *dev; | 371 | struct c4iw_dev *dev; |
| 372 | int size; | ||
| 373 | }; | 372 | }; |
| 374 | 373 | ||
| 375 | static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list( | 374 | static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list( |
| @@ -817,6 +816,15 @@ static inline int compute_wscale(int win) · 441 unmodified lines | |||
| 817 | return wscale; | 816 | return wscale; |
| 818 | } | 817 | } |
| 819 | 818 | ||
| 819 | static inline int ocqp_supported(const struct cxgb4_lld_info *infop) | ||
| 820 | { | ||
| 821 | #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) | ||
| 822 | return infop->vr->ocq.size > 0; | ||
| 823 | #else | ||
| 824 | return 0; | ||
| 825 | #endif | ||
| 826 | } | ||
| 827 | |||
| 820 | u32 c4iw_id_alloc(struct c4iw_id_table *alloc); | 828 | u32 c4iw_id_alloc(struct c4iw_id_table *alloc); |
| 821 | void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj); | 829 | void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj); |
| 822 | int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num, | 830 | int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num, |
| @@ -930,6 +938,8 @@ extern struct cxgb4_client t4c_client; · 107 unmodified lines | |||
| 930 | extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; | 938 | extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; |
| 931 | extern int c4iw_max_read_depth; | 939 | extern int c4iw_max_read_depth; |
| 932 | extern int db_fc_threshold; | 940 | extern int db_fc_threshold; |
| 941 | extern int db_coalescing_threshold; | ||
| 942 | extern int use_dsgl; | ||
| 933 | 943 | ||
| 934 | 944 | ||
| 935 | #endif | 945 | #endif |
| @@ -30,16 +30,76 @@ · 29 unmodified lines | |||
| 30 | * SOFTWARE. | 30 | * SOFTWARE. |
| 31 | */ | 31 | */ |
| 32 | 32 | ||
| 33 | #include <linux/module.h> | ||
| 34 | #include <linux/moduleparam.h> | ||
| 33 | #include <rdma/ib_umem.h> | 35 | #include <rdma/ib_umem.h> |
| 34 | #include <linux/atomic.h> | 36 | #include <linux/atomic.h> |
| 35 | 37 | ||
| 36 | #include "iw_cxgb4.h" | 38 | #include "iw_cxgb4.h" |
| 37 | 39 | ||
| 40 | int use_dsgl = 1; | ||
| 41 | module_param(use_dsgl, int, 0644); | ||
| 42 | MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=1)"); | ||
| 43 | |||
| 38 | #define T4_ULPTX_MIN_IO 32 | 44 | #define T4_ULPTX_MIN_IO 32 |
| 39 | #define C4IW_MAX_INLINE_SIZE 96 | 45 | #define C4IW_MAX_INLINE_SIZE 96 |
| 46 | #define T4_ULPTX_MAX_DMA 1024 | ||
| 47 | #define C4IW_INLINE_THRESHOLD 128 | ||
| 40 | 48 | ||
| 41 | static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, | 49 | static int inline_threshold = C4IW_INLINE_THRESHOLD; |
| 42 | void *data) | 50 | module_param(inline_threshold, int, 0644); |
| 51 | MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)"); | ||
| 52 | |||
| 53 | static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr, | ||
| 54 | u32 len, dma_addr_t data, int wait) | ||
| 55 | { | ||
| 56 | struct sk_buff *skb; | ||
| 57 | struct ulp_mem_io *req; | ||
| 58 | struct ulptx_sgl *sgl; | ||
| 59 | u8 wr_len; | ||
| 60 | int ret = 0; | ||
| 61 | struct c4iw_wr_wait wr_wait; | ||
| 62 | |||
| 63 | addr &= 0x7FFFFFF; | ||
| 64 | |||
| 65 | if (wait) | ||
| 66 | c4iw_init_wr_wait(&wr_wait); | ||
| 67 | wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16); | ||
| 68 | |||
| 69 | skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL); | ||
| 70 | if (!skb) | ||
| 71 | return -ENOMEM; | ||
| 72 | set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); | ||
| 73 | |||
| 74 | req = (struct ulp_mem_io *)__skb_put(skb, wr_len); | ||
| 75 | memset(req, 0, wr_len); | ||
| 76 | INIT_ULPTX_WR(req, wr_len, 0, 0); | ||
| 77 | req->wr.wr_hi = cpu_to_be32(FW_WR_OP(FW_ULPTX_WR) | | ||
| 78 | (wait ? FW_WR_COMPL(1) : 0)); | ||
| 79 | req->wr.wr_lo = wait ? (__force __be64)&wr_wait : 0; | ||
| 80 | req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16))); | ||
| 81 | req->cmd = cpu_to_be32(ULPTX_CMD(ULP_TX_MEM_WRITE)); | ||
| 82 | req->cmd |= cpu_to_be32(V_T5_ULP_MEMIO_ORDER(1)); | ||
| 83 | req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN(len>>5)); | ||
| 84 | req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16)); | ||
| 85 | req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR(addr)); | ||
| 86 | |||
| 87 | sgl = (struct ulptx_sgl *)(req + 1); | ||
| 88 | sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD(ULP_TX_SC_DSGL) | | ||
| 89 | ULPTX_NSGE(1)); | ||
| 90 | sgl->len0 = cpu_to_be32(len); | ||
| 91 | sgl->addr0 = cpu_to_be64(data); | ||
| 92 | |||
| 93 | ret = c4iw_ofld_send(rdev, skb); | ||
| 94 | if (ret) | ||
| 95 | return ret; | ||
| 96 | if (wait) | ||
| 97 | ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__); | ||
| 98 | return ret; | ||
| 99 | } | ||
| 100 | |||
| 101 | static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len, | ||
| 102 | void *data) | ||
| 43 | { | 103 | { |
| 44 | struct sk_buff *skb; | 104 | struct sk_buff *skb; |
| 45 | struct ulp_mem_io *req; | 105 | struct ulp_mem_io *req; |
| @@ -47,6 +107,12 @@ static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, · 1 unmodified line | |||
| 47 | u8 wr_len, *to_dp, *from_dp; | 107 | u8 wr_len, *to_dp, *from_dp; |
| 48 | int copy_len, num_wqe, i, ret = 0; | 108 | int copy_len, num_wqe, i, ret = 0; |
| 49 | struct c4iw_wr_wait wr_wait; | 109 | struct c4iw_wr_wait wr_wait; |
| 110 | __be32 cmd = cpu_to_be32(ULPTX_CMD(ULP_TX_MEM_WRITE)); | ||
| 111 | |||
| 112 | if (is_t4(rdev->lldi.adapter_type)) | ||
| 113 | cmd |= cpu_to_be32(ULP_MEMIO_ORDER(1)); | ||
| 114 | else | ||
| 115 | cmd |= cpu_to_be32(V_T5_ULP_MEMIO_IMM(1)); | ||
| 50 | 116 | ||
| 51 | addr &= 0x7FFFFFF; | 117 | addr &= 0x7FFFFFF; |
| 52 | PDBG("%s addr 0x%x len %u\n", __func__, addr, len); | 118 | PDBG("%s addr 0x%x len %u\n", __func__, addr, len); |
| @@ -77,7 +143,7 @@ static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, · 24 unmodified lines | |||
| 77 | req->wr.wr_mid = cpu_to_be32( | 143 | req->wr.wr_mid = cpu_to_be32( |
| 78 | FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16))); | 144 | FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16))); |
| 79 | 145 | ||
| 80 | req->cmd = cpu_to_be32(ULPTX_CMD(ULP_TX_MEM_WRITE) | (1<<23)); | 146 | req->cmd = cmd; |
| 81 | req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN( | 147 | req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN( |
| 82 | DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO))); | 148 | DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO))); |
| 83 | req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), | 149 | req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), |
| @@ -107,6 +173,67 @@ static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, · 23 unmodified lines | |||
| 107 | return ret; | 173 | return ret; |
| 108 | } | 174 | } |
| 109 | 175 | ||
| 176 | int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data) | ||
| 177 | { | ||
| 178 | u32 remain = len; | ||
| 179 | u32 dmalen; | ||
| 180 | int ret = 0; | ||
| 181 | dma_addr_t daddr; | ||
| 182 | dma_addr_t save; | ||
| 183 | |||
| 184 | daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE); | ||
| 185 | if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr)) | ||
| 186 | return -1; | ||
| 187 | save = daddr; | ||
| 188 | |||
| 189 | while (remain > inline_threshold) { | ||
| 190 | if (remain < T4_ULPTX_MAX_DMA) { | ||
| 191 | if (remain & ~T4_ULPTX_MIN_IO) | ||
| 192 | dmalen = remain & ~(T4_ULPTX_MIN_IO-1); | ||
| 193 | else | ||
| 194 | dmalen = remain; | ||
| 195 | } else | ||
| 196 | dmalen = T4_ULPTX_MAX_DMA; | ||
| 197 | remain -= dmalen; | ||
| 198 | ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr, | ||
| 199 | !remain); | ||
| 200 | if (ret) | ||
| 201 | goto out; | ||
| 202 | addr += dmalen >> 5; | ||
| 203 | data += dmalen; | ||
| 204 | daddr += dmalen; | ||
| 205 | } | ||
| 206 | if (remain) | ||
| 207 | ret = _c4iw_write_mem_inline(rdev, addr, remain, data); | ||
| 208 | out: | ||
| 209 | dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE); | ||
| 210 | return ret; | ||
| 211 | } | ||
| 212 | |||
| 213 | /* | ||
| 214 | * write len bytes of data into addr (32B aligned address) | ||
| 215 | * If data is NULL, clear len byte of memory to zero. | ||
| 216 | */ | ||
| 217 | static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, | ||
| 218 | void *data) | ||
| 219 | { | ||
| 220 | if (is_t5(rdev->lldi.adapter_type) && use_dsgl) { | ||
| 221 | if (len > inline_threshold) { | ||
| 222 | if (_c4iw_write_mem_dma(rdev, addr, len, data)) { | ||
| 223 | printk_ratelimited(KERN_WARNING | ||
| 224 | "%s: dma map" | ||
| 225 | " failure (non fatal)\n", | ||
| 226 | pci_name(rdev->lldi.pdev)); | ||
| 227 | return _c4iw_write_mem_inline(rdev, addr, len, | ||
| 228 | data); | ||
| 229 | } else | ||
| 230 | return 0; | ||
| 231 | } else | ||
| 232 | return _c4iw_write_mem_inline(rdev, addr, len, data); | ||
| 233 | } else | ||
| 234 | return _c4iw_write_mem_inline(rdev, addr, len, data); | ||
| 235 | } | ||
| 236 | |||
| 110 | /* | 237 | /* |
| 111 | * Build and write a TPT entry. | 238 | * Build and write a TPT entry. |
| 112 | * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size, | 239 | * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size, |
| @@ -760,19 +887,23 @@ struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(struct ib_device *device, · 647 unmodified lines | |||
| 760 | struct c4iw_fr_page_list *c4pl; | 887 | struct c4iw_fr_page_list *c4pl; |
| 761 | struct c4iw_dev *dev = to_c4iw_dev(device); | 888 | struct c4iw_dev *dev = to_c4iw_dev(device); |
| 762 | dma_addr_t dma_addr; | 889 | dma_addr_t dma_addr; |
| 763 | int size = sizeof *c4pl + page_list_len * sizeof(u64); | 890 | int pll_len = roundup(page_list_len * sizeof(u64), 32); |
| 764 | 891 | ||
| 765 | c4pl = dma_alloc_coherent(&dev->rdev.lldi.pdev->dev, size, | 892 | c4pl = kmalloc(sizeof(*c4pl), GFP_KERNEL); |
| 766 | &dma_addr, GFP_KERNEL); | ||
| 767 | if (!c4pl) | 893 | if (!c4pl) |
| 768 | return ERR_PTR(-ENOMEM); | 894 | return ERR_PTR(-ENOMEM); |
| 769 | 895 | ||
| 896 | c4pl->ibpl.page_list = dma_alloc_coherent(&dev->rdev.lldi.pdev->dev, | ||
| 897 | pll_len, &dma_addr, | ||
| 898 | GFP_KERNEL); | ||
| 899 | if (!c4pl->ibpl.page_list) { | ||
| 900 | kfree(c4pl); | ||
| 901 | return ERR_PTR(-ENOMEM); | ||
| 902 | } | ||
| 770 | dma_unmap_addr_set(c4pl, mapping, dma_addr); | 903 | dma_unmap_addr_set(c4pl, mapping, dma_addr); |
| 771 | c4pl->dma_addr = dma_addr; | 904 | c4pl->dma_addr = dma_addr; |
| 772 | c4pl->dev = dev; | 905 | c4pl->dev = dev; |
| 773 | c4pl->size = size; | 906 | c4pl->ibpl.max_page_list_len = pll_len; |
| 774 | c4pl->ibpl.page_list = (u64 *)(c4pl + 1); | ||
| 775 | c4pl->ibpl.max_page_list_len = page_list_len; | ||
| 776 | 907 | ||
| 777 | return &c4pl->ibpl; | 908 | return &c4pl->ibpl; |
| 778 | } | 909 | } |
| @@ -781,8 +912,10 @@ void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *ibpl) · 2 unmodified lines | |||
| 781 | { | 912 | { |
| 782 | struct c4iw_fr_page_list *c4pl = to_c4iw_fr_page_list(ibpl); | 913 | struct c4iw_fr_page_list *c4pl = to_c4iw_fr_page_list(ibpl); |
| 783 | 914 | ||
| 784 | dma_free_coherent(&c4pl->dev->rdev.lldi.pdev->dev, c4pl->size, | 915 | dma_free_coherent(&c4pl->dev->rdev.lldi.pdev->dev, |
| 785 | c4pl, dma_unmap_addr(c4pl, mapping)); | 916 | c4pl->ibpl.max_page_list_len, |
| 917 | c4pl->ibpl.page_list, dma_unmap_addr(c4pl, mapping)); | ||
| 918 | kfree(c4pl); | ||
| 786 | } | 919 | } |
| 787 | 920 | ||
| 788 | int c4iw_dereg_mr(struct ib_mr *ib_mr) | 921 | int c4iw_dereg_mr(struct ib_mr *ib_mr) |
| @@ -162,8 +162,14 @@ static int c4iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) · 161 unmodified lines | |||
| 162 | */ | 162 | */ |
| 163 | if (addr >= rdev->oc_mw_pa) | 163 | if (addr >= rdev->oc_mw_pa) |
| 164 | vma->vm_page_prot = t4_pgprot_wc(vma->vm_page_prot); | 164 | vma->vm_page_prot = t4_pgprot_wc(vma->vm_page_prot); |
| 165 | else | 165 | else { |
| 166 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | 166 | if (is_t5(rdev->lldi.adapter_type)) |
| 167 | vma->vm_page_prot = | ||
| 168 | t4_pgprot_wc(vma->vm_page_prot); | ||
| 169 | else | ||
| 170 | vma->vm_page_prot = | ||
| 171 | pgprot_noncached(vma->vm_page_prot); | ||
| 172 | } | ||
| 167 | ret = io_remap_pfn_range(vma, vma->vm_start, | 173 | ret = io_remap_pfn_range(vma, vma->vm_start, |
| 168 | addr >> PAGE_SHIFT, | 174 | addr >> PAGE_SHIFT, |
| 169 | len, vma->vm_page_prot); | 175 | len, vma->vm_page_prot); |
| @@ -263,7 +269,7 @@ static int c4iw_query_device(struct ib_device *ibdev, · 93 unmodified lines | |||
| 263 | dev = to_c4iw_dev(ibdev); | 269 | dev = to_c4iw_dev(ibdev); |
| 264 | memset(props, 0, sizeof *props); | 270 | memset(props, 0, sizeof *props); |
| 265 | memcpy(&props->sys_image_guid, dev->rdev.lldi.ports[0]->dev_addr, 6); | 271 | memcpy(&props->sys_image_guid, dev->rdev.lldi.ports[0]->dev_addr, 6); |
| 266 | props->hw_ver = dev->rdev.lldi.adapter_type; | 272 | props->hw_ver = CHELSIO_CHIP_RELEASE(dev->rdev.lldi.adapter_type); |
| 267 | props->fw_ver = dev->rdev.lldi.fw_vers; | 273 | props->fw_ver = dev->rdev.lldi.fw_vers; |
| 268 | props->device_cap_flags = dev->device_cap_flags; | 274 | props->device_cap_flags = dev->device_cap_flags; |
| 269 | props->page_size_cap = T4_PAGESIZE_MASK; | 275 | props->page_size_cap = T4_PAGESIZE_MASK; |
| @@ -346,7 +352,8 @@ static ssize_t show_rev(struct device *dev, struct device_attribute *attr, · 76 unmodified lines | |||
| 346 | struct c4iw_dev *c4iw_dev = container_of(dev, struct c4iw_dev, | 352 | struct c4iw_dev *c4iw_dev = container_of(dev, struct c4iw_dev, |
| 347 | ibdev.dev); | 353 | ibdev.dev); |
| 348 | PDBG("%s dev 0x%p\n", __func__, dev); | 354 | PDBG("%s dev 0x%p\n", __func__, dev); |
| 349 | return sprintf(buf, "%d\n", c4iw_dev->rdev.lldi.adapter_type); | 355 | return sprintf(buf, "%d\n", |
| 356 | CHELSIO_CHIP_RELEASE(c4iw_dev->rdev.lldi.adapter_type)); | ||
| 350 | } | 357 | } |
| 351 | 358 | ||
| 352 | static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr, | 359 | static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr, |
| @@ -42,10 +42,21 @@ static int ocqp_support = 1; · 41 unmodified lines | |||
| 42 | module_param(ocqp_support, int, 0644); | 42 | module_param(ocqp_support, int, 0644); |
| 43 | MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)"); | 43 | MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)"); |
| 44 | 44 | ||
| 45 | int db_fc_threshold = 2000; | 45 | int db_fc_threshold = 1000; |
| 46 | module_param(db_fc_threshold, int, 0644); | 46 | module_param(db_fc_threshold, int, 0644); |
| 47 | MODULE_PARM_DESC(db_fc_threshold, "QP count/threshold that triggers automatic " | 47 | MODULE_PARM_DESC(db_fc_threshold, |
| 48 | "db flow control mode (default = 2000)"); | 48 | "QP count/threshold that triggers" |
| 49 | " automatic db flow control mode (default = 1000)"); | ||
| 50 | |||
| 51 | int db_coalescing_threshold; | ||
| 52 | module_param(db_coalescing_threshold, int, 0644); | ||
| 53 | MODULE_PARM_DESC(db_coalescing_threshold, | ||
| 54 | "QP count/threshold that triggers" | ||
| 55 | " disabling db coalescing (default = 0)"); | ||
| 56 | |||
| 57 | static int max_fr_immd = T4_MAX_FR_IMMD; | ||
| 58 | module_param(max_fr_immd, int, 0644); | ||
| 59 | MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate"); | ||
| 49 | 60 | ||
| 50 | static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) | 61 | static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) |
| 51 | { | 62 | { |
| @@ -76,7 +87,7 @@ static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) · 24 unmodified lines | |||
| 76 | 87 | ||
| 77 | static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) | 88 | static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) |
| 78 | { | 89 | { |
| 79 | if (!ocqp_support || !t4_ocqp_supported()) | 90 | if (!ocqp_support || !ocqp_supported(&rdev->lldi)) |
| 80 | return -ENOSYS; | 91 | return -ENOSYS; |
| 81 | sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize); | 92 | sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize); |
| 82 | if (!sq->dma_addr) | 93 | if (!sq->dma_addr) |
| @@ -129,7 +140,7 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, · 46 unmodified lines | |||
| 129 | int wr_len; | 140 | int wr_len; |
| 130 | struct c4iw_wr_wait wr_wait; | 141 | struct c4iw_wr_wait wr_wait; |
| 131 | struct sk_buff *skb; | 142 | struct sk_buff *skb; |
| 132 | int ret; | 143 | int ret = 0; |
| 133 | int eqsize; | 144 | int eqsize; |
| 134 | 145 | ||
| 135 | wq->sq.qid = c4iw_get_qpid(rdev, uctx); | 146 | wq->sq.qid = c4iw_get_qpid(rdev, uctx); |
| @@ -169,17 +180,14 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, · 33 unmodified lines | |||
| 169 | } | 180 | } |
| 170 | 181 | ||
| 171 | if (user) { | 182 | if (user) { |
| 172 | ret = alloc_oc_sq(rdev, &wq->sq); | 183 | if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq)) |
| 173 | if (ret) | ||
| 174 | goto free_hwaddr; | 184 | goto free_hwaddr; |
| 175 | 185 | } else { | |
| 176 | ret = alloc_host_sq(rdev, &wq->sq); | ||
| 177 | if (ret) | ||
| 178 | goto free_sq; | ||
| 179 | } else | ||
| 180 | ret = alloc_host_sq(rdev, &wq->sq); | 186 | ret = alloc_host_sq(rdev, &wq->sq); |
| 181 | if (ret) | 187 | if (ret) |
| 182 | goto free_hwaddr; | 188 | goto free_hwaddr; |
| 189 | } | ||
| 190 | |||
| 183 | memset(wq->sq.queue, 0, wq->sq.memsize); | 191 | memset(wq->sq.queue, 0, wq->sq.memsize); |
| 184 | dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); | 192 | dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); |
| 185 | 193 | ||
| @@ -534,7 +542,7 @@ static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, · 348 unmodified lines | |||
| 534 | } | 542 | } |
| 535 | 543 | ||
| 536 | static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, | 544 | static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, |
| 537 | struct ib_send_wr *wr, u8 *len16) | 545 | struct ib_send_wr *wr, u8 *len16, u8 t5dev) |
| 538 | { | 546 | { |
| 539 | 547 | ||
| 540 | struct fw_ri_immd *imdp; | 548 | struct fw_ri_immd *imdp; |
| @@ -556,28 +564,51 @@ static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, · 15 unmodified lines | |||
| 556 | wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32); | 564 | wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32); |
| 557 | wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start & | 565 | wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start & |
| 558 | 0xffffffff); | 566 | 0xffffffff); |
| 559 | WARN_ON(pbllen > T4_MAX_FR_IMMD); | 567 | |
| 560 | imdp = (struct fw_ri_immd *)(&wqe->fr + 1); | 568 | if (t5dev && use_dsgl && (pbllen > max_fr_immd)) { |
| 561 | imdp->op = FW_RI_DATA_IMMD; | 569 | struct c4iw_fr_page_list *c4pl = |
| 562 | imdp->r1 = 0; | 570 | to_c4iw_fr_page_list(wr->wr.fast_reg.page_list); |
| 563 | imdp->r2 = 0; | 571 | struct fw_ri_dsgl *sglp; |
| 564 | imdp->immdlen = cpu_to_be32(pbllen); | 572 | |
| 565 | p = (__be64 *)(imdp + 1); | 573 | for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { |
| 566 | rem = pbllen; | 574 | wr->wr.fast_reg.page_list->page_list[i] = (__force u64) |
| 567 | for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { | 575 | cpu_to_be64((u64) |
| 568 | *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]); | 576 | wr->wr.fast_reg.page_list->page_list[i]); |
| 569 | rem -= sizeof *p; | 577 | } |
| 570 | if (++p == (__be64 *)&sq->queue[sq->size]) | 578 | |
| 571 | p = (__be64 *)sq->queue; | 579 | sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1); |
| 572 | } | 580 | sglp->op = FW_RI_DATA_DSGL; |
| 573 | BUG_ON(rem < 0); | 581 | sglp->r1 = 0; |
| 574 | while (rem) { | 582 | sglp->nsge = cpu_to_be16(1); |
| 575 | *p = 0; | 583 | sglp->addr0 = cpu_to_be64(c4pl->dma_addr); |
| 576 | rem -= sizeof *p; | 584 | sglp->len0 = cpu_to_be32(pbllen); |
| 577 | if (++p == (__be64 *)&sq->queue[sq->size]) | 585 | |
| 578 | p = (__be64 *)sq->queue; | 586 | *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16); |
| 587 | } else { | ||
| 588 | imdp = (struct fw_ri_immd *)(&wqe->fr + 1); | ||
| 589 | imdp->op = FW_RI_DATA_IMMD; | ||
| 590 | imdp->r1 = 0; | ||
| 591 | imdp->r2 = 0; | ||
| 592 | imdp->immdlen = cpu_to_be32(pbllen); | ||
| 593 | p = (__be64 *)(imdp + 1); | ||
| 594 | rem = pbllen; | ||
| 595 | for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { | ||
| 596 | *p = cpu_to_be64( | ||
| 597 | (u64)wr->wr.fast_reg.page_list->page_list[i]); | ||
| 598 | rem -= sizeof(*p); | ||
| 599 | if (++p == (__be64 *)&sq->queue[sq->size]) | ||
| 600 | p = (__be64 *)sq->queue; | ||
| 601 | } | ||
| 602 | BUG_ON(rem < 0); | ||
| 603 | while (rem) { | ||
| 604 | *p = 0; | ||
| 605 | rem -= sizeof(*p); | ||
| 606 | if (++p == (__be64 *)&sq->queue[sq->size]) | ||
| 607 | p = (__be64 *)sq->queue; | ||
| 608 | } | ||
| 609 | *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp) | ||
| 610 | + pbllen, 16); | ||
| 579 | } | 611 | } |
| 580 | *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16); | ||
| 581 | return 0; | 612 | return 0; |
| 582 | } | 613 | } |
| 583 | 614 | ||
| @@ -678,7 +709,10 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, · 94 unmodified lines | |||
| 678 | case IB_WR_FAST_REG_MR: | 709 | case IB_WR_FAST_REG_MR: |
| 679 | fw_opcode = FW_RI_FR_NSMR_WR; | 710 | fw_opcode = FW_RI_FR_NSMR_WR; |
| 680 | swsqe->opcode = FW_RI_FAST_REGISTER; | 711 | swsqe->opcode = FW_RI_FAST_REGISTER; |
| 681 | err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16); | 712 | err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16, |
| 713 | is_t5( | ||
| 714 | qhp->rhp->rdev.lldi.adapter_type) ? | ||
| 715 | 1 : 0); | ||
| 682 | break; | 716 | break; |
| 683 | case IB_WR_LOCAL_INV: | 717 | case IB_WR_LOCAL_INV: |
| 684 | if (wr->send_flags & IB_SEND_FENCE) | 718 | if (wr->send_flags & IB_SEND_FENCE) |
| @@ -1450,6 +1484,9 @@ int c4iw_destroy_qp(struct ib_qp *ib_qp) · 765 unmodified lines | |||
| 1450 | rhp->db_state = NORMAL; | 1484 | rhp->db_state = NORMAL; |
| 1451 | idr_for_each(&rhp->qpidr, enable_qp_db, NULL); | 1485 | idr_for_each(&rhp->qpidr, enable_qp_db, NULL); |
| 1452 | } | 1486 | } |
| 1487 | if (db_coalescing_threshold >= 0) | ||
| 1488 | if (rhp->qpcnt <= db_coalescing_threshold) | ||
| 1489 | cxgb4_enable_db_coalescing(rhp->rdev.lldi.ports[0]); | ||
| 1453 | spin_unlock_irq(&rhp->lock); | 1490 | spin_unlock_irq(&rhp->lock); |
| 1454 | atomic_dec(&qhp->refcnt); | 1491 | atomic_dec(&qhp->refcnt); |
| 1455 | wait_event(qhp->wait, !atomic_read(&qhp->refcnt)); | 1492 | wait_event(qhp->wait, !atomic_read(&qhp->refcnt)); |
| @@ -1561,11 +1598,15 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, · 105 unmodified lines | |||
| 1561 | spin_lock_irq(&rhp->lock); | 1598 | spin_lock_irq(&rhp->lock); |
| 1562 | if (rhp->db_state != NORMAL) | 1599 | if (rhp->db_state != NORMAL) |
| 1563 | t4_disable_wq_db(&qhp->wq); | 1600 | t4_disable_wq_db(&qhp->wq); |
| 1564 | if (++rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) { | 1601 | rhp->qpcnt++; |
| 1602 | if (rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) { | ||
| 1565 | rhp->rdev.stats.db_state_transitions++; | 1603 | rhp->rdev.stats.db_state_transitions++; |
| 1566 | rhp->db_state = FLOW_CONTROL; | 1604 | rhp->db_state = FLOW_CONTROL; |
| 1567 | idr_for_each(&rhp->qpidr, disable_qp_db, NULL); | 1605 | idr_for_each(&rhp->qpidr, disable_qp_db, NULL); |
| 1568 | } | 1606 | } |
| 1607 | if (db_coalescing_threshold >= 0) | ||
| 1608 | if (rhp->qpcnt > db_coalescing_threshold) | ||
| 1609 | cxgb4_disable_db_coalescing(rhp->rdev.lldi.ports[0]); | ||
| 1569 | ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); | 1610 | ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); |
| 1570 | spin_unlock_irq(&rhp->lock); | 1611 | spin_unlock_irq(&rhp->lock); |
| 1571 | if (ret) | 1612 | if (ret) |
| @@ -84,7 +84,7 @@ struct t4_status_page { · 83 unmodified lines | |||
| 84 | sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) | 84 | sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) |
| 85 | #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ | 85 | #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ |
| 86 | sizeof(struct fw_ri_immd)) & ~31UL) | 86 | sizeof(struct fw_ri_immd)) & ~31UL) |
| 87 | #define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) | 87 | #define T4_MAX_FR_DEPTH (1024 / sizeof(u64)) |
| 88 | 88 | ||
| 89 | #define T4_RQ_NUM_SLOTS 2 | 89 | #define T4_RQ_NUM_SLOTS 2 |
| 90 | #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) | 90 | #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) |
| @@ -280,15 +280,6 @@ static inline pgprot_t t4_pgprot_wc(pgprot_t prot) · 189 unmodified lines | |||
| 280 | #endif | 280 | #endif |
| 281 | } | 281 | } |
| 282 | 282 | ||
| 283 | static inline int t4_ocqp_supported(void) | ||
| 284 | { | ||
| 285 | #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) | ||
| 286 | return 1; | ||
| 287 | #else | ||
| 288 | return 0; | ||
| 289 | #endif | ||
| 290 | } | ||
| 291 | |||
| 292 | enum { | 283 | enum { |
| 293 | T4_SQ_ONCHIP = (1<<0), | 284 | T4_SQ_ONCHIP = (1<<0), |
| 294 | }; | 285 | }; |
| @@ -228,7 +228,7 @@ struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector · 227 unmodified lines | |||
| 228 | vector = dev->eq_table[vector % ibdev->num_comp_vectors]; | 228 | vector = dev->eq_table[vector % ibdev->num_comp_vectors]; |
| 229 | 229 | ||
| 230 | err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, | 230 | err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, |
| 231 | cq->db.dma, &cq->mcq, vector, 0); | 231 | cq->db.dma, &cq->mcq, vector, 0, 0); |
| 232 | if (err) | 232 | if (err) |
| 233 | goto err_dbmap; | 233 | goto err_dbmap; |
| 234 | 234 | ||
| @@ -2948,7 +2948,7 @@ void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq) · 2947 unmodified lines | |||
| 2948 | nes_debug(NES_DBG_CQ, "%s: Reporting stripped VLAN packet. Tag = 0x%04X\n", | 2948 | nes_debug(NES_DBG_CQ, "%s: Reporting stripped VLAN packet. Tag = 0x%04X\n", |
| 2949 | nesvnic->netdev->name, vlan_tag); | 2949 | nesvnic->netdev->name, vlan_tag); |
| 2950 | 2950 | ||
| 2951 | __vlan_hwaccel_put_tag(rx_skb, vlan_tag); | 2951 | __vlan_hwaccel_put_tag(rx_skb, htons(ETH_P_8021Q), vlan_tag); |
| 2952 | } | 2952 | } |
| 2953 | if (nes_use_lro) | 2953 | if (nes_use_lro) |
| 2954 | lro_receive_skb(&nesvnic->lro_mgr, rx_skb, NULL); | 2954 | lro_receive_skb(&nesvnic->lro_mgr, rx_skb, NULL); |
| @@ -1599,7 +1599,7 @@ static void nes_vlan_mode(struct net_device *netdev, struct nes_device *nesdev, · 1598 unmodified lines | |||
| 1599 | 1599 | ||
| 1600 | /* Enable/Disable VLAN Stripping */ | 1600 | /* Enable/Disable VLAN Stripping */ |
| 1601 | u32temp = nes_read_indexed(nesdev, NES_IDX_PCIX_DIAG); | 1601 | u32temp = nes_read_indexed(nesdev, NES_IDX_PCIX_DIAG); |
| 1602 | if (features & NETIF_F_HW_VLAN_RX) | 1602 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 1603 | u32temp &= 0xfdffffff; | 1603 | u32temp &= 0xfdffffff; |
| 1604 | else | 1604 | else |
| 1605 | u32temp |= 0x02000000; | 1605 | u32temp |= 0x02000000; |
| @@ -1614,10 +1614,10 @@ static netdev_features_t nes_fix_features(struct net_device *netdev, netdev_feat · 8 unmodified lines | |||
| 1614 | * Since there is no support for separate rx/tx vlan accel | 1614 | * Since there is no support for separate rx/tx vlan accel |
| 1615 | * enable/disable make sure tx flag is always in same state as rx. | 1615 | * enable/disable make sure tx flag is always in same state as rx. |
| 1616 | */ | 1616 | */ |
| 1617 | if (features & NETIF_F_HW_VLAN_RX) | 1617 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 1618 | features |= NETIF_F_HW_VLAN_TX; | 1618 | features |= NETIF_F_HW_VLAN_CTAG_TX; |
| 1619 | else | 1619 | else |
| 1620 | features &= ~NETIF_F_HW_VLAN_TX; | 1620 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 1621 | 1621 | ||
| 1622 | return features; | 1622 | return features; |
| 1623 | } | 1623 | } |
| @@ -1628,7 +1628,7 @@ static int nes_set_features(struct net_device *netdev, netdev_features_t feature · 4 unmodified lines | |||
| 1628 | struct nes_device *nesdev = nesvnic->nesdev; | 1628 | struct nes_device *nesdev = nesvnic->nesdev; |
| 1629 | u32 changed = netdev->features ^ features; | 1629 | u32 changed = netdev->features ^ features; |
| 1630 | 1630 | ||
| 1631 | if (changed & NETIF_F_HW_VLAN_RX) | 1631 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
| 1632 | nes_vlan_mode(netdev, nesdev, features); | 1632 | nes_vlan_mode(netdev, nesdev, features); |
| 1633 | 1633 | ||
| 1634 | return 0; | 1634 | return 0; |
| @@ -1706,11 +1706,11 @@ struct net_device *nes_netdev_init(struct nes_device *nesdev, · 71 unmodified lines | |||
| 1706 | netdev->dev_addr[4] = (u8)(u64temp>>8); | 1706 | netdev->dev_addr[4] = (u8)(u64temp>>8); |
| 1707 | netdev->dev_addr[5] = (u8)u64temp; | 1707 | netdev->dev_addr[5] = (u8)u64temp; |
| 1708 | 1708 | ||
| 1709 | netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX; | 1709 | netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX; |
| 1710 | if ((nesvnic->logical_port < 2) || (nesdev->nesadapter->hw_rev != NE020_REV)) | 1710 | if ((nesvnic->logical_port < 2) || (nesdev->nesadapter->hw_rev != NE020_REV)) |
| 1711 | netdev->hw_features |= NETIF_F_TSO; | 1711 | netdev->hw_features |= NETIF_F_TSO; |
| 1712 | 1712 | ||
| 1713 | netdev->features = netdev->hw_features | NETIF_F_HIGHDMA | NETIF_F_HW_VLAN_TX; | 1713 | netdev->features = netdev->hw_features | NETIF_F_HIGHDMA | NETIF_F_HW_VLAN_CTAG_TX; |
| 1714 | netdev->hw_features |= NETIF_F_LRO; | 1714 | netdev->hw_features |= NETIF_F_LRO; |
| 1715 | 1715 | ||
| 1716 | nes_debug(NES_DBG_INIT, "nesvnic = %p, reported features = 0x%lX, QPid = %d," | 1716 | nes_debug(NES_DBG_INIT, "nesvnic = %p, reported features = 0x%lX, QPid = %d," |
| @@ -730,7 +730,8 @@ static int ipoib_start_xmit(struct sk_buff *skb, struct net_device *dev) · 729 unmodified lines | |||
| 730 | if ((header->proto != htons(ETH_P_IP)) && | 730 | if ((header->proto != htons(ETH_P_IP)) && |
| 731 | (header->proto != htons(ETH_P_IPV6)) && | 731 | (header->proto != htons(ETH_P_IPV6)) && |
| 732 | (header->proto != htons(ETH_P_ARP)) && | 732 | (header->proto != htons(ETH_P_ARP)) && |
| 733 | (header->proto != htons(ETH_P_RARP))) { | 733 | (header->proto != htons(ETH_P_RARP)) && |
| 734 | (header->proto != htons(ETH_P_TIPC))) { | ||
| 734 | /* ethertype not supported by IPoIB */ | 735 | /* ethertype not supported by IPoIB */ |
| 735 | ++dev->stats.tx_dropped; | 736 | ++dev->stats.tx_dropped; |
| 736 | dev_kfree_skb_any(skb); | 737 | dev_kfree_skb_any(skb); |
| @@ -751,6 +752,7 @@ static int ipoib_start_xmit(struct sk_buff *skb, struct net_device *dev) · 14 unmodified lines | |||
| 751 | switch (header->proto) { | 752 | switch (header->proto) { |
| 752 | case htons(ETH_P_IP): | 753 | case htons(ETH_P_IP): |
| 753 | case htons(ETH_P_IPV6): | 754 | case htons(ETH_P_IPV6): |
| 755 | case htons(ETH_P_TIPC): | ||
| 754 | neigh = ipoib_neigh_get(dev, cb->hwaddr); | 756 | neigh = ipoib_neigh_get(dev, cb->hwaddr); |
| 755 | if (unlikely(!neigh)) { | 757 | if (unlikely(!neigh)) { |
| 756 | neigh_add_path(skb, cb->hwaddr, dev); | 758 | neigh_add_path(skb, cb->hwaddr, dev); |
| @@ -469,8 +469,7 @@ static int capidrv_add_ack(struct capidrv_ncci *nccip, · 468 unmodified lines | |||
| 469 | { | 469 | { |
| 470 | struct ncci_datahandle_queue *n, **pp; | 470 | struct ncci_datahandle_queue *n, **pp; |
| 471 | 471 | ||
| 472 | n = (struct ncci_datahandle_queue *) | 472 | n = kmalloc(sizeof(struct ncci_datahandle_queue), GFP_ATOMIC); |
| 473 | kmalloc(sizeof(struct ncci_datahandle_queue), GFP_ATOMIC); | ||
| 474 | if (!n) { | 473 | if (!n) { |
| 475 | printk(KERN_ERR "capidrv: kmalloc ncci_datahandle failed\n"); | 474 | printk(KERN_ERR "capidrv: kmalloc ncci_datahandle failed\n"); |
| 476 | return -1; | 475 | return -1; |
| @@ -441,8 +441,7 @@ static int isdn_divert_icall(isdn_ctrl *ic) · 440 unmodified lines | |||
| 441 | 441 | ||
| 442 | switch (dv->rule.action) { | 442 | switch (dv->rule.action) { |
| 443 | case DEFLECT_IGNORE: | 443 | case DEFLECT_IGNORE: |
| 444 | return (0); | 444 | return 0; |
| 445 | break; | ||
| 446 | 445 | ||
| 447 | case DEFLECT_ALERT: | 446 | case DEFLECT_ALERT: |
| 448 | case DEFLECT_PROCEED: | 447 | case DEFLECT_PROCEED: |
| @@ -510,10 +509,9 @@ static int isdn_divert_icall(isdn_ctrl *ic) · 61 unmodified lines | |||
| 510 | break; | 509 | break; |
| 511 | 510 | ||
| 512 | default: | 511 | default: |
| 513 | return (0); /* ignore call */ | 512 | return 0; /* ignore call */ |
| 514 | break; | ||
| 515 | } /* switch action */ | 513 | } /* switch action */ |
| 516 | break; | 514 | break; /* will break the 'for' looping */ |
| 517 | } /* scan_table */ | 515 | } /* scan_table */ |
| 518 | 516 | ||
| 519 | if (cs) { | 517 | if (cs) { |
| @@ -26,7 +26,7 @@ FsmNew(struct Fsm *fsm, struct FsmNode *fnlist, int fncount) · 25 unmodified lines | |||
| 26 | { | 26 | { |
| 27 | int i; | 27 | int i; |
| 28 | 28 | ||
| 29 | fsm->jumpmatrix = (FSMFNPTR *) | 29 | fsm->jumpmatrix = |
| 30 | kzalloc(sizeof(FSMFNPTR) * fsm->state_count * fsm->event_count, GFP_KERNEL); | 30 | kzalloc(sizeof(FSMFNPTR) * fsm->state_count * fsm->event_count, GFP_KERNEL); |
| 31 | if (!fsm->jumpmatrix) | 31 | if (!fsm->jumpmatrix) |
| 32 | return -ENOMEM; | 32 | return -ENOMEM; |
| @@ -1479,7 +1479,7 @@ int setup_hfcsx(struct IsdnCard *card) · 1478 unmodified lines | |||
| 1479 | release_region(cs->hw.hfcsx.base, 2); | 1479 | release_region(cs->hw.hfcsx.base, 2); |
| 1480 | return (0); | 1480 | return (0); |
| 1481 | } | 1481 | } |
| 1482 | if (!(cs->hw.hfcsx.extra = (void *) | 1482 | if (!(cs->hw.hfcsx.extra = |
| 1483 | kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) { | 1483 | kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) { |
| 1484 | release_region(cs->hw.hfcsx.base, 2); | 1484 | release_region(cs->hw.hfcsx.base, 2); |
| 1485 | printk(KERN_WARNING "HFC-SX: unable to allocate memory\n"); | 1485 | printk(KERN_WARNING "HFC-SX: unable to allocate memory\n"); |
| @@ -1385,7 +1385,7 @@ isdn_net_type_trans(struct sk_buff *skb, struct net_device *dev) · 1384 unmodified lines | |||
| 1385 | if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN)) | 1385 | if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN)) |
| 1386 | skb->pkt_type = PACKET_OTHERHOST; | 1386 | skb->pkt_type = PACKET_OTHERHOST; |
| 1387 | } | 1387 | } |
| 1388 | if (ntohs(eth->h_proto) >= 1536) | 1388 | if (ntohs(eth->h_proto) >= ETH_P_802_3_MIN) |
| 1389 | return eth->h_proto; | 1389 | return eth->h_proto; |
| 1390 | 1390 | ||
| 1391 | rawp = skb->data; | 1391 | rawp = skb->data; |
| @@ -578,6 +578,7 @@ data_sock_getname(struct socket *sock, struct sockaddr *addr, · 577 unmodified lines | |||
| 578 | lock_sock(sk); | 578 | lock_sock(sk); |
| 579 | 579 | ||
| 580 | *addr_len = sizeof(*maddr); | 580 | *addr_len = sizeof(*maddr); |
| 581 | maddr->family = AF_ISDN; | ||
| 581 | maddr->dev = _pms(sk)->dev->id; | 582 | maddr->dev = _pms(sk)->dev->id; |
| 582 | maddr->channel = _pms(sk)->ch.nr; | 583 | maddr->channel = _pms(sk)->ch.nr; |
| 583 | maddr->sapi = _pms(sk)->ch.addr & 0xff; | 584 | maddr->sapi = _pms(sk)->ch.addr & 0xff; |
| @@ -33,8 +33,8 @@ static unsigned long ram[] = {0, 0, 0, 0}; · 32 unmodified lines | |||
| 33 | static bool do_reset = 0; | 33 | static bool do_reset = 0; |
| 34 | 34 | ||
| 35 | module_param_array(io, int, NULL, 0); | 35 | module_param_array(io, int, NULL, 0); |
| 36 | module_param_array(irq, int, NULL, 0); | 36 | module_param_array(irq, byte, NULL, 0); |
| 37 | module_param_array(ram, int, NULL, 0); | 37 | module_param_array(ram, long, NULL, 0); |
| 38 | module_param(do_reset, bool, 0); | 38 | module_param(do_reset, bool, 0); |
| 39 | 39 | ||
| 40 | static int identify_board(unsigned long, unsigned int); | 40 | static int identify_board(unsigned long, unsigned int); |
| @@ -185,7 +185,7 @@ static __be16 dvb_net_eth_type_trans(struct sk_buff *skb, · 184 unmodified lines | |||
| 185 | skb->pkt_type=PACKET_MULTICAST; | 185 | skb->pkt_type=PACKET_MULTICAST; |
| 186 | } | 186 | } |
| 187 | 187 | ||
| 188 | if (ntohs(eth->h_proto) >= 1536) | 188 | if (ntohs(eth->h_proto) >= ETH_P_802_3_MIN) |
| 189 | return eth->h_proto; | 189 | return eth->h_proto; |
| 190 | 190 | ||
| 191 | rawp = skb->data; | 191 | rawp = skb->data; |
| @@ -228,9 +228,9 @@ static int ule_test_sndu( struct dvb_net_priv *p ) · 36 unmodified lines | |||
| 228 | static int ule_bridged_sndu( struct dvb_net_priv *p ) | 228 | static int ule_bridged_sndu( struct dvb_net_priv *p ) |
| 229 | { | 229 | { |
| 230 | struct ethhdr *hdr = (struct ethhdr*) p->ule_next_hdr; | 230 | struct ethhdr *hdr = (struct ethhdr*) p->ule_next_hdr; |
| 231 | if(ntohs(hdr->h_proto) < 1536) { | 231 | if(ntohs(hdr->h_proto) < ETH_P_802_3_MIN) { |
| 232 | int framelen = p->ule_sndu_len - ((p->ule_next_hdr+sizeof(struct ethhdr)) - p->ule_skb->data); | 232 | int framelen = p->ule_sndu_len - ((p->ule_next_hdr+sizeof(struct ethhdr)) - p->ule_skb->data); |
| 233 | /* A frame Type < 1536 for a bridged frame, introduces a LLC Length field. */ | 233 | /* A frame Type < ETH_P_802_3_MIN for a bridged frame, introduces a LLC Length field. */ |
| 234 | if(framelen != ntohs(hdr->h_proto)) { | 234 | if(framelen != ntohs(hdr->h_proto)) { |
| 235 | return -1; | 235 | return -1; |
| 236 | } | 236 | } |
| @@ -320,7 +320,7 @@ static int handle_ule_extensions( struct dvb_net_priv *p ) · 83 unmodified lines | |||
| 320 | (int) p->ule_sndu_type, l, total_ext_len); | 320 | (int) p->ule_sndu_type, l, total_ext_len); |
| 321 | #endif | 321 | #endif |
| 322 | 322 | ||
| 323 | } while (p->ule_sndu_type < 1536); | 323 | } while (p->ule_sndu_type < ETH_P_802_3_MIN); |
| 324 | 324 | ||
| 325 | return total_ext_len; | 325 | return total_ext_len; |
| 326 | } | 326 | } |
| @@ -712,7 +712,7 @@ static void dvb_net_ule( struct net_device *dev, const u8 *buf, size_t buf_len ) · 385 unmodified lines | |||
| 712 | } | 712 | } |
| 713 | 713 | ||
| 714 | /* Handle ULE Extension Headers. */ | 714 | /* Handle ULE Extension Headers. */ |
| 715 | if (priv->ule_sndu_type < 1536) { | 715 | if (priv->ule_sndu_type < ETH_P_802_3_MIN) { |
| 716 | /* There is an extension header. Handle it accordingly. */ | 716 | /* There is an extension header. Handle it accordingly. */ |
| 717 | int l = handle_ule_extensions(priv); | 717 | int l = handle_ule_extensions(priv); |
| 718 | if (l < 0) { | 718 | if (l < 0) { |
| @@ -151,6 +151,7 @@ config MACVTAP · 150 unmodified lines | |||
| 151 | config VXLAN | 151 | config VXLAN |
| 152 | tristate "Virtual eXtensible Local Area Network (VXLAN)" | 152 | tristate "Virtual eXtensible Local Area Network (VXLAN)" |
| 153 | depends on INET | 153 | depends on INET |
| 154 | select NET_IP_TUNNEL | ||
| 154 | ---help--- | 155 | ---help--- |
| 155 | This allows one to create vxlan virtual interfaces that provide | 156 | This allows one to create vxlan virtual interfaces that provide |
| 156 | Layer 2 Networks over Layer 3 Networks. VXLAN is often used | 157 | Layer 2 Networks over Layer 3 Networks. VXLAN is often used |
| @@ -106,20 +106,4 @@ config IPDDP_ENCAP · 105 unmodified lines | |||
| 106 | IP packets inside AppleTalk frames; this is useful if your Linux box | 106 | IP packets inside AppleTalk frames; this is useful if your Linux box |
| 107 | is stuck on an AppleTalk network (which hopefully contains a | 107 | is stuck on an AppleTalk network (which hopefully contains a |
| 108 | decapsulator somewhere). Please see | 108 | decapsulator somewhere). Please see |
| 109 | <file:Documentation/networking/ipddp.txt> for more information. If | 109 | <file:Documentation/networking/ipddp.txt> for more information. |
| 110 | you said Y to "AppleTalk-IP driver support" above and you say Y | ||
| 111 | here, then you cannot say Y to "AppleTalk-IP to IP Decapsulation | ||
| 112 | support", below. | ||
| 113 | |||
| 114 | config IPDDP_DECAP | ||
| 115 | bool "Appletalk-IP to IP Decapsulation support" | ||
| 116 | depends on IPDDP | ||
| 117 | help | ||
| 118 | If you say Y here, the AppleTalk-IP code will be able to decapsulate | ||
| 119 | AppleTalk-IP frames to IP packets; this is useful if you want your | ||
| 120 | Linux box to act as an Internet gateway for an AppleTalk network. | ||
| 121 | Please see <file:Documentation/networking/ipddp.txt> for more | ||
| 122 | information. If you said Y to "AppleTalk-IP driver support" above | ||
| 123 | and you say Y here, then you cannot say Y to "IP to AppleTalk-IP | ||
| 124 | Encapsulation support", above. | ||
| 125 | |||
| @@ -514,7 +514,7 @@ static void rlb_update_client(struct rlb_client_info *client_info) · 513 unmodified lines | |||
| 514 | skb->dev = client_info->slave->dev; | 514 | skb->dev = client_info->slave->dev; |
| 515 | 515 | ||
| 516 | if (client_info->tag) { | 516 | if (client_info->tag) { |
| 517 | skb = vlan_put_tag(skb, client_info->vlan_id); | 517 | skb = vlan_put_tag(skb, htons(ETH_P_8021Q), client_info->vlan_id); |
| 518 | if (!skb) { | 518 | if (!skb) { |
| 519 | pr_err("%s: Error: failed to insert VLAN tag\n", | 519 | pr_err("%s: Error: failed to insert VLAN tag\n", |
| 520 | client_info->slave->bond->dev->name); | 520 | client_info->slave->bond->dev->name); |
| @@ -1014,7 +1014,7 @@ static void alb_send_learning_packets(struct slave *slave, u8 mac_addr[]) · 493 unmodified lines | |||
| 1014 | continue; | 1014 | continue; |
| 1015 | } | 1015 | } |
| 1016 | 1016 | ||
| 1017 | skb = vlan_put_tag(skb, vlan->vlan_id); | 1017 | skb = vlan_put_tag(skb, htons(ETH_P_8021Q), vlan->vlan_id); |
| 1018 | if (!skb) { | 1018 | if (!skb) { |
| 1019 | pr_err("%s: Error: failed to insert VLAN tag\n", | 1019 | pr_err("%s: Error: failed to insert VLAN tag\n", |
| 1020 | bond->dev->name); | 1020 | bond->dev->name); |
| @@ -428,14 +428,15 @@ int bond_dev_queue_xmit(struct bonding *bond, struct sk_buff *skb, · 427 unmodified lines | |||
| 428 | * @bond_dev: bonding net device that got called | 428 | * @bond_dev: bonding net device that got called |
| 429 | * @vid: vlan id being added | 429 | * @vid: vlan id being added |
| 430 | */ | 430 | */ |
| 431 | static int bond_vlan_rx_add_vid(struct net_device *bond_dev, uint16_t vid) | 431 | static int bond_vlan_rx_add_vid(struct net_device *bond_dev, |
| 432 | __be16 proto, u16 vid) | ||
| 432 | { | 433 | { |
| 433 | struct bonding *bond = netdev_priv(bond_dev); | 434 | struct bonding *bond = netdev_priv(bond_dev); |
| 434 | struct slave *slave, *stop_at; | 435 | struct slave *slave, *stop_at; |
| 435 | int i, res; | 436 | int i, res; |
| 436 | 437 | ||
| 437 | bond_for_each_slave(bond, slave, i) { | 438 | bond_for_each_slave(bond, slave, i) { |
| 438 | res = vlan_vid_add(slave->dev, vid); | 439 | res = vlan_vid_add(slave->dev, proto, vid); |
| 439 | if (res) | 440 | if (res) |
| 440 | goto unwind; | 441 | goto unwind; |
| 441 | } | 442 | } |
| @@ -453,7 +454,7 @@ unwind: · 11 unmodified lines | |||
| 453 | /* unwind from head to the slave that failed */ | 454 | /* unwind from head to the slave that failed */ |
| 454 | stop_at = slave; | 455 | stop_at = slave; |
| 455 | bond_for_each_slave_from_to(bond, slave, i, bond->first_slave, stop_at) | 456 | bond_for_each_slave_from_to(bond, slave, i, bond->first_slave, stop_at) |
| 456 | vlan_vid_del(slave->dev, vid); | 457 | vlan_vid_del(slave->dev, proto, vid); |
| 457 | 458 | ||
| 458 | return res; | 459 | return res; |
| 459 | } | 460 | } |
| @@ -463,14 +464,15 @@ unwind: · 3 unmodified lines | |||
| 463 | * @bond_dev: bonding net device that got called | 464 | * @bond_dev: bonding net device that got called |
| 464 | * @vid: vlan id being removed | 465 | * @vid: vlan id being removed |
| 465 | */ | 466 | */ |
| 466 | static int bond_vlan_rx_kill_vid(struct net_device *bond_dev, uint16_t vid) | 467 | static int bond_vlan_rx_kill_vid(struct net_device *bond_dev, |
| 468 | __be16 proto, u16 vid) | ||
| 467 | { | 469 | { |
| 468 | struct bonding *bond = netdev_priv(bond_dev); | 470 | struct bonding *bond = netdev_priv(bond_dev); |
| 469 | struct slave *slave; | 471 | struct slave *slave; |
| 470 | int i, res; | 472 | int i, res; |
| 471 | 473 | ||
| 472 | bond_for_each_slave(bond, slave, i) | 474 | bond_for_each_slave(bond, slave, i) |
| 473 | vlan_vid_del(slave->dev, vid); | 475 | vlan_vid_del(slave->dev, proto, vid); |
| 474 | 476 | ||
| 475 | res = bond_del_vlan(bond, vid); | 477 | res = bond_del_vlan(bond, vid); |
| 476 | if (res) { | 478 | if (res) { |
| @@ -488,7 +490,8 @@ static void bond_add_vlans_on_slave(struct bonding *bond, struct net_device *sla · 11 unmodified lines | |||
| 488 | int res; | 490 | int res; |
| 489 | 491 | ||
| 490 | list_for_each_entry(vlan, &bond->vlan_list, vlan_list) { | 492 | list_for_each_entry(vlan, &bond->vlan_list, vlan_list) { |
| 491 | res = vlan_vid_add(slave_dev, vlan->vlan_id); | 493 | res = vlan_vid_add(slave_dev, htons(ETH_P_8021Q), |
| 494 | vlan->vlan_id); | ||
| 492 | if (res) | 495 | if (res) |
| 493 | pr_warning("%s: Failed to add vlan id %d to device %s\n", | 496 | pr_warning("%s: Failed to add vlan id %d to device %s\n", |
| 494 | bond->dev->name, vlan->vlan_id, | 497 | bond->dev->name, vlan->vlan_id, |
| @@ -504,7 +507,7 @@ static void bond_del_vlans_from_slave(struct bonding *bond, · 9 unmodified lines | |||
| 504 | list_for_each_entry(vlan, &bond->vlan_list, vlan_list) { | 507 | list_for_each_entry(vlan, &bond->vlan_list, vlan_list) { |
| 505 | if (!vlan->vlan_id) | 508 | if (!vlan->vlan_id) |
| 506 | continue; | 509 | continue; |
| 507 | vlan_vid_del(slave_dev, vlan->vlan_id); | 510 | vlan_vid_del(slave_dev, htons(ETH_P_8021Q), vlan->vlan_id); |
| 508 | } | 511 | } |
| 509 | } | 512 | } |
| 510 | 513 | ||
| @@ -779,7 +782,7 @@ static void bond_resend_igmp_join_requests(struct bonding *bond) · 268 unmodified lines | |||
| 779 | 782 | ||
| 780 | /* rejoin all groups on vlan devices */ | 783 | /* rejoin all groups on vlan devices */ |
| 781 | list_for_each_entry(vlan, &bond->vlan_list, vlan_list) { | 784 | list_for_each_entry(vlan, &bond->vlan_list, vlan_list) { |
| 782 | vlan_dev = __vlan_find_dev_deep(bond_dev, | 785 | vlan_dev = __vlan_find_dev_deep(bond_dev, htons(ETH_P_8021Q), |
| 783 | vlan->vlan_id); | 786 | vlan->vlan_id); |
| 784 | if (vlan_dev) | 787 | if (vlan_dev) |
| 785 | __bond_resend_igmp_join_requests(vlan_dev); | 788 | __bond_resend_igmp_join_requests(vlan_dev); |
| @@ -796,9 +799,8 @@ static void bond_resend_igmp_join_requests_delayed(struct work_struct *work) · 10 unmodified lines | |||
| 796 | { | 799 | { |
| 797 | struct bonding *bond = container_of(work, struct bonding, | 800 | struct bonding *bond = container_of(work, struct bonding, |
| 798 | mcast_work.work); | 801 | mcast_work.work); |
| 799 | rcu_read_lock(); | 802 | |
| 800 | bond_resend_igmp_join_requests(bond); | 803 | bond_resend_igmp_join_requests(bond); |
| 801 | rcu_read_unlock(); | ||
| 802 | } | 804 | } |
| 803 | 805 | ||
| 804 | /* | 806 | /* |
| @@ -1915,14 +1917,16 @@ err_detach: · 1110 unmodified lines | |||
| 1915 | bond_detach_slave(bond, new_slave); | 1917 | bond_detach_slave(bond, new_slave); |
| 1916 | if (bond->primary_slave == new_slave) | 1918 | if (bond->primary_slave == new_slave) |
| 1917 | bond->primary_slave = NULL; | 1919 | bond->primary_slave = NULL; |
| 1918 | write_unlock_bh(&bond->lock); | ||
| 1919 | if (bond->curr_active_slave == new_slave) { | 1920 | if (bond->curr_active_slave == new_slave) { |
| 1921 | bond_change_active_slave(bond, NULL); | ||
| 1922 | write_unlock_bh(&bond->lock); | ||
| 1920 | read_lock(&bond->lock); | 1923 | read_lock(&bond->lock); |
| 1921 | write_lock_bh(&bond->curr_slave_lock); | 1924 | write_lock_bh(&bond->curr_slave_lock); |
| 1922 | bond_change_active_slave(bond, NULL); | ||
| 1923 | bond_select_active_slave(bond); | 1925 | bond_select_active_slave(bond); |
| 1924 | write_unlock_bh(&bond->curr_slave_lock); | 1926 | write_unlock_bh(&bond->curr_slave_lock); |
| 1925 | read_unlock(&bond->lock); | 1927 | read_unlock(&bond->lock); |
| 1928 | } else { | ||
| 1929 | write_unlock_bh(&bond->lock); | ||
| 1926 | } | 1930 | } |
| 1927 | slave_disable_netpoll(new_slave); | 1931 | slave_disable_netpoll(new_slave); |
| 1928 | 1932 | ||
| @@ -2532,7 +2536,8 @@ static int bond_has_this_ip(struct bonding *bond, __be32 ip) · 603 unmodified lines | |||
| 2532 | 2536 | ||
| 2533 | list_for_each_entry(vlan, &bond->vlan_list, vlan_list) { | 2537 | list_for_each_entry(vlan, &bond->vlan_list, vlan_list) { |
| 2534 | rcu_read_lock(); | 2538 | rcu_read_lock(); |
| 2535 | vlan_dev = __vlan_find_dev_deep(bond->dev, vlan->vlan_id); | 2539 | vlan_dev = __vlan_find_dev_deep(bond->dev, htons(ETH_P_8021Q), |
| 2540 | vlan->vlan_id); | ||
| 2536 | rcu_read_unlock(); | 2541 | rcu_read_unlock(); |
| 2537 | if (vlan_dev && ip == bond_confirm_addr(vlan_dev, 0, ip)) | 2542 | if (vlan_dev && ip == bond_confirm_addr(vlan_dev, 0, ip)) |
| 2538 | return 1; | 2543 | return 1; |
| @@ -2561,7 +2566,7 @@ static void bond_arp_send(struct net_device *slave_dev, int arp_op, __be32 dest_ · 22 unmodified lines | |||
| 2561 | return; | 2566 | return; |
| 2562 | } | 2567 | } |
| 2563 | if (vlan_id) { | 2568 | if (vlan_id) { |
| 2564 | skb = vlan_put_tag(skb, vlan_id); | 2569 | skb = vlan_put_tag(skb, htons(ETH_P_8021Q), vlan_id); |
| 2565 | if (!skb) { | 2570 | if (!skb) { |
| 2566 | pr_err("failed to insert VLAN tag\n"); | 2571 | pr_err("failed to insert VLAN tag\n"); |
| 2567 | return; | 2572 | return; |
| @@ -2623,6 +2628,7 @@ static void bond_arp_send_all(struct bonding *bond, struct slave *slave) · 55 unmodified lines | |||
| 2623 | list_for_each_entry(vlan, &bond->vlan_list, vlan_list) { | 2628 | list_for_each_entry(vlan, &bond->vlan_list, vlan_list) { |
| 2624 | rcu_read_lock(); | 2629 | rcu_read_lock(); |
| 2625 | vlan_dev = __vlan_find_dev_deep(bond->dev, | 2630 | vlan_dev = __vlan_find_dev_deep(bond->dev, |
| 2631 | htons(ETH_P_8021Q), | ||
| 2626 | vlan->vlan_id); | 2632 | vlan->vlan_id); |
| 2627 | rcu_read_unlock(); | 2633 | rcu_read_unlock(); |
| 2628 | if (vlan_dev == rt->dst.dev) { | 2634 | if (vlan_dev == rt->dst.dev) { |
| @@ -4258,6 +4264,37 @@ void bond_set_mode_ops(struct bonding *bond, int mode) · 1629 unmodified lines | |||
| 4258 | } | 4264 | } |
| 4259 | } | 4265 | } |
| 4260 | 4266 | ||
| 4267 | static int bond_ethtool_get_settings(struct net_device *bond_dev, | ||
| 4268 | struct ethtool_cmd *ecmd) | ||
| 4269 | { | ||
| 4270 | struct bonding *bond = netdev_priv(bond_dev); | ||
| 4271 | struct slave *slave; | ||
| 4272 | int i; | ||
| 4273 | unsigned long speed = 0; | ||
| 4274 | |||
| 4275 | ecmd->duplex = DUPLEX_UNKNOWN; | ||
| 4276 | ecmd->port = PORT_OTHER; | ||
| 4277 | |||
| 4278 | /* Since SLAVE_IS_OK returns false for all inactive or down slaves, we | ||
| 4279 | * do not need to check mode. Though link speed might not represent | ||
| 4280 | * the true receive or transmit bandwidth (not all modes are symmetric) | ||
| 4281 | * this is an accurate maximum. | ||
| 4282 | */ | ||
| 4283 | read_lock(&bond->lock); | ||
| 4284 | bond_for_each_slave(bond, slave, i) { | ||
| 4285 | if (SLAVE_IS_OK(slave)) { | ||
| 4286 | if (slave->speed != SPEED_UNKNOWN) | ||
| 4287 | speed += slave->speed; | ||
| 4288 | if (ecmd->duplex == DUPLEX_UNKNOWN && | ||
| 4289 | slave->duplex != DUPLEX_UNKNOWN) | ||
| 4290 | ecmd->duplex = slave->duplex; | ||
| 4291 | } | ||
| 4292 | } | ||
| 4293 | ethtool_cmd_speed_set(ecmd, speed ? : SPEED_UNKNOWN); | ||
| 4294 | read_unlock(&bond->lock); | ||
| 4295 | return 0; | ||
| 4296 | } | ||
| 4297 | |||
| 4261 | static void bond_ethtool_get_drvinfo(struct net_device *bond_dev, | 4298 | static void bond_ethtool_get_drvinfo(struct net_device *bond_dev, |
| 4262 | struct ethtool_drvinfo *drvinfo) | 4299 | struct ethtool_drvinfo *drvinfo) |
| 4263 | { | 4300 | { |
| @@ -4269,6 +4306,7 @@ static void bond_ethtool_get_drvinfo(struct net_device *bond_dev, · 5 unmodified lines | |||
| 4269 | 4306 | ||
| 4270 | static const struct ethtool_ops bond_ethtool_ops = { | 4307 | static const struct ethtool_ops bond_ethtool_ops = { |
| 4271 | .get_drvinfo = bond_ethtool_get_drvinfo, | 4308 | .get_drvinfo = bond_ethtool_get_drvinfo, |
| 4309 | .get_settings = bond_ethtool_get_settings, | ||
| 4272 | .get_link = ethtool_op_get_link, | 4310 | .get_link = ethtool_op_get_link, |
| 4273 | }; | 4311 | }; |
| 4274 | 4312 | ||
| @@ -4359,9 +4397,9 @@ static void bond_setup(struct net_device *bond_dev) · 84 unmodified lines | |||
| 4359 | */ | 4397 | */ |
| 4360 | 4398 | ||
| 4361 | bond_dev->hw_features = BOND_VLAN_FEATURES | | 4399 | bond_dev->hw_features = BOND_VLAN_FEATURES | |
| 4362 | NETIF_F_HW_VLAN_TX | | 4400 | NETIF_F_HW_VLAN_CTAG_TX | |
| 4363 | NETIF_F_HW_VLAN_RX | | 4401 | NETIF_F_HW_VLAN_CTAG_RX | |
| 4364 | NETIF_F_HW_VLAN_FILTER; | 4402 | NETIF_F_HW_VLAN_CTAG_FILTER; |
| 4365 | 4403 | ||
| 4366 | bond_dev->hw_features &= ~(NETIF_F_ALL_CSUM & ~NETIF_F_HW_CSUM); | 4404 | bond_dev->hw_features &= ~(NETIF_F_ALL_CSUM & ~NETIF_F_HW_CSUM); |
| 4367 | bond_dev->features |= bond_dev->hw_features; | 4405 | bond_dev->features |= bond_dev->hw_features; |
| @@ -32,13 +32,6 @@ config CAIF_SPI_SYNC · 31 unmodified lines | |||
| 32 | help to synchronize to the next transfer in case of over or under-runs. | 32 | help to synchronize to the next transfer in case of over or under-runs. |
| 33 | This option also needs to be enabled on the modem. | 33 | This option also needs to be enabled on the modem. |
| 34 | 34 | ||
| 35 | config CAIF_SHM | ||
| 36 | tristate "CAIF shared memory protocol driver" | ||
| 37 | depends on CAIF && U5500_MBOX | ||
| 38 | default n | ||
| 39 | ---help--- | ||
| 40 | The CAIF shared memory protocol driver for the STE UX5500 platform. | ||
| 41 | |||
| 42 | config CAIF_HSI | 35 | config CAIF_HSI |
| 43 | tristate "CAIF HSI transport driver" | 36 | tristate "CAIF HSI transport driver" |
| 44 | depends on CAIF | 37 | depends on CAIF |
| @@ -7,9 +7,5 @@ obj-$(CONFIG_CAIF_TTY) += caif_serial.o · 6 unmodified lines | |||
| 7 | cfspi_slave-objs := caif_spi.o caif_spi_slave.o | 7 | cfspi_slave-objs := caif_spi.o caif_spi_slave.o |
| 8 | obj-$(CONFIG_CAIF_SPI_SLAVE) += cfspi_slave.o | 8 | obj-$(CONFIG_CAIF_SPI_SLAVE) += cfspi_slave.o |
| 9 | 9 | ||
| 10 | # Shared memory | ||
| 11 | caif_shm-objs := caif_shmcore.o caif_shm_u5500.o | ||
| 12 | obj-$(CONFIG_CAIF_SHM) += caif_shm.o | ||
| 13 | |||
| 14 | # HSI interface | 10 | # HSI interface |
| 15 | obj-$(CONFIG_CAIF_HSI) += caif_hsi.o | 11 | obj-$(CONFIG_CAIF_HSI) += caif_hsi.o |
| @@ -1,8 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson AB 2010 | 2 | * Copyright (C) ST-Ericsson AB 2010 |
| 3 | * Contact: Sjur Brendeland / sjur.brandeland@stericsson.com | 3 | * Author: Daniel Martensson |
| 4 | * Author: Daniel Martensson / daniel.martensson@stericsson.com | 4 | * Dmitry.Tarnyagin / dmitry.tarnyagin@lockless.no |
| 5 | * Dmitry.Tarnyagin / dmitry.tarnyagin@stericsson.com | ||
| 6 | * License terms: GNU General Public License (GPL) version 2. | 5 | * License terms: GNU General Public License (GPL) version 2. |
| 7 | */ | 6 | */ |
| 8 | 7 | ||
| @@ -25,7 +24,7 @@ · 16 unmodified lines | |||
| 25 | #include <net/caif/caif_hsi.h> | 24 | #include <net/caif/caif_hsi.h> |
| 26 | 25 | ||
| 27 | MODULE_LICENSE("GPL"); | 26 | MODULE_LICENSE("GPL"); |
| 28 | MODULE_AUTHOR("Daniel Martensson<daniel.martensson@stericsson.com>"); | 27 | MODULE_AUTHOR("Daniel Martensson"); |
| 29 | MODULE_DESCRIPTION("CAIF HSI driver"); | 28 | MODULE_DESCRIPTION("CAIF HSI driver"); |
| 30 | 29 | ||
| 31 | /* Returns the number of padding bytes for alignment. */ | 30 | /* Returns the number of padding bytes for alignment. */ |
| @@ -1,6 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson AB 2010 | 2 | * Copyright (C) ST-Ericsson AB 2010 |
| 3 | * Author: Sjur Brendeland / sjur.brandeland@stericsson.com | 3 | * Author: Sjur Brendeland |
| 4 | * License terms: GNU General Public License (GPL) version 2 | 4 | * License terms: GNU General Public License (GPL) version 2 |
| 5 | */ | 5 | */ |
| 6 | 6 | ||
| @@ -21,7 +21,7 @@ · 14 unmodified lines | |||
| 21 | #include <linux/debugfs.h> | 21 | #include <linux/debugfs.h> |
| 22 | 22 | ||
| 23 | MODULE_LICENSE("GPL"); | 23 | MODULE_LICENSE("GPL"); |
| 24 | MODULE_AUTHOR("Sjur Brendeland<sjur.brandeland@stericsson.com>"); | 24 | MODULE_AUTHOR("Sjur Brendeland"); |
| 25 | MODULE_DESCRIPTION("CAIF serial device TTY line discipline"); | 25 | MODULE_DESCRIPTION("CAIF serial device TTY line discipline"); |
| 26 | MODULE_LICENSE("GPL"); | 26 | MODULE_LICENSE("GPL"); |
| 27 | MODULE_ALIAS_LDISC(N_CAIF); | 27 | MODULE_ALIAS_LDISC(N_CAIF); |
| @@ -1,128 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson AB 2010 | ||
| 3 | * Contact: Sjur Brendeland / sjur.brandeland@stericsson.com | ||
| 4 | * Author: Amarnath Revanna / amarnath.bangalore.revanna@stericsson.com | ||
| 5 | * License terms: GNU General Public License (GPL) version 2 | ||
| 6 | */ | ||
| 7 | |||
| 8 | #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt | ||
| 9 | |||
| 10 | #include <linux/init.h> | ||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/netdevice.h> | ||
| 13 | #include <mach/mbox-db5500.h> | ||
| 14 | #include <net/caif/caif_shm.h> | ||
| 15 | |||
| 16 | MODULE_LICENSE("GPL"); | ||
| 17 | MODULE_DESCRIPTION("CAIF Shared Memory protocol driver"); | ||
| 18 | |||
| 19 | #define MAX_SHM_INSTANCES 1 | ||
| 20 | |||
| 21 | enum { | ||
| 22 | MBX_ACC0, | ||
| 23 | MBX_ACC1, | ||
| 24 | MBX_DSP | ||
| 25 | }; | ||
| 26 | |||
| 27 | static struct shmdev_layer shmdev_lyr[MAX_SHM_INSTANCES]; | ||
| 28 | |||
| 29 | static unsigned int shm_start; | ||
| 30 | static unsigned int shm_size; | ||
| 31 | |||
| 32 | module_param(shm_size, uint , 0440); | ||
| 33 | MODULE_PARM_DESC(shm_total_size, "Start of SHM shared memory"); | ||
| 34 | |||
| 35 | module_param(shm_start, uint , 0440); | ||
| 36 | MODULE_PARM_DESC(shm_total_start, "Total Size of SHM shared memory"); | ||
| 37 | |||
| 38 | static int shmdev_send_msg(u32 dev_id, u32 mbx_msg) | ||
| 39 | { | ||
| 40 | /* Always block until msg is written successfully */ | ||
| 41 | mbox_send(shmdev_lyr[dev_id].hmbx, mbx_msg, true); | ||
| 42 | return 0; | ||
| 43 | } | ||
| 44 | |||
| 45 | static int shmdev_mbx_setup(void *pshmdrv_cb, struct shmdev_layer *pshm_dev, | ||
| 46 | void *pshm_drv) | ||
| 47 | { | ||
| 48 | /* | ||
| 49 | * For UX5500, we have only 1 SHM instance which uses MBX0 | ||
| 50 | * for communication with the peer modem | ||
| 51 | */ | ||
| 52 | pshm_dev->hmbx = mbox_setup(MBX_ACC0, pshmdrv_cb, pshm_drv); | ||
| 53 | |||
| 54 | if (!pshm_dev->hmbx) | ||
| 55 | return -ENODEV; | ||
| 56 | else | ||
| 57 | return 0; | ||
| 58 | } | ||
| 59 | |||
| 60 | static int __init caif_shmdev_init(void) | ||
| 61 | { | ||
| 62 | int i, result; | ||
| 63 | |||
| 64 | /* Loop is currently overkill, there is only one instance */ | ||
| 65 | for (i = 0; i < MAX_SHM_INSTANCES; i++) { | ||
| 66 | |||
| 67 | shmdev_lyr[i].shm_base_addr = shm_start; | ||
| 68 | shmdev_lyr[i].shm_total_sz = shm_size; | ||
| 69 | |||
| 70 | if (((char *)shmdev_lyr[i].shm_base_addr == NULL) | ||
| 71 | || (shmdev_lyr[i].shm_total_sz <= 0)) { | ||
| 72 | pr_warn("ERROR," | ||
| 73 | "Shared memory Address and/or Size incorrect" | ||
| 74 | ", Bailing out ...\n"); | ||
| 75 | result = -EINVAL; | ||
| 76 | goto clean; | ||
| 77 | } | ||
| 78 | |||
| 79 | pr_info("SHM AREA (instance %d) STARTS" | ||
| 80 | " AT %p\n", i, (char *)shmdev_lyr[i].shm_base_addr); | ||
| 81 | |||
| 82 | shmdev_lyr[i].shm_id = i; | ||
| 83 | shmdev_lyr[i].pshmdev_mbxsend = shmdev_send_msg; | ||
| 84 | shmdev_lyr[i].pshmdev_mbxsetup = shmdev_mbx_setup; | ||
| 85 | |||
| 86 | /* | ||
| 87 | * Finally, CAIF core module is called with details in place: | ||
| 88 | * 1. SHM base address | ||
| 89 | * 2. SHM size | ||
| 90 | * 3. MBX handle | ||
| 91 | */ | ||
| 92 | result = caif_shmcore_probe(&shmdev_lyr[i]); | ||
| 93 | if (result) { | ||
| 94 | pr_warn("ERROR[%d]," | ||
| 95 | "Could not probe SHM core (instance %d)" | ||
| 96 | " Bailing out ...\n", result, i); | ||
| 97 | goto clean; | ||
| 98 | } | ||
| 99 | } | ||
| 100 | |||
| 101 | return 0; | ||
| 102 | |||
| 103 | clean: | ||
| 104 | /* | ||
| 105 | * For now, we assume that even if one instance of SHM fails, we bail | ||
| 106 | * out of the driver support completely. For this, we need to release | ||
| 107 | * any memory allocated and unregister any instance of SHM net device. | ||
| 108 | */ | ||
| 109 | for (i = 0; i < MAX_SHM_INSTANCES; i++) { | ||
| 110 | if (shmdev_lyr[i].pshm_netdev) | ||
| 111 | unregister_netdev(shmdev_lyr[i].pshm_netdev); | ||
| 112 | } | ||
| 113 | return result; | ||
| 114 | } | ||
| 115 | |||
| 116 | static void __exit caif_shmdev_exit(void) | ||
| 117 | { | ||
| 118 | int i; | ||
| 119 | |||
| 120 | for (i = 0; i < MAX_SHM_INSTANCES; i++) { | ||
| 121 | caif_shmcore_remove(shmdev_lyr[i].pshm_netdev); | ||
| 122 | kfree((void *)shmdev_lyr[i].shm_base_addr); | ||
| 123 | } | ||
| 124 | |||
| 125 | } | ||
| 126 | |||
| 127 | module_init(caif_shmdev_init); | ||
| 128 | module_exit(caif_shmdev_exit); | ||
| @@ -1,747 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson AB 2010 | ||
| 3 | * Contact: Sjur Brendeland / sjur.brandeland@stericsson.com | ||
| 4 | * Authors: Amarnath Revanna / amarnath.bangalore.revanna@stericsson.com, | ||
| 5 | * Daniel Martensson / daniel.martensson@stericsson.com | ||
| 6 | * License terms: GNU General Public License (GPL) version 2 | ||
| 7 | */ | ||
| 8 | |||
| 9 | #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt | ||
| 10 | |||
| 11 | #include <linux/spinlock.h> | ||
| 12 | #include <linux/sched.h> | ||
| 13 | #include <linux/list.h> | ||
| 14 | #include <linux/netdevice.h> | ||
| 15 | #include <linux/if_arp.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | |||
| 18 | #include <net/caif/caif_device.h> | ||
| 19 | #include <net/caif/caif_shm.h> | ||
| 20 | |||
| 21 | #define NR_TX_BUF 6 | ||
| 22 | #define NR_RX_BUF 6 | ||
| 23 | #define TX_BUF_SZ 0x2000 | ||
| 24 | #define RX_BUF_SZ 0x2000 | ||
| 25 | |||
| 26 | #define CAIF_NEEDED_HEADROOM 32 | ||
| 27 | |||
| 28 | #define CAIF_FLOW_ON 1 | ||
| 29 | #define CAIF_FLOW_OFF 0 | ||
| 30 | |||
| 31 | #define LOW_WATERMARK 3 | ||
| 32 | #define HIGH_WATERMARK 4 | ||
| 33 | |||
| 34 | /* Maximum number of CAIF buffers per shared memory buffer. */ | ||
| 35 | #define SHM_MAX_FRMS_PER_BUF 10 | ||
| 36 | |||
| 37 | /* | ||
| 38 | * Size in bytes of the descriptor area | ||
| 39 | * (With end of descriptor signalling) | ||
| 40 | */ | ||
| 41 | #define SHM_CAIF_DESC_SIZE ((SHM_MAX_FRMS_PER_BUF + 1) * \ | ||
| 42 | sizeof(struct shm_pck_desc)) | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Offset to the first CAIF frame within a shared memory buffer. | ||
| 46 | * Aligned on 32 bytes. | ||
| 47 | */ | ||
| 48 | #define SHM_CAIF_FRM_OFS (SHM_CAIF_DESC_SIZE + (SHM_CAIF_DESC_SIZE % 32)) | ||
| 49 | |||
| 50 | /* Number of bytes for CAIF shared memory header. */ | ||
| 51 | #define SHM_HDR_LEN 1 | ||
| 52 | |||
| 53 | /* Number of padding bytes for the complete CAIF frame. */ | ||
| 54 | #define SHM_FRM_PAD_LEN 4 | ||
| 55 | |||
| 56 | #define CAIF_MAX_MTU 4096 | ||
| 57 | |||
| 58 | #define SHM_SET_FULL(x) (((x+1) & 0x0F) << 0) | ||
| 59 | #define SHM_GET_FULL(x) (((x >> 0) & 0x0F) - 1) | ||
| 60 | |||
| 61 | #define SHM_SET_EMPTY(x) (((x+1) & 0x0F) << 4) | ||
| 62 | #define SHM_GET_EMPTY(x) (((x >> 4) & 0x0F) - 1) | ||
| 63 | |||
| 64 | #define SHM_FULL_MASK (0x0F << 0) | ||
| 65 | #define SHM_EMPTY_MASK (0x0F << 4) | ||
| 66 | |||
| 67 | struct shm_pck_desc { | ||
| 68 | /* | ||
| 69 | * Offset from start of shared memory area to start of | ||
| 70 | * shared memory CAIF frame. | ||
| 71 | */ | ||
| 72 | u32 frm_ofs; | ||
| 73 | u32 frm_len; | ||
| 74 | }; | ||
| 75 | |||
| 76 | struct buf_list { | ||
| 77 | unsigned char *desc_vptr; | ||
| 78 | u32 phy_addr; | ||
| 79 | u32 index; | ||
| 80 | u32 len; | ||
| 81 | u32 frames; | ||
| 82 | u32 frm_ofs; | ||
| 83 | struct list_head list; | ||
| 84 | }; | ||
| 85 | |||
| 86 | struct shm_caif_frm { | ||
| 87 | /* Number of bytes of padding before the CAIF frame. */ | ||
| 88 | u8 hdr_ofs; | ||
| 89 | }; | ||
| 90 | |||
| 91 | struct shmdrv_layer { | ||
| 92 | /* caif_dev_common must always be first in the structure*/ | ||
| 93 | struct caif_dev_common cfdev; | ||
| 94 | |||
| 95 | u32 shm_tx_addr; | ||
| 96 | u32 shm_rx_addr; | ||
| 97 | u32 shm_base_addr; | ||
| 98 | u32 tx_empty_available; | ||
| 99 | spinlock_t lock; | ||
| 100 | |||
| 101 | struct list_head tx_empty_list; | ||
| 102 | struct list_head tx_pend_list; | ||
| 103 | struct list_head tx_full_list; | ||
| 104 | struct list_head rx_empty_list; | ||
| 105 | struct list_head rx_pend_list; | ||
| 106 | struct list_head rx_full_list; | ||
| 107 | |||
| 108 | struct workqueue_struct *pshm_tx_workqueue; | ||
| 109 | struct workqueue_struct *pshm_rx_workqueue; | ||
| 110 | |||
| 111 | struct work_struct shm_tx_work; | ||
| 112 | struct work_struct shm_rx_work; | ||
| 113 | |||
| 114 | struct sk_buff_head sk_qhead; | ||
| 115 | struct shmdev_layer *pshm_dev; | ||
| 116 | }; | ||
| 117 | |||
| 118 | static int shm_netdev_open(struct net_device *shm_netdev) | ||
| 119 | { | ||
| 120 | netif_wake_queue(shm_netdev); | ||
| 121 | return 0; | ||
| 122 | } | ||
| 123 | |||
| 124 | static int shm_netdev_close(struct net_device *shm_netdev) | ||
| 125 | { | ||
| 126 | netif_stop_queue(shm_netdev); | ||
| 127 | return 0; | ||
| 128 | } | ||
| 129 | |||
| 130 | int caif_shmdrv_rx_cb(u32 mbx_msg, void *priv) | ||
| 131 | { | ||
| 132 | struct buf_list *pbuf; | ||
| 133 | struct shmdrv_layer *pshm_drv; | ||
| 134 | struct list_head *pos; | ||
| 135 | u32 avail_emptybuff = 0; | ||
| 136 | unsigned long flags = 0; | ||
| 137 | |||
| 138 | pshm_drv = priv; | ||
| 139 | |||
| 140 | /* Check for received buffers. */ | ||
| 141 | if (mbx_msg & SHM_FULL_MASK) { | ||
| 142 | int idx; | ||
| 143 | |||
| 144 | spin_lock_irqsave(&pshm_drv->lock, flags); | ||
| 145 | |||
| 146 | /* Check whether we have any outstanding buffers. */ | ||
| 147 | if (list_empty(&pshm_drv->rx_empty_list)) { | ||
| 148 | |||
| 149 | /* Release spin lock. */ | ||
| 150 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 151 | |||
| 152 | /* We print even in IRQ context... */ | ||
| 153 | pr_warn("No empty Rx buffers to fill: " | ||
| 154 | "mbx_msg:%x\n", mbx_msg); | ||
| 155 | |||
| 156 | /* Bail out. */ | ||
| 157 | goto err_sync; | ||
| 158 | } | ||
| 159 | |||
| 160 | pbuf = | ||
| 161 | list_entry(pshm_drv->rx_empty_list.next, | ||
| 162 | struct buf_list, list); | ||
| 163 | idx = pbuf->index; | ||
| 164 | |||
| 165 | /* Check buffer synchronization. */ | ||
| 166 | if (idx != SHM_GET_FULL(mbx_msg)) { | ||
| 167 | |||
| 168 | /* We print even in IRQ context... */ | ||
| 169 | pr_warn( | ||
| 170 | "phyif_shm_mbx_msg_cb: RX full out of sync:" | ||
| 171 | " idx:%d, msg:%x SHM_GET_FULL(mbx_msg):%x\n", | ||
| 172 | idx, mbx_msg, SHM_GET_FULL(mbx_msg)); | ||
| 173 | |||
| 174 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 175 | |||
| 176 | /* Bail out. */ | ||
| 177 | goto err_sync; | ||
| 178 | } | ||
| 179 | |||
| 180 | list_del_init(&pbuf->list); | ||
| 181 | list_add_tail(&pbuf->list, &pshm_drv->rx_full_list); | ||
| 182 | |||
| 183 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 184 | |||
| 185 | /* Schedule RX work queue. */ | ||
| 186 | if (!work_pending(&pshm_drv->shm_rx_work)) | ||
| 187 | queue_work(pshm_drv->pshm_rx_workqueue, | ||
| 188 | &pshm_drv->shm_rx_work); | ||
| 189 | } | ||
| 190 | |||
| 191 | /* Check for emptied buffers. */ | ||
| 192 | if (mbx_msg & SHM_EMPTY_MASK) { | ||
| 193 | int idx; | ||
| 194 | |||
| 195 | spin_lock_irqsave(&pshm_drv->lock, flags); | ||
| 196 | |||
| 197 | /* Check whether we have any outstanding buffers. */ | ||
| 198 | if (list_empty(&pshm_drv->tx_full_list)) { | ||
| 199 | |||
| 200 | /* We print even in IRQ context... */ | ||
| 201 | pr_warn("No TX to empty: msg:%x\n", mbx_msg); | ||
| 202 | |||
| 203 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 204 | |||
| 205 | /* Bail out. */ | ||
| 206 | goto err_sync; | ||
| 207 | } | ||
| 208 | |||
| 209 | pbuf = | ||
| 210 | list_entry(pshm_drv->tx_full_list.next, | ||
| 211 | struct buf_list, list); | ||
| 212 | idx = pbuf->index; | ||
| 213 | |||
| 214 | /* Check buffer synchronization. */ | ||
| 215 | if (idx != SHM_GET_EMPTY(mbx_msg)) { | ||
| 216 | |||
| 217 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 218 | |||
| 219 | /* We print even in IRQ context... */ | ||
| 220 | pr_warn("TX empty " | ||
| 221 | "out of sync:idx:%d, msg:%x\n", idx, mbx_msg); | ||
| 222 | |||
| 223 | /* Bail out. */ | ||
| 224 | goto err_sync; | ||
| 225 | } | ||
| 226 | list_del_init(&pbuf->list); | ||
| 227 | |||
| 228 | /* Reset buffer parameters. */ | ||
| 229 | pbuf->frames = 0; | ||
| 230 | pbuf->frm_ofs = SHM_CAIF_FRM_OFS; | ||
| 231 | |||
| 232 | list_add_tail(&pbuf->list, &pshm_drv->tx_empty_list); | ||
| 233 | |||
| 234 | /* Check the available no. of buffers in the empty list */ | ||
| 235 | list_for_each(pos, &pshm_drv->tx_empty_list) | ||
| 236 | avail_emptybuff++; | ||
| 237 | |||
| 238 | /* Check whether we have to wake up the transmitter. */ | ||
| 239 | if ((avail_emptybuff > HIGH_WATERMARK) && | ||
| 240 | (!pshm_drv->tx_empty_available)) { | ||
| 241 | pshm_drv->tx_empty_available = 1; | ||
| 242 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 243 | pshm_drv->cfdev.flowctrl | ||
| 244 | (pshm_drv->pshm_dev->pshm_netdev, | ||
| 245 | CAIF_FLOW_ON); | ||
| 246 | |||
| 247 | |||
| 248 | /* Schedule the work queue. if required */ | ||
| 249 | if (!work_pending(&pshm_drv->shm_tx_work)) | ||
| 250 | queue_work(pshm_drv->pshm_tx_workqueue, | ||
| 251 | &pshm_drv->shm_tx_work); | ||
| 252 | } else | ||
| 253 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 254 | } | ||
| 255 | |||
| 256 | return 0; | ||
| 257 | |||
| 258 | err_sync: | ||
| 259 | return -EIO; | ||
| 260 | } | ||
| 261 | |||
| 262 | static void shm_rx_work_func(struct work_struct *rx_work) | ||
| 263 | { | ||
| 264 | struct shmdrv_layer *pshm_drv; | ||
| 265 | struct buf_list *pbuf; | ||
| 266 | unsigned long flags = 0; | ||
| 267 | struct sk_buff *skb; | ||
| 268 | char *p; | ||
| 269 | int ret; | ||
| 270 | |||
| 271 | pshm_drv = container_of(rx_work, struct shmdrv_layer, shm_rx_work); | ||
| 272 | |||
| 273 | while (1) { | ||
| 274 | |||
| 275 | struct shm_pck_desc *pck_desc; | ||
| 276 | |||
| 277 | spin_lock_irqsave(&pshm_drv->lock, flags); | ||
| 278 | |||
| 279 | /* Check for received buffers. */ | ||
| 280 | if (list_empty(&pshm_drv->rx_full_list)) { | ||
| 281 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 282 | break; | ||
| 283 | } | ||
| 284 | |||
| 285 | pbuf = | ||
| 286 | list_entry(pshm_drv->rx_full_list.next, struct buf_list, | ||
| 287 | list); | ||
| 288 | list_del_init(&pbuf->list); | ||
| 289 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 290 | |||
| 291 | /* Retrieve pointer to start of the packet descriptor area. */ | ||
| 292 | pck_desc = (struct shm_pck_desc *) pbuf->desc_vptr; | ||
| 293 | |||
| 294 | /* | ||
| 295 | * Check whether descriptor contains a CAIF shared memory | ||
| 296 | * frame. | ||
| 297 | */ | ||
| 298 | while (pck_desc->frm_ofs) { | ||
| 299 | unsigned int frm_buf_ofs; | ||
| 300 | unsigned int frm_pck_ofs; | ||
| 301 | unsigned int frm_pck_len; | ||
| 302 | /* | ||
| 303 | * Check whether offset is within buffer limits | ||
| 304 | * (lower). | ||
| 305 | */ | ||
| 306 | if (pck_desc->frm_ofs < | ||
| 307 | (pbuf->phy_addr - pshm_drv->shm_base_addr)) | ||
| 308 | break; | ||
| 309 | /* | ||
| 310 | * Check whether offset is within buffer limits | ||
| 311 | * (higher). | ||
| 312 | */ | ||
| 313 | if (pck_desc->frm_ofs > | ||
| 314 | ((pbuf->phy_addr - pshm_drv->shm_base_addr) + | ||
| 315 | pbuf->len)) | ||
| 316 | break; | ||
| 317 | |||
| 318 | /* Calculate offset from start of buffer. */ | ||
| 319 | frm_buf_ofs = | ||
| 320 | pck_desc->frm_ofs - (pbuf->phy_addr - | ||
| 321 | pshm_drv->shm_base_addr); | ||
| 322 | |||
| 323 | /* | ||
| 324 | * Calculate offset and length of CAIF packet while | ||
| 325 | * taking care of the shared memory header. | ||
| 326 | */ | ||
| 327 | frm_pck_ofs = | ||
| 328 | frm_buf_ofs + SHM_HDR_LEN + | ||
| 329 | (*(pbuf->desc_vptr + frm_buf_ofs)); | ||
| 330 | frm_pck_len = | ||
| 331 | (pck_desc->frm_len - SHM_HDR_LEN - | ||
| 332 | (*(pbuf->desc_vptr + frm_buf_ofs))); | ||
| 333 | |||
| 334 | /* Check whether CAIF packet is within buffer limits */ | ||
| 335 | if ((frm_pck_ofs + pck_desc->frm_len) > pbuf->len) | ||
| 336 | break; | ||
| 337 | |||
| 338 | /* Get a suitable CAIF packet and copy in data. */ | ||
| 339 | skb = netdev_alloc_skb(pshm_drv->pshm_dev->pshm_netdev, | ||
| 340 | frm_pck_len + 1); | ||
| 341 | |||
| 342 | if (skb == NULL) { | ||
| 343 | pr_info("OOM: Try next frame in descriptor\n"); | ||
| 344 | break; | ||
| 345 | } | ||
| 346 | |||
| 347 | p = skb_put(skb, frm_pck_len); | ||
| 348 | memcpy(p, pbuf->desc_vptr + frm_pck_ofs, frm_pck_len); | ||
| 349 | |||
| 350 | skb->protocol = htons(ETH_P_CAIF); | ||
| 351 | skb_reset_mac_header(skb); | ||
| 352 | skb->dev = pshm_drv->pshm_dev->pshm_netdev; | ||
| 353 | |||
| 354 | /* Push received packet up the stack. */ | ||
| 355 | ret = netif_rx_ni(skb); | ||
| 356 | |||
| 357 | if (!ret) { | ||
| 358 | pshm_drv->pshm_dev->pshm_netdev->stats. | ||
| 359 | rx_packets++; | ||
| 360 | pshm_drv->pshm_dev->pshm_netdev->stats. | ||
| 361 | rx_bytes += pck_desc->frm_len; | ||
| 362 | } else | ||
| 363 | ++pshm_drv->pshm_dev->pshm_netdev->stats. | ||
| 364 | rx_dropped; | ||
| 365 | /* Move to next packet descriptor. */ | ||
| 366 | pck_desc++; | ||
| 367 | } | ||
| 368 | |||
| 369 | spin_lock_irqsave(&pshm_drv->lock, flags); | ||
| 370 | list_add_tail(&pbuf->list, &pshm_drv->rx_pend_list); | ||
| 371 | |||
| 372 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 373 | |||
| 374 | } | ||
| 375 | |||
| 376 | /* Schedule the work queue. if required */ | ||
| 377 | if (!work_pending(&pshm_drv->shm_tx_work)) | ||
| 378 | queue_work(pshm_drv->pshm_tx_workqueue, &pshm_drv->shm_tx_work); | ||
| 379 | |||
| 380 | } | ||
| 381 | |||
| 382 | static void shm_tx_work_func(struct work_struct *tx_work) | ||
| 383 | { | ||
| 384 | u32 mbox_msg; | ||
| 385 | unsigned int frmlen, avail_emptybuff, append = 0; | ||
| 386 | unsigned long flags = 0; | ||
| 387 | struct buf_list *pbuf = NULL; | ||
| 388 | struct shmdrv_layer *pshm_drv; | ||
| 389 | struct shm_caif_frm *frm; | ||
| 390 | struct sk_buff *skb; | ||
| 391 | struct shm_pck_desc *pck_desc; | ||
| 392 | struct list_head *pos; | ||
| 393 | |||
| 394 | pshm_drv = container_of(tx_work, struct shmdrv_layer, shm_tx_work); | ||
| 395 | |||
| 396 | do { | ||
| 397 | /* Initialize mailbox message. */ | ||
| 398 | mbox_msg = 0x00; | ||
| 399 | avail_emptybuff = 0; | ||
| 400 | |||
| 401 | spin_lock_irqsave(&pshm_drv->lock, flags); | ||
| 402 | |||
| 403 | /* Check for pending receive buffers. */ | ||
| 404 | if (!list_empty(&pshm_drv->rx_pend_list)) { | ||
| 405 | |||
| 406 | pbuf = list_entry(pshm_drv->rx_pend_list.next, | ||
| 407 | struct buf_list, list); | ||
| 408 | |||
| 409 | list_del_init(&pbuf->list); | ||
| 410 | list_add_tail(&pbuf->list, &pshm_drv->rx_empty_list); | ||
| 411 | /* | ||
| 412 | * Value index is never changed, | ||
| 413 | * so read access should be safe. | ||
| 414 | */ | ||
| 415 | mbox_msg |= SHM_SET_EMPTY(pbuf->index); | ||
| 416 | } | ||
| 417 | |||
| 418 | skb = skb_peek(&pshm_drv->sk_qhead); | ||
| 419 | |||
| 420 | if (skb == NULL) | ||
| 421 | goto send_msg; | ||
| 422 | /* Check the available no. of buffers in the empty list */ | ||
| 423 | list_for_each(pos, &pshm_drv->tx_empty_list) | ||
| 424 | avail_emptybuff++; | ||
| 425 | |||
| 426 | if ((avail_emptybuff < LOW_WATERMARK) && | ||
| 427 | pshm_drv->tx_empty_available) { | ||
| 428 | /* Update blocking condition. */ | ||
| 429 | pshm_drv->tx_empty_available = 0; | ||
| 430 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 431 | pshm_drv->cfdev.flowctrl | ||
| 432 | (pshm_drv->pshm_dev->pshm_netdev, | ||
| 433 | CAIF_FLOW_OFF); | ||
| 434 | spin_lock_irqsave(&pshm_drv->lock, flags); | ||
| 435 | } | ||
| 436 | /* | ||
| 437 | * We simply return back to the caller if we do not have space | ||
| 438 | * either in Tx pending list or Tx empty list. In this case, | ||
| 439 | * we hold the received skb in the skb list, waiting to | ||
| 440 | * be transmitted once Tx buffers become available | ||
| 441 | */ | ||
| 442 | if (list_empty(&pshm_drv->tx_empty_list)) | ||
| 443 | goto send_msg; | ||
| 444 | |||
| 445 | /* Get the first free Tx buffer. */ | ||
| 446 | pbuf = list_entry(pshm_drv->tx_empty_list.next, | ||
| 447 | struct buf_list, list); | ||
| 448 | do { | ||
| 449 | if (append) { | ||
| 450 | skb = skb_peek(&pshm_drv->sk_qhead); | ||
| 451 | if (skb == NULL) | ||
| 452 | break; | ||
| 453 | } | ||
| 454 | |||
| 455 | frm = (struct shm_caif_frm *) | ||
| 456 | (pbuf->desc_vptr + pbuf->frm_ofs); | ||
| 457 | |||
| 458 | frm->hdr_ofs = 0; | ||
| 459 | frmlen = 0; | ||
| 460 | frmlen += SHM_HDR_LEN + frm->hdr_ofs + skb->len; | ||
| 461 | |||
| 462 | /* Add tail padding if needed. */ | ||
| 463 | if (frmlen % SHM_FRM_PAD_LEN) | ||
| 464 | frmlen += SHM_FRM_PAD_LEN - | ||
| 465 | (frmlen % SHM_FRM_PAD_LEN); | ||
| 466 | |||
| 467 | /* | ||
| 468 | * Verify that packet, header and additional padding | ||
| 469 | * can fit within the buffer frame area. | ||
| 470 | */ | ||
| 471 | if (frmlen >= (pbuf->len - pbuf->frm_ofs)) | ||
| 472 | break; | ||
| 473 | |||
| 474 | if (!append) { | ||
| 475 | list_del_init(&pbuf->list); | ||
| 476 | append = 1; | ||
| 477 | } | ||
| 478 | |||
| 479 | skb = skb_dequeue(&pshm_drv->sk_qhead); | ||
| 480 | if (skb == NULL) | ||
| 481 | break; | ||
| 482 | /* Copy in CAIF frame. */ | ||
| 483 | skb_copy_bits(skb, 0, pbuf->desc_vptr + | ||
| 484 | pbuf->frm_ofs + SHM_HDR_LEN + | ||
| 485 | frm->hdr_ofs, skb->len); | ||
| 486 | |||
| 487 | pshm_drv->pshm_dev->pshm_netdev->stats.tx_packets++; | ||
| 488 | pshm_drv->pshm_dev->pshm_netdev->stats.tx_bytes += | ||
| 489 | frmlen; | ||
| 490 | dev_kfree_skb_irq(skb); | ||
| 491 | |||
| 492 | /* Fill in the shared memory packet descriptor area. */ | ||
| 493 | pck_desc = (struct shm_pck_desc *) (pbuf->desc_vptr); | ||
| 494 | /* Forward to current frame. */ | ||
| 495 | pck_desc += pbuf->frames; | ||
| 496 | pck_desc->frm_ofs = (pbuf->phy_addr - | ||
| 497 | pshm_drv->shm_base_addr) + | ||
| 498 | pbuf->frm_ofs; | ||
| 499 | pck_desc->frm_len = frmlen; | ||
| 500 | /* Terminate packet descriptor area. */ | ||
| 501 | pck_desc++; | ||
| 502 | pck_desc->frm_ofs = 0; | ||
| 503 | /* Update buffer parameters. */ | ||
| 504 | pbuf->frames++; | ||
| 505 | pbuf->frm_ofs += frmlen + (frmlen % 32); | ||
| 506 | |||
| 507 | } while (pbuf->frames < SHM_MAX_FRMS_PER_BUF); | ||
| 508 | |||
| 509 | /* Assign buffer as full. */ | ||
| 510 | list_add_tail(&pbuf->list, &pshm_drv->tx_full_list); | ||
| 511 | append = 0; | ||
| 512 | mbox_msg |= SHM_SET_FULL(pbuf->index); | ||
| 513 | send_msg: | ||
| 514 | spin_unlock_irqrestore(&pshm_drv->lock, flags); | ||
| 515 | |||
| 516 | if (mbox_msg) | ||
| 517 | pshm_drv->pshm_dev->pshmdev_mbxsend | ||
| 518 | (pshm_drv->pshm_dev->shm_id, mbox_msg); | ||
| 519 | } while (mbox_msg); | ||
| 520 | } | ||
| 521 | |||
| 522 | static int shm_netdev_tx(struct sk_buff *skb, struct net_device *shm_netdev) | ||
| 523 | { | ||
| 524 | struct shmdrv_layer *pshm_drv; | ||
| 525 | |||
| 526 | pshm_drv = netdev_priv(shm_netdev); | ||
| 527 | |||
| 528 | skb_queue_tail(&pshm_drv->sk_qhead, skb); | ||
| 529 | |||
| 530 | /* Schedule Tx work queue. for deferred processing of skbs*/ | ||
| 531 | if (!work_pending(&pshm_drv->shm_tx_work)) | ||
| 532 | queue_work(pshm_drv->pshm_tx_workqueue, &pshm_drv->shm_tx_work); | ||
| 533 | |||
| 534 | return 0; | ||
| 535 | } | ||
| 536 | |||
| 537 | static const struct net_device_ops netdev_ops = { | ||
| 538 | .ndo_open = shm_netdev_open, | ||
| 539 | .ndo_stop = shm_netdev_close, | ||
| 540 | .ndo_start_xmit = shm_netdev_tx, | ||
| 541 | }; | ||
| 542 | |||
| 543 | static void shm_netdev_setup(struct net_device *pshm_netdev) | ||
| 544 | { | ||
| 545 | struct shmdrv_layer *pshm_drv; | ||
| 546 | pshm_netdev->netdev_ops = &netdev_ops; | ||
| 547 | |||
| 548 | pshm_netdev->mtu = CAIF_MAX_MTU; | ||
| 549 | pshm_netdev->type = ARPHRD_CAIF; | ||
| 550 | pshm_netdev->hard_header_len = CAIF_NEEDED_HEADROOM; | ||
| 551 | pshm_netdev->tx_queue_len = 0; | ||
| 552 | pshm_netdev->destructor = free_netdev; | ||
| 553 | |||
| 554 | pshm_drv = netdev_priv(pshm_netdev); | ||
| 555 | |||
| 556 | /* Initialize structures in a clean state. */ | ||
| 557 | memset(pshm_drv, 0, sizeof(struct shmdrv_layer)); | ||
| 558 | |||
| 559 | pshm_drv->cfdev.link_select = CAIF_LINK_LOW_LATENCY; | ||
| 560 | } | ||
| 561 | |||
| 562 | int caif_shmcore_probe(struct shmdev_layer *pshm_dev) | ||
| 563 | { | ||
| 564 | int result, j; | ||
| 565 | struct shmdrv_layer *pshm_drv = NULL; | ||
| 566 | |||
| 567 | pshm_dev->pshm_netdev = alloc_netdev(sizeof(struct shmdrv_layer), | ||
| 568 | "cfshm%d", shm_netdev_setup); | ||
| 569 | if (!pshm_dev->pshm_netdev) | ||
| 570 | return -ENOMEM; | ||
| 571 | |||
| 572 | pshm_drv = netdev_priv(pshm_dev->pshm_netdev); | ||
| 573 | pshm_drv->pshm_dev = pshm_dev; | ||
| 574 | |||
| 575 | /* | ||
| 576 | * Initialization starts with the verification of the | ||
| 577 | * availability of MBX driver by calling its setup function. | ||
| 578 | * MBX driver must be available by this time for proper | ||
| 579 | * functioning of SHM driver. | ||
| 580 | */ | ||
| 581 | if ((pshm_dev->pshmdev_mbxsetup | ||
| 582 | (caif_shmdrv_rx_cb, pshm_dev, pshm_drv)) != 0) { | ||
| 583 | pr_warn("Could not config. SHM Mailbox," | ||
| 584 | " Bailing out.....\n"); | ||
| 585 | free_netdev(pshm_dev->pshm_netdev); | ||
| 586 | return -ENODEV; | ||
| 587 | } | ||
| 588 | |||
| 589 | skb_queue_head_init(&pshm_drv->sk_qhead); | ||
| 590 | |||
| 591 | pr_info("SHM DEVICE[%d] PROBED BY DRIVER, NEW SHM DRIVER" | ||
| 592 | " INSTANCE AT pshm_drv =0x%p\n", | ||
| 593 | pshm_drv->pshm_dev->shm_id, pshm_drv); | ||
| 594 | |||
| 595 | if (pshm_dev->shm_total_sz < | ||
| 596 | (NR_TX_BUF * TX_BUF_SZ + NR_RX_BUF * RX_BUF_SZ)) { | ||
| 597 | |||
| 598 | pr_warn("ERROR, Amount of available" | ||
| 599 | " Phys. SHM cannot accommodate current SHM " | ||
| 600 | "driver configuration, Bailing out ...\n"); | ||
| 601 | free_netdev(pshm_dev->pshm_netdev); | ||
| 602 | return -ENOMEM; | ||
| 603 | } | ||
| 604 | |||
| 605 | pshm_drv->shm_base_addr = pshm_dev->shm_base_addr; | ||
| 606 | pshm_drv->shm_tx_addr = pshm_drv->shm_base_addr; | ||
| 607 | |||
| 608 | if (pshm_dev->shm_loopback) | ||
| 609 | pshm_drv->shm_rx_addr = pshm_drv->shm_tx_addr; | ||
| 610 | else | ||
| 611 | pshm_drv->shm_rx_addr = pshm_dev->shm_base_addr + | ||
| 612 | (NR_TX_BUF * TX_BUF_SZ); | ||
| 613 | |||
| 614 | spin_lock_init(&pshm_drv->lock); | ||
| 615 | INIT_LIST_HEAD(&pshm_drv->tx_empty_list); | ||
| 616 | INIT_LIST_HEAD(&pshm_drv->tx_pend_list); | ||
| 617 | INIT_LIST_HEAD(&pshm_drv->tx_full_list); | ||
| 618 | |||
| 619 | INIT_LIST_HEAD(&pshm_drv->rx_empty_list); | ||
| 620 | INIT_LIST_HEAD(&pshm_drv->rx_pend_list); | ||
| 621 | INIT_LIST_HEAD(&pshm_drv->rx_full_list); | ||
| 622 | |||
| 623 | INIT_WORK(&pshm_drv->shm_tx_work, shm_tx_work_func); | ||
| 624 | INIT_WORK(&pshm_drv->shm_rx_work, shm_rx_work_func); | ||
| 625 | |||
| 626 | pshm_drv->pshm_tx_workqueue = | ||
| 627 | create_singlethread_workqueue("shm_tx_work"); | ||
| 628 | pshm_drv->pshm_rx_workqueue = | ||
| 629 | create_singlethread_workqueue("shm_rx_work"); | ||
| 630 | |||
| 631 | for (j = 0; j < NR_TX_BUF; j++) { | ||
| 632 | struct buf_list *tx_buf = | ||
| 633 | kmalloc(sizeof(struct buf_list), GFP_KERNEL); | ||
| 634 | |||
| 635 | if (tx_buf == NULL) { | ||
| 636 | free_netdev(pshm_dev->pshm_netdev); | ||
| 637 | return -ENOMEM; | ||
| 638 | } | ||
| 639 | tx_buf->index = j; | ||
| 640 | tx_buf->phy_addr = pshm_drv->shm_tx_addr + (TX_BUF_SZ * j); | ||
| 641 | tx_buf->len = TX_BUF_SZ; | ||
| 642 | tx_buf->frames = 0; | ||
| 643 | tx_buf->frm_ofs = SHM_CAIF_FRM_OFS; | ||
| 644 | |||
| 645 | if (pshm_dev->shm_loopback) | ||
| 646 | tx_buf->desc_vptr = (unsigned char *)tx_buf->phy_addr; | ||
| 647 | else | ||
| 648 | /* | ||
| 649 | * FIXME: the result of ioremap is not a pointer - arnd | ||
| 650 | */ | ||
| 651 | tx_buf->desc_vptr = | ||
| 652 | ioremap(tx_buf->phy_addr, TX_BUF_SZ); | ||
| 653 | |||
| 654 | list_add_tail(&tx_buf->list, &pshm_drv->tx_empty_list); | ||
| 655 | } | ||
| 656 | |||
| 657 | for (j = 0; j < NR_RX_BUF; j++) { | ||
| 658 | struct buf_list *rx_buf = | ||
| 659 | kmalloc(sizeof(struct buf_list), GFP_KERNEL); | ||
| 660 | |||
| 661 | if (rx_buf == NULL) { | ||
| 662 | free_netdev(pshm_dev->pshm_netdev); | ||
| 663 | return -ENOMEM; | ||
| 664 | } | ||
| 665 | rx_buf->index = j; | ||
| 666 | rx_buf->phy_addr = pshm_drv->shm_rx_addr + (RX_BUF_SZ * j); | ||
| 667 | rx_buf->len = RX_BUF_SZ; | ||
| 668 | |||
| 669 | if (pshm_dev->shm_loopback) | ||
| 670 | rx_buf->desc_vptr = (unsigned char *)rx_buf->phy_addr; | ||
| 671 | else | ||
| 672 | rx_buf->desc_vptr = | ||
| 673 | ioremap(rx_buf->phy_addr, RX_BUF_SZ); | ||
| 674 | list_add_tail(&rx_buf->list, &pshm_drv->rx_empty_list); | ||
| 675 | } | ||
| 676 | |||
| 677 | pshm_drv->tx_empty_available = 1; | ||
| 678 | result = register_netdev(pshm_dev->pshm_netdev); | ||
| 679 | if (result) | ||
| 680 | pr_warn("ERROR[%d], SHM could not, " | ||
| 681 | "register with NW FRMWK Bailing out ...\n", result); | ||
| 682 | |||
| 683 | return result; | ||
| 684 | } | ||
| 685 | |||
| 686 | void caif_shmcore_remove(struct net_device *pshm_netdev) | ||
| 687 | { | ||
| 688 | struct buf_list *pbuf; | ||
| 689 | struct shmdrv_layer *pshm_drv = NULL; | ||
| 690 | |||
| 691 | pshm_drv = netdev_priv(pshm_netdev); | ||
| 692 | |||
| 693 | while (!(list_empty(&pshm_drv->tx_pend_list))) { | ||
| 694 | pbuf = | ||
| 695 | list_entry(pshm_drv->tx_pend_list.next, | ||
| 696 | struct buf_list, list); | ||
| 697 | |||
| 698 | list_del(&pbuf->list); | ||
| 699 | kfree(pbuf); | ||
| 700 | } | ||
| 701 | |||
| 702 | while (!(list_empty(&pshm_drv->tx_full_list))) { | ||
| 703 | pbuf = | ||
| 704 | list_entry(pshm_drv->tx_full_list.next, | ||
| 705 | struct buf_list, list); | ||
| 706 | list_del(&pbuf->list); | ||
| 707 | kfree(pbuf); | ||
| 708 | } | ||
| 709 | |||
| 710 | while (!(list_empty(&pshm_drv->tx_empty_list))) { | ||
| 711 | pbuf = | ||
| 712 | list_entry(pshm_drv->tx_empty_list.next, | ||
| 713 | struct buf_list, list); | ||
| 714 | list_del(&pbuf->list); | ||
| 715 | kfree(pbuf); | ||
| 716 | } | ||
| 717 | |||
| 718 | while (!(list_empty(&pshm_drv->rx_full_list))) { | ||
| 719 | pbuf = | ||
| 720 | list_entry(pshm_drv->tx_full_list.next, | ||
| 721 | struct buf_list, list); | ||
| 722 | list_del(&pbuf->list); | ||
| 723 | kfree(pbuf); | ||
| 724 | } | ||
| 725 | |||
| 726 | while (!(list_empty(&pshm_drv->rx_pend_list))) { | ||
| 727 | pbuf = | ||
| 728 | list_entry(pshm_drv->tx_pend_list.next, | ||
| 729 | struct buf_list, list); | ||
| 730 | list_del(&pbuf->list); | ||
| 731 | kfree(pbuf); | ||
| 732 | } | ||
| 733 | |||
| 734 | while (!(list_empty(&pshm_drv->rx_empty_list))) { | ||
| 735 | pbuf = | ||
| 736 | list_entry(pshm_drv->rx_empty_list.next, | ||
| 737 | struct buf_list, list); | ||
| 738 | list_del(&pbuf->list); | ||
| 739 | kfree(pbuf); | ||
| 740 | } | ||
| 741 | |||
| 742 | /* Destroy work queues. */ | ||
| 743 | destroy_workqueue(pshm_drv->pshm_tx_workqueue); | ||
| 744 | destroy_workqueue(pshm_drv->pshm_rx_workqueue); | ||
| 745 | |||
| 746 | unregister_netdev(pshm_netdev); | ||
| 747 | } | ||
| @@ -1,7 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson AB 2010 | 2 | * Copyright (C) ST-Ericsson AB 2010 |
| 3 | * Contact: Sjur Brendeland / sjur.brandeland@stericsson.com | 3 | * Author: Daniel Martensson |
| 4 | * Author: Daniel Martensson / Daniel.Martensson@stericsson.com | ||
| 5 | * License terms: GNU General Public License (GPL) version 2. | 4 | * License terms: GNU General Public License (GPL) version 2. |
| 6 | */ | 5 | */ |
| 7 | 6 | ||
| @@ -29,7 +28,7 @@ · 21 unmodified lines | |||
| 29 | #endif /* CONFIG_CAIF_SPI_SYNC */ | 28 | #endif /* CONFIG_CAIF_SPI_SYNC */ |
| 30 | 29 | ||
| 31 | MODULE_LICENSE("GPL"); | 30 | MODULE_LICENSE("GPL"); |
| 32 | MODULE_AUTHOR("Daniel Martensson<daniel.martensson@stericsson.com>"); | 31 | MODULE_AUTHOR("Daniel Martensson"); |
| 33 | MODULE_DESCRIPTION("CAIF SPI driver"); | 32 | MODULE_DESCRIPTION("CAIF SPI driver"); |
| 34 | 33 | ||
| 35 | /* Returns the number of padding bytes for alignment. */ | 34 | /* Returns the number of padding bytes for alignment. */ |
| @@ -864,6 +863,7 @@ static int __init cfspi_init_module(void) · 828 unmodified lines | |||
| 864 | driver_remove_file(&cfspi_spi_driver.driver, | 863 | driver_remove_file(&cfspi_spi_driver.driver, |
| 865 | &driver_attr_up_head_align); | 864 | &driver_attr_up_head_align); |
| 866 | err_create_up_head_align: | 865 | err_create_up_head_align: |
| 866 | platform_driver_unregister(&cfspi_spi_driver); | ||
| 867 | err_dev_register: | 867 | err_dev_register: |
| 868 | return result; | 868 | return result; |
| 869 | } | 869 | } |
| @@ -1,7 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson AB 2010 | 2 | * Copyright (C) ST-Ericsson AB 2010 |
| 3 | * Contact: Sjur Brendeland / sjur.brandeland@stericsson.com | 3 | * Author: Daniel Martensson |
| 4 | * Author: Daniel Martensson / Daniel.Martensson@stericsson.com | ||
| 5 | * License terms: GNU General Public License (GPL) version 2. | 4 | * License terms: GNU General Public License (GPL) version 2. |
| 6 | */ | 5 | */ |
| 7 | #include <linux/init.h> | 6 | #include <linux/init.h> |
| @@ -65,7 +65,7 @@ config CAN_LEDS · 64 unmodified lines | |||
| 65 | 65 | ||
| 66 | config CAN_AT91 | 66 | config CAN_AT91 |
| 67 | tristate "Atmel AT91 onchip CAN controller" | 67 | tristate "Atmel AT91 onchip CAN controller" |
| 68 | depends on ARCH_AT91SAM9263 || ARCH_AT91SAM9X5 | 68 | depends on ARM |
| 69 | ---help--- | 69 | ---help--- |
| 70 | This is a driver for the SoC CAN controller in Atmel's AT91SAM9263 | 70 | This is a driver for the SoC CAN controller in Atmel's AT91SAM9263 |
| 71 | and AT91SAM9X5 processors. | 71 | and AT91SAM9X5 processors. |
| @@ -27,6 +27,7 @@ · 26 unmodified lines | |||
| 27 | #include <linux/kernel.h> | 27 | #include <linux/kernel.h> |
| 28 | #include <linux/module.h> | 28 | #include <linux/module.h> |
| 29 | #include <linux/netdevice.h> | 29 | #include <linux/netdevice.h> |
| 30 | #include <linux/of.h> | ||
| 30 | #include <linux/platform_device.h> | 31 | #include <linux/platform_device.h> |
| 31 | #include <linux/rtnetlink.h> | 32 | #include <linux/rtnetlink.h> |
| 32 | #include <linux/skbuff.h> | 33 | #include <linux/skbuff.h> |
| @@ -155,19 +156,20 @@ struct at91_priv { · 122 unmodified lines | |||
| 155 | canid_t mb0_id; | 156 | canid_t mb0_id; |
| 156 | }; | 157 | }; |
| 157 | 158 | ||
| 158 | static const struct at91_devtype_data at91_devtype_data[] = { | 159 | static const struct at91_devtype_data at91_at91sam9263_data = { |
| 159 | [AT91_DEVTYPE_SAM9263] = { | 160 | .rx_first = 1, |
| 160 | .rx_first = 1, | 161 | .rx_split = 8, |
| 161 | .rx_split = 8, | 162 | .rx_last = 11, |
| 162 | .rx_last = 11, | 163 | .tx_shift = 2, |
| 163 | .tx_shift = 2, | 164 | .type = AT91_DEVTYPE_SAM9263, |
| 164 | }, | 165 | }; |
| 165 | [AT91_DEVTYPE_SAM9X5] = { | 166 | |
| 166 | .rx_first = 0, | 167 | static const struct at91_devtype_data at91_at91sam9x5_data = { |
| 167 | .rx_split = 4, | 168 | .rx_first = 0, |
| 168 | .rx_last = 5, | 169 | .rx_split = 4, |
| 169 | .tx_shift = 1, | 170 | .rx_last = 5, |
| 170 | }, | 171 | .tx_shift = 1, |
| 172 | .type = AT91_DEVTYPE_SAM9X5, | ||
| 171 | }; | 173 | }; |
| 172 | 174 | ||
| 173 | static const struct can_bittiming_const at91_bittiming_const = { | 175 | static const struct can_bittiming_const at91_bittiming_const = { |
| @@ -1249,10 +1251,42 @@ static struct attribute_group at91_sysfs_attr_group = { · 1075 unmodified lines | |||
| 1249 | .attrs = at91_sysfs_attrs, | 1251 | .attrs = at91_sysfs_attrs, |
| 1250 | }; | 1252 | }; |
| 1251 | 1253 | ||
| 1254 | #if defined(CONFIG_OF) | ||
| 1255 | static const struct of_device_id at91_can_dt_ids[] = { | ||
| 1256 | { | ||
| 1257 | .compatible = "atmel,at91sam9x5-can", | ||
| 1258 | .data = &at91_at91sam9x5_data, | ||
| 1259 | }, { | ||
| 1260 | .compatible = "atmel,at91sam9263-can", | ||
| 1261 | .data = &at91_at91sam9263_data, | ||
| 1262 | }, { | ||
| 1263 | /* sentinel */ | ||
| 1264 | } | ||
| 1265 | }; | ||
| 1266 | MODULE_DEVICE_TABLE(of, at91_can_dt_ids); | ||
| 1267 | #else | ||
| 1268 | #define at91_can_dt_ids NULL | ||
| 1269 | #endif | ||
| 1270 | |||
| 1271 | static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev) | ||
| 1272 | { | ||
| 1273 | if (pdev->dev.of_node) { | ||
| 1274 | const struct of_device_id *match; | ||
| 1275 | |||
| 1276 | match = of_match_node(at91_can_dt_ids, pdev->dev.of_node); | ||
| 1277 | if (!match) { | ||
| 1278 | dev_err(&pdev->dev, "no matching node found in dtb\n"); | ||
| 1279 | return NULL; | ||
| 1280 | } | ||
| 1281 | return (const struct at91_devtype_data *)match->data; | ||
| 1282 | } | ||
| 1283 | return (const struct at91_devtype_data *) | ||
| 1284 | platform_get_device_id(pdev)->driver_data; | ||
| 1285 | } | ||
| 1286 | |||
| 1252 | static int at91_can_probe(struct platform_device *pdev) | 1287 | static int at91_can_probe(struct platform_device *pdev) |
| 1253 | { | 1288 | { |
| 1254 | const struct at91_devtype_data *devtype_data; | 1289 | const struct at91_devtype_data *devtype_data; |
| 1255 | enum at91_devtype devtype; | ||
| 1256 | struct net_device *dev; | 1290 | struct net_device *dev; |
| 1257 | struct at91_priv *priv; | 1291 | struct at91_priv *priv; |
| 1258 | struct resource *res; | 1292 | struct resource *res; |
| @@ -1260,8 +1294,12 @@ static int at91_can_probe(struct platform_device *pdev) · 1 unmodified line | |||
| 1260 | void __iomem *addr; | 1294 | void __iomem *addr; |
| 1261 | int err, irq; | 1295 | int err, irq; |
| 1262 | 1296 | ||
| 1263 | devtype = pdev->id_entry->driver_data; | 1297 | devtype_data = at91_can_get_driver_data(pdev); |
| 1264 | devtype_data = &at91_devtype_data[devtype]; | 1298 | if (!devtype_data) { |
| 1299 | dev_err(&pdev->dev, "no driver data\n"); | ||
| 1300 | err = -ENODEV; | ||
| 1301 | goto exit; | ||
| 1302 | } | ||
| 1265 | 1303 | ||
| 1266 | clk = clk_get(&pdev->dev, "can_clk"); | 1304 | clk = clk_get(&pdev->dev, "can_clk"); |
| 1267 | if (IS_ERR(clk)) { | 1305 | if (IS_ERR(clk)) { |
| @@ -1310,7 +1348,6 @@ static int at91_can_probe(struct platform_device *pdev) · 42 unmodified lines | |||
| 1310 | priv->dev = dev; | 1348 | priv->dev = dev; |
| 1311 | priv->reg_base = addr; | 1349 | priv->reg_base = addr; |
| 1312 | priv->devtype_data = *devtype_data; | 1350 | priv->devtype_data = *devtype_data; |
| 1313 | priv->devtype_data.type = devtype; | ||
| 1314 | priv->clk = clk; | 1351 | priv->clk = clk; |
| 1315 | priv->pdata = pdev->dev.platform_data; | 1352 | priv->pdata = pdev->dev.platform_data; |
| 1316 | priv->mb0_id = 0x7ff; | 1353 | priv->mb0_id = 0x7ff; |
| @@ -1373,10 +1410,10 @@ static int at91_can_remove(struct platform_device *pdev) · 56 unmodified lines | |||
| 1373 | static const struct platform_device_id at91_can_id_table[] = { | 1410 | static const struct platform_device_id at91_can_id_table[] = { |
| 1374 | { | 1411 | { |
| 1375 | .name = "at91_can", | 1412 | .name = "at91_can", |
| 1376 | .driver_data = AT91_DEVTYPE_SAM9263, | 1413 | .driver_data = (kernel_ulong_t)&at91_at91sam9x5_data, |
| 1377 | }, { | 1414 | }, { |
| 1378 | .name = "at91sam9x5_can", | 1415 | .name = "at91sam9x5_can", |
| 1379 | .driver_data = AT91_DEVTYPE_SAM9X5, | 1416 | .driver_data = (kernel_ulong_t)&at91_at91sam9263_data, |
| 1380 | }, { | 1417 | }, { |
| 1381 | /* sentinel */ | 1418 | /* sentinel */ |
| 1382 | } | 1419 | } |
| @@ -1389,6 +1426,7 @@ static struct platform_driver at91_can_driver = { · 6 unmodified lines | |||
| 1389 | .driver = { | 1426 | .driver = { |
| 1390 | .name = KBUILD_MODNAME, | 1427 | .name = KBUILD_MODNAME, |
| 1391 | .owner = THIS_MODULE, | 1428 | .owner = THIS_MODULE, |
| 1429 | .of_match_table = at91_can_dt_ids, | ||
| 1392 | }, | 1430 | }, |
| 1393 | .id_table = at91_can_id_table, | 1431 | .id_table = at91_can_id_table, |
| 1394 | }; | 1432 | }; |
| @@ -412,7 +412,7 @@ static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status) · 411 unmodified lines | |||
| 412 | return 0; | 412 | return 0; |
| 413 | } | 413 | } |
| 414 | 414 | ||
| 415 | irqreturn_t bfin_can_interrupt(int irq, void *dev_id) | 415 | static irqreturn_t bfin_can_interrupt(int irq, void *dev_id) |
| 416 | { | 416 | { |
| 417 | struct net_device *dev = dev_id; | 417 | struct net_device *dev = dev_id; |
| 418 | struct bfin_can_priv *priv = netdev_priv(dev); | 418 | struct bfin_can_priv *priv = netdev_priv(dev); |
| @@ -504,7 +504,7 @@ static int bfin_can_close(struct net_device *dev) · 85 unmodified lines | |||
| 504 | return 0; | 504 | return 0; |
| 505 | } | 505 | } |
| 506 | 506 | ||
| 507 | struct net_device *alloc_bfin_candev(void) | 507 | static struct net_device *alloc_bfin_candev(void) |
| 508 | { | 508 | { |
| 509 | struct net_device *dev; | 509 | struct net_device *dev; |
| 510 | struct bfin_can_priv *priv; | 510 | struct bfin_can_priv *priv; |
| @@ -269,7 +269,7 @@ struct mcp251x_priv { · 268 unmodified lines | |||
| 269 | #define MCP251X_IS(_model) \ | 269 | #define MCP251X_IS(_model) \ |
| 270 | static inline int mcp251x_is_##_model(struct spi_device *spi) \ | 270 | static inline int mcp251x_is_##_model(struct spi_device *spi) \ |
| 271 | { \ | 271 | { \ |
| 272 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); \ | 272 | struct mcp251x_priv *priv = spi_get_drvdata(spi); \ |
| 273 | return priv->model == CAN_MCP251X_MCP##_model; \ | 273 | return priv->model == CAN_MCP251X_MCP##_model; \ |
| 274 | } | 274 | } |
| 275 | 275 | ||
| @@ -305,7 +305,7 @@ static void mcp251x_clean(struct net_device *net) · 29 unmodified lines | |||
| 305 | */ | 305 | */ |
| 306 | static int mcp251x_spi_trans(struct spi_device *spi, int len) | 306 | static int mcp251x_spi_trans(struct spi_device *spi, int len) |
| 307 | { | 307 | { |
| 308 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 308 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 309 | struct spi_transfer t = { | 309 | struct spi_transfer t = { |
| 310 | .tx_buf = priv->spi_tx_buf, | 310 | .tx_buf = priv->spi_tx_buf, |
| 311 | .rx_buf = priv->spi_rx_buf, | 311 | .rx_buf = priv->spi_rx_buf, |
| @@ -333,7 +333,7 @@ static int mcp251x_spi_trans(struct spi_device *spi, int len) · 21 unmodified lines | |||
| 333 | 333 | ||
| 334 | static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) | 334 | static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) |
| 335 | { | 335 | { |
| 336 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 336 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 337 | u8 val = 0; | 337 | u8 val = 0; |
| 338 | 338 | ||
| 339 | priv->spi_tx_buf[0] = INSTRUCTION_READ; | 339 | priv->spi_tx_buf[0] = INSTRUCTION_READ; |
| @@ -348,7 +348,7 @@ static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) · 8 unmodified lines | |||
| 348 | static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg, | 348 | static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg, |
| 349 | uint8_t *v1, uint8_t *v2) | 349 | uint8_t *v1, uint8_t *v2) |
| 350 | { | 350 | { |
| 351 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 351 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 352 | 352 | ||
| 353 | priv->spi_tx_buf[0] = INSTRUCTION_READ; | 353 | priv->spi_tx_buf[0] = INSTRUCTION_READ; |
| 354 | priv->spi_tx_buf[1] = reg; | 354 | priv->spi_tx_buf[1] = reg; |
| @@ -361,7 +361,7 @@ static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg, · 6 unmodified lines | |||
| 361 | 361 | ||
| 362 | static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val) | 362 | static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val) |
| 363 | { | 363 | { |
| 364 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 364 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 365 | 365 | ||
| 366 | priv->spi_tx_buf[0] = INSTRUCTION_WRITE; | 366 | priv->spi_tx_buf[0] = INSTRUCTION_WRITE; |
| 367 | priv->spi_tx_buf[1] = reg; | 367 | priv->spi_tx_buf[1] = reg; |
| @@ -373,7 +373,7 @@ static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val) · 5 unmodified lines | |||
| 373 | static void mcp251x_write_bits(struct spi_device *spi, u8 reg, | 373 | static void mcp251x_write_bits(struct spi_device *spi, u8 reg, |
| 374 | u8 mask, uint8_t val) | 374 | u8 mask, uint8_t val) |
| 375 | { | 375 | { |
| 376 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 376 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 377 | 377 | ||
| 378 | priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY; | 378 | priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY; |
| 379 | priv->spi_tx_buf[1] = reg; | 379 | priv->spi_tx_buf[1] = reg; |
| @@ -386,7 +386,7 @@ static void mcp251x_write_bits(struct spi_device *spi, u8 reg, · 6 unmodified lines | |||
| 386 | static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, | 386 | static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, |
| 387 | int len, int tx_buf_idx) | 387 | int len, int tx_buf_idx) |
| 388 | { | 388 | { |
| 389 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 389 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 390 | 390 | ||
| 391 | if (mcp251x_is_2510(spi)) { | 391 | if (mcp251x_is_2510(spi)) { |
| 392 | int i; | 392 | int i; |
| @@ -403,7 +403,7 @@ static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, · 10 unmodified lines | |||
| 403 | static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, | 403 | static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, |
| 404 | int tx_buf_idx) | 404 | int tx_buf_idx) |
| 405 | { | 405 | { |
| 406 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 406 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 407 | u32 sid, eid, exide, rtr; | 407 | u32 sid, eid, exide, rtr; |
| 408 | u8 buf[SPI_TRANSFER_BUF_LEN]; | 408 | u8 buf[SPI_TRANSFER_BUF_LEN]; |
| 409 | 409 | ||
| @@ -434,7 +434,7 @@ static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, · 24 unmodified lines | |||
| 434 | static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, | 434 | static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, |
| 435 | int buf_idx) | 435 | int buf_idx) |
| 436 | { | 436 | { |
| 437 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 437 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 438 | 438 | ||
| 439 | if (mcp251x_is_2510(spi)) { | 439 | if (mcp251x_is_2510(spi)) { |
| 440 | int i, len; | 440 | int i, len; |
| @@ -454,7 +454,7 @@ static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, · 13 unmodified lines | |||
| 454 | 454 | ||
| 455 | static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx) | 455 | static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx) |
| 456 | { | 456 | { |
| 457 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 457 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 458 | struct sk_buff *skb; | 458 | struct sk_buff *skb; |
| 459 | struct can_frame *frame; | 459 | struct can_frame *frame; |
| 460 | u8 buf[SPI_TRANSFER_BUF_LEN]; | 460 | u8 buf[SPI_TRANSFER_BUF_LEN]; |
| @@ -550,7 +550,7 @@ static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode) · 89 unmodified lines | |||
| 550 | 550 | ||
| 551 | static int mcp251x_set_normal_mode(struct spi_device *spi) | 551 | static int mcp251x_set_normal_mode(struct spi_device *spi) |
| 552 | { | 552 | { |
| 553 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 553 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 554 | unsigned long timeout; | 554 | unsigned long timeout; |
| 555 | 555 | ||
| 556 | /* Enable interrupts */ | 556 | /* Enable interrupts */ |
| @@ -620,7 +620,7 @@ static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv, · 63 unmodified lines | |||
| 620 | 620 | ||
| 621 | static int mcp251x_hw_reset(struct spi_device *spi) | 621 | static int mcp251x_hw_reset(struct spi_device *spi) |
| 622 | { | 622 | { |
| 623 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 623 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 624 | int ret; | 624 | int ret; |
| 625 | unsigned long timeout; | 625 | unsigned long timeout; |
| 626 | 626 | ||
| @@ -1026,7 +1026,7 @@ static int mcp251x_can_probe(struct spi_device *spi) · 399 unmodified lines | |||
| 1026 | CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; | 1026 | CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; |
| 1027 | priv->model = spi_get_device_id(spi)->driver_data; | 1027 | priv->model = spi_get_device_id(spi)->driver_data; |
| 1028 | priv->net = net; | 1028 | priv->net = net; |
| 1029 | dev_set_drvdata(&spi->dev, priv); | 1029 | spi_set_drvdata(spi, priv); |
| 1030 | 1030 | ||
| 1031 | priv->spi = spi; | 1031 | priv->spi = spi; |
| 1032 | mutex_init(&priv->mcp_lock); | 1032 | mutex_init(&priv->mcp_lock); |
| @@ -1124,7 +1124,7 @@ error_out: · 91 unmodified lines | |||
| 1124 | static int mcp251x_can_remove(struct spi_device *spi) | 1124 | static int mcp251x_can_remove(struct spi_device *spi) |
| 1125 | { | 1125 | { |
| 1126 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | 1126 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; |
| 1127 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 1127 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 1128 | struct net_device *net = priv->net; | 1128 | struct net_device *net = priv->net; |
| 1129 | 1129 | ||
| 1130 | unregister_candev(net); | 1130 | unregister_candev(net); |
| @@ -1144,11 +1144,13 @@ static int mcp251x_can_remove(struct spi_device *spi) · 13 unmodified lines | |||
| 1144 | return 0; | 1144 | return 0; |
| 1145 | } | 1145 | } |
| 1146 | 1146 | ||
| 1147 | #ifdef CONFIG_PM | 1147 | #ifdef CONFIG_PM_SLEEP |
| 1148 | static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state) | 1148 | |
| 1149 | static int mcp251x_can_suspend(struct device *dev) | ||
| 1149 | { | 1150 | { |
| 1151 | struct spi_device *spi = to_spi_device(dev); | ||
| 1150 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | 1152 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; |
| 1151 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 1153 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 1152 | struct net_device *net = priv->net; | 1154 | struct net_device *net = priv->net; |
| 1153 | 1155 | ||
| 1154 | priv->force_quit = 1; | 1156 | priv->force_quit = 1; |
| @@ -1176,10 +1178,11 @@ static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state) · 21 unmodified lines | |||
| 1176 | return 0; | 1178 | return 0; |
| 1177 | } | 1179 | } |
| 1178 | 1180 | ||
| 1179 | static int mcp251x_can_resume(struct spi_device *spi) | 1181 | static int mcp251x_can_resume(struct device *dev) |
| 1180 | { | 1182 | { |
| 1183 | struct spi_device *spi = to_spi_device(dev); | ||
| 1181 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | 1184 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; |
| 1182 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | 1185 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
| 1183 | 1186 | ||
| 1184 | if (priv->after_suspend & AFTER_SUSPEND_POWER) { | 1187 | if (priv->after_suspend & AFTER_SUSPEND_POWER) { |
| 1185 | pdata->power_enable(1); | 1188 | pdata->power_enable(1); |
| @@ -1197,11 +1200,11 @@ static int mcp251x_can_resume(struct spi_device *spi) · 11 unmodified lines | |||
| 1197 | enable_irq(spi->irq); | 1200 | enable_irq(spi->irq); |
| 1198 | return 0; | 1201 | return 0; |
| 1199 | } | 1202 | } |
| 1200 | #else | ||
| 1201 | #define mcp251x_can_suspend NULL | ||
| 1202 | #define mcp251x_can_resume NULL | ||
| 1203 | #endif | 1203 | #endif |
| 1204 | 1204 | ||
| 1205 | static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend, | ||
| 1206 | mcp251x_can_resume); | ||
| 1207 | |||
| 1205 | static const struct spi_device_id mcp251x_id_table[] = { | 1208 | static const struct spi_device_id mcp251x_id_table[] = { |
| 1206 | { "mcp2510", CAN_MCP251X_MCP2510 }, | 1209 | { "mcp2510", CAN_MCP251X_MCP2510 }, |
| 1207 | { "mcp2515", CAN_MCP251X_MCP2515 }, | 1210 | { "mcp2515", CAN_MCP251X_MCP2515 }, |
| @@ -1213,29 +1216,15 @@ MODULE_DEVICE_TABLE(spi, mcp251x_id_table); · 5 unmodified lines | |||
| 1213 | static struct spi_driver mcp251x_can_driver = { | 1216 | static struct spi_driver mcp251x_can_driver = { |
| 1214 | .driver = { | 1217 | .driver = { |
| 1215 | .name = DEVICE_NAME, | 1218 | .name = DEVICE_NAME, |
| 1216 | .bus = &spi_bus_type, | ||
| 1217 | .owner = THIS_MODULE, | 1219 | .owner = THIS_MODULE, |
| 1220 | .pm = &mcp251x_can_pm_ops, | ||
| 1218 | }, | 1221 | }, |
| 1219 | 1222 | ||
| 1220 | .id_table = mcp251x_id_table, | 1223 | .id_table = mcp251x_id_table, |
| 1221 | .probe = mcp251x_can_probe, | 1224 | .probe = mcp251x_can_probe, |
| 1222 | .remove = mcp251x_can_remove, | 1225 | .remove = mcp251x_can_remove, |
| 1223 | .suspend = mcp251x_can_suspend, | ||
| 1224 | .resume = mcp251x_can_resume, | ||
| 1225 | }; | 1226 | }; |
| 1226 | 1227 | module_spi_driver(mcp251x_can_driver); | |
| 1227 | static int __init mcp251x_can_init(void) | ||
| 1228 | { | ||
| 1229 | return spi_register_driver(&mcp251x_can_driver); | ||
| 1230 | } | ||
| 1231 | |||
| 1232 | static void __exit mcp251x_can_exit(void) | ||
| 1233 | { | ||
| 1234 | spi_unregister_driver(&mcp251x_can_driver); | ||
| 1235 | } | ||
| 1236 | |||
| 1237 | module_init(mcp251x_can_init); | ||
| 1238 | module_exit(mcp251x_can_exit); | ||
| 1239 | 1228 | ||
| 1240 | MODULE_AUTHOR("Chris Elston <celston@katalix.com>, " | 1229 | MODULE_AUTHOR("Chris Elston <celston@katalix.com>, " |
| 1241 | "Christian Pellegrin <chripell@evolware.org>"); | 1230 | "Christian Pellegrin <chripell@evolware.org>"); |
| @@ -168,12 +168,12 @@ static inline int ems_pci_check_chan(const struct sja1000_priv *priv) · 167 unmodified lines | |||
| 168 | unsigned char res; | 168 | unsigned char res; |
| 169 | 169 | ||
| 170 | /* Make sure SJA1000 is in reset mode */ | 170 | /* Make sure SJA1000 is in reset mode */ |
| 171 | priv->write_reg(priv, REG_MOD, 1); | 171 | priv->write_reg(priv, SJA1000_MOD, 1); |
| 172 | 172 | ||
| 173 | priv->write_reg(priv, REG_CDR, CDR_PELICAN); | 173 | priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); |
| 174 | 174 | ||
| 175 | /* read reset-values */ | 175 | /* read reset-values */ |
| 176 | res = priv->read_reg(priv, REG_CDR); | 176 | res = priv->read_reg(priv, SJA1000_CDR); |
| 177 | 177 | ||
| 178 | if (res == CDR_PELICAN) | 178 | if (res == CDR_PELICAN) |
| 179 | return 1; | 179 | return 1; |
| @@ -126,11 +126,11 @@ static irqreturn_t ems_pcmcia_interrupt(int irq, void *dev_id) · 125 unmodified lines | |||
| 126 | static inline int ems_pcmcia_check_chan(struct sja1000_priv *priv) | 126 | static inline int ems_pcmcia_check_chan(struct sja1000_priv *priv) |
| 127 | { | 127 | { |
| 128 | /* Make sure SJA1000 is in reset mode */ | 128 | /* Make sure SJA1000 is in reset mode */ |
| 129 | ems_pcmcia_write_reg(priv, REG_MOD, 1); | 129 | ems_pcmcia_write_reg(priv, SJA1000_MOD, 1); |
| 130 | ems_pcmcia_write_reg(priv, REG_CDR, CDR_PELICAN); | 130 | ems_pcmcia_write_reg(priv, SJA1000_CDR, CDR_PELICAN); |
| 131 | 131 | ||
| 132 | /* read reset-values */ | 132 | /* read reset-values */ |
| 133 | if (ems_pcmcia_read_reg(priv, REG_CDR) == CDR_PELICAN) | 133 | if (ems_pcmcia_read_reg(priv, SJA1000_CDR) == CDR_PELICAN) |
| 134 | return 1; | 134 | return 1; |
| 135 | 135 | ||
| 136 | return 0; | 136 | return 0; |
| @@ -159,9 +159,9 @@ static int number_of_sja1000_chip(void __iomem *base_addr) · 158 unmodified lines | |||
| 159 | for (i = 0; i < MAX_NO_OF_CHANNELS; i++) { | 159 | for (i = 0; i < MAX_NO_OF_CHANNELS; i++) { |
| 160 | /* reset chip */ | 160 | /* reset chip */ |
| 161 | iowrite8(MOD_RM, base_addr + | 161 | iowrite8(MOD_RM, base_addr + |
| 162 | (i * KVASER_PCI_PORT_BYTES) + REG_MOD); | 162 | (i * KVASER_PCI_PORT_BYTES) + SJA1000_MOD); |
| 163 | status = ioread8(base_addr + | 163 | status = ioread8(base_addr + |
| 164 | (i * KVASER_PCI_PORT_BYTES) + REG_MOD); | 164 | (i * KVASER_PCI_PORT_BYTES) + SJA1000_MOD); |
| 165 | /* check reset bit */ | 165 | /* check reset bit */ |
| 166 | if (!(status & MOD_RM)) | 166 | if (!(status & MOD_RM)) |
| 167 | break; | 167 | break; |
| @@ -402,7 +402,7 @@ static void peak_pciec_write_reg(const struct sja1000_priv *priv, · 401 unmodified lines | |||
| 402 | int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE; | 402 | int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE; |
| 403 | 403 | ||
| 404 | /* sja1000 register changes control the leds state */ | 404 | /* sja1000 register changes control the leds state */ |
| 405 | if (port == REG_MOD) | 405 | if (port == SJA1000_MOD) |
| 406 | switch (val) { | 406 | switch (val) { |
| 407 | case MOD_RM: | 407 | case MOD_RM: |
| 408 | /* Reset Mode: set led on */ | 408 | /* Reset Mode: set led on */ |
| @@ -196,7 +196,7 @@ static void pcan_write_canreg(const struct sja1000_priv *priv, int port, u8 v) · 195 unmodified lines | |||
| 196 | int c = (priv->reg_base - card->ioport_addr) / PCC_CHAN_SIZE; | 196 | int c = (priv->reg_base - card->ioport_addr) / PCC_CHAN_SIZE; |
| 197 | 197 | ||
| 198 | /* sja1000 register changes control the leds state */ | 198 | /* sja1000 register changes control the leds state */ |
| 199 | if (port == REG_MOD) | 199 | if (port == SJA1000_MOD) |
| 200 | switch (v) { | 200 | switch (v) { |
| 201 | case MOD_RM: | 201 | case MOD_RM: |
| 202 | /* Reset Mode: set led on */ | 202 | /* Reset Mode: set led on */ |
| @@ -509,11 +509,11 @@ static void pcan_free_channels(struct pcan_pccard *card) · 306 unmodified lines | |||
| 509 | static inline int pcan_channel_present(struct sja1000_priv *priv) | 509 | static inline int pcan_channel_present(struct sja1000_priv *priv) |
| 510 | { | 510 | { |
| 511 | /* make sure SJA1000 is in reset mode */ | 511 | /* make sure SJA1000 is in reset mode */ |
| 512 | pcan_write_canreg(priv, REG_MOD, 1); | 512 | pcan_write_canreg(priv, SJA1000_MOD, 1); |
| 513 | pcan_write_canreg(priv, REG_CDR, CDR_PELICAN); | 513 | pcan_write_canreg(priv, SJA1000_CDR, CDR_PELICAN); |
| 514 | 514 | ||
| 515 | /* read reset-values */ | 515 | /* read reset-values */ |
| 516 | if (pcan_read_canreg(priv, REG_CDR) == CDR_PELICAN) | 516 | if (pcan_read_canreg(priv, SJA1000_CDR) == CDR_PELICAN) |
| 517 | return 1; | 517 | return 1; |
| 518 | 518 | ||
| 519 | return 0; | 519 | return 0; |
| @@ -348,20 +348,20 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) · 347 unmodified lines | |||
| 348 | */ | 348 | */ |
| 349 | if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == | 349 | if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == |
| 350 | REG_CR_BASICCAN_INITIAL && | 350 | REG_CR_BASICCAN_INITIAL && |
| 351 | (priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_BASICCAN_INITIAL) && | 351 | (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) && |
| 352 | (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL)) | 352 | (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL)) |
| 353 | flag = 1; | 353 | flag = 1; |
| 354 | 354 | ||
| 355 | /* Bring the SJA1000 into the PeliCAN mode*/ | 355 | /* Bring the SJA1000 into the PeliCAN mode*/ |
| 356 | priv->write_reg(priv, REG_CDR, CDR_PELICAN); | 356 | priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); |
| 357 | 357 | ||
| 358 | /* | 358 | /* |
| 359 | * Check registers after reset in the PeliCAN mode. | 359 | * Check registers after reset in the PeliCAN mode. |
| 360 | * See states on p. 23 of the Datasheet. | 360 | * See states on p. 23 of the Datasheet. |
| 361 | */ | 361 | */ |
| 362 | if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL && | 362 | if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL && |
| 363 | priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_PELICAN_INITIAL && | 363 | priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL && |
| 364 | priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL) | 364 | priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL) |
| 365 | return flag; | 365 | return flag; |
| 366 | 366 | ||
| 367 | return 0; | 367 | return 0; |
| @@ -91,14 +91,14 @@ static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val) · 90 unmodified lines | |||
| 91 | * the write_reg() operation - especially on SMP systems. | 91 | * the write_reg() operation - especially on SMP systems. |
| 92 | */ | 92 | */ |
| 93 | spin_lock_irqsave(&priv->cmdreg_lock, flags); | 93 | spin_lock_irqsave(&priv->cmdreg_lock, flags); |
| 94 | priv->write_reg(priv, REG_CMR, val); | 94 | priv->write_reg(priv, SJA1000_CMR, val); |
| 95 | priv->read_reg(priv, SJA1000_REG_SR); | 95 | priv->read_reg(priv, SJA1000_SR); |
| 96 | spin_unlock_irqrestore(&priv->cmdreg_lock, flags); | 96 | spin_unlock_irqrestore(&priv->cmdreg_lock, flags); |
| 97 | } | 97 | } |
| 98 | 98 | ||
| 99 | static int sja1000_is_absent(struct sja1000_priv *priv) | 99 | static int sja1000_is_absent(struct sja1000_priv *priv) |
| 100 | { | 100 | { |
| 101 | return (priv->read_reg(priv, REG_MOD) == 0xFF); | 101 | return (priv->read_reg(priv, SJA1000_MOD) == 0xFF); |
| 102 | } | 102 | } |
| 103 | 103 | ||
| 104 | static int sja1000_probe_chip(struct net_device *dev) | 104 | static int sja1000_probe_chip(struct net_device *dev) |
| @@ -116,11 +116,11 @@ static int sja1000_probe_chip(struct net_device *dev) · 11 unmodified lines | |||
| 116 | static void set_reset_mode(struct net_device *dev) | 116 | static void set_reset_mode(struct net_device *dev) |
| 117 | { | 117 | { |
| 118 | struct sja1000_priv *priv = netdev_priv(dev); | 118 | struct sja1000_priv *priv = netdev_priv(dev); |
| 119 | unsigned char status = priv->read_reg(priv, REG_MOD); | 119 | unsigned char status = priv->read_reg(priv, SJA1000_MOD); |
| 120 | int i; | 120 | int i; |
| 121 | 121 | ||
| 122 | /* disable interrupts */ | 122 | /* disable interrupts */ |
| 123 | priv->write_reg(priv, REG_IER, IRQ_OFF); | 123 | priv->write_reg(priv, SJA1000_IER, IRQ_OFF); |
| 124 | 124 | ||
| 125 | for (i = 0; i < 100; i++) { | 125 | for (i = 0; i < 100; i++) { |
| 126 | /* check reset bit */ | 126 | /* check reset bit */ |
| @@ -129,9 +129,10 @@ static void set_reset_mode(struct net_device *dev) · 2 unmodified lines | |||
| 129 | return; | 129 | return; |
| 130 | } | 130 | } |
| 131 | 131 | ||
| 132 | priv->write_reg(priv, REG_MOD, MOD_RM); /* reset chip */ | 132 | /* reset chip */ |
| 133 | priv->write_reg(priv, SJA1000_MOD, MOD_RM); | ||
| 133 | udelay(10); | 134 | udelay(10); |
| 134 | status = priv->read_reg(priv, REG_MOD); | 135 | status = priv->read_reg(priv, SJA1000_MOD); |
| 135 | } | 136 | } |
| 136 | 137 | ||
| 137 | netdev_err(dev, "setting SJA1000 into reset mode failed!\n"); | 138 | netdev_err(dev, "setting SJA1000 into reset mode failed!\n"); |
| @@ -140,7 +141,7 @@ static void set_reset_mode(struct net_device *dev) · 2 unmodified lines | |||
| 140 | static void set_normal_mode(struct net_device *dev) | 141 | static void set_normal_mode(struct net_device *dev) |
| 141 | { | 142 | { |
| 142 | struct sja1000_priv *priv = netdev_priv(dev); | 143 | struct sja1000_priv *priv = netdev_priv(dev); |
| 143 | unsigned char status = priv->read_reg(priv, REG_MOD); | 144 | unsigned char status = priv->read_reg(priv, SJA1000_MOD); |
| 144 | int i; | 145 | int i; |
| 145 | 146 | ||
| 146 | for (i = 0; i < 100; i++) { | 147 | for (i = 0; i < 100; i++) { |
| @@ -149,22 +150,22 @@ static void set_normal_mode(struct net_device *dev) · 2 unmodified lines | |||
| 149 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | 150 | priv->can.state = CAN_STATE_ERROR_ACTIVE; |
| 150 | /* enable interrupts */ | 151 | /* enable interrupts */ |
| 151 | if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) | 152 | if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) |
| 152 | priv->write_reg(priv, REG_IER, IRQ_ALL); | 153 | priv->write_reg(priv, SJA1000_IER, IRQ_ALL); |
| 153 | else | 154 | else |
| 154 | priv->write_reg(priv, REG_IER, | 155 | priv->write_reg(priv, SJA1000_IER, |
| 155 | IRQ_ALL & ~IRQ_BEI); | 156 | IRQ_ALL & ~IRQ_BEI); |
| 156 | return; | 157 | return; |
| 157 | } | 158 | } |
| 158 | 159 | ||
| 159 | /* set chip to normal mode */ | 160 | /* set chip to normal mode */ |
| 160 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | 161 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) |
| 161 | priv->write_reg(priv, REG_MOD, MOD_LOM); | 162 | priv->write_reg(priv, SJA1000_MOD, MOD_LOM); |
| 162 | else | 163 | else |
| 163 | priv->write_reg(priv, REG_MOD, 0x00); | 164 | priv->write_reg(priv, SJA1000_MOD, 0x00); |
| 164 | 165 | ||
| 165 | udelay(10); | 166 | udelay(10); |
| 166 | 167 | ||
| 167 | status = priv->read_reg(priv, REG_MOD); | 168 | status = priv->read_reg(priv, SJA1000_MOD); |
| 168 | } | 169 | } |
| 169 | 170 | ||
| 170 | netdev_err(dev, "setting SJA1000 into normal mode failed!\n"); | 171 | netdev_err(dev, "setting SJA1000 into normal mode failed!\n"); |
| @@ -179,9 +180,9 @@ static void sja1000_start(struct net_device *dev) · 8 unmodified lines | |||
| 179 | set_reset_mode(dev); | 180 | set_reset_mode(dev); |
| 180 | 181 | ||
| 181 | /* Clear error counters and error code capture */ | 182 | /* Clear error counters and error code capture */ |
| 182 | priv->write_reg(priv, REG_TXERR, 0x0); | 183 | priv->write_reg(priv, SJA1000_TXERR, 0x0); |
| 183 | priv->write_reg(priv, REG_RXERR, 0x0); | 184 | priv->write_reg(priv, SJA1000_RXERR, 0x0); |
| 184 | priv->read_reg(priv, REG_ECC); | 185 | priv->read_reg(priv, SJA1000_ECC); |
| 185 | 186 | ||
| 186 | /* leave reset mode */ | 187 | /* leave reset mode */ |
| 187 | set_normal_mode(dev); | 188 | set_normal_mode(dev); |
| @@ -217,8 +218,8 @@ static int sja1000_set_bittiming(struct net_device *dev) · 29 unmodified lines | |||
| 217 | 218 | ||
| 218 | netdev_info(dev, "setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1); | 219 | netdev_info(dev, "setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1); |
| 219 | 220 | ||
| 220 | priv->write_reg(priv, REG_BTR0, btr0); | 221 | priv->write_reg(priv, SJA1000_BTR0, btr0); |
| 221 | priv->write_reg(priv, REG_BTR1, btr1); | 222 | priv->write_reg(priv, SJA1000_BTR1, btr1); |
| 222 | 223 | ||
| 223 | return 0; | 224 | return 0; |
| 224 | } | 225 | } |
| @@ -228,8 +229,8 @@ static int sja1000_get_berr_counter(const struct net_device *dev, · 3 unmodified lines | |||
| 228 | { | 229 | { |
| 229 | struct sja1000_priv *priv = netdev_priv(dev); | 230 | struct sja1000_priv *priv = netdev_priv(dev); |
| 230 | 231 | ||
| 231 | bec->txerr = priv->read_reg(priv, REG_TXERR); | 232 | bec->txerr = priv->read_reg(priv, SJA1000_TXERR); |
| 232 | bec->rxerr = priv->read_reg(priv, REG_RXERR); | 233 | bec->rxerr = priv->read_reg(priv, SJA1000_RXERR); |
| 233 | 234 | ||
| 234 | return 0; | 235 | return 0; |
| 235 | } | 236 | } |
| @@ -247,20 +248,20 @@ static void chipset_init(struct net_device *dev) · 11 unmodified lines | |||
| 247 | struct sja1000_priv *priv = netdev_priv(dev); | 248 | struct sja1000_priv *priv = netdev_priv(dev); |
| 248 | 249 | ||
| 249 | /* set clock divider and output control register */ | 250 | /* set clock divider and output control register */ |
| 250 | priv->write_reg(priv, REG_CDR, priv->cdr | CDR_PELICAN); | 251 | priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN); |
| 251 | 252 | ||
| 252 | /* set acceptance filter (accept all) */ | 253 | /* set acceptance filter (accept all) */ |
| 253 | priv->write_reg(priv, REG_ACCC0, 0x00); | 254 | priv->write_reg(priv, SJA1000_ACCC0, 0x00); |
| 254 | priv->write_reg(priv, REG_ACCC1, 0x00); | 255 | priv->write_reg(priv, SJA1000_ACCC1, 0x00); |
| 255 | priv->write_reg(priv, REG_ACCC2, 0x00); | 256 | priv->write_reg(priv, SJA1000_ACCC2, 0x00); |
| 256 | priv->write_reg(priv, REG_ACCC3, 0x00); | 257 | priv->write_reg(priv, SJA1000_ACCC3, 0x00); |
| 257 | 258 | ||
| 258 | priv->write_reg(priv, REG_ACCM0, 0xFF); | 259 | priv->write_reg(priv, SJA1000_ACCM0, 0xFF); |
| 259 | priv->write_reg(priv, REG_ACCM1, 0xFF); | 260 | priv->write_reg(priv, SJA1000_ACCM1, 0xFF); |
| 260 | priv->write_reg(priv, REG_ACCM2, 0xFF); | 261 | priv->write_reg(priv, SJA1000_ACCM2, 0xFF); |
| 261 | priv->write_reg(priv, REG_ACCM3, 0xFF); | 262 | priv->write_reg(priv, SJA1000_ACCM3, 0xFF); |
| 262 | 263 | ||
| 263 | priv->write_reg(priv, REG_OCR, priv->ocr | OCR_MODE_NORMAL); | 264 | priv->write_reg(priv, SJA1000_OCR, priv->ocr | OCR_MODE_NORMAL); |
| 264 | } | 265 | } |
| 265 | 266 | ||
| 266 | /* | 267 | /* |
| @@ -289,21 +290,21 @@ static netdev_tx_t sja1000_start_xmit(struct sk_buff *skb, · 22 unmodified lines | |||
| 289 | id = cf->can_id; | 290 | id = cf->can_id; |
| 290 | 291 | ||
| 291 | if (id & CAN_RTR_FLAG) | 292 | if (id & CAN_RTR_FLAG) |
| 292 | fi |= FI_RTR; | 293 | fi |= SJA1000_FI_RTR; |
| 293 | 294 | ||
| 294 | if (id & CAN_EFF_FLAG) { | 295 | if (id & CAN_EFF_FLAG) { |
| 295 | fi |= FI_FF; | 296 | fi |= SJA1000_FI_FF; |
| 296 | dreg = EFF_BUF; | 297 | dreg = SJA1000_EFF_BUF; |
| 297 | priv->write_reg(priv, REG_FI, fi); | 298 | priv->write_reg(priv, SJA1000_FI, fi); |
| 298 | priv->write_reg(priv, REG_ID1, (id & 0x1fe00000) >> (5 + 16)); | 299 | priv->write_reg(priv, SJA1000_ID1, (id & 0x1fe00000) >> 21); |
| 299 | priv->write_reg(priv, REG_ID2, (id & 0x001fe000) >> (5 + 8)); | 300 | priv->write_reg(priv, SJA1000_ID2, (id & 0x001fe000) >> 13); |
| 300 | priv->write_reg(priv, REG_ID3, (id & 0x00001fe0) >> 5); | 301 | priv->write_reg(priv, SJA1000_ID3, (id & 0x00001fe0) >> 5); |
| 301 | priv->write_reg(priv, REG_ID4, (id & 0x0000001f) << 3); | 302 | priv->write_reg(priv, SJA1000_ID4, (id & 0x0000001f) << 3); |
| 302 | } else { | 303 | } else { |
| 303 | dreg = SFF_BUF; | 304 | dreg = SJA1000_SFF_BUF; |
| 304 | priv->write_reg(priv, REG_FI, fi); | 305 | priv->write_reg(priv, SJA1000_FI, fi); |
| 305 | priv->write_reg(priv, REG_ID1, (id & 0x000007f8) >> 3); | 306 | priv->write_reg(priv, SJA1000_ID1, (id & 0x000007f8) >> 3); |
| 306 | priv->write_reg(priv, REG_ID2, (id & 0x00000007) << 5); | 307 | priv->write_reg(priv, SJA1000_ID2, (id & 0x00000007) << 5); |
| 307 | } | 308 | } |
| 308 | 309 | ||
| 309 | for (i = 0; i < dlc; i++) | 310 | for (i = 0; i < dlc; i++) |
| @@ -335,25 +336,25 @@ static void sja1000_rx(struct net_device *dev) · 25 unmodified lines | |||
| 335 | if (skb == NULL) | 336 | if (skb == NULL) |
| 336 | return; | 337 | return; |
| 337 | 338 | ||
| 338 | fi = priv->read_reg(priv, REG_FI); | 339 | fi = priv->read_reg(priv, SJA1000_FI); |
| 339 | 340 | ||
| 340 | if (fi & FI_FF) { | 341 | if (fi & SJA1000_FI_FF) { |
| 341 | /* extended frame format (EFF) */ | 342 | /* extended frame format (EFF) */ |
| 342 | dreg = EFF_BUF; | 343 | dreg = SJA1000_EFF_BUF; |
| 343 | id = (priv->read_reg(priv, REG_ID1) << (5 + 16)) | 344 | id = (priv->read_reg(priv, SJA1000_ID1) << 21) |
| 344 | | (priv->read_reg(priv, REG_ID2) << (5 + 8)) | 345 | | (priv->read_reg(priv, SJA1000_ID2) << 13) |
| 345 | | (priv->read_reg(priv, REG_ID3) << 5) | 346 | | (priv->read_reg(priv, SJA1000_ID3) << 5) |
| 346 | | (priv->read_reg(priv, REG_ID4) >> 3); | 347 | | (priv->read_reg(priv, SJA1000_ID4) >> 3); |
| 347 | id |= CAN_EFF_FLAG; | 348 | id |= CAN_EFF_FLAG; |
| 348 | } else { | 349 | } else { |
| 349 | /* standard frame format (SFF) */ | 350 | /* standard frame format (SFF) */ |
| 350 | dreg = SFF_BUF; | 351 | dreg = SJA1000_SFF_BUF; |
| 351 | id = (priv->read_reg(priv, REG_ID1) << 3) | 352 | id = (priv->read_reg(priv, SJA1000_ID1) << 3) |
| 352 | | (priv->read_reg(priv, REG_ID2) >> 5); | 353 | | (priv->read_reg(priv, SJA1000_ID2) >> 5); |
| 353 | } | 354 | } |
| 354 | 355 | ||
| 355 | cf->can_dlc = get_can_dlc(fi & 0x0F); | 356 | cf->can_dlc = get_can_dlc(fi & 0x0F); |
| 356 | if (fi & FI_RTR) { | 357 | if (fi & SJA1000_FI_RTR) { |
| 357 | id |= CAN_RTR_FLAG; | 358 | id |= CAN_RTR_FLAG; |
| 358 | } else { | 359 | } else { |
| 359 | for (i = 0; i < cf->can_dlc; i++) | 360 | for (i = 0; i < cf->can_dlc; i++) |
| @@ -414,7 +415,7 @@ static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status) · 54 unmodified lines | |||
| 414 | priv->can.can_stats.bus_error++; | 415 | priv->can.can_stats.bus_error++; |
| 415 | stats->rx_errors++; | 416 | stats->rx_errors++; |
| 416 | 417 | ||
| 417 | ecc = priv->read_reg(priv, REG_ECC); | 418 | ecc = priv->read_reg(priv, SJA1000_ECC); |
| 418 | 419 | ||
| 419 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | 420 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; |
| 420 | 421 | ||
| @@ -448,7 +449,7 @@ static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status) · 27 unmodified lines | |||
| 448 | if (isrc & IRQ_ALI) { | 449 | if (isrc & IRQ_ALI) { |
| 449 | /* arbitration lost interrupt */ | 450 | /* arbitration lost interrupt */ |
| 450 | netdev_dbg(dev, "arbitration lost interrupt\n"); | 451 | netdev_dbg(dev, "arbitration lost interrupt\n"); |
| 451 | alc = priv->read_reg(priv, REG_ALC); | 452 | alc = priv->read_reg(priv, SJA1000_ALC); |
| 452 | priv->can.can_stats.arbitration_lost++; | 453 | priv->can.can_stats.arbitration_lost++; |
| 453 | stats->tx_errors++; | 454 | stats->tx_errors++; |
| 454 | cf->can_id |= CAN_ERR_LOSTARB; | 455 | cf->can_id |= CAN_ERR_LOSTARB; |
| @@ -457,8 +458,8 @@ static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status) · 2 unmodified lines | |||
| 457 | 458 | ||
| 458 | if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING || | 459 | if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING || |
| 459 | state == CAN_STATE_ERROR_PASSIVE)) { | 460 | state == CAN_STATE_ERROR_PASSIVE)) { |
| 460 | uint8_t rxerr = priv->read_reg(priv, REG_RXERR); | 461 | uint8_t rxerr = priv->read_reg(priv, SJA1000_RXERR); |
| 461 | uint8_t txerr = priv->read_reg(priv, REG_TXERR); | 462 | uint8_t txerr = priv->read_reg(priv, SJA1000_TXERR); |
| 462 | cf->can_id |= CAN_ERR_CRTL; | 463 | cf->can_id |= CAN_ERR_CRTL; |
| 463 | if (state == CAN_STATE_ERROR_WARNING) { | 464 | if (state == CAN_STATE_ERROR_WARNING) { |
| 464 | priv->can.can_stats.error_warning++; | 465 | priv->can.can_stats.error_warning++; |
| @@ -494,15 +495,16 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id) · 29 unmodified lines | |||
| 494 | int n = 0; | 495 | int n = 0; |
| 495 | 496 | ||
| 496 | /* Shared interrupts and IRQ off? */ | 497 | /* Shared interrupts and IRQ off? */ |
| 497 | if (priv->read_reg(priv, REG_IER) == IRQ_OFF) | 498 | if (priv->read_reg(priv, SJA1000_IER) == IRQ_OFF) |
| 498 | return IRQ_NONE; | 499 | return IRQ_NONE; |
| 499 | 500 | ||
| 500 | if (priv->pre_irq) | 501 | if (priv->pre_irq) |
| 501 | priv->pre_irq(priv); | 502 | priv->pre_irq(priv); |
| 502 | 503 | ||
| 503 | while ((isrc = priv->read_reg(priv, REG_IR)) && (n < SJA1000_MAX_IRQ)) { | 504 | while ((isrc = priv->read_reg(priv, SJA1000_IR)) && |
| 505 | (n < SJA1000_MAX_IRQ)) { | ||
| 504 | n++; | 506 | n++; |
| 505 | status = priv->read_reg(priv, SJA1000_REG_SR); | 507 | status = priv->read_reg(priv, SJA1000_SR); |
| 506 | /* check for absent controller due to hw unplug */ | 508 | /* check for absent controller due to hw unplug */ |
| 507 | if (status == 0xFF && sja1000_is_absent(priv)) | 509 | if (status == 0xFF && sja1000_is_absent(priv)) |
| 508 | return IRQ_NONE; | 510 | return IRQ_NONE; |
| @@ -519,7 +521,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id) · 10 unmodified lines | |||
| 519 | } else { | 521 | } else { |
| 520 | /* transmission complete */ | 522 | /* transmission complete */ |
| 521 | stats->tx_bytes += | 523 | stats->tx_bytes += |
| 522 | priv->read_reg(priv, REG_FI) & 0xf; | 524 | priv->read_reg(priv, SJA1000_FI) & 0xf; |
| 523 | stats->tx_packets++; | 525 | stats->tx_packets++; |
| 524 | can_get_echo_skb(dev, 0); | 526 | can_get_echo_skb(dev, 0); |
| 525 | } | 527 | } |
| @@ -530,7 +532,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id) · 4 unmodified lines | |||
| 530 | /* receive interrupt */ | 532 | /* receive interrupt */ |
| 531 | while (status & SR_RBS) { | 533 | while (status & SR_RBS) { |
| 532 | sja1000_rx(dev); | 534 | sja1000_rx(dev); |
| 533 | status = priv->read_reg(priv, SJA1000_REG_SR); | 535 | status = priv->read_reg(priv, SJA1000_SR); |
| 534 | /* check for absent controller */ | 536 | /* check for absent controller */ |
| 535 | if (status == 0xFF && sja1000_is_absent(priv)) | 537 | if (status == 0xFF && sja1000_is_absent(priv)) |
| 536 | return IRQ_NONE; | 538 | return IRQ_NONE; |
| @@ -54,46 +54,46 @@ · 53 unmodified lines | |||
| 54 | #define SJA1000_MAX_IRQ 20 /* max. number of interrupts handled in ISR */ | 54 | #define SJA1000_MAX_IRQ 20 /* max. number of interrupts handled in ISR */ |
| 55 | 55 | ||
| 56 | /* SJA1000 registers - manual section 6.4 (Pelican Mode) */ | 56 | /* SJA1000 registers - manual section 6.4 (Pelican Mode) */ |
| 57 | #define REG_MOD 0x00 | 57 | #define SJA1000_MOD 0x00 |
| 58 | #define REG_CMR 0x01 | 58 | #define SJA1000_CMR 0x01 |
| 59 | #define SJA1000_REG_SR 0x02 | 59 | #define SJA1000_SR 0x02 |
| 60 | #define REG_IR 0x03 | 60 | #define SJA1000_IR 0x03 |
| 61 | #define REG_IER 0x04 | 61 | #define SJA1000_IER 0x04 |
| 62 | #define REG_ALC 0x0B | 62 | #define SJA1000_ALC 0x0B |
| 63 | #define REG_ECC 0x0C | 63 | #define SJA1000_ECC 0x0C |
| 64 | #define REG_EWL 0x0D | 64 | #define SJA1000_EWL 0x0D |
| 65 | #define REG_RXERR 0x0E | 65 | #define SJA1000_RXERR 0x0E |
| 66 | #define REG_TXERR 0x0F | 66 | #define SJA1000_TXERR 0x0F |
| 67 | #define REG_ACCC0 0x10 | 67 | #define SJA1000_ACCC0 0x10 |
| 68 | #define REG_ACCC1 0x11 | 68 | #define SJA1000_ACCC1 0x11 |
| 69 | #define REG_ACCC2 0x12 | 69 | #define SJA1000_ACCC2 0x12 |
| 70 | #define REG_ACCC3 0x13 | 70 | #define SJA1000_ACCC3 0x13 |
| 71 | #define REG_ACCM0 0x14 | 71 | #define SJA1000_ACCM0 0x14 |
| 72 | #define REG_ACCM1 0x15 | 72 | #define SJA1000_ACCM1 0x15 |
| 73 | #define REG_ACCM2 0x16 | 73 | #define SJA1000_ACCM2 0x16 |
| 74 | #define REG_ACCM3 0x17 | 74 | #define SJA1000_ACCM3 0x17 |
| 75 | #define REG_RMC 0x1D | 75 | #define SJA1000_RMC 0x1D |
| 76 | #define REG_RBSA 0x1E | 76 | #define SJA1000_RBSA 0x1E |
| 77 | 77 | ||
| 78 | /* Common registers - manual section 6.5 */ | 78 | /* Common registers - manual section 6.5 */ |
| 79 | #define REG_BTR0 0x06 | 79 | #define SJA1000_BTR0 0x06 |
| 80 | #define REG_BTR1 0x07 | 80 | #define SJA1000_BTR1 0x07 |
| 81 | #define REG_OCR 0x08 | 81 | #define SJA1000_OCR 0x08 |
| 82 | #define REG_CDR 0x1F | 82 | #define SJA1000_CDR 0x1F |
| 83 | 83 | ||
| 84 | #define REG_FI 0x10 | 84 | #define SJA1000_FI 0x10 |
| 85 | #define SFF_BUF 0x13 | 85 | #define SJA1000_SFF_BUF 0x13 |
| 86 | #define EFF_BUF 0x15 | 86 | #define SJA1000_EFF_BUF 0x15 |
| 87 | 87 | ||
| 88 | #define FI_FF 0x80 | 88 | #define SJA1000_FI_FF 0x80 |
| 89 | #define FI_RTR 0x40 | 89 | #define SJA1000_FI_RTR 0x40 |
| 90 | 90 | ||
| 91 | #define REG_ID1 0x11 | 91 | #define SJA1000_ID1 0x11 |
| 92 | #define REG_ID2 0x12 | 92 | #define SJA1000_ID2 0x12 |
| 93 | #define REG_ID3 0x13 | 93 | #define SJA1000_ID3 0x13 |
| 94 | #define REG_ID4 0x14 | 94 | #define SJA1000_ID4 0x14 |
| 95 | 95 | ||
| 96 | #define CAN_RAM 0x20 | 96 | #define SJA1000_CAN_RAM 0x20 |
| 97 | 97 | ||
| 98 | /* mode register */ | 98 | /* mode register */ |
| 99 | #define MOD_RM 0x01 | 99 | #define MOD_RM 0x01 |
| @@ -306,6 +306,7 @@ static int el3_isa_match(struct device *pdev, unsigned int ndev) · 305 unmodified lines | |||
| 306 | if (!dev) | 306 | if (!dev) |
| 307 | return -ENOMEM; | 307 | return -ENOMEM; |
| 308 | 308 | ||
| 309 | SET_NETDEV_DEV(dev, pdev); | ||
| 309 | netdev_boot_setup_check(dev); | 310 | netdev_boot_setup_check(dev); |
| 310 | 311 | ||
| 311 | if (!request_region(ioaddr, EL3_IO_EXTENT, "3c509-isa")) { | 312 | if (!request_region(ioaddr, EL3_IO_EXTENT, "3c509-isa")) { |
| @@ -595,6 +596,7 @@ static int __init el3_eisa_probe (struct device *device) · 283 unmodified lines | |||
| 595 | return -ENOMEM; | 596 | return -ENOMEM; |
| 596 | } | 597 | } |
| 597 | 598 | ||
| 599 | SET_NETDEV_DEV(dev, device); | ||
| 598 | netdev_boot_setup_check(dev); | 600 | netdev_boot_setup_check(dev); |
| 599 | 601 | ||
| 600 | el3_dev_fill(dev, phys_addr, ioaddr, irq, if_port, EL3_EISA); | 602 | el3_dev_fill(dev, phys_addr, ioaddr, irq, if_port, EL3_EISA); |
| @@ -1690,7 +1690,7 @@ typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * read · 1689 unmodified lines | |||
| 1690 | skb_checksum_none_assert(new_skb); | 1690 | skb_checksum_none_assert(new_skb); |
| 1691 | 1691 | ||
| 1692 | if (rx->rxStatus & TYPHOON_RX_VLAN) | 1692 | if (rx->rxStatus & TYPHOON_RX_VLAN) |
| 1693 | __vlan_hwaccel_put_tag(new_skb, | 1693 | __vlan_hwaccel_put_tag(new_skb, htons(ETH_P_8021Q), |
| 1694 | ntohl(rx->vlanTag) & 0xffff); | 1694 | ntohl(rx->vlanTag) & 0xffff); |
| 1695 | netif_receive_skb(new_skb); | 1695 | netif_receive_skb(new_skb); |
| 1696 | 1696 | ||
| @@ -2445,9 +2445,9 @@ typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 748 unmodified lines | |||
| 2445 | * settings -- so we only allow the user to toggle the TX processing. | 2445 | * settings -- so we only allow the user to toggle the TX processing. |
| 2446 | */ | 2446 | */ |
| 2447 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | 2447 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
| 2448 | NETIF_F_HW_VLAN_TX; | 2448 | NETIF_F_HW_VLAN_CTAG_TX; |
| 2449 | dev->features = dev->hw_features | | 2449 | dev->features = dev->hw_features | |
| 2450 | NETIF_F_HW_VLAN_RX | NETIF_F_RXCSUM; | 2450 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_RXCSUM; |
| 2451 | 2451 | ||
| 2452 | if(register_netdev(dev) < 0) { | 2452 | if(register_netdev(dev) < 0) { |
| 2453 | err_msg = "unable to register netdev"; | 2453 | err_msg = "unable to register netdev"; |
| @@ -594,7 +594,8 @@ static const struct ethtool_ops ethtool_ops; · 593 unmodified lines | |||
| 594 | 594 | ||
| 595 | 595 | ||
| 596 | #ifdef VLAN_SUPPORT | 596 | #ifdef VLAN_SUPPORT |
| 597 | static int netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid) | 597 | static int netdev_vlan_rx_add_vid(struct net_device *dev, |
| 598 | __be16 proto, u16 vid) | ||
| 598 | { | 599 | { |
| 599 | struct netdev_private *np = netdev_priv(dev); | 600 | struct netdev_private *np = netdev_priv(dev); |
| 600 | 601 | ||
| @@ -608,7 +609,8 @@ static int netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid) · 7 unmodified lines | |||
| 608 | return 0; | 609 | return 0; |
| 609 | } | 610 | } |
| 610 | 611 | ||
| 611 | static int netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | 612 | static int netdev_vlan_rx_kill_vid(struct net_device *dev, |
| 613 | __be16 proto, u16 vid) | ||
| 612 | { | 614 | { |
| 613 | struct netdev_private *np = netdev_priv(dev); | 615 | struct netdev_private *np = netdev_priv(dev); |
| 614 | 616 | ||
| @@ -702,7 +704,7 @@ static int starfire_init_one(struct pci_dev *pdev, · 87 unmodified lines | |||
| 702 | #endif /* ZEROCOPY */ | 704 | #endif /* ZEROCOPY */ |
| 703 | 705 | ||
| 704 | #ifdef VLAN_SUPPORT | 706 | #ifdef VLAN_SUPPORT |
| 705 | dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER; | 707 | dev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER; |
| 706 | #endif /* VLAN_RX_KILL_VID */ | 708 | #endif /* VLAN_RX_KILL_VID */ |
| 707 | #ifdef ADDR_64BITS | 709 | #ifdef ADDR_64BITS |
| 708 | dev->features |= NETIF_F_HIGHDMA; | 710 | dev->features |= NETIF_F_HIGHDMA; |
| @@ -1496,7 +1498,7 @@ static int __netdev_rx(struct net_device *dev, int *quota) · 787 unmodified lines | |||
| 1496 | printk(KERN_DEBUG " netdev_rx() vlanid = %d\n", | 1498 | printk(KERN_DEBUG " netdev_rx() vlanid = %d\n", |
| 1497 | vlid); | 1499 | vlid); |
| 1498 | } | 1500 | } |
| 1499 | __vlan_hwaccel_put_tag(skb, vlid); | 1501 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlid); |
| 1500 | } | 1502 | } |
| 1501 | #endif /* VLAN_SUPPORT */ | 1503 | #endif /* VLAN_SUPPORT */ |
| 1502 | netif_receive_skb(skb); | 1504 | netif_receive_skb(skb); |
| @@ -188,10 +188,9 @@ static int desc_list_init(struct net_device *dev) · 187 unmodified lines | |||
| 188 | 188 | ||
| 189 | /* allocate a new skb for next time receive */ | 189 | /* allocate a new skb for next time receive */ |
| 190 | new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); | 190 | new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); |
| 191 | if (!new_skb) { | 191 | if (!new_skb) |
| 192 | pr_notice("init: low on mem - packet dropped\n"); | ||
| 193 | goto init_error; | 192 | goto init_error; |
| 194 | } | 193 | |
| 195 | skb_reserve(new_skb, NET_IP_ALIGN); | 194 | skb_reserve(new_skb, NET_IP_ALIGN); |
| 196 | /* Invidate the data cache of skb->data range when it is write back | 195 | /* Invidate the data cache of skb->data range when it is write back |
| 197 | * cache. It will prevent overwritting the new data from DMA | 196 | * cache. It will prevent overwritting the new data from DMA |
| @@ -1236,7 +1235,6 @@ static void bfin_mac_rx(struct net_device *dev) · 1038 unmodified lines | |||
| 1236 | 1235 | ||
| 1237 | new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); | 1236 | new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); |
| 1238 | if (!new_skb) { | 1237 | if (!new_skb) { |
| 1239 | netdev_notice(dev, "rx: low on mem - packet dropped\n"); | ||
| 1240 | dev->stats.rx_dropped++; | 1238 | dev->stats.rx_dropped++; |
| 1241 | goto out; | 1239 | goto out; |
| 1242 | } | 1240 | } |
| @@ -1464,35 +1464,23 @@ static int greth_of_probe(struct platform_device *ofdev) · 1463 unmodified lines | |||
| 1464 | } | 1464 | } |
| 1465 | 1465 | ||
| 1466 | /* Allocate TX descriptor ring in coherent memory */ | 1466 | /* Allocate TX descriptor ring in coherent memory */ |
| 1467 | greth->tx_bd_base = (struct greth_bd *) dma_alloc_coherent(greth->dev, | 1467 | greth->tx_bd_base = dma_alloc_coherent(greth->dev, 1024, |
| 1468 | 1024, | 1468 | &greth->tx_bd_base_phys, |
| 1469 | &greth->tx_bd_base_phys, | 1469 | GFP_KERNEL | __GFP_ZERO); |
| 1470 | GFP_KERNEL); | ||
| 1471 | |||
| 1472 | if (!greth->tx_bd_base) { | 1470 | if (!greth->tx_bd_base) { |
| 1473 | if (netif_msg_probe(greth)) | ||
| 1474 | dev_err(&dev->dev, "could not allocate descriptor memory.\n"); | ||
| 1475 | err = -ENOMEM; | 1471 | err = -ENOMEM; |
| 1476 | goto error3; | 1472 | goto error3; |
| 1477 | } | 1473 | } |
| 1478 | 1474 | ||
| 1479 | memset(greth->tx_bd_base, 0, 1024); | ||
| 1480 | |||
| 1481 | /* Allocate RX descriptor ring in coherent memory */ | 1475 | /* Allocate RX descriptor ring in coherent memory */ |
| 1482 | greth->rx_bd_base = (struct greth_bd *) dma_alloc_coherent(greth->dev, | 1476 | greth->rx_bd_base = dma_alloc_coherent(greth->dev, 1024, |
| 1483 | 1024, | 1477 | &greth->rx_bd_base_phys, |
| 1484 | &greth->rx_bd_base_phys, | 1478 | GFP_KERNEL | __GFP_ZERO); |
| 1485 | GFP_KERNEL); | ||
| 1486 | |||
| 1487 | if (!greth->rx_bd_base) { | 1479 | if (!greth->rx_bd_base) { |
| 1488 | if (netif_msg_probe(greth)) | ||
| 1489 | dev_err(greth->dev, "could not allocate descriptor memory.\n"); | ||
| 1490 | err = -ENOMEM; | 1480 | err = -ENOMEM; |
| 1491 | goto error4; | 1481 | goto error4; |
| 1492 | } | 1482 | } |
| 1493 | 1483 | ||
| 1494 | memset(greth->rx_bd_base, 0, 1024); | ||
| 1495 | |||
| 1496 | /* Get MAC address from: module param, OF property or ID prom */ | 1484 | /* Get MAC address from: module param, OF property or ID prom */ |
| 1497 | for (i = 0; i < 6; i++) { | 1485 | for (i = 0; i < 6; i++) { |
| 1498 | if (macaddr[i] != 0) | 1486 | if (macaddr[i] != 0) |
| @@ -472,7 +472,7 @@ static int acenic_probe_one(struct pci_dev *pdev, · 471 unmodified lines | |||
| 472 | ap->name = pci_name(pdev); | 472 | ap->name = pci_name(pdev); |
| 473 | 473 | ||
| 474 | dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; | 474 | dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; |
| 475 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | 475 | dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
| 476 | 476 | ||
| 477 | dev->watchdog_timeo = 5*HZ; | 477 | dev->watchdog_timeo = 5*HZ; |
| 478 | 478 | ||
| @@ -2019,7 +2019,7 @@ static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm) · 1540 unmodified lines | |||
| 2019 | 2019 | ||
| 2020 | /* send it up */ | 2020 | /* send it up */ |
| 2021 | if ((bd_flags & BD_FLG_VLAN_TAG)) | 2021 | if ((bd_flags & BD_FLG_VLAN_TAG)) |
| 2022 | __vlan_hwaccel_put_tag(skb, retdesc->vlan); | 2022 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), retdesc->vlan); |
| 2023 | netif_rx(skb); | 2023 | netif_rx(skb); |
| 2024 | 2024 | ||
| 2025 | dev->stats.rx_packets++; | 2025 | dev->stats.rx_packets++; |
| @@ -318,8 +318,6 @@ static int lance_rx (struct net_device *dev) · 317 unmodified lines | |||
| 318 | struct sk_buff *skb = netdev_alloc_skb(dev, len + 2); | 318 | struct sk_buff *skb = netdev_alloc_skb(dev, len + 2); |
| 319 | 319 | ||
| 320 | if (!skb) { | 320 | if (!skb) { |
| 321 | printk ("%s: Memory squeeze, deferring packet.\n", | ||
| 322 | dev->name); | ||
| 323 | dev->stats.rx_dropped++; | 321 | dev->stats.rx_dropped++; |
| 324 | rd->mblength = 0; | 322 | rd->mblength = 0; |
| 325 | rd->rmd1_bits = LE_R1_OWN; | 323 | rd->rmd1_bits = LE_R1_OWN; |
| @@ -293,7 +293,6 @@ static int lance_rx(struct net_device *dev) · 292 unmodified lines | |||
| 293 | struct sk_buff *skb = netdev_alloc_skb(dev, len + 2); | 293 | struct sk_buff *skb = netdev_alloc_skb(dev, len + 2); |
| 294 | 294 | ||
| 295 | if (!skb) { | 295 | if (!skb) { |
| 296 | netdev_warn(dev, "Memory squeeze, deferring packet\n"); | ||
| 297 | dev->stats.rx_dropped++; | 296 | dev->stats.rx_dropped++; |
| 298 | rd->mblength = 0; | 297 | rd->mblength = 0; |
| 299 | rd->rmd1_bits = LE_R1_OWN; | 298 | rd->rmd1_bits = LE_R1_OWN; |
| @@ -528,7 +528,6 @@ am79c961_rx(struct net_device *dev, struct dev_priv *priv) · 527 unmodified lines | |||
| 528 | dev->stats.rx_packets++; | 528 | dev->stats.rx_packets++; |
| 529 | } else { | 529 | } else { |
| 530 | am_writeword (dev, hdraddr + 2, RMD_OWN); | 530 | am_writeword (dev, hdraddr + 2, RMD_OWN); |
| 531 | printk (KERN_WARNING "%s: memory squeeze, dropping packet.\n", dev->name); | ||
| 532 | dev->stats.rx_dropped++; | 531 | dev->stats.rx_dropped++; |
| 533 | break; | 532 | break; |
| 534 | } | 533 | } |
| @@ -793,7 +793,7 @@ static int amd8111e_rx_poll(struct napi_struct *napi, int budget) · 792 unmodified lines | |||
| 793 | #if AMD8111E_VLAN_TAG_USED | 793 | #if AMD8111E_VLAN_TAG_USED |
| 794 | if (vtag == TT_VLAN_TAGGED){ | 794 | if (vtag == TT_VLAN_TAGGED){ |
| 795 | u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info); | 795 | u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info); |
| 796 | __vlan_hwaccel_put_tag(skb, vlan_tag); | 796 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); |
| 797 | } | 797 | } |
| 798 | #endif | 798 | #endif |
| 799 | netif_receive_skb(skb); | 799 | netif_receive_skb(skb); |
| @@ -1869,7 +1869,7 @@ static int amd8111e_probe_one(struct pci_dev *pdev, · 1069 unmodified lines | |||
| 1869 | SET_NETDEV_DEV(dev, &pdev->dev); | 1869 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 1870 | 1870 | ||
| 1871 | #if AMD8111E_VLAN_TAG_USED | 1871 | #if AMD8111E_VLAN_TAG_USED |
| 1872 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ; | 1872 | dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX ; |
| 1873 | #endif | 1873 | #endif |
| 1874 | 1874 | ||
| 1875 | lp = netdev_priv(dev); | 1875 | lp = netdev_priv(dev); |
| @@ -1907,7 +1907,7 @@ static int amd8111e_probe_one(struct pci_dev *pdev, · 31 unmodified lines | |||
| 1907 | netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32); | 1907 | netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32); |
| 1908 | 1908 | ||
| 1909 | #if AMD8111E_VLAN_TAG_USED | 1909 | #if AMD8111E_VLAN_TAG_USED |
| 1910 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | 1910 | dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
| 1911 | #endif | 1911 | #endif |
| 1912 | /* Probe the external PHY */ | 1912 | /* Probe the external PHY */ |
| 1913 | amd8111e_probe_ext_phy(dev); | 1913 | amd8111e_probe_ext_phy(dev); |
| @@ -193,7 +193,6 @@ static int ariadne_rx(struct net_device *dev) · 192 unmodified lines | |||
| 193 | 193 | ||
| 194 | skb = netdev_alloc_skb(dev, pkt_len + 2); | 194 | skb = netdev_alloc_skb(dev, pkt_len + 2); |
| 195 | if (skb == NULL) { | 195 | if (skb == NULL) { |
| 196 | netdev_warn(dev, "Memory squeeze, deferring packet\n"); | ||
| 197 | for (i = 0; i < RX_RING_SIZE; i++) | 196 | for (i = 0; i < RX_RING_SIZE; i++) |
| 198 | if (lowb(priv->rx_ring[(entry + i) % RX_RING_SIZE]->RMD1) & RF_OWN) | 197 | if (lowb(priv->rx_ring[(entry + i) % RX_RING_SIZE]->RMD1) & RF_OWN) |
| 199 | break; | 198 | break; |
| @@ -996,8 +996,6 @@ static int lance_rx( struct net_device *dev ) · 995 unmodified lines | |||
| 996 | else { | 996 | else { |
| 997 | skb = netdev_alloc_skb(dev, pkt_len + 2); | 997 | skb = netdev_alloc_skb(dev, pkt_len + 2); |
| 998 | if (skb == NULL) { | 998 | if (skb == NULL) { |
| 999 | DPRINTK( 1, ( "%s: Memory squeeze, deferring packet.\n", | ||
| 1000 | dev->name )); | ||
| 1001 | for( i = 0; i < RX_RING_SIZE; i++ ) | 999 | for( i = 0; i < RX_RING_SIZE; i++ ) |
| 1002 | if (MEM->rx_head[(entry+i) & RX_RING_MOD_MASK].flag & | 1000 | if (MEM->rx_head[(entry+i) & RX_RING_MOD_MASK].flag & |
| 1003 | RMD1_OWN_CHIP) | 1001 | RMD1_OWN_CHIP) |
| @@ -1149,9 +1147,7 @@ static struct net_device *atarilance_dev; · 145 unmodified lines | |||
| 1149 | static int __init atarilance_module_init(void) | 1147 | static int __init atarilance_module_init(void) |
| 1150 | { | 1148 | { |
| 1151 | atarilance_dev = atarilance_probe(-1); | 1149 | atarilance_dev = atarilance_probe(-1); |
| 1152 | if (IS_ERR(atarilance_dev)) | 1150 | return PTR_RET(atarilance_dev); |
| 1153 | return PTR_ERR(atarilance_dev); | ||
| 1154 | return 0; | ||
| 1155 | } | 1151 | } |
| 1156 | 1152 | ||
| 1157 | static void __exit atarilance_module_exit(void) | 1153 | static void __exit atarilance_module_exit(void) |
| @@ -727,7 +727,6 @@ static int au1000_rx(struct net_device *dev) · 726 unmodified lines | |||
| 727 | frmlen -= 4; /* Remove FCS */ | 727 | frmlen -= 4; /* Remove FCS */ |
| 728 | skb = netdev_alloc_skb(dev, frmlen + 2); | 728 | skb = netdev_alloc_skb(dev, frmlen + 2); |
| 729 | if (skb == NULL) { | 729 | if (skb == NULL) { |
| 730 | netdev_err(dev, "Memory squeeze, dropping packet.\n"); | ||
| 731 | dev->stats.rx_dropped++; | 730 | dev->stats.rx_dropped++; |
| 732 | continue; | 731 | continue; |
| 733 | } | 732 | } |
| @@ -607,8 +607,6 @@ static int lance_rx(struct net_device *dev) · 606 unmodified lines | |||
| 607 | skb = netdev_alloc_skb(dev, len + 2); | 607 | skb = netdev_alloc_skb(dev, len + 2); |
| 608 | 608 | ||
| 609 | if (skb == 0) { | 609 | if (skb == 0) { |
| 610 | printk("%s: Memory squeeze, deferring packet.\n", | ||
| 611 | dev->name); | ||
| 612 | dev->stats.rx_dropped++; | 610 | dev->stats.rx_dropped++; |
| 613 | *rds_ptr(rd, mblength, lp->type) = 0; | 611 | *rds_ptr(rd, mblength, lp->type) = 0; |
| 614 | *rds_ptr(rd, rmd1, lp->type) = | 612 | *rds_ptr(rd, rmd1, lp->type) = |
| @@ -188,9 +188,7 @@ static struct net_device *dev_mvme147_lance; · 187 unmodified lines | |||
| 188 | int __init init_module(void) | 188 | int __init init_module(void) |
| 189 | { | 189 | { |
| 190 | dev_mvme147_lance = mvme147lance_probe(-1); | 190 | dev_mvme147_lance = mvme147lance_probe(-1); |
| 191 | if (IS_ERR(dev_mvme147_lance)) | 191 | return PTR_RET(dev_mvme147_lance); |
| 192 | return PTR_ERR(dev_mvme147_lance); | ||
| 193 | return 0; | ||
| 194 | } | 192 | } |
| 195 | 193 | ||
| 196 | void __exit cleanup_module(void) | 194 | void __exit cleanup_module(void) |
| @@ -1238,7 +1238,7 @@ MODULE_PARM_DESC(dma, "ni6510 ISA DMA channel (ignored for some cards)"); · 1237 unmodified lines | |||
| 1238 | int __init init_module(void) | 1238 | int __init init_module(void) |
| 1239 | { | 1239 | { |
| 1240 | dev_ni65 = ni65_probe(-1); | 1240 | dev_ni65 = ni65_probe(-1); |
| 1241 | return IS_ERR(dev_ni65) ? PTR_ERR(dev_ni65) : 0; | 1241 | return PTR_RET(dev_ni65); |
| 1242 | } | 1242 | } |
| 1243 | 1243 | ||
| 1244 | void __exit cleanup_module(void) | 1244 | void __exit cleanup_module(void) |
| @@ -1166,7 +1166,6 @@ static void pcnet32_rx_entry(struct net_device *dev, · 1165 unmodified lines | |||
| 1166 | skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN); | 1166 | skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN); |
| 1167 | 1167 | ||
| 1168 | if (skb == NULL) { | 1168 | if (skb == NULL) { |
| 1169 | netif_err(lp, drv, dev, "Memory squeeze, dropping packet\n"); | ||
| 1170 | dev->stats.rx_dropped++; | 1169 | dev->stats.rx_dropped++; |
| 1171 | return; | 1170 | return; |
| 1172 | } | 1171 | } |
| @@ -812,9 +812,6 @@ static int lance_rx( struct net_device *dev ) · 811 unmodified lines | |||
| 812 | else { | 812 | else { |
| 813 | skb = netdev_alloc_skb(dev, pkt_len + 2); | 813 | skb = netdev_alloc_skb(dev, pkt_len + 2); |
| 814 | if (skb == NULL) { | 814 | if (skb == NULL) { |
| 815 | DPRINTK( 1, ( "%s: Memory squeeze, deferring packet.\n", | ||
| 816 | dev->name )); | ||
| 817 | |||
| 818 | dev->stats.rx_dropped++; | 815 | dev->stats.rx_dropped++; |
| 819 | head->msg_length = 0; | 816 | head->msg_length = 0; |
| 820 | head->flag |= RMD1_OWN_CHIP; | 817 | head->flag |= RMD1_OWN_CHIP; |
| @@ -943,9 +940,7 @@ static struct net_device *sun3lance_dev; · 122 unmodified lines | |||
| 943 | int __init init_module(void) | 940 | int __init init_module(void) |
| 944 | { | 941 | { |
| 945 | sun3lance_dev = sun3lance_probe(-1); | 942 | sun3lance_dev = sun3lance_probe(-1); |
| 946 | if (IS_ERR(sun3lance_dev)) | 943 | return PTR_RET(sun3lance_dev); |
| 947 | return PTR_ERR(sun3lance_dev); | ||
| 948 | return 0; | ||
| 949 | } | 944 | } |
| 950 | 945 | ||
| 951 | void __exit cleanup_module(void) | 946 | void __exit cleanup_module(void) |
| @@ -536,8 +536,6 @@ static void lance_rx_dvma(struct net_device *dev) · 535 unmodified lines | |||
| 536 | skb = netdev_alloc_skb(dev, len + 2); | 536 | skb = netdev_alloc_skb(dev, len + 2); |
| 537 | 537 | ||
| 538 | if (skb == NULL) { | 538 | if (skb == NULL) { |
| 539 | printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", | ||
| 540 | dev->name); | ||
| 541 | dev->stats.rx_dropped++; | 539 | dev->stats.rx_dropped++; |
| 542 | rd->mblength = 0; | 540 | rd->mblength = 0; |
| 543 | rd->rmd1_bits = LE_R1_OWN; | 541 | rd->rmd1_bits = LE_R1_OWN; |
| @@ -708,8 +706,6 @@ static void lance_rx_pio(struct net_device *dev) · 164 unmodified lines | |||
| 708 | skb = netdev_alloc_skb(dev, len + 2); | 706 | skb = netdev_alloc_skb(dev, len + 2); |
| 709 | 707 | ||
| 710 | if (skb == NULL) { | 708 | if (skb == NULL) { |
| 711 | printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", | ||
| 712 | dev->name); | ||
| 713 | dev->stats.rx_dropped++; | 709 | dev->stats.rx_dropped++; |
| 714 | sbus_writew(0, &rd->mblength); | 710 | sbus_writew(0, &rd->mblength); |
| 715 | sbus_writeb(LE_R1_OWN, &rd->rmd1_bits); | 711 | sbus_writeb(LE_R1_OWN, &rd->rmd1_bits); |
| @@ -1377,10 +1373,9 @@ static int sparc_lance_probe_one(struct platform_device *op, · 661 unmodified lines | |||
| 1377 | dma_alloc_coherent(&op->dev, | 1373 | dma_alloc_coherent(&op->dev, |
| 1378 | sizeof(struct lance_init_block), | 1374 | sizeof(struct lance_init_block), |
| 1379 | &lp->init_block_dvma, GFP_ATOMIC); | 1375 | &lp->init_block_dvma, GFP_ATOMIC); |
| 1380 | if (!lp->init_block_mem) { | 1376 | if (!lp->init_block_mem) |
| 1381 | printk(KERN_ERR "SunLance: Cannot allocate consistent DMA memory.\n"); | ||
| 1382 | goto fail; | 1377 | goto fail; |
| 1383 | } | 1378 | |
| 1384 | lp->pio_buffer = 0; | 1379 | lp->pio_buffer = 0; |
| 1385 | lp->init_ring = lance_init_ring_dvma; | 1380 | lp->init_ring = lance_init_ring_dvma; |
| 1386 | lp->rx = lance_rx_dvma; | 1381 | lp->rx = lance_rx_dvma; |
| @@ -386,20 +386,16 @@ static int mace_open(struct net_device *dev) · 385 unmodified lines | |||
| 386 | /* Allocate the DMA ring buffers */ | 386 | /* Allocate the DMA ring buffers */ |
| 387 | 387 | ||
| 388 | mp->tx_ring = dma_alloc_coherent(mp->device, | 388 | mp->tx_ring = dma_alloc_coherent(mp->device, |
| 389 | N_TX_RING * MACE_BUFF_SIZE, | 389 | N_TX_RING * MACE_BUFF_SIZE, |
| 390 | &mp->tx_ring_phys, GFP_KERNEL); | 390 | &mp->tx_ring_phys, GFP_KERNEL); |
| 391 | if (mp->tx_ring == NULL) { | 391 | if (mp->tx_ring == NULL) |
| 392 | printk(KERN_ERR "%s: unable to allocate DMA tx buffers\n", dev->name); | ||
| 393 | goto out1; | 392 | goto out1; |
| 394 | } | ||
| 395 | 393 | ||
| 396 | mp->rx_ring = dma_alloc_coherent(mp->device, | 394 | mp->rx_ring = dma_alloc_coherent(mp->device, |
| 397 | N_RX_RING * MACE_BUFF_SIZE, | 395 | N_RX_RING * MACE_BUFF_SIZE, |
| 398 | &mp->rx_ring_phys, GFP_KERNEL); | 396 | &mp->rx_ring_phys, GFP_KERNEL); |
| 399 | if (mp->rx_ring == NULL) { | 397 | if (mp->rx_ring == NULL) |
| 400 | printk(KERN_ERR "%s: unable to allocate DMA rx buffers\n", dev->name); | ||
| 401 | goto out2; | 398 | goto out2; |
| 402 | } | ||
| 403 | 399 | ||
| 404 | mace_dma_off(dev); | 400 | mace_dma_off(dev); |
| 405 | 401 | ||
| @@ -417,7 +417,7 @@ static void atl1c_set_multi(struct net_device *netdev) · 416 unmodified lines | |||
| 417 | 417 | ||
| 418 | static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data) | 418 | static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data) |
| 419 | { | 419 | { |
| 420 | if (features & NETIF_F_HW_VLAN_RX) { | 420 | if (features & NETIF_F_HW_VLAN_CTAG_RX) { |
| 421 | /* enable VLAN tag insert/strip */ | 421 | /* enable VLAN tag insert/strip */ |
| 422 | *mac_ctrl_data |= MAC_CTRL_RMV_VLAN; | 422 | *mac_ctrl_data |= MAC_CTRL_RMV_VLAN; |
| 423 | } else { | 423 | } else { |
| @@ -494,10 +494,10 @@ static netdev_features_t atl1c_fix_features(struct net_device *netdev, · 70 unmodified lines | |||
| 494 | * Since there is no support for separate rx/tx vlan accel | 494 | * Since there is no support for separate rx/tx vlan accel |
| 495 | * enable/disable make sure tx flag is always in same state as rx. | 495 | * enable/disable make sure tx flag is always in same state as rx. |
| 496 | */ | 496 | */ |
| 497 | if (features & NETIF_F_HW_VLAN_RX) | 497 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 498 | features |= NETIF_F_HW_VLAN_TX; | 498 | features |= NETIF_F_HW_VLAN_CTAG_TX; |
| 499 | else | 499 | else |
| 500 | features &= ~NETIF_F_HW_VLAN_TX; | 500 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 501 | 501 | ||
| 502 | if (netdev->mtu > MAX_TSO_FRAME_SIZE) | 502 | if (netdev->mtu > MAX_TSO_FRAME_SIZE) |
| 503 | features &= ~(NETIF_F_TSO | NETIF_F_TSO6); | 503 | features &= ~(NETIF_F_TSO | NETIF_F_TSO6); |
| @@ -510,7 +510,7 @@ static int atl1c_set_features(struct net_device *netdev, · 6 unmodified lines | |||
| 510 | { | 510 | { |
| 511 | netdev_features_t changed = netdev->features ^ features; | 511 | netdev_features_t changed = netdev->features ^ features; |
| 512 | 512 | ||
| 513 | if (changed & NETIF_F_HW_VLAN_RX) | 513 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
| 514 | atl1c_vlan_mode(netdev, features); | 514 | atl1c_vlan_mode(netdev, features); |
| 515 | 515 | ||
| 516 | return 0; | 516 | return 0; |
| @@ -1809,7 +1809,7 @@ rrs_checked: · 1292 unmodified lines | |||
| 1809 | 1809 | ||
| 1810 | AT_TAG_TO_VLAN(rrs->vlan_tag, vlan); | 1810 | AT_TAG_TO_VLAN(rrs->vlan_tag, vlan); |
| 1811 | vlan = le16_to_cpu(vlan); | 1811 | vlan = le16_to_cpu(vlan); |
| 1812 | __vlan_hwaccel_put_tag(skb, vlan); | 1812 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan); |
| 1813 | } | 1813 | } |
| 1814 | netif_receive_skb(skb); | 1814 | netif_receive_skb(skb); |
| 1815 | 1815 | ||
| @@ -2475,13 +2475,13 @@ static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev) · 659 unmodified lines | |||
| 2475 | atl1c_set_ethtool_ops(netdev); | 2475 | atl1c_set_ethtool_ops(netdev); |
| 2476 | 2476 | ||
| 2477 | /* TODO: add when ready */ | 2477 | /* TODO: add when ready */ |
| 2478 | netdev->hw_features = NETIF_F_SG | | 2478 | netdev->hw_features = NETIF_F_SG | |
| 2479 | NETIF_F_HW_CSUM | | 2479 | NETIF_F_HW_CSUM | |
| 2480 | NETIF_F_HW_VLAN_RX | | 2480 | NETIF_F_HW_VLAN_CTAG_RX | |
| 2481 | NETIF_F_TSO | | 2481 | NETIF_F_TSO | |
| 2482 | NETIF_F_TSO6; | 2482 | NETIF_F_TSO6; |
| 2483 | netdev->features = netdev->hw_features | | 2483 | netdev->features = netdev->hw_features | |
| 2484 | NETIF_F_HW_VLAN_TX; | 2484 | NETIF_F_HW_VLAN_CTAG_TX; |
| 2485 | return 0; | 2485 | return 0; |
| 2486 | } | 2486 | } |
| 2487 | 2487 | ||
| @@ -315,7 +315,7 @@ static void atl1e_set_multi(struct net_device *netdev) · 314 unmodified lines | |||
| 315 | 315 | ||
| 316 | static void __atl1e_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data) | 316 | static void __atl1e_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data) |
| 317 | { | 317 | { |
| 318 | if (features & NETIF_F_HW_VLAN_RX) { | 318 | if (features & NETIF_F_HW_VLAN_CTAG_RX) { |
| 319 | /* enable VLAN tag insert/strip */ | 319 | /* enable VLAN tag insert/strip */ |
| 320 | *mac_ctrl_data |= MAC_CTRL_RMV_VLAN; | 320 | *mac_ctrl_data |= MAC_CTRL_RMV_VLAN; |
| 321 | } else { | 321 | } else { |
| @@ -378,10 +378,10 @@ static netdev_features_t atl1e_fix_features(struct net_device *netdev, · 56 unmodified lines | |||
| 378 | * Since there is no support for separate rx/tx vlan accel | 378 | * Since there is no support for separate rx/tx vlan accel |
| 379 | * enable/disable make sure tx flag is always in same state as rx. | 379 | * enable/disable make sure tx flag is always in same state as rx. |
| 380 | */ | 380 | */ |
| 381 | if (features & NETIF_F_HW_VLAN_RX) | 381 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 382 | features |= NETIF_F_HW_VLAN_TX; | 382 | features |= NETIF_F_HW_VLAN_CTAG_TX; |
| 383 | else | 383 | else |
| 384 | features &= ~NETIF_F_HW_VLAN_TX; | 384 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 385 | 385 | ||
| 386 | return features; | 386 | return features; |
| 387 | } | 387 | } |
| @@ -391,7 +391,7 @@ static int atl1e_set_features(struct net_device *netdev, · 3 unmodified lines | |||
| 391 | { | 391 | { |
| 392 | netdev_features_t changed = netdev->features ^ features; | 392 | netdev_features_t changed = netdev->features ^ features; |
| 393 | 393 | ||
| 394 | if (changed & NETIF_F_HW_VLAN_RX) | 394 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
| 395 | atl1e_vlan_mode(netdev, features); | 395 | atl1e_vlan_mode(netdev, features); |
| 396 | 396 | ||
| 397 | return 0; | 397 | return 0; |
| @@ -1420,11 +1420,9 @@ static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter, u8 que, · 1022 unmodified lines | |||
| 1420 | packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) & | 1420 | packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) & |
| 1421 | RRS_PKT_SIZE_MASK) - 4; /* CRC */ | 1421 | RRS_PKT_SIZE_MASK) - 4; /* CRC */ |
| 1422 | skb = netdev_alloc_skb_ip_align(netdev, packet_size); | 1422 | skb = netdev_alloc_skb_ip_align(netdev, packet_size); |
| 1423 | if (skb == NULL) { | 1423 | if (skb == NULL) |
| 1424 | netdev_warn(netdev, | ||
| 1425 | "Memory squeeze, deferring packet\n"); | ||
| 1426 | goto skip_pkt; | 1424 | goto skip_pkt; |
| 1427 | } | 1425 | |
| 1428 | memcpy(skb->data, (u8 *)(prrs + 1), packet_size); | 1426 | memcpy(skb->data, (u8 *)(prrs + 1), packet_size); |
| 1429 | skb_put(skb, packet_size); | 1427 | skb_put(skb, packet_size); |
| 1430 | skb->protocol = eth_type_trans(skb, netdev); | 1428 | skb->protocol = eth_type_trans(skb, netdev); |
| @@ -1437,7 +1435,7 @@ static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter, u8 que, · 6 unmodified lines | |||
| 1437 | netdev_dbg(netdev, | 1435 | netdev_dbg(netdev, |
| 1438 | "RXD VLAN TAG<RRD>=0x%04x\n", | 1436 | "RXD VLAN TAG<RRD>=0x%04x\n", |
| 1439 | prrs->vtag); | 1437 | prrs->vtag); |
| 1440 | __vlan_hwaccel_put_tag(skb, vlan_tag); | 1438 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); |
| 1441 | } | 1439 | } |
| 1442 | netif_receive_skb(skb); | 1440 | netif_receive_skb(skb); |
| 1443 | 1441 | ||
| @@ -2200,9 +2198,9 @@ static int atl1e_init_netdev(struct net_device *netdev, struct pci_dev *pdev) · 756 unmodified lines | |||
| 2200 | atl1e_set_ethtool_ops(netdev); | 2198 | atl1e_set_ethtool_ops(netdev); |
| 2201 | 2199 | ||
| 2202 | netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO | | 2200 | netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO | |
| 2203 | NETIF_F_HW_VLAN_RX; | 2201 | NETIF_F_HW_VLAN_CTAG_RX; |
| 2204 | netdev->features = netdev->hw_features | NETIF_F_LLTX | | 2202 | netdev->features = netdev->hw_features | NETIF_F_LLTX | |
| 2205 | NETIF_F_HW_VLAN_TX; | 2203 | NETIF_F_HW_VLAN_CTAG_TX; |
| 2206 | 2204 | ||
| 2207 | return 0; | 2205 | return 0; |
| 2208 | } | 2206 | } |
| @@ -2024,7 +2024,7 @@ rrd_ok: · 2023 unmodified lines | |||
| 2024 | ((rrd->vlan_tag & 7) << 13) | | 2024 | ((rrd->vlan_tag & 7) << 13) | |
| 2025 | ((rrd->vlan_tag & 8) << 9); | 2025 | ((rrd->vlan_tag & 8) << 9); |
| 2026 | 2026 | ||
| 2027 | __vlan_hwaccel_put_tag(skb, vlan_tag); | 2027 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); |
| 2028 | } | 2028 | } |
| 2029 | netif_receive_skb(skb); | 2029 | netif_receive_skb(skb); |
| 2030 | 2030 | ||
| @@ -2774,7 +2774,7 @@ static int atl1_close(struct net_device *netdev) · 743 unmodified lines | |||
| 2774 | return 0; | 2774 | return 0; |
| 2775 | } | 2775 | } |
| 2776 | 2776 | ||
| 2777 | #ifdef CONFIG_PM | 2777 | #ifdef CONFIG_PM_SLEEP |
| 2778 | static int atl1_suspend(struct device *dev) | 2778 | static int atl1_suspend(struct device *dev) |
| 2779 | { | 2779 | { |
| 2780 | struct pci_dev *pdev = to_pci_dev(dev); | 2780 | struct pci_dev *pdev = to_pci_dev(dev); |
| @@ -2876,23 +2876,18 @@ static int atl1_resume(struct device *dev) · 95 unmodified lines | |||
| 2876 | 2876 | ||
| 2877 | return 0; | 2877 | return 0; |
| 2878 | } | 2878 | } |
| 2879 | #endif | ||
| 2879 | 2880 | ||
| 2880 | static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume); | 2881 | static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume); |
| 2881 | #define ATL1_PM_OPS (&atl1_pm_ops) | ||
| 2882 | |||
| 2883 | #else | ||
| 2884 | |||
| 2885 | static int atl1_suspend(struct device *dev) { return 0; } | ||
| 2886 | |||
| 2887 | #define ATL1_PM_OPS NULL | ||
| 2888 | #endif | ||
| 2889 | 2882 | ||
| 2890 | static void atl1_shutdown(struct pci_dev *pdev) | 2883 | static void atl1_shutdown(struct pci_dev *pdev) |
| 2891 | { | 2884 | { |
| 2892 | struct net_device *netdev = pci_get_drvdata(pdev); | 2885 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 2893 | struct atl1_adapter *adapter = netdev_priv(netdev); | 2886 | struct atl1_adapter *adapter = netdev_priv(netdev); |
| 2894 | 2887 | ||
| 2888 | #ifdef CONFIG_PM_SLEEP | ||
| 2895 | atl1_suspend(&pdev->dev); | 2889 | atl1_suspend(&pdev->dev); |
| 2890 | #endif | ||
| 2896 | pci_wake_from_d3(pdev, adapter->wol); | 2891 | pci_wake_from_d3(pdev, adapter->wol); |
| 2897 | pci_set_power_state(pdev, PCI_D3hot); | 2892 | pci_set_power_state(pdev, PCI_D3hot); |
| 2898 | } | 2893 | } |
| @@ -3023,10 +3018,10 @@ static int atl1_probe(struct pci_dev *pdev, const struct pci_device_id *ent) · 124 unmodified lines | |||
| 3023 | 3018 | ||
| 3024 | netdev->features = NETIF_F_HW_CSUM; | 3019 | netdev->features = NETIF_F_HW_CSUM; |
| 3025 | netdev->features |= NETIF_F_SG; | 3020 | netdev->features |= NETIF_F_SG; |
| 3026 | netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); | 3021 | netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); |
| 3027 | 3022 | ||
| 3028 | netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO | | 3023 | netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO | |
| 3029 | NETIF_F_HW_VLAN_RX; | 3024 | NETIF_F_HW_VLAN_CTAG_RX; |
| 3030 | 3025 | ||
| 3031 | /* is this valid? see atl1_setup_mac_ctrl() */ | 3026 | /* is this valid? see atl1_setup_mac_ctrl() */ |
| 3032 | netdev->features |= NETIF_F_RXCSUM; | 3027 | netdev->features |= NETIF_F_RXCSUM; |
| @@ -3147,7 +3142,7 @@ static struct pci_driver atl1_driver = { · 114 unmodified lines | |||
| 3147 | .probe = atl1_probe, | 3142 | .probe = atl1_probe, |
| 3148 | .remove = atl1_remove, | 3143 | .remove = atl1_remove, |
| 3149 | .shutdown = atl1_shutdown, | 3144 | .shutdown = atl1_shutdown, |
| 3150 | .driver.pm = ATL1_PM_OPS, | 3145 | .driver.pm = &atl1_pm_ops, |
| 3151 | }; | 3146 | }; |
| 3152 | 3147 | ||
| 3153 | /** | 3148 | /** |
| @@ -363,7 +363,7 @@ static inline void atl2_irq_disable(struct atl2_adapter *adapter) · 362 unmodified lines | |||
| 363 | 363 | ||
| 364 | static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl) | 364 | static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl) |
| 365 | { | 365 | { |
| 366 | if (features & NETIF_F_HW_VLAN_RX) { | 366 | if (features & NETIF_F_HW_VLAN_CTAG_RX) { |
| 367 | /* enable VLAN tag insert/strip */ | 367 | /* enable VLAN tag insert/strip */ |
| 368 | *ctrl |= MAC_CTRL_RMV_VLAN; | 368 | *ctrl |= MAC_CTRL_RMV_VLAN; |
| 369 | } else { | 369 | } else { |
| @@ -399,10 +399,10 @@ static netdev_features_t atl2_fix_features(struct net_device *netdev, · 29 unmodified lines | |||
| 399 | * Since there is no support for separate rx/tx vlan accel | 399 | * Since there is no support for separate rx/tx vlan accel |
| 400 | * enable/disable make sure tx flag is always in same state as rx. | 400 | * enable/disable make sure tx flag is always in same state as rx. |
| 401 | */ | 401 | */ |
| 402 | if (features & NETIF_F_HW_VLAN_RX) | 402 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 403 | features |= NETIF_F_HW_VLAN_TX; | 403 | features |= NETIF_F_HW_VLAN_CTAG_TX; |
| 404 | else | 404 | else |
| 405 | features &= ~NETIF_F_HW_VLAN_TX; | 405 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 406 | 406 | ||
| 407 | return features; | 407 | return features; |
| 408 | } | 408 | } |
| @@ -412,7 +412,7 @@ static int atl2_set_features(struct net_device *netdev, · 3 unmodified lines | |||
| 412 | { | 412 | { |
| 413 | netdev_features_t changed = netdev->features ^ features; | 413 | netdev_features_t changed = netdev->features ^ features; |
| 414 | 414 | ||
| 415 | if (changed & NETIF_F_HW_VLAN_RX) | 415 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
| 416 | atl2_vlan_mode(netdev, features); | 416 | atl2_vlan_mode(netdev, features); |
| 417 | 417 | ||
| 418 | return 0; | 418 | return 0; |
| @@ -437,9 +437,6 @@ static void atl2_intr_rx(struct atl2_adapter *adapter) · 18 unmodified lines | |||
| 437 | /* alloc new buffer */ | 437 | /* alloc new buffer */ |
| 438 | skb = netdev_alloc_skb_ip_align(netdev, rx_size); | 438 | skb = netdev_alloc_skb_ip_align(netdev, rx_size); |
| 439 | if (NULL == skb) { | 439 | if (NULL == skb) { |
| 440 | printk(KERN_WARNING | ||
| 441 | "%s: Mem squeeze, deferring packet.\n", | ||
| 442 | netdev->name); | ||
| 443 | /* | 440 | /* |
| 444 | * Check that some rx space is free. If not, | 441 | * Check that some rx space is free. If not, |
| 445 | * free one and mark stats->rx_dropped++. | 442 | * free one and mark stats->rx_dropped++. |
| @@ -455,7 +452,7 @@ static void atl2_intr_rx(struct atl2_adapter *adapter) · 9 unmodified lines | |||
| 455 | ((rxd->status.vtag&7) << 13) | | 452 | ((rxd->status.vtag&7) << 13) | |
| 456 | ((rxd->status.vtag&8) << 9); | 453 | ((rxd->status.vtag&8) << 9); |
| 457 | 454 | ||
| 458 | __vlan_hwaccel_put_tag(skb, vlan_tag); | 455 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); |
| 459 | } | 456 | } |
| 460 | netif_rx(skb); | 457 | netif_rx(skb); |
| 461 | netdev->stats.rx_bytes += rx_size; | 458 | netdev->stats.rx_bytes += rx_size; |
| @@ -890,7 +887,7 @@ static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb, · 428 unmodified lines | |||
| 890 | skb->len-copy_len); | 887 | skb->len-copy_len); |
| 891 | offset = ((u32)(skb->len-copy_len + 3) & ~3); | 888 | offset = ((u32)(skb->len-copy_len + 3) & ~3); |
| 892 | } | 889 | } |
| 893 | #ifdef NETIF_F_HW_VLAN_TX | 890 | #ifdef NETIF_F_HW_VLAN_CTAG_TX |
| 894 | if (vlan_tx_tag_present(skb)) { | 891 | if (vlan_tx_tag_present(skb)) { |
| 895 | u16 vlan_tag = vlan_tx_tag_get(skb); | 892 | u16 vlan_tag = vlan_tx_tag_get(skb); |
| 896 | vlan_tag = (vlan_tag << 4) | | 893 | vlan_tag = (vlan_tag << 4) | |
| @@ -1416,8 +1413,8 @@ static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) · 519 unmodified lines | |||
| 1416 | 1413 | ||
| 1417 | err = -EIO; | 1414 | err = -EIO; |
| 1418 | 1415 | ||
| 1419 | netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_RX; | 1416 | netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX; |
| 1420 | netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); | 1417 | netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); |
| 1421 | 1418 | ||
| 1422 | /* Init PHY as early as possible due to power saving issue */ | 1419 | /* Init PHY as early as possible due to power saving issue */ |
| 1423 | atl2_phy_init(&adapter->hw); | 1420 | atl2_phy_init(&adapter->hw); |
| @@ -220,7 +220,7 @@ static void atlx_link_chg_task(struct work_struct *work) · 219 unmodified lines | |||
| 220 | 220 | ||
| 221 | static void __atlx_vlan_mode(netdev_features_t features, u32 *ctrl) | 221 | static void __atlx_vlan_mode(netdev_features_t features, u32 *ctrl) |
| 222 | { | 222 | { |
| 223 | if (features & NETIF_F_HW_VLAN_RX) { | 223 | if (features & NETIF_F_HW_VLAN_CTAG_RX) { |
| 224 | /* enable VLAN tag insert/strip */ | 224 | /* enable VLAN tag insert/strip */ |
| 225 | *ctrl |= MAC_CTRL_RMV_VLAN; | 225 | *ctrl |= MAC_CTRL_RMV_VLAN; |
| 226 | } else { | 226 | } else { |
| @@ -257,10 +257,10 @@ static netdev_features_t atlx_fix_features(struct net_device *netdev, · 30 unmodified lines | |||
| 257 | * Since there is no support for separate rx/tx vlan accel | 257 | * Since there is no support for separate rx/tx vlan accel |
| 258 | * enable/disable make sure tx flag is always in same state as rx. | 258 | * enable/disable make sure tx flag is always in same state as rx. |
| 259 | */ | 259 | */ |
| 260 | if (features & NETIF_F_HW_VLAN_RX) | 260 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 261 | features |= NETIF_F_HW_VLAN_TX; | 261 | features |= NETIF_F_HW_VLAN_CTAG_TX; |
| 262 | else | 262 | else |
| 263 | features &= ~NETIF_F_HW_VLAN_TX; | 263 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 264 | 264 | ||
| 265 | return features; | 265 | return features; |
| 266 | } | 266 | } |
| @@ -270,7 +270,7 @@ static int atlx_set_features(struct net_device *netdev, · 3 unmodified lines | |||
| 270 | { | 270 | { |
| 271 | netdev_features_t changed = netdev->features ^ features; | 271 | netdev_features_t changed = netdev->features ^ features; |
| 272 | 272 | ||
| 273 | if (changed & NETIF_F_HW_VLAN_RX) | 273 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
| 274 | atlx_vlan_mode(netdev, features); | 274 | atlx_vlan_mode(netdev, features); |
| 275 | 275 | ||
| 276 | return 0; | 276 | return 0; |
| @@ -862,27 +862,25 @@ static int bcm_enet_open(struct net_device *dev) · 861 unmodified lines | |||
| 862 | 862 | ||
| 863 | /* allocate rx dma ring */ | 863 | /* allocate rx dma ring */ |
| 864 | size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); | 864 | size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); |
| 865 | p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL); | 865 | p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, |
| 866 | GFP_KERNEL | __GFP_ZERO); | ||
| 866 | if (!p) { | 867 | if (!p) { |
| 867 | dev_err(kdev, "cannot allocate rx ring %u\n", size); | ||
| 868 | ret = -ENOMEM; | 868 | ret = -ENOMEM; |
| 869 | goto out_freeirq_tx; | 869 | goto out_freeirq_tx; |
| 870 | } | 870 | } |
| 871 | 871 | ||
| 872 | memset(p, 0, size); | ||
| 873 | priv->rx_desc_alloc_size = size; | 872 | priv->rx_desc_alloc_size = size; |
| 874 | priv->rx_desc_cpu = p; | 873 | priv->rx_desc_cpu = p; |
| 875 | 874 | ||
| 876 | /* allocate tx dma ring */ | 875 | /* allocate tx dma ring */ |
| 877 | size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); | 876 | size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); |
| 878 | p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL); | 877 | p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, |
| 878 | GFP_KERNEL | __GFP_ZERO); | ||
| 879 | if (!p) { | 879 | if (!p) { |
| 880 | dev_err(kdev, "cannot allocate tx ring\n"); | ||
| 881 | ret = -ENOMEM; | 880 | ret = -ENOMEM; |
| 882 | goto out_free_rx_ring; | 881 | goto out_free_rx_ring; |
| 883 | } | 882 | } |
| 884 | 883 | ||
| 885 | memset(p, 0, size); | ||
| 886 | priv->tx_desc_alloc_size = size; | 884 | priv->tx_desc_alloc_size = size; |
| 887 | priv->tx_desc_cpu = p; | 885 | priv->tx_desc_cpu = p; |
| 888 | 886 | ||
| @@ -1619,7 +1617,6 @@ static int bcm_enet_probe(struct platform_device *pdev) · 730 unmodified lines | |||
| 1619 | struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx; | 1617 | struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx; |
| 1620 | struct mii_bus *bus; | 1618 | struct mii_bus *bus; |
| 1621 | const char *clk_name; | 1619 | const char *clk_name; |
| 1622 | unsigned int iomem_size; | ||
| 1623 | int i, ret; | 1620 | int i, ret; |
| 1624 | 1621 | ||
| 1625 | /* stop if shared driver failed, assume driver->probe will be | 1622 | /* stop if shared driver failed, assume driver->probe will be |
| @@ -1644,17 +1641,12 @@ static int bcm_enet_probe(struct platform_device *pdev) · 18 unmodified lines | |||
| 1644 | if (ret) | 1641 | if (ret) |
| 1645 | goto out; | 1642 | goto out; |
| 1646 | 1643 | ||
| 1647 | iomem_size = resource_size(res_mem); | 1644 | priv->base = devm_request_and_ioremap(&pdev->dev, res_mem); |
| 1648 | if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) { | ||
| 1649 | ret = -EBUSY; | ||
| 1650 | goto out; | ||
| 1651 | } | ||
| 1652 | |||
| 1653 | priv->base = ioremap(res_mem->start, iomem_size); | ||
| 1654 | if (priv->base == NULL) { | 1645 | if (priv->base == NULL) { |
| 1655 | ret = -ENOMEM; | 1646 | ret = -ENOMEM; |
| 1656 | goto out_release_mem; | 1647 | goto out; |
| 1657 | } | 1648 | } |
| 1649 | |||
| 1658 | dev->irq = priv->irq = res_irq->start; | 1650 | dev->irq = priv->irq = res_irq->start; |
| 1659 | priv->irq_rx = res_irq_rx->start; | 1651 | priv->irq_rx = res_irq_rx->start; |
| 1660 | priv->irq_tx = res_irq_tx->start; | 1652 | priv->irq_tx = res_irq_tx->start; |
| @@ -1674,9 +1666,9 @@ static int bcm_enet_probe(struct platform_device *pdev) · 13 unmodified lines | |||
| 1674 | priv->mac_clk = clk_get(&pdev->dev, clk_name); | 1666 | priv->mac_clk = clk_get(&pdev->dev, clk_name); |
| 1675 | if (IS_ERR(priv->mac_clk)) { | 1667 | if (IS_ERR(priv->mac_clk)) { |
| 1676 | ret = PTR_ERR(priv->mac_clk); | 1668 | ret = PTR_ERR(priv->mac_clk); |
| 1677 | goto out_unmap; | 1669 | goto out; |
| 1678 | } | 1670 | } |
| 1679 | clk_enable(priv->mac_clk); | 1671 | clk_prepare_enable(priv->mac_clk); |
| 1680 | 1672 | ||
| 1681 | /* initialize default and fetch platform data */ | 1673 | /* initialize default and fetch platform data */ |
| 1682 | priv->rx_ring_size = BCMENET_DEF_RX_DESC; | 1674 | priv->rx_ring_size = BCMENET_DEF_RX_DESC; |
| @@ -1705,7 +1697,7 @@ static int bcm_enet_probe(struct platform_device *pdev) · 22 unmodified lines | |||
| 1705 | priv->phy_clk = NULL; | 1697 | priv->phy_clk = NULL; |
| 1706 | goto out_put_clk_mac; | 1698 | goto out_put_clk_mac; |
| 1707 | } | 1699 | } |
| 1708 | clk_enable(priv->phy_clk); | 1700 | clk_prepare_enable(priv->phy_clk); |
| 1709 | } | 1701 | } |
| 1710 | 1702 | ||
| 1711 | /* do minimal hardware init to be able to probe mii bus */ | 1703 | /* do minimal hardware init to be able to probe mii bus */ |
| @@ -1733,7 +1725,8 @@ static int bcm_enet_probe(struct platform_device *pdev) · 21 unmodified lines | |||
| 1733 | * if a slave is not present on hw */ | 1725 | * if a slave is not present on hw */ |
| 1734 | bus->phy_mask = ~(1 << priv->phy_id); | 1726 | bus->phy_mask = ~(1 << priv->phy_id); |
| 1735 | 1727 | ||
| 1736 | bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | 1728 | bus->irq = devm_kzalloc(&pdev->dev, sizeof(int) * PHY_MAX_ADDR, |
| 1729 | GFP_KERNEL); | ||
| 1737 | if (!bus->irq) { | 1730 | if (!bus->irq) { |
| 1738 | ret = -ENOMEM; | 1731 | ret = -ENOMEM; |
| 1739 | goto out_free_mdio; | 1732 | goto out_free_mdio; |
| @@ -1794,10 +1787,8 @@ static int bcm_enet_probe(struct platform_device *pdev) · 54 unmodified lines | |||
| 1794 | return 0; | 1787 | return 0; |
| 1795 | 1788 | ||
| 1796 | out_unregister_mdio: | 1789 | out_unregister_mdio: |
| 1797 | if (priv->mii_bus) { | 1790 | if (priv->mii_bus) |
| 1798 | mdiobus_unregister(priv->mii_bus); | 1791 | mdiobus_unregister(priv->mii_bus); |
| 1799 | kfree(priv->mii_bus->irq); | ||
| 1800 | } | ||
| 1801 | 1792 | ||
| 1802 | out_free_mdio: | 1793 | out_free_mdio: |
| 1803 | if (priv->mii_bus) | 1794 | if (priv->mii_bus) |
| @@ -1807,19 +1798,13 @@ out_uninit_hw: · 3 unmodified lines | |||
| 1807 | /* turn off mdc clock */ | 1798 | /* turn off mdc clock */ |
| 1808 | enet_writel(priv, 0, ENET_MIISC_REG); | 1799 | enet_writel(priv, 0, ENET_MIISC_REG); |
| 1809 | if (priv->phy_clk) { | 1800 | if (priv->phy_clk) { |
| 1810 | clk_disable(priv->phy_clk); | 1801 | clk_disable_unprepare(priv->phy_clk); |
| 1811 | clk_put(priv->phy_clk); | 1802 | clk_put(priv->phy_clk); |
| 1812 | } | 1803 | } |
| 1813 | 1804 | ||
| 1814 | out_put_clk_mac: | 1805 | out_put_clk_mac: |
| 1815 | clk_disable(priv->mac_clk); | 1806 | clk_disable_unprepare(priv->mac_clk); |
| 1816 | clk_put(priv->mac_clk); | 1807 | clk_put(priv->mac_clk); |
| 1817 | |||
| 1818 | out_unmap: | ||
| 1819 | iounmap(priv->base); | ||
| 1820 | |||
| 1821 | out_release_mem: | ||
| 1822 | release_mem_region(res_mem->start, iomem_size); | ||
| 1823 | out: | 1808 | out: |
| 1824 | free_netdev(dev); | 1809 | free_netdev(dev); |
| 1825 | return ret; | 1810 | return ret; |
| @@ -1833,7 +1818,6 @@ static int bcm_enet_remove(struct platform_device *pdev) · 7 unmodified lines | |||
| 1833 | { | 1818 | { |
| 1834 | struct bcm_enet_priv *priv; | 1819 | struct bcm_enet_priv *priv; |
| 1835 | struct net_device *dev; | 1820 | struct net_device *dev; |
| 1836 | struct resource *res; | ||
| 1837 | 1821 | ||
| 1838 | /* stop netdevice */ | 1822 | /* stop netdevice */ |
| 1839 | dev = platform_get_drvdata(pdev); | 1823 | dev = platform_get_drvdata(pdev); |
| @@ -1845,7 +1829,6 @@ static int bcm_enet_remove(struct platform_device *pdev) · 5 unmodified lines | |||
| 1845 | 1829 | ||
| 1846 | if (priv->has_phy) { | 1830 | if (priv->has_phy) { |
| 1847 | mdiobus_unregister(priv->mii_bus); | 1831 | mdiobus_unregister(priv->mii_bus); |
| 1848 | kfree(priv->mii_bus->irq); | ||
| 1849 | mdiobus_free(priv->mii_bus); | 1832 | mdiobus_free(priv->mii_bus); |
| 1850 | } else { | 1833 | } else { |
| 1851 | struct bcm63xx_enet_platform_data *pd; | 1834 | struct bcm63xx_enet_platform_data *pd; |
| @@ -1856,17 +1839,12 @@ static int bcm_enet_remove(struct platform_device *pdev) · 4 unmodified lines | |||
| 1856 | bcm_enet_mdio_write_mii); | 1839 | bcm_enet_mdio_write_mii); |
| 1857 | } | 1840 | } |
| 1858 | 1841 | ||
| 1859 | /* release device resources */ | ||
| 1860 | iounmap(priv->base); | ||
| 1861 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 1862 | release_mem_region(res->start, resource_size(res)); | ||
| 1863 | |||
| 1864 | /* disable hw block clocks */ | 1842 | /* disable hw block clocks */ |
| 1865 | if (priv->phy_clk) { | 1843 | if (priv->phy_clk) { |
| 1866 | clk_disable(priv->phy_clk); | 1844 | clk_disable_unprepare(priv->phy_clk); |
| 1867 | clk_put(priv->phy_clk); | 1845 | clk_put(priv->phy_clk); |
| 1868 | } | 1846 | } |
| 1869 | clk_disable(priv->mac_clk); | 1847 | clk_disable_unprepare(priv->mac_clk); |
| 1870 | clk_put(priv->mac_clk); | 1848 | clk_put(priv->mac_clk); |
| 1871 | 1849 | ||
| 1872 | platform_set_drvdata(pdev, NULL); | 1850 | platform_set_drvdata(pdev, NULL); |
| @@ -1889,31 +1867,20 @@ struct platform_driver bcm63xx_enet_driver = { · 16 unmodified lines | |||
| 1889 | static int bcm_enet_shared_probe(struct platform_device *pdev) | 1867 | static int bcm_enet_shared_probe(struct platform_device *pdev) |
| 1890 | { | 1868 | { |
| 1891 | struct resource *res; | 1869 | struct resource *res; |
| 1892 | unsigned int iomem_size; | ||
| 1893 | 1870 | ||
| 1894 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1871 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1895 | if (!res) | 1872 | if (!res) |
| 1896 | return -ENODEV; | 1873 | return -ENODEV; |
| 1897 | 1874 | ||
| 1898 | iomem_size = resource_size(res); | 1875 | bcm_enet_shared_base = devm_request_and_ioremap(&pdev->dev, res); |
| 1899 | if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma")) | 1876 | if (!bcm_enet_shared_base) |
| 1900 | return -EBUSY; | ||
| 1901 | |||
| 1902 | bcm_enet_shared_base = ioremap(res->start, iomem_size); | ||
| 1903 | if (!bcm_enet_shared_base) { | ||
| 1904 | release_mem_region(res->start, iomem_size); | ||
| 1905 | return -ENOMEM; | 1877 | return -ENOMEM; |
| 1906 | } | 1878 | |
| 1907 | return 0; | 1879 | return 0; |
| 1908 | } | 1880 | } |
| 1909 | 1881 | ||
| 1910 | static int bcm_enet_shared_remove(struct platform_device *pdev) | 1882 | static int bcm_enet_shared_remove(struct platform_device *pdev) |
| 1911 | { | 1883 | { |
| 1912 | struct resource *res; | ||
| 1913 | |||
| 1914 | iounmap(bcm_enet_shared_base); | ||
| 1915 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 1916 | release_mem_region(res->start, resource_size(res)); | ||
| 1917 | return 0; | 1884 | return 0; |
| 1918 | } | 1885 | } |
| 1919 | 1886 | ||
| @@ -13,6 +13,7 @@ · 12 unmodified lines | |||
| 13 | #include <linux/delay.h> | 13 | #include <linux/delay.h> |
| 14 | #include <linux/etherdevice.h> | 14 | #include <linux/etherdevice.h> |
| 15 | #include <linux/mii.h> | 15 | #include <linux/mii.h> |
| 16 | #include <linux/phy.h> | ||
| 16 | #include <linux/interrupt.h> | 17 | #include <linux/interrupt.h> |
| 17 | #include <linux/dma-mapping.h> | 18 | #include <linux/dma-mapping.h> |
| 18 | #include <bcm47xx_nvram.h> | 19 | #include <bcm47xx_nvram.h> |
| @@ -244,10 +245,8 @@ static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, · 225 unmodified lines | |||
| 244 | 245 | ||
| 245 | /* Alloc skb */ | 246 | /* Alloc skb */ |
| 246 | slot->skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE); | 247 | slot->skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE); |
| 247 | if (!slot->skb) { | 248 | if (!slot->skb) |
| 248 | bgmac_err(bgmac, "Allocation of skb failed!\n"); | ||
| 249 | return -ENOMEM; | 249 | return -ENOMEM; |
| 250 | } | ||
| 251 | 250 | ||
| 252 | /* Poison - if everything goes fine, hardware will overwrite it */ | 251 | /* Poison - if everything goes fine, hardware will overwrite it */ |
| 253 | rx = (struct bgmac_rx_header *)slot->skb->data; | 252 | rx = (struct bgmac_rx_header *)slot->skb->data; |
| @@ -1312,6 +1311,73 @@ static const struct ethtool_ops bgmac_ethtool_ops = { · 1058 unmodified lines | |||
| 1312 | .get_drvinfo = bgmac_get_drvinfo, | 1311 | .get_drvinfo = bgmac_get_drvinfo, |
| 1313 | }; | 1312 | }; |
| 1314 | 1313 | ||
| 1314 | /************************************************** | ||
| 1315 | * MII | ||
| 1316 | **************************************************/ | ||
| 1317 | |||
| 1318 | static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum) | ||
| 1319 | { | ||
| 1320 | return bgmac_phy_read(bus->priv, mii_id, regnum); | ||
| 1321 | } | ||
| 1322 | |||
| 1323 | static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum, | ||
| 1324 | u16 value) | ||
| 1325 | { | ||
| 1326 | return bgmac_phy_write(bus->priv, mii_id, regnum, value); | ||
| 1327 | } | ||
| 1328 | |||
| 1329 | static int bgmac_mii_register(struct bgmac *bgmac) | ||
| 1330 | { | ||
| 1331 | struct mii_bus *mii_bus; | ||
| 1332 | int i, err = 0; | ||
| 1333 | |||
| 1334 | mii_bus = mdiobus_alloc(); | ||
| 1335 | if (!mii_bus) | ||
| 1336 | return -ENOMEM; | ||
| 1337 | |||
| 1338 | mii_bus->name = "bgmac mii bus"; | ||
| 1339 | sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num, | ||
| 1340 | bgmac->core->core_unit); | ||
| 1341 | mii_bus->priv = bgmac; | ||
| 1342 | mii_bus->read = bgmac_mii_read; | ||
| 1343 | mii_bus->write = bgmac_mii_write; | ||
| 1344 | mii_bus->parent = &bgmac->core->dev; | ||
| 1345 | mii_bus->phy_mask = ~(1 << bgmac->phyaddr); | ||
| 1346 | |||
| 1347 | mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); | ||
| 1348 | if (!mii_bus->irq) { | ||
| 1349 | err = -ENOMEM; | ||
| 1350 | goto err_free_bus; | ||
| 1351 | } | ||
| 1352 | for (i = 0; i < PHY_MAX_ADDR; i++) | ||
| 1353 | mii_bus->irq[i] = PHY_POLL; | ||
| 1354 | |||
| 1355 | err = mdiobus_register(mii_bus); | ||
| 1356 | if (err) { | ||
| 1357 | bgmac_err(bgmac, "Registration of mii bus failed\n"); | ||
| 1358 | goto err_free_irq; | ||
| 1359 | } | ||
| 1360 | |||
| 1361 | bgmac->mii_bus = mii_bus; | ||
| 1362 | |||
| 1363 | return err; | ||
| 1364 | |||
| 1365 | err_free_irq: | ||
| 1366 | kfree(mii_bus->irq); | ||
| 1367 | err_free_bus: | ||
| 1368 | mdiobus_free(mii_bus); | ||
| 1369 | return err; | ||
| 1370 | } | ||
| 1371 | |||
| 1372 | static void bgmac_mii_unregister(struct bgmac *bgmac) | ||
| 1373 | { | ||
| 1374 | struct mii_bus *mii_bus = bgmac->mii_bus; | ||
| 1375 | |||
| 1376 | mdiobus_unregister(mii_bus); | ||
| 1377 | kfree(mii_bus->irq); | ||
| 1378 | mdiobus_free(mii_bus); | ||
| 1379 | } | ||
| 1380 | |||
| 1315 | /************************************************** | 1381 | /************************************************** |
| 1316 | * BCMA bus ops | 1382 | * BCMA bus ops |
| 1317 | **************************************************/ | 1383 | **************************************************/ |
| @@ -1404,11 +1470,18 @@ static int bgmac_probe(struct bcma_device *core) · 86 unmodified lines | |||
| 1404 | if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) | 1470 | if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) |
| 1405 | bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); | 1471 | bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); |
| 1406 | 1472 | ||
| 1473 | err = bgmac_mii_register(bgmac); | ||
| 1474 | if (err) { | ||
| 1475 | bgmac_err(bgmac, "Cannot register MDIO\n"); | ||
| 1476 | err = -ENOTSUPP; | ||
| 1477 | goto err_dma_free; | ||
| 1478 | } | ||
| 1479 | |||
| 1407 | err = register_netdev(bgmac->net_dev); | 1480 | err = register_netdev(bgmac->net_dev); |
| 1408 | if (err) { | 1481 | if (err) { |
| 1409 | bgmac_err(bgmac, "Cannot register net device\n"); | 1482 | bgmac_err(bgmac, "Cannot register net device\n"); |
| 1410 | err = -ENOTSUPP; | 1483 | err = -ENOTSUPP; |
| 1411 | goto err_dma_free; | 1484 | goto err_mii_unregister; |
| 1412 | } | 1485 | } |
| 1413 | 1486 | ||
| 1414 | netif_carrier_off(net_dev); | 1487 | netif_carrier_off(net_dev); |
| @@ -1417,6 +1490,8 @@ static int bgmac_probe(struct bcma_device *core) · 2 unmodified lines | |||
| 1417 | 1490 | ||
| 1418 | return 0; | 1491 | return 0; |
| 1419 | 1492 | ||
| 1493 | err_mii_unregister: | ||
| 1494 | bgmac_mii_unregister(bgmac); | ||
| 1420 | err_dma_free: | 1495 | err_dma_free: |
| 1421 | bgmac_dma_free(bgmac); | 1496 | bgmac_dma_free(bgmac); |
| 1422 | 1497 | ||
| @@ -1433,6 +1508,7 @@ static void bgmac_remove(struct bcma_device *core) · 10 unmodified lines | |||
| 1433 | 1508 | ||
| 1434 | netif_napi_del(&bgmac->napi); | 1509 | netif_napi_del(&bgmac->napi); |
| 1435 | unregister_netdev(bgmac->net_dev); | 1510 | unregister_netdev(bgmac->net_dev); |
| 1511 | bgmac_mii_unregister(bgmac); | ||
| 1436 | bgmac_dma_free(bgmac); | 1512 | bgmac_dma_free(bgmac); |
| 1437 | bcma_set_drvdata(core, NULL); | 1513 | bcma_set_drvdata(core, NULL); |
| 1438 | free_netdev(bgmac->net_dev); | 1514 | free_netdev(bgmac->net_dev); |
| @@ -399,6 +399,7 @@ struct bgmac { · 398 unmodified lines | |||
| 399 | struct bcma_device *cmn; /* Reference to CMN core for BCM4706 */ | 399 | struct bcma_device *cmn; /* Reference to CMN core for BCM4706 */ |
| 400 | struct net_device *net_dev; | 400 | struct net_device *net_dev; |
| 401 | struct napi_struct napi; | 401 | struct napi_struct napi; |
| 402 | struct mii_bus *mii_bus; | ||
| 402 | 403 | ||
| 403 | /* DMA */ | 404 | /* DMA */ |
| 404 | struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS]; | 405 | struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS]; |
| @@ -416,7 +416,7 @@ static int bnx2_unregister_cnic(struct net_device *dev) · 415 unmodified lines | |||
| 416 | return 0; | 416 | return 0; |
| 417 | } | 417 | } |
| 418 | 418 | ||
| 419 | struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) | 419 | static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) |
| 420 | { | 420 | { |
| 421 | struct bnx2 *bp = netdev_priv(dev); | 421 | struct bnx2 *bp = netdev_priv(dev); |
| 422 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | 422 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
| @@ -854,12 +854,11 @@ bnx2_alloc_mem(struct bnx2 *bp) · 431 unmodified lines | |||
| 854 | sizeof(struct statistics_block); | 854 | sizeof(struct statistics_block); |
| 855 | 855 | ||
| 856 | status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size, | 856 | status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size, |
| 857 | &bp->status_blk_mapping, GFP_KERNEL); | 857 | &bp->status_blk_mapping, |
| 858 | GFP_KERNEL | __GFP_ZERO); | ||
| 858 | if (status_blk == NULL) | 859 | if (status_blk == NULL) |
| 859 | goto alloc_mem_err; | 860 | goto alloc_mem_err; |
| 860 | 861 | ||
| 861 | memset(status_blk, 0, bp->status_stats_size); | ||
| 862 | |||
| 863 | bnapi = &bp->bnx2_napi[0]; | 862 | bnapi = &bp->bnx2_napi[0]; |
| 864 | bnapi->status_blk.msi = status_blk; | 863 | bnapi->status_blk.msi = status_blk; |
| 865 | bnapi->hw_tx_cons_ptr = | 864 | bnapi->hw_tx_cons_ptr = |
| @@ -3212,7 +3211,7 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) · 2346 unmodified lines | |||
| 3212 | } | 3211 | } |
| 3213 | if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && | 3212 | if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && |
| 3214 | !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) | 3213 | !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) |
| 3215 | __vlan_hwaccel_put_tag(skb, rx_hdr->l2_fhdr_vlan_tag); | 3214 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag); |
| 3216 | 3215 | ||
| 3217 | skb->protocol = eth_type_trans(skb, bp->dev); | 3216 | skb->protocol = eth_type_trans(skb, bp->dev); |
| 3218 | 3217 | ||
| @@ -3554,7 +3553,7 @@ bnx2_set_rx_mode(struct net_device *dev) · 335 unmodified lines | |||
| 3554 | rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | | 3553 | rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | |
| 3555 | BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); | 3554 | BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); |
| 3556 | sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; | 3555 | sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; |
| 3557 | if (!(dev->features & NETIF_F_HW_VLAN_RX) && | 3556 | if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
| 3558 | (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) | 3557 | (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) |
| 3559 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; | 3558 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; |
| 3560 | if (dev->flags & IFF_PROMISC) { | 3559 | if (dev->flags & IFF_PROMISC) { |
| @@ -7696,7 +7695,7 @@ bnx2_fix_features(struct net_device *dev, netdev_features_t features) · 4135 unmodified lines | |||
| 7696 | struct bnx2 *bp = netdev_priv(dev); | 7695 | struct bnx2 *bp = netdev_priv(dev); |
| 7697 | 7696 | ||
| 7698 | if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) | 7697 | if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) |
| 7699 | features |= NETIF_F_HW_VLAN_RX; | 7698 | features |= NETIF_F_HW_VLAN_CTAG_RX; |
| 7700 | 7699 | ||
| 7701 | return features; | 7700 | return features; |
| 7702 | } | 7701 | } |
| @@ -7707,12 +7706,12 @@ bnx2_set_features(struct net_device *dev, netdev_features_t features) · 4 unmodified lines | |||
| 7707 | struct bnx2 *bp = netdev_priv(dev); | 7706 | struct bnx2 *bp = netdev_priv(dev); |
| 7708 | 7707 | ||
| 7709 | /* TSO with VLAN tag won't work with current firmware */ | 7708 | /* TSO with VLAN tag won't work with current firmware */ |
| 7710 | if (features & NETIF_F_HW_VLAN_TX) | 7709 | if (features & NETIF_F_HW_VLAN_CTAG_TX) |
| 7711 | dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO); | 7710 | dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO); |
| 7712 | else | 7711 | else |
| 7713 | dev->vlan_features &= ~NETIF_F_ALL_TSO; | 7712 | dev->vlan_features &= ~NETIF_F_ALL_TSO; |
| 7714 | 7713 | ||
| 7715 | if ((!!(features & NETIF_F_HW_VLAN_RX) != | 7714 | if ((!!(features & NETIF_F_HW_VLAN_CTAG_RX) != |
| 7716 | !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) && | 7715 | !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) && |
| 7717 | netif_running(dev)) { | 7716 | netif_running(dev)) { |
| 7718 | bnx2_netif_stop(bp, false); | 7717 | bnx2_netif_stop(bp, false); |
| @@ -8552,7 +8551,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 833 unmodified lines | |||
| 8552 | dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | 8551 | dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; |
| 8553 | 8552 | ||
| 8554 | dev->vlan_features = dev->hw_features; | 8553 | dev->vlan_features = dev->hw_features; |
| 8555 | dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | 8554 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
| 8556 | dev->features |= dev->hw_features; | 8555 | dev->features |= dev->hw_features; |
| 8557 | dev->priv_flags |= IFF_UNICAST_FLT; | 8556 | dev->priv_flags |= IFF_UNICAST_FLT; |
| 8558 | 8557 | ||
| @@ -26,8 +26,8 @@ · 25 unmodified lines | |||
| 26 | * (you will need to reboot afterwards) */ | 26 | * (you will need to reboot afterwards) */ |
| 27 | /* #define BNX2X_STOP_ON_ERROR */ | 27 | /* #define BNX2X_STOP_ON_ERROR */ |
| 28 | 28 | ||
| 29 | #define DRV_MODULE_VERSION "1.78.02-0" | 29 | #define DRV_MODULE_VERSION "1.78.17-0" |
| 30 | #define DRV_MODULE_RELDATE "2013/01/14" | 30 | #define DRV_MODULE_RELDATE "2013/04/11" |
| 31 | #define BNX2X_BC_VER 0x040200 | 31 | #define BNX2X_BC_VER 0x040200 |
| 32 | 32 | ||
| 33 | #if defined(CONFIG_DCB) | 33 | #if defined(CONFIG_DCB) |
| @@ -492,7 +492,6 @@ enum bnx2x_tpa_mode_t { · 458 unmodified lines | |||
| 492 | struct bnx2x_fastpath { | 492 | struct bnx2x_fastpath { |
| 493 | struct bnx2x *bp; /* parent */ | 493 | struct bnx2x *bp; /* parent */ |
| 494 | 494 | ||
| 495 | #define BNX2X_NAPI_WEIGHT 128 | ||
| 496 | struct napi_struct napi; | 495 | struct napi_struct napi; |
| 497 | union host_hc_status_block status_blk; | 496 | union host_hc_status_block status_blk; |
| 498 | /* chip independed shortcuts into sb structure */ | 497 | /* chip independed shortcuts into sb structure */ |
| @@ -613,9 +612,10 @@ struct bnx2x_fastpath { · 114 unmodified lines | |||
| 613 | * START_BD - describes packed | 612 | * START_BD - describes packed |
| 614 | * START_BD(splitted) - includes unpaged data segment for GSO | 613 | * START_BD(splitted) - includes unpaged data segment for GSO |
| 615 | * PARSING_BD - for TSO and CSUM data | 614 | * PARSING_BD - for TSO and CSUM data |
| 615 | * PARSING_BD2 - for encapsulation data | ||
| 616 | * Frag BDs - decribes pages for frags | 616 | * Frag BDs - decribes pages for frags |
| 617 | */ | 617 | */ |
| 618 | #define BDS_PER_TX_PKT 3 | 618 | #define BDS_PER_TX_PKT 4 |
| 619 | #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) | 619 | #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) |
| 620 | /* max BDs per tx packet including next pages */ | 620 | /* max BDs per tx packet including next pages */ |
| 621 | #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ | 621 | #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ |
| @@ -730,18 +730,24 @@ struct bnx2x_fastpath { · 108 unmodified lines | |||
| 730 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | 730 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ |
| 731 | skb->csum_offset)) | 731 | skb->csum_offset)) |
| 732 | 732 | ||
| 733 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | 733 | #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) |
| 734 | 734 | ||
| 735 | #define XMIT_PLAIN 0 | 735 | #define XMIT_PLAIN 0 |
| 736 | #define XMIT_CSUM_V4 0x1 | 736 | #define XMIT_CSUM_V4 (1 << 0) |
| 737 | #define XMIT_CSUM_V6 0x2 | 737 | #define XMIT_CSUM_V6 (1 << 1) |
| 738 | #define XMIT_CSUM_TCP 0x4 | 738 | #define XMIT_CSUM_TCP (1 << 2) |
| 739 | #define XMIT_GSO_V4 0x8 | 739 | #define XMIT_GSO_V4 (1 << 3) |
| 740 | #define XMIT_GSO_V6 0x10 | 740 | #define XMIT_GSO_V6 (1 << 4) |
| 741 | #define XMIT_CSUM_ENC_V4 (1 << 5) | ||
| 742 | #define XMIT_CSUM_ENC_V6 (1 << 6) | ||
| 743 | #define XMIT_GSO_ENC_V4 (1 << 7) | ||
| 744 | #define XMIT_GSO_ENC_V6 (1 << 8) | ||
| 741 | 745 | ||
| 742 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) | 746 | #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) |
| 743 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) | 747 | #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) |
| 744 | 748 | ||
| 749 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) | ||
| 750 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) | ||
| 745 | 751 | ||
| 746 | /* stuff added to make the code fit 80Col */ | 752 | /* stuff added to make the code fit 80Col */ |
| 747 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) | 753 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
| @@ -844,6 +850,9 @@ struct bnx2x_common { · 96 unmodified lines | |||
| 844 | #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) | 850 | #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) |
| 845 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ | 851 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ |
| 846 | CHIP_IS_57711E(bp)) | 852 | CHIP_IS_57711E(bp)) |
| 853 | #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ | ||
| 854 | CHIP_IS_57811_MF(bp) || \ | ||
| 855 | CHIP_IS_57811_VF(bp)) | ||
| 847 | #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ | 856 | #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ |
| 848 | CHIP_IS_57712_MF(bp) || \ | 857 | CHIP_IS_57712_MF(bp) || \ |
| 849 | CHIP_IS_57712_VF(bp)) | 858 | CHIP_IS_57712_VF(bp)) |
| @@ -853,9 +862,7 @@ struct bnx2x_common { · 3 unmodified lines | |||
| 853 | CHIP_IS_57810(bp) || \ | 862 | CHIP_IS_57810(bp) || \ |
| 854 | CHIP_IS_57810_MF(bp) || \ | 863 | CHIP_IS_57810_MF(bp) || \ |
| 855 | CHIP_IS_57810_VF(bp) || \ | 864 | CHIP_IS_57810_VF(bp) || \ |
| 856 | CHIP_IS_57811(bp) || \ | 865 | CHIP_IS_57811xx(bp) || \ |
| 857 | CHIP_IS_57811_MF(bp) || \ | ||
| 858 | CHIP_IS_57811_VF(bp) || \ | ||
| 859 | CHIP_IS_57840(bp) || \ | 866 | CHIP_IS_57840(bp) || \ |
| 860 | CHIP_IS_57840_MF(bp) || \ | 867 | CHIP_IS_57840_MF(bp) || \ |
| 861 | CHIP_IS_57840_VF(bp)) | 868 | CHIP_IS_57840_VF(bp)) |
| @@ -1215,14 +1222,16 @@ enum { · 353 unmodified lines | |||
| 1215 | BNX2X_SP_RTNL_ENABLE_SRIOV, | 1222 | BNX2X_SP_RTNL_ENABLE_SRIOV, |
| 1216 | BNX2X_SP_RTNL_VFPF_MCAST, | 1223 | BNX2X_SP_RTNL_VFPF_MCAST, |
| 1217 | BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, | 1224 | BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, |
| 1225 | BNX2X_SP_RTNL_HYPERVISOR_VLAN, | ||
| 1218 | }; | 1226 | }; |
| 1219 | 1227 | ||
| 1220 | 1228 | ||
| 1221 | struct bnx2x_prev_path_list { | 1229 | struct bnx2x_prev_path_list { |
| 1230 | struct list_head list; | ||
| 1222 | u8 bus; | 1231 | u8 bus; |
| 1223 | u8 slot; | 1232 | u8 slot; |
| 1224 | u8 path; | 1233 | u8 path; |
| 1225 | struct list_head list; | 1234 | u8 aer; |
| 1226 | u8 undi; | 1235 | u8 undi; |
| 1227 | }; | 1236 | }; |
| 1228 | 1237 | ||
| @@ -1269,6 +1278,8 @@ struct bnx2x { · 40 unmodified lines | |||
| 1269 | #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) | 1278 | #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) |
| 1270 | 1279 | ||
| 1271 | #ifdef CONFIG_BNX2X_SRIOV | 1280 | #ifdef CONFIG_BNX2X_SRIOV |
| 1281 | /* protects vf2pf mailbox from simultaneous access */ | ||
| 1282 | struct mutex vf2pf_mutex; | ||
| 1272 | /* vf pf channel mailbox contains request and response buffers */ | 1283 | /* vf pf channel mailbox contains request and response buffers */ |
| 1273 | struct bnx2x_vf_mbx_msg *vf2pf_mbox; | 1284 | struct bnx2x_vf_mbx_msg *vf2pf_mbox; |
| 1274 | dma_addr_t vf2pf_mbox_mapping; | 1285 | dma_addr_t vf2pf_mbox_mapping; |
| @@ -1281,6 +1292,8 @@ struct bnx2x { · 6 unmodified lines | |||
| 1281 | dma_addr_t pf2vf_bulletin_mapping; | 1292 | dma_addr_t pf2vf_bulletin_mapping; |
| 1282 | 1293 | ||
| 1283 | struct pf_vf_bulletin_content old_bulletin; | 1294 | struct pf_vf_bulletin_content old_bulletin; |
| 1295 | |||
| 1296 | u16 requested_nr_virtfn; | ||
| 1284 | #endif /* CONFIG_BNX2X_SRIOV */ | 1297 | #endif /* CONFIG_BNX2X_SRIOV */ |
| 1285 | 1298 | ||
| 1286 | struct net_device *dev; | 1299 | struct net_device *dev; |
| @@ -1944,12 +1957,9 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, · 657 unmodified lines | |||
| 1944 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, | 1957 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, |
| 1945 | bool is_pf); | 1958 | bool is_pf); |
| 1946 | 1959 | ||
| 1947 | #define BNX2X_ILT_ZALLOC(x, y, size) \ | 1960 | #define BNX2X_ILT_ZALLOC(x, y, size) \ |
| 1948 | do { \ | 1961 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, \ |
| 1949 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | 1962 | GFP_KERNEL | __GFP_ZERO) |
| 1950 | if (x) \ | ||
| 1951 | memset(x, 0, size); \ | ||
| 1952 | } while (0) | ||
| 1953 | 1963 | ||
| 1954 | #define BNX2X_ILT_FREE(x, y, size) \ | 1964 | #define BNX2X_ILT_FREE(x, y, size) \ |
| 1955 | do { \ | 1965 | do { \ |
| @@ -2286,7 +2296,7 @@ static const u32 dmae_reg_go_c[] = { · 330 unmodified lines | |||
| 2286 | DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 | 2296 | DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 |
| 2287 | }; | 2297 | }; |
| 2288 | 2298 | ||
| 2289 | void bnx2x_set_ethtool_ops(struct net_device *netdev); | 2299 | void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); |
| 2290 | void bnx2x_notify_link_changed(struct bnx2x *bp); | 2300 | void bnx2x_notify_link_changed(struct bnx2x *bp); |
| 2291 | 2301 | ||
| 2292 | #define BNX2X_MF_SD_PROTOCOL(bp) \ | 2302 | #define BNX2X_MF_SD_PROTOCOL(bp) \ |
| @@ -451,7 +451,8 @@ static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue, · 450 unmodified lines | |||
| 451 | * Compute number of aggregated segments, and gso_type. | 451 | * Compute number of aggregated segments, and gso_type. |
| 452 | */ | 452 | */ |
| 453 | static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags, | 453 | static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags, |
| 454 | u16 len_on_bd, unsigned int pkt_len) | 454 | u16 len_on_bd, unsigned int pkt_len, |
| 455 | u16 num_of_coalesced_segs) | ||
| 455 | { | 456 | { |
| 456 | /* TPA aggregation won't have either IP options or TCP options | 457 | /* TPA aggregation won't have either IP options or TCP options |
| 457 | * other than timestamp or IPv6 extension headers. | 458 | * other than timestamp or IPv6 extension headers. |
| @@ -480,8 +481,7 @@ static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags, · 22 unmodified lines | |||
| 480 | /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count | 481 | /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count |
| 481 | * to skb_shinfo(skb)->gso_segs | 482 | * to skb_shinfo(skb)->gso_segs |
| 482 | */ | 483 | */ |
| 483 | NAPI_GRO_CB(skb)->count = DIV_ROUND_UP(pkt_len - hdrs_len, | 484 | NAPI_GRO_CB(skb)->count = num_of_coalesced_segs; |
| 484 | skb_shinfo(skb)->gso_size); | ||
| 485 | } | 485 | } |
| 486 | 486 | ||
| 487 | static int bnx2x_alloc_rx_sge(struct bnx2x *bp, | 487 | static int bnx2x_alloc_rx_sge(struct bnx2x *bp, |
| @@ -537,7 +537,8 @@ static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp, · 49 unmodified lines | |||
| 537 | /* This is needed in order to enable forwarding support */ | 537 | /* This is needed in order to enable forwarding support */ |
| 538 | if (frag_size) | 538 | if (frag_size) |
| 539 | bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd, | 539 | bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd, |
| 540 | le16_to_cpu(cqe->pkt_len)); | 540 | le16_to_cpu(cqe->pkt_len), |
| 541 | le16_to_cpu(cqe->num_of_coalesced_segs)); | ||
| 541 | 542 | ||
| 542 | #ifdef BNX2X_STOP_ON_ERROR | 543 | #ifdef BNX2X_STOP_ON_ERROR |
| 543 | if (pages > min_t(u32, 8, MAX_SKB_FRAGS) * SGE_PAGES) { | 544 | if (pages > min_t(u32, 8, MAX_SKB_FRAGS) * SGE_PAGES) { |
| @@ -641,6 +642,14 @@ static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb) · 97 unmodified lines | |||
| 641 | th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb), | 642 | th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb), |
| 642 | &iph->saddr, &iph->daddr, 0); | 643 | &iph->saddr, &iph->daddr, 0); |
| 643 | } | 644 | } |
| 645 | |||
| 646 | static void bnx2x_gro_csum(struct bnx2x *bp, struct sk_buff *skb, | ||
| 647 | void (*gro_func)(struct bnx2x*, struct sk_buff*)) | ||
| 648 | { | ||
| 649 | skb_set_network_header(skb, 0); | ||
| 650 | gro_func(bp, skb); | ||
| 651 | tcp_gro_complete(skb); | ||
| 652 | } | ||
| 644 | #endif | 653 | #endif |
| 645 | 654 | ||
| 646 | static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp, | 655 | static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
| @@ -648,19 +657,17 @@ static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp, · 1 unmodified line | |||
| 648 | { | 657 | { |
| 649 | #ifdef CONFIG_INET | 658 | #ifdef CONFIG_INET |
| 650 | if (skb_shinfo(skb)->gso_size) { | 659 | if (skb_shinfo(skb)->gso_size) { |
| 651 | skb_set_network_header(skb, 0); | ||
| 652 | switch (be16_to_cpu(skb->protocol)) { | 660 | switch (be16_to_cpu(skb->protocol)) { |
| 653 | case ETH_P_IP: | 661 | case ETH_P_IP: |
| 654 | bnx2x_gro_ip_csum(bp, skb); | 662 | bnx2x_gro_csum(bp, skb, bnx2x_gro_ip_csum); |
| 655 | break; | 663 | break; |
| 656 | case ETH_P_IPV6: | 664 | case ETH_P_IPV6: |
| 657 | bnx2x_gro_ipv6_csum(bp, skb); | 665 | bnx2x_gro_csum(bp, skb, bnx2x_gro_ipv6_csum); |
| 658 | break; | 666 | break; |
| 659 | default: | 667 | default: |
| 660 | BNX2X_ERR("FW GRO supports only IPv4/IPv6, not 0x%04x\n", | 668 | BNX2X_ERR("Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n", |
| 661 | be16_to_cpu(skb->protocol)); | 669 | be16_to_cpu(skb->protocol)); |
| 662 | } | 670 | } |
| 663 | tcp_gro_complete(skb); | ||
| 664 | } | 671 | } |
| 665 | #endif | 672 | #endif |
| 666 | napi_gro_receive(&fp->napi, skb); | 673 | napi_gro_receive(&fp->napi, skb); |
| @@ -718,7 +725,7 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp, · 51 unmodified lines | |||
| 718 | if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages, | 725 | if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages, |
| 719 | skb, cqe, cqe_idx)) { | 726 | skb, cqe, cqe_idx)) { |
| 720 | if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN) | 727 | if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN) |
| 721 | __vlan_hwaccel_put_tag(skb, tpa_info->vlan_tag); | 728 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tpa_info->vlan_tag); |
| 722 | bnx2x_gro_receive(bp, fp, skb); | 729 | bnx2x_gro_receive(bp, fp, skb); |
| 723 | } else { | 730 | } else { |
| 724 | DP(NETIF_MSG_RX_STATUS, | 731 | DP(NETIF_MSG_RX_STATUS, |
| @@ -993,7 +1000,7 @@ reuse_rx: · 268 unmodified lines | |||
| 993 | 1000 | ||
| 994 | if (le16_to_cpu(cqe_fp->pars_flags.flags) & | 1001 | if (le16_to_cpu(cqe_fp->pars_flags.flags) & |
| 995 | PARSING_FLAGS_VLAN) | 1002 | PARSING_FLAGS_VLAN) |
| 996 | __vlan_hwaccel_put_tag(skb, | 1003 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), |
| 997 | le16_to_cpu(cqe_fp->vlan_tag)); | 1004 | le16_to_cpu(cqe_fp->vlan_tag)); |
| 998 | napi_gro_receive(&fp->napi, skb); | 1005 | napi_gro_receive(&fp->napi, skb); |
| 999 | 1006 | ||
| @@ -1037,6 +1044,7 @@ static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie) · 37 unmodified lines | |||
| 1037 | DP(NETIF_MSG_INTR, | 1044 | DP(NETIF_MSG_INTR, |
| 1038 | "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n", | 1045 | "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n", |
| 1039 | fp->index, fp->fw_sb_id, fp->igu_sb_id); | 1046 | fp->index, fp->fw_sb_id, fp->igu_sb_id); |
| 1047 | |||
| 1040 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); | 1048 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); |
| 1041 | 1049 | ||
| 1042 | #ifdef BNX2X_STOP_ON_ERROR | 1050 | #ifdef BNX2X_STOP_ON_ERROR |
| @@ -1718,7 +1726,7 @@ static int bnx2x_req_irq(struct bnx2x *bp) · 675 unmodified lines | |||
| 1718 | return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev); | 1726 | return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev); |
| 1719 | } | 1727 | } |
| 1720 | 1728 | ||
| 1721 | static int bnx2x_setup_irqs(struct bnx2x *bp) | 1729 | int bnx2x_setup_irqs(struct bnx2x *bp) |
| 1722 | { | 1730 | { |
| 1723 | int rc = 0; | 1731 | int rc = 0; |
| 1724 | if (bp->flags & USING_MSIX_FLAG && | 1732 | if (bp->flags & USING_MSIX_FLAG && |
| @@ -2009,7 +2017,7 @@ static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code) · 284 unmodified lines | |||
| 2009 | * Cleans the object that have internal lists without sending | 2017 | * Cleans the object that have internal lists without sending |
| 2010 | * ramrods. Should be run when interrutps are disabled. | 2018 | * ramrods. Should be run when interrutps are disabled. |
| 2011 | */ | 2019 | */ |
| 2012 | static void bnx2x_squeeze_objects(struct bnx2x *bp) | 2020 | void bnx2x_squeeze_objects(struct bnx2x *bp) |
| 2013 | { | 2021 | { |
| 2014 | int rc; | 2022 | int rc; |
| 2015 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | 2023 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; |
| @@ -2574,6 +2582,8 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode) · 558 unmodified lines | |||
| 2574 | } | 2582 | } |
| 2575 | } | 2583 | } |
| 2576 | 2584 | ||
| 2585 | bnx2x_pre_irq_nic_init(bp); | ||
| 2586 | |||
| 2577 | /* Connect to IRQs */ | 2587 | /* Connect to IRQs */ |
| 2578 | rc = bnx2x_setup_irqs(bp); | 2588 | rc = bnx2x_setup_irqs(bp); |
| 2579 | if (rc) { | 2589 | if (rc) { |
| @@ -2583,11 +2593,11 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode) · 3 unmodified lines | |||
| 2583 | LOAD_ERROR_EXIT(bp, load_error2); | 2593 | LOAD_ERROR_EXIT(bp, load_error2); |
| 2584 | } | 2594 | } |
| 2585 | 2595 | ||
| 2586 | /* Setup NIC internals and enable interrupts */ | ||
| 2587 | bnx2x_nic_init(bp, load_code); | ||
| 2588 | |||
| 2589 | /* Init per-function objects */ | 2596 | /* Init per-function objects */ |
| 2590 | if (IS_PF(bp)) { | 2597 | if (IS_PF(bp)) { |
| 2598 | /* Setup NIC internals and enable interrupts */ | ||
| 2599 | bnx2x_post_irq_nic_init(bp, load_code); | ||
| 2600 | |||
| 2591 | bnx2x_init_bp_objs(bp); | 2601 | bnx2x_init_bp_objs(bp); |
| 2592 | bnx2x_iov_nic_init(bp); | 2602 | bnx2x_iov_nic_init(bp); |
| 2593 | 2603 | ||
| @@ -2657,7 +2667,8 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode) · 63 unmodified lines | |||
| 2657 | if (IS_PF(bp)) | 2667 | if (IS_PF(bp)) |
| 2658 | rc = bnx2x_set_eth_mac(bp, true); | 2668 | rc = bnx2x_set_eth_mac(bp, true); |
| 2659 | else /* vf */ | 2669 | else /* vf */ |
| 2660 | rc = bnx2x_vfpf_set_mac(bp); | 2670 | rc = bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, bp->fp->index, |
| 2671 | true); | ||
| 2661 | if (rc) { | 2672 | if (rc) { |
| 2662 | BNX2X_ERR("Setting Ethernet MAC failed\n"); | 2673 | BNX2X_ERR("Setting Ethernet MAC failed\n"); |
| 2663 | LOAD_ERROR_EXIT(bp, load_error3); | 2674 | LOAD_ERROR_EXIT(bp, load_error3); |
| @@ -2777,7 +2788,7 @@ load_error0: · 113 unmodified lines | |||
| 2777 | #endif /* ! BNX2X_STOP_ON_ERROR */ | 2788 | #endif /* ! BNX2X_STOP_ON_ERROR */ |
| 2778 | } | 2789 | } |
| 2779 | 2790 | ||
| 2780 | static int bnx2x_drain_tx_queues(struct bnx2x *bp) | 2791 | int bnx2x_drain_tx_queues(struct bnx2x *bp) |
| 2781 | { | 2792 | { |
| 2782 | u8 rc = 0, cos, i; | 2793 | u8 rc = 0, cos, i; |
| 2783 | 2794 | ||
| @@ -2926,9 +2937,9 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link) · 142 unmodified lines | |||
| 2926 | bnx2x_free_fp_mem_cnic(bp); | 2937 | bnx2x_free_fp_mem_cnic(bp); |
| 2927 | 2938 | ||
| 2928 | if (IS_PF(bp)) { | 2939 | if (IS_PF(bp)) { |
| 2929 | bnx2x_free_mem(bp); | ||
| 2930 | if (CNIC_LOADED(bp)) | 2940 | if (CNIC_LOADED(bp)) |
| 2931 | bnx2x_free_mem_cnic(bp); | 2941 | bnx2x_free_mem_cnic(bp); |
| 2942 | bnx2x_free_mem(bp); | ||
| 2932 | } | 2943 | } |
| 2933 | bp->state = BNX2X_STATE_CLOSED; | 2944 | bp->state = BNX2X_STATE_CLOSED; |
| 2934 | bp->cnic_loaded = false; | 2945 | bp->cnic_loaded = false; |
| @@ -3089,11 +3100,11 @@ int bnx2x_poll(struct napi_struct *napi, int budget) · 154 unmodified lines | |||
| 3089 | * to ease the pain of our fellow microcode engineers | 3100 | * to ease the pain of our fellow microcode engineers |
| 3090 | * we use one mapping for both BDs | 3101 | * we use one mapping for both BDs |
| 3091 | */ | 3102 | */ |
| 3092 | static noinline u16 bnx2x_tx_split(struct bnx2x *bp, | 3103 | static u16 bnx2x_tx_split(struct bnx2x *bp, |
| 3093 | struct bnx2x_fp_txdata *txdata, | 3104 | struct bnx2x_fp_txdata *txdata, |
| 3094 | struct sw_tx_bd *tx_buf, | 3105 | struct sw_tx_bd *tx_buf, |
| 3095 | struct eth_tx_start_bd **tx_bd, u16 hlen, | 3106 | struct eth_tx_start_bd **tx_bd, u16 hlen, |
| 3096 | u16 bd_prod, int nbd) | 3107 | u16 bd_prod) |
| 3097 | { | 3108 | { |
| 3098 | struct eth_tx_start_bd *h_tx_bd = *tx_bd; | 3109 | struct eth_tx_start_bd *h_tx_bd = *tx_bd; |
| 3099 | struct eth_tx_bd *d_tx_bd; | 3110 | struct eth_tx_bd *d_tx_bd; |
| @@ -3101,11 +3112,10 @@ static noinline u16 bnx2x_tx_split(struct bnx2x *bp, · 1 unmodified line | |||
| 3101 | int old_len = le16_to_cpu(h_tx_bd->nbytes); | 3112 | int old_len = le16_to_cpu(h_tx_bd->nbytes); |
| 3102 | 3113 | ||
| 3103 | /* first fix first BD */ | 3114 | /* first fix first BD */ |
| 3104 | h_tx_bd->nbd = cpu_to_le16(nbd); | ||
| 3105 | h_tx_bd->nbytes = cpu_to_le16(hlen); | 3115 | h_tx_bd->nbytes = cpu_to_le16(hlen); |
| 3106 | 3116 | ||
| 3107 | DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d (%x:%x) nbd %d\n", | 3117 | DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d (%x:%x)\n", |
| 3108 | h_tx_bd->nbytes, h_tx_bd->addr_hi, h_tx_bd->addr_lo, h_tx_bd->nbd); | 3118 | h_tx_bd->nbytes, h_tx_bd->addr_hi, h_tx_bd->addr_lo); |
| 3109 | 3119 | ||
| 3110 | /* now get a new data BD | 3120 | /* now get a new data BD |
| 3111 | * (after the pbd) and fill it */ | 3121 | * (after the pbd) and fill it */ |
| @@ -3134,7 +3144,7 @@ static noinline u16 bnx2x_tx_split(struct bnx2x *bp, · 22 unmodified lines | |||
| 3134 | 3144 | ||
| 3135 | #define bswab32(b32) ((__force __le32) swab32((__force __u32) (b32))) | 3145 | #define bswab32(b32) ((__force __le32) swab32((__force __u32) (b32))) |
| 3136 | #define bswab16(b16) ((__force __le16) swab16((__force __u16) (b16))) | 3146 | #define bswab16(b16) ((__force __le16) swab16((__force __u16) (b16))) |
| 3137 | static inline __le16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix) | 3147 | static __le16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix) |
| 3138 | { | 3148 | { |
| 3139 | __sum16 tsum = (__force __sum16) csum; | 3149 | __sum16 tsum = (__force __sum16) csum; |
| 3140 | 3150 | ||
| @@ -3149,30 +3159,47 @@ static inline __le16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix) · 8 unmodified lines | |||
| 3149 | return bswab16(tsum); | 3159 | return bswab16(tsum); |
| 3150 | } | 3160 | } |
| 3151 | 3161 | ||
| 3152 | static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb) | 3162 | static u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb) |
| 3153 | { | 3163 | { |
| 3154 | u32 rc; | 3164 | u32 rc; |
| 3165 | __u8 prot = 0; | ||
| 3166 | __be16 protocol; | ||
| 3155 | 3167 | ||
| 3156 | if (skb->ip_summed != CHECKSUM_PARTIAL) | 3168 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
| 3157 | rc = XMIT_PLAIN; | 3169 | return XMIT_PLAIN; |
| 3158 | 3170 | ||
| 3159 | else { | 3171 | protocol = vlan_get_protocol(skb); |
| 3160 | if (vlan_get_protocol(skb) == htons(ETH_P_IPV6)) { | 3172 | if (protocol == htons(ETH_P_IPV6)) { |
| 3161 | rc = XMIT_CSUM_V6; | 3173 | rc = XMIT_CSUM_V6; |
| 3162 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | 3174 | prot = ipv6_hdr(skb)->nexthdr; |
| 3163 | rc |= XMIT_CSUM_TCP; | 3175 | } else { |
| 3176 | rc = XMIT_CSUM_V4; | ||
| 3177 | prot = ip_hdr(skb)->protocol; | ||
| 3178 | } | ||
| 3164 | 3179 | ||
| 3180 | if (!CHIP_IS_E1x(bp) && skb->encapsulation) { | ||
| 3181 | if (inner_ip_hdr(skb)->version == 6) { | ||
| 3182 | rc |= XMIT_CSUM_ENC_V6; | ||
| 3183 | if (inner_ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | ||
| 3184 | rc |= XMIT_CSUM_TCP; | ||
| 3165 | } else { | 3185 | } else { |
| 3166 | rc = XMIT_CSUM_V4; | 3186 | rc |= XMIT_CSUM_ENC_V4; |
| 3167 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) | 3187 | if (inner_ip_hdr(skb)->protocol == IPPROTO_TCP) |
| 3168 | rc |= XMIT_CSUM_TCP; | 3188 | rc |= XMIT_CSUM_TCP; |
| 3169 | } | 3189 | } |
| 3170 | } | 3190 | } |
| 3191 | if (prot == IPPROTO_TCP) | ||
| 3192 | rc |= XMIT_CSUM_TCP; | ||
| 3171 | 3193 | ||
| 3172 | if (skb_is_gso_v6(skb)) | 3194 | if (skb_is_gso_v6(skb)) { |
| 3173 | rc |= XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6; | 3195 | rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6); |
| 3174 | else if (skb_is_gso(skb)) | 3196 | if (rc & XMIT_CSUM_ENC) |
| 3175 | rc |= XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP; | 3197 | rc |= XMIT_GSO_ENC_V6; |
| 3198 | } else if (skb_is_gso(skb)) { | ||
| 3199 | rc |= (XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP); | ||
| 3200 | if (rc & XMIT_CSUM_ENC) | ||
| 3201 | rc |= XMIT_GSO_ENC_V4; | ||
| 3202 | } | ||
| 3176 | 3203 | ||
| 3177 | return rc; | 3204 | return rc; |
| 3178 | } | 3205 | } |
| @@ -3257,14 +3284,23 @@ exit_lbl: · 78 unmodified lines | |||
| 3257 | } | 3284 | } |
| 3258 | #endif | 3285 | #endif |
| 3259 | 3286 | ||
| 3260 | static inline void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data, | 3287 | static void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data, |
| 3261 | u32 xmit_type) | 3288 | u32 xmit_type) |
| 3262 | { | 3289 | { |
| 3290 | struct ipv6hdr *ipv6; | ||
| 3291 | |||
| 3263 | *parsing_data |= (skb_shinfo(skb)->gso_size << | 3292 | *parsing_data |= (skb_shinfo(skb)->gso_size << |
| 3264 | ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) & | 3293 | ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) & |
| 3265 | ETH_TX_PARSE_BD_E2_LSO_MSS; | 3294 | ETH_TX_PARSE_BD_E2_LSO_MSS; |
| 3266 | if ((xmit_type & XMIT_GSO_V6) && | 3295 | |
| 3267 | (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6)) | 3296 | if (xmit_type & XMIT_GSO_ENC_V6) |
| 3297 | ipv6 = inner_ipv6_hdr(skb); | ||
| 3298 | else if (xmit_type & XMIT_GSO_V6) | ||
| 3299 | ipv6 = ipv6_hdr(skb); | ||
| 3300 | else | ||
| 3301 | ipv6 = NULL; | ||
| 3302 | |||
| 3303 | if (ipv6 && ipv6->nexthdr == NEXTHDR_IPV6) | ||
| 3268 | *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR; | 3304 | *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR; |
| 3269 | } | 3305 | } |
| 3270 | 3306 | ||
| @@ -3275,13 +3311,13 @@ static inline void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data, · 4 unmodified lines | |||
| 3275 | * @pbd: parse BD | 3311 | * @pbd: parse BD |
| 3276 | * @xmit_type: xmit flags | 3312 | * @xmit_type: xmit flags |
| 3277 | */ | 3313 | */ |
| 3278 | static inline void bnx2x_set_pbd_gso(struct sk_buff *skb, | 3314 | static void bnx2x_set_pbd_gso(struct sk_buff *skb, |
| 3279 | struct eth_tx_parse_bd_e1x *pbd, | 3315 | struct eth_tx_parse_bd_e1x *pbd, |
| 3280 | u32 xmit_type) | 3316 | u32 xmit_type) |
| 3281 | { | 3317 | { |
| 3282 | pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size); | 3318 | pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size); |
| 3283 | pbd->tcp_send_seq = bswab32(tcp_hdr(skb)->seq); | 3319 | pbd->tcp_send_seq = bswab32(tcp_hdr(skb)->seq); |
| 3284 | pbd->tcp_flags = pbd_tcp_flags(skb); | 3320 | pbd->tcp_flags = pbd_tcp_flags(tcp_hdr(skb)); |
| 3285 | 3321 | ||
| 3286 | if (xmit_type & XMIT_GSO_V4) { | 3322 | if (xmit_type & XMIT_GSO_V4) { |
| 3287 | pbd->ip_id = bswab16(ip_hdr(skb)->id); | 3323 | pbd->ip_id = bswab16(ip_hdr(skb)->id); |
| @@ -3300,6 +3336,40 @@ static inline void bnx2x_set_pbd_gso(struct sk_buff *skb, · 12 unmodified lines | |||
| 3300 | cpu_to_le16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN); | 3336 | cpu_to_le16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN); |
| 3301 | } | 3337 | } |
| 3302 | 3338 | ||
| 3339 | /** | ||
| 3340 | * bnx2x_set_pbd_csum_enc - update PBD with checksum and return header length | ||
| 3341 | * | ||
| 3342 | * @bp: driver handle | ||
| 3343 | * @skb: packet skb | ||
| 3344 | * @parsing_data: data to be updated | ||
| 3345 | * @xmit_type: xmit flags | ||
| 3346 | * | ||
| 3347 | * 57712/578xx related, when skb has encapsulation | ||
| 3348 | */ | ||
| 3349 | static u8 bnx2x_set_pbd_csum_enc(struct bnx2x *bp, struct sk_buff *skb, | ||
| 3350 | u32 *parsing_data, u32 xmit_type) | ||
| 3351 | { | ||
| 3352 | *parsing_data |= | ||
| 3353 | ((((u8 *)skb_inner_transport_header(skb) - skb->data) >> 1) << | ||
| 3354 | ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) & | ||
| 3355 | ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W; | ||
| 3356 | |||
| 3357 | if (xmit_type & XMIT_CSUM_TCP) { | ||
| 3358 | *parsing_data |= ((inner_tcp_hdrlen(skb) / 4) << | ||
| 3359 | ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) & | ||
| 3360 | ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW; | ||
| 3361 | |||
| 3362 | return skb_inner_transport_header(skb) + | ||
| 3363 | inner_tcp_hdrlen(skb) - skb->data; | ||
| 3364 | } | ||
| 3365 | |||
| 3366 | /* We support checksum offload for TCP and UDP only. | ||
| 3367 | * No need to pass the UDP header length - it's a constant. | ||
| 3368 | */ | ||
| 3369 | return skb_inner_transport_header(skb) + | ||
| 3370 | sizeof(struct udphdr) - skb->data; | ||
| 3371 | } | ||
| 3372 | |||
| 3303 | /** | 3373 | /** |
| 3304 | * bnx2x_set_pbd_csum_e2 - update PBD with checksum and return header length | 3374 | * bnx2x_set_pbd_csum_e2 - update PBD with checksum and return header length |
| 3305 | * | 3375 | * |
| @@ -3308,15 +3378,15 @@ static inline void bnx2x_set_pbd_gso(struct sk_buff *skb, · 2 unmodified lines | |||
| 3308 | * @parsing_data: data to be updated | 3378 | * @parsing_data: data to be updated |
| 3309 | * @xmit_type: xmit flags | 3379 | * @xmit_type: xmit flags |
| 3310 | * | 3380 | * |
| 3311 | * 57712 related | 3381 | * 57712/578xx related |
| 3312 | */ | 3382 | */ |
| 3313 | static inline u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb, | 3383 | static u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb, |
| 3314 | u32 *parsing_data, u32 xmit_type) | 3384 | u32 *parsing_data, u32 xmit_type) |
| 3315 | { | 3385 | { |
| 3316 | *parsing_data |= | 3386 | *parsing_data |= |
| 3317 | ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) << | 3387 | ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) << |
| 3318 | ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT) & | 3388 | ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) & |
| 3319 | ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W; | 3389 | ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W; |
| 3320 | 3390 | ||
| 3321 | if (xmit_type & XMIT_CSUM_TCP) { | 3391 | if (xmit_type & XMIT_CSUM_TCP) { |
| 3322 | *parsing_data |= ((tcp_hdrlen(skb) / 4) << | 3392 | *parsing_data |= ((tcp_hdrlen(skb) / 4) << |
| @@ -3331,17 +3401,15 @@ static inline u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb, · 8 unmodified lines | |||
| 3331 | return skb_transport_header(skb) + sizeof(struct udphdr) - skb->data; | 3401 | return skb_transport_header(skb) + sizeof(struct udphdr) - skb->data; |
| 3332 | } | 3402 | } |
| 3333 | 3403 | ||
| 3334 | static inline void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb, | 3404 | /* set FW indication according to inner or outer protocols if tunneled */ |
| 3335 | struct eth_tx_start_bd *tx_start_bd, u32 xmit_type) | 3405 | static void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb, |
| 3406 | struct eth_tx_start_bd *tx_start_bd, | ||
| 3407 | u32 xmit_type) | ||
| 3336 | { | 3408 | { |
| 3337 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM; | 3409 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM; |
| 3338 | 3410 | ||
| 3339 | if (xmit_type & XMIT_CSUM_V4) | 3411 | if (xmit_type & (XMIT_CSUM_ENC_V6 | XMIT_CSUM_V6)) |
| 3340 | tx_start_bd->bd_flags.as_bitfield |= | 3412 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6; |
| 3341 | ETH_TX_BD_FLAGS_IP_CSUM; | ||
| 3342 | else | ||
| 3343 | tx_start_bd->bd_flags.as_bitfield |= | ||
| 3344 | ETH_TX_BD_FLAGS_IPV6; | ||
| 3345 | 3413 | ||
| 3346 | if (!(xmit_type & XMIT_CSUM_TCP)) | 3414 | if (!(xmit_type & XMIT_CSUM_TCP)) |
| 3347 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IS_UDP; | 3415 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IS_UDP; |
| @@ -3355,9 +3423,9 @@ static inline void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb, · 7 unmodified lines | |||
| 3355 | * @pbd: parse BD to be updated | 3423 | * @pbd: parse BD to be updated |
| 3356 | * @xmit_type: xmit flags | 3424 | * @xmit_type: xmit flags |
| 3357 | */ | 3425 | */ |
| 3358 | static inline u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb, | 3426 | static u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb, |
| 3359 | struct eth_tx_parse_bd_e1x *pbd, | 3427 | struct eth_tx_parse_bd_e1x *pbd, |
| 3360 | u32 xmit_type) | 3428 | u32 xmit_type) |
| 3361 | { | 3429 | { |
| 3362 | u8 hlen = (skb_network_header(skb) - skb->data) >> 1; | 3430 | u8 hlen = (skb_network_header(skb) - skb->data) >> 1; |
| 3363 | 3431 | ||
| @@ -3403,6 +3471,75 @@ static inline u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb, · 39 unmodified lines | |||
| 3403 | return hlen; | 3471 | return hlen; |
| 3404 | } | 3472 | } |
| 3405 | 3473 | ||
| 3474 | static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb, | ||
| 3475 | struct eth_tx_parse_bd_e2 *pbd_e2, | ||
| 3476 | struct eth_tx_parse_2nd_bd *pbd2, | ||
| 3477 | u16 *global_data, | ||
| 3478 | u32 xmit_type) | ||
| 3479 | { | ||
| 3480 | u16 hlen_w = 0; | ||
| 3481 | u8 outerip_off, outerip_len = 0; | ||
| 3482 | /* from outer IP to transport */ | ||
| 3483 | hlen_w = (skb_inner_transport_header(skb) - | ||
| 3484 | skb_network_header(skb)) >> 1; | ||
| 3485 | |||
| 3486 | /* transport len */ | ||
| 3487 | if (xmit_type & XMIT_CSUM_TCP) | ||
| 3488 | hlen_w += inner_tcp_hdrlen(skb) >> 1; | ||
| 3489 | else | ||
| 3490 | hlen_w += sizeof(struct udphdr) >> 1; | ||
| 3491 | |||
| 3492 | pbd2->fw_ip_hdr_to_payload_w = hlen_w; | ||
| 3493 | |||
| 3494 | if (xmit_type & XMIT_CSUM_ENC_V4) { | ||
| 3495 | struct iphdr *iph = ip_hdr(skb); | ||
| 3496 | pbd2->fw_ip_csum_wo_len_flags_frag = | ||
| 3497 | bswab16(csum_fold((~iph->check) - | ||
| 3498 | iph->tot_len - iph->frag_off)); | ||
| 3499 | } else { | ||
| 3500 | pbd2->fw_ip_hdr_to_payload_w = | ||
| 3501 | hlen_w - ((sizeof(struct ipv6hdr)) >> 1); | ||
| 3502 | } | ||
| 3503 | |||
| 3504 | pbd2->tcp_send_seq = bswab32(inner_tcp_hdr(skb)->seq); | ||
| 3505 | |||
| 3506 | pbd2->tcp_flags = pbd_tcp_flags(inner_tcp_hdr(skb)); | ||
| 3507 | |||
| 3508 | if (xmit_type & XMIT_GSO_V4) { | ||
| 3509 | pbd2->hw_ip_id = bswab16(inner_ip_hdr(skb)->id); | ||
| 3510 | |||
| 3511 | pbd_e2->data.tunnel_data.pseudo_csum = | ||
| 3512 | bswab16(~csum_tcpudp_magic( | ||
| 3513 | inner_ip_hdr(skb)->saddr, | ||
| 3514 | inner_ip_hdr(skb)->daddr, | ||
| 3515 | 0, IPPROTO_TCP, 0)); | ||
| 3516 | |||
| 3517 | outerip_len = ip_hdr(skb)->ihl << 1; | ||
| 3518 | } else { | ||
| 3519 | pbd_e2->data.tunnel_data.pseudo_csum = | ||
| 3520 | bswab16(~csum_ipv6_magic( | ||
| 3521 | &inner_ipv6_hdr(skb)->saddr, | ||
| 3522 | &inner_ipv6_hdr(skb)->daddr, | ||
| 3523 | 0, IPPROTO_TCP, 0)); | ||
| 3524 | } | ||
| 3525 | |||
| 3526 | outerip_off = (skb_network_header(skb) - skb->data) >> 1; | ||
| 3527 | |||
| 3528 | *global_data |= | ||
| 3529 | outerip_off | | ||
| 3530 | (!!(xmit_type & XMIT_CSUM_V6) << | ||
| 3531 | ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT) | | ||
| 3532 | (outerip_len << | ||
| 3533 | ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT) | | ||
| 3534 | ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) << | ||
| 3535 | ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT); | ||
| 3536 | |||
| 3537 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { | ||
| 3538 | SET_FLAG(*global_data, ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST, 1); | ||
| 3539 | pbd2->tunnel_udp_hdr_start_w = skb_transport_offset(skb) >> 1; | ||
| 3540 | } | ||
| 3541 | } | ||
| 3542 | |||
| 3406 | /* called with netif_tx_lock | 3543 | /* called with netif_tx_lock |
| 3407 | * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call | 3544 | * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call |
| 3408 | * netif_wake_queue() | 3545 | * netif_wake_queue() |
| @@ -3418,6 +3555,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) · 9 unmodified lines | |||
| 3418 | struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL; | 3555 | struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL; |
| 3419 | struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; | 3556 | struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; |
| 3420 | struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; | 3557 | struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; |
| 3558 | struct eth_tx_parse_2nd_bd *pbd2 = NULL; | ||
| 3421 | u32 pbd_e2_parsing_data = 0; | 3559 | u32 pbd_e2_parsing_data = 0; |
| 3422 | u16 pkt_prod, bd_prod; | 3560 | u16 pkt_prod, bd_prod; |
| 3423 | int nbd, txq_index; | 3561 | int nbd, txq_index; |
| @@ -3485,7 +3623,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) · 61 unmodified lines | |||
| 3485 | mac_type = MULTICAST_ADDRESS; | 3623 | mac_type = MULTICAST_ADDRESS; |
| 3486 | } | 3624 | } |
| 3487 | 3625 | ||
| 3488 | #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3) | 3626 | #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - BDS_PER_TX_PKT) |
| 3489 | /* First, check if we need to linearize the skb (due to FW | 3627 | /* First, check if we need to linearize the skb (due to FW |
| 3490 | restrictions). No need to check fragmentation if page size > 8K | 3628 | restrictions). No need to check fragmentation if page size > 8K |
| 3491 | (there will be no violation to FW restrictions) */ | 3629 | (there will be no violation to FW restrictions) */ |
| @@ -3533,12 +3671,9 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) · 41 unmodified lines | |||
| 3533 | first_bd = tx_start_bd; | 3671 | first_bd = tx_start_bd; |
| 3534 | 3672 | ||
| 3535 | tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; | 3673 | tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; |
| 3536 | SET_FLAG(tx_start_bd->general_data, | ||
| 3537 | ETH_TX_START_BD_PARSE_NBDS, | ||
| 3538 | 0); | ||
| 3539 | 3674 | ||
| 3540 | /* header nbd */ | 3675 | /* header nbd: indirectly zero other flags! */ |
| 3541 | SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_HDR_NBDS, 1); | 3676 | tx_start_bd->general_data = 1 << ETH_TX_START_BD_HDR_NBDS_SHIFT; |
| 3542 | 3677 | ||
| 3543 | /* remember the first BD of the packet */ | 3678 | /* remember the first BD of the packet */ |
| 3544 | tx_buf->first_bd = txdata->tx_bd_prod; | 3679 | tx_buf->first_bd = txdata->tx_bd_prod; |
| @@ -3558,19 +3693,16 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) · 13 unmodified lines | |||
| 3558 | /* when transmitting in a vf, start bd must hold the ethertype | 3693 | /* when transmitting in a vf, start bd must hold the ethertype |
| 3559 | * for fw to enforce it | 3694 | * for fw to enforce it |
| 3560 | */ | 3695 | */ |
| 3561 | #ifndef BNX2X_STOP_ON_ERROR | 3696 | if (IS_VF(bp)) |
| 3562 | if (IS_VF(bp)) { | ||
| 3563 | #endif | ||
| 3564 | tx_start_bd->vlan_or_ethertype = | 3697 | tx_start_bd->vlan_or_ethertype = |
| 3565 | cpu_to_le16(ntohs(eth->h_proto)); | 3698 | cpu_to_le16(ntohs(eth->h_proto)); |
| 3566 | #ifndef BNX2X_STOP_ON_ERROR | 3699 | else |
| 3567 | } else { | ||
| 3568 | /* used by FW for packet accounting */ | 3700 | /* used by FW for packet accounting */ |
| 3569 | tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); | 3701 | tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); |
| 3570 | } | ||
| 3571 | #endif | ||
| 3572 | } | 3702 | } |
| 3573 | 3703 | ||
| 3704 | nbd = 2; /* start_bd + pbd + frags (updated when pages are mapped) */ | ||
| 3705 | |||
| 3574 | /* turn on parsing and get a BD */ | 3706 | /* turn on parsing and get a BD */ |
| 3575 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); | 3707 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); |
| 3576 | 3708 | ||
| @@ -3580,23 +3712,58 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) · 3 unmodified lines | |||
| 3580 | if (!CHIP_IS_E1x(bp)) { | 3712 | if (!CHIP_IS_E1x(bp)) { |
| 3581 | pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2; | 3713 | pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2; |
| 3582 | memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); | 3714 | memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); |
| 3583 | /* Set PBD in checksum offload case */ | 3715 | |
| 3584 | if (xmit_type & XMIT_CSUM) | 3716 | if (xmit_type & XMIT_CSUM_ENC) { |
| 3717 | u16 global_data = 0; | ||
| 3718 | |||
| 3719 | /* Set PBD in enc checksum offload case */ | ||
| 3720 | hlen = bnx2x_set_pbd_csum_enc(bp, skb, | ||
| 3721 | &pbd_e2_parsing_data, | ||
| 3722 | xmit_type); | ||
| 3723 | |||
| 3724 | /* turn on 2nd parsing and get a BD */ | ||
| 3725 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); | ||
| 3726 | |||
| 3727 | pbd2 = &txdata->tx_desc_ring[bd_prod].parse_2nd_bd; | ||
| 3728 | |||
| 3729 | memset(pbd2, 0, sizeof(*pbd2)); | ||
| 3730 | |||
| 3731 | pbd_e2->data.tunnel_data.ip_hdr_start_inner_w = | ||
| 3732 | (skb_inner_network_header(skb) - | ||
| 3733 | skb->data) >> 1; | ||
| 3734 | |||
| 3735 | if (xmit_type & XMIT_GSO_ENC) | ||
| 3736 | bnx2x_update_pbds_gso_enc(skb, pbd_e2, pbd2, | ||
| 3737 | &global_data, | ||
| 3738 | xmit_type); | ||
| 3739 | |||
| 3740 | pbd2->global_data = cpu_to_le16(global_data); | ||
| 3741 | |||
| 3742 | /* add addition parse BD indication to start BD */ | ||
| 3743 | SET_FLAG(tx_start_bd->general_data, | ||
| 3744 | ETH_TX_START_BD_PARSE_NBDS, 1); | ||
| 3745 | /* set encapsulation flag in start BD */ | ||
| 3746 | SET_FLAG(tx_start_bd->general_data, | ||
| 3747 | ETH_TX_START_BD_TUNNEL_EXIST, 1); | ||
| 3748 | nbd++; | ||
| 3749 | } else if (xmit_type & XMIT_CSUM) { | ||
| 3750 | /* Set PBD in checksum offload case w/o encapsulation */ | ||
| 3585 | hlen = bnx2x_set_pbd_csum_e2(bp, skb, | 3751 | hlen = bnx2x_set_pbd_csum_e2(bp, skb, |
| 3586 | &pbd_e2_parsing_data, | 3752 | &pbd_e2_parsing_data, |
| 3587 | xmit_type); | 3753 | xmit_type); |
| 3754 | } | ||
| 3588 | 3755 | ||
| 3589 | if (IS_MF_SI(bp) || IS_VF(bp)) { | 3756 | /* Add the macs to the parsing BD this is a vf */ |
| 3590 | /* fill in the MAC addresses in the PBD - for local | 3757 | if (IS_VF(bp)) { |
| 3591 | * switching | 3758 | /* override GRE parameters in BD */ |
| 3592 | */ | 3759 | bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi, |
| 3593 | bnx2x_set_fw_mac_addr(&pbd_e2->src_mac_addr_hi, | 3760 | &pbd_e2->data.mac_addr.src_mid, |
| 3594 | &pbd_e2->src_mac_addr_mid, | 3761 | &pbd_e2->data.mac_addr.src_lo, |
| 3595 | &pbd_e2->src_mac_addr_lo, | ||
| 3596 | eth->h_source); | 3762 | eth->h_source); |
| 3597 | bnx2x_set_fw_mac_addr(&pbd_e2->dst_mac_addr_hi, | 3763 | |
| 3598 | &pbd_e2->dst_mac_addr_mid, | 3764 | bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.dst_hi, |
| 3599 | &pbd_e2->dst_mac_addr_lo, | 3765 | &pbd_e2->data.mac_addr.dst_mid, |
| 3766 | &pbd_e2->data.mac_addr.dst_lo, | ||
| 3600 | eth->h_dest); | 3767 | eth->h_dest); |
| 3601 | } | 3768 | } |
| 3602 | 3769 | ||
| @@ -3618,14 +3785,13 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) · 15 unmodified lines | |||
| 3618 | /* Setup the data pointer of the first BD of the packet */ | 3785 | /* Setup the data pointer of the first BD of the packet */ |
| 3619 | tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); | 3786 | tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); |
| 3620 | tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | 3787 | tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); |
| 3621 | nbd = 2; /* start_bd + pbd + frags (updated when pages are mapped) */ | ||
| 3622 | tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); | 3788 | tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); |
| 3623 | pkt_size = tx_start_bd->nbytes; | 3789 | pkt_size = tx_start_bd->nbytes; |
| 3624 | 3790 | ||
| 3625 | DP(NETIF_MSG_TX_QUEUED, | 3791 | DP(NETIF_MSG_TX_QUEUED, |
| 3626 | "first bd @%p addr (%x:%x) nbd %d nbytes %d flags %x vlan %x\n", | 3792 | "first bd @%p addr (%x:%x) nbytes %d flags %x vlan %x\n", |
| 3627 | tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo, | 3793 | tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo, |
| 3628 | le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes), | 3794 | le16_to_cpu(tx_start_bd->nbytes), |
| 3629 | tx_start_bd->bd_flags.as_bitfield, | 3795 | tx_start_bd->bd_flags.as_bitfield, |
| 3630 | le16_to_cpu(tx_start_bd->vlan_or_ethertype)); | 3796 | le16_to_cpu(tx_start_bd->vlan_or_ethertype)); |
| 3631 | 3797 | ||
| @@ -3638,10 +3804,12 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) · 6 unmodified lines | |||
| 3638 | 3804 | ||
| 3639 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO; | 3805 | tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO; |
| 3640 | 3806 | ||
| 3641 | if (unlikely(skb_headlen(skb) > hlen)) | 3807 | if (unlikely(skb_headlen(skb) > hlen)) { |
| 3808 | nbd++; | ||
| 3642 | bd_prod = bnx2x_tx_split(bp, txdata, tx_buf, | 3809 | bd_prod = bnx2x_tx_split(bp, txdata, tx_buf, |
| 3643 | &tx_start_bd, hlen, | 3810 | &tx_start_bd, hlen, |
| 3644 | bd_prod, ++nbd); | 3811 | bd_prod); |
| 3812 | } | ||
| 3645 | if (!CHIP_IS_E1x(bp)) | 3813 | if (!CHIP_IS_E1x(bp)) |
| 3646 | bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data, | 3814 | bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data, |
| 3647 | xmit_type); | 3815 | xmit_type); |
| @@ -3731,9 +3899,13 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) · 83 unmodified lines | |||
| 3731 | if (pbd_e2) | 3899 | if (pbd_e2) |
| 3732 | DP(NETIF_MSG_TX_QUEUED, | 3900 | DP(NETIF_MSG_TX_QUEUED, |
| 3733 | "PBD (E2) @%p dst %x %x %x src %x %x %x parsing_data %x\n", | 3901 | "PBD (E2) @%p dst %x %x %x src %x %x %x parsing_data %x\n", |
| 3734 | pbd_e2, pbd_e2->dst_mac_addr_hi, pbd_e2->dst_mac_addr_mid, | 3902 | pbd_e2, |
| 3735 | pbd_e2->dst_mac_addr_lo, pbd_e2->src_mac_addr_hi, | 3903 | pbd_e2->data.mac_addr.dst_hi, |
| 3736 | pbd_e2->src_mac_addr_mid, pbd_e2->src_mac_addr_lo, | 3904 | pbd_e2->data.mac_addr.dst_mid, |
| 3905 | pbd_e2->data.mac_addr.dst_lo, | ||
| 3906 | pbd_e2->data.mac_addr.src_hi, | ||
| 3907 | pbd_e2->data.mac_addr.src_mid, | ||
| 3908 | pbd_e2->data.mac_addr.src_lo, | ||
| 3737 | pbd_e2->parsing_data); | 3909 | pbd_e2->parsing_data); |
| 3738 | DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod); | 3910 | DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod); |
| 3739 | 3911 | ||
| @@ -50,13 +50,13 @@ extern int int_mode; · 49 unmodified lines | |||
| 50 | } \ | 50 | } \ |
| 51 | } while (0) | 51 | } while (0) |
| 52 | 52 | ||
| 53 | #define BNX2X_PCI_ALLOC(x, y, size) \ | 53 | #define BNX2X_PCI_ALLOC(x, y, size) \ |
| 54 | do { \ | 54 | do { \ |
| 55 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | 55 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, \ |
| 56 | if (x == NULL) \ | 56 | GFP_KERNEL | __GFP_ZERO); \ |
| 57 | goto alloc_mem_err; \ | 57 | if (x == NULL) \ |
| 58 | memset((void *)x, 0, size); \ | 58 | goto alloc_mem_err; \ |
| 59 | } while (0) | 59 | } while (0) |
| 60 | 60 | ||
| 61 | #define BNX2X_ALLOC(x, size) \ | 61 | #define BNX2X_ALLOC(x, size) \ |
| 62 | do { \ | 62 | do { \ |
| @@ -295,16 +295,29 @@ void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); · 232 unmodified lines | |||
| 295 | void bnx2x_nic_init_cnic(struct bnx2x *bp); | 295 | void bnx2x_nic_init_cnic(struct bnx2x *bp); |
| 296 | 296 | ||
| 297 | /** | 297 | /** |
| 298 | * bnx2x_nic_init - init driver internals. | 298 | * bnx2x_preirq_nic_init - init driver internals. |
| 299 | * | 299 | * |
| 300 | * @bp: driver handle | 300 | * @bp: driver handle |
| 301 | * | 301 | * |
| 302 | * Initializes: | 302 | * Initializes: |
| 303 | * - rings | 303 | * - fastpath object |
| 304 | * - fastpath rings | ||
| 305 | * etc. | ||
| 306 | */ | ||
| 307 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp); | ||
| 308 | |||
| 309 | /** | ||
| 310 | * bnx2x_postirq_nic_init - init driver internals. | ||
| 311 | * | ||
| 312 | * @bp: driver handle | ||
| 313 | * @load_code: COMMON, PORT or FUNCTION | ||
| 314 | * | ||
| 315 | * Initializes: | ||
| 304 | * - status blocks | 316 | * - status blocks |
| 317 | * - slowpath rings | ||
| 305 | * - etc. | 318 | * - etc. |
| 306 | */ | 319 | */ |
| 307 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); | 320 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code); |
| 308 | /** | 321 | /** |
| 309 | * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. | 322 | * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. |
| 310 | * | 323 | * |
| @@ -496,7 +509,10 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); · 185 unmodified lines | |||
| 496 | /* setup_tc callback */ | 509 | /* setup_tc callback */ |
| 497 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); | 510 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); |
| 498 | 511 | ||
| 512 | int bnx2x_get_vf_config(struct net_device *dev, int vf, | ||
| 513 | struct ifla_vf_info *ivi); | ||
| 499 | int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); | 514 | int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); |
| 515 | int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos); | ||
| 500 | 516 | ||
| 501 | /* select_queue callback */ | 517 | /* select_queue callback */ |
| 502 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); | 518 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); |
| @@ -834,7 +850,7 @@ static inline void bnx2x_add_all_napi_cnic(struct bnx2x *bp) · 331 unmodified lines | |||
| 834 | /* Add NAPI objects */ | 850 | /* Add NAPI objects */ |
| 835 | for_each_rx_queue_cnic(bp, i) | 851 | for_each_rx_queue_cnic(bp, i) |
| 836 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), | 852 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
| 837 | bnx2x_poll, BNX2X_NAPI_WEIGHT); | 853 | bnx2x_poll, NAPI_POLL_WEIGHT); |
| 838 | } | 854 | } |
| 839 | 855 | ||
| 840 | static inline void bnx2x_add_all_napi(struct bnx2x *bp) | 856 | static inline void bnx2x_add_all_napi(struct bnx2x *bp) |
| @@ -844,7 +860,7 @@ static inline void bnx2x_add_all_napi(struct bnx2x *bp) · 3 unmodified lines | |||
| 844 | /* Add NAPI objects */ | 860 | /* Add NAPI objects */ |
| 845 | for_each_eth_queue(bp, i) | 861 | for_each_eth_queue(bp, i) |
| 846 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), | 862 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
| 847 | bnx2x_poll, BNX2X_NAPI_WEIGHT); | 863 | bnx2x_poll, NAPI_POLL_WEIGHT); |
| 848 | } | 864 | } |
| 849 | 865 | ||
| 850 | static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) | 866 | static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) |
| @@ -970,6 +986,9 @@ static inline int bnx2x_func_start(struct bnx2x *bp) · 119 unmodified lines | |||
| 970 | else /* CHIP_IS_E1X */ | 986 | else /* CHIP_IS_E1X */ |
| 971 | start_params->network_cos_mode = FW_WRR; | 987 | start_params->network_cos_mode = FW_WRR; |
| 972 | 988 | ||
| 989 | start_params->gre_tunnel_mode = IPGRE_TUNNEL; | ||
| 990 | start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS; | ||
| 991 | |||
| 973 | return bnx2x_func_state_change(bp, &func_params); | 992 | return bnx2x_func_state_change(bp, &func_params); |
| 974 | } | 993 | } |
| 975 | 994 | ||
| @@ -1396,4 +1415,8 @@ static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) · 420 unmodified lines | |||
| 1396 | * | 1415 | * |
| 1397 | */ | 1416 | */ |
| 1398 | void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); | 1417 | void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); |
| 1418 | |||
| 1419 | int bnx2x_drain_tx_queues(struct bnx2x *bp); | ||
| 1420 | void bnx2x_squeeze_objects(struct bnx2x *bp); | ||
| 1421 | |||
| 1399 | #endif /* BNX2X_CMN_H */ | 1422 | #endif /* BNX2X_CMN_H */ |
| @@ -1364,11 +1364,27 @@ static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, · 1363 unmodified lines | |||
| 1364 | return rc; | 1364 | return rc; |
| 1365 | } | 1365 | } |
| 1366 | 1366 | ||
| 1367 | static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, | ||
| 1368 | int buf_size) | ||
| 1369 | { | ||
| 1370 | int rc; | ||
| 1371 | |||
| 1372 | rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); | ||
| 1373 | |||
| 1374 | if (!rc) { | ||
| 1375 | __be32 *be = (__be32 *)buf; | ||
| 1376 | |||
| 1377 | while ((buf_size -= 4) >= 0) | ||
| 1378 | *buf++ = be32_to_cpu(*be++); | ||
| 1379 | } | ||
| 1380 | |||
| 1381 | return rc; | ||
| 1382 | } | ||
| 1383 | |||
| 1367 | static int bnx2x_get_eeprom(struct net_device *dev, | 1384 | static int bnx2x_get_eeprom(struct net_device *dev, |
| 1368 | struct ethtool_eeprom *eeprom, u8 *eebuf) | 1385 | struct ethtool_eeprom *eeprom, u8 *eebuf) |
| 1369 | { | 1386 | { |
| 1370 | struct bnx2x *bp = netdev_priv(dev); | 1387 | struct bnx2x *bp = netdev_priv(dev); |
| 1371 | int rc; | ||
| 1372 | 1388 | ||
| 1373 | if (!netif_running(dev)) { | 1389 | if (!netif_running(dev)) { |
| 1374 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | 1390 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
| @@ -1383,9 +1399,7 @@ static int bnx2x_get_eeprom(struct net_device *dev, · 8 unmodified lines | |||
| 1383 | 1399 | ||
| 1384 | /* parameters already validated in ethtool_get_eeprom */ | 1400 | /* parameters already validated in ethtool_get_eeprom */ |
| 1385 | 1401 | ||
| 1386 | rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); | 1402 | return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); |
| 1387 | |||
| 1388 | return rc; | ||
| 1389 | } | 1403 | } |
| 1390 | 1404 | ||
| 1391 | static int bnx2x_get_module_eeprom(struct net_device *dev, | 1405 | static int bnx2x_get_module_eeprom(struct net_device *dev, |
| @@ -1393,10 +1407,9 @@ static int bnx2x_get_module_eeprom(struct net_device *dev, · 1 unmodified line | |||
| 1393 | u8 *data) | 1407 | u8 *data) |
| 1394 | { | 1408 | { |
| 1395 | struct bnx2x *bp = netdev_priv(dev); | 1409 | struct bnx2x *bp = netdev_priv(dev); |
| 1396 | int rc = 0, phy_idx; | 1410 | int rc = -EINVAL, phy_idx; |
| 1397 | u8 *user_data = data; | 1411 | u8 *user_data = data; |
| 1398 | int remaining_len = ee->len, xfer_size; | 1412 | unsigned int start_addr = ee->offset, xfer_size = 0; |
| 1399 | unsigned int page_off = ee->offset; | ||
| 1400 | 1413 | ||
| 1401 | if (!netif_running(dev)) { | 1414 | if (!netif_running(dev)) { |
| 1402 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | 1415 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
| @@ -1405,21 +1418,52 @@ static int bnx2x_get_module_eeprom(struct net_device *dev, · 2 unmodified lines | |||
| 1405 | } | 1418 | } |
| 1406 | 1419 | ||
| 1407 | phy_idx = bnx2x_get_cur_phy_idx(bp); | 1420 | phy_idx = bnx2x_get_cur_phy_idx(bp); |
| 1408 | bnx2x_acquire_phy_lock(bp); | 1421 | |
| 1409 | while (!rc && remaining_len > 0) { | 1422 | /* Read A0 section */ |
| 1410 | xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ? | 1423 | if (start_addr < ETH_MODULE_SFF_8079_LEN) { |
| 1411 | SFP_EEPROM_PAGE_SIZE : remaining_len; | 1424 | /* Limit transfer size to the A0 section boundary */ |
| 1425 | if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) | ||
| 1426 | xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; | ||
| 1427 | else | ||
| 1428 | xfer_size = ee->len; | ||
| 1429 | bnx2x_acquire_phy_lock(bp); | ||
| 1412 | rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], | 1430 | rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], |
| 1413 | &bp->link_params, | 1431 | &bp->link_params, |
| 1414 | page_off, | 1432 | I2C_DEV_ADDR_A0, |
| 1433 | start_addr, | ||
| 1415 | xfer_size, | 1434 | xfer_size, |
| 1416 | user_data); | 1435 | user_data); |
| 1417 | remaining_len -= xfer_size; | 1436 | bnx2x_release_phy_lock(bp); |
| 1437 | if (rc) { | ||
| 1438 | DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); | ||
| 1439 | |||
| 1440 | return -EINVAL; | ||
| 1441 | } | ||
| 1418 | user_data += xfer_size; | 1442 | user_data += xfer_size; |
| 1419 | page_off += xfer_size; | 1443 | start_addr += xfer_size; |
| 1420 | } | 1444 | } |
| 1421 | 1445 | ||
| 1422 | bnx2x_release_phy_lock(bp); | 1446 | /* Read A2 section */ |
| 1447 | if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && | ||
| 1448 | (start_addr < ETH_MODULE_SFF_8472_LEN)) { | ||
| 1449 | xfer_size = ee->len - xfer_size; | ||
| 1450 | /* Limit transfer size to the A2 section boundary */ | ||
| 1451 | if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) | ||
| 1452 | xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; | ||
| 1453 | start_addr -= ETH_MODULE_SFF_8079_LEN; | ||
| 1454 | bnx2x_acquire_phy_lock(bp); | ||
| 1455 | rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], | ||
| 1456 | &bp->link_params, | ||
| 1457 | I2C_DEV_ADDR_A2, | ||
| 1458 | start_addr, | ||
| 1459 | xfer_size, | ||
| 1460 | user_data); | ||
| 1461 | bnx2x_release_phy_lock(bp); | ||
| 1462 | if (rc) { | ||
| 1463 | DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); | ||
| 1464 | return -EINVAL; | ||
| 1465 | } | ||
| 1466 | } | ||
| 1423 | return rc; | 1467 | return rc; |
| 1424 | } | 1468 | } |
| 1425 | 1469 | ||
| @@ -1427,24 +1471,50 @@ static int bnx2x_get_module_info(struct net_device *dev, · 1 unmodified line | |||
| 1427 | struct ethtool_modinfo *modinfo) | 1471 | struct ethtool_modinfo *modinfo) |
| 1428 | { | 1472 | { |
| 1429 | struct bnx2x *bp = netdev_priv(dev); | 1473 | struct bnx2x *bp = netdev_priv(dev); |
| 1430 | int phy_idx; | 1474 | int phy_idx, rc; |
| 1475 | u8 sff8472_comp, diag_type; | ||
| 1476 | |||
| 1431 | if (!netif_running(dev)) { | 1477 | if (!netif_running(dev)) { |
| 1432 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | 1478 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
| 1433 | "cannot access eeprom when the interface is down\n"); | 1479 | "cannot access eeprom when the interface is down\n"); |
| 1434 | return -EAGAIN; | 1480 | return -EAGAIN; |
| 1435 | } | 1481 | } |
| 1436 | |||
| 1437 | phy_idx = bnx2x_get_cur_phy_idx(bp); | 1482 | phy_idx = bnx2x_get_cur_phy_idx(bp); |
| 1438 | switch (bp->link_params.phy[phy_idx].media_type) { | 1483 | bnx2x_acquire_phy_lock(bp); |
| 1439 | case ETH_PHY_SFPP_10G_FIBER: | 1484 | rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], |
| 1440 | case ETH_PHY_SFP_1G_FIBER: | 1485 | &bp->link_params, |
| 1441 | case ETH_PHY_DA_TWINAX: | 1486 | I2C_DEV_ADDR_A0, |
| 1487 | SFP_EEPROM_SFF_8472_COMP_ADDR, | ||
| 1488 | SFP_EEPROM_SFF_8472_COMP_SIZE, | ||
| 1489 | &sff8472_comp); | ||
| 1490 | bnx2x_release_phy_lock(bp); | ||
| 1491 | if (rc) { | ||
| 1492 | DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); | ||
| 1493 | return -EINVAL; | ||
| 1494 | } | ||
| 1495 | |||
| 1496 | bnx2x_acquire_phy_lock(bp); | ||
| 1497 | rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], | ||
| 1498 | &bp->link_params, | ||
| 1499 | I2C_DEV_ADDR_A0, | ||
| 1500 | SFP_EEPROM_DIAG_TYPE_ADDR, | ||
| 1501 | SFP_EEPROM_DIAG_TYPE_SIZE, | ||
| 1502 | &diag_type); | ||
| 1503 | bnx2x_release_phy_lock(bp); | ||
| 1504 | if (rc) { | ||
| 1505 | DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); | ||
| 1506 | return -EINVAL; | ||
| 1507 | } | ||
| 1508 | |||
| 1509 | if (!sff8472_comp || | ||
| 1510 | (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { | ||
| 1442 | modinfo->type = ETH_MODULE_SFF_8079; | 1511 | modinfo->type = ETH_MODULE_SFF_8079; |
| 1443 | modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; | 1512 | modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; |
| 1444 | return 0; | 1513 | } else { |
| 1445 | default: | 1514 | modinfo->type = ETH_MODULE_SFF_8472; |
| 1446 | return -EOPNOTSUPP; | 1515 | modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; |
| 1447 | } | 1516 | } |
| 1517 | return 0; | ||
| 1448 | } | 1518 | } |
| 1449 | 1519 | ||
| 1450 | static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, | 1520 | static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, |
| @@ -1496,9 +1566,8 @@ static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, · 45 unmodified lines | |||
| 1496 | int buf_size) | 1566 | int buf_size) |
| 1497 | { | 1567 | { |
| 1498 | int rc; | 1568 | int rc; |
| 1499 | u32 cmd_flags; | 1569 | u32 cmd_flags, align_offset, val; |
| 1500 | u32 align_offset; | 1570 | __be32 val_be; |
| 1501 | __be32 val; | ||
| 1502 | 1571 | ||
| 1503 | if (offset + buf_size > bp->common.flash_size) { | 1572 | if (offset + buf_size > bp->common.flash_size) { |
| 1504 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | 1573 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
| @@ -1517,16 +1586,16 @@ static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, · 12 unmodified lines | |||
| 1517 | 1586 | ||
| 1518 | cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); | 1587 | cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); |
| 1519 | align_offset = (offset & ~0x03); | 1588 | align_offset = (offset & ~0x03); |
| 1520 | rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags); | 1589 | rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); |
| 1521 | 1590 | ||
| 1522 | if (rc == 0) { | 1591 | if (rc == 0) { |
| 1523 | val &= ~(0xff << BYTE_OFFSET(offset)); | ||
| 1524 | val |= (*data_buf << BYTE_OFFSET(offset)); | ||
| 1525 | |||
| 1526 | /* nvram data is returned as an array of bytes | 1592 | /* nvram data is returned as an array of bytes |
| 1527 | * convert it back to cpu order | 1593 | * convert it back to cpu order |
| 1528 | */ | 1594 | */ |
| 1529 | val = be32_to_cpu(val); | 1595 | val = be32_to_cpu(val_be); |
| 1596 | |||
| 1597 | val &= ~le32_to_cpu(0xff << BYTE_OFFSET(offset)); | ||
| 1598 | val |= le32_to_cpu(*data_buf << BYTE_OFFSET(offset)); | ||
| 1530 | 1599 | ||
| 1531 | rc = bnx2x_nvram_write_dword(bp, align_offset, val, | 1600 | rc = bnx2x_nvram_write_dword(bp, align_offset, val, |
| 1532 | cmd_flags); | 1601 | cmd_flags); |
| @@ -1820,12 +1889,15 @@ static int bnx2x_set_pauseparam(struct net_device *dev, · 287 unmodified lines | |||
| 1820 | bp->link_params.req_flow_ctrl[cfg_idx] = | 1889 | bp->link_params.req_flow_ctrl[cfg_idx] = |
| 1821 | BNX2X_FLOW_CTRL_AUTO; | 1890 | BNX2X_FLOW_CTRL_AUTO; |
| 1822 | } | 1891 | } |
| 1823 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE; | 1892 | bp->link_params.req_fc_auto_adv = 0; |
| 1824 | if (epause->rx_pause) | 1893 | if (epause->rx_pause) |
| 1825 | bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; | 1894 | bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; |
| 1826 | 1895 | ||
| 1827 | if (epause->tx_pause) | 1896 | if (epause->tx_pause) |
| 1828 | bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; | 1897 | bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; |
| 1898 | |||
| 1899 | if (!bp->link_params.req_fc_auto_adv) | ||
| 1900 | bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; | ||
| 1829 | } | 1901 | } |
| 1830 | 1902 | ||
| 1831 | DP(BNX2X_MSG_ETHTOOL, | 1903 | DP(BNX2X_MSG_ETHTOOL, |
| @@ -2526,14 +2598,168 @@ static int bnx2x_test_ext_loopback(struct bnx2x *bp) · 694 unmodified lines | |||
| 2526 | return rc; | 2598 | return rc; |
| 2527 | } | 2599 | } |
| 2528 | 2600 | ||
| 2601 | struct code_entry { | ||
| 2602 | u32 sram_start_addr; | ||
| 2603 | u32 code_attribute; | ||
| 2604 | #define CODE_IMAGE_TYPE_MASK 0xf0800003 | ||
| 2605 | #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 | ||
| 2606 | #define CODE_IMAGE_LENGTH_MASK 0x007ffffc | ||
| 2607 | #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 | ||
| 2608 | u32 nvm_start_addr; | ||
| 2609 | }; | ||
| 2610 | |||
| 2611 | #define CODE_ENTRY_MAX 16 | ||
| 2612 | #define CODE_ENTRY_EXTENDED_DIR_IDX 15 | ||
| 2613 | #define MAX_IMAGES_IN_EXTENDED_DIR 64 | ||
| 2614 | #define NVRAM_DIR_OFFSET 0x14 | ||
| 2615 | |||
| 2616 | #define EXTENDED_DIR_EXISTS(code) \ | ||
| 2617 | ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ | ||
| 2618 | (code & CODE_IMAGE_LENGTH_MASK) != 0) | ||
| 2619 | |||
| 2529 | #define CRC32_RESIDUAL 0xdebb20e3 | 2620 | #define CRC32_RESIDUAL 0xdebb20e3 |
| 2621 | #define CRC_BUFF_SIZE 256 | ||
| 2622 | |||
| 2623 | static int bnx2x_nvram_crc(struct bnx2x *bp, | ||
| 2624 | int offset, | ||
| 2625 | int size, | ||
| 2626 | u8 *buff) | ||
| 2627 | { | ||
| 2628 | u32 crc = ~0; | ||
| 2629 | int rc = 0, done = 0; | ||
| 2630 | |||
| 2631 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | ||
| 2632 | "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); | ||
| 2633 | |||
| 2634 | while (done < size) { | ||
| 2635 | int count = min_t(int, size - done, CRC_BUFF_SIZE); | ||
| 2636 | |||
| 2637 | rc = bnx2x_nvram_read(bp, offset + done, buff, count); | ||
| 2638 | |||
| 2639 | if (rc) | ||
| 2640 | return rc; | ||
| 2641 | |||
| 2642 | crc = crc32_le(crc, buff, count); | ||
| 2643 | done += count; | ||
| 2644 | } | ||
| 2645 | |||
| 2646 | if (crc != CRC32_RESIDUAL) | ||
| 2647 | rc = -EINVAL; | ||
| 2648 | |||
| 2649 | return rc; | ||
| 2650 | } | ||
| 2651 | |||
| 2652 | static int bnx2x_test_nvram_dir(struct bnx2x *bp, | ||
| 2653 | struct code_entry *entry, | ||
| 2654 | u8 *buff) | ||
| 2655 | { | ||
| 2656 | size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; | ||
| 2657 | u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; | ||
| 2658 | int rc; | ||
| 2659 | |||
| 2660 | /* Zero-length images and AFEX profiles do not have CRC */ | ||
| 2661 | if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) | ||
| 2662 | return 0; | ||
| 2663 | |||
| 2664 | rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); | ||
| 2665 | if (rc) | ||
| 2666 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | ||
| 2667 | "image %x has failed crc test (rc %d)\n", type, rc); | ||
| 2668 | |||
| 2669 | return rc; | ||
| 2670 | } | ||
| 2671 | |||
| 2672 | static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) | ||
| 2673 | { | ||
| 2674 | int rc; | ||
| 2675 | struct code_entry entry; | ||
| 2676 | |||
| 2677 | rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); | ||
| 2678 | if (rc) | ||
| 2679 | return rc; | ||
| 2680 | |||
| 2681 | return bnx2x_test_nvram_dir(bp, &entry, buff); | ||
| 2682 | } | ||
| 2683 | |||
| 2684 | static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) | ||
| 2685 | { | ||
| 2686 | u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; | ||
| 2687 | struct code_entry entry; | ||
| 2688 | int i; | ||
| 2689 | |||
| 2690 | rc = bnx2x_nvram_read32(bp, | ||
| 2691 | dir_offset + | ||
| 2692 | sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, | ||
| 2693 | (u32 *)&entry, sizeof(entry)); | ||
| 2694 | if (rc) | ||
| 2695 | return rc; | ||
| 2696 | |||
| 2697 | if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) | ||
| 2698 | return 0; | ||
| 2699 | |||
| 2700 | rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, | ||
| 2701 | &cnt, sizeof(u32)); | ||
| 2702 | if (rc) | ||
| 2703 | return rc; | ||
| 2704 | |||
| 2705 | dir_offset = entry.nvm_start_addr + 8; | ||
| 2706 | |||
| 2707 | for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { | ||
| 2708 | rc = bnx2x_test_dir_entry(bp, dir_offset + | ||
| 2709 | sizeof(struct code_entry) * i, | ||
| 2710 | buff); | ||
| 2711 | if (rc) | ||
| 2712 | return rc; | ||
| 2713 | } | ||
| 2714 | |||
| 2715 | return 0; | ||
| 2716 | } | ||
| 2717 | |||
| 2718 | static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) | ||
| 2719 | { | ||
| 2720 | u32 rc, dir_offset = NVRAM_DIR_OFFSET; | ||
| 2721 | int i; | ||
| 2722 | |||
| 2723 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); | ||
| 2724 | |||
| 2725 | for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { | ||
| 2726 | rc = bnx2x_test_dir_entry(bp, dir_offset + | ||
| 2727 | sizeof(struct code_entry) * i, | ||
| 2728 | buff); | ||
| 2729 | if (rc) | ||
| 2730 | return rc; | ||
| 2731 | } | ||
| 2732 | |||
| 2733 | return bnx2x_test_nvram_ext_dirs(bp, buff); | ||
| 2734 | } | ||
| 2735 | |||
| 2736 | struct crc_pair { | ||
| 2737 | int offset; | ||
| 2738 | int size; | ||
| 2739 | }; | ||
| 2740 | |||
| 2741 | static int bnx2x_test_nvram_tbl(struct bnx2x *bp, | ||
| 2742 | const struct crc_pair *nvram_tbl, u8 *buf) | ||
| 2743 | { | ||
| 2744 | int i; | ||
| 2745 | |||
| 2746 | for (i = 0; nvram_tbl[i].size; i++) { | ||
| 2747 | int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, | ||
| 2748 | nvram_tbl[i].size, buf); | ||
| 2749 | if (rc) { | ||
| 2750 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | ||
| 2751 | "nvram_tbl[%d] has failed crc test (rc %d)\n", | ||
| 2752 | i, rc); | ||
| 2753 | return rc; | ||
| 2754 | } | ||
| 2755 | } | ||
| 2756 | |||
| 2757 | return 0; | ||
| 2758 | } | ||
| 2530 | 2759 | ||
| 2531 | static int bnx2x_test_nvram(struct bnx2x *bp) | 2760 | static int bnx2x_test_nvram(struct bnx2x *bp) |
| 2532 | { | 2761 | { |
| 2533 | static const struct { | 2762 | const struct crc_pair nvram_tbl[] = { |
| 2534 | int offset; | ||
| 2535 | int size; | ||
| 2536 | } nvram_tbl[] = { | ||
| 2537 | { 0, 0x14 }, /* bootstrap */ | 2763 | { 0, 0x14 }, /* bootstrap */ |
| 2538 | { 0x14, 0xec }, /* dir */ | 2764 | { 0x14, 0xec }, /* dir */ |
| 2539 | { 0x100, 0x350 }, /* manuf_info */ | 2765 | { 0x100, 0x350 }, /* manuf_info */ |
| @@ -2542,30 +2768,33 @@ static int bnx2x_test_nvram(struct bnx2x *bp) · 2 unmodified lines | |||
| 2542 | { 0x708, 0x70 }, /* manuf_key_info */ | 2768 | { 0x708, 0x70 }, /* manuf_key_info */ |
| 2543 | { 0, 0 } | 2769 | { 0, 0 } |
| 2544 | }; | 2770 | }; |
| 2545 | __be32 *buf; | 2771 | const struct crc_pair nvram_tbl2[] = { |
| 2546 | u8 *data; | 2772 | { 0x7e8, 0x350 }, /* manuf_info2 */ |
| 2547 | int i, rc; | 2773 | { 0xb38, 0xf0 }, /* feature_info */ |
| 2548 | u32 magic, crc; | 2774 | { 0, 0 } |
| 2775 | }; | ||
| 2776 | |||
| 2777 | u8 *buf; | ||
| 2778 | int rc; | ||
| 2779 | u32 magic; | ||
| 2549 | 2780 | ||
| 2550 | if (BP_NOMCP(bp)) | 2781 | if (BP_NOMCP(bp)) |
| 2551 | return 0; | 2782 | return 0; |
| 2552 | 2783 | ||
| 2553 | buf = kmalloc(0x350, GFP_KERNEL); | 2784 | buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); |
| 2554 | if (!buf) { | 2785 | if (!buf) { |
| 2555 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); | 2786 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); |
| 2556 | rc = -ENOMEM; | 2787 | rc = -ENOMEM; |
| 2557 | goto test_nvram_exit; | 2788 | goto test_nvram_exit; |
| 2558 | } | 2789 | } |
| 2559 | data = (u8 *)buf; | ||
| 2560 | 2790 | ||
| 2561 | rc = bnx2x_nvram_read(bp, 0, data, 4); | 2791 | rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); |
| 2562 | if (rc) { | 2792 | if (rc) { |
| 2563 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | 2793 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
| 2564 | "magic value read (rc %d)\n", rc); | 2794 | "magic value read (rc %d)\n", rc); |
| 2565 | goto test_nvram_exit; | 2795 | goto test_nvram_exit; |
| 2566 | } | 2796 | } |
| 2567 | 2797 | ||
| 2568 | magic = be32_to_cpu(buf[0]); | ||
| 2569 | if (magic != 0x669955aa) { | 2798 | if (magic != 0x669955aa) { |
| 2570 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | 2799 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
| 2571 | "wrong magic value (0x%08x)\n", magic); | 2800 | "wrong magic value (0x%08x)\n", magic); |
| @@ -2573,25 +2802,26 @@ static int bnx2x_test_nvram(struct bnx2x *bp) · 1 unmodified line | |||
| 2573 | goto test_nvram_exit; | 2802 | goto test_nvram_exit; |
| 2574 | } | 2803 | } |
| 2575 | 2804 | ||
| 2576 | for (i = 0; nvram_tbl[i].size; i++) { | 2805 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); |
| 2806 | rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); | ||
| 2807 | if (rc) | ||
| 2808 | goto test_nvram_exit; | ||
| 2577 | 2809 | ||
| 2578 | rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, | 2810 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { |
| 2579 | nvram_tbl[i].size); | 2811 | u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
| 2580 | if (rc) { | 2812 | SHARED_HW_CFG_HIDE_PORT1; |
| 2581 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | ||
| 2582 | "nvram_tbl[%d] read data (rc %d)\n", i, rc); | ||
| 2583 | goto test_nvram_exit; | ||
| 2584 | } | ||
| 2585 | 2813 | ||
| 2586 | crc = ether_crc_le(nvram_tbl[i].size, data); | 2814 | if (!hide) { |
| 2587 | if (crc != CRC32_RESIDUAL) { | ||
| 2588 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | 2815 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
| 2589 | "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc); | 2816 | "Port 1 CRC test-set\n"); |
| 2590 | rc = -ENODEV; | 2817 | rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); |
| 2591 | goto test_nvram_exit; | 2818 | if (rc) |
| 2819 | goto test_nvram_exit; | ||
| 2592 | } | 2820 | } |
| 2593 | } | 2821 | } |
| 2594 | 2822 | ||
| 2823 | rc = bnx2x_test_nvram_dirs(bp, buf); | ||
| 2824 | |||
| 2595 | test_nvram_exit: | 2825 | test_nvram_exit: |
| 2596 | kfree(buf); | 2826 | kfree(buf); |
| 2597 | return rc; | 2827 | return rc; |
| @@ -3232,7 +3462,32 @@ static const struct ethtool_ops bnx2x_ethtool_ops = { · 634 unmodified lines | |||
| 3232 | .get_ts_info = ethtool_op_get_ts_info, | 3462 | .get_ts_info = ethtool_op_get_ts_info, |
| 3233 | }; | 3463 | }; |
| 3234 | 3464 | ||
| 3235 | void bnx2x_set_ethtool_ops(struct net_device *netdev) | 3465 | static const struct ethtool_ops bnx2x_vf_ethtool_ops = { |
| 3466 | .get_settings = bnx2x_get_settings, | ||
| 3467 | .set_settings = bnx2x_set_settings, | ||
| 3468 | .get_drvinfo = bnx2x_get_drvinfo, | ||
| 3469 | .get_msglevel = bnx2x_get_msglevel, | ||
| 3470 | .set_msglevel = bnx2x_set_msglevel, | ||
| 3471 | .get_link = bnx2x_get_link, | ||
| 3472 | .get_coalesce = bnx2x_get_coalesce, | ||
| 3473 | .get_ringparam = bnx2x_get_ringparam, | ||
| 3474 | .set_ringparam = bnx2x_set_ringparam, | ||
| 3475 | .get_sset_count = bnx2x_get_sset_count, | ||
| 3476 | .get_strings = bnx2x_get_strings, | ||
| 3477 | .get_ethtool_stats = bnx2x_get_ethtool_stats, | ||
| 3478 | .get_rxnfc = bnx2x_get_rxnfc, | ||
| 3479 | .set_rxnfc = bnx2x_set_rxnfc, | ||
| 3480 | .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, | ||
| 3481 | .get_rxfh_indir = bnx2x_get_rxfh_indir, | ||
| 3482 | .set_rxfh_indir = bnx2x_set_rxfh_indir, | ||
| 3483 | .get_channels = bnx2x_get_channels, | ||
| 3484 | .set_channels = bnx2x_set_channels, | ||
| 3485 | }; | ||
| 3486 | |||
| 3487 | void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) | ||
| 3236 | { | 3488 | { |
| 3237 | SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); | 3489 | if (IS_PF(bp)) |
| 3490 | SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); | ||
| 3491 | else /* vf */ | ||
| 3492 | SET_ETHTOOL_OPS(netdev, &bnx2x_vf_ethtool_ops); | ||
| 3238 | } | 3493 | } |
| @@ -30,31 +30,31 @@ · 29 unmodified lines | |||
| 30 | * IRO[138].m2) + ((sbId) * IRO[138].m3)) | 30 | * IRO[138].m2) + ((sbId) * IRO[138].m3)) |
| 31 | #define CSTORM_IGU_MODE_OFFSET (IRO[157].base) | 31 | #define CSTORM_IGU_MODE_OFFSET (IRO[157].base) |
| 32 | #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ | 32 | #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ |
| 33 | (IRO[316].base + ((pfId) * IRO[316].m1)) | ||
| 34 | #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ | ||
| 35 | (IRO[317].base + ((pfId) * IRO[317].m1)) | 33 | (IRO[317].base + ((pfId) * IRO[317].m1)) |
| 34 | #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ | ||
| 35 | (IRO[318].base + ((pfId) * IRO[318].m1)) | ||
| 36 | #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ | 36 | #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ |
| 37 | (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2)) | 37 | (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2)) |
| 38 | #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ | 38 | #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ |
| 39 | (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2)) | 39 | (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2)) |
| 40 | #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ | 40 | #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ |
| 41 | (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2)) | 41 | (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2)) |
| 42 | #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ | 42 | #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ |
| 43 | (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2)) | 43 | (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2)) |
| 44 | #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ | 44 | #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ |
| 45 | (IRO[308].base + ((pfId) * IRO[308].m1) + ((iscsiEqId) * IRO[308].m2)) | 45 | (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2)) |
| 46 | #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \ | 46 | #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \ |
| 47 | (IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2)) | 47 | (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2)) |
| 48 | #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ | 48 | #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ |
| 49 | (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2)) | 49 | (IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2)) |
| 50 | #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ | 50 | #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ |
| 51 | (IRO[315].base + ((pfId) * IRO[315].m1)) | 51 | (IRO[316].base + ((pfId) * IRO[316].m1)) |
| 52 | #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ | 52 | #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ |
| 53 | (IRO[307].base + ((pfId) * IRO[307].m1)) | 53 | (IRO[308].base + ((pfId) * IRO[308].m1)) |
| 54 | #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ | 54 | #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ |
| 55 | (IRO[306].base + ((pfId) * IRO[306].m1)) | 55 | (IRO[307].base + ((pfId) * IRO[307].m1)) |
| 56 | #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ | 56 | #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ |
| 57 | (IRO[305].base + ((pfId) * IRO[305].m1)) | 57 | (IRO[306].base + ((pfId) * IRO[306].m1)) |
| 58 | #define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ | 58 | #define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ |
| 59 | (IRO[151].base + ((funcId) * IRO[151].m1)) | 59 | (IRO[151].base + ((funcId) * IRO[151].m1)) |
| 60 | #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ | 60 | #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ |
| @@ -114,7 +114,7 @@ · 53 unmodified lines | |||
| 114 | #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ | 114 | #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ |
| 115 | (IRO[268].base + ((pfId) * IRO[268].m1)) | 115 | (IRO[268].base + ((pfId) * IRO[268].m1)) |
| 116 | #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ | 116 | #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ |
| 117 | (IRO[277].base + ((pfId) * IRO[277].m1)) | 117 | (IRO[278].base + ((pfId) * IRO[278].m1)) |
| 118 | #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ | 118 | #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ |
| 119 | (IRO[264].base + ((pfId) * IRO[264].m1)) | 119 | (IRO[264].base + ((pfId) * IRO[264].m1)) |
| 120 | #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ | 120 | #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ |
| @@ -136,35 +136,32 @@ · 15 unmodified lines | |||
| 136 | #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base) | 136 | #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base) |
| 137 | #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \ | 137 | #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \ |
| 138 | (IRO[176].base + ((assertListEntry) * IRO[176].m1)) | 138 | (IRO[176].base + ((assertListEntry) * IRO[176].m1)) |
| 139 | #define USTORM_CQE_PAGE_NEXT_OFFSET(portId, clientId) \ | ||
| 140 | (IRO[205].base + ((portId) * IRO[205].m1) + ((clientId) * \ | ||
| 141 | IRO[205].m2)) | ||
| 142 | #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ | 139 | #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ |
| 143 | (IRO[183].base + ((portId) * IRO[183].m1)) | 140 | (IRO[183].base + ((portId) * IRO[183].m1)) |
| 144 | #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ | 141 | #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ |
| 145 | (IRO[318].base + ((pfId) * IRO[318].m1)) | 142 | (IRO[319].base + ((pfId) * IRO[319].m1)) |
| 146 | #define USTORM_FUNC_EN_OFFSET(funcId) \ | 143 | #define USTORM_FUNC_EN_OFFSET(funcId) \ |
| 147 | (IRO[178].base + ((funcId) * IRO[178].m1)) | 144 | (IRO[178].base + ((funcId) * IRO[178].m1)) |
| 148 | #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ | 145 | #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ |
| 149 | (IRO[282].base + ((pfId) * IRO[282].m1)) | ||
| 150 | #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ | ||
| 151 | (IRO[283].base + ((pfId) * IRO[283].m1)) | 146 | (IRO[283].base + ((pfId) * IRO[283].m1)) |
| 147 | #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ | ||
| 148 | (IRO[284].base + ((pfId) * IRO[284].m1)) | ||
| 152 | #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ | 149 | #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ |
| 153 | (IRO[287].base + ((pfId) * IRO[287].m1)) | 150 | (IRO[288].base + ((pfId) * IRO[288].m1)) |
| 154 | #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ | 151 | #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ |
| 155 | (IRO[284].base + ((pfId) * IRO[284].m1)) | 152 | (IRO[285].base + ((pfId) * IRO[285].m1)) |
| 156 | #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ | 153 | #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ |
| 157 | (IRO[280].base + ((pfId) * IRO[280].m1)) | 154 | (IRO[281].base + ((pfId) * IRO[281].m1)) |
| 158 | #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ | 155 | #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ |
| 159 | (IRO[279].base + ((pfId) * IRO[279].m1)) | 156 | (IRO[280].base + ((pfId) * IRO[280].m1)) |
| 160 | #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ | 157 | #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ |
| 161 | (IRO[278].base + ((pfId) * IRO[278].m1)) | 158 | (IRO[279].base + ((pfId) * IRO[279].m1)) |
| 162 | #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ | 159 | #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ |
| 163 | (IRO[281].base + ((pfId) * IRO[281].m1)) | 160 | (IRO[282].base + ((pfId) * IRO[282].m1)) |
| 164 | #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ | 161 | #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ |
| 165 | (IRO[285].base + ((pfId) * IRO[285].m1)) | ||
| 166 | #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ | ||
| 167 | (IRO[286].base + ((pfId) * IRO[286].m1)) | 162 | (IRO[286].base + ((pfId) * IRO[286].m1)) |
| 163 | #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ | ||
| 164 | (IRO[287].base + ((pfId) * IRO[287].m1)) | ||
| 168 | #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ | 165 | #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ |
| 169 | (IRO[182].base + ((pfId) * IRO[182].m1)) | 166 | (IRO[182].base + ((pfId) * IRO[182].m1)) |
| 170 | #define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ | 167 | #define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ |
| @@ -190,39 +187,39 @@ · 19 unmodified lines | |||
| 190 | #define XSTORM_FUNC_EN_OFFSET(funcId) \ | 187 | #define XSTORM_FUNC_EN_OFFSET(funcId) \ |
| 191 | (IRO[47].base + ((funcId) * IRO[47].m1)) | 188 | (IRO[47].base + ((funcId) * IRO[47].m1)) |
| 192 | #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ | 189 | #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ |
| 193 | (IRO[295].base + ((pfId) * IRO[295].m1)) | 190 | (IRO[296].base + ((pfId) * IRO[296].m1)) |
| 194 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ | 191 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ |
| 195 | (IRO[298].base + ((pfId) * IRO[298].m1)) | ||
| 196 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \ | ||
| 197 | (IRO[299].base + ((pfId) * IRO[299].m1)) | 192 | (IRO[299].base + ((pfId) * IRO[299].m1)) |
| 198 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ | 193 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \ |
| 199 | (IRO[300].base + ((pfId) * IRO[300].m1)) | 194 | (IRO[300].base + ((pfId) * IRO[300].m1)) |
| 200 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ | 195 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ |
| 201 | (IRO[301].base + ((pfId) * IRO[301].m1)) | 196 | (IRO[301].base + ((pfId) * IRO[301].m1)) |
| 202 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ | 197 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ |
| 203 | (IRO[302].base + ((pfId) * IRO[302].m1)) | 198 | (IRO[302].base + ((pfId) * IRO[302].m1)) |
| 204 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ | 199 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ |
| 205 | (IRO[303].base + ((pfId) * IRO[303].m1)) | 200 | (IRO[303].base + ((pfId) * IRO[303].m1)) |
| 206 | #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ | 201 | #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ |
| 207 | (IRO[304].base + ((pfId) * IRO[304].m1)) | 202 | (IRO[304].base + ((pfId) * IRO[304].m1)) |
| 203 | #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ | ||
| 204 | (IRO[305].base + ((pfId) * IRO[305].m1)) | ||
| 208 | #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ | 205 | #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ |
| 209 | (IRO[294].base + ((pfId) * IRO[294].m1)) | 206 | (IRO[295].base + ((pfId) * IRO[295].m1)) |
| 210 | #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ | 207 | #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ |
| 211 | (IRO[293].base + ((pfId) * IRO[293].m1)) | 208 | (IRO[294].base + ((pfId) * IRO[294].m1)) |
| 212 | #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ | 209 | #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ |
| 213 | (IRO[292].base + ((pfId) * IRO[292].m1)) | 210 | (IRO[293].base + ((pfId) * IRO[293].m1)) |
| 214 | #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ | 211 | #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ |
| 215 | (IRO[297].base + ((pfId) * IRO[297].m1)) | 212 | (IRO[298].base + ((pfId) * IRO[298].m1)) |
| 216 | #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ | 213 | #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ |
| 217 | (IRO[296].base + ((pfId) * IRO[296].m1)) | 214 | (IRO[297].base + ((pfId) * IRO[297].m1)) |
| 218 | #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ | 215 | #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ |
| 219 | (IRO[291].base + ((pfId) * IRO[291].m1)) | 216 | (IRO[292].base + ((pfId) * IRO[292].m1)) |
| 220 | #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ | 217 | #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ |
| 221 | (IRO[290].base + ((pfId) * IRO[290].m1)) | 218 | (IRO[291].base + ((pfId) * IRO[291].m1)) |
| 222 | #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ | 219 | #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ |
| 223 | (IRO[289].base + ((pfId) * IRO[289].m1)) | 220 | (IRO[290].base + ((pfId) * IRO[290].m1)) |
| 224 | #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ | 221 | #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ |
| 225 | (IRO[288].base + ((pfId) * IRO[288].m1)) | 222 | (IRO[289].base + ((pfId) * IRO[289].m1)) |
| 226 | #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ | 223 | #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ |
| 227 | (IRO[44].base + ((pfId) * IRO[44].m1)) | 224 | (IRO[44].base + ((pfId) * IRO[44].m1)) |
| 228 | #define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ | 225 | #define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ |
| @@ -389,4 +386,8 @@ · 160 unmodified lines | |||
| 389 | 386 | ||
| 390 | #define UNDEF_IRO 0x80000000 | 387 | #define UNDEF_IRO 0x80000000 |
| 391 | 388 | ||
| 389 | /* used for defining the amount of FCoE tasks supported for PF */ | ||
| 390 | #define MAX_FCOE_FUNCS_PER_ENGINE 2 | ||
| 391 | #define MAX_NUM_FCOE_TASKS_PER_ENGINE 4096 | ||
| 392 | |||
| 392 | #endif /* BNX2X_FW_DEFS_H */ | 393 | #endif /* BNX2X_FW_DEFS_H */ |
| @@ -114,6 +114,10 @@ struct license_key { · 113 unmodified lines | |||
| 114 | #define EPIO_CFG_EPIO30 0x0000001f | 114 | #define EPIO_CFG_EPIO30 0x0000001f |
| 115 | #define EPIO_CFG_EPIO31 0x00000020 | 115 | #define EPIO_CFG_EPIO31 0x00000020 |
| 116 | 116 | ||
| 117 | struct mac_addr { | ||
| 118 | u32 upper; | ||
| 119 | u32 lower; | ||
| 120 | }; | ||
| 117 | 121 | ||
| 118 | struct shared_hw_cfg { /* NVRAM Offset */ | 122 | struct shared_hw_cfg { /* NVRAM Offset */ |
| 119 | /* Up to 16 bytes of NULL-terminated string */ | 123 | /* Up to 16 bytes of NULL-terminated string */ |
| @@ -508,7 +512,22 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ · 388 unmodified lines | |||
| 508 | #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 | 512 | #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 |
| 509 | #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 | 513 | #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 |
| 510 | 514 | ||
| 511 | u32 reserved0[6]; /* 0x178 */ | 515 | /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 |
| 516 | * LOM recommended and tested value is 0xBEB2. Using a different | ||
| 517 | * value means using a value not tested by BRCM | ||
| 518 | */ | ||
| 519 | u32 sfi_tap_values; /* 0x178 */ | ||
| 520 | #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF | ||
| 521 | #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 | ||
| 522 | |||
| 523 | /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested | ||
| 524 | * value is 0x2. LOM recommended and tested value is 0x2. Using a | ||
| 525 | * different value means using a value not tested by BRCM | ||
| 526 | */ | ||
| 527 | #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 | ||
| 528 | #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 | ||
| 529 | |||
| 530 | u32 reserved0[5]; /* 0x17c */ | ||
| 512 | 531 | ||
| 513 | u32 aeu_int_mask; /* 0x190 */ | 532 | u32 aeu_int_mask; /* 0x190 */ |
| 514 | 533 | ||
| @@ -2821,8 +2840,8 @@ struct afex_stats { · 2306 unmodified lines | |||
| 2821 | 2840 | ||
| 2822 | #define BCM_5710_FW_MAJOR_VERSION 7 | 2841 | #define BCM_5710_FW_MAJOR_VERSION 7 |
| 2823 | #define BCM_5710_FW_MINOR_VERSION 8 | 2842 | #define BCM_5710_FW_MINOR_VERSION 8 |
| 2824 | #define BCM_5710_FW_REVISION_VERSION 2 | 2843 | #define BCM_5710_FW_REVISION_VERSION 17 |
| 2825 | #define BCM_5710_FW_ENGINEERING_VERSION 0 | 2844 | #define BCM_5710_FW_ENGINEERING_VERSION 0 |
| 2826 | #define BCM_5710_FW_COMPILE_FLAGS 1 | 2845 | #define BCM_5710_FW_COMPILE_FLAGS 1 |
| 2827 | 2846 | ||
| 2828 | 2847 | ||
| @@ -3513,11 +3532,14 @@ struct client_init_tx_data { · 684 unmodified lines | |||
| 3513 | #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 | 3532 | #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 |
| 3514 | #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) | 3533 | #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) |
| 3515 | #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 | 3534 | #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 |
| 3516 | #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4) | 3535 | #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) |
| 3517 | #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4 | 3536 | #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 |
| 3518 | u8 default_vlan_flg; | 3537 | u8 default_vlan_flg; |
| 3519 | u8 force_default_pri_flg; | 3538 | u8 force_default_pri_flg; |
| 3520 | __le32 reserved3; | 3539 | u8 tunnel_lso_inc_ip_id; |
| 3540 | u8 refuse_outband_vlan_flg; | ||
| 3541 | u8 tunnel_non_lso_pcsum_location; | ||
| 3542 | u8 reserved1; | ||
| 3521 | }; | 3543 | }; |
| 3522 | 3544 | ||
| 3523 | /* | 3545 | /* |
| @@ -3551,6 +3573,11 @@ struct client_update_ramrod_data { · 27 unmodified lines | |||
| 3551 | __le16 silent_vlan_mask; | 3573 | __le16 silent_vlan_mask; |
| 3552 | u8 silent_vlan_removal_flg; | 3574 | u8 silent_vlan_removal_flg; |
| 3553 | u8 silent_vlan_change_flg; | 3575 | u8 silent_vlan_change_flg; |
| 3576 | u8 refuse_outband_vlan_flg; | ||
| 3577 | u8 refuse_outband_vlan_change_flg; | ||
| 3578 | u8 tx_switching_flg; | ||
| 3579 | u8 tx_switching_change_flg; | ||
| 3580 | __le32 reserved1; | ||
| 3554 | __le32 echo; | 3581 | __le32 echo; |
| 3555 | }; | 3582 | }; |
| 3556 | 3583 | ||
| @@ -3620,7 +3647,8 @@ struct eth_classify_header { · 63 unmodified lines | |||
| 3620 | */ | 3647 | */ |
| 3621 | struct eth_classify_mac_cmd { | 3648 | struct eth_classify_mac_cmd { |
| 3622 | struct eth_classify_cmd_header header; | 3649 | struct eth_classify_cmd_header header; |
| 3623 | __le32 reserved0; | 3650 | __le16 reserved0; |
| 3651 | __le16 inner_mac; | ||
| 3624 | __le16 mac_lsb; | 3652 | __le16 mac_lsb; |
| 3625 | __le16 mac_mid; | 3653 | __le16 mac_mid; |
| 3626 | __le16 mac_msb; | 3654 | __le16 mac_msb; |
| @@ -3633,7 +3661,8 @@ struct eth_classify_mac_cmd { · 6 unmodified lines | |||
| 3633 | */ | 3661 | */ |
| 3634 | struct eth_classify_pair_cmd { | 3662 | struct eth_classify_pair_cmd { |
| 3635 | struct eth_classify_cmd_header header; | 3663 | struct eth_classify_cmd_header header; |
| 3636 | __le32 reserved0; | 3664 | __le16 reserved0; |
| 3665 | __le16 inner_mac; | ||
| 3637 | __le16 mac_lsb; | 3666 | __le16 mac_lsb; |
| 3638 | __le16 mac_mid; | 3667 | __le16 mac_mid; |
| 3639 | __le16 mac_msb; | 3668 | __le16 mac_msb; |
| @@ -3855,8 +3884,68 @@ struct eth_halt_ramrod_data { · 215 unmodified lines | |||
| 3855 | 3884 | ||
| 3856 | 3885 | ||
| 3857 | /* | 3886 | /* |
| 3858 | * Command for setting multicast classification for a client | 3887 | * destination and source mac address. |
| 3888 | */ | ||
| 3889 | struct eth_mac_addresses { | ||
| 3890 | #if defined(__BIG_ENDIAN) | ||
| 3891 | __le16 dst_mid; | ||
| 3892 | __le16 dst_lo; | ||
| 3893 | #elif defined(__LITTLE_ENDIAN) | ||
| 3894 | __le16 dst_lo; | ||
| 3895 | __le16 dst_mid; | ||
| 3896 | #endif | ||
| 3897 | #if defined(__BIG_ENDIAN) | ||
| 3898 | __le16 src_lo; | ||
| 3899 | __le16 dst_hi; | ||
| 3900 | #elif defined(__LITTLE_ENDIAN) | ||
| 3901 | __le16 dst_hi; | ||
| 3902 | __le16 src_lo; | ||
| 3903 | #endif | ||
| 3904 | #if defined(__BIG_ENDIAN) | ||
| 3905 | __le16 src_hi; | ||
| 3906 | __le16 src_mid; | ||
| 3907 | #elif defined(__LITTLE_ENDIAN) | ||
| 3908 | __le16 src_mid; | ||
| 3909 | __le16 src_hi; | ||
| 3910 | #endif | ||
| 3911 | }; | ||
| 3912 | |||
| 3913 | /* tunneling related data */ | ||
| 3914 | struct eth_tunnel_data { | ||
| 3915 | #if defined(__BIG_ENDIAN) | ||
| 3916 | __le16 dst_mid; | ||
| 3917 | __le16 dst_lo; | ||
| 3918 | #elif defined(__LITTLE_ENDIAN) | ||
| 3919 | __le16 dst_lo; | ||
| 3920 | __le16 dst_mid; | ||
| 3921 | #endif | ||
| 3922 | #if defined(__BIG_ENDIAN) | ||
| 3923 | __le16 reserved0; | ||
| 3924 | __le16 dst_hi; | ||
| 3925 | #elif defined(__LITTLE_ENDIAN) | ||
| 3926 | __le16 dst_hi; | ||
| 3927 | __le16 reserved0; | ||
| 3928 | #endif | ||
| 3929 | #if defined(__BIG_ENDIAN) | ||
| 3930 | u8 reserved1; | ||
| 3931 | u8 ip_hdr_start_inner_w; | ||
| 3932 | __le16 pseudo_csum; | ||
| 3933 | #elif defined(__LITTLE_ENDIAN) | ||
| 3934 | __le16 pseudo_csum; | ||
| 3935 | u8 ip_hdr_start_inner_w; | ||
| 3936 | u8 reserved1; | ||
| 3937 | #endif | ||
| 3938 | }; | ||
| 3939 | |||
| 3940 | /* union for mac addresses and for tunneling data. | ||
| 3941 | * considered as tunneling data only if (tunnel_exist == 1). | ||
| 3859 | */ | 3942 | */ |
| 3943 | union eth_mac_addr_or_tunnel_data { | ||
| 3944 | struct eth_mac_addresses mac_addr; | ||
| 3945 | struct eth_tunnel_data tunnel_data; | ||
| 3946 | }; | ||
| 3947 | |||
| 3948 | /*Command for setting multicast classification for a client */ | ||
| 3860 | struct eth_multicast_rules_cmd { | 3949 | struct eth_multicast_rules_cmd { |
| 3861 | u8 cmd_general_data; | 3950 | u8 cmd_general_data; |
| 3862 | #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) | 3951 | #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) |
| @@ -3874,7 +3963,6 @@ struct eth_multicast_rules_cmd { · 11 unmodified lines | |||
| 3874 | struct regpair reserved3; | 3963 | struct regpair reserved3; |
| 3875 | }; | 3964 | }; |
| 3876 | 3965 | ||
| 3877 | |||
| 3878 | /* | 3966 | /* |
| 3879 | * parameters for multicast classification ramrod | 3967 | * parameters for multicast classification ramrod |
| 3880 | */ | 3968 | */ |
| @@ -3883,7 +3971,6 @@ struct eth_multicast_rules_ramrod_data { · 2 unmodified lines | |||
| 3883 | struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; | 3971 | struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; |
| 3884 | }; | 3972 | }; |
| 3885 | 3973 | ||
| 3886 | |||
| 3887 | /* | 3974 | /* |
| 3888 | * Place holder for ramrods protocol specific data | 3975 | * Place holder for ramrods protocol specific data |
| 3889 | */ | 3976 | */ |
| @@ -3947,11 +4034,14 @@ struct eth_rss_update_ramrod_data { · 57 unmodified lines | |||
| 3947 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 | 4034 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 |
| 3948 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) | 4035 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) |
| 3949 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 | 4036 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 |
| 4037 | #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) | ||
| 4038 | #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 | ||
| 3950 | #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) | 4039 | #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) |
| 3951 | #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 | 4040 | #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 |
| 3952 | u8 rss_result_mask; | 4041 | u8 rss_result_mask; |
| 3953 | u8 rss_mode; | 4042 | u8 rss_mode; |
| 3954 | __le32 __reserved2; | 4043 | __le16 udp_4tuple_dst_port_mask; |
| 4044 | __le16 udp_4tuple_dst_port_value; | ||
| 3955 | u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; | 4045 | u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; |
| 3956 | __le32 rss_key[T_ETH_RSS_KEY]; | 4046 | __le32 rss_key[T_ETH_RSS_KEY]; |
| 3957 | __le32 echo; | 4047 | __le32 echo; |
| @@ -4115,6 +4205,23 @@ enum eth_tpa_update_command { · 157 unmodified lines | |||
| 4115 | MAX_ETH_TPA_UPDATE_COMMAND | 4205 | MAX_ETH_TPA_UPDATE_COMMAND |
| 4116 | }; | 4206 | }; |
| 4117 | 4207 | ||
| 4208 | /* In case of LSO over IPv4 tunnel, whether to increment | ||
| 4209 | * IP ID on external IP header or internal IP header | ||
| 4210 | */ | ||
| 4211 | enum eth_tunnel_lso_inc_ip_id { | ||
| 4212 | EXT_HEADER, | ||
| 4213 | INT_HEADER, | ||
| 4214 | MAX_ETH_TUNNEL_LSO_INC_IP_ID | ||
| 4215 | }; | ||
| 4216 | |||
| 4217 | /* In case tunnel exist and L4 checksum offload, | ||
| 4218 | * the pseudo checksum location, on packet or on BD. | ||
| 4219 | */ | ||
| 4220 | enum eth_tunnel_non_lso_pcsum_location { | ||
| 4221 | PCSUM_ON_PKT, | ||
| 4222 | PCSUM_ON_BD, | ||
| 4223 | MAX_ETH_TUNNEL_NON_LSO_PCSUM_LOCATION | ||
| 4224 | }; | ||
| 4118 | 4225 | ||
| 4119 | /* | 4226 | /* |
| 4120 | * Tx regular BD structure | 4227 | * Tx regular BD structure |
| @@ -4166,8 +4273,8 @@ struct eth_tx_start_bd { · 45 unmodified lines | |||
| 4166 | #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 | 4273 | #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 |
| 4167 | #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) | 4274 | #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) |
| 4168 | #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 | 4275 | #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 |
| 4169 | #define ETH_TX_START_BD_RESREVED (0x1<<7) | 4276 | #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) |
| 4170 | #define ETH_TX_START_BD_RESREVED_SHIFT 7 | 4277 | #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 |
| 4171 | }; | 4278 | }; |
| 4172 | 4279 | ||
| 4173 | /* | 4280 | /* |
| @@ -4216,15 +4323,10 @@ struct eth_tx_parse_bd_e1x { · 42 unmodified lines | |||
| 4216 | * Tx parsing BD structure for ETH E2 | 4323 | * Tx parsing BD structure for ETH E2 |
| 4217 | */ | 4324 | */ |
| 4218 | struct eth_tx_parse_bd_e2 { | 4325 | struct eth_tx_parse_bd_e2 { |
| 4219 | __le16 dst_mac_addr_lo; | 4326 | union eth_mac_addr_or_tunnel_data data; |
| 4220 | __le16 dst_mac_addr_mid; | ||
| 4221 | __le16 dst_mac_addr_hi; | ||
| 4222 | __le16 src_mac_addr_lo; | ||
| 4223 | __le16 src_mac_addr_mid; | ||
| 4224 | __le16 src_mac_addr_hi; | ||
| 4225 | __le32 parsing_data; | 4327 | __le32 parsing_data; |
| 4226 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x7FF<<0) | 4328 | #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) |
| 4227 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0 | 4329 | #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 |
| 4228 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) | 4330 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) |
| 4229 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 | 4331 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 |
| 4230 | #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) | 4332 | #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) |
| @@ -4236,8 +4338,51 @@ struct eth_tx_parse_bd_e2 { · 5 unmodified lines | |||
| 4236 | }; | 4338 | }; |
| 4237 | 4339 | ||
| 4238 | /* | 4340 | /* |
| 4239 | * The last BD in the BD memory will hold a pointer to the next BD memory | 4341 | * Tx 2nd parsing BD structure for ETH packet |
| 4240 | */ | 4342 | */ |
| 4343 | struct eth_tx_parse_2nd_bd { | ||
| 4344 | __le16 global_data; | ||
| 4345 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) | ||
| 4346 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 | ||
| 4347 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER (0x1<<4) | ||
| 4348 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT 4 | ||
| 4349 | #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) | ||
| 4350 | #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 | ||
| 4351 | #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) | ||
| 4352 | #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 | ||
| 4353 | #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) | ||
| 4354 | #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 | ||
| 4355 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) | ||
| 4356 | #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 | ||
| 4357 | #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x7<<13) | ||
| 4358 | #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 13 | ||
| 4359 | __le16 reserved1; | ||
| 4360 | u8 tcp_flags; | ||
| 4361 | #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) | ||
| 4362 | #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 | ||
| 4363 | #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) | ||
| 4364 | #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 | ||
| 4365 | #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) | ||
| 4366 | #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 | ||
| 4367 | #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) | ||
| 4368 | #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 | ||
| 4369 | #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) | ||
| 4370 | #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 | ||
| 4371 | #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) | ||
| 4372 | #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 | ||
| 4373 | #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) | ||
| 4374 | #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 | ||
| 4375 | #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) | ||
| 4376 | #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 | ||
| 4377 | u8 reserved2; | ||
| 4378 | u8 tunnel_udp_hdr_start_w; | ||
| 4379 | u8 fw_ip_hdr_to_payload_w; | ||
| 4380 | __le16 fw_ip_csum_wo_len_flags_frag; | ||
| 4381 | __le16 hw_ip_id; | ||
| 4382 | __le32 tcp_send_seq; | ||
| 4383 | }; | ||
| 4384 | |||
| 4385 | /* The last BD in the BD memory will hold a pointer to the next BD memory */ | ||
| 4241 | struct eth_tx_next_bd { | 4386 | struct eth_tx_next_bd { |
| 4242 | __le32 addr_lo; | 4387 | __le32 addr_lo; |
| 4243 | __le32 addr_hi; | 4388 | __le32 addr_hi; |
| @@ -4252,6 +4397,7 @@ union eth_tx_bd_types { · 8 unmodified lines | |||
| 4252 | struct eth_tx_bd reg_bd; | 4397 | struct eth_tx_bd reg_bd; |
| 4253 | struct eth_tx_parse_bd_e1x parse_bd_e1x; | 4398 | struct eth_tx_parse_bd_e1x parse_bd_e1x; |
| 4254 | struct eth_tx_parse_bd_e2 parse_bd_e2; | 4399 | struct eth_tx_parse_bd_e2 parse_bd_e2; |
| 4400 | struct eth_tx_parse_2nd_bd parse_2nd_bd; | ||
| 4255 | struct eth_tx_next_bd next_bd; | 4401 | struct eth_tx_next_bd next_bd; |
| 4256 | }; | 4402 | }; |
| 4257 | 4403 | ||
| @@ -4663,10 +4809,10 @@ enum common_spqe_cmd_id { · 405 unmodified lines | |||
| 4663 | RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, | 4809 | RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, |
| 4664 | RAMROD_CMD_ID_COMMON_START_TRAFFIC, | 4810 | RAMROD_CMD_ID_COMMON_START_TRAFFIC, |
| 4665 | RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, | 4811 | RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, |
| 4812 | RAMROD_CMD_ID_COMMON_SET_TIMESYNC, | ||
| 4666 | MAX_COMMON_SPQE_CMD_ID | 4813 | MAX_COMMON_SPQE_CMD_ID |
| 4667 | }; | 4814 | }; |
| 4668 | 4815 | ||
| 4669 | |||
| 4670 | /* | 4816 | /* |
| 4671 | * Per-protocol connection types | 4817 | * Per-protocol connection types |
| 4672 | */ | 4818 | */ |
| @@ -4863,7 +5009,7 @@ struct vf_flr_event_data { · 190 unmodified lines | |||
| 4863 | */ | 5009 | */ |
| 4864 | struct malicious_vf_event_data { | 5010 | struct malicious_vf_event_data { |
| 4865 | u8 vf_id; | 5011 | u8 vf_id; |
| 4866 | u8 reserved0; | 5012 | u8 err_id; |
| 4867 | u16 reserved1; | 5013 | u16 reserved1; |
| 4868 | u32 reserved2; | 5014 | u32 reserved2; |
| 4869 | u32 reserved3; | 5015 | u32 reserved3; |
| @@ -4969,10 +5115,10 @@ enum event_ring_opcode { · 99 unmodified lines | |||
| 4969 | EVENT_RING_OPCODE_CLASSIFICATION_RULES, | 5115 | EVENT_RING_OPCODE_CLASSIFICATION_RULES, |
| 4970 | EVENT_RING_OPCODE_FILTERS_RULES, | 5116 | EVENT_RING_OPCODE_FILTERS_RULES, |
| 4971 | EVENT_RING_OPCODE_MULTICAST_RULES, | 5117 | EVENT_RING_OPCODE_MULTICAST_RULES, |
| 5118 | EVENT_RING_OPCODE_SET_TIMESYNC, | ||
| 4972 | MAX_EVENT_RING_OPCODE | 5119 | MAX_EVENT_RING_OPCODE |
| 4973 | }; | 5120 | }; |
| 4974 | 5121 | ||
| 4975 | |||
| 4976 | /* | 5122 | /* |
| 4977 | * Modes for fairness algorithm | 5123 | * Modes for fairness algorithm |
| 4978 | */ | 5124 | */ |
| @@ -5010,14 +5156,18 @@ struct flow_control_configuration { · 31 unmodified lines | |||
| 5010 | */ | 5156 | */ |
| 5011 | struct function_start_data { | 5157 | struct function_start_data { |
| 5012 | u8 function_mode; | 5158 | u8 function_mode; |
| 5013 | u8 reserved; | 5159 | u8 allow_npar_tx_switching; |
| 5014 | __le16 sd_vlan_tag; | 5160 | __le16 sd_vlan_tag; |
| 5015 | __le16 vif_id; | 5161 | __le16 vif_id; |
| 5016 | u8 path_id; | 5162 | u8 path_id; |
| 5017 | u8 network_cos_mode; | 5163 | u8 network_cos_mode; |
| 5164 | u8 dmae_cmd_id; | ||
| 5165 | u8 gre_tunnel_mode; | ||
| 5166 | u8 gre_tunnel_rss; | ||
| 5167 | u8 nvgre_clss_en; | ||
| 5168 | __le16 reserved1[2]; | ||
| 5018 | }; | 5169 | }; |
| 5019 | 5170 | ||
| 5020 | |||
| 5021 | struct function_update_data { | 5171 | struct function_update_data { |
| 5022 | u8 vif_id_change_flg; | 5172 | u8 vif_id_change_flg; |
| 5023 | u8 afex_default_vlan_change_flg; | 5173 | u8 afex_default_vlan_change_flg; |
| @@ -5027,14 +5177,19 @@ struct function_update_data { · 3 unmodified lines | |||
| 5027 | __le16 afex_default_vlan; | 5177 | __le16 afex_default_vlan; |
| 5028 | u8 allowed_priorities; | 5178 | u8 allowed_priorities; |
| 5029 | u8 network_cos_mode; | 5179 | u8 network_cos_mode; |
| 5180 | u8 lb_mode_en_change_flg; | ||
| 5030 | u8 lb_mode_en; | 5181 | u8 lb_mode_en; |
| 5031 | u8 tx_switch_suspend_change_flg; | 5182 | u8 tx_switch_suspend_change_flg; |
| 5032 | u8 tx_switch_suspend; | 5183 | u8 tx_switch_suspend; |
| 5033 | u8 echo; | 5184 | u8 echo; |
| 5034 | __le16 reserved1; | 5185 | u8 reserved1; |
| 5186 | u8 update_gre_cfg_flg; | ||
| 5187 | u8 gre_tunnel_mode; | ||
| 5188 | u8 gre_tunnel_rss; | ||
| 5189 | u8 nvgre_clss_en; | ||
| 5190 | u32 reserved3; | ||
| 5035 | }; | 5191 | }; |
| 5036 | 5192 | ||
| 5037 | |||
| 5038 | /* | 5193 | /* |
| 5039 | * FW version stored in the Xstorm RAM | 5194 | * FW version stored in the Xstorm RAM |
| 5040 | */ | 5195 | */ |
| @@ -5061,6 +5216,22 @@ struct fw_version { · 20 unmodified lines | |||
| 5061 | #define __FW_VERSION_RESERVED_SHIFT 4 | 5216 | #define __FW_VERSION_RESERVED_SHIFT 4 |
| 5062 | }; | 5217 | }; |
| 5063 | 5218 | ||
| 5219 | /* GRE RSS Mode */ | ||
| 5220 | enum gre_rss_mode { | ||
| 5221 | GRE_OUTER_HEADERS_RSS, | ||
| 5222 | GRE_INNER_HEADERS_RSS, | ||
| 5223 | NVGRE_KEY_ENTROPY_RSS, | ||
| 5224 | MAX_GRE_RSS_MODE | ||
| 5225 | }; | ||
| 5226 | |||
| 5227 | /* GRE Tunnel Mode */ | ||
| 5228 | enum gre_tunnel_type { | ||
| 5229 | NO_GRE_TUNNEL, | ||
| 5230 | NVGRE_TUNNEL, | ||
| 5231 | L2GRE_TUNNEL, | ||
| 5232 | IPGRE_TUNNEL, | ||
| 5233 | MAX_GRE_TUNNEL_TYPE | ||
| 5234 | }; | ||
| 5064 | 5235 | ||
| 5065 | /* | 5236 | /* |
| 5066 | * Dynamic Host-Coalescing - Driver(host) counters | 5237 | * Dynamic Host-Coalescing - Driver(host) counters |
| @@ -5224,6 +5395,26 @@ enum ip_ver { · 157 unmodified lines | |||
| 5224 | MAX_IP_VER | 5395 | MAX_IP_VER |
| 5225 | }; | 5396 | }; |
| 5226 | 5397 | ||
| 5398 | /* | ||
| 5399 | * Malicious VF error ID | ||
| 5400 | */ | ||
| 5401 | enum malicious_vf_error_id { | ||
| 5402 | VF_PF_CHANNEL_NOT_READY, | ||
| 5403 | ETH_ILLEGAL_BD_LENGTHS, | ||
| 5404 | ETH_PACKET_TOO_SHORT, | ||
| 5405 | ETH_PAYLOAD_TOO_BIG, | ||
| 5406 | ETH_ILLEGAL_ETH_TYPE, | ||
| 5407 | ETH_ILLEGAL_LSO_HDR_LEN, | ||
| 5408 | ETH_TOO_MANY_BDS, | ||
| 5409 | ETH_ZERO_HDR_NBDS, | ||
| 5410 | ETH_START_BD_NOT_SET, | ||
| 5411 | ETH_ILLEGAL_PARSE_NBDS, | ||
| 5412 | ETH_IPV6_AND_CHECKSUM, | ||
| 5413 | ETH_VLAN_FLG_INCORRECT, | ||
| 5414 | ETH_ILLEGAL_LSO_MSS, | ||
| 5415 | ETH_TUNNEL_NOT_SUPPORTED, | ||
| 5416 | MAX_MALICIOUS_VF_ERROR_ID | ||
| 5417 | }; | ||
| 5227 | 5418 | ||
| 5228 | /* | 5419 | /* |
| 5229 | * Multi-function modes | 5420 | * Multi-function modes |
| @@ -5368,7 +5559,6 @@ struct protocol_common_spe { · 138 unmodified lines | |||
| 5368 | union protocol_common_specific_data data; | 5559 | union protocol_common_specific_data data; |
| 5369 | }; | 5560 | }; |
| 5370 | 5561 | ||
| 5371 | |||
| 5372 | /* | 5562 | /* |
| 5373 | * The send queue element | 5563 | * The send queue element |
| 5374 | */ | 5564 | */ |
| @@ -27,6 +27,10 @@ · 26 unmodified lines | |||
| 27 | #include "bnx2x.h" | 27 | #include "bnx2x.h" |
| 28 | #include "bnx2x_cmn.h" | 28 | #include "bnx2x_cmn.h" |
| 29 | 29 | ||
| 30 | typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, | ||
| 31 | struct link_params *params, | ||
| 32 | u8 dev_addr, u16 addr, u8 byte_cnt, | ||
| 33 | u8 *o_buf, u8); | ||
| 30 | /********************************************************/ | 34 | /********************************************************/ |
| 31 | #define ETH_HLEN 14 | 35 | #define ETH_HLEN 14 |
| 32 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ | 36 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
| @@ -152,6 +156,7 @@ · 119 unmodified lines | |||
| 152 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 | 156 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 |
| 153 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 | 157 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 |
| 154 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 | 158 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 |
| 159 | #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 | ||
| 155 | 160 | ||
| 156 | 161 | ||
| 157 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 | 162 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 |
| @@ -3127,11 +3132,6 @@ static int bnx2x_bsc_read(struct link_params *params, · 2969 unmodified lines | |||
| 3127 | int rc = 0; | 3132 | int rc = 0; |
| 3128 | struct bnx2x *bp = params->bp; | 3133 | struct bnx2x *bp = params->bp; |
| 3129 | 3134 | ||
| 3130 | if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) { | ||
| 3131 | DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid); | ||
| 3132 | return -EINVAL; | ||
| 3133 | } | ||
| 3134 | |||
| 3135 | if (xfer_cnt > 16) { | 3135 | if (xfer_cnt > 16) { |
| 3136 | DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", | 3136 | DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", |
| 3137 | xfer_cnt); | 3137 | xfer_cnt); |
| @@ -3426,13 +3426,19 @@ static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, · 288 unmodified lines | |||
| 3426 | 3426 | ||
| 3427 | switch (phy->req_flow_ctrl) { | 3427 | switch (phy->req_flow_ctrl) { |
| 3428 | case BNX2X_FLOW_CTRL_AUTO: | 3428 | case BNX2X_FLOW_CTRL_AUTO: |
| 3429 | if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) | 3429 | switch (params->req_fc_auto_adv) { |
| 3430 | case BNX2X_FLOW_CTRL_BOTH: | ||
| 3430 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | 3431 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
| 3431 | else | 3432 | break; |
| 3433 | case BNX2X_FLOW_CTRL_RX: | ||
| 3434 | case BNX2X_FLOW_CTRL_TX: | ||
| 3432 | *ieee_fc |= | 3435 | *ieee_fc |= |
| 3433 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | 3436 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
| 3437 | break; | ||
| 3438 | default: | ||
| 3439 | break; | ||
| 3440 | } | ||
| 3434 | break; | 3441 | break; |
| 3435 | |||
| 3436 | case BNX2X_FLOW_CTRL_TX: | 3442 | case BNX2X_FLOW_CTRL_TX: |
| 3437 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | 3443 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
| 3438 | break; | 3444 | break; |
| @@ -3629,6 +3635,16 @@ static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, · 190 unmodified lines | |||
| 3629 | * init configuration, and set/clear SGMII flag. Internal | 3635 | * init configuration, and set/clear SGMII flag. Internal |
| 3630 | * phy init is done purely in phy_init stage. | 3636 | * phy init is done purely in phy_init stage. |
| 3631 | */ | 3637 | */ |
| 3638 | #define WC_TX_DRIVER(post2, idriver, ipre) \ | ||
| 3639 | ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ | ||
| 3640 | (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ | ||
| 3641 | (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) | ||
| 3642 | |||
| 3643 | #define WC_TX_FIR(post, main, pre) \ | ||
| 3644 | ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ | ||
| 3645 | (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ | ||
| 3646 | (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) | ||
| 3647 | |||
| 3632 | static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, | 3648 | static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, |
| 3633 | struct link_params *params, | 3649 | struct link_params *params, |
| 3634 | struct link_vars *vars) | 3650 | struct link_vars *vars) |
| @@ -3728,7 +3744,7 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, · 93 unmodified lines | |||
| 3728 | if (((vars->line_speed == SPEED_AUTO_NEG) && | 3744 | if (((vars->line_speed == SPEED_AUTO_NEG) && |
| 3729 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | 3745 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
| 3730 | (vars->line_speed == SPEED_1000)) { | 3746 | (vars->line_speed == SPEED_1000)) { |
| 3731 | u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; | 3747 | u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; |
| 3732 | an_adv |= (1<<5); | 3748 | an_adv |= (1<<5); |
| 3733 | 3749 | ||
| 3734 | /* Enable CL37 1G Parallel Detect */ | 3750 | /* Enable CL37 1G Parallel Detect */ |
| @@ -3753,20 +3769,13 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, · 18 unmodified lines | |||
| 3753 | /* Set Transmit PMD settings */ | 3769 | /* Set Transmit PMD settings */ |
| 3754 | lane = bnx2x_get_warpcore_lane(phy, params); | 3770 | lane = bnx2x_get_warpcore_lane(phy, params); |
| 3755 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 3771 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3756 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | 3772 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, |
| 3757 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | 3773 | WC_TX_DRIVER(0x02, 0x06, 0x09)); |
| 3758 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | ||
| 3759 | (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); | ||
| 3760 | /* Configure the next lane if dual mode */ | 3774 | /* Configure the next lane if dual mode */ |
| 3761 | if (phy->flags & FLAGS_WC_DUAL_MODE) | 3775 | if (phy->flags & FLAGS_WC_DUAL_MODE) |
| 3762 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 3776 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3763 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), | 3777 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), |
| 3764 | ((0x02 << | 3778 | WC_TX_DRIVER(0x02, 0x06, 0x09)); |
| 3765 | MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | ||
| 3766 | (0x06 << | ||
| 3767 | MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | ||
| 3768 | (0x09 << | ||
| 3769 | MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); | ||
| 3770 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 3779 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3771 | MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, | 3780 | MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, |
| 3772 | 0x03f0); | 3781 | 0x03f0); |
| @@ -3909,6 +3918,8 @@ static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, · 136 unmodified lines | |||
| 3909 | { | 3918 | { |
| 3910 | struct bnx2x *bp = params->bp; | 3919 | struct bnx2x *bp = params->bp; |
| 3911 | u16 misc1_val, tap_val, tx_driver_val, lane, val; | 3920 | u16 misc1_val, tap_val, tx_driver_val, lane, val; |
| 3921 | u32 cfg_tap_val, tx_drv_brdct, tx_equal; | ||
| 3922 | |||
| 3912 | /* Hold rxSeqStart */ | 3923 | /* Hold rxSeqStart */ |
| 3913 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | 3924 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
| 3914 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); | 3925 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); |
| @@ -3952,23 +3963,33 @@ static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, · 37 unmodified lines | |||
| 3952 | 3963 | ||
| 3953 | if (is_xfi) { | 3964 | if (is_xfi) { |
| 3954 | misc1_val |= 0x5; | 3965 | misc1_val |= 0x5; |
| 3955 | tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | | 3966 | tap_val = WC_TX_FIR(0x08, 0x37, 0x00); |
| 3956 | (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | 3967 | tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); |
| 3957 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); | ||
| 3958 | tx_driver_val = | ||
| 3959 | ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | ||
| 3960 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | ||
| 3961 | (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); | ||
| 3962 | |||
| 3963 | } else { | 3968 | } else { |
| 3969 | cfg_tap_val = REG_RD(bp, params->shmem_base + | ||
| 3970 | offsetof(struct shmem_region, dev_info. | ||
| 3971 | port_hw_config[params->port]. | ||
| 3972 | sfi_tap_values)); | ||
| 3973 | |||
| 3974 | tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; | ||
| 3975 | |||
| 3976 | tx_drv_brdct = (cfg_tap_val & | ||
| 3977 | PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> | ||
| 3978 | PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; | ||
| 3979 | |||
| 3964 | misc1_val |= 0x9; | 3980 | misc1_val |= 0x9; |
| 3965 | tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | | 3981 | |
| 3966 | (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | 3982 | /* TAP values are controlled by nvram, if value there isn't 0 */ |
| 3967 | (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); | 3983 | if (tx_equal) |
| 3968 | tx_driver_val = | 3984 | tap_val = (u16)tx_equal; |
| 3969 | ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | 3985 | else |
| 3970 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | 3986 | tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); |
| 3971 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); | 3987 | |
| 3988 | if (tx_drv_brdct) | ||
| 3989 | tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct, | ||
| 3990 | 0x06); | ||
| 3991 | else | ||
| 3992 | tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); | ||
| 3972 | } | 3993 | } |
| 3973 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 3994 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 3974 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); | 3995 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); |
| @@ -4105,15 +4126,11 @@ static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, · 130 unmodified lines | |||
| 4105 | /* Set Transmit PMD settings */ | 4126 | /* Set Transmit PMD settings */ |
| 4106 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 4127 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4107 | MDIO_WC_REG_TX_FIR_TAP, | 4128 | MDIO_WC_REG_TX_FIR_TAP, |
| 4108 | ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | | 4129 | (WC_TX_FIR(0x12, 0x2d, 0x00) | |
| 4109 | (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | 4130 | MDIO_WC_REG_TX_FIR_TAP_ENABLE)); |
| 4110 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) | | ||
| 4111 | MDIO_WC_REG_TX_FIR_TAP_ENABLE)); | ||
| 4112 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 4131 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
| 4113 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | 4132 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, |
| 4114 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | 4133 | WC_TX_DRIVER(0x02, 0x02, 0x02)); |
| 4115 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | ||
| 4116 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); | ||
| 4117 | } | 4134 | } |
| 4118 | 4135 | ||
| 4119 | static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, | 4136 | static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, |
| @@ -4750,8 +4767,8 @@ void bnx2x_link_status_update(struct link_params *params, · 630 unmodified lines | |||
| 4750 | port_mb[port].link_status)); | 4767 | port_mb[port].link_status)); |
| 4751 | 4768 | ||
| 4752 | /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ | 4769 | /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ |
| 4753 | if (bp->link_params.loopback_mode != LOOPBACK_NONE && | 4770 | if (params->loopback_mode != LOOPBACK_NONE && |
| 4754 | bp->link_params.loopback_mode != LOOPBACK_EXT) | 4771 | params->loopback_mode != LOOPBACK_EXT) |
| 4755 | vars->link_status |= LINK_STATUS_LINK_UP; | 4772 | vars->link_status |= LINK_STATUS_LINK_UP; |
| 4756 | 4773 | ||
| 4757 | if (bnx2x_eee_has_cap(params)) | 4774 | if (bnx2x_eee_has_cap(params)) |
| @@ -7758,7 +7775,8 @@ static void bnx2x_sfp_set_transmitter(struct link_params *params, · 3000 unmodified lines | |||
| 7758 | 7775 | ||
| 7759 | static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, | 7776 | static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
| 7760 | struct link_params *params, | 7777 | struct link_params *params, |
| 7761 | u16 addr, u8 byte_cnt, u8 *o_buf) | 7778 | u8 dev_addr, u16 addr, u8 byte_cnt, |
| 7779 | u8 *o_buf, u8 is_init) | ||
| 7762 | { | 7780 | { |
| 7763 | struct bnx2x *bp = params->bp; | 7781 | struct bnx2x *bp = params->bp; |
| 7764 | u16 val = 0; | 7782 | u16 val = 0; |
| @@ -7771,7 +7789,7 @@ static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, · 6 unmodified lines | |||
| 7771 | /* Set the read command byte count */ | 7789 | /* Set the read command byte count */ |
| 7772 | bnx2x_cl45_write(bp, phy, | 7790 | bnx2x_cl45_write(bp, phy, |
| 7773 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, | 7791 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, |
| 7774 | (byte_cnt | 0xa000)); | 7792 | (byte_cnt | (dev_addr << 8))); |
| 7775 | 7793 | ||
| 7776 | /* Set the read command address */ | 7794 | /* Set the read command address */ |
| 7777 | bnx2x_cl45_write(bp, phy, | 7795 | bnx2x_cl45_write(bp, phy, |
| @@ -7845,6 +7863,7 @@ static void bnx2x_warpcore_power_module(struct link_params *params, · 67 unmodified lines | |||
| 7845 | } | 7863 | } |
| 7846 | static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, | 7864 | static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
| 7847 | struct link_params *params, | 7865 | struct link_params *params, |
| 7866 | u8 dev_addr, | ||
| 7848 | u16 addr, u8 byte_cnt, | 7867 | u16 addr, u8 byte_cnt, |
| 7849 | u8 *o_buf, u8 is_init) | 7868 | u8 *o_buf, u8 is_init) |
| 7850 | { | 7869 | { |
| @@ -7869,7 +7888,7 @@ static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, · 18 unmodified lines | |||
| 7869 | usleep_range(1000, 2000); | 7888 | usleep_range(1000, 2000); |
| 7870 | bnx2x_warpcore_power_module(params, 1); | 7889 | bnx2x_warpcore_power_module(params, 1); |
| 7871 | } | 7890 | } |
| 7872 | rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt, | 7891 | rc = bnx2x_bsc_read(params, phy, dev_addr, addr32, 0, byte_cnt, |
| 7873 | data_array); | 7892 | data_array); |
| 7874 | } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); | 7893 | } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); |
| 7875 | 7894 | ||
| @@ -7885,7 +7904,8 @@ static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, · 9 unmodified lines | |||
| 7885 | 7904 | ||
| 7886 | static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, | 7905 | static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
| 7887 | struct link_params *params, | 7906 | struct link_params *params, |
| 7888 | u16 addr, u8 byte_cnt, u8 *o_buf) | 7907 | u8 dev_addr, u16 addr, u8 byte_cnt, |
| 7908 | u8 *o_buf, u8 is_init) | ||
| 7889 | { | 7909 | { |
| 7890 | struct bnx2x *bp = params->bp; | 7910 | struct bnx2x *bp = params->bp; |
| 7891 | u16 val, i; | 7911 | u16 val, i; |
| @@ -7896,6 +7916,15 @@ static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, · 4 unmodified lines | |||
| 7896 | return -EINVAL; | 7916 | return -EINVAL; |
| 7897 | } | 7917 | } |
| 7898 | 7918 | ||
| 7919 | /* Set 2-wire transfer rate of SFP+ module EEPROM | ||
| 7920 | * to 100Khz since some DACs(direct attached cables) do | ||
| 7921 | * not work at 400Khz. | ||
| 7922 | */ | ||
| 7923 | bnx2x_cl45_write(bp, phy, | ||
| 7924 | MDIO_PMA_DEVAD, | ||
| 7925 | MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, | ||
| 7926 | ((dev_addr << 8) | 1)); | ||
| 7927 | |||
| 7899 | /* Need to read from 1.8000 to clear it */ | 7928 | /* Need to read from 1.8000 to clear it */ |
| 7900 | bnx2x_cl45_read(bp, phy, | 7929 | bnx2x_cl45_read(bp, phy, |
| 7901 | MDIO_PMA_DEVAD, | 7930 | MDIO_PMA_DEVAD, |
| @@ -7968,26 +7997,44 @@ static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, · 66 unmodified lines | |||
| 7968 | 7997 | ||
| 7969 | return -EINVAL; | 7998 | return -EINVAL; |
| 7970 | } | 7999 | } |
| 7971 | |||
| 7972 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, | 8000 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
| 7973 | struct link_params *params, u16 addr, | 8001 | struct link_params *params, u8 dev_addr, |
| 7974 | u8 byte_cnt, u8 *o_buf) | 8002 | u16 addr, u16 byte_cnt, u8 *o_buf) |
| 7975 | { | 8003 | { |
| 7976 | int rc = -EOPNOTSUPP; | 8004 | int rc = 0; |
| 8005 | struct bnx2x *bp = params->bp; | ||
| 8006 | u8 xfer_size; | ||
| 8007 | u8 *user_data = o_buf; | ||
| 8008 | read_sfp_module_eeprom_func_p read_func; | ||
| 8009 | |||
| 8010 | if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { | ||
| 8011 | DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); | ||
| 8012 | return -EINVAL; | ||
| 8013 | } | ||
| 8014 | |||
| 7977 | switch (phy->type) { | 8015 | switch (phy->type) { |
| 7978 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | 8016 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
| 7979 | rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, | 8017 | read_func = bnx2x_8726_read_sfp_module_eeprom; |
| 7980 | byte_cnt, o_buf); | 8018 | break; |
| 7981 | break; | ||
| 7982 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | 8019 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
| 7983 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | 8020 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
| 7984 | rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, | 8021 | read_func = bnx2x_8727_read_sfp_module_eeprom; |
| 7985 | byte_cnt, o_buf); | 8022 | break; |
| 7986 | break; | ||
| 7987 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: | 8023 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
| 7988 | rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr, | 8024 | read_func = bnx2x_warpcore_read_sfp_module_eeprom; |
| 7989 | byte_cnt, o_buf, 0); | 8025 | break; |
| 7990 | break; | 8026 | default: |
| 8027 | return -EOPNOTSUPP; | ||
| 8028 | } | ||
| 8029 | |||
| 8030 | while (!rc && (byte_cnt > 0)) { | ||
| 8031 | xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ? | ||
| 8032 | SFP_EEPROM_PAGE_SIZE : byte_cnt; | ||
| 8033 | rc = read_func(phy, params, dev_addr, addr, xfer_size, | ||
| 8034 | user_data, 0); | ||
| 8035 | byte_cnt -= xfer_size; | ||
| 8036 | user_data += xfer_size; | ||
| 8037 | addr += xfer_size; | ||
| 7991 | } | 8038 | } |
| 7992 | return rc; | 8039 | return rc; |
| 7993 | } | 8040 | } |
| @@ -8004,6 +8051,7 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, · 10 unmodified lines | |||
| 8004 | /* First check for copper cable */ | 8051 | /* First check for copper cable */ |
| 8005 | if (bnx2x_read_sfp_module_eeprom(phy, | 8052 | if (bnx2x_read_sfp_module_eeprom(phy, |
| 8006 | params, | 8053 | params, |
| 8054 | I2C_DEV_ADDR_A0, | ||
| 8007 | SFP_EEPROM_CON_TYPE_ADDR, | 8055 | SFP_EEPROM_CON_TYPE_ADDR, |
| 8008 | 2, | 8056 | 2, |
| 8009 | (u8 *)val) != 0) { | 8057 | (u8 *)val) != 0) { |
| @@ -8021,6 +8069,7 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, · 11 unmodified lines | |||
| 8021 | */ | 8069 | */ |
| 8022 | if (bnx2x_read_sfp_module_eeprom(phy, | 8070 | if (bnx2x_read_sfp_module_eeprom(phy, |
| 8023 | params, | 8071 | params, |
| 8072 | I2C_DEV_ADDR_A0, | ||
| 8024 | SFP_EEPROM_FC_TX_TECH_ADDR, | 8073 | SFP_EEPROM_FC_TX_TECH_ADDR, |
| 8025 | 1, | 8074 | 1, |
| 8026 | &copper_module_type) != 0) { | 8075 | &copper_module_type) != 0) { |
| @@ -8049,20 +8098,24 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, · 22 unmodified lines | |||
| 8049 | break; | 8098 | break; |
| 8050 | } | 8099 | } |
| 8051 | case SFP_EEPROM_CON_TYPE_VAL_LC: | 8100 | case SFP_EEPROM_CON_TYPE_VAL_LC: |
| 8101 | case SFP_EEPROM_CON_TYPE_VAL_RJ45: | ||
| 8052 | check_limiting_mode = 1; | 8102 | check_limiting_mode = 1; |
| 8053 | if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | | 8103 | if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | |
| 8054 | SFP_EEPROM_COMP_CODE_LR_MASK | | 8104 | SFP_EEPROM_COMP_CODE_LR_MASK | |
| 8055 | SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { | 8105 | SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { |
| 8056 | DP(NETIF_MSG_LINK, "1G Optic module detected\n"); | 8106 | DP(NETIF_MSG_LINK, "1G SFP module detected\n"); |
| 8057 | gport = params->port; | 8107 | gport = params->port; |
| 8058 | phy->media_type = ETH_PHY_SFP_1G_FIBER; | 8108 | phy->media_type = ETH_PHY_SFP_1G_FIBER; |
| 8059 | phy->req_line_speed = SPEED_1000; | 8109 | if (phy->req_line_speed != SPEED_1000) { |
| 8060 | if (!CHIP_IS_E1x(bp)) | 8110 | phy->req_line_speed = SPEED_1000; |
| 8061 | gport = BP_PATH(bp) + (params->port << 1); | 8111 | if (!CHIP_IS_E1x(bp)) { |
| 8062 | netdev_err(bp->dev, "Warning: Link speed was forced to 1000Mbps." | 8112 | gport = BP_PATH(bp) + |
| 8063 | " Current SFP module in port %d is not" | 8113 | (params->port << 1); |
| 8064 | " compliant with 10G Ethernet\n", | 8114 | } |
| 8065 | gport); | 8115 | netdev_err(bp->dev, |
| 8116 | "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", | ||
| 8117 | gport); | ||
| 8118 | } | ||
| 8066 | } else { | 8119 | } else { |
| 8067 | int idx, cfg_idx = 0; | 8120 | int idx, cfg_idx = 0; |
| 8068 | DP(NETIF_MSG_LINK, "10G Optic module detected\n"); | 8121 | DP(NETIF_MSG_LINK, "10G Optic module detected\n"); |
| @@ -8101,6 +8154,7 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, · 32 unmodified lines | |||
| 8101 | u8 options[SFP_EEPROM_OPTIONS_SIZE]; | 8154 | u8 options[SFP_EEPROM_OPTIONS_SIZE]; |
| 8102 | if (bnx2x_read_sfp_module_eeprom(phy, | 8155 | if (bnx2x_read_sfp_module_eeprom(phy, |
| 8103 | params, | 8156 | params, |
| 8157 | I2C_DEV_ADDR_A0, | ||
| 8104 | SFP_EEPROM_OPTIONS_ADDR, | 8158 | SFP_EEPROM_OPTIONS_ADDR, |
| 8105 | SFP_EEPROM_OPTIONS_SIZE, | 8159 | SFP_EEPROM_OPTIONS_SIZE, |
| 8106 | options) != 0) { | 8160 | options) != 0) { |
| @@ -8167,6 +8221,7 @@ static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, · 60 unmodified lines | |||
| 8167 | /* Format the warning message */ | 8221 | /* Format the warning message */ |
| 8168 | if (bnx2x_read_sfp_module_eeprom(phy, | 8222 | if (bnx2x_read_sfp_module_eeprom(phy, |
| 8169 | params, | 8223 | params, |
| 8224 | I2C_DEV_ADDR_A0, | ||
| 8170 | SFP_EEPROM_VENDOR_NAME_ADDR, | 8225 | SFP_EEPROM_VENDOR_NAME_ADDR, |
| 8171 | SFP_EEPROM_VENDOR_NAME_SIZE, | 8226 | SFP_EEPROM_VENDOR_NAME_SIZE, |
| 8172 | (u8 *)vendor_name)) | 8227 | (u8 *)vendor_name)) |
| @@ -8175,6 +8230,7 @@ static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, · 2 unmodified lines | |||
| 8175 | vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; | 8230 | vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; |
| 8176 | if (bnx2x_read_sfp_module_eeprom(phy, | 8231 | if (bnx2x_read_sfp_module_eeprom(phy, |
| 8177 | params, | 8232 | params, |
| 8233 | I2C_DEV_ADDR_A0, | ||
| 8178 | SFP_EEPROM_PART_NO_ADDR, | 8234 | SFP_EEPROM_PART_NO_ADDR, |
| 8179 | SFP_EEPROM_PART_NO_SIZE, | 8235 | SFP_EEPROM_PART_NO_SIZE, |
| 8180 | (u8 *)vendor_pn)) | 8236 | (u8 *)vendor_pn)) |
| @@ -8205,12 +8261,13 @@ static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, · 24 unmodified lines | |||
| 8205 | 8261 | ||
| 8206 | for (timeout = 0; timeout < 60; timeout++) { | 8262 | for (timeout = 0; timeout < 60; timeout++) { |
| 8207 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) | 8263 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
| 8208 | rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, | 8264 | rc = bnx2x_warpcore_read_sfp_module_eeprom( |
| 8209 | params, 1, | 8265 | phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, |
| 8210 | 1, &val, 1); | 8266 | 1); |
| 8211 | else | 8267 | else |
| 8212 | rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, | 8268 | rc = bnx2x_read_sfp_module_eeprom(phy, params, |
| 8213 | &val); | 8269 | I2C_DEV_ADDR_A0, |
| 8270 | 1, 1, &val); | ||
| 8214 | if (rc == 0) { | 8271 | if (rc == 0) { |
| 8215 | DP(NETIF_MSG_LINK, | 8272 | DP(NETIF_MSG_LINK, |
| 8216 | "SFP+ module initialization took %d ms\n", | 8273 | "SFP+ module initialization took %d ms\n", |
| @@ -8219,7 +8276,8 @@ static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, · 2 unmodified lines | |||
| 8219 | } | 8276 | } |
| 8220 | usleep_range(5000, 10000); | 8277 | usleep_range(5000, 10000); |
| 8221 | } | 8278 | } |
| 8222 | rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val); | 8279 | rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, |
| 8280 | 1, 1, &val); | ||
| 8223 | return rc; | 8281 | return rc; |
| 8224 | } | 8282 | } |
| 8225 | 8283 | ||
| @@ -8376,15 +8434,6 @@ static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, · 150 unmodified lines | |||
| 8376 | bnx2x_cl45_write(bp, phy, | 8434 | bnx2x_cl45_write(bp, phy, |
| 8377 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, | 8435 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, |
| 8378 | val); | 8436 | val); |
| 8379 | |||
| 8380 | /* Set 2-wire transfer rate of SFP+ module EEPROM | ||
| 8381 | * to 100Khz since some DACs(direct attached cables) do | ||
| 8382 | * not work at 400Khz. | ||
| 8383 | */ | ||
| 8384 | bnx2x_cl45_write(bp, phy, | ||
| 8385 | MDIO_PMA_DEVAD, | ||
| 8386 | MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, | ||
| 8387 | 0xa001); | ||
| 8388 | break; | 8437 | break; |
| 8389 | default: | 8438 | default: |
| 8390 | DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", | 8439 | DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", |
| @@ -9528,8 +9577,7 @@ static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, · 1137 unmodified lines | |||
| 9528 | } else { | 9577 | } else { |
| 9529 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ | 9578 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ |
| 9530 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | 9579 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ |
| 9531 | for (i = 0; i < ARRAY_SIZE(reg_set); | 9580 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
| 9532 | i++) | ||
| 9533 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, | 9581 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, |
| 9534 | reg_set[i].reg, reg_set[i].val); | 9582 | reg_set[i].reg, reg_set[i].val); |
| 9535 | 9583 | ||
| @@ -10281,7 +10329,8 @@ static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, · 745 unmodified lines | |||
| 10281 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | 10329 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; |
| 10282 | 10330 | ||
| 10283 | /* Determine if EEE was negotiated */ | 10331 | /* Determine if EEE was negotiated */ |
| 10284 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | 10332 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
| 10333 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) | ||
| 10285 | bnx2x_eee_an_resolve(phy, params, vars); | 10334 | bnx2x_eee_an_resolve(phy, params, vars); |
| 10286 | } | 10335 | } |
| 10287 | 10336 | ||
| @@ -12242,7 +12291,7 @@ static void bnx2x_init_bmac_loopback(struct link_params *params, · 1954 unmodified lines | |||
| 12242 | 12291 | ||
| 12243 | bnx2x_xgxs_deassert(params); | 12292 | bnx2x_xgxs_deassert(params); |
| 12244 | 12293 | ||
| 12245 | /* set bmac loopback */ | 12294 | /* Set bmac loopback */ |
| 12246 | bnx2x_bmac_enable(params, vars, 1, 1); | 12295 | bnx2x_bmac_enable(params, vars, 1, 1); |
| 12247 | 12296 | ||
| 12248 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | 12297 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
| @@ -12261,7 +12310,7 @@ static void bnx2x_init_emac_loopback(struct link_params *params, · 12 unmodified lines | |||
| 12261 | vars->phy_flags = PHY_XGXS_FLAG; | 12310 | vars->phy_flags = PHY_XGXS_FLAG; |
| 12262 | 12311 | ||
| 12263 | bnx2x_xgxs_deassert(params); | 12312 | bnx2x_xgxs_deassert(params); |
| 12264 | /* set bmac loopback */ | 12313 | /* Set bmac loopback */ |
| 12265 | bnx2x_emac_enable(params, vars, 1); | 12314 | bnx2x_emac_enable(params, vars, 1); |
| 12266 | bnx2x_emac_program(params, vars); | 12315 | bnx2x_emac_program(params, vars); |
| 12267 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | 12316 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
| @@ -12521,6 +12570,7 @@ int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) · 253 unmodified lines | |||
| 12521 | params->req_line_speed[0], params->req_flow_ctrl[0]); | 12570 | params->req_line_speed[0], params->req_flow_ctrl[0]); |
| 12522 | DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", | 12571 | DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", |
| 12523 | params->req_line_speed[1], params->req_flow_ctrl[1]); | 12572 | params->req_line_speed[1], params->req_flow_ctrl[1]); |
| 12573 | DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); | ||
| 12524 | vars->link_status = 0; | 12574 | vars->link_status = 0; |
| 12525 | vars->phy_link_up = 0; | 12575 | vars->phy_link_up = 0; |
| 12526 | vars->link_up = 0; | 12576 | vars->link_up = 0; |
| @@ -13440,8 +13490,8 @@ static void bnx2x_check_kr2_wa(struct link_params *params, · 913 unmodified lines | |||
| 13440 | int sigdet; | 13490 | int sigdet; |
| 13441 | 13491 | ||
| 13442 | /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery | 13492 | /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery |
| 13443 | * since some switches tend to reinit the AN process and clear the | 13493 | * Since some switches tend to reinit the AN process and clear the |
| 13444 | * advertised BP/NP after ~2 seconds causing the KR2 to be disabled | 13494 | * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled |
| 13445 | * and recovered many times | 13495 | * and recovered many times |
| 13446 | */ | 13496 | */ |
| 13447 | if (vars->check_kr2_recovery_cnt > 0) { | 13497 | if (vars->check_kr2_recovery_cnt > 0) { |
| @@ -13469,8 +13519,10 @@ static void bnx2x_check_kr2_wa(struct link_params *params, · 21 unmodified lines | |||
| 13469 | 13519 | ||
| 13470 | /* CL73 has not begun yet */ | 13520 | /* CL73 has not begun yet */ |
| 13471 | if (base_page == 0) { | 13521 | if (base_page == 0) { |
| 13472 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) | 13522 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { |
| 13473 | bnx2x_kr2_recovery(params, vars, phy); | 13523 | bnx2x_kr2_recovery(params, vars, phy); |
| 13524 | DP(NETIF_MSG_LINK, "No BP\n"); | ||
| 13525 | } | ||
| 13474 | return; | 13526 | return; |
| 13475 | } | 13527 | } |
| 13476 | 13528 | ||
| @@ -13486,7 +13538,7 @@ static void bnx2x_check_kr2_wa(struct link_params *params, · 9 unmodified lines | |||
| 13486 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | 13538 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { |
| 13487 | if (!not_kr2_device) { | 13539 | if (!not_kr2_device) { |
| 13488 | DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, | 13540 | DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, |
| 13489 | next_page); | 13541 | next_page); |
| 13490 | bnx2x_kr2_recovery(params, vars, phy); | 13542 | bnx2x_kr2_recovery(params, vars, phy); |
| 13491 | } | 13543 | } |
| 13492 | return; | 13544 | return; |
| @@ -41,6 +41,9 @@ · 40 unmodified lines | |||
| 41 | #define SPEED_AUTO_NEG 0 | 41 | #define SPEED_AUTO_NEG 0 |
| 42 | #define SPEED_20000 20000 | 42 | #define SPEED_20000 20000 |
| 43 | 43 | ||
| 44 | #define I2C_DEV_ADDR_A0 0xa0 | ||
| 45 | #define I2C_DEV_ADDR_A2 0xa2 | ||
| 46 | |||
| 44 | #define SFP_EEPROM_PAGE_SIZE 16 | 47 | #define SFP_EEPROM_PAGE_SIZE 16 |
| 45 | #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14 | 48 | #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14 |
| 46 | #define SFP_EEPROM_VENDOR_NAME_SIZE 16 | 49 | #define SFP_EEPROM_VENDOR_NAME_SIZE 16 |
| @@ -54,6 +57,15 @@ · 7 unmodified lines | |||
| 54 | #define SFP_EEPROM_SERIAL_SIZE 16 | 57 | #define SFP_EEPROM_SERIAL_SIZE 16 |
| 55 | #define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ | 58 | #define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ |
| 56 | #define SFP_EEPROM_DATE_SIZE 6 | 59 | #define SFP_EEPROM_DATE_SIZE 6 |
| 60 | #define SFP_EEPROM_DIAG_TYPE_ADDR 0x5c | ||
| 61 | #define SFP_EEPROM_DIAG_TYPE_SIZE 1 | ||
| 62 | #define SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2) | ||
| 63 | #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e | ||
| 64 | #define SFP_EEPROM_SFF_8472_COMP_SIZE 1 | ||
| 65 | |||
| 66 | #define SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e | ||
| 67 | #define SFP_EEPROM_A2_CC_DMI_ADDR 0x5f | ||
| 68 | |||
| 57 | #define PWR_FLT_ERR_MSG_LEN 250 | 69 | #define PWR_FLT_ERR_MSG_LEN 250 |
| 58 | 70 | ||
| 59 | #define XGXS_EXT_PHY_TYPE(ext_phy_config) \ | 71 | #define XGXS_EXT_PHY_TYPE(ext_phy_config) \ |
| @@ -420,8 +432,8 @@ void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy); · 360 unmodified lines | |||
| 420 | 432 | ||
| 421 | /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ | 433 | /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ |
| 422 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, | 434 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
| 423 | struct link_params *params, u16 addr, | 435 | struct link_params *params, u8 dev_addr, |
| 424 | u8 byte_cnt, u8 *o_buf); | 436 | u16 addr, u16 byte_cnt, u8 *o_buf); |
| 425 | 437 | ||
| 426 | void bnx2x_hw_reset_phy(struct link_params *params); | 438 | void bnx2x_hw_reset_phy(struct link_params *params); |
| 427 | 439 | ||
| @@ -75,8 +75,6 @@ · 74 unmodified lines | |||
| 75 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | 75 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" |
| 76 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" | 76 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
| 77 | 77 | ||
| 78 | #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) | ||
| 79 | |||
| 80 | /* Time in jiffies before concluding the transmitter is hung */ | 78 | /* Time in jiffies before concluding the transmitter is hung */ |
| 81 | #define TX_TIMEOUT (5*HZ) | 79 | #define TX_TIMEOUT (5*HZ) |
| 82 | 80 | ||
| @@ -2955,14 +2953,16 @@ static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, · 2872 unmodified lines | |||
| 2955 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | 2953 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); |
| 2956 | 2954 | ||
| 2957 | /* tx only connections collect statistics (on the same index as the | 2955 | /* tx only connections collect statistics (on the same index as the |
| 2958 | * parent connection). The statistics are zeroed when the parent | 2956 | * parent connection). The statistics are zeroed when the parent |
| 2959 | * connection is initialized. | 2957 | * connection is initialized. |
| 2960 | */ | 2958 | */ |
| 2961 | 2959 | ||
| 2962 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | 2960 | __set_bit(BNX2X_Q_FLG_STATS, &flags); |
| 2963 | if (zero_stats) | 2961 | if (zero_stats) |
| 2964 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | 2962 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); |
| 2965 | 2963 | ||
| 2964 | __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); | ||
| 2965 | __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); | ||
| 2966 | 2966 | ||
| 2967 | #ifdef BNX2X_STOP_ON_ERROR | 2967 | #ifdef BNX2X_STOP_ON_ERROR |
| 2968 | __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); | 2968 | __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); |
| @@ -3227,16 +3227,29 @@ static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) · 258 unmodified lines | |||
| 3227 | { | 3227 | { |
| 3228 | struct eth_stats_info *ether_stat = | 3228 | struct eth_stats_info *ether_stat = |
| 3229 | &bp->slowpath->drv_info_to_mcp.ether_stat; | 3229 | &bp->slowpath->drv_info_to_mcp.ether_stat; |
| 3230 | struct bnx2x_vlan_mac_obj *mac_obj = | ||
| 3231 | &bp->sp_objs->mac_obj; | ||
| 3232 | int i; | ||
| 3230 | 3233 | ||
| 3231 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, | 3234 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, |
| 3232 | ETH_STAT_INFO_VERSION_LEN); | 3235 | ETH_STAT_INFO_VERSION_LEN); |
| 3233 | 3236 | ||
| 3234 | bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj, | 3237 | /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the |
| 3235 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | 3238 | * mac_local field in ether_stat struct. The base address is offset by 2 |
| 3236 | ether_stat->mac_local); | 3239 | * bytes to account for the field being 8 bytes but a mac address is |
| 3237 | 3240 | * only 6 bytes. Likewise, the stride for the get_n_elements function is | |
| 3241 | * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes | ||
| 3242 | * allocated by the ether_stat struct, so the macs will land in their | ||
| 3243 | * proper positions. | ||
| 3244 | */ | ||
| 3245 | for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) | ||
| 3246 | memset(ether_stat->mac_local + i, 0, | ||
| 3247 | sizeof(ether_stat->mac_local[0])); | ||
| 3248 | mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, | ||
| 3249 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | ||
| 3250 | ether_stat->mac_local + MAC_PAD, MAC_PAD, | ||
| 3251 | ETH_ALEN); | ||
| 3238 | ether_stat->mtu_size = bp->dev->mtu; | 3252 | ether_stat->mtu_size = bp->dev->mtu; |
| 3239 | |||
| 3240 | if (bp->dev->features & NETIF_F_RXCSUM) | 3253 | if (bp->dev->features & NETIF_F_RXCSUM) |
| 3241 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | 3254 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; |
| 3242 | if (bp->dev->features & NETIF_F_TSO) | 3255 | if (bp->dev->features & NETIF_F_TSO) |
| @@ -3258,8 +3271,7 @@ static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) · 15 unmodified lines | |||
| 3258 | if (!CNIC_LOADED(bp)) | 3271 | if (!CNIC_LOADED(bp)) |
| 3259 | return; | 3272 | return; |
| 3260 | 3273 | ||
| 3261 | memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT, | 3274 | memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); |
| 3262 | bp->fip_mac, ETH_ALEN); | ||
| 3263 | 3275 | ||
| 3264 | fcoe_stat->qos_priority = | 3276 | fcoe_stat->qos_priority = |
| 3265 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | 3277 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; |
| @@ -3361,8 +3373,8 @@ static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) · 95 unmodified lines | |||
| 3361 | if (!CNIC_LOADED(bp)) | 3373 | if (!CNIC_LOADED(bp)) |
| 3362 | return; | 3374 | return; |
| 3363 | 3375 | ||
| 3364 | memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT, | 3376 | memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, |
| 3365 | bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); | 3377 | ETH_ALEN); |
| 3366 | 3378 | ||
| 3367 | iscsi_stat->qos_priority = | 3379 | iscsi_stat->qos_priority = |
| 3368 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | 3380 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; |
| @@ -6018,10 +6030,11 @@ void bnx2x_nic_init_cnic(struct bnx2x *bp) · 2649 unmodified lines | |||
| 6018 | mmiowb(); | 6030 | mmiowb(); |
| 6019 | } | 6031 | } |
| 6020 | 6032 | ||
| 6021 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) | 6033 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp) |
| 6022 | { | 6034 | { |
| 6023 | int i; | 6035 | int i; |
| 6024 | 6036 | ||
| 6037 | /* Setup NIC internals and enable interrupts */ | ||
| 6025 | for_each_eth_queue(bp, i) | 6038 | for_each_eth_queue(bp, i) |
| 6026 | bnx2x_init_eth_fp(bp, i); | 6039 | bnx2x_init_eth_fp(bp, i); |
| 6027 | 6040 | ||
| @@ -6030,17 +6043,26 @@ void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) · 2 unmodified lines | |||
| 6030 | bnx2x_init_rx_rings(bp); | 6043 | bnx2x_init_rx_rings(bp); |
| 6031 | bnx2x_init_tx_rings(bp); | 6044 | bnx2x_init_tx_rings(bp); |
| 6032 | 6045 | ||
| 6033 | if (IS_VF(bp)) | 6046 | if (IS_VF(bp)) { |
| 6047 | bnx2x_memset_stats(bp); | ||
| 6034 | return; | 6048 | return; |
| 6049 | } | ||
| 6035 | 6050 | ||
| 6036 | /* Initialize MOD_ABS interrupts */ | 6051 | if (IS_PF(bp)) { |
| 6037 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | 6052 | /* Initialize MOD_ABS interrupts */ |
| 6038 | bp->common.shmem_base, bp->common.shmem2_base, | 6053 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, |
| 6039 | BP_PORT(bp)); | 6054 | bp->common.shmem_base, |
| 6055 | bp->common.shmem2_base, BP_PORT(bp)); | ||
| 6040 | 6056 | ||
| 6041 | bnx2x_init_def_sb(bp); | 6057 | /* initialize the default status block and sp ring */ |
| 6042 | bnx2x_update_dsb_idx(bp); | 6058 | bnx2x_init_def_sb(bp); |
| 6043 | bnx2x_init_sp_ring(bp); | 6059 | bnx2x_update_dsb_idx(bp); |
| 6060 | bnx2x_init_sp_ring(bp); | ||
| 6061 | } | ||
| 6062 | } | ||
| 6063 | |||
| 6064 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) | ||
| 6065 | { | ||
| 6044 | bnx2x_init_eq_ring(bp); | 6066 | bnx2x_init_eq_ring(bp); |
| 6045 | bnx2x_init_internal(bp, load_code); | 6067 | bnx2x_init_internal(bp, load_code); |
| 6046 | bnx2x_pf_init(bp); | 6068 | bnx2x_pf_init(bp); |
| @@ -6058,12 +6080,7 @@ void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) · 11 unmodified lines | |||
| 6058 | AEU_INPUTS_ATTN_BITS_SPIO5); | 6080 | AEU_INPUTS_ATTN_BITS_SPIO5); |
| 6059 | } | 6081 | } |
| 6060 | 6082 | ||
| 6061 | /* end of nic init */ | 6083 | /* gzip service functions */ |
| 6062 | |||
| 6063 | /* | ||
| 6064 | * gzip service functions | ||
| 6065 | */ | ||
| 6066 | |||
| 6067 | static int bnx2x_gunzip_init(struct bnx2x *bp) | 6084 | static int bnx2x_gunzip_init(struct bnx2x *bp) |
| 6068 | { | 6085 | { |
| 6069 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, | 6086 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
| @@ -7757,6 +7774,8 @@ void bnx2x_free_mem(struct bnx2x *bp) · 1687 unmodified lines | |||
| 7757 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, | 7774 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
| 7758 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | 7775 | BCM_PAGE_SIZE * NUM_EQ_PAGES); |
| 7759 | 7776 | ||
| 7777 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); | ||
| 7778 | |||
| 7760 | bnx2x_iov_free_mem(bp); | 7779 | bnx2x_iov_free_mem(bp); |
| 7761 | } | 7780 | } |
| 7762 | 7781 | ||
| @@ -7773,7 +7792,7 @@ int bnx2x_alloc_mem_cnic(struct bnx2x *bp) · 10 unmodified lines | |||
| 7773 | sizeof(struct | 7792 | sizeof(struct |
| 7774 | host_hc_status_block_e1x)); | 7793 | host_hc_status_block_e1x)); |
| 7775 | 7794 | ||
| 7776 | if (CONFIGURE_NIC_MODE(bp)) | 7795 | if (CONFIGURE_NIC_MODE(bp) && !bp->t2) |
| 7777 | /* allocate searcher T2 table, as it wan't allocated before */ | 7796 | /* allocate searcher T2 table, as it wan't allocated before */ |
| 7778 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | 7797 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); |
| 7779 | 7798 | ||
| @@ -7796,7 +7815,7 @@ int bnx2x_alloc_mem(struct bnx2x *bp) · 16 unmodified lines | |||
| 7796 | { | 7815 | { |
| 7797 | int i, allocated, context_size; | 7816 | int i, allocated, context_size; |
| 7798 | 7817 | ||
| 7799 | if (!CONFIGURE_NIC_MODE(bp)) | 7818 | if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) |
| 7800 | /* allocate searcher T2 table */ | 7819 | /* allocate searcher T2 table */ |
| 7801 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | 7820 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); |
| 7802 | 7821 | ||
| @@ -7917,8 +7936,6 @@ int bnx2x_del_all_macs(struct bnx2x *bp, · 114 unmodified lines | |||
| 7917 | 7936 | ||
| 7918 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) | 7937 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
| 7919 | { | 7938 | { |
| 7920 | unsigned long ramrod_flags = 0; | ||
| 7921 | |||
| 7922 | if (is_zero_ether_addr(bp->dev->dev_addr) && | 7939 | if (is_zero_ether_addr(bp->dev->dev_addr) && |
| 7923 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { | 7940 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { |
| 7924 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, | 7941 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, |
| @@ -7926,12 +7943,18 @@ int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) · 1 unmodified line | |||
| 7926 | return 0; | 7943 | return 0; |
| 7927 | } | 7944 | } |
| 7928 | 7945 | ||
| 7929 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); | 7946 | if (IS_PF(bp)) { |
| 7947 | unsigned long ramrod_flags = 0; | ||
| 7930 | 7948 | ||
| 7931 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | 7949 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
| 7932 | /* Eth MAC is set on RSS leading client (fp[0]) */ | 7950 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
| 7933 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj, | 7951 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, |
| 7934 | set, BNX2X_ETH_MAC, &ramrod_flags); | 7952 | &bp->sp_objs->mac_obj, set, |
| 7953 | BNX2X_ETH_MAC, &ramrod_flags); | ||
| 7954 | } else { /* vf */ | ||
| 7955 | return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, | ||
| 7956 | bp->fp->index, true); | ||
| 7957 | } | ||
| 7935 | } | 7958 | } |
| 7936 | 7959 | ||
| 7937 | int bnx2x_setup_leading(struct bnx2x *bp) | 7960 | int bnx2x_setup_leading(struct bnx2x *bp) |
| @@ -9525,6 +9548,10 @@ sp_rtnl_not_reset: · 1587 unmodified lines | |||
| 9525 | bnx2x_vfpf_storm_rx_mode(bp); | 9548 | bnx2x_vfpf_storm_rx_mode(bp); |
| 9526 | } | 9549 | } |
| 9527 | 9550 | ||
| 9551 | if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, | ||
| 9552 | &bp->sp_rtnl_state)) | ||
| 9553 | bnx2x_pf_set_vfs_vlan(bp); | ||
| 9554 | |||
| 9528 | /* work which needs rtnl lock not-taken (as it takes the lock itself and | 9555 | /* work which needs rtnl lock not-taken (as it takes the lock itself and |
| 9529 | * can be called from other contexts as well) | 9556 | * can be called from other contexts as well) |
| 9530 | */ | 9557 | */ |
| @@ -9532,8 +9559,10 @@ sp_rtnl_not_reset: · 1 unmodified line | |||
| 9532 | 9559 | ||
| 9533 | /* enable SR-IOV if applicable */ | 9560 | /* enable SR-IOV if applicable */ |
| 9534 | if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, | 9561 | if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, |
| 9535 | &bp->sp_rtnl_state)) | 9562 | &bp->sp_rtnl_state)) { |
| 9563 | bnx2x_disable_sriov(bp); | ||
| 9536 | bnx2x_enable_sriov(bp); | 9564 | bnx2x_enable_sriov(bp); |
| 9565 | } | ||
| 9537 | } | 9566 | } |
| 9538 | 9567 | ||
| 9539 | static void bnx2x_period_task(struct work_struct *work) | 9568 | static void bnx2x_period_task(struct work_struct *work) |
| @@ -9701,6 +9730,31 @@ static struct bnx2x_prev_path_list * · 161 unmodified lines | |||
| 9701 | return NULL; | 9730 | return NULL; |
| 9702 | } | 9731 | } |
| 9703 | 9732 | ||
| 9733 | static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) | ||
| 9734 | { | ||
| 9735 | struct bnx2x_prev_path_list *tmp_list; | ||
| 9736 | int rc; | ||
| 9737 | |||
| 9738 | rc = down_interruptible(&bnx2x_prev_sem); | ||
| 9739 | if (rc) { | ||
| 9740 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | ||
| 9741 | return rc; | ||
| 9742 | } | ||
| 9743 | |||
| 9744 | tmp_list = bnx2x_prev_path_get_entry(bp); | ||
| 9745 | if (tmp_list) { | ||
| 9746 | tmp_list->aer = 1; | ||
| 9747 | rc = 0; | ||
| 9748 | } else { | ||
| 9749 | BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", | ||
| 9750 | BP_PATH(bp)); | ||
| 9751 | } | ||
| 9752 | |||
| 9753 | up(&bnx2x_prev_sem); | ||
| 9754 | |||
| 9755 | return rc; | ||
| 9756 | } | ||
| 9757 | |||
| 9704 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) | 9758 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) |
| 9705 | { | 9759 | { |
| 9706 | struct bnx2x_prev_path_list *tmp_list; | 9760 | struct bnx2x_prev_path_list *tmp_list; |
| @@ -9709,14 +9763,15 @@ static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) · 2 unmodified lines | |||
| 9709 | if (down_trylock(&bnx2x_prev_sem)) | 9763 | if (down_trylock(&bnx2x_prev_sem)) |
| 9710 | return false; | 9764 | return false; |
| 9711 | 9765 | ||
| 9712 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) { | 9766 | tmp_list = bnx2x_prev_path_get_entry(bp); |
| 9713 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | 9767 | if (tmp_list) { |
| 9714 | bp->pdev->bus->number == tmp_list->bus && | 9768 | if (tmp_list->aer) { |
| 9715 | BP_PATH(bp) == tmp_list->path) { | 9769 | DP(NETIF_MSG_HW, "Path %d was marked by AER\n", |
| 9770 | BP_PATH(bp)); | ||
| 9771 | } else { | ||
| 9716 | rc = true; | 9772 | rc = true; |
| 9717 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | 9773 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", |
| 9718 | BP_PATH(bp)); | 9774 | BP_PATH(bp)); |
| 9719 | break; | ||
| 9720 | } | 9775 | } |
| 9721 | } | 9776 | } |
| 9722 | 9777 | ||
| @@ -9730,6 +9785,28 @@ static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) · 7 unmodified lines | |||
| 9730 | struct bnx2x_prev_path_list *tmp_list; | 9785 | struct bnx2x_prev_path_list *tmp_list; |
| 9731 | int rc; | 9786 | int rc; |
| 9732 | 9787 | ||
| 9788 | rc = down_interruptible(&bnx2x_prev_sem); | ||
| 9789 | if (rc) { | ||
| 9790 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | ||
| 9791 | return rc; | ||
| 9792 | } | ||
| 9793 | |||
| 9794 | /* Check whether the entry for this path already exists */ | ||
| 9795 | tmp_list = bnx2x_prev_path_get_entry(bp); | ||
| 9796 | if (tmp_list) { | ||
| 9797 | if (!tmp_list->aer) { | ||
| 9798 | BNX2X_ERR("Re-Marking the path.\n"); | ||
| 9799 | } else { | ||
| 9800 | DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", | ||
| 9801 | BP_PATH(bp)); | ||
| 9802 | tmp_list->aer = 0; | ||
| 9803 | } | ||
| 9804 | up(&bnx2x_prev_sem); | ||
| 9805 | return 0; | ||
| 9806 | } | ||
| 9807 | up(&bnx2x_prev_sem); | ||
| 9808 | |||
| 9809 | /* Create an entry for this path and add it */ | ||
| 9733 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); | 9810 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); |
| 9734 | if (!tmp_list) { | 9811 | if (!tmp_list) { |
| 9735 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | 9812 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); |
| @@ -9739,6 +9816,7 @@ static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) · 3 unmodified lines | |||
| 9739 | tmp_list->bus = bp->pdev->bus->number; | 9816 | tmp_list->bus = bp->pdev->bus->number; |
| 9740 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | 9817 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); |
| 9741 | tmp_list->path = BP_PATH(bp); | 9818 | tmp_list->path = BP_PATH(bp); |
| 9819 | tmp_list->aer = 0; | ||
| 9742 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; | 9820 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; |
| 9743 | 9821 | ||
| 9744 | rc = down_interruptible(&bnx2x_prev_sem); | 9822 | rc = down_interruptible(&bnx2x_prev_sem); |
| @@ -9746,8 +9824,8 @@ static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) · 1 unmodified line | |||
| 9746 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | 9824 | BNX2X_ERR("Received %d when tried to take lock\n", rc); |
| 9747 | kfree(tmp_list); | 9825 | kfree(tmp_list); |
| 9748 | } else { | 9826 | } else { |
| 9749 | BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n", | 9827 | DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", |
| 9750 | BP_PATH(bp)); | 9828 | BP_PATH(bp)); |
| 9751 | list_add(&tmp_list->list, &bnx2x_prev_list); | 9829 | list_add(&tmp_list->list, &bnx2x_prev_list); |
| 9752 | up(&bnx2x_prev_sem); | 9830 | up(&bnx2x_prev_sem); |
| 9753 | } | 9831 | } |
| @@ -9990,6 +10068,7 @@ static int bnx2x_prev_unload(struct bnx2x *bp) · 236 unmodified lines | |||
| 9990 | } | 10068 | } |
| 9991 | 10069 | ||
| 9992 | do { | 10070 | do { |
| 10071 | int aer = 0; | ||
| 9993 | /* Lock MCP using an unload request */ | 10072 | /* Lock MCP using an unload request */ |
| 9994 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | 10073 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); |
| 9995 | if (!fw) { | 10074 | if (!fw) { |
| @@ -9998,7 +10077,18 @@ static int bnx2x_prev_unload(struct bnx2x *bp) · 2 unmodified lines | |||
| 9998 | break; | 10077 | break; |
| 9999 | } | 10078 | } |
| 10000 | 10079 | ||
| 10001 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { | 10080 | rc = down_interruptible(&bnx2x_prev_sem); |
| 10081 | if (rc) { | ||
| 10082 | BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", | ||
| 10083 | rc); | ||
| 10084 | } else { | ||
| 10085 | /* If Path is marked by EEH, ignore unload status */ | ||
| 10086 | aer = !!(bnx2x_prev_path_get_entry(bp) && | ||
| 10087 | bnx2x_prev_path_get_entry(bp)->aer); | ||
| 10088 | up(&bnx2x_prev_sem); | ||
| 10089 | } | ||
| 10090 | |||
| 10091 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { | ||
| 10002 | rc = bnx2x_prev_unload_common(bp); | 10092 | rc = bnx2x_prev_unload_common(bp); |
| 10003 | break; | 10093 | break; |
| 10004 | } | 10094 | } |
| @@ -10038,8 +10128,12 @@ static void bnx2x_get_common_hwinfo(struct bnx2x *bp) · 33 unmodified lines | |||
| 10038 | id = ((val & 0xffff) << 16); | 10128 | id = ((val & 0xffff) << 16); |
| 10039 | val = REG_RD(bp, MISC_REG_CHIP_REV); | 10129 | val = REG_RD(bp, MISC_REG_CHIP_REV); |
| 10040 | id |= ((val & 0xf) << 12); | 10130 | id |= ((val & 0xf) << 12); |
| 10041 | val = REG_RD(bp, MISC_REG_CHIP_METAL); | 10131 | |
| 10042 | id |= ((val & 0xff) << 4); | 10132 | /* Metal is read from PCI regs, but we can't access >=0x400 from |
| 10133 | * the configuration space (so we need to reg_rd) | ||
| 10134 | */ | ||
| 10135 | val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); | ||
| 10136 | id |= (((val >> 24) & 0xf) << 4); | ||
| 10043 | val = REG_RD(bp, MISC_REG_BOND_ID); | 10137 | val = REG_RD(bp, MISC_REG_BOND_ID); |
| 10044 | id |= (val & 0xf); | 10138 | id |= (val & 0xf); |
| 10045 | bp->common.chip_id = id; | 10139 | bp->common.chip_id = id; |
| @@ -10575,10 +10669,12 @@ static void bnx2x_get_port_hwinfo(struct bnx2x *bp) · 529 unmodified lines | |||
| 10575 | 10669 | ||
| 10576 | bp->link_params.speed_cap_mask[0] = | 10670 | bp->link_params.speed_cap_mask[0] = |
| 10577 | SHMEM_RD(bp, | 10671 | SHMEM_RD(bp, |
| 10578 | dev_info.port_hw_config[port].speed_capability_mask); | 10672 | dev_info.port_hw_config[port].speed_capability_mask) & |
| 10673 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | ||
| 10579 | bp->link_params.speed_cap_mask[1] = | 10674 | bp->link_params.speed_cap_mask[1] = |
| 10580 | SHMEM_RD(bp, | 10675 | SHMEM_RD(bp, |
| 10581 | dev_info.port_hw_config[port].speed_capability_mask2); | 10676 | dev_info.port_hw_config[port].speed_capability_mask2) & |
| 10677 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | ||
| 10582 | bp->port.link_config[0] = | 10678 | bp->port.link_config[0] = |
| 10583 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); | 10679 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
| 10584 | 10680 | ||
| @@ -10703,6 +10799,12 @@ static void bnx2x_get_fcoe_info(struct bnx2x *bp) · 118 unmodified lines | |||
| 10703 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | 10799 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> |
| 10704 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | 10800 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; |
| 10705 | 10801 | ||
| 10802 | /* Calculate the number of maximum allowed FCoE tasks */ | ||
| 10803 | bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; | ||
| 10804 | if (IS_MF(bp) || CHIP_MODE_IS_4_PORT(bp)) | ||
| 10805 | bp->cnic_eth_dev.max_fcoe_exchanges /= | ||
| 10806 | MAX_FCOE_FUNCS_PER_ENGINE; | ||
| 10807 | |||
| 10706 | /* Read the WWN: */ | 10808 | /* Read the WWN: */ |
| 10707 | if (!IS_MF(bp)) { | 10809 | if (!IS_MF(bp)) { |
| 10708 | /* Port info */ | 10810 | /* Port info */ |
| @@ -10816,14 +10918,12 @@ static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) · 107 unmodified lines | |||
| 10816 | } | 10918 | } |
| 10817 | } | 10919 | } |
| 10818 | 10920 | ||
| 10819 | if (IS_MF_STORAGE_SD(bp)) | 10921 | /* If this is a storage-only interface, use SAN mac as |
| 10820 | /* Zero primary MAC configuration */ | 10922 | * primary MAC. Notice that for SD this is already the case, |
| 10821 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | 10923 | * as the SAN mac was copied from the primary MAC. |
| 10822 | 10924 | */ | |
| 10823 | if (IS_MF_FCOE_AFEX(bp) || IS_MF_FCOE_SD(bp)) | 10925 | if (IS_MF_FCOE_AFEX(bp)) |
| 10824 | /* use FIP MAC as primary MAC */ | ||
| 10825 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); | 10926 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); |
| 10826 | |||
| 10827 | } else { | 10927 | } else { |
| 10828 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | 10928 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
| 10829 | iscsi_mac_upper); | 10929 | iscsi_mac_upper); |
| @@ -11060,6 +11160,9 @@ static int bnx2x_get_hwinfo(struct bnx2x *bp) · 230 unmodified lines | |||
| 11060 | } else | 11160 | } else |
| 11061 | BNX2X_DEV_INFO("illegal OV for SD\n"); | 11161 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
| 11062 | break; | 11162 | break; |
| 11163 | case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: | ||
| 11164 | bp->mf_config[vn] = 0; | ||
| 11165 | break; | ||
| 11063 | default: | 11166 | default: |
| 11064 | /* Unknown configuration: reset mf_config */ | 11167 | /* Unknown configuration: reset mf_config */ |
| 11065 | bp->mf_config[vn] = 0; | 11168 | bp->mf_config[vn] = 0; |
| @@ -11406,26 +11509,6 @@ static int bnx2x_init_bp(struct bnx2x *bp) · 340 unmodified lines | |||
| 11406 | * net_device service functions | 11509 | * net_device service functions |
| 11407 | */ | 11510 | */ |
| 11408 | 11511 | ||
| 11409 | static int bnx2x_open_epilog(struct bnx2x *bp) | ||
| 11410 | { | ||
| 11411 | /* Enable sriov via delayed work. This must be done via delayed work | ||
| 11412 | * because it causes the probe of the vf devices to be run, which invoke | ||
| 11413 | * register_netdevice which must have rtnl lock taken. As we are holding | ||
| 11414 | * the lock right now, that could only work if the probe would not take | ||
| 11415 | * the lock. However, as the probe of the vf may be called from other | ||
| 11416 | * contexts as well (such as passthrough to vm failes) it can't assume | ||
| 11417 | * the lock is being held for it. Using delayed work here allows the | ||
| 11418 | * probe code to simply take the lock (i.e. wait for it to be released | ||
| 11419 | * if it is being held). | ||
| 11420 | */ | ||
| 11421 | smp_mb__before_clear_bit(); | ||
| 11422 | set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, &bp->sp_rtnl_state); | ||
| 11423 | smp_mb__after_clear_bit(); | ||
| 11424 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | ||
| 11425 | |||
| 11426 | return 0; | ||
| 11427 | } | ||
| 11428 | |||
| 11429 | /* called with rtnl_lock */ | 11512 | /* called with rtnl_lock */ |
| 11430 | static int bnx2x_open(struct net_device *dev) | 11513 | static int bnx2x_open(struct net_device *dev) |
| 11431 | { | 11514 | { |
| @@ -11795,6 +11878,8 @@ static const struct net_device_ops bnx2x_netdev_ops = { · 363 unmodified lines | |||
| 11795 | .ndo_setup_tc = bnx2x_setup_tc, | 11878 | .ndo_setup_tc = bnx2x_setup_tc, |
| 11796 | #ifdef CONFIG_BNX2X_SRIOV | 11879 | #ifdef CONFIG_BNX2X_SRIOV |
| 11797 | .ndo_set_vf_mac = bnx2x_set_vf_mac, | 11880 | .ndo_set_vf_mac = bnx2x_set_vf_mac, |
| 11881 | .ndo_set_vf_vlan = bnx2x_set_vf_vlan, | ||
| 11882 | .ndo_get_vf_config = bnx2x_get_vf_config, | ||
| 11798 | #endif | 11883 | #endif |
| 11799 | #ifdef NETDEV_FCOE_WWNN | 11884 | #ifdef NETDEV_FCOE_WWNN |
| 11800 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, | 11885 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
| @@ -11957,19 +12042,26 @@ static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, · 156 unmodified lines | |||
| 11957 | dev->watchdog_timeo = TX_TIMEOUT; | 12042 | dev->watchdog_timeo = TX_TIMEOUT; |
| 11958 | 12043 | ||
| 11959 | dev->netdev_ops = &bnx2x_netdev_ops; | 12044 | dev->netdev_ops = &bnx2x_netdev_ops; |
| 11960 | bnx2x_set_ethtool_ops(dev); | 12045 | bnx2x_set_ethtool_ops(bp, dev); |
| 11961 | 12046 | ||
| 11962 | dev->priv_flags |= IFF_UNICAST_FLT; | 12047 | dev->priv_flags |= IFF_UNICAST_FLT; |
| 11963 | 12048 | ||
| 11964 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | 12049 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
| 11965 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | | 12050 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
| 11966 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | 12051 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | |
| 11967 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; | 12052 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; |
| 12053 | if (!CHIP_IS_E1x(bp)) { | ||
| 12054 | dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; | ||
| 12055 | dev->hw_enc_features = | ||
| 12056 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | ||
| 12057 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | | ||
| 12058 | NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; | ||
| 12059 | } | ||
| 11968 | 12060 | ||
| 11969 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | 12061 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
| 11970 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | 12062 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; |
| 11971 | 12063 | ||
| 11972 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; | 12064 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; |
| 11973 | if (bp->flags & USING_DAC_FLAG) | 12065 | if (bp->flags & USING_DAC_FLAG) |
| 11974 | dev->features |= NETIF_F_HIGHDMA; | 12066 | dev->features |= NETIF_F_HIGHDMA; |
| 11975 | 12067 | ||
| @@ -12451,7 +12543,7 @@ static int bnx2x_init_one(struct pci_dev *pdev, · 475 unmodified lines | |||
| 12451 | * l2 connections. | 12543 | * l2 connections. |
| 12452 | */ | 12544 | */ |
| 12453 | if (IS_VF(bp)) { | 12545 | if (IS_VF(bp)) { |
| 12454 | bnx2x_vf_map_doorbells(bp); | 12546 | bp->doorbells = bnx2x_vf_doorbells(bp); |
| 12455 | rc = bnx2x_vf_pci_alloc(bp); | 12547 | rc = bnx2x_vf_pci_alloc(bp); |
| 12456 | if (rc) | 12548 | if (rc) |
| 12457 | goto init_one_exit; | 12549 | goto init_one_exit; |
| @@ -12479,13 +12571,8 @@ static int bnx2x_init_one(struct pci_dev *pdev, · 21 unmodified lines | |||
| 12479 | goto init_one_exit; | 12571 | goto init_one_exit; |
| 12480 | } | 12572 | } |
| 12481 | 12573 | ||
| 12482 | /* Enable SRIOV if capability found in configuration space. | 12574 | /* Enable SRIOV if capability found in configuration space */ |
| 12483 | * Once the generic SR-IOV framework makes it in from the | 12575 | rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); |
| 12484 | * pci tree this will be revised, to allow dynamic control | ||
| 12485 | * over the number of VFs. Right now, change the num of vfs | ||
| 12486 | * param below to enable SR-IOV. | ||
| 12487 | */ | ||
| 12488 | rc = bnx2x_iov_init_one(bp, int_mode, 0/*num vfs*/); | ||
| 12489 | if (rc) | 12576 | if (rc) |
| 12490 | goto init_one_exit; | 12577 | goto init_one_exit; |
| 12491 | 12578 | ||
| @@ -12497,16 +12584,6 @@ static int bnx2x_init_one(struct pci_dev *pdev, · 5 unmodified lines | |||
| 12497 | if (CHIP_IS_E1x(bp)) | 12584 | if (CHIP_IS_E1x(bp)) |
| 12498 | bp->flags |= NO_FCOE_FLAG; | 12585 | bp->flags |= NO_FCOE_FLAG; |
| 12499 | 12586 | ||
| 12500 | /* disable FCOE for 57840 device, until FW supports it */ | ||
| 12501 | switch (ent->driver_data) { | ||
| 12502 | case BCM57840_O: | ||
| 12503 | case BCM57840_4_10: | ||
| 12504 | case BCM57840_2_20: | ||
| 12505 | case BCM57840_MFO: | ||
| 12506 | case BCM57840_MF: | ||
| 12507 | bp->flags |= NO_FCOE_FLAG; | ||
| 12508 | } | ||
| 12509 | |||
| 12510 | /* Set bp->num_queues for MSI-X mode*/ | 12587 | /* Set bp->num_queues for MSI-X mode*/ |
| 12511 | bnx2x_set_num_queues(bp); | 12588 | bnx2x_set_num_queues(bp); |
| 12512 | 12589 | ||
| @@ -12640,9 +12717,7 @@ static void bnx2x_remove_one(struct pci_dev *pdev) · 127 unmodified lines | |||
| 12640 | 12717 | ||
| 12641 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) | 12718 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
| 12642 | { | 12719 | { |
| 12643 | int i; | 12720 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; |
| 12644 | |||
| 12645 | bp->state = BNX2X_STATE_ERROR; | ||
| 12646 | 12721 | ||
| 12647 | bp->rx_mode = BNX2X_RX_MODE_NONE; | 12722 | bp->rx_mode = BNX2X_RX_MODE_NONE; |
| 12648 | 12723 | ||
| @@ -12651,29 +12726,21 @@ static int bnx2x_eeh_nic_unload(struct bnx2x *bp) · 2 unmodified lines | |||
| 12651 | 12726 | ||
| 12652 | /* Stop Tx */ | 12727 | /* Stop Tx */ |
| 12653 | bnx2x_tx_disable(bp); | 12728 | bnx2x_tx_disable(bp); |
| 12654 | |||
| 12655 | bnx2x_netif_stop(bp, 0); | ||
| 12656 | /* Delete all NAPI objects */ | 12729 | /* Delete all NAPI objects */ |
| 12657 | bnx2x_del_all_napi(bp); | 12730 | bnx2x_del_all_napi(bp); |
| 12658 | if (CNIC_LOADED(bp)) | 12731 | if (CNIC_LOADED(bp)) |
| 12659 | bnx2x_del_all_napi_cnic(bp); | 12732 | bnx2x_del_all_napi_cnic(bp); |
| 12733 | netdev_reset_tc(bp->dev); | ||
| 12660 | 12734 | ||
| 12661 | del_timer_sync(&bp->timer); | 12735 | del_timer_sync(&bp->timer); |
| 12736 | cancel_delayed_work(&bp->sp_task); | ||
| 12737 | cancel_delayed_work(&bp->period_task); | ||
| 12662 | 12738 | ||
| 12663 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | 12739 | spin_lock_bh(&bp->stats_lock); |
| 12664 | 12740 | bp->stats_state = STATS_STATE_DISABLED; | |
| 12665 | /* Release IRQs */ | 12741 | spin_unlock_bh(&bp->stats_lock); |
| 12666 | bnx2x_free_irq(bp); | ||
| 12667 | |||
| 12668 | /* Free SKBs, SGEs, TPA pool and driver internals */ | ||
| 12669 | bnx2x_free_skbs(bp); | ||
| 12670 | |||
| 12671 | for_each_rx_queue(bp, i) | ||
| 12672 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); | ||
| 12673 | |||
| 12674 | bnx2x_free_mem(bp); | ||
| 12675 | 12742 | ||
| 12676 | bp->state = BNX2X_STATE_CLOSED; | 12743 | bnx2x_save_statistics(bp); |
| 12677 | 12744 | ||
| 12678 | netif_carrier_off(bp->dev); | 12745 | netif_carrier_off(bp->dev); |
| 12679 | 12746 | ||
| @@ -12709,6 +12776,8 @@ static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, · 29 unmodified lines | |||
| 12709 | 12776 | ||
| 12710 | rtnl_lock(); | 12777 | rtnl_lock(); |
| 12711 | 12778 | ||
| 12779 | BNX2X_ERR("IO error detected\n"); | ||
| 12780 | |||
| 12712 | netif_device_detach(dev); | 12781 | netif_device_detach(dev); |
| 12713 | 12782 | ||
| 12714 | if (state == pci_channel_io_perm_failure) { | 12783 | if (state == pci_channel_io_perm_failure) { |
| @@ -12719,6 +12788,8 @@ static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, · 4 unmodified lines | |||
| 12719 | if (netif_running(dev)) | 12788 | if (netif_running(dev)) |
| 12720 | bnx2x_eeh_nic_unload(bp); | 12789 | bnx2x_eeh_nic_unload(bp); |
| 12721 | 12790 | ||
| 12791 | bnx2x_prev_path_mark_eeh(bp); | ||
| 12792 | |||
| 12722 | pci_disable_device(pdev); | 12793 | pci_disable_device(pdev); |
| 12723 | 12794 | ||
| 12724 | rtnl_unlock(); | 12795 | rtnl_unlock(); |
| @@ -12737,9 +12808,10 @@ static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) · 12 unmodified lines | |||
| 12737 | { | 12808 | { |
| 12738 | struct net_device *dev = pci_get_drvdata(pdev); | 12809 | struct net_device *dev = pci_get_drvdata(pdev); |
| 12739 | struct bnx2x *bp = netdev_priv(dev); | 12810 | struct bnx2x *bp = netdev_priv(dev); |
| 12811 | int i; | ||
| 12740 | 12812 | ||
| 12741 | rtnl_lock(); | 12813 | rtnl_lock(); |
| 12742 | 12814 | BNX2X_ERR("IO slot reset initializing...\n"); | |
| 12743 | if (pci_enable_device(pdev)) { | 12815 | if (pci_enable_device(pdev)) { |
| 12744 | dev_err(&pdev->dev, | 12816 | dev_err(&pdev->dev, |
| 12745 | "Cannot re-enable PCI device after reset\n"); | 12817 | "Cannot re-enable PCI device after reset\n"); |
| @@ -12749,10 +12821,47 @@ static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) · 3 unmodified lines | |||
| 12749 | 12821 | ||
| 12750 | pci_set_master(pdev); | 12822 | pci_set_master(pdev); |
| 12751 | pci_restore_state(pdev); | 12823 | pci_restore_state(pdev); |
| 12824 | pci_save_state(pdev); | ||
| 12752 | 12825 | ||
| 12753 | if (netif_running(dev)) | 12826 | if (netif_running(dev)) |
| 12754 | bnx2x_set_power_state(bp, PCI_D0); | 12827 | bnx2x_set_power_state(bp, PCI_D0); |
| 12755 | 12828 | ||
| 12829 | if (netif_running(dev)) { | ||
| 12830 | BNX2X_ERR("IO slot reset --> driver unload\n"); | ||
| 12831 | if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { | ||
| 12832 | u32 v; | ||
| 12833 | |||
| 12834 | v = SHMEM2_RD(bp, | ||
| 12835 | drv_capabilities_flag[BP_FW_MB_IDX(bp)]); | ||
| 12836 | SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], | ||
| 12837 | v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); | ||
| 12838 | } | ||
| 12839 | bnx2x_drain_tx_queues(bp); | ||
| 12840 | bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); | ||
| 12841 | bnx2x_netif_stop(bp, 1); | ||
| 12842 | bnx2x_free_irq(bp); | ||
| 12843 | |||
| 12844 | /* Report UNLOAD_DONE to MCP */ | ||
| 12845 | bnx2x_send_unload_done(bp, true); | ||
| 12846 | |||
| 12847 | bp->sp_state = 0; | ||
| 12848 | bp->port.pmf = 0; | ||
| 12849 | |||
| 12850 | bnx2x_prev_unload(bp); | ||
| 12851 | |||
| 12852 | /* We should have resetted the engine, so It's fair to | ||
| 12853 | * assume the FW will no longer write to the bnx2x driver. | ||
| 12854 | */ | ||
| 12855 | bnx2x_squeeze_objects(bp); | ||
| 12856 | bnx2x_free_skbs(bp); | ||
| 12857 | for_each_rx_queue(bp, i) | ||
| 12858 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); | ||
| 12859 | bnx2x_free_fp_mem(bp); | ||
| 12860 | bnx2x_free_mem(bp); | ||
| 12861 | |||
| 12862 | bp->state = BNX2X_STATE_CLOSED; | ||
| 12863 | } | ||
| 12864 | |||
| 12756 | rtnl_unlock(); | 12865 | rtnl_unlock(); |
| 12757 | 12866 | ||
| 12758 | return PCI_ERS_RESULT_RECOVERED; | 12867 | return PCI_ERS_RESULT_RECOVERED; |
| @@ -12779,6 +12888,9 @@ static void bnx2x_io_resume(struct pci_dev *pdev) · 20 unmodified lines | |||
| 12779 | 12888 | ||
| 12780 | bnx2x_eeh_recover(bp); | 12889 | bnx2x_eeh_recover(bp); |
| 12781 | 12890 | ||
| 12891 | bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | ||
| 12892 | DRV_MSG_SEQ_NUMBER_MASK; | ||
| 12893 | |||
| 12782 | if (netif_running(dev)) | 12894 | if (netif_running(dev)) |
| 12783 | bnx2x_nic_load(bp, LOAD_NORMAL); | 12895 | bnx2x_nic_load(bp, LOAD_NORMAL); |
| 12784 | 12896 | ||
| @@ -12801,6 +12913,9 @@ static struct pci_driver bnx2x_pci_driver = { · 16 unmodified lines | |||
| 12801 | .suspend = bnx2x_suspend, | 12913 | .suspend = bnx2x_suspend, |
| 12802 | .resume = bnx2x_resume, | 12914 | .resume = bnx2x_resume, |
| 12803 | .err_handler = &bnx2x_err_handler, | 12915 | .err_handler = &bnx2x_err_handler, |
| 12916 | #ifdef CONFIG_BNX2X_SRIOV | ||
| 12917 | .sriov_configure = bnx2x_sriov_configure, | ||
| 12918 | #endif | ||
| 12804 | }; | 12919 | }; |
| 12805 | 12920 | ||
| 12806 | static int __init bnx2x_init(void) | 12921 | static int __init bnx2x_init(void) |
| @@ -1491,10 +1491,6 @@ · 1490 unmodified lines | |||
| 1491 | /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 | 1491 | /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 |
| 1492 | Port. */ | 1492 | Port. */ |
| 1493 | #define MISC_REG_BOND_ID 0xa400 | 1493 | #define MISC_REG_BOND_ID 0xa400 |
| 1494 | /* [R 8] These bits indicate the metal revision of the chip. This value | ||
| 1495 | starts at 0x00 for each all-layer tape-out and increments by one for each | ||
| 1496 | tape-out. */ | ||
| 1497 | #define MISC_REG_CHIP_METAL 0xa404 | ||
| 1498 | /* [R 16] These bits indicate the part number for the chip. */ | 1494 | /* [R 16] These bits indicate the part number for the chip. */ |
| 1499 | #define MISC_REG_CHIP_NUM 0xa408 | 1495 | #define MISC_REG_CHIP_NUM 0xa408 |
| 1500 | /* [R 4] These bits indicate the base revision of the chip. This value | 1496 | /* [R 4] These bits indicate the base revision of the chip. This value |
| @@ -6331,6 +6327,8 @@ · 4830 unmodified lines | |||
| 6331 | #define PCI_PM_DATA_B 0x414 | 6327 | #define PCI_PM_DATA_B 0x414 |
| 6332 | #define PCI_ID_VAL1 0x434 | 6328 | #define PCI_ID_VAL1 0x434 |
| 6333 | #define PCI_ID_VAL2 0x438 | 6329 | #define PCI_ID_VAL2 0x438 |
| 6330 | #define PCI_ID_VAL3 0x43c | ||
| 6331 | |||
| 6334 | #define GRC_CONFIG_REG_PF_INIT_VF 0x624 | 6332 | #define GRC_CONFIG_REG_PF_INIT_VF 0x624 |
| 6335 | #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xf | 6333 | #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xf |
| 6336 | /* First VF_NUM for PF is encoded in this register. | 6334 | /* First VF_NUM for PF is encoded in this register. |
| @@ -30,8 +30,6 @@ · 29 unmodified lines | |||
| 30 | 30 | ||
| 31 | #define BNX2X_MAX_EMUL_MULTI 16 | 31 | #define BNX2X_MAX_EMUL_MULTI 16 |
| 32 | 32 | ||
| 33 | #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) | ||
| 34 | |||
| 35 | /**** Exe Queue interfaces ****/ | 33 | /**** Exe Queue interfaces ****/ |
| 36 | 34 | ||
| 37 | /** | 35 | /** |
| @@ -444,30 +442,21 @@ static bool bnx2x_put_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o) · 406 unmodified lines | |||
| 444 | } | 442 | } |
| 445 | 443 | ||
| 446 | static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, | 444 | static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, |
| 447 | int n, u8 *buf) | 445 | int n, u8 *base, u8 stride, u8 size) |
| 448 | { | 446 | { |
| 449 | struct bnx2x_vlan_mac_registry_elem *pos; | 447 | struct bnx2x_vlan_mac_registry_elem *pos; |
| 450 | u8 *next = buf; | 448 | u8 *next = base; |
| 451 | int counter = 0; | 449 | int counter = 0; |
| 452 | 450 | ||
| 453 | /* traverse list */ | 451 | /* traverse list */ |
| 454 | list_for_each_entry(pos, &o->head, link) { | 452 | list_for_each_entry(pos, &o->head, link) { |
| 455 | if (counter < n) { | 453 | if (counter < n) { |
| 456 | /* place leading zeroes in buffer */ | 454 | memcpy(next, &pos->u, size); |
| 457 | memset(next, 0, MAC_LEADING_ZERO_CNT); | ||
| 458 | |||
| 459 | /* place mac after leading zeroes*/ | ||
| 460 | memcpy(next + MAC_LEADING_ZERO_CNT, pos->u.mac.mac, | ||
| 461 | ETH_ALEN); | ||
| 462 | |||
| 463 | /* calculate address of next element and | ||
| 464 | * advance counter | ||
| 465 | */ | ||
| 466 | counter++; | 455 | counter++; |
| 467 | next = buf + counter * ALIGN(ETH_ALEN, sizeof(u32)); | 456 | DP(BNX2X_MSG_SP, "copied element number %d to address %p element was:\n", |
| 457 | counter, next); | ||
| 458 | next += stride + size; | ||
| 468 | 459 | ||
| 469 | DP(BNX2X_MSG_SP, "copied element number %d to address %p element was %pM\n", | ||
| 470 | counter, next, pos->u.mac.mac); | ||
| 471 | } | 460 | } |
| 472 | } | 461 | } |
| 473 | return counter * ETH_ALEN; | 462 | return counter * ETH_ALEN; |
| @@ -487,7 +476,8 @@ static int bnx2x_check_mac_add(struct bnx2x *bp, · 13 unmodified lines | |||
| 487 | 476 | ||
| 488 | /* Check if a requested MAC already exists */ | 477 | /* Check if a requested MAC already exists */ |
| 489 | list_for_each_entry(pos, &o->head, link) | 478 | list_for_each_entry(pos, &o->head, link) |
| 490 | if (!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN)) | 479 | if (!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN) && |
| 480 | (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) | ||
| 491 | return -EEXIST; | 481 | return -EEXIST; |
| 492 | 482 | ||
| 493 | return 0; | 483 | return 0; |
| @@ -520,7 +510,9 @@ static int bnx2x_check_vlan_mac_add(struct bnx2x *bp, · 26 unmodified lines | |||
| 520 | list_for_each_entry(pos, &o->head, link) | 510 | list_for_each_entry(pos, &o->head, link) |
| 521 | if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && | 511 | if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && |
| 522 | (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac, | 512 | (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac, |
| 523 | ETH_ALEN))) | 513 | ETH_ALEN)) && |
| 514 | (data->vlan_mac.is_inner_mac == | ||
| 515 | pos->u.vlan_mac.is_inner_mac)) | ||
| 524 | return -EEXIST; | 516 | return -EEXIST; |
| 525 | 517 | ||
| 526 | return 0; | 518 | return 0; |
| @@ -538,7 +530,8 @@ static struct bnx2x_vlan_mac_registry_elem * · 11 unmodified lines | |||
| 538 | DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac); | 530 | DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac); |
| 539 | 531 | ||
| 540 | list_for_each_entry(pos, &o->head, link) | 532 | list_for_each_entry(pos, &o->head, link) |
| 541 | if (!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN)) | 533 | if ((!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN)) && |
| 534 | (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) | ||
| 542 | return pos; | 535 | return pos; |
| 543 | 536 | ||
| 544 | return NULL; | 537 | return NULL; |
| @@ -573,7 +566,9 @@ static struct bnx2x_vlan_mac_registry_elem * · 28 unmodified lines | |||
| 573 | list_for_each_entry(pos, &o->head, link) | 566 | list_for_each_entry(pos, &o->head, link) |
| 574 | if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && | 567 | if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && |
| 575 | (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac, | 568 | (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac, |
| 576 | ETH_ALEN))) | 569 | ETH_ALEN)) && |
| 570 | (data->vlan_mac.is_inner_mac == | ||
| 571 | pos->u.vlan_mac.is_inner_mac)) | ||
| 577 | return pos; | 572 | return pos; |
| 578 | 573 | ||
| 579 | return NULL; | 574 | return NULL; |
| @@ -770,6 +765,8 @@ static void bnx2x_set_one_mac_e2(struct bnx2x *bp, · 190 unmodified lines | |||
| 770 | bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, | 765 | bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, |
| 771 | &rule_entry->mac.mac_mid, | 766 | &rule_entry->mac.mac_mid, |
| 772 | &rule_entry->mac.mac_lsb, mac); | 767 | &rule_entry->mac.mac_lsb, mac); |
| 768 | rule_entry->mac.inner_mac = | ||
| 769 | cpu_to_le16(elem->cmd_data.vlan_mac.u.mac.is_inner_mac); | ||
| 773 | 770 | ||
| 774 | /* MOVE: Add a rule that will add this MAC to the target Queue */ | 771 | /* MOVE: Add a rule that will add this MAC to the target Queue */ |
| 775 | if (cmd == BNX2X_VLAN_MAC_MOVE) { | 772 | if (cmd == BNX2X_VLAN_MAC_MOVE) { |
| @@ -786,6 +783,9 @@ static void bnx2x_set_one_mac_e2(struct bnx2x *bp, · 10 unmodified lines | |||
| 786 | bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, | 783 | bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, |
| 787 | &rule_entry->mac.mac_mid, | 784 | &rule_entry->mac.mac_mid, |
| 788 | &rule_entry->mac.mac_lsb, mac); | 785 | &rule_entry->mac.mac_lsb, mac); |
| 786 | rule_entry->mac.inner_mac = | ||
| 787 | cpu_to_le16(elem->cmd_data.vlan_mac. | ||
| 788 | u.mac.is_inner_mac); | ||
| 789 | } | 789 | } |
| 790 | 790 | ||
| 791 | /* Set the ramrod data header */ | 791 | /* Set the ramrod data header */ |
| @@ -974,7 +974,8 @@ static void bnx2x_set_one_vlan_mac_e2(struct bnx2x *bp, · 182 unmodified lines | |||
| 974 | bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb, | 974 | bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb, |
| 975 | &rule_entry->pair.mac_mid, | 975 | &rule_entry->pair.mac_mid, |
| 976 | &rule_entry->pair.mac_lsb, mac); | 976 | &rule_entry->pair.mac_lsb, mac); |
| 977 | 977 | rule_entry->pair.inner_mac = | |
| 978 | cpu_to_le16(elem->cmd_data.vlan_mac.u.vlan_mac.is_inner_mac); | ||
| 978 | /* MOVE: Add a rule that will add this MAC to the target Queue */ | 979 | /* MOVE: Add a rule that will add this MAC to the target Queue */ |
| 979 | if (cmd == BNX2X_VLAN_MAC_MOVE) { | 980 | if (cmd == BNX2X_VLAN_MAC_MOVE) { |
| 980 | rule_entry++; | 981 | rule_entry++; |
| @@ -991,6 +992,9 @@ static void bnx2x_set_one_vlan_mac_e2(struct bnx2x *bp, · 10 unmodified lines | |||
| 991 | bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb, | 992 | bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb, |
| 992 | &rule_entry->pair.mac_mid, | 993 | &rule_entry->pair.mac_mid, |
| 993 | &rule_entry->pair.mac_lsb, mac); | 994 | &rule_entry->pair.mac_lsb, mac); |
| 995 | rule_entry->pair.inner_mac = | ||
| 996 | cpu_to_le16(elem->cmd_data.vlan_mac.u. | ||
| 997 | vlan_mac.is_inner_mac); | ||
| 994 | } | 998 | } |
| 995 | 999 | ||
| 996 | /* Set the ramrod data header */ | 1000 | /* Set the ramrod data header */ |
| @@ -1854,6 +1858,7 @@ static int bnx2x_vlan_mac_del_all(struct bnx2x *bp, · 857 unmodified lines | |||
| 1854 | return rc; | 1858 | return rc; |
| 1855 | } | 1859 | } |
| 1856 | list_del(&exeq_pos->link); | 1860 | list_del(&exeq_pos->link); |
| 1861 | bnx2x_exe_queue_free_elem(bp, exeq_pos); | ||
| 1857 | } | 1862 | } |
| 1858 | } | 1863 | } |
| 1859 | 1864 | ||
| @@ -2012,6 +2017,7 @@ void bnx2x_init_vlan_obj(struct bnx2x *bp, · 152 unmodified lines | |||
| 2012 | vlan_obj->check_move = bnx2x_check_move; | 2017 | vlan_obj->check_move = bnx2x_check_move; |
| 2013 | vlan_obj->ramrod_cmd = | 2018 | vlan_obj->ramrod_cmd = |
| 2014 | RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; | 2019 | RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; |
| 2020 | vlan_obj->get_n_elements = bnx2x_get_n_elements; | ||
| 2015 | 2021 | ||
| 2016 | /* Exe Queue */ | 2022 | /* Exe Queue */ |
| 2017 | bnx2x_exe_queue_init(bp, | 2023 | bnx2x_exe_queue_init(bp, |
| @@ -4426,6 +4432,12 @@ static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o, · 2408 unmodified lines | |||
| 4426 | tx_data->force_default_pri_flg = | 4432 | tx_data->force_default_pri_flg = |
| 4427 | test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags); | 4433 | test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags); |
| 4428 | 4434 | ||
| 4435 | tx_data->tunnel_lso_inc_ip_id = | ||
| 4436 | test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags); | ||
| 4437 | tx_data->tunnel_non_lso_pcsum_location = | ||
| 4438 | test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? PCSUM_ON_PKT : | ||
| 4439 | PCSUM_ON_BD; | ||
| 4440 | |||
| 4429 | tx_data->tx_status_block_id = params->fw_sb_id; | 4441 | tx_data->tx_status_block_id = params->fw_sb_id; |
| 4430 | tx_data->tx_sb_index_number = params->sb_cq_index; | 4442 | tx_data->tx_sb_index_number = params->sb_cq_index; |
| 4431 | tx_data->tss_leading_client_id = params->tss_leading_cl_id; | 4443 | tx_data->tss_leading_client_id = params->tss_leading_cl_id; |
| @@ -5669,17 +5681,18 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp, · 1237 unmodified lines | |||
| 5669 | memset(rdata, 0, sizeof(*rdata)); | 5681 | memset(rdata, 0, sizeof(*rdata)); |
| 5670 | 5682 | ||
| 5671 | /* Fill the ramrod data with provided parameters */ | 5683 | /* Fill the ramrod data with provided parameters */ |
| 5672 | rdata->function_mode = (u8)start_params->mf_mode; | 5684 | rdata->function_mode = (u8)start_params->mf_mode; |
| 5673 | rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag); | 5685 | rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag); |
| 5674 | rdata->path_id = BP_PATH(bp); | 5686 | rdata->path_id = BP_PATH(bp); |
| 5675 | rdata->network_cos_mode = start_params->network_cos_mode; | 5687 | rdata->network_cos_mode = start_params->network_cos_mode; |
| 5676 | 5688 | rdata->gre_tunnel_mode = start_params->gre_tunnel_mode; | |
| 5677 | /* | 5689 | rdata->gre_tunnel_rss = start_params->gre_tunnel_rss; |
| 5678 | * No need for an explicit memory barrier here as long we would | 5690 | |
| 5679 | * need to ensure the ordering of writing to the SPQ element | 5691 | /* No need for an explicit memory barrier here as long we would |
| 5680 | * and updating of the SPQ producer which involves a memory | 5692 | * need to ensure the ordering of writing to the SPQ element |
| 5681 | * read and we will have to put a full memory barrier there | 5693 | * and updating of the SPQ producer which involves a memory |
| 5682 | * (inside bnx2x_sp_post()). | 5694 | * read and we will have to put a full memory barrier there |
| 5695 | * (inside bnx2x_sp_post()). | ||
| 5683 | */ | 5696 | */ |
| 5684 | 5697 | ||
| 5685 | return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, | 5698 | return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, |
| @@ -100,6 +100,7 @@ struct bnx2x_raw_obj { · 99 unmodified lines | |||
| 100 | /************************* VLAN-MAC commands related parameters ***************/ | 100 | /************************* VLAN-MAC commands related parameters ***************/ |
| 101 | struct bnx2x_mac_ramrod_data { | 101 | struct bnx2x_mac_ramrod_data { |
| 102 | u8 mac[ETH_ALEN]; | 102 | u8 mac[ETH_ALEN]; |
| 103 | u8 is_inner_mac; | ||
| 103 | }; | 104 | }; |
| 104 | 105 | ||
| 105 | struct bnx2x_vlan_ramrod_data { | 106 | struct bnx2x_vlan_ramrod_data { |
| @@ -108,6 +109,7 @@ struct bnx2x_vlan_ramrod_data { · 2 unmodified lines | |||
| 108 | 109 | ||
| 109 | struct bnx2x_vlan_mac_ramrod_data { | 110 | struct bnx2x_vlan_mac_ramrod_data { |
| 110 | u8 mac[ETH_ALEN]; | 111 | u8 mac[ETH_ALEN]; |
| 112 | u8 is_inner_mac; | ||
| 111 | u16 vlan; | 113 | u16 vlan; |
| 112 | }; | 114 | }; |
| 113 | 115 | ||
| @@ -313,8 +315,9 @@ struct bnx2x_vlan_mac_obj { · 199 unmodified lines | |||
| 313 | * | 315 | * |
| 314 | * @return number of copied bytes | 316 | * @return number of copied bytes |
| 315 | */ | 317 | */ |
| 316 | int (*get_n_elements)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, | 318 | int (*get_n_elements)(struct bnx2x *bp, |
| 317 | int n, u8 *buf); | 319 | struct bnx2x_vlan_mac_obj *o, int n, u8 *base, |
| 320 | u8 stride, u8 size); | ||
| 318 | 321 | ||
| 319 | /** | 322 | /** |
| 320 | * Checks if ADD-ramrod with the given params may be performed. | 323 | * Checks if ADD-ramrod with the given params may be performed. |
| @@ -824,7 +827,9 @@ enum { · 503 unmodified lines | |||
| 824 | BNX2X_Q_FLG_TX_SEC, | 827 | BNX2X_Q_FLG_TX_SEC, |
| 825 | BNX2X_Q_FLG_ANTI_SPOOF, | 828 | BNX2X_Q_FLG_ANTI_SPOOF, |
| 826 | BNX2X_Q_FLG_SILENT_VLAN_REM, | 829 | BNX2X_Q_FLG_SILENT_VLAN_REM, |
| 827 | BNX2X_Q_FLG_FORCE_DEFAULT_PRI | 830 | BNX2X_Q_FLG_FORCE_DEFAULT_PRI, |
| 831 | BNX2X_Q_FLG_PCSUM_ON_PKT, | ||
| 832 | BNX2X_Q_FLG_TUN_INC_INNER_IP_ID | ||
| 828 | }; | 833 | }; |
| 829 | 834 | ||
| 830 | /* Queue type options: queue type may be a compination of below. */ | 835 | /* Queue type options: queue type may be a compination of below. */ |
| @@ -842,6 +847,7 @@ enum bnx2x_q_type { · 11 unmodified lines | |||
| 842 | #define BNX2X_MULTI_TX_COS_E3B0 3 | 847 | #define BNX2X_MULTI_TX_COS_E3B0 3 |
| 843 | #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ | 848 | #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ |
| 844 | 849 | ||
| 850 | #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) | ||
| 845 | 851 | ||
| 846 | struct bnx2x_queue_init_params { | 852 | struct bnx2x_queue_init_params { |
| 847 | struct { | 853 | struct { |
| @@ -1118,6 +1124,15 @@ struct bnx2x_func_start_params { · 270 unmodified lines | |||
| 1118 | 1124 | ||
| 1119 | /* Function cos mode */ | 1125 | /* Function cos mode */ |
| 1120 | u8 network_cos_mode; | 1126 | u8 network_cos_mode; |
| 1127 | |||
| 1128 | /* NVGRE classification enablement */ | ||
| 1129 | u8 nvgre_clss_en; | ||
| 1130 | |||
| 1131 | /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ | ||
| 1132 | u8 gre_tunnel_mode; | ||
| 1133 | |||
| 1134 | /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */ | ||
| 1135 | u8 gre_tunnel_rss; | ||
| 1121 | }; | 1136 | }; |
| 1122 | 1137 | ||
| 1123 | struct bnx2x_func_switch_update_params { | 1138 | struct bnx2x_func_switch_update_params { |
| @@ -20,7 +20,9 @@ · 19 unmodified lines | |||
| 20 | #include "bnx2x.h" | 20 | #include "bnx2x.h" |
| 21 | #include "bnx2x_init.h" | 21 | #include "bnx2x_init.h" |
| 22 | #include "bnx2x_cmn.h" | 22 | #include "bnx2x_cmn.h" |
| 23 | #include "bnx2x_sp.h" | ||
| 23 | #include <linux/crc32.h> | 24 | #include <linux/crc32.h> |
| 25 | #include <linux/if_vlan.h> | ||
| 24 | 26 | ||
| 25 | /* General service functions */ | 27 | /* General service functions */ |
| 26 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, | 28 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
| @@ -555,8 +557,7 @@ static int bnx2x_vfop_config_list(struct bnx2x *bp, · 528 unmodified lines | |||
| 555 | rc = bnx2x_config_vlan_mac(bp, vlan_mac); | 557 | rc = bnx2x_config_vlan_mac(bp, vlan_mac); |
| 556 | if (rc >= 0) { | 558 | if (rc >= 0) { |
| 557 | cnt += pos->add ? 1 : -1; | 559 | cnt += pos->add ? 1 : -1; |
| 558 | list_del(&pos->link); | 560 | list_move(&pos->link, &rollback_list); |
| 559 | list_add(&pos->link, &rollback_list); | ||
| 560 | rc = 0; | 561 | rc = 0; |
| 561 | } else if (rc == -EEXIST) { | 562 | } else if (rc == -EEXIST) { |
| 562 | rc = 0; | 563 | rc = 0; |
| @@ -958,6 +959,12 @@ op_err: · 395 unmodified lines | |||
| 958 | BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, vfop->rc); | 959 | BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, vfop->rc); |
| 959 | op_done: | 960 | op_done: |
| 960 | case BNX2X_VFOP_QSETUP_DONE: | 961 | case BNX2X_VFOP_QSETUP_DONE: |
| 962 | vf->cfg_flags |= VF_CFG_VLAN; | ||
| 963 | smp_mb__before_clear_bit(); | ||
| 964 | set_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, | ||
| 965 | &bp->sp_rtnl_state); | ||
| 966 | smp_mb__after_clear_bit(); | ||
| 967 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | ||
| 961 | bnx2x_vfop_end(bp, vf, vfop); | 968 | bnx2x_vfop_end(bp, vf, vfop); |
| 962 | return; | 969 | return; |
| 963 | default: | 970 | default: |
| @@ -1459,7 +1466,6 @@ static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid) · 495 unmodified lines | |||
| 1459 | return bnx2x_is_pcie_pending(dev); | 1466 | return bnx2x_is_pcie_pending(dev); |
| 1460 | 1467 | ||
| 1461 | unknown_dev: | 1468 | unknown_dev: |
| 1462 | BNX2X_ERR("Unknown device\n"); | ||
| 1463 | return false; | 1469 | return false; |
| 1464 | } | 1470 | } |
| 1465 | 1471 | ||
| @@ -1926,20 +1932,22 @@ int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, · 460 unmodified lines | |||
| 1926 | 1932 | ||
| 1927 | /* SRIOV can be enabled only with MSIX */ | 1933 | /* SRIOV can be enabled only with MSIX */ |
| 1928 | if (int_mode_param == BNX2X_INT_MODE_MSI || | 1934 | if (int_mode_param == BNX2X_INT_MODE_MSI || |
| 1929 | int_mode_param == BNX2X_INT_MODE_INTX) | 1935 | int_mode_param == BNX2X_INT_MODE_INTX) { |
| 1930 | BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n"); | 1936 | BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n"); |
| 1937 | return 0; | ||
| 1938 | } | ||
| 1931 | 1939 | ||
| 1932 | err = -EIO; | 1940 | err = -EIO; |
| 1933 | /* verify ari is enabled */ | 1941 | /* verify ari is enabled */ |
| 1934 | if (!bnx2x_ari_enabled(bp->pdev)) { | 1942 | if (!bnx2x_ari_enabled(bp->pdev)) { |
| 1935 | BNX2X_ERR("ARI not supported, SRIOV can not be enabled\n"); | 1943 | BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n"); |
| 1936 | return err; | 1944 | return 0; |
| 1937 | } | 1945 | } |
| 1938 | 1946 | ||
| 1939 | /* verify igu is in normal mode */ | 1947 | /* verify igu is in normal mode */ |
| 1940 | if (CHIP_INT_MODE_IS_BC(bp)) { | 1948 | if (CHIP_INT_MODE_IS_BC(bp)) { |
| 1941 | BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n"); | 1949 | BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n"); |
| 1942 | return err; | 1950 | return 0; |
| 1943 | } | 1951 | } |
| 1944 | 1952 | ||
| 1945 | /* allocate the vfs database */ | 1953 | /* allocate the vfs database */ |
| @@ -1964,8 +1972,10 @@ int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, · 18 unmodified lines | |||
| 1964 | if (iov->total == 0) | 1972 | if (iov->total == 0) |
| 1965 | goto failed; | 1973 | goto failed; |
| 1966 | 1974 | ||
| 1967 | /* calculate the actual number of VFs */ | 1975 | iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param); |
| 1968 | iov->nr_virtfn = min_t(u16, iov->total, (u16)num_vfs_param); | 1976 | |
| 1977 | DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n", | ||
| 1978 | num_vfs_param, iov->nr_virtfn); | ||
| 1969 | 1979 | ||
| 1970 | /* allocate the vf array */ | 1980 | /* allocate the vf array */ |
| 1971 | bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) * | 1981 | bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) * |
| @@ -2378,8 +2388,8 @@ int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem) · 406 unmodified lines | |||
| 2378 | goto get_vf; | 2388 | goto get_vf; |
| 2379 | case EVENT_RING_OPCODE_MALICIOUS_VF: | 2389 | case EVENT_RING_OPCODE_MALICIOUS_VF: |
| 2380 | abs_vfid = elem->message.data.malicious_vf_event.vf_id; | 2390 | abs_vfid = elem->message.data.malicious_vf_event.vf_id; |
| 2381 | DP(BNX2X_MSG_IOV, "Got VF MALICIOUS notification abs_vfid=%d\n", | 2391 | DP(BNX2X_MSG_IOV, "Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n", |
| 2382 | abs_vfid); | 2392 | abs_vfid, elem->message.data.malicious_vf_event.err_id); |
| 2383 | goto get_vf; | 2393 | goto get_vf; |
| 2384 | default: | 2394 | default: |
| 2385 | return 1; | 2395 | return 1; |
| @@ -2436,8 +2446,8 @@ get_vf: · 50 unmodified lines | |||
| 2436 | /* Do nothing for now */ | 2446 | /* Do nothing for now */ |
| 2437 | break; | 2447 | break; |
| 2438 | case EVENT_RING_OPCODE_MALICIOUS_VF: | 2448 | case EVENT_RING_OPCODE_MALICIOUS_VF: |
| 2439 | DP(BNX2X_MSG_IOV, "got VF [%d] MALICIOUS notification\n", | 2449 | DP(BNX2X_MSG_IOV, "Got VF MALICIOUS notification abs_vfid=%d error id %x\n", |
| 2440 | vf->abs_vfid); | 2450 | abs_vfid, elem->message.data.malicious_vf_event.err_id); |
| 2441 | /* Do nothing for now */ | 2451 | /* Do nothing for now */ |
| 2442 | break; | 2452 | break; |
| 2443 | } | 2453 | } |
| @@ -3012,21 +3022,138 @@ void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, · 568 unmodified lines | |||
| 3012 | vf->op_current = CHANNEL_TLV_NONE; | 3022 | vf->op_current = CHANNEL_TLV_NONE; |
| 3013 | } | 3023 | } |
| 3014 | 3024 | ||
| 3015 | void bnx2x_enable_sriov(struct bnx2x *bp) | 3025 | int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param) |
| 3016 | { | 3026 | { |
| 3017 | int rc = 0; | ||
| 3018 | 3027 | ||
| 3019 | /* disbale sriov in case it is still enabled */ | 3028 | struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev)); |
| 3029 | |||
| 3030 | DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n", | ||
| 3031 | num_vfs_param, BNX2X_NR_VIRTFN(bp)); | ||
| 3032 | |||
| 3033 | /* HW channel is only operational when PF is up */ | ||
| 3034 | if (bp->state != BNX2X_STATE_OPEN) { | ||
| 3035 | BNX2X_ERR("VF num configurtion via sysfs not supported while PF is down"); | ||
| 3036 | return -EINVAL; | ||
| 3037 | } | ||
| 3038 | |||
| 3039 | /* we are always bound by the total_vfs in the configuration space */ | ||
| 3040 | if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) { | ||
| 3041 | BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n", | ||
| 3042 | num_vfs_param, BNX2X_NR_VIRTFN(bp)); | ||
| 3043 | num_vfs_param = BNX2X_NR_VIRTFN(bp); | ||
| 3044 | } | ||
| 3045 | |||
| 3046 | bp->requested_nr_virtfn = num_vfs_param; | ||
| 3047 | if (num_vfs_param == 0) { | ||
| 3048 | pci_disable_sriov(dev); | ||
| 3049 | return 0; | ||
| 3050 | } else { | ||
| 3051 | return bnx2x_enable_sriov(bp); | ||
| 3052 | } | ||
| 3053 | } | ||
| 3054 | |||
| 3055 | int bnx2x_enable_sriov(struct bnx2x *bp) | ||
| 3056 | { | ||
| 3057 | int rc = 0, req_vfs = bp->requested_nr_virtfn; | ||
| 3058 | |||
| 3059 | rc = pci_enable_sriov(bp->pdev, req_vfs); | ||
| 3060 | if (rc) { | ||
| 3061 | BNX2X_ERR("pci_enable_sriov failed with %d\n", rc); | ||
| 3062 | return rc; | ||
| 3063 | } | ||
| 3064 | DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs); | ||
| 3065 | return req_vfs; | ||
| 3066 | } | ||
| 3067 | |||
| 3068 | void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp) | ||
| 3069 | { | ||
| 3070 | int vfidx; | ||
| 3071 | struct pf_vf_bulletin_content *bulletin; | ||
| 3072 | |||
| 3073 | DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n"); | ||
| 3074 | for_each_vf(bp, vfidx) { | ||
| 3075 | bulletin = BP_VF_BULLETIN(bp, vfidx); | ||
| 3076 | if (BP_VF(bp, vfidx)->cfg_flags & VF_CFG_VLAN) | ||
| 3077 | bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0); | ||
| 3078 | } | ||
| 3079 | } | ||
| 3080 | |||
| 3081 | void bnx2x_disable_sriov(struct bnx2x *bp) | ||
| 3082 | { | ||
| 3020 | pci_disable_sriov(bp->pdev); | 3083 | pci_disable_sriov(bp->pdev); |
| 3021 | DP(BNX2X_MSG_IOV, "sriov disabled\n"); | 3084 | } |
| 3085 | |||
| 3086 | static int bnx2x_vf_ndo_sanity(struct bnx2x *bp, int vfidx, | ||
| 3087 | struct bnx2x_virtf *vf) | ||
| 3088 | { | ||
| 3089 | if (!IS_SRIOV(bp)) { | ||
| 3090 | BNX2X_ERR("vf ndo called though sriov is disabled\n"); | ||
| 3091 | return -EINVAL; | ||
| 3092 | } | ||
| 3093 | |||
| 3094 | if (vfidx >= BNX2X_NR_VIRTFN(bp)) { | ||
| 3095 | BNX2X_ERR("vf ndo called for uninitialized VF. vfidx was %d BNX2X_NR_VIRTFN was %d\n", | ||
| 3096 | vfidx, BNX2X_NR_VIRTFN(bp)); | ||
| 3097 | return -EINVAL; | ||
| 3098 | } | ||
| 3099 | |||
| 3100 | if (!vf) { | ||
| 3101 | BNX2X_ERR("vf ndo called but vf was null. vfidx was %d\n", | ||
| 3102 | vfidx); | ||
| 3103 | return -EINVAL; | ||
| 3104 | } | ||
| 3022 | 3105 | ||
| 3023 | /* enable sriov */ | 3106 | return 0; |
| 3024 | DP(BNX2X_MSG_IOV, "vf num (%d)\n", (bp->vfdb->sriov.nr_virtfn)); | 3107 | } |
| 3025 | rc = pci_enable_sriov(bp->pdev, (bp->vfdb->sriov.nr_virtfn)); | 3108 | |
| 3109 | int bnx2x_get_vf_config(struct net_device *dev, int vfidx, | ||
| 3110 | struct ifla_vf_info *ivi) | ||
| 3111 | { | ||
| 3112 | struct bnx2x *bp = netdev_priv(dev); | ||
| 3113 | struct bnx2x_virtf *vf = BP_VF(bp, vfidx); | ||
| 3114 | struct bnx2x_vlan_mac_obj *mac_obj = &bnx2x_vfq(vf, 0, mac_obj); | ||
| 3115 | struct bnx2x_vlan_mac_obj *vlan_obj = &bnx2x_vfq(vf, 0, vlan_obj); | ||
| 3116 | struct pf_vf_bulletin_content *bulletin = BP_VF_BULLETIN(bp, vfidx); | ||
| 3117 | int rc; | ||
| 3118 | |||
| 3119 | /* sanity */ | ||
| 3120 | rc = bnx2x_vf_ndo_sanity(bp, vfidx, vf); | ||
| 3026 | if (rc) | 3121 | if (rc) |
| 3027 | BNX2X_ERR("pci_enable_sriov failed with %d\n", rc); | 3122 | return rc; |
| 3028 | else | 3123 | if (!mac_obj || !vlan_obj || !bulletin) { |
| 3029 | DP(BNX2X_MSG_IOV, "sriov enabled\n"); | 3124 | BNX2X_ERR("VF partially initialized\n"); |
| 3125 | return -EINVAL; | ||
| 3126 | } | ||
| 3127 | |||
| 3128 | ivi->vf = vfidx; | ||
| 3129 | ivi->qos = 0; | ||
| 3130 | ivi->tx_rate = 10000; /* always 10G. TBA take from link struct */ | ||
| 3131 | ivi->spoofchk = 1; /*always enabled */ | ||
| 3132 | if (vf->state == VF_ENABLED) { | ||
| 3133 | /* mac and vlan are in vlan_mac objects */ | ||
| 3134 | mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac, | ||
| 3135 | 0, ETH_ALEN); | ||
| 3136 | vlan_obj->get_n_elements(bp, vlan_obj, 1, (u8 *)&ivi->vlan, | ||
| 3137 | 0, VLAN_HLEN); | ||
| 3138 | } else { | ||
| 3139 | /* mac */ | ||
| 3140 | if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID)) | ||
| 3141 | /* mac configured by ndo so its in bulletin board */ | ||
| 3142 | memcpy(&ivi->mac, bulletin->mac, ETH_ALEN); | ||
| 3143 | else | ||
| 3144 | /* funtion has not been loaded yet. Show mac as 0s */ | ||
| 3145 | memset(&ivi->mac, 0, ETH_ALEN); | ||
| 3146 | |||
| 3147 | /* vlan */ | ||
| 3148 | if (bulletin->valid_bitmap & (1 << VLAN_VALID)) | ||
| 3149 | /* vlan configured by ndo so its in bulletin board */ | ||
| 3150 | memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN); | ||
| 3151 | else | ||
| 3152 | /* funtion has not been loaded yet. Show vlans as 0s */ | ||
| 3153 | memset(&ivi->vlan, 0, VLAN_HLEN); | ||
| 3154 | } | ||
| 3155 | |||
| 3156 | return 0; | ||
| 3030 | } | 3157 | } |
| 3031 | 3158 | ||
| 3032 | /* New mac for VF. Consider these cases: | 3159 | /* New mac for VF. Consider these cases: |
| @@ -3044,23 +3171,19 @@ void bnx2x_enable_sriov(struct bnx2x *bp) · 11 unmodified lines | |||
| 3044 | * VF to configure any mac for itself except for this mac. In case of a race | 3171 | * VF to configure any mac for itself except for this mac. In case of a race |
| 3045 | * where the VF fails to see the new post on its bulletin board before sending a | 3172 | * where the VF fails to see the new post on its bulletin board before sending a |
| 3046 | * mac configuration request, the PF will simply fail the request and VF can try | 3173 | * mac configuration request, the PF will simply fail the request and VF can try |
| 3047 | * again after consulting its bulletin board | 3174 | * again after consulting its bulletin board. |
| 3048 | */ | 3175 | */ |
| 3049 | int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac) | 3176 | int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac) |
| 3050 | { | 3177 | { |
| 3051 | struct bnx2x *bp = netdev_priv(dev); | 3178 | struct bnx2x *bp = netdev_priv(dev); |
| 3052 | int rc, q_logical_state, vfidx = queue; | 3179 | int rc, q_logical_state; |
| 3053 | struct bnx2x_virtf *vf = BP_VF(bp, vfidx); | 3180 | struct bnx2x_virtf *vf = BP_VF(bp, vfidx); |
| 3054 | struct pf_vf_bulletin_content *bulletin = BP_VF_BULLETIN(bp, vfidx); | 3181 | struct pf_vf_bulletin_content *bulletin = BP_VF_BULLETIN(bp, vfidx); |
| 3055 | 3182 | ||
| 3056 | /* if SRIOV is disabled there is nothing to do (and somewhere, someone | 3183 | /* sanity */ |
| 3057 | * has erred). | 3184 | rc = bnx2x_vf_ndo_sanity(bp, vfidx, vf); |
| 3058 | */ | 3185 | if (rc) |
| 3059 | if (!IS_SRIOV(bp)) { | 3186 | return rc; |
| 3060 | BNX2X_ERR("bnx2x_set_vf_mac called though sriov is disabled\n"); | ||
| 3061 | return -EINVAL; | ||
| 3062 | } | ||
| 3063 | |||
| 3064 | if (!is_valid_ether_addr(mac)) { | 3187 | if (!is_valid_ether_addr(mac)) { |
| 3065 | BNX2X_ERR("mac address invalid\n"); | 3188 | BNX2X_ERR("mac address invalid\n"); |
| 3066 | return -EINVAL; | 3189 | return -EINVAL; |
| @@ -3085,7 +3208,7 @@ int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac) · 18 unmodified lines | |||
| 3085 | if (vf->state == VF_ENABLED && | 3208 | if (vf->state == VF_ENABLED && |
| 3086 | q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) { | 3209 | q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) { |
| 3087 | /* configure the mac in device on this vf's queue */ | 3210 | /* configure the mac in device on this vf's queue */ |
| 3088 | unsigned long flags = 0; | 3211 | unsigned long ramrod_flags = 0; |
| 3089 | struct bnx2x_vlan_mac_obj *mac_obj = &bnx2x_vfq(vf, 0, mac_obj); | 3212 | struct bnx2x_vlan_mac_obj *mac_obj = &bnx2x_vfq(vf, 0, mac_obj); |
| 3090 | 3213 | ||
| 3091 | /* must lock vfpf channel to protect against vf flows */ | 3214 | /* must lock vfpf channel to protect against vf flows */ |
| @@ -3106,14 +3229,133 @@ int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac) · 14 unmodified lines | |||
| 3106 | } | 3229 | } |
| 3107 | 3230 | ||
| 3108 | /* configure the new mac to device */ | 3231 | /* configure the new mac to device */ |
| 3109 | __set_bit(RAMROD_COMP_WAIT, &flags); | 3232 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
| 3110 | bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true, | 3233 | bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true, |
| 3111 | BNX2X_ETH_MAC, &flags); | 3234 | BNX2X_ETH_MAC, &ramrod_flags); |
| 3112 | 3235 | ||
| 3113 | bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); | 3236 | bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); |
| 3114 | } | 3237 | } |
| 3115 | 3238 | ||
| 3116 | return rc; | 3239 | return 0; |
| 3240 | } | ||
| 3241 | |||
| 3242 | int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos) | ||
| 3243 | { | ||
| 3244 | struct bnx2x *bp = netdev_priv(dev); | ||
| 3245 | int rc, q_logical_state; | ||
| 3246 | struct bnx2x_virtf *vf = BP_VF(bp, vfidx); | ||
| 3247 | struct pf_vf_bulletin_content *bulletin = BP_VF_BULLETIN(bp, vfidx); | ||
| 3248 | |||
| 3249 | /* sanity */ | ||
| 3250 | rc = bnx2x_vf_ndo_sanity(bp, vfidx, vf); | ||
| 3251 | if (rc) | ||
| 3252 | return rc; | ||
| 3253 | |||
| 3254 | if (vlan > 4095) { | ||
| 3255 | BNX2X_ERR("illegal vlan value %d\n", vlan); | ||
| 3256 | return -EINVAL; | ||
| 3257 | } | ||
| 3258 | |||
| 3259 | DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n", | ||
| 3260 | vfidx, vlan, 0); | ||
| 3261 | |||
| 3262 | /* update PF's copy of the VF's bulletin. No point in posting the vlan | ||
| 3263 | * to the VF since it doesn't have anything to do with it. But it useful | ||
| 3264 | * to store it here in case the VF is not up yet and we can only | ||
| 3265 | * configure the vlan later when it does. | ||
| 3266 | */ | ||
| 3267 | bulletin->valid_bitmap |= 1 << VLAN_VALID; | ||
| 3268 | bulletin->vlan = vlan; | ||
| 3269 | |||
| 3270 | /* is vf initialized and queue set up? */ | ||
| 3271 | q_logical_state = | ||
| 3272 | bnx2x_get_q_logical_state(bp, &bnx2x_vfq(vf, 0, sp_obj)); | ||
| 3273 | if (vf->state == VF_ENABLED && | ||
| 3274 | q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) { | ||
| 3275 | /* configure the vlan in device on this vf's queue */ | ||
| 3276 | unsigned long ramrod_flags = 0; | ||
| 3277 | unsigned long vlan_mac_flags = 0; | ||
| 3278 | struct bnx2x_vlan_mac_obj *vlan_obj = | ||
| 3279 | &bnx2x_vfq(vf, 0, vlan_obj); | ||
| 3280 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | ||
| 3281 | struct bnx2x_queue_state_params q_params = {NULL}; | ||
| 3282 | struct bnx2x_queue_update_params *update_params; | ||
| 3283 | |||
| 3284 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | ||
| 3285 | |||
| 3286 | /* must lock vfpf channel to protect against vf flows */ | ||
| 3287 | bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); | ||
| 3288 | |||
| 3289 | /* remove existing vlans */ | ||
| 3290 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | ||
| 3291 | rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags, | ||
| 3292 | &ramrod_flags); | ||
| 3293 | if (rc) { | ||
| 3294 | BNX2X_ERR("failed to delete vlans\n"); | ||
| 3295 | return -EINVAL; | ||
| 3296 | } | ||
| 3297 | |||
| 3298 | /* send queue update ramrod to configure default vlan and silent | ||
| 3299 | * vlan removal | ||
| 3300 | */ | ||
| 3301 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | ||
| 3302 | q_params.cmd = BNX2X_Q_CMD_UPDATE; | ||
| 3303 | q_params.q_obj = &bnx2x_vfq(vf, 0, sp_obj); | ||
| 3304 | update_params = &q_params.params.update; | ||
| 3305 | __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, | ||
| 3306 | &update_params->update_flags); | ||
| 3307 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | ||
| 3308 | &update_params->update_flags); | ||
| 3309 | |||
| 3310 | if (vlan == 0) { | ||
| 3311 | /* if vlan is 0 then we want to leave the VF traffic | ||
| 3312 | * untagged, and leave the incoming traffic untouched | ||
| 3313 | * (i.e. do not remove any vlan tags). | ||
| 3314 | */ | ||
| 3315 | __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, | ||
| 3316 | &update_params->update_flags); | ||
| 3317 | __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | ||
| 3318 | &update_params->update_flags); | ||
| 3319 | } else { | ||
| 3320 | /* configure the new vlan to device */ | ||
| 3321 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | ||
| 3322 | ramrod_param.vlan_mac_obj = vlan_obj; | ||
| 3323 | ramrod_param.ramrod_flags = ramrod_flags; | ||
| 3324 | ramrod_param.user_req.u.vlan.vlan = vlan; | ||
| 3325 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | ||
| 3326 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); | ||
| 3327 | if (rc) { | ||
| 3328 | BNX2X_ERR("failed to configure vlan\n"); | ||
| 3329 | return -EINVAL; | ||
| 3330 | } | ||
| 3331 | |||
| 3332 | /* configure default vlan to vf queue and set silent | ||
| 3333 | * vlan removal (the vf remains unaware of this vlan). | ||
| 3334 | */ | ||
| 3335 | update_params = &q_params.params.update; | ||
| 3336 | __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, | ||
| 3337 | &update_params->update_flags); | ||
| 3338 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | ||
| 3339 | &update_params->update_flags); | ||
| 3340 | update_params->def_vlan = vlan; | ||
| 3341 | } | ||
| 3342 | |||
| 3343 | /* Update the Queue state */ | ||
| 3344 | rc = bnx2x_queue_state_change(bp, &q_params); | ||
| 3345 | if (rc) { | ||
| 3346 | BNX2X_ERR("Failed to configure default VLAN\n"); | ||
| 3347 | return rc; | ||
| 3348 | } | ||
| 3349 | |||
| 3350 | /* clear the flag indicating that this VF needs its vlan | ||
| 3351 | * (will only be set if the HV configured th Vlan before vf was | ||
| 3352 | * and we were called because the VF came up later | ||
| 3353 | */ | ||
| 3354 | vf->cfg_flags &= ~VF_CFG_VLAN; | ||
| 3355 | |||
| 3356 | bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); | ||
| 3357 | } | ||
| 3358 | return 0; | ||
| 3117 | } | 3359 | } |
| 3118 | 3360 | ||
| 3119 | /* crc is the first field in the bulletin board. compute the crc over the | 3361 | /* crc is the first field in the bulletin board. compute the crc over the |
| @@ -3165,20 +3407,26 @@ enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp) · 45 unmodified lines | |||
| 3165 | memcpy(bp->dev->dev_addr, bulletin.mac, ETH_ALEN); | 3407 | memcpy(bp->dev->dev_addr, bulletin.mac, ETH_ALEN); |
| 3166 | } | 3408 | } |
| 3167 | 3409 | ||
| 3410 | /* the vlan in bulletin board is valid and is new */ | ||
| 3411 | if (bulletin.valid_bitmap & 1 << VLAN_VALID) | ||
| 3412 | memcpy(&bulletin.vlan, &bp->old_bulletin.vlan, VLAN_HLEN); | ||
| 3413 | |||
| 3168 | /* copy new bulletin board to bp */ | 3414 | /* copy new bulletin board to bp */ |
| 3169 | bp->old_bulletin = bulletin; | 3415 | bp->old_bulletin = bulletin; |
| 3170 | 3416 | ||
| 3171 | return PFVF_BULLETIN_UPDATED; | 3417 | return PFVF_BULLETIN_UPDATED; |
| 3172 | } | 3418 | } |
| 3173 | 3419 | ||
| 3174 | void bnx2x_vf_map_doorbells(struct bnx2x *bp) | 3420 | void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp) |
| 3175 | { | 3421 | { |
| 3176 | /* vf doorbells are embedded within the regview */ | 3422 | /* vf doorbells are embedded within the regview */ |
| 3177 | bp->doorbells = bp->regview + PXP_VF_ADDR_DB_START; | 3423 | return bp->regview + PXP_VF_ADDR_DB_START; |
| 3178 | } | 3424 | } |
| 3179 | 3425 | ||
| 3180 | int bnx2x_vf_pci_alloc(struct bnx2x *bp) | 3426 | int bnx2x_vf_pci_alloc(struct bnx2x *bp) |
| 3181 | { | 3427 | { |
| 3428 | mutex_init(&bp->vf2pf_mutex); | ||
| 3429 | |||
| 3182 | /* allocate vf2pf mailbox for vf to pf channel */ | 3430 | /* allocate vf2pf mailbox for vf to pf channel */ |
| 3183 | BNX2X_PCI_ALLOC(bp->vf2pf_mbox, &bp->vf2pf_mbox_mapping, | 3431 | BNX2X_PCI_ALLOC(bp->vf2pf_mbox, &bp->vf2pf_mbox_mapping, |
| 3184 | sizeof(struct bnx2x_vf_mbx_msg)); | 3432 | sizeof(struct bnx2x_vf_mbx_msg)); |
| @@ -3196,3 +3444,26 @@ alloc_mem_err: · 11 unmodified lines | |||
| 3196 | sizeof(union pf_vf_bulletin)); | 3444 | sizeof(union pf_vf_bulletin)); |
| 3197 | return -ENOMEM; | 3445 | return -ENOMEM; |
| 3198 | } | 3446 | } |
| 3447 | |||
| 3448 | int bnx2x_open_epilog(struct bnx2x *bp) | ||
| 3449 | { | ||
| 3450 | /* Enable sriov via delayed work. This must be done via delayed work | ||
| 3451 | * because it causes the probe of the vf devices to be run, which invoke | ||
| 3452 | * register_netdevice which must have rtnl lock taken. As we are holding | ||
| 3453 | * the lock right now, that could only work if the probe would not take | ||
| 3454 | * the lock. However, as the probe of the vf may be called from other | ||
| 3455 | * contexts as well (such as passthrough to vm failes) it can't assume | ||
| 3456 | * the lock is being held for it. Using delayed work here allows the | ||
| 3457 | * probe code to simply take the lock (i.e. wait for it to be released | ||
| 3458 | * if it is being held). We only want to do this if the number of VFs | ||
| 3459 | * was set before PF driver was loaded. | ||
| 3460 | */ | ||
| 3461 | if (IS_SRIOV(bp) && BNX2X_NR_VIRTFN(bp)) { | ||
| 3462 | smp_mb__before_clear_bit(); | ||
| 3463 | set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, &bp->sp_rtnl_state); | ||
| 3464 | smp_mb__after_clear_bit(); | ||
| 3465 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | ||
| 3466 | } | ||
| 3467 | |||
| 3468 | return 0; | ||
| 3469 | } | ||
| @@ -193,6 +193,7 @@ struct bnx2x_virtf { · 192 unmodified lines | |||
| 193 | #define VF_CFG_TPA 0x0004 | 193 | #define VF_CFG_TPA 0x0004 |
| 194 | #define VF_CFG_INT_SIMD 0x0008 | 194 | #define VF_CFG_INT_SIMD 0x0008 |
| 195 | #define VF_CACHE_LINE 0x0010 | 195 | #define VF_CACHE_LINE 0x0010 |
| 196 | #define VF_CFG_VLAN 0x0020 | ||
| 196 | 197 | ||
| 197 | u8 state; | 198 | u8 state; |
| 198 | #define VF_FREE 0 /* VF ready to be acquired holds no resc */ | 199 | #define VF_FREE 0 /* VF ready to be acquired holds no resc */ |
| @@ -712,6 +713,7 @@ void bnx2x_add_tlv(struct bnx2x *bp, void *tlvs_list, u16 offset, u16 type, · 513 unmodified lines | |||
| 712 | u16 length); | 713 | u16 length); |
| 713 | void bnx2x_vfpf_prep(struct bnx2x *bp, struct vfpf_first_tlv *first_tlv, | 714 | void bnx2x_vfpf_prep(struct bnx2x *bp, struct vfpf_first_tlv *first_tlv, |
| 714 | u16 type, u16 length); | 715 | u16 type, u16 length); |
| 716 | void bnx2x_vfpf_finalize(struct bnx2x *bp, struct vfpf_first_tlv *first_tlv); | ||
| 715 | void bnx2x_dp_tlv_list(struct bnx2x *bp, void *tlvs_list); | 717 | void bnx2x_dp_tlv_list(struct bnx2x *bp, void *tlvs_list); |
| 716 | 718 | ||
| 717 | bool bnx2x_tlv_supported(u16 tlvtype); | 719 | bool bnx2x_tlv_supported(u16 tlvtype); |
| @@ -731,7 +733,7 @@ int bnx2x_vfpf_init(struct bnx2x *bp); · 13 unmodified lines | |||
| 731 | void bnx2x_vfpf_close_vf(struct bnx2x *bp); | 733 | void bnx2x_vfpf_close_vf(struct bnx2x *bp); |
| 732 | int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx); | 734 | int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx); |
| 733 | int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx); | 735 | int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx); |
| 734 | int bnx2x_vfpf_set_mac(struct bnx2x *bp); | 736 | int bnx2x_vfpf_config_mac(struct bnx2x *bp, u8 *addr, u8 vf_qid, bool set); |
| 735 | int bnx2x_vfpf_set_mcast(struct net_device *dev); | 737 | int bnx2x_vfpf_set_mcast(struct net_device *dev); |
| 736 | int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp); | 738 | int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp); |
| 737 | 739 | ||
| @@ -750,13 +752,17 @@ static inline int bnx2x_vf_ustorm_prods_offset(struct bnx2x *bp, · 12 unmodified lines | |||
| 750 | } | 752 | } |
| 751 | 753 | ||
| 752 | enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp); | 754 | enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp); |
| 753 | void bnx2x_vf_map_doorbells(struct bnx2x *bp); | 755 | void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp); |
| 754 | int bnx2x_vf_pci_alloc(struct bnx2x *bp); | 756 | int bnx2x_vf_pci_alloc(struct bnx2x *bp); |
| 755 | void bnx2x_enable_sriov(struct bnx2x *bp); | 757 | int bnx2x_enable_sriov(struct bnx2x *bp); |
| 758 | void bnx2x_disable_sriov(struct bnx2x *bp); | ||
| 756 | static inline int bnx2x_vf_headroom(struct bnx2x *bp) | 759 | static inline int bnx2x_vf_headroom(struct bnx2x *bp) |
| 757 | { | 760 | { |
| 758 | return bp->vfdb->sriov.nr_virtfn * BNX2X_CLIENTS_PER_VF; | 761 | return bp->vfdb->sriov.nr_virtfn * BNX2X_CLIENTS_PER_VF; |
| 759 | } | 762 | } |
| 763 | void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp); | ||
| 764 | int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs); | ||
| 765 | int bnx2x_open_epilog(struct bnx2x *bp); | ||
| 760 | 766 | ||
| 761 | #else /* CONFIG_BNX2X_SRIOV */ | 767 | #else /* CONFIG_BNX2X_SRIOV */ |
| 762 | 768 | ||
| @@ -779,7 +785,8 @@ static inline void bnx2x_iov_init_dmae(struct bnx2x *bp) {} · 16 unmodified lines | |||
| 779 | static inline int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, | 785 | static inline int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, |
| 780 | int num_vfs_param) {return 0; } | 786 | int num_vfs_param) {return 0; } |
| 781 | static inline void bnx2x_iov_remove_one(struct bnx2x *bp) {} | 787 | static inline void bnx2x_iov_remove_one(struct bnx2x *bp) {} |
| 782 | static inline void bnx2x_enable_sriov(struct bnx2x *bp) {} | 788 | static inline int bnx2x_enable_sriov(struct bnx2x *bp) {return 0; } |
| 789 | static inline void bnx2x_disable_sriov(struct bnx2x *bp) {} | ||
| 783 | static inline int bnx2x_vfpf_acquire(struct bnx2x *bp, | 790 | static inline int bnx2x_vfpf_acquire(struct bnx2x *bp, |
| 784 | u8 tx_count, u8 rx_count) {return 0; } | 791 | u8 tx_count, u8 rx_count) {return 0; } |
| 785 | static inline int bnx2x_vfpf_release(struct bnx2x *bp) {return 0; } | 792 | static inline int bnx2x_vfpf_release(struct bnx2x *bp) {return 0; } |
| @@ -787,7 +794,8 @@ static inline int bnx2x_vfpf_init(struct bnx2x *bp) {return 0; } · 1 unmodified line | |||
| 787 | static inline void bnx2x_vfpf_close_vf(struct bnx2x *bp) {} | 794 | static inline void bnx2x_vfpf_close_vf(struct bnx2x *bp) {} |
| 788 | static inline int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx) {return 0; } | 795 | static inline int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx) {return 0; } |
| 789 | static inline int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx) {return 0; } | 796 | static inline int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx) {return 0; } |
| 790 | static inline int bnx2x_vfpf_set_mac(struct bnx2x *bp) {return 0; } | 797 | static inline int bnx2x_vfpf_config_mac(struct bnx2x *bp, u8 *addr, |
| 798 | u8 vf_qid, bool set) {return 0; } | ||
| 791 | static inline int bnx2x_vfpf_set_mcast(struct net_device *dev) {return 0; } | 799 | static inline int bnx2x_vfpf_set_mcast(struct net_device *dev) {return 0; } |
| 792 | static inline int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp) {return 0; } | 800 | static inline int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp) {return 0; } |
| 793 | static inline int bnx2x_iov_nic_init(struct bnx2x *bp) {return 0; } | 801 | static inline int bnx2x_iov_nic_init(struct bnx2x *bp) {return 0; } |
| @@ -802,8 +810,15 @@ static inline enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp · 8 unmodified lines | |||
| 802 | return PFVF_BULLETIN_UNCHANGED; | 810 | return PFVF_BULLETIN_UNCHANGED; |
| 803 | } | 811 | } |
| 804 | 812 | ||
| 805 | static inline int bnx2x_vf_map_doorbells(struct bnx2x *bp) {return 0; } | 813 | static inline void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp) |
| 814 | { | ||
| 815 | return NULL; | ||
| 816 | } | ||
| 817 | |||
| 806 | static inline int bnx2x_vf_pci_alloc(struct bnx2x *bp) {return 0; } | 818 | static inline int bnx2x_vf_pci_alloc(struct bnx2x *bp) {return 0; } |
| 819 | static inline void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp) {} | ||
| 820 | static inline int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs) {return 0; } | ||
| 821 | static inline int bnx2x_open_epilog(struct bnx2x *bp) {return 0; } | ||
| 807 | 822 | ||
| 808 | #endif /* CONFIG_BNX2X_SRIOV */ | 823 | #endif /* CONFIG_BNX2X_SRIOV */ |
| 809 | #endif /* bnx2x_sriov.h */ | 824 | #endif /* bnx2x_sriov.h */ |
| @@ -1547,11 +1547,51 @@ static void bnx2x_prep_fw_stats_req(struct bnx2x *bp) · 1546 unmodified lines | |||
| 1547 | } | 1547 | } |
| 1548 | } | 1548 | } |
| 1549 | 1549 | ||
| 1550 | void bnx2x_memset_stats(struct bnx2x *bp) | ||
| 1551 | { | ||
| 1552 | int i; | ||
| 1553 | |||
| 1554 | /* function stats */ | ||
| 1555 | for_each_queue(bp, i) { | ||
| 1556 | struct bnx2x_fp_stats *fp_stats = &bp->fp_stats[i]; | ||
| 1557 | |||
| 1558 | memset(&fp_stats->old_tclient, 0, | ||
| 1559 | sizeof(fp_stats->old_tclient)); | ||
| 1560 | memset(&fp_stats->old_uclient, 0, | ||
| 1561 | sizeof(fp_stats->old_uclient)); | ||
| 1562 | memset(&fp_stats->old_xclient, 0, | ||
| 1563 | sizeof(fp_stats->old_xclient)); | ||
| 1564 | if (bp->stats_init) { | ||
| 1565 | memset(&fp_stats->eth_q_stats, 0, | ||
| 1566 | sizeof(fp_stats->eth_q_stats)); | ||
| 1567 | memset(&fp_stats->eth_q_stats_old, 0, | ||
| 1568 | sizeof(fp_stats->eth_q_stats_old)); | ||
| 1569 | } | ||
| 1570 | } | ||
| 1571 | |||
| 1572 | memset(&bp->dev->stats, 0, sizeof(bp->dev->stats)); | ||
| 1573 | |||
| 1574 | if (bp->stats_init) { | ||
| 1575 | memset(&bp->net_stats_old, 0, sizeof(bp->net_stats_old)); | ||
| 1576 | memset(&bp->fw_stats_old, 0, sizeof(bp->fw_stats_old)); | ||
| 1577 | memset(&bp->eth_stats_old, 0, sizeof(bp->eth_stats_old)); | ||
| 1578 | memset(&bp->eth_stats, 0, sizeof(bp->eth_stats)); | ||
| 1579 | memset(&bp->func_stats, 0, sizeof(bp->func_stats)); | ||
| 1580 | } | ||
| 1581 | |||
| 1582 | bp->stats_state = STATS_STATE_DISABLED; | ||
| 1583 | |||
| 1584 | if (bp->port.pmf && bp->port.port_stx) | ||
| 1585 | bnx2x_port_stats_base_init(bp); | ||
| 1586 | |||
| 1587 | /* mark the end of statistics initializiation */ | ||
| 1588 | bp->stats_init = false; | ||
| 1589 | } | ||
| 1590 | |||
| 1550 | void bnx2x_stats_init(struct bnx2x *bp) | 1591 | void bnx2x_stats_init(struct bnx2x *bp) |
| 1551 | { | 1592 | { |
| 1552 | int /*abs*/port = BP_PORT(bp); | 1593 | int /*abs*/port = BP_PORT(bp); |
| 1553 | int mb_idx = BP_FW_MB_IDX(bp); | 1594 | int mb_idx = BP_FW_MB_IDX(bp); |
| 1554 | int i; | ||
| 1555 | 1595 | ||
| 1556 | bp->stats_pending = 0; | 1596 | bp->stats_pending = 0; |
| 1557 | bp->executer_idx = 0; | 1597 | bp->executer_idx = 0; |
| @@ -1587,36 +1627,11 @@ void bnx2x_stats_init(struct bnx2x *bp) · 29 unmodified lines | |||
| 1587 | &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2); | 1627 | &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2); |
| 1588 | } | 1628 | } |
| 1589 | 1629 | ||
| 1590 | /* function stats */ | ||
| 1591 | for_each_queue(bp, i) { | ||
| 1592 | struct bnx2x_fp_stats *fp_stats = &bp->fp_stats[i]; | ||
| 1593 | |||
| 1594 | memset(&fp_stats->old_tclient, 0, | ||
| 1595 | sizeof(fp_stats->old_tclient)); | ||
| 1596 | memset(&fp_stats->old_uclient, 0, | ||
| 1597 | sizeof(fp_stats->old_uclient)); | ||
| 1598 | memset(&fp_stats->old_xclient, 0, | ||
| 1599 | sizeof(fp_stats->old_xclient)); | ||
| 1600 | if (bp->stats_init) { | ||
| 1601 | memset(&fp_stats->eth_q_stats, 0, | ||
| 1602 | sizeof(fp_stats->eth_q_stats)); | ||
| 1603 | memset(&fp_stats->eth_q_stats_old, 0, | ||
| 1604 | sizeof(fp_stats->eth_q_stats_old)); | ||
| 1605 | } | ||
| 1606 | } | ||
| 1607 | |||
| 1608 | /* Prepare statistics ramrod data */ | 1630 | /* Prepare statistics ramrod data */ |
| 1609 | bnx2x_prep_fw_stats_req(bp); | 1631 | bnx2x_prep_fw_stats_req(bp); |
| 1610 | 1632 | ||
| 1611 | memset(&bp->dev->stats, 0, sizeof(bp->dev->stats)); | 1633 | /* Clean SP from previous statistics */ |
| 1612 | if (bp->stats_init) { | 1634 | if (bp->stats_init) { |
| 1613 | memset(&bp->net_stats_old, 0, sizeof(bp->net_stats_old)); | ||
| 1614 | memset(&bp->fw_stats_old, 0, sizeof(bp->fw_stats_old)); | ||
| 1615 | memset(&bp->eth_stats_old, 0, sizeof(bp->eth_stats_old)); | ||
| 1616 | memset(&bp->eth_stats, 0, sizeof(bp->eth_stats)); | ||
| 1617 | memset(&bp->func_stats, 0, sizeof(bp->func_stats)); | ||
| 1618 | |||
| 1619 | /* Clean SP from previous statistics */ | ||
| 1620 | if (bp->func_stx) { | 1635 | if (bp->func_stx) { |
| 1621 | memset(bnx2x_sp(bp, func_stats), 0, | 1636 | memset(bnx2x_sp(bp, func_stats), 0, |
| 1622 | sizeof(struct host_func_stats)); | 1637 | sizeof(struct host_func_stats)); |
| @@ -1626,13 +1641,7 @@ void bnx2x_stats_init(struct bnx2x *bp) · 3 unmodified lines | |||
| 1626 | } | 1641 | } |
| 1627 | } | 1642 | } |
| 1628 | 1643 | ||
| 1629 | bp->stats_state = STATS_STATE_DISABLED; | 1644 | bnx2x_memset_stats(bp); |
| 1630 | |||
| 1631 | if (bp->port.pmf && bp->port.port_stx) | ||
| 1632 | bnx2x_port_stats_base_init(bp); | ||
| 1633 | |||
| 1634 | /* mark the end of statistics initializiation */ | ||
| 1635 | bp->stats_init = false; | ||
| 1636 | } | 1645 | } |
| 1637 | 1646 | ||
| 1638 | void bnx2x_save_statistics(struct bnx2x *bp) | 1647 | void bnx2x_save_statistics(struct bnx2x *bp) |
| @@ -540,8 +540,8 @@ struct bnx2x_fw_port_stats_old { · 539 unmodified lines | |||
| 540 | /* forward */ | 540 | /* forward */ |
| 541 | struct bnx2x; | 541 | struct bnx2x; |
| 542 | 542 | ||
| 543 | void bnx2x_memset_stats(struct bnx2x *bp); | ||
| 543 | void bnx2x_stats_init(struct bnx2x *bp); | 544 | void bnx2x_stats_init(struct bnx2x *bp); |
| 544 | |||
| 545 | void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event); | 545 | void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event); |
| 546 | 546 | ||
| 547 | /** | 547 | /** |
| @@ -36,6 +36,8 @@ void bnx2x_add_tlv(struct bnx2x *bp, void *tlvs_list, u16 offset, u16 type, · 35 unmodified lines | |||
| 36 | void bnx2x_vfpf_prep(struct bnx2x *bp, struct vfpf_first_tlv *first_tlv, | 36 | void bnx2x_vfpf_prep(struct bnx2x *bp, struct vfpf_first_tlv *first_tlv, |
| 37 | u16 type, u16 length) | 37 | u16 type, u16 length) |
| 38 | { | 38 | { |
| 39 | mutex_lock(&bp->vf2pf_mutex); | ||
| 40 | |||
| 39 | DP(BNX2X_MSG_IOV, "preparing to send %d tlv over vf pf channel\n", | 41 | DP(BNX2X_MSG_IOV, "preparing to send %d tlv over vf pf channel\n", |
| 40 | type); | 42 | type); |
| 41 | 43 | ||
| @@ -49,6 +51,15 @@ void bnx2x_vfpf_prep(struct bnx2x *bp, struct vfpf_first_tlv *first_tlv, · 7 unmodified lines | |||
| 49 | first_tlv->resp_msg_offset = sizeof(bp->vf2pf_mbox->req); | 51 | first_tlv->resp_msg_offset = sizeof(bp->vf2pf_mbox->req); |
| 50 | } | 52 | } |
| 51 | 53 | ||
| 54 | /* releases the mailbox */ | ||
| 55 | void bnx2x_vfpf_finalize(struct bnx2x *bp, struct vfpf_first_tlv *first_tlv) | ||
| 56 | { | ||
| 57 | DP(BNX2X_MSG_IOV, "done sending [%d] tlv over vf pf channel\n", | ||
| 58 | first_tlv->tl.type); | ||
| 59 | |||
| 60 | mutex_unlock(&bp->vf2pf_mutex); | ||
| 61 | } | ||
| 62 | |||
| 52 | /* list the types and lengths of the tlvs on the buffer */ | 63 | /* list the types and lengths of the tlvs on the buffer */ |
| 53 | void bnx2x_dp_tlv_list(struct bnx2x *bp, void *tlvs_list) | 64 | void bnx2x_dp_tlv_list(struct bnx2x *bp, void *tlvs_list) |
| 54 | { | 65 | { |
| @@ -181,8 +192,10 @@ int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count) · 126 unmodified lines | |||
| 181 | /* clear mailbox and prep first tlv */ | 192 | /* clear mailbox and prep first tlv */ |
| 182 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_ACQUIRE, sizeof(*req)); | 193 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_ACQUIRE, sizeof(*req)); |
| 183 | 194 | ||
| 184 | if (bnx2x_get_vf_id(bp, &vf_id)) | 195 | if (bnx2x_get_vf_id(bp, &vf_id)) { |
| 185 | return -EAGAIN; | 196 | rc = -EAGAIN; |
| 197 | goto out; | ||
| 198 | } | ||
| 186 | 199 | ||
| 187 | req->vfdev_info.vf_id = vf_id; | 200 | req->vfdev_info.vf_id = vf_id; |
| 188 | req->vfdev_info.vf_os = 0; | 201 | req->vfdev_info.vf_os = 0; |
| @@ -213,7 +226,7 @@ int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count) · 24 unmodified lines | |||
| 213 | 226 | ||
| 214 | /* PF timeout */ | 227 | /* PF timeout */ |
| 215 | if (rc) | 228 | if (rc) |
| 216 | return rc; | 229 | goto out; |
| 217 | 230 | ||
| 218 | /* copy acquire response from buffer to bp */ | 231 | /* copy acquire response from buffer to bp */ |
| 219 | memcpy(&bp->acquire_resp, resp, sizeof(bp->acquire_resp)); | 232 | memcpy(&bp->acquire_resp, resp, sizeof(bp->acquire_resp)); |
| @@ -253,7 +266,8 @@ int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count) · 33 unmodified lines | |||
| 253 | /* PF reports error */ | 266 | /* PF reports error */ |
| 254 | BNX2X_ERR("Failed to get the requested amount of resources: %d. Breaking...\n", | 267 | BNX2X_ERR("Failed to get the requested amount of resources: %d. Breaking...\n", |
| 255 | bp->acquire_resp.hdr.status); | 268 | bp->acquire_resp.hdr.status); |
| 256 | return -EAGAIN; | 269 | rc = -EAGAIN; |
| 270 | goto out; | ||
| 257 | } | 271 | } |
| 258 | } | 272 | } |
| 259 | 273 | ||
| @@ -279,20 +293,24 @@ int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count) · 19 unmodified lines | |||
| 279 | bp->acquire_resp.resc.current_mac_addr, | 293 | bp->acquire_resp.resc.current_mac_addr, |
| 280 | ETH_ALEN); | 294 | ETH_ALEN); |
| 281 | 295 | ||
| 282 | return 0; | 296 | out: |
| 297 | bnx2x_vfpf_finalize(bp, &req->first_tlv); | ||
| 298 | return rc; | ||
| 283 | } | 299 | } |
| 284 | 300 | ||
| 285 | int bnx2x_vfpf_release(struct bnx2x *bp) | 301 | int bnx2x_vfpf_release(struct bnx2x *bp) |
| 286 | { | 302 | { |
| 287 | struct vfpf_release_tlv *req = &bp->vf2pf_mbox->req.release; | 303 | struct vfpf_release_tlv *req = &bp->vf2pf_mbox->req.release; |
| 288 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; | 304 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; |
| 289 | u32 rc = 0, vf_id; | 305 | u32 rc, vf_id; |
| 290 | 306 | ||
| 291 | /* clear mailbox and prep first tlv */ | 307 | /* clear mailbox and prep first tlv */ |
| 292 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_RELEASE, sizeof(*req)); | 308 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_RELEASE, sizeof(*req)); |
| 293 | 309 | ||
| 294 | if (bnx2x_get_vf_id(bp, &vf_id)) | 310 | if (bnx2x_get_vf_id(bp, &vf_id)) { |
| 295 | return -EAGAIN; | 311 | rc = -EAGAIN; |
| 312 | goto out; | ||
| 313 | } | ||
| 296 | 314 | ||
| 297 | req->vf_id = vf_id; | 315 | req->vf_id = vf_id; |
| 298 | 316 | ||
| @@ -308,7 +326,8 @@ int bnx2x_vfpf_release(struct bnx2x *bp) · 9 unmodified lines | |||
| 308 | 326 | ||
| 309 | if (rc) | 327 | if (rc) |
| 310 | /* PF timeout */ | 328 | /* PF timeout */ |
| 311 | return rc; | 329 | goto out; |
| 330 | |||
| 312 | if (resp->hdr.status == PFVF_STATUS_SUCCESS) { | 331 | if (resp->hdr.status == PFVF_STATUS_SUCCESS) { |
| 313 | /* PF released us */ | 332 | /* PF released us */ |
| 314 | DP(BNX2X_MSG_SP, "vf released\n"); | 333 | DP(BNX2X_MSG_SP, "vf released\n"); |
| @@ -316,10 +335,13 @@ int bnx2x_vfpf_release(struct bnx2x *bp) · 1 unmodified line | |||
| 316 | /* PF reports error */ | 335 | /* PF reports error */ |
| 317 | BNX2X_ERR("PF failed our release request - are we out of sync? response status: %d\n", | 336 | BNX2X_ERR("PF failed our release request - are we out of sync? response status: %d\n", |
| 318 | resp->hdr.status); | 337 | resp->hdr.status); |
| 319 | return -EAGAIN; | 338 | rc = -EAGAIN; |
| 339 | goto out; | ||
| 320 | } | 340 | } |
| 341 | out: | ||
| 342 | bnx2x_vfpf_finalize(bp, &req->first_tlv); | ||
| 321 | 343 | ||
| 322 | return 0; | 344 | return rc; |
| 323 | } | 345 | } |
| 324 | 346 | ||
| 325 | /* Tell PF about SB addresses */ | 347 | /* Tell PF about SB addresses */ |
| @@ -350,16 +372,20 @@ int bnx2x_vfpf_init(struct bnx2x *bp) · 24 unmodified lines | |||
| 350 | 372 | ||
| 351 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | 373 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); |
| 352 | if (rc) | 374 | if (rc) |
| 353 | return rc; | 375 | goto out; |
| 354 | 376 | ||
| 355 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | 377 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { |
| 356 | BNX2X_ERR("INIT VF failed: %d. Breaking...\n", | 378 | BNX2X_ERR("INIT VF failed: %d. Breaking...\n", |
| 357 | resp->hdr.status); | 379 | resp->hdr.status); |
| 358 | return -EAGAIN; | 380 | rc = -EAGAIN; |
| 381 | goto out; | ||
| 359 | } | 382 | } |
| 360 | 383 | ||
| 361 | DP(BNX2X_MSG_SP, "INIT VF Succeeded\n"); | 384 | DP(BNX2X_MSG_SP, "INIT VF Succeeded\n"); |
| 362 | return 0; | 385 | out: |
| 386 | bnx2x_vfpf_finalize(bp, &req->first_tlv); | ||
| 387 | |||
| 388 | return rc; | ||
| 363 | } | 389 | } |
| 364 | 390 | ||
| 365 | /* CLOSE VF - opposite to INIT_VF */ | 391 | /* CLOSE VF - opposite to INIT_VF */ |
| @@ -380,6 +406,9 @@ void bnx2x_vfpf_close_vf(struct bnx2x *bp) · 14 unmodified lines | |||
| 380 | for_each_queue(bp, i) | 406 | for_each_queue(bp, i) |
| 381 | bnx2x_vfpf_teardown_queue(bp, i); | 407 | bnx2x_vfpf_teardown_queue(bp, i); |
| 382 | 408 | ||
| 409 | /* remove mac */ | ||
| 410 | bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, bp->fp->index, false); | ||
| 411 | |||
| 383 | /* clear mailbox and prep first tlv */ | 412 | /* clear mailbox and prep first tlv */ |
| 384 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_CLOSE, sizeof(*req)); | 413 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_CLOSE, sizeof(*req)); |
| 385 | 414 | ||
| @@ -401,6 +430,8 @@ void bnx2x_vfpf_close_vf(struct bnx2x *bp) · 15 unmodified lines | |||
| 401 | BNX2X_ERR("Sending CLOSE failed: pf response was %d\n", | 430 | BNX2X_ERR("Sending CLOSE failed: pf response was %d\n", |
| 402 | resp->hdr.status); | 431 | resp->hdr.status); |
| 403 | 432 | ||
| 433 | bnx2x_vfpf_finalize(bp, &req->first_tlv); | ||
| 434 | |||
| 404 | free_irq: | 435 | free_irq: |
| 405 | /* Disable HW interrupts, NAPI */ | 436 | /* Disable HW interrupts, NAPI */ |
| 406 | bnx2x_netif_stop(bp, 0); | 437 | bnx2x_netif_stop(bp, 0); |
| @@ -435,7 +466,6 @@ int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx) · 28 unmodified lines | |||
| 435 | /* calculate queue flags */ | 466 | /* calculate queue flags */ |
| 436 | flags |= VFPF_QUEUE_FLG_STATS; | 467 | flags |= VFPF_QUEUE_FLG_STATS; |
| 437 | flags |= VFPF_QUEUE_FLG_CACHE_ALIGN; | 468 | flags |= VFPF_QUEUE_FLG_CACHE_ALIGN; |
| 438 | flags |= IS_MF_SD(bp) ? VFPF_QUEUE_FLG_OV : 0; | ||
| 439 | flags |= VFPF_QUEUE_FLG_VLAN; | 469 | flags |= VFPF_QUEUE_FLG_VLAN; |
| 440 | DP(NETIF_MSG_IFUP, "vlan removal enabled\n"); | 470 | DP(NETIF_MSG_IFUP, "vlan removal enabled\n"); |
| 441 | 471 | ||
| @@ -486,8 +516,11 @@ int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx) · 44 unmodified lines | |||
| 486 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | 516 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { |
| 487 | BNX2X_ERR("Status of SETUP_Q for queue[%d] is %d\n", | 517 | BNX2X_ERR("Status of SETUP_Q for queue[%d] is %d\n", |
| 488 | fp_idx, resp->hdr.status); | 518 | fp_idx, resp->hdr.status); |
| 489 | return -EINVAL; | 519 | rc = -EINVAL; |
| 490 | } | 520 | } |
| 521 | |||
| 522 | bnx2x_vfpf_finalize(bp, &req->first_tlv); | ||
| 523 | |||
| 491 | return rc; | 524 | return rc; |
| 492 | } | 525 | } |
| 493 | 526 | ||
| @@ -515,41 +548,46 @@ int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx) · 21 unmodified lines | |||
| 515 | if (rc) { | 548 | if (rc) { |
| 516 | BNX2X_ERR("Sending TEARDOWN for queue %d failed: %d\n", qidx, | 549 | BNX2X_ERR("Sending TEARDOWN for queue %d failed: %d\n", qidx, |
| 517 | rc); | 550 | rc); |
| 518 | return rc; | 551 | goto out; |
| 519 | } | 552 | } |
| 520 | 553 | ||
| 521 | /* PF failed the transaction */ | 554 | /* PF failed the transaction */ |
| 522 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | 555 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { |
| 523 | BNX2X_ERR("TEARDOWN for queue %d failed: %d\n", qidx, | 556 | BNX2X_ERR("TEARDOWN for queue %d failed: %d\n", qidx, |
| 524 | resp->hdr.status); | 557 | resp->hdr.status); |
| 525 | return -EINVAL; | 558 | rc = -EINVAL; |
| 526 | } | 559 | } |
| 527 | 560 | ||
| 528 | return 0; | 561 | out: |
| 562 | bnx2x_vfpf_finalize(bp, &req->first_tlv); | ||
| 563 | return rc; | ||
| 529 | } | 564 | } |
| 530 | 565 | ||
| 531 | /* request pf to add a mac for the vf */ | 566 | /* request pf to add a mac for the vf */ |
| 532 | int bnx2x_vfpf_set_mac(struct bnx2x *bp) | 567 | int bnx2x_vfpf_config_mac(struct bnx2x *bp, u8 *addr, u8 vf_qid, bool set) |
| 533 | { | 568 | { |
| 534 | struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters; | 569 | struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters; |
| 535 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; | 570 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; |
| 536 | int rc; | 571 | struct pf_vf_bulletin_content bulletin = bp->pf2vf_bulletin->content; |
| 572 | int rc = 0; | ||
| 537 | 573 | ||
| 538 | /* clear mailbox and prep first tlv */ | 574 | /* clear mailbox and prep first tlv */ |
| 539 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS, | 575 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS, |
| 540 | sizeof(*req)); | 576 | sizeof(*req)); |
| 541 | 577 | ||
| 542 | req->flags = VFPF_SET_Q_FILTERS_MAC_VLAN_CHANGED; | 578 | req->flags = VFPF_SET_Q_FILTERS_MAC_VLAN_CHANGED; |
| 543 | req->vf_qid = 0; | 579 | req->vf_qid = vf_qid; |
| 544 | req->n_mac_vlan_filters = 1; | 580 | req->n_mac_vlan_filters = 1; |
| 545 | req->filters[0].flags = | 581 | |
| 546 | VFPF_Q_FILTER_DEST_MAC_VALID | VFPF_Q_FILTER_SET_MAC; | 582 | req->filters[0].flags = VFPF_Q_FILTER_DEST_MAC_VALID; |
| 583 | if (set) | ||
| 584 | req->filters[0].flags |= VFPF_Q_FILTER_SET_MAC; | ||
| 547 | 585 | ||
| 548 | /* sample bulletin board for new mac */ | 586 | /* sample bulletin board for new mac */ |
| 549 | bnx2x_sample_bulletin(bp); | 587 | bnx2x_sample_bulletin(bp); |
| 550 | 588 | ||
| 551 | /* copy mac from device to request */ | 589 | /* copy mac from device to request */ |
| 552 | memcpy(req->filters[0].mac, bp->dev->dev_addr, ETH_ALEN); | 590 | memcpy(req->filters[0].mac, addr, ETH_ALEN); |
| 553 | 591 | ||
| 554 | /* add list termination tlv */ | 592 | /* add list termination tlv */ |
| 555 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, | 593 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, |
| @@ -562,7 +600,7 @@ int bnx2x_vfpf_set_mac(struct bnx2x *bp) · 6 unmodified lines | |||
| 562 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | 600 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); |
| 563 | if (rc) { | 601 | if (rc) { |
| 564 | BNX2X_ERR("failed to send message to pf. rc was %d\n", rc); | 602 | BNX2X_ERR("failed to send message to pf. rc was %d\n", rc); |
| 565 | return rc; | 603 | goto out; |
| 566 | } | 604 | } |
| 567 | 605 | ||
| 568 | /* failure may mean PF was configured with a new mac for us */ | 606 | /* failure may mean PF was configured with a new mac for us */ |
| @@ -570,6 +608,9 @@ int bnx2x_vfpf_set_mac(struct bnx2x *bp) · 1 unmodified line | |||
| 570 | DP(BNX2X_MSG_IOV, | 608 | DP(BNX2X_MSG_IOV, |
| 571 | "vfpf SET MAC failed. Check bulletin board for new posts\n"); | 609 | "vfpf SET MAC failed. Check bulletin board for new posts\n"); |
| 572 | 610 | ||
| 611 | /* copy mac from bulletin to device */ | ||
| 612 | memcpy(bp->dev->dev_addr, bulletin.mac, ETH_ALEN); | ||
| 613 | |||
| 573 | /* check if bulletin board was updated */ | 614 | /* check if bulletin board was updated */ |
| 574 | if (bnx2x_sample_bulletin(bp) == PFVF_BULLETIN_UPDATED) { | 615 | if (bnx2x_sample_bulletin(bp) == PFVF_BULLETIN_UPDATED) { |
| 575 | /* copy mac from device to request */ | 616 | /* copy mac from device to request */ |
| @@ -587,8 +628,10 @@ int bnx2x_vfpf_set_mac(struct bnx2x *bp) · 11 unmodified lines | |||
| 587 | 628 | ||
| 588 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | 629 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { |
| 589 | BNX2X_ERR("vfpf SET MAC failed: %d\n", resp->hdr.status); | 630 | BNX2X_ERR("vfpf SET MAC failed: %d\n", resp->hdr.status); |
| 590 | return -EINVAL; | 631 | rc = -EINVAL; |
| 591 | } | 632 | } |
| 633 | out: | ||
| 634 | bnx2x_vfpf_finalize(bp, &req->first_tlv); | ||
| 592 | 635 | ||
| 593 | return 0; | 636 | return 0; |
| 594 | } | 637 | } |
| @@ -643,14 +686,16 @@ int bnx2x_vfpf_set_mcast(struct net_device *dev) · 48 unmodified lines | |||
| 643 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | 686 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); |
| 644 | if (rc) { | 687 | if (rc) { |
| 645 | BNX2X_ERR("Sending a message failed: %d\n", rc); | 688 | BNX2X_ERR("Sending a message failed: %d\n", rc); |
| 646 | return rc; | 689 | goto out; |
| 647 | } | 690 | } |
| 648 | 691 | ||
| 649 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | 692 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { |
| 650 | BNX2X_ERR("Set Rx mode/multicast failed: %d\n", | 693 | BNX2X_ERR("Set Rx mode/multicast failed: %d\n", |
| 651 | resp->hdr.status); | 694 | resp->hdr.status); |
| 652 | return -EINVAL; | 695 | rc = -EINVAL; |
| 653 | } | 696 | } |
| 697 | out: | ||
| 698 | bnx2x_vfpf_finalize(bp, &req->first_tlv); | ||
| 654 | 699 | ||
| 655 | return 0; | 700 | return 0; |
| 656 | } | 701 | } |
| @@ -689,7 +734,8 @@ int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp) · 32 unmodified lines | |||
| 689 | break; | 734 | break; |
| 690 | default: | 735 | default: |
| 691 | BNX2X_ERR("BAD rx mode (%d)\n", mode); | 736 | BNX2X_ERR("BAD rx mode (%d)\n", mode); |
| 692 | return -EINVAL; | 737 | rc = -EINVAL; |
| 738 | goto out; | ||
| 693 | } | 739 | } |
| 694 | 740 | ||
| 695 | req->flags |= VFPF_SET_Q_FILTERS_RX_MASK_CHANGED; | 741 | req->flags |= VFPF_SET_Q_FILTERS_RX_MASK_CHANGED; |
| @@ -708,8 +754,10 @@ int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp) · 12 unmodified lines | |||
| 708 | 754 | ||
| 709 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | 755 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { |
| 710 | BNX2X_ERR("Set Rx mode failed: %d\n", resp->hdr.status); | 756 | BNX2X_ERR("Set Rx mode failed: %d\n", resp->hdr.status); |
| 711 | return -EINVAL; | 757 | rc = -EINVAL; |
| 712 | } | 758 | } |
| 759 | out: | ||
| 760 | bnx2x_vfpf_finalize(bp, &req->first_tlv); | ||
| 713 | 761 | ||
| 714 | return rc; | 762 | return rc; |
| 715 | } | 763 | } |
| @@ -1004,7 +1052,7 @@ static void bnx2x_vf_mbx_init_vf(struct bnx2x *bp, struct bnx2x_virtf *vf, · 288 unmodified lines | |||
| 1004 | } | 1052 | } |
| 1005 | 1053 | ||
| 1006 | /* convert MBX queue-flags to standard SP queue-flags */ | 1054 | /* convert MBX queue-flags to standard SP queue-flags */ |
| 1007 | static void bnx2x_vf_mbx_set_q_flags(u32 mbx_q_flags, | 1055 | static void bnx2x_vf_mbx_set_q_flags(struct bnx2x *bp, u32 mbx_q_flags, |
| 1008 | unsigned long *sp_q_flags) | 1056 | unsigned long *sp_q_flags) |
| 1009 | { | 1057 | { |
| 1010 | if (mbx_q_flags & VFPF_QUEUE_FLG_TPA) | 1058 | if (mbx_q_flags & VFPF_QUEUE_FLG_TPA) |
| @@ -1015,8 +1063,6 @@ static void bnx2x_vf_mbx_set_q_flags(u32 mbx_q_flags, · 4 unmodified lines | |||
| 1015 | __set_bit(BNX2X_Q_FLG_TPA_GRO, sp_q_flags); | 1063 | __set_bit(BNX2X_Q_FLG_TPA_GRO, sp_q_flags); |
| 1016 | if (mbx_q_flags & VFPF_QUEUE_FLG_STATS) | 1064 | if (mbx_q_flags & VFPF_QUEUE_FLG_STATS) |
| 1017 | __set_bit(BNX2X_Q_FLG_STATS, sp_q_flags); | 1065 | __set_bit(BNX2X_Q_FLG_STATS, sp_q_flags); |
| 1018 | if (mbx_q_flags & VFPF_QUEUE_FLG_OV) | ||
| 1019 | __set_bit(BNX2X_Q_FLG_OV, sp_q_flags); | ||
| 1020 | if (mbx_q_flags & VFPF_QUEUE_FLG_VLAN) | 1066 | if (mbx_q_flags & VFPF_QUEUE_FLG_VLAN) |
| 1021 | __set_bit(BNX2X_Q_FLG_VLAN, sp_q_flags); | 1067 | __set_bit(BNX2X_Q_FLG_VLAN, sp_q_flags); |
| 1022 | if (mbx_q_flags & VFPF_QUEUE_FLG_COS) | 1068 | if (mbx_q_flags & VFPF_QUEUE_FLG_COS) |
| @@ -1025,6 +1071,10 @@ static void bnx2x_vf_mbx_set_q_flags(u32 mbx_q_flags, · 2 unmodified lines | |||
| 1025 | __set_bit(BNX2X_Q_FLG_HC, sp_q_flags); | 1071 | __set_bit(BNX2X_Q_FLG_HC, sp_q_flags); |
| 1026 | if (mbx_q_flags & VFPF_QUEUE_FLG_DHC) | 1072 | if (mbx_q_flags & VFPF_QUEUE_FLG_DHC) |
| 1027 | __set_bit(BNX2X_Q_FLG_DHC, sp_q_flags); | 1073 | __set_bit(BNX2X_Q_FLG_DHC, sp_q_flags); |
| 1074 | |||
| 1075 | /* outer vlan removal is set according to the PF's multi fuction mode */ | ||
| 1076 | if (IS_MF_SD(bp)) | ||
| 1077 | __set_bit(BNX2X_Q_FLG_OV, sp_q_flags); | ||
| 1028 | } | 1078 | } |
| 1029 | 1079 | ||
| 1030 | static void bnx2x_vf_mbx_setup_q(struct bnx2x *bp, struct bnx2x_virtf *vf, | 1080 | static void bnx2x_vf_mbx_setup_q(struct bnx2x *bp, struct bnx2x_virtf *vf, |
| @@ -1075,11 +1125,11 @@ static void bnx2x_vf_mbx_setup_q(struct bnx2x *bp, struct bnx2x_virtf *vf, · 44 unmodified lines | |||
| 1075 | init_p->tx.hc_rate = setup_q->txq.hc_rate; | 1125 | init_p->tx.hc_rate = setup_q->txq.hc_rate; |
| 1076 | init_p->tx.sb_cq_index = setup_q->txq.sb_index; | 1126 | init_p->tx.sb_cq_index = setup_q->txq.sb_index; |
| 1077 | 1127 | ||
| 1078 | bnx2x_vf_mbx_set_q_flags(setup_q->txq.flags, | 1128 | bnx2x_vf_mbx_set_q_flags(bp, setup_q->txq.flags, |
| 1079 | &init_p->tx.flags); | 1129 | &init_p->tx.flags); |
| 1080 | 1130 | ||
| 1081 | /* tx setup - flags */ | 1131 | /* tx setup - flags */ |
| 1082 | bnx2x_vf_mbx_set_q_flags(setup_q->txq.flags, | 1132 | bnx2x_vf_mbx_set_q_flags(bp, setup_q->txq.flags, |
| 1083 | &setup_p->flags); | 1133 | &setup_p->flags); |
| 1084 | 1134 | ||
| 1085 | /* tx setup - general, nothing */ | 1135 | /* tx setup - general, nothing */ |
| @@ -1107,11 +1157,11 @@ static void bnx2x_vf_mbx_setup_q(struct bnx2x *bp, struct bnx2x_virtf *vf, · 21 unmodified lines | |||
| 1107 | /* rx init */ | 1157 | /* rx init */ |
| 1108 | init_p->rx.hc_rate = setup_q->rxq.hc_rate; | 1158 | init_p->rx.hc_rate = setup_q->rxq.hc_rate; |
| 1109 | init_p->rx.sb_cq_index = setup_q->rxq.sb_index; | 1159 | init_p->rx.sb_cq_index = setup_q->rxq.sb_index; |
| 1110 | bnx2x_vf_mbx_set_q_flags(setup_q->rxq.flags, | 1160 | bnx2x_vf_mbx_set_q_flags(bp, setup_q->rxq.flags, |
| 1111 | &init_p->rx.flags); | 1161 | &init_p->rx.flags); |
| 1112 | 1162 | ||
| 1113 | /* rx setup - flags */ | 1163 | /* rx setup - flags */ |
| 1114 | bnx2x_vf_mbx_set_q_flags(setup_q->rxq.flags, | 1164 | bnx2x_vf_mbx_set_q_flags(bp, setup_q->rxq.flags, |
| 1115 | &setup_p->flags); | 1165 | &setup_p->flags); |
| 1116 | 1166 | ||
| 1117 | /* rx setup - general */ | 1167 | /* rx setup - general */ |
| @@ -328,9 +328,15 @@ struct pf_vf_bulletin_content { · 327 unmodified lines | |||
| 328 | #define MAC_ADDR_VALID 0 /* alert the vf that a new mac address | 328 | #define MAC_ADDR_VALID 0 /* alert the vf that a new mac address |
| 329 | * is available for it | 329 | * is available for it |
| 330 | */ | 330 | */ |
| 331 | #define VLAN_VALID 1 /* when set, the vf should not access | ||
| 332 | * the vfpf channel | ||
| 333 | */ | ||
| 331 | 334 | ||
| 332 | u8 mac[ETH_ALEN]; | 335 | u8 mac[ETH_ALEN]; |
| 333 | u8 padding[2]; | 336 | u8 mac_padding[2]; |
| 337 | |||
| 338 | u16 vlan; | ||
| 339 | u8 vlan_padding[6]; | ||
| 334 | }; | 340 | }; |
| 335 | 341 | ||
| 336 | union pf_vf_bulletin { | 342 | union pf_vf_bulletin { |
| @@ -353,6 +359,7 @@ enum channel_tlvs { · 16 unmodified lines | |||
| 353 | CHANNEL_TLV_LIST_END, | 359 | CHANNEL_TLV_LIST_END, |
| 354 | CHANNEL_TLV_FLR, | 360 | CHANNEL_TLV_FLR, |
| 355 | CHANNEL_TLV_PF_SET_MAC, | 361 | CHANNEL_TLV_PF_SET_MAC, |
| 362 | CHANNEL_TLV_PF_SET_VLAN, | ||
| 356 | CHANNEL_TLV_MAX | 363 | CHANNEL_TLV_MAX |
| 357 | }; | 364 | }; |
| 358 | 365 | ||
| @@ -5544,8 +5544,10 @@ static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev) · 5543 unmodified lines | |||
| 5544 | 5544 | ||
| 5545 | if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)) | 5545 | if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)) |
| 5546 | cdev->max_iscsi_conn = ethdev->max_iscsi_conn; | 5546 | cdev->max_iscsi_conn = ethdev->max_iscsi_conn; |
| 5547 | if (CNIC_SUPPORTS_FCOE(cp)) | 5547 | if (CNIC_SUPPORTS_FCOE(cp)) { |
| 5548 | cdev->max_fcoe_conn = ethdev->max_fcoe_conn; | 5548 | cdev->max_fcoe_conn = ethdev->max_fcoe_conn; |
| 5549 | cdev->max_fcoe_exchanges = ethdev->max_fcoe_exchanges; | ||
| 5550 | } | ||
| 5549 | 5551 | ||
| 5550 | if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS) | 5552 | if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS) |
| 5551 | cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS; | 5553 | cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS; |
| @@ -195,6 +195,7 @@ struct cnic_eth_dev { · 194 unmodified lines | |||
| 195 | u32 max_fcoe_conn; | 195 | u32 max_fcoe_conn; |
| 196 | u32 max_rdma_conn; | 196 | u32 max_rdma_conn; |
| 197 | u32 fcoe_init_cid; | 197 | u32 fcoe_init_cid; |
| 198 | u32 max_fcoe_exchanges; | ||
| 198 | u32 fcoe_wwn_port_name_hi; | 199 | u32 fcoe_wwn_port_name_hi; |
| 199 | u32 fcoe_wwn_port_name_lo; | 200 | u32 fcoe_wwn_port_name_lo; |
| 200 | u32 fcoe_wwn_node_name_hi; | 201 | u32 fcoe_wwn_node_name_hi; |
| @@ -313,6 +314,8 @@ struct cnic_dev { · 112 unmodified lines | |||
| 313 | int max_fcoe_conn; | 314 | int max_fcoe_conn; |
| 314 | int max_rdma_conn; | 315 | int max_rdma_conn; |
| 315 | 316 | ||
| 317 | int max_fcoe_exchanges; | ||
| 318 | |||
| 316 | union drv_info_to_mcp *stats_addr; | 319 | union drv_info_to_mcp *stats_addr; |
| 317 | struct fcoe_capabilities *fcoe_cap; | 320 | struct fcoe_capabilities *fcoe_cap; |
| 318 | 321 | ||
| @@ -831,11 +831,8 @@ static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, · 830 unmodified lines | |||
| 831 | sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE + | 831 | sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE + |
| 832 | SMP_CACHE_BYTES * 2 + | 832 | SMP_CACHE_BYTES * 2 + |
| 833 | NET_IP_ALIGN); | 833 | NET_IP_ALIGN); |
| 834 | if (sb_new == NULL) { | 834 | if (sb_new == NULL) |
| 835 | pr_info("%s: sk_buff allocation failed\n", | ||
| 836 | d->sbdma_eth->sbm_dev->name); | ||
| 837 | return -ENOBUFS; | 835 | return -ENOBUFS; |
| 838 | } | ||
| 839 | 836 | ||
| 840 | sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN); | 837 | sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN); |
| 841 | } | 838 | } |
| @@ -94,10 +94,10 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) · 93 unmodified lines | |||
| 94 | 94 | ||
| 95 | #define DRV_MODULE_NAME "tg3" | 95 | #define DRV_MODULE_NAME "tg3" |
| 96 | #define TG3_MAJ_NUM 3 | 96 | #define TG3_MAJ_NUM 3 |
| 97 | #define TG3_MIN_NUM 130 | 97 | #define TG3_MIN_NUM 131 |
| 98 | #define DRV_MODULE_VERSION \ | 98 | #define DRV_MODULE_VERSION \ |
| 99 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) | 99 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) |
| 100 | #define DRV_MODULE_RELDATE "February 14, 2013" | 100 | #define DRV_MODULE_RELDATE "April 09, 2013" |
| 101 | 101 | ||
| 102 | #define RESET_KIND_SHUTDOWN 0 | 102 | #define RESET_KIND_SHUTDOWN 0 |
| 103 | #define RESET_KIND_INIT 1 | 103 | #define RESET_KIND_INIT 1 |
| @@ -212,6 +212,7 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) · 108 unmodified lines | |||
| 212 | #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2) | 212 | #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2) |
| 213 | 213 | ||
| 214 | #define FIRMWARE_TG3 "tigon/tg3.bin" | 214 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
| 215 | #define FIRMWARE_TG357766 "tigon/tg357766.bin" | ||
| 215 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | 216 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" |
| 216 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | 217 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" |
| 217 | 218 | ||
| @@ -1873,6 +1874,20 @@ static void tg3_link_report(struct tg3 *tp) · 1655 unmodified lines | |||
| 1873 | tp->link_up = netif_carrier_ok(tp->dev); | 1874 | tp->link_up = netif_carrier_ok(tp->dev); |
| 1874 | } | 1875 | } |
| 1875 | 1876 | ||
| 1877 | static u32 tg3_decode_flowctrl_1000T(u32 adv) | ||
| 1878 | { | ||
| 1879 | u32 flowctrl = 0; | ||
| 1880 | |||
| 1881 | if (adv & ADVERTISE_PAUSE_CAP) { | ||
| 1882 | flowctrl |= FLOW_CTRL_RX; | ||
| 1883 | if (!(adv & ADVERTISE_PAUSE_ASYM)) | ||
| 1884 | flowctrl |= FLOW_CTRL_TX; | ||
| 1885 | } else if (adv & ADVERTISE_PAUSE_ASYM) | ||
| 1886 | flowctrl |= FLOW_CTRL_TX; | ||
| 1887 | |||
| 1888 | return flowctrl; | ||
| 1889 | } | ||
| 1890 | |||
| 1876 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | 1891 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) |
| 1877 | { | 1892 | { |
| 1878 | u16 miireg; | 1893 | u16 miireg; |
| @@ -1889,6 +1904,20 @@ static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) · 10 unmodified lines | |||
| 1889 | return miireg; | 1904 | return miireg; |
| 1890 | } | 1905 | } |
| 1891 | 1906 | ||
| 1907 | static u32 tg3_decode_flowctrl_1000X(u32 adv) | ||
| 1908 | { | ||
| 1909 | u32 flowctrl = 0; | ||
| 1910 | |||
| 1911 | if (adv & ADVERTISE_1000XPAUSE) { | ||
| 1912 | flowctrl |= FLOW_CTRL_RX; | ||
| 1913 | if (!(adv & ADVERTISE_1000XPSE_ASYM)) | ||
| 1914 | flowctrl |= FLOW_CTRL_TX; | ||
| 1915 | } else if (adv & ADVERTISE_1000XPSE_ASYM) | ||
| 1916 | flowctrl |= FLOW_CTRL_TX; | ||
| 1917 | |||
| 1918 | return flowctrl; | ||
| 1919 | } | ||
| 1920 | |||
| 1892 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) | 1921 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
| 1893 | { | 1922 | { |
| 1894 | u8 cap = 0; | 1923 | u8 cap = 0; |
| @@ -2199,7 +2228,7 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) · 304 unmodified lines | |||
| 2199 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | 2228 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); |
| 2200 | } | 2229 | } |
| 2201 | 2230 | ||
| 2202 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) | 2231 | static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) |
| 2203 | { | 2232 | { |
| 2204 | u32 phy; | 2233 | u32 phy; |
| 2205 | 2234 | ||
| @@ -2291,7 +2320,7 @@ static void tg3_phy_apply_otp(struct tg3 *tp) · 85 unmodified lines | |||
| 2291 | tg3_phy_toggle_auxctl_smdsp(tp, false); | 2320 | tg3_phy_toggle_auxctl_smdsp(tp, false); |
| 2292 | } | 2321 | } |
| 2293 | 2322 | ||
| 2294 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) | 2323 | static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up) |
| 2295 | { | 2324 | { |
| 2296 | u32 val; | 2325 | u32 val; |
| 2297 | 2326 | ||
| @@ -2301,7 +2330,7 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) · 3 unmodified lines | |||
| 2301 | tp->setlpicnt = 0; | 2330 | tp->setlpicnt = 0; |
| 2302 | 2331 | ||
| 2303 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | 2332 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
| 2304 | current_link_up == 1 && | 2333 | current_link_up && |
| 2305 | tp->link_config.active_duplex == DUPLEX_FULL && | 2334 | tp->link_config.active_duplex == DUPLEX_FULL && |
| 2306 | (tp->link_config.active_speed == SPEED_100 || | 2335 | (tp->link_config.active_speed == SPEED_100 || |
| 2307 | tp->link_config.active_speed == SPEED_1000)) { | 2336 | tp->link_config.active_speed == SPEED_1000)) { |
| @@ -2323,7 +2352,7 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) · 15 unmodified lines | |||
| 2323 | } | 2352 | } |
| 2324 | 2353 | ||
| 2325 | if (!tp->setlpicnt) { | 2354 | if (!tp->setlpicnt) { |
| 2326 | if (current_link_up == 1 && | 2355 | if (current_link_up && |
| 2327 | !tg3_phy_toggle_auxctl_smdsp(tp, true)) { | 2356 | !tg3_phy_toggle_auxctl_smdsp(tp, true)) { |
| 2328 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | 2357 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); |
| 2329 | tg3_phy_toggle_auxctl_smdsp(tp, false); | 2358 | tg3_phy_toggle_auxctl_smdsp(tp, false); |
| @@ -2530,6 +2559,13 @@ static void tg3_carrier_off(struct tg3 *tp) · 200 unmodified lines | |||
| 2530 | tp->link_up = false; | 2559 | tp->link_up = false; |
| 2531 | } | 2560 | } |
| 2532 | 2561 | ||
| 2562 | static void tg3_warn_mgmt_link_flap(struct tg3 *tp) | ||
| 2563 | { | ||
| 2564 | if (tg3_flag(tp, ENABLE_ASF)) | ||
| 2565 | netdev_warn(tp->dev, | ||
| 2566 | "Management side-band traffic will be interrupted during phy settings change\n"); | ||
| 2567 | } | ||
| 2568 | |||
| 2533 | /* This will reset the tigon3 PHY if there is no valid | 2569 | /* This will reset the tigon3 PHY if there is no valid |
| 2534 | * link unless the FORCE argument is non-zero. | 2570 | * link unless the FORCE argument is non-zero. |
| 2535 | */ | 2571 | */ |
| @@ -2669,7 +2705,7 @@ out: · 133 unmodified lines | |||
| 2669 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) | 2705 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) |
| 2670 | tg3_phydsp_write(tp, 0xffb, 0x4000); | 2706 | tg3_phydsp_write(tp, 0xffb, 0x4000); |
| 2671 | 2707 | ||
| 2672 | tg3_phy_toggle_automdix(tp, 1); | 2708 | tg3_phy_toggle_automdix(tp, true); |
| 2673 | tg3_phy_set_wirespeed(tp); | 2709 | tg3_phy_set_wirespeed(tp); |
| 2674 | return 0; | 2710 | return 0; |
| 2675 | } | 2711 | } |
| @@ -2925,6 +2961,9 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) · 249 unmodified lines | |||
| 2925 | { | 2961 | { |
| 2926 | u32 val; | 2962 | u32 val; |
| 2927 | 2963 | ||
| 2964 | if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) | ||
| 2965 | return; | ||
| 2966 | |||
| 2928 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | 2967 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
| 2929 | if (tg3_asic_rev(tp) == ASIC_REV_5704) { | 2968 | if (tg3_asic_rev(tp) == ASIC_REV_5704) { |
| 2930 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | 2969 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); |
| @@ -3448,11 +3487,58 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) · 517 unmodified lines | |||
| 3448 | #define TX_CPU_SCRATCH_SIZE 0x04000 | 3487 | #define TX_CPU_SCRATCH_SIZE 0x04000 |
| 3449 | 3488 | ||
| 3450 | /* tp->lock is held. */ | 3489 | /* tp->lock is held. */ |
| 3451 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | 3490 | static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) |
| 3452 | { | 3491 | { |
| 3453 | int i; | 3492 | int i; |
| 3493 | const int iters = 10000; | ||
| 3494 | |||
| 3495 | for (i = 0; i < iters; i++) { | ||
| 3496 | tw32(cpu_base + CPU_STATE, 0xffffffff); | ||
| 3497 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | ||
| 3498 | if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT) | ||
| 3499 | break; | ||
| 3500 | } | ||
| 3501 | |||
| 3502 | return (i == iters) ? -EBUSY : 0; | ||
| 3503 | } | ||
| 3504 | |||
| 3505 | /* tp->lock is held. */ | ||
| 3506 | static int tg3_rxcpu_pause(struct tg3 *tp) | ||
| 3507 | { | ||
| 3508 | int rc = tg3_pause_cpu(tp, RX_CPU_BASE); | ||
| 3509 | |||
| 3510 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | ||
| 3511 | tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | ||
| 3512 | udelay(10); | ||
| 3513 | |||
| 3514 | return rc; | ||
| 3515 | } | ||
| 3516 | |||
| 3517 | /* tp->lock is held. */ | ||
| 3518 | static int tg3_txcpu_pause(struct tg3 *tp) | ||
| 3519 | { | ||
| 3520 | return tg3_pause_cpu(tp, TX_CPU_BASE); | ||
| 3521 | } | ||
| 3522 | |||
| 3523 | /* tp->lock is held. */ | ||
| 3524 | static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) | ||
| 3525 | { | ||
| 3526 | tw32(cpu_base + CPU_STATE, 0xffffffff); | ||
| 3527 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | ||
| 3528 | } | ||
| 3454 | 3529 | ||
| 3455 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); | 3530 | /* tp->lock is held. */ |
| 3531 | static void tg3_rxcpu_resume(struct tg3 *tp) | ||
| 3532 | { | ||
| 3533 | tg3_resume_cpu(tp, RX_CPU_BASE); | ||
| 3534 | } | ||
| 3535 | |||
| 3536 | /* tp->lock is held. */ | ||
| 3537 | static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) | ||
| 3538 | { | ||
| 3539 | int rc; | ||
| 3540 | |||
| 3541 | BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); | ||
| 3456 | 3542 | ||
| 3457 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { | 3543 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
| 3458 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | 3544 | u32 val = tr32(GRC_VCPU_EXT_CTRL); |
| @@ -3460,17 +3546,8 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset) · 1 unmodified line | |||
| 3460 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | 3546 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); |
| 3461 | return 0; | 3547 | return 0; |
| 3462 | } | 3548 | } |
| 3463 | if (offset == RX_CPU_BASE) { | 3549 | if (cpu_base == RX_CPU_BASE) { |
| 3464 | for (i = 0; i < 10000; i++) { | 3550 | rc = tg3_rxcpu_pause(tp); |
| 3465 | tw32(offset + CPU_STATE, 0xffffffff); | ||
| 3466 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | ||
| 3467 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | ||
| 3468 | break; | ||
| 3469 | } | ||
| 3470 | |||
| 3471 | tw32(offset + CPU_STATE, 0xffffffff); | ||
| 3472 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | ||
| 3473 | udelay(10); | ||
| 3474 | } else { | 3551 | } else { |
| 3475 | /* | 3552 | /* |
| 3476 | * There is only an Rx CPU for the 5750 derivative in the | 3553 | * There is only an Rx CPU for the 5750 derivative in the |
| @@ -3479,17 +3556,12 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset) · 2 unmodified lines | |||
| 3479 | if (tg3_flag(tp, IS_SSB_CORE)) | 3556 | if (tg3_flag(tp, IS_SSB_CORE)) |
| 3480 | return 0; | 3557 | return 0; |
| 3481 | 3558 | ||
| 3482 | for (i = 0; i < 10000; i++) { | 3559 | rc = tg3_txcpu_pause(tp); |
| 3483 | tw32(offset + CPU_STATE, 0xffffffff); | ||
| 3484 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | ||
| 3485 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | ||
| 3486 | break; | ||
| 3487 | } | ||
| 3488 | } | 3560 | } |
| 3489 | 3561 | ||
| 3490 | if (i >= 10000) { | 3562 | if (rc) { |
| 3491 | netdev_err(tp->dev, "%s timed out, %s CPU\n", | 3563 | netdev_err(tp->dev, "%s timed out, %s CPU\n", |
| 3492 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | 3564 | __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX"); |
| 3493 | return -ENODEV; | 3565 | return -ENODEV; |
| 3494 | } | 3566 | } |
| 3495 | 3567 | ||
| @@ -3499,19 +3571,41 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset) · 3 unmodified lines | |||
| 3499 | return 0; | 3571 | return 0; |
| 3500 | } | 3572 | } |
| 3501 | 3573 | ||
| 3502 | struct fw_info { | 3574 | static int tg3_fw_data_len(struct tg3 *tp, |
| 3503 | unsigned int fw_base; | 3575 | const struct tg3_firmware_hdr *fw_hdr) |
| 3504 | unsigned int fw_len; | 3576 | { |
| 3505 | const __be32 *fw_data; | 3577 | int fw_len; |
| 3506 | }; | 3578 | |
| 3579 | /* Non fragmented firmware have one firmware header followed by a | ||
| 3580 | * contiguous chunk of data to be written. The length field in that | ||
| 3581 | * header is not the length of data to be written but the complete | ||
| 3582 | * length of the bss. The data length is determined based on | ||
| 3583 | * tp->fw->size minus headers. | ||
| 3584 | * | ||
| 3585 | * Fragmented firmware have a main header followed by multiple | ||
| 3586 | * fragments. Each fragment is identical to non fragmented firmware | ||
| 3587 | * with a firmware header followed by a contiguous chunk of data. In | ||
| 3588 | * the main header, the length field is unused and set to 0xffffffff. | ||
| 3589 | * In each fragment header the length is the entire size of that | ||
| 3590 | * fragment i.e. fragment data + header length. Data length is | ||
| 3591 | * therefore length field in the header minus TG3_FW_HDR_LEN. | ||
| 3592 | */ | ||
| 3593 | if (tp->fw_len == 0xffffffff) | ||
| 3594 | fw_len = be32_to_cpu(fw_hdr->len); | ||
| 3595 | else | ||
| 3596 | fw_len = tp->fw->size; | ||
| 3597 | |||
| 3598 | return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32); | ||
| 3599 | } | ||
| 3507 | 3600 | ||
| 3508 | /* tp->lock is held. */ | 3601 | /* tp->lock is held. */ |
| 3509 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, | 3602 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, |
| 3510 | u32 cpu_scratch_base, int cpu_scratch_size, | 3603 | u32 cpu_scratch_base, int cpu_scratch_size, |
| 3511 | struct fw_info *info) | 3604 | const struct tg3_firmware_hdr *fw_hdr) |
| 3512 | { | 3605 | { |
| 3513 | int err, lock_err, i; | 3606 | int err, i; |
| 3514 | void (*write_op)(struct tg3 *, u32, u32); | 3607 | void (*write_op)(struct tg3 *, u32, u32); |
| 3608 | int total_len = tp->fw->size; | ||
| 3515 | 3609 | ||
| 3516 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { | 3610 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { |
| 3517 | netdev_err(tp->dev, | 3611 | netdev_err(tp->dev, |
| @@ -3520,30 +3614,49 @@ static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, · 2 unmodified lines | |||
| 3520 | return -EINVAL; | 3614 | return -EINVAL; |
| 3521 | } | 3615 | } |
| 3522 | 3616 | ||
| 3523 | if (tg3_flag(tp, 5705_PLUS)) | 3617 | if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766) |
| 3524 | write_op = tg3_write_mem; | 3618 | write_op = tg3_write_mem; |
| 3525 | else | 3619 | else |
| 3526 | write_op = tg3_write_indirect_reg32; | 3620 | write_op = tg3_write_indirect_reg32; |
| 3527 | 3621 | ||
| 3528 | /* It is possible that bootcode is still loading at this point. | 3622 | if (tg3_asic_rev(tp) != ASIC_REV_57766) { |
| 3529 | * Get the nvram lock first before halting the cpu. | 3623 | /* It is possible that bootcode is still loading at this point. |
| 3530 | */ | 3624 | * Get the nvram lock first before halting the cpu. |
| 3531 | lock_err = tg3_nvram_lock(tp); | 3625 | */ |
| 3532 | err = tg3_halt_cpu(tp, cpu_base); | 3626 | int lock_err = tg3_nvram_lock(tp); |
| 3533 | if (!lock_err) | 3627 | err = tg3_halt_cpu(tp, cpu_base); |
| 3534 | tg3_nvram_unlock(tp); | 3628 | if (!lock_err) |
| 3535 | if (err) | 3629 | tg3_nvram_unlock(tp); |
| 3536 | goto out; | 3630 | if (err) |
| 3631 | goto out; | ||
| 3537 | 3632 | ||
| 3538 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | 3633 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) |
| 3539 | write_op(tp, cpu_scratch_base + i, 0); | 3634 | write_op(tp, cpu_scratch_base + i, 0); |
| 3540 | tw32(cpu_base + CPU_STATE, 0xffffffff); | 3635 | tw32(cpu_base + CPU_STATE, 0xffffffff); |
| 3541 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | 3636 | tw32(cpu_base + CPU_MODE, |
| 3542 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) | 3637 | tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT); |
| 3543 | write_op(tp, (cpu_scratch_base + | 3638 | } else { |
| 3544 | (info->fw_base & 0xffff) + | 3639 | /* Subtract additional main header for fragmented firmware and |
| 3545 | (i * sizeof(u32))), | 3640 | * advance to the first fragment |
| 3546 | be32_to_cpu(info->fw_data[i])); | 3641 | */ |
| 3642 | total_len -= TG3_FW_HDR_LEN; | ||
| 3643 | fw_hdr++; | ||
| 3644 | } | ||
| 3645 | |||
| 3646 | do { | ||
| 3647 | u32 *fw_data = (u32 *)(fw_hdr + 1); | ||
| 3648 | for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++) | ||
| 3649 | write_op(tp, cpu_scratch_base + | ||
| 3650 | (be32_to_cpu(fw_hdr->base_addr) & 0xffff) + | ||
| 3651 | (i * sizeof(u32)), | ||
| 3652 | be32_to_cpu(fw_data[i])); | ||
| 3653 | |||
| 3654 | total_len -= be32_to_cpu(fw_hdr->len); | ||
| 3655 | |||
| 3656 | /* Advance to next fragment */ | ||
| 3657 | fw_hdr = (struct tg3_firmware_hdr *) | ||
| 3658 | ((void *)fw_hdr + be32_to_cpu(fw_hdr->len)); | ||
| 3659 | } while (total_len > 0); | ||
| 3547 | 3660 | ||
| 3548 | err = 0; | 3661 | err = 0; |
| 3549 | 3662 | ||
| @@ -3551,14 +3664,34 @@ out: · 1 unmodified line | |||
| 3551 | return err; | 3664 | return err; |
| 3552 | } | 3665 | } |
| 3553 | 3666 | ||
| 3667 | /* tp->lock is held. */ | ||
| 3668 | static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc) | ||
| 3669 | { | ||
| 3670 | int i; | ||
| 3671 | const int iters = 5; | ||
| 3672 | |||
| 3673 | tw32(cpu_base + CPU_STATE, 0xffffffff); | ||
| 3674 | tw32_f(cpu_base + CPU_PC, pc); | ||
| 3675 | |||
| 3676 | for (i = 0; i < iters; i++) { | ||
| 3677 | if (tr32(cpu_base + CPU_PC) == pc) | ||
| 3678 | break; | ||
| 3679 | tw32(cpu_base + CPU_STATE, 0xffffffff); | ||
| 3680 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | ||
| 3681 | tw32_f(cpu_base + CPU_PC, pc); | ||
| 3682 | udelay(1000); | ||
| 3683 | } | ||
| 3684 | |||
| 3685 | return (i == iters) ? -EBUSY : 0; | ||
| 3686 | } | ||
| 3687 | |||
| 3554 | /* tp->lock is held. */ | 3688 | /* tp->lock is held. */ |
| 3555 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | 3689 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) |
| 3556 | { | 3690 | { |
| 3557 | struct fw_info info; | 3691 | const struct tg3_firmware_hdr *fw_hdr; |
| 3558 | const __be32 *fw_data; | 3692 | int err; |
| 3559 | int err, i; | ||
| 3560 | 3693 | ||
| 3561 | fw_data = (void *)tp->fw->data; | 3694 | fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; |
| 3562 | 3695 | ||
| 3563 | /* Firmware blob starts with version numbers, followed by | 3696 | /* Firmware blob starts with version numbers, followed by |
| 3564 | start address and length. We are setting complete length. | 3697 | start address and length. We are setting complete length. |
| @@ -3566,60 +3699,117 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) · 1 unmodified line | |||
| 3566 | Remainder is the blob to be loaded contiguously | 3699 | Remainder is the blob to be loaded contiguously |
| 3567 | from start address. */ | 3700 | from start address. */ |
| 3568 | 3701 | ||
| 3569 | info.fw_base = be32_to_cpu(fw_data[1]); | ||
| 3570 | info.fw_len = tp->fw->size - 12; | ||
| 3571 | info.fw_data = &fw_data[3]; | ||
| 3572 | |||
| 3573 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | 3702 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, |
| 3574 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | 3703 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, |
| 3575 | &info); | 3704 | fw_hdr); |
| 3576 | if (err) | 3705 | if (err) |
| 3577 | return err; | 3706 | return err; |
| 3578 | 3707 | ||
| 3579 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | 3708 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, |
| 3580 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | 3709 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, |
| 3581 | &info); | 3710 | fw_hdr); |
| 3582 | if (err) | 3711 | if (err) |
| 3583 | return err; | 3712 | return err; |
| 3584 | 3713 | ||
| 3585 | /* Now startup only the RX cpu. */ | 3714 | /* Now startup only the RX cpu. */ |
| 3586 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | 3715 | err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE, |
| 3587 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | 3716 | be32_to_cpu(fw_hdr->base_addr)); |
| 3588 | 3717 | if (err) { | |
| 3589 | for (i = 0; i < 5; i++) { | ||
| 3590 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) | ||
| 3591 | break; | ||
| 3592 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | ||
| 3593 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | ||
| 3594 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); | ||
| 3595 | udelay(1000); | ||
| 3596 | } | ||
| 3597 | if (i >= 5) { | ||
| 3598 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " | 3718 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " |
| 3599 | "should be %08x\n", __func__, | 3719 | "should be %08x\n", __func__, |
| 3600 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); | 3720 | tr32(RX_CPU_BASE + CPU_PC), |
| 3721 | be32_to_cpu(fw_hdr->base_addr)); | ||
| 3601 | return -ENODEV; | 3722 | return -ENODEV; |
| 3602 | } | 3723 | } |
| 3603 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | 3724 | |
| 3604 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | 3725 | tg3_rxcpu_resume(tp); |
| 3605 | 3726 | ||
| 3606 | return 0; | 3727 | return 0; |
| 3607 | } | 3728 | } |
| 3608 | 3729 | ||
| 3730 | static int tg3_validate_rxcpu_state(struct tg3 *tp) | ||
| 3731 | { | ||
| 3732 | const int iters = 1000; | ||
| 3733 | int i; | ||
| 3734 | u32 val; | ||
| 3735 | |||
| 3736 | /* Wait for boot code to complete initialization and enter service | ||
| 3737 | * loop. It is then safe to download service patches | ||
| 3738 | */ | ||
| 3739 | for (i = 0; i < iters; i++) { | ||
| 3740 | if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP) | ||
| 3741 | break; | ||
| 3742 | |||
| 3743 | udelay(10); | ||
| 3744 | } | ||
| 3745 | |||
| 3746 | if (i == iters) { | ||
| 3747 | netdev_err(tp->dev, "Boot code not ready for service patches\n"); | ||
| 3748 | return -EBUSY; | ||
| 3749 | } | ||
| 3750 | |||
| 3751 | val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE); | ||
| 3752 | if (val & 0xff) { | ||
| 3753 | netdev_warn(tp->dev, | ||
| 3754 | "Other patches exist. Not downloading EEE patch\n"); | ||
| 3755 | return -EEXIST; | ||
| 3756 | } | ||
| 3757 | |||
| 3758 | return 0; | ||
| 3759 | } | ||
| 3760 | |||
| 3761 | /* tp->lock is held. */ | ||
| 3762 | static void tg3_load_57766_firmware(struct tg3 *tp) | ||
| 3763 | { | ||
| 3764 | struct tg3_firmware_hdr *fw_hdr; | ||
| 3765 | |||
| 3766 | if (!tg3_flag(tp, NO_NVRAM)) | ||
| 3767 | return; | ||
| 3768 | |||
| 3769 | if (tg3_validate_rxcpu_state(tp)) | ||
| 3770 | return; | ||
| 3771 | |||
| 3772 | if (!tp->fw) | ||
| 3773 | return; | ||
| 3774 | |||
| 3775 | /* This firmware blob has a different format than older firmware | ||
| 3776 | * releases as given below. The main difference is we have fragmented | ||
| 3777 | * data to be written to non-contiguous locations. | ||
| 3778 | * | ||
| 3779 | * In the beginning we have a firmware header identical to other | ||
| 3780 | * firmware which consists of version, base addr and length. The length | ||
| 3781 | * here is unused and set to 0xffffffff. | ||
| 3782 | * | ||
| 3783 | * This is followed by a series of firmware fragments which are | ||
| 3784 | * individually identical to previous firmware. i.e. they have the | ||
| 3785 | * firmware header and followed by data for that fragment. The version | ||
| 3786 | * field of the individual fragment header is unused. | ||
| 3787 | */ | ||
| 3788 | |||
| 3789 | fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; | ||
| 3790 | if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR) | ||
| 3791 | return; | ||
| 3792 | |||
| 3793 | if (tg3_rxcpu_pause(tp)) | ||
| 3794 | return; | ||
| 3795 | |||
| 3796 | /* tg3_load_firmware_cpu() will always succeed for the 57766 */ | ||
| 3797 | tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr); | ||
| 3798 | |||
| 3799 | tg3_rxcpu_resume(tp); | ||
| 3800 | } | ||
| 3801 | |||
| 3609 | /* tp->lock is held. */ | 3802 | /* tp->lock is held. */ |
| 3610 | static int tg3_load_tso_firmware(struct tg3 *tp) | 3803 | static int tg3_load_tso_firmware(struct tg3 *tp) |
| 3611 | { | 3804 | { |
| 3612 | struct fw_info info; | 3805 | const struct tg3_firmware_hdr *fw_hdr; |
| 3613 | const __be32 *fw_data; | ||
| 3614 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; | 3806 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
| 3615 | int err, i; | 3807 | int err; |
| 3616 | 3808 | ||
| 3617 | if (tg3_flag(tp, HW_TSO_1) || | 3809 | if (!tg3_flag(tp, FW_TSO)) |
| 3618 | tg3_flag(tp, HW_TSO_2) || | ||
| 3619 | tg3_flag(tp, HW_TSO_3)) | ||
| 3620 | return 0; | 3810 | return 0; |
| 3621 | 3811 | ||
| 3622 | fw_data = (void *)tp->fw->data; | 3812 | fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; |
| 3623 | 3813 | ||
| 3624 | /* Firmware blob starts with version numbers, followed by | 3814 | /* Firmware blob starts with version numbers, followed by |
| 3625 | start address and length. We are setting complete length. | 3815 | start address and length. We are setting complete length. |
| @@ -3627,10 +3817,7 @@ static int tg3_load_tso_firmware(struct tg3 *tp) · 1 unmodified line | |||
| 3627 | Remainder is the blob to be loaded contiguously | 3817 | Remainder is the blob to be loaded contiguously |
| 3628 | from start address. */ | 3818 | from start address. */ |
| 3629 | 3819 | ||
| 3630 | info.fw_base = be32_to_cpu(fw_data[1]); | ||
| 3631 | cpu_scratch_size = tp->fw_len; | 3820 | cpu_scratch_size = tp->fw_len; |
| 3632 | info.fw_len = tp->fw->size - 12; | ||
| 3633 | info.fw_data = &fw_data[3]; | ||
| 3634 | 3821 | ||
| 3635 | if (tg3_asic_rev(tp) == ASIC_REV_5705) { | 3822 | if (tg3_asic_rev(tp) == ASIC_REV_5705) { |
| 3636 | cpu_base = RX_CPU_BASE; | 3823 | cpu_base = RX_CPU_BASE; |
| @@ -3643,36 +3830,28 @@ static int tg3_load_tso_firmware(struct tg3 *tp) · 6 unmodified lines | |||
| 3643 | 3830 | ||
| 3644 | err = tg3_load_firmware_cpu(tp, cpu_base, | 3831 | err = tg3_load_firmware_cpu(tp, cpu_base, |
| 3645 | cpu_scratch_base, cpu_scratch_size, | 3832 | cpu_scratch_base, cpu_scratch_size, |
| 3646 | &info); | 3833 | fw_hdr); |
| 3647 | if (err) | 3834 | if (err) |
| 3648 | return err; | 3835 | return err; |
| 3649 | 3836 | ||
| 3650 | /* Now startup the cpu. */ | 3837 | /* Now startup the cpu. */ |
| 3651 | tw32(cpu_base + CPU_STATE, 0xffffffff); | 3838 | err = tg3_pause_cpu_and_set_pc(tp, cpu_base, |
| 3652 | tw32_f(cpu_base + CPU_PC, info.fw_base); | 3839 | be32_to_cpu(fw_hdr->base_addr)); |
| 3653 | 3840 | if (err) { | |
| 3654 | for (i = 0; i < 5; i++) { | ||
| 3655 | if (tr32(cpu_base + CPU_PC) == info.fw_base) | ||
| 3656 | break; | ||
| 3657 | tw32(cpu_base + CPU_STATE, 0xffffffff); | ||
| 3658 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | ||
| 3659 | tw32_f(cpu_base + CPU_PC, info.fw_base); | ||
| 3660 | udelay(1000); | ||
| 3661 | } | ||
| 3662 | if (i >= 5) { | ||
| 3663 | netdev_err(tp->dev, | 3841 | netdev_err(tp->dev, |
| 3664 | "%s fails to set CPU PC, is %08x should be %08x\n", | 3842 | "%s fails to set CPU PC, is %08x should be %08x\n", |
| 3665 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); | 3843 | __func__, tr32(cpu_base + CPU_PC), |
| 3844 | be32_to_cpu(fw_hdr->base_addr)); | ||
| 3666 | return -ENODEV; | 3845 | return -ENODEV; |
| 3667 | } | 3846 | } |
| 3668 | tw32(cpu_base + CPU_STATE, 0xffffffff); | 3847 | |
| 3669 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | 3848 | tg3_resume_cpu(tp, cpu_base); |
| 3670 | return 0; | 3849 | return 0; |
| 3671 | } | 3850 | } |
| 3672 | 3851 | ||
| 3673 | 3852 | ||
| 3674 | /* tp->lock is held. */ | 3853 | /* tp->lock is held. */ |
| 3675 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | 3854 | static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1) |
| 3676 | { | 3855 | { |
| 3677 | u32 addr_high, addr_low; | 3856 | u32 addr_high, addr_low; |
| 3678 | int i; | 3857 | int i; |
| @@ -3735,7 +3914,7 @@ static int tg3_power_up(struct tg3 *tp) · 56 unmodified lines | |||
| 3735 | return err; | 3914 | return err; |
| 3736 | } | 3915 | } |
| 3737 | 3916 | ||
| 3738 | static int tg3_setup_phy(struct tg3 *, int); | 3917 | static int tg3_setup_phy(struct tg3 *, bool); |
| 3739 | 3918 | ||
| 3740 | static int tg3_power_down_prepare(struct tg3 *tp) | 3919 | static int tg3_power_down_prepare(struct tg3 *tp) |
| 3741 | { | 3920 | { |
| @@ -3807,7 +3986,7 @@ static int tg3_power_down_prepare(struct tg3 *tp) · 65 unmodified lines | |||
| 3807 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; | 3986 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
| 3808 | 3987 | ||
| 3809 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | 3988 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
| 3810 | tg3_setup_phy(tp, 0); | 3989 | tg3_setup_phy(tp, false); |
| 3811 | } | 3990 | } |
| 3812 | 3991 | ||
| 3813 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { | 3992 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
| @@ -3848,7 +4027,13 @@ static int tg3_power_down_prepare(struct tg3 *tp) · 34 unmodified lines | |||
| 3848 | 4027 | ||
| 3849 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) | 4028 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
| 3850 | mac_mode = MAC_MODE_PORT_MODE_GMII; | 4029 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
| 3851 | else | 4030 | else if (tp->phy_flags & |
| 4031 | TG3_PHYFLG_KEEP_LINK_ON_PWRDN) { | ||
| 4032 | if (tp->link_config.active_speed == SPEED_1000) | ||
| 4033 | mac_mode = MAC_MODE_PORT_MODE_GMII; | ||
| 4034 | else | ||
| 4035 | mac_mode = MAC_MODE_PORT_MODE_MII; | ||
| 4036 | } else | ||
| 3852 | mac_mode = MAC_MODE_PORT_MODE_MII; | 4037 | mac_mode = MAC_MODE_PORT_MODE_MII; |
| 3853 | 4038 | ||
| 3854 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; | 4039 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
| @@ -4102,12 +4287,16 @@ static void tg3_phy_copper_begin(struct tg3 *tp) · 247 unmodified lines | |||
| 4102 | (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { | 4287 | (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
| 4103 | u32 adv, fc; | 4288 | u32 adv, fc; |
| 4104 | 4289 | ||
| 4105 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { | 4290 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && |
| 4291 | !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { | ||
| 4106 | adv = ADVERTISED_10baseT_Half | | 4292 | adv = ADVERTISED_10baseT_Half | |
| 4107 | ADVERTISED_10baseT_Full; | 4293 | ADVERTISED_10baseT_Full; |
| 4108 | if (tg3_flag(tp, WOL_SPEED_100MB)) | 4294 | if (tg3_flag(tp, WOL_SPEED_100MB)) |
| 4109 | adv |= ADVERTISED_100baseT_Half | | 4295 | adv |= ADVERTISED_100baseT_Half | |
| 4110 | ADVERTISED_100baseT_Full; | 4296 | ADVERTISED_100baseT_Full; |
| 4297 | if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) | ||
| 4298 | adv |= ADVERTISED_1000baseT_Half | | ||
| 4299 | ADVERTISED_1000baseT_Full; | ||
| 4111 | 4300 | ||
| 4112 | fc = FLOW_CTRL_TX | FLOW_CTRL_RX; | 4301 | fc = FLOW_CTRL_TX | FLOW_CTRL_RX; |
| 4113 | } else { | 4302 | } else { |
| @@ -4121,6 +4310,15 @@ static void tg3_phy_copper_begin(struct tg3 *tp) · 7 unmodified lines | |||
| 4121 | 4310 | ||
| 4122 | tg3_phy_autoneg_cfg(tp, adv, fc); | 4311 | tg3_phy_autoneg_cfg(tp, adv, fc); |
| 4123 | 4312 | ||
| 4313 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && | ||
| 4314 | (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { | ||
| 4315 | /* Normally during power down we want to autonegotiate | ||
| 4316 | * the lowest possible speed for WOL. However, to avoid | ||
| 4317 | * link flap, we leave it untouched. | ||
| 4318 | */ | ||
| 4319 | return; | ||
| 4320 | } | ||
| 4321 | |||
| 4124 | tg3_writephy(tp, MII_BMCR, | 4322 | tg3_writephy(tp, MII_BMCR, |
| 4125 | BMCR_ANENABLE | BMCR_ANRESTART); | 4323 | BMCR_ANENABLE | BMCR_ANRESTART); |
| 4126 | } else { | 4324 | } else { |
| @@ -4177,6 +4375,103 @@ static void tg3_phy_copper_begin(struct tg3 *tp) · 50 unmodified lines | |||
| 4177 | } | 4375 | } |
| 4178 | } | 4376 | } |
| 4179 | 4377 | ||
| 4378 | static int tg3_phy_pull_config(struct tg3 *tp) | ||
| 4379 | { | ||
| 4380 | int err; | ||
| 4381 | u32 val; | ||
| 4382 | |||
| 4383 | err = tg3_readphy(tp, MII_BMCR, &val); | ||
| 4384 | if (err) | ||
| 4385 | goto done; | ||
| 4386 | |||
| 4387 | if (!(val & BMCR_ANENABLE)) { | ||
| 4388 | tp->link_config.autoneg = AUTONEG_DISABLE; | ||
| 4389 | tp->link_config.advertising = 0; | ||
| 4390 | tg3_flag_clear(tp, PAUSE_AUTONEG); | ||
| 4391 | |||
| 4392 | err = -EIO; | ||
| 4393 | |||
| 4394 | switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) { | ||
| 4395 | case 0: | ||
| 4396 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | ||
| 4397 | goto done; | ||
| 4398 | |||
| 4399 | tp->link_config.speed = SPEED_10; | ||
| 4400 | break; | ||
| 4401 | case BMCR_SPEED100: | ||
| 4402 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) | ||
| 4403 | goto done; | ||
| 4404 | |||
| 4405 | tp->link_config.speed = SPEED_100; | ||
| 4406 | break; | ||
| 4407 | case BMCR_SPEED1000: | ||
| 4408 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { | ||
| 4409 | tp->link_config.speed = SPEED_1000; | ||
| 4410 | break; | ||
| 4411 | } | ||
| 4412 | /* Fall through */ | ||
| 4413 | default: | ||
| 4414 | goto done; | ||
| 4415 | } | ||
| 4416 | |||
| 4417 | if (val & BMCR_FULLDPLX) | ||
| 4418 | tp->link_config.duplex = DUPLEX_FULL; | ||
| 4419 | else | ||
| 4420 | tp->link_config.duplex = DUPLEX_HALF; | ||
| 4421 | |||
| 4422 | tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; | ||
| 4423 | |||
| 4424 | err = 0; | ||
| 4425 | goto done; | ||
| 4426 | } | ||
| 4427 | |||
| 4428 | tp->link_config.autoneg = AUTONEG_ENABLE; | ||
| 4429 | tp->link_config.advertising = ADVERTISED_Autoneg; | ||
| 4430 | tg3_flag_set(tp, PAUSE_AUTONEG); | ||
| 4431 | |||
| 4432 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { | ||
| 4433 | u32 adv; | ||
| 4434 | |||
| 4435 | err = tg3_readphy(tp, MII_ADVERTISE, &val); | ||
| 4436 | if (err) | ||
| 4437 | goto done; | ||
| 4438 | |||
| 4439 | adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL); | ||
| 4440 | tp->link_config.advertising |= adv | ADVERTISED_TP; | ||
| 4441 | |||
| 4442 | tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); | ||
| 4443 | } else { | ||
| 4444 | tp->link_config.advertising |= ADVERTISED_FIBRE; | ||
| 4445 | } | ||
| 4446 | |||
| 4447 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { | ||
| 4448 | u32 adv; | ||
| 4449 | |||
| 4450 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { | ||
| 4451 | err = tg3_readphy(tp, MII_CTRL1000, &val); | ||
| 4452 | if (err) | ||
| 4453 | goto done; | ||
| 4454 | |||
| 4455 | adv = mii_ctrl1000_to_ethtool_adv_t(val); | ||
| 4456 | } else { | ||
| 4457 | err = tg3_readphy(tp, MII_ADVERTISE, &val); | ||
| 4458 | if (err) | ||
| 4459 | goto done; | ||
| 4460 | |||
| 4461 | adv = tg3_decode_flowctrl_1000X(val); | ||
| 4462 | tp->link_config.flowctrl = adv; | ||
| 4463 | |||
| 4464 | val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL); | ||
| 4465 | adv = mii_adv_to_ethtool_adv_x(val); | ||
| 4466 | } | ||
| 4467 | |||
| 4468 | tp->link_config.advertising |= adv; | ||
| 4469 | } | ||
| 4470 | |||
| 4471 | done: | ||
| 4472 | return err; | ||
| 4473 | } | ||
| 4474 | |||
| 4180 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | 4475 | static int tg3_init_5401phy_dsp(struct tg3 *tp) |
| 4181 | { | 4476 | { |
| 4182 | int err; | 4477 | int err; |
| @@ -4196,6 +4491,32 @@ static int tg3_init_5401phy_dsp(struct tg3 *tp) · 13 unmodified lines | |||
| 4196 | return err; | 4491 | return err; |
| 4197 | } | 4492 | } |
| 4198 | 4493 | ||
| 4494 | static bool tg3_phy_eee_config_ok(struct tg3 *tp) | ||
| 4495 | { | ||
| 4496 | u32 val; | ||
| 4497 | u32 tgtadv = 0; | ||
| 4498 | u32 advertising = tp->link_config.advertising; | ||
| 4499 | |||
| 4500 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) | ||
| 4501 | return true; | ||
| 4502 | |||
| 4503 | if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val)) | ||
| 4504 | return false; | ||
| 4505 | |||
| 4506 | val &= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T); | ||
| 4507 | |||
| 4508 | |||
| 4509 | if (advertising & ADVERTISED_100baseT_Full) | ||
| 4510 | tgtadv |= MDIO_AN_EEE_ADV_100TX; | ||
| 4511 | if (advertising & ADVERTISED_1000baseT_Full) | ||
| 4512 | tgtadv |= MDIO_AN_EEE_ADV_1000T; | ||
| 4513 | |||
| 4514 | if (val != tgtadv) | ||
| 4515 | return false; | ||
| 4516 | |||
| 4517 | return true; | ||
| 4518 | } | ||
| 4519 | |||
| 4199 | static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) | 4520 | static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) |
| 4200 | { | 4521 | { |
| 4201 | u32 advmsk, tgtadv, advertising; | 4522 | u32 advmsk, tgtadv, advertising; |
| @@ -4262,7 +4583,7 @@ static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) · 60 unmodified lines | |||
| 4262 | return true; | 4583 | return true; |
| 4263 | } | 4584 | } |
| 4264 | 4585 | ||
| 4265 | static bool tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up) | 4586 | static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up) |
| 4266 | { | 4587 | { |
| 4267 | if (curr_link_up != tp->link_up) { | 4588 | if (curr_link_up != tp->link_up) { |
| 4268 | if (curr_link_up) { | 4589 | if (curr_link_up) { |
| @@ -4280,23 +4601,28 @@ static bool tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up) · 11 unmodified lines | |||
| 4280 | return false; | 4601 | return false; |
| 4281 | } | 4602 | } |
| 4282 | 4603 | ||
| 4283 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | 4604 | static void tg3_clear_mac_status(struct tg3 *tp) |
| 4284 | { | 4605 | { |
| 4285 | int current_link_up; | 4606 | tw32(MAC_EVENT, 0); |
| 4607 | |||
| 4608 | tw32_f(MAC_STATUS, | ||
| 4609 | MAC_STATUS_SYNC_CHANGED | | ||
| 4610 | MAC_STATUS_CFG_CHANGED | | ||
| 4611 | MAC_STATUS_MI_COMPLETION | | ||
| 4612 | MAC_STATUS_LNKSTATE_CHANGED); | ||
| 4613 | udelay(40); | ||
| 4614 | } | ||
| 4615 | |||
| 4616 | static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset) | ||
| 4617 | { | ||
| 4618 | bool current_link_up; | ||
| 4286 | u32 bmsr, val; | 4619 | u32 bmsr, val; |
| 4287 | u32 lcl_adv, rmt_adv; | 4620 | u32 lcl_adv, rmt_adv; |
| 4288 | u16 current_speed; | 4621 | u16 current_speed; |
| 4289 | u8 current_duplex; | 4622 | u8 current_duplex; |
| 4290 | int i, err; | 4623 | int i, err; |
| 4291 | 4624 | ||
| 4292 | tw32(MAC_EVENT, 0); | 4625 | tg3_clear_mac_status(tp); |
| 4293 | |||
| 4294 | tw32_f(MAC_STATUS, | ||
| 4295 | (MAC_STATUS_SYNC_CHANGED | | ||
| 4296 | MAC_STATUS_CFG_CHANGED | | ||
| 4297 | MAC_STATUS_MI_COMPLETION | | ||
| 4298 | MAC_STATUS_LNKSTATE_CHANGED)); | ||
| 4299 | udelay(40); | ||
| 4300 | 4626 | ||
| 4301 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | 4627 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
| 4302 | tw32_f(MAC_MI_MODE, | 4628 | tw32_f(MAC_MI_MODE, |
| @@ -4316,7 +4642,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) · 13 unmodified lines | |||
| 4316 | tg3_readphy(tp, MII_BMSR, &bmsr); | 4642 | tg3_readphy(tp, MII_BMSR, &bmsr); |
| 4317 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | 4643 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && |
| 4318 | !(bmsr & BMSR_LSTATUS)) | 4644 | !(bmsr & BMSR_LSTATUS)) |
| 4319 | force_reset = 1; | 4645 | force_reset = true; |
| 4320 | } | 4646 | } |
| 4321 | if (force_reset) | 4647 | if (force_reset) |
| 4322 | tg3_phy_reset(tp); | 4648 | tg3_phy_reset(tp); |
| @@ -4380,7 +4706,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) · 57 unmodified lines | |||
| 4380 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | 4706 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); |
| 4381 | } | 4707 | } |
| 4382 | 4708 | ||
| 4383 | current_link_up = 0; | 4709 | current_link_up = false; |
| 4384 | current_speed = SPEED_UNKNOWN; | 4710 | current_speed = SPEED_UNKNOWN; |
| 4385 | current_duplex = DUPLEX_UNKNOWN; | 4711 | current_duplex = DUPLEX_UNKNOWN; |
| 4386 | tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; | 4712 | tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; |
| @@ -4439,21 +4765,31 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) · 52 unmodified lines | |||
| 4439 | tp->link_config.active_duplex = current_duplex; | 4765 | tp->link_config.active_duplex = current_duplex; |
| 4440 | 4766 | ||
| 4441 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | 4767 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { |
| 4768 | bool eee_config_ok = tg3_phy_eee_config_ok(tp); | ||
| 4769 | |||
| 4442 | if ((bmcr & BMCR_ANENABLE) && | 4770 | if ((bmcr & BMCR_ANENABLE) && |
| 4771 | eee_config_ok && | ||
| 4443 | tg3_phy_copper_an_config_ok(tp, &lcl_adv) && | 4772 | tg3_phy_copper_an_config_ok(tp, &lcl_adv) && |
| 4444 | tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) | 4773 | tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) |
| 4445 | current_link_up = 1; | 4774 | current_link_up = true; |
| 4775 | |||
| 4776 | /* EEE settings changes take effect only after a phy | ||
| 4777 | * reset. If we have skipped a reset due to Link Flap | ||
| 4778 | * Avoidance being enabled, do it now. | ||
| 4779 | */ | ||
| 4780 | if (!eee_config_ok && | ||
| 4781 | (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && | ||
| 4782 | !force_reset) | ||
| 4783 | tg3_phy_reset(tp); | ||
| 4446 | } else { | 4784 | } else { |
| 4447 | if (!(bmcr & BMCR_ANENABLE) && | 4785 | if (!(bmcr & BMCR_ANENABLE) && |
| 4448 | tp->link_config.speed == current_speed && | 4786 | tp->link_config.speed == current_speed && |
| 4449 | tp->link_config.duplex == current_duplex && | 4787 | tp->link_config.duplex == current_duplex) { |
| 4450 | tp->link_config.flowctrl == | 4788 | current_link_up = true; |
| 4451 | tp->link_config.active_flowctrl) { | ||
| 4452 | current_link_up = 1; | ||
| 4453 | } | 4789 | } |
| 4454 | } | 4790 | } |
| 4455 | 4791 | ||
| 4456 | if (current_link_up == 1 && | 4792 | if (current_link_up && |
| 4457 | tp->link_config.active_duplex == DUPLEX_FULL) { | 4793 | tp->link_config.active_duplex == DUPLEX_FULL) { |
| 4458 | u32 reg, bit; | 4794 | u32 reg, bit; |
| 4459 | 4795 | ||
| @@ -4473,11 +4809,11 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) · 13 unmodified lines | |||
| 4473 | } | 4809 | } |
| 4474 | 4810 | ||
| 4475 | relink: | 4811 | relink: |
| 4476 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { | 4812 | if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
| 4477 | tg3_phy_copper_begin(tp); | 4813 | tg3_phy_copper_begin(tp); |
| 4478 | 4814 | ||
| 4479 | if (tg3_flag(tp, ROBOSWITCH)) { | 4815 | if (tg3_flag(tp, ROBOSWITCH)) { |
| 4480 | current_link_up = 1; | 4816 | current_link_up = true; |
| 4481 | /* FIXME: when BCM5325 switch is used use 100 MBit/s */ | 4817 | /* FIXME: when BCM5325 switch is used use 100 MBit/s */ |
| 4482 | current_speed = SPEED_1000; | 4818 | current_speed = SPEED_1000; |
| 4483 | current_duplex = DUPLEX_FULL; | 4819 | current_duplex = DUPLEX_FULL; |
| @@ -4488,11 +4824,11 @@ relink: · 4 unmodified lines | |||
| 4488 | tg3_readphy(tp, MII_BMSR, &bmsr); | 4824 | tg3_readphy(tp, MII_BMSR, &bmsr); |
| 4489 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || | 4825 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
| 4490 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) | 4826 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) |
| 4491 | current_link_up = 1; | 4827 | current_link_up = true; |
| 4492 | } | 4828 | } |
| 4493 | 4829 | ||
| 4494 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | 4830 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; |
| 4495 | if (current_link_up == 1) { | 4831 | if (current_link_up) { |
| 4496 | if (tp->link_config.active_speed == SPEED_100 || | 4832 | if (tp->link_config.active_speed == SPEED_100 || |
| 4497 | tp->link_config.active_speed == SPEED_10) | 4833 | tp->link_config.active_speed == SPEED_10) |
| 4498 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | 4834 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
| @@ -4528,7 +4864,7 @@ relink: · 29 unmodified lines | |||
| 4528 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | 4864 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; |
| 4529 | 4865 | ||
| 4530 | if (tg3_asic_rev(tp) == ASIC_REV_5700) { | 4866 | if (tg3_asic_rev(tp) == ASIC_REV_5700) { |
| 4531 | if (current_link_up == 1 && | 4867 | if (current_link_up && |
| 4532 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | 4868 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) |
| 4533 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | 4869 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
| 4534 | else | 4870 | else |
| @@ -4559,7 +4895,7 @@ relink: · 24 unmodified lines | |||
| 4559 | udelay(40); | 4895 | udelay(40); |
| 4560 | 4896 | ||
| 4561 | if (tg3_asic_rev(tp) == ASIC_REV_5700 && | 4897 | if (tg3_asic_rev(tp) == ASIC_REV_5700 && |
| 4562 | current_link_up == 1 && | 4898 | current_link_up && |
| 4563 | tp->link_config.active_speed == SPEED_1000 && | 4899 | tp->link_config.active_speed == SPEED_1000 && |
| 4564 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { | 4900 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
| 4565 | udelay(120); | 4901 | udelay(120); |
| @@ -4999,19 +5335,19 @@ static void tg3_init_bcm8002(struct tg3 *tp) · 433 unmodified lines | |||
| 4999 | tg3_writephy(tp, 0x10, 0x8011); | 5335 | tg3_writephy(tp, 0x10, 0x8011); |
| 5000 | } | 5336 | } |
| 5001 | 5337 | ||
| 5002 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | 5338 | static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) |
| 5003 | { | 5339 | { |
| 5004 | u16 flowctrl; | 5340 | u16 flowctrl; |
| 5341 | bool current_link_up; | ||
| 5005 | u32 sg_dig_ctrl, sg_dig_status; | 5342 | u32 sg_dig_ctrl, sg_dig_status; |
| 5006 | u32 serdes_cfg, expected_sg_dig_ctrl; | 5343 | u32 serdes_cfg, expected_sg_dig_ctrl; |
| 5007 | int workaround, port_a; | 5344 | int workaround, port_a; |
| 5008 | int current_link_up; | ||
| 5009 | 5345 | ||
| 5010 | serdes_cfg = 0; | 5346 | serdes_cfg = 0; |
| 5011 | expected_sg_dig_ctrl = 0; | 5347 | expected_sg_dig_ctrl = 0; |
| 5012 | workaround = 0; | 5348 | workaround = 0; |
| 5013 | port_a = 1; | 5349 | port_a = 1; |
| 5014 | current_link_up = 0; | 5350 | current_link_up = false; |
| 5015 | 5351 | ||
| 5016 | if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && | 5352 | if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && |
| 5017 | tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { | 5353 | tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { |
| @@ -5042,7 +5378,7 @@ static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) · 24 unmodified lines | |||
| 5042 | } | 5378 | } |
| 5043 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | 5379 | if (mac_status & MAC_STATUS_PCS_SYNCED) { |
| 5044 | tg3_setup_flow_control(tp, 0, 0); | 5380 | tg3_setup_flow_control(tp, 0, 0); |
| 5045 | current_link_up = 1; | 5381 | current_link_up = true; |
| 5046 | } | 5382 | } |
| 5047 | goto out; | 5383 | goto out; |
| 5048 | } | 5384 | } |
| @@ -5063,7 +5399,7 @@ static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) · 14 unmodified lines | |||
| 5063 | MAC_STATUS_RCVD_CFG)) == | 5399 | MAC_STATUS_RCVD_CFG)) == |
| 5064 | MAC_STATUS_PCS_SYNCED)) { | 5400 | MAC_STATUS_PCS_SYNCED)) { |
| 5065 | tp->serdes_counter--; | 5401 | tp->serdes_counter--; |
| 5066 | current_link_up = 1; | 5402 | current_link_up = true; |
| 5067 | goto out; | 5403 | goto out; |
| 5068 | } | 5404 | } |
| 5069 | restart_autoneg: | 5405 | restart_autoneg: |
| @@ -5098,7 +5434,7 @@ restart_autoneg: · 28 unmodified lines | |||
| 5098 | mii_adv_to_ethtool_adv_x(remote_adv); | 5434 | mii_adv_to_ethtool_adv_x(remote_adv); |
| 5099 | 5435 | ||
| 5100 | tg3_setup_flow_control(tp, local_adv, remote_adv); | 5436 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
| 5101 | current_link_up = 1; | 5437 | current_link_up = true; |
| 5102 | tp->serdes_counter = 0; | 5438 | tp->serdes_counter = 0; |
| 5103 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; | 5439 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
| 5104 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { | 5440 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
| @@ -5126,7 +5462,7 @@ restart_autoneg: · 21 unmodified lines | |||
| 5126 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | 5462 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && |
| 5127 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | 5463 | !(mac_status & MAC_STATUS_RCVD_CFG)) { |
| 5128 | tg3_setup_flow_control(tp, 0, 0); | 5464 | tg3_setup_flow_control(tp, 0, 0); |
| 5129 | current_link_up = 1; | 5465 | current_link_up = true; |
| 5130 | tp->phy_flags |= | 5466 | tp->phy_flags |= |
| 5131 | TG3_PHYFLG_PARALLEL_DETECT; | 5467 | TG3_PHYFLG_PARALLEL_DETECT; |
| 5132 | tp->serdes_counter = | 5468 | tp->serdes_counter = |
| @@ -5144,9 +5480,9 @@ out: · 11 unmodified lines | |||
| 5144 | return current_link_up; | 5480 | return current_link_up; |
| 5145 | } | 5481 | } |
| 5146 | 5482 | ||
| 5147 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | 5483 | static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) |
| 5148 | { | 5484 | { |
| 5149 | int current_link_up = 0; | 5485 | bool current_link_up = false; |
| 5150 | 5486 | ||
| 5151 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) | 5487 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
| 5152 | goto out; | 5488 | goto out; |
| @@ -5173,7 +5509,7 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) · 20 unmodified lines | |||
| 5173 | 5509 | ||
| 5174 | tg3_setup_flow_control(tp, local_adv, remote_adv); | 5510 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
| 5175 | 5511 | ||
| 5176 | current_link_up = 1; | 5512 | current_link_up = true; |
| 5177 | } | 5513 | } |
| 5178 | for (i = 0; i < 30; i++) { | 5514 | for (i = 0; i < 30; i++) { |
| 5179 | udelay(20); | 5515 | udelay(20); |
| @@ -5188,15 +5524,15 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) · 8 unmodified lines | |||
| 5188 | } | 5524 | } |
| 5189 | 5525 | ||
| 5190 | mac_status = tr32(MAC_STATUS); | 5526 | mac_status = tr32(MAC_STATUS); |
| 5191 | if (current_link_up == 0 && | 5527 | if (!current_link_up && |
| 5192 | (mac_status & MAC_STATUS_PCS_SYNCED) && | 5528 | (mac_status & MAC_STATUS_PCS_SYNCED) && |
| 5193 | !(mac_status & MAC_STATUS_RCVD_CFG)) | 5529 | !(mac_status & MAC_STATUS_RCVD_CFG)) |
| 5194 | current_link_up = 1; | 5530 | current_link_up = true; |
| 5195 | } else { | 5531 | } else { |
| 5196 | tg3_setup_flow_control(tp, 0, 0); | 5532 | tg3_setup_flow_control(tp, 0, 0); |
| 5197 | 5533 | ||
| 5198 | /* Forcing 1000FD link up. */ | 5534 | /* Forcing 1000FD link up. */ |
| 5199 | current_link_up = 1; | 5535 | current_link_up = true; |
| 5200 | 5536 | ||
| 5201 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | 5537 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); |
| 5202 | udelay(40); | 5538 | udelay(40); |
| @@ -5209,13 +5545,13 @@ out: · 6 unmodified lines | |||
| 5209 | return current_link_up; | 5545 | return current_link_up; |
| 5210 | } | 5546 | } |
| 5211 | 5547 | ||
| 5212 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | 5548 | static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset) |
| 5213 | { | 5549 | { |
| 5214 | u32 orig_pause_cfg; | 5550 | u32 orig_pause_cfg; |
| 5215 | u16 orig_active_speed; | 5551 | u16 orig_active_speed; |
| 5216 | u8 orig_active_duplex; | 5552 | u8 orig_active_duplex; |
| 5217 | u32 mac_status; | 5553 | u32 mac_status; |
| 5218 | int current_link_up; | 5554 | bool current_link_up; |
| 5219 | int i; | 5555 | int i; |
| 5220 | 5556 | ||
| 5221 | orig_pause_cfg = tp->link_config.active_flowctrl; | 5557 | orig_pause_cfg = tp->link_config.active_flowctrl; |
| @@ -5252,7 +5588,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) · 30 unmodified lines | |||
| 5252 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | 5588 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); |
| 5253 | udelay(40); | 5589 | udelay(40); |
| 5254 | 5590 | ||
| 5255 | current_link_up = 0; | 5591 | current_link_up = false; |
| 5256 | tp->link_config.rmt_adv = 0; | 5592 | tp->link_config.rmt_adv = 0; |
| 5257 | mac_status = tr32(MAC_STATUS); | 5593 | mac_status = tr32(MAC_STATUS); |
| 5258 | 5594 | ||
| @@ -5277,7 +5613,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) · 18 unmodified lines | |||
| 5277 | 5613 | ||
| 5278 | mac_status = tr32(MAC_STATUS); | 5614 | mac_status = tr32(MAC_STATUS); |
| 5279 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | 5615 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { |
| 5280 | current_link_up = 0; | 5616 | current_link_up = false; |
| 5281 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | 5617 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
| 5282 | tp->serdes_counter == 0) { | 5618 | tp->serdes_counter == 0) { |
| 5283 | tw32_f(MAC_MODE, (tp->mac_mode | | 5619 | tw32_f(MAC_MODE, (tp->mac_mode | |
| @@ -5287,7 +5623,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) · 3 unmodified lines | |||
| 5287 | } | 5623 | } |
| 5288 | } | 5624 | } |
| 5289 | 5625 | ||
| 5290 | if (current_link_up == 1) { | 5626 | if (current_link_up) { |
| 5291 | tp->link_config.active_speed = SPEED_1000; | 5627 | tp->link_config.active_speed = SPEED_1000; |
| 5292 | tp->link_config.active_duplex = DUPLEX_FULL; | 5628 | tp->link_config.active_duplex = DUPLEX_FULL; |
| 5293 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | 5629 | tw32(MAC_LED_CTRL, (tp->led_ctrl | |
| @@ -5312,33 +5648,63 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) · 18 unmodified lines | |||
| 5312 | return 0; | 5648 | return 0; |
| 5313 | } | 5649 | } |
| 5314 | 5650 | ||
| 5315 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) | 5651 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) |
| 5316 | { | 5652 | { |
| 5317 | int current_link_up, err = 0; | 5653 | int err = 0; |
| 5318 | u32 bmsr, bmcr; | 5654 | u32 bmsr, bmcr; |
| 5319 | u16 current_speed; | 5655 | u16 current_speed = SPEED_UNKNOWN; |
| 5320 | u8 current_duplex; | 5656 | u8 current_duplex = DUPLEX_UNKNOWN; |
| 5321 | u32 local_adv, remote_adv; | 5657 | bool current_link_up = false; |
| 5658 | u32 local_adv, remote_adv, sgsr; | ||
| 5659 | |||
| 5660 | if ((tg3_asic_rev(tp) == ASIC_REV_5719 || | ||
| 5661 | tg3_asic_rev(tp) == ASIC_REV_5720) && | ||
| 5662 | !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) && | ||
| 5663 | (sgsr & SERDES_TG3_SGMII_MODE)) { | ||
| 5664 | |||
| 5665 | if (force_reset) | ||
| 5666 | tg3_phy_reset(tp); | ||
| 5667 | |||
| 5668 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | ||
| 5669 | |||
| 5670 | if (!(sgsr & SERDES_TG3_LINK_UP)) { | ||
| 5671 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | ||
| 5672 | } else { | ||
| 5673 | current_link_up = true; | ||
| 5674 | if (sgsr & SERDES_TG3_SPEED_1000) { | ||
| 5675 | current_speed = SPEED_1000; | ||
| 5676 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | ||
| 5677 | } else if (sgsr & SERDES_TG3_SPEED_100) { | ||
| 5678 | current_speed = SPEED_100; | ||
| 5679 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | ||
| 5680 | } else { | ||
| 5681 | current_speed = SPEED_10; | ||
| 5682 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | ||
| 5683 | } | ||
| 5684 | |||
| 5685 | if (sgsr & SERDES_TG3_FULL_DUPLEX) | ||
| 5686 | current_duplex = DUPLEX_FULL; | ||
| 5687 | else | ||
| 5688 | current_duplex = DUPLEX_HALF; | ||
| 5689 | } | ||
| 5690 | |||
| 5691 | tw32_f(MAC_MODE, tp->mac_mode); | ||
| 5692 | udelay(40); | ||
| 5693 | |||
| 5694 | tg3_clear_mac_status(tp); | ||
| 5695 | |||
| 5696 | goto fiber_setup_done; | ||
| 5697 | } | ||
| 5322 | 5698 | ||
| 5323 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | 5699 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
| 5324 | tw32_f(MAC_MODE, tp->mac_mode); | 5700 | tw32_f(MAC_MODE, tp->mac_mode); |
| 5325 | udelay(40); | 5701 | udelay(40); |
| 5326 | 5702 | ||
| 5327 | tw32(MAC_EVENT, 0); | 5703 | tg3_clear_mac_status(tp); |
| 5328 | |||
| 5329 | tw32_f(MAC_STATUS, | ||
| 5330 | (MAC_STATUS_SYNC_CHANGED | | ||
| 5331 | MAC_STATUS_CFG_CHANGED | | ||
| 5332 | MAC_STATUS_MI_COMPLETION | | ||
| 5333 | MAC_STATUS_LNKSTATE_CHANGED)); | ||
| 5334 | udelay(40); | ||
| 5335 | 5704 | ||
| 5336 | if (force_reset) | 5705 | if (force_reset) |
| 5337 | tg3_phy_reset(tp); | 5706 | tg3_phy_reset(tp); |
| 5338 | 5707 | ||
| 5339 | current_link_up = 0; | ||
| 5340 | current_speed = SPEED_UNKNOWN; | ||
| 5341 | current_duplex = DUPLEX_UNKNOWN; | ||
| 5342 | tp->link_config.rmt_adv = 0; | 5708 | tp->link_config.rmt_adv = 0; |
| 5343 | 5709 | ||
| 5344 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | 5710 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); |
| @@ -5424,7 +5790,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) · 79 unmodified lines | |||
| 5424 | 5790 | ||
| 5425 | if (bmsr & BMSR_LSTATUS) { | 5791 | if (bmsr & BMSR_LSTATUS) { |
| 5426 | current_speed = SPEED_1000; | 5792 | current_speed = SPEED_1000; |
| 5427 | current_link_up = 1; | 5793 | current_link_up = true; |
| 5428 | if (bmcr & BMCR_FULLDPLX) | 5794 | if (bmcr & BMCR_FULLDPLX) |
| 5429 | current_duplex = DUPLEX_FULL; | 5795 | current_duplex = DUPLEX_FULL; |
| 5430 | else | 5796 | else |
| @@ -5451,12 +5817,13 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) · 20 unmodified lines | |||
| 5451 | } else if (!tg3_flag(tp, 5780_CLASS)) { | 5817 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
| 5452 | /* Link is up via parallel detect */ | 5818 | /* Link is up via parallel detect */ |
| 5453 | } else { | 5819 | } else { |
| 5454 | current_link_up = 0; | 5820 | current_link_up = false; |
| 5455 | } | 5821 | } |
| 5456 | } | 5822 | } |
| 5457 | } | 5823 | } |
| 5458 | 5824 | ||
| 5459 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) | 5825 | fiber_setup_done: |
| 5826 | if (current_link_up && current_duplex == DUPLEX_FULL) | ||
| 5460 | tg3_setup_flow_control(tp, local_adv, remote_adv); | 5827 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
| 5461 | 5828 | ||
| 5462 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | 5829 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
| @@ -5535,7 +5902,7 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp) · 72 unmodified lines | |||
| 5535 | } | 5902 | } |
| 5536 | } | 5903 | } |
| 5537 | 5904 | ||
| 5538 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) | 5905 | static int tg3_setup_phy(struct tg3 *tp, bool force_reset) |
| 5539 | { | 5906 | { |
| 5540 | u32 val; | 5907 | u32 val; |
| 5541 | int err; | 5908 | int err; |
| @@ -5625,10 +5992,13 @@ static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info) · 83 unmodified lines | |||
| 5625 | 5992 | ||
| 5626 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | 5993 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | |
| 5627 | SOF_TIMESTAMPING_RX_SOFTWARE | | 5994 | SOF_TIMESTAMPING_RX_SOFTWARE | |
| 5628 | SOF_TIMESTAMPING_SOFTWARE | | 5995 | SOF_TIMESTAMPING_SOFTWARE; |
| 5629 | SOF_TIMESTAMPING_TX_HARDWARE | | 5996 | |
| 5630 | SOF_TIMESTAMPING_RX_HARDWARE | | 5997 | if (tg3_flag(tp, PTP_CAPABLE)) { |
| 5631 | SOF_TIMESTAMPING_RAW_HARDWARE; | 5998 | info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | |
| 5999 | SOF_TIMESTAMPING_RX_HARDWARE | | ||
| 6000 | SOF_TIMESTAMPING_RAW_HARDWARE; | ||
| 6001 | } | ||
| 5632 | 6002 | ||
| 5633 | if (tp->ptp_clock) | 6003 | if (tp->ptp_clock) |
| 5634 | info->phc_index = ptp_clock_index(tp->ptp_clock); | 6004 | info->phc_index = ptp_clock_index(tp->ptp_clock); |
| @@ -6348,7 +6718,7 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget) · 713 unmodified lines | |||
| 6348 | 6718 | ||
| 6349 | if (desc->type_flags & RXD_FLAG_VLAN && | 6719 | if (desc->type_flags & RXD_FLAG_VLAN && |
| 6350 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) | 6720 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
| 6351 | __vlan_hwaccel_put_tag(skb, | 6721 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), |
| 6352 | desc->err_vlan & RXD_VLAN_MASK); | 6722 | desc->err_vlan & RXD_VLAN_MASK); |
| 6353 | 6723 | ||
| 6354 | napi_gro_receive(&tnapi->napi, skb); | 6724 | napi_gro_receive(&tnapi->napi, skb); |
| @@ -6436,7 +6806,7 @@ static void tg3_poll_link(struct tg3 *tp) · 81 unmodified lines | |||
| 6436 | MAC_STATUS_LNKSTATE_CHANGED)); | 6806 | MAC_STATUS_LNKSTATE_CHANGED)); |
| 6437 | udelay(40); | 6807 | udelay(40); |
| 6438 | } else | 6808 | } else |
| 6439 | tg3_setup_phy(tp, 0); | 6809 | tg3_setup_phy(tp, false); |
| 6440 | spin_unlock(&tp->lock); | 6810 | spin_unlock(&tp->lock); |
| 6441 | } | 6811 | } |
| 6442 | } | 6812 | } |
| @@ -7533,7 +7903,7 @@ static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) · 1090 unmodified lines | |||
| 7533 | u32 val, bmcr, mac_mode, ptest = 0; | 7903 | u32 val, bmcr, mac_mode, ptest = 0; |
| 7534 | 7904 | ||
| 7535 | tg3_phy_toggle_apd(tp, false); | 7905 | tg3_phy_toggle_apd(tp, false); |
| 7536 | tg3_phy_toggle_automdix(tp, 0); | 7906 | tg3_phy_toggle_automdix(tp, false); |
| 7537 | 7907 | ||
| 7538 | if (extlpbk && tg3_phy_set_extloopbk(tp)) | 7908 | if (extlpbk && tg3_phy_set_extloopbk(tp)) |
| 7539 | return -EIO; | 7909 | return -EIO; |
| @@ -7641,7 +8011,7 @@ static void tg3_set_loopback(struct net_device *dev, netdev_features_t features) · 101 unmodified lines | |||
| 7641 | spin_lock_bh(&tp->lock); | 8011 | spin_lock_bh(&tp->lock); |
| 7642 | tg3_mac_loopback(tp, false); | 8012 | tg3_mac_loopback(tp, false); |
| 7643 | /* Force link status check */ | 8013 | /* Force link status check */ |
| 7644 | tg3_setup_phy(tp, 1); | 8014 | tg3_setup_phy(tp, true); |
| 7645 | spin_unlock_bh(&tp->lock); | 8015 | spin_unlock_bh(&tp->lock); |
| 7646 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); | 8016 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); |
| 7647 | } | 8017 | } |
| @@ -8039,11 +8409,9 @@ static int tg3_mem_rx_acquire(struct tg3 *tp) · 391 unmodified lines | |||
| 8039 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, | 8409 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
| 8040 | TG3_RX_RCB_RING_BYTES(tp), | 8410 | TG3_RX_RCB_RING_BYTES(tp), |
| 8041 | &tnapi->rx_rcb_mapping, | 8411 | &tnapi->rx_rcb_mapping, |
| 8042 | GFP_KERNEL); | 8412 | GFP_KERNEL | __GFP_ZERO); |
| 8043 | if (!tnapi->rx_rcb) | 8413 | if (!tnapi->rx_rcb) |
| 8044 | goto err_out; | 8414 | goto err_out; |
| 8045 | |||
| 8046 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | ||
| 8047 | } | 8415 | } |
| 8048 | 8416 | ||
| 8049 | return 0; | 8417 | return 0; |
| @@ -8093,12 +8461,10 @@ static int tg3_alloc_consistent(struct tg3 *tp) · 43 unmodified lines | |||
| 8093 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, | 8461 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
| 8094 | sizeof(struct tg3_hw_stats), | 8462 | sizeof(struct tg3_hw_stats), |
| 8095 | &tp->stats_mapping, | 8463 | &tp->stats_mapping, |
| 8096 | GFP_KERNEL); | 8464 | GFP_KERNEL | __GFP_ZERO); |
| 8097 | if (!tp->hw_stats) | 8465 | if (!tp->hw_stats) |
| 8098 | goto err_out; | 8466 | goto err_out; |
| 8099 | 8467 | ||
| 8100 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | ||
| 8101 | |||
| 8102 | for (i = 0; i < tp->irq_cnt; i++) { | 8468 | for (i = 0; i < tp->irq_cnt; i++) { |
| 8103 | struct tg3_napi *tnapi = &tp->napi[i]; | 8469 | struct tg3_napi *tnapi = &tp->napi[i]; |
| 8104 | struct tg3_hw_status *sblk; | 8470 | struct tg3_hw_status *sblk; |
| @@ -8106,11 +8472,10 @@ static int tg3_alloc_consistent(struct tg3 *tp) · 1 unmodified line | |||
| 8106 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, | 8472 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
| 8107 | TG3_HW_STATUS_SIZE, | 8473 | TG3_HW_STATUS_SIZE, |
| 8108 | &tnapi->status_mapping, | 8474 | &tnapi->status_mapping, |
| 8109 | GFP_KERNEL); | 8475 | GFP_KERNEL | __GFP_ZERO); |
| 8110 | if (!tnapi->hw_status) | 8476 | if (!tnapi->hw_status) |
| 8111 | goto err_out; | 8477 | goto err_out; |
| 8112 | 8478 | ||
| 8113 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | ||
| 8114 | sblk = tnapi->hw_status; | 8479 | sblk = tnapi->hw_status; |
| 8115 | 8480 | ||
| 8116 | if (tg3_flag(tp, ENABLE_RSS)) { | 8481 | if (tg3_flag(tp, ENABLE_RSS)) { |
| @@ -8157,7 +8522,7 @@ err_out: · 40 unmodified lines | |||
| 8157 | /* To stop a block, clear the enable bit and poll till it | 8522 | /* To stop a block, clear the enable bit and poll till it |
| 8158 | * clears. tp->lock is held. | 8523 | * clears. tp->lock is held. |
| 8159 | */ | 8524 | */ |
| 8160 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) | 8525 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) |
| 8161 | { | 8526 | { |
| 8162 | unsigned int i; | 8527 | unsigned int i; |
| 8163 | u32 val; | 8528 | u32 val; |
| @@ -8201,7 +8566,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int · 37 unmodified lines | |||
| 8201 | } | 8566 | } |
| 8202 | 8567 | ||
| 8203 | /* tp->lock is held. */ | 8568 | /* tp->lock is held. */ |
| 8204 | static int tg3_abort_hw(struct tg3 *tp, int silent) | 8569 | static int tg3_abort_hw(struct tg3 *tp, bool silent) |
| 8205 | { | 8570 | { |
| 8206 | int i, err; | 8571 | int i, err; |
| 8207 | 8572 | ||
| @@ -8561,6 +8926,9 @@ static int tg3_chip_reset(struct tg3 *tp) · 353 unmodified lines | |||
| 8561 | 8926 | ||
| 8562 | /* Reprobe ASF enable state. */ | 8927 | /* Reprobe ASF enable state. */ |
| 8563 | tg3_flag_clear(tp, ENABLE_ASF); | 8928 | tg3_flag_clear(tp, ENABLE_ASF); |
| 8929 | tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | | ||
| 8930 | TG3_PHYFLG_KEEP_LINK_ON_PWRDN); | ||
| 8931 | |||
| 8564 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); | 8932 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); |
| 8565 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | 8933 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
| 8566 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | 8934 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { |
| @@ -8572,6 +8940,12 @@ static int tg3_chip_reset(struct tg3 *tp) · 5 unmodified lines | |||
| 8572 | tp->last_event_jiffies = jiffies; | 8940 | tp->last_event_jiffies = jiffies; |
| 8573 | if (tg3_flag(tp, 5750_PLUS)) | 8941 | if (tg3_flag(tp, 5750_PLUS)) |
| 8574 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); | 8942 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); |
| 8943 | |||
| 8944 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg); | ||
| 8945 | if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK) | ||
| 8946 | tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; | ||
| 8947 | if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID) | ||
| 8948 | tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; | ||
| 8575 | } | 8949 | } |
| 8576 | } | 8950 | } |
| 8577 | 8951 | ||
| @@ -8582,7 +8956,7 @@ static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *); · 4 unmodified lines | |||
| 8582 | static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *); | 8956 | static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *); |
| 8583 | 8957 | ||
| 8584 | /* tp->lock is held. */ | 8958 | /* tp->lock is held. */ |
| 8585 | static int tg3_halt(struct tg3 *tp, int kind, int silent) | 8959 | static int tg3_halt(struct tg3 *tp, int kind, bool silent) |
| 8586 | { | 8960 | { |
| 8587 | int err; | 8961 | int err; |
| 8588 | 8962 | ||
| @@ -8593,7 +8967,7 @@ static int tg3_halt(struct tg3 *tp, int kind, int silent) · 4 unmodified lines | |||
| 8593 | tg3_abort_hw(tp, silent); | 8967 | tg3_abort_hw(tp, silent); |
| 8594 | err = tg3_chip_reset(tp); | 8968 | err = tg3_chip_reset(tp); |
| 8595 | 8969 | ||
| 8596 | __tg3_set_mac_addr(tp, 0); | 8970 | __tg3_set_mac_addr(tp, false); |
| 8597 | 8971 | ||
| 8598 | tg3_write_sig_legacy(tp, kind); | 8972 | tg3_write_sig_legacy(tp, kind); |
| 8599 | tg3_write_sig_post_reset(tp, kind); | 8973 | tg3_write_sig_post_reset(tp, kind); |
| @@ -8617,7 +8991,8 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p) · 17 unmodified lines | |||
| 8617 | { | 8991 | { |
| 8618 | struct tg3 *tp = netdev_priv(dev); | 8992 | struct tg3 *tp = netdev_priv(dev); |
| 8619 | struct sockaddr *addr = p; | 8993 | struct sockaddr *addr = p; |
| 8620 | int err = 0, skip_mac_1 = 0; | 8994 | int err = 0; |
| 8995 | bool skip_mac_1 = false; | ||
| 8621 | 8996 | ||
| 8622 | if (!is_valid_ether_addr(addr->sa_data)) | 8997 | if (!is_valid_ether_addr(addr->sa_data)) |
| 8623 | return -EADDRNOTAVAIL; | 8998 | return -EADDRNOTAVAIL; |
| @@ -8638,7 +9013,7 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p) · 14 unmodified lines | |||
| 8638 | /* Skip MAC addr 1 if ASF is using it. */ | 9013 | /* Skip MAC addr 1 if ASF is using it. */ |
| 8639 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | 9014 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && |
| 8640 | !(addr1_high == 0 && addr1_low == 0)) | 9015 | !(addr1_high == 0 && addr1_low == 0)) |
| 8641 | skip_mac_1 = 1; | 9016 | skip_mac_1 = true; |
| 8642 | } | 9017 | } |
| 8643 | spin_lock_bh(&tp->lock); | 9018 | spin_lock_bh(&tp->lock); |
| 8644 | __tg3_set_mac_addr(tp, skip_mac_1); | 9019 | __tg3_set_mac_addr(tp, skip_mac_1); |
| @@ -9057,7 +9432,7 @@ static void tg3_rss_write_indir_tbl(struct tg3 *tp) · 412 unmodified lines | |||
| 9057 | } | 9432 | } |
| 9058 | 9433 | ||
| 9059 | /* tp->lock is held. */ | 9434 | /* tp->lock is held. */ |
| 9060 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | 9435 | static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) |
| 9061 | { | 9436 | { |
| 9062 | u32 val, rdmac_mode; | 9437 | u32 val, rdmac_mode; |
| 9063 | int i, err, limit; | 9438 | int i, err, limit; |
| @@ -9106,6 +9481,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) · 42 unmodified lines | |||
| 9106 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); | 9481 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
| 9107 | } | 9482 | } |
| 9108 | 9483 | ||
| 9484 | if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && | ||
| 9485 | !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { | ||
| 9486 | tg3_phy_pull_config(tp); | ||
| 9487 | tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; | ||
| 9488 | } | ||
| 9489 | |||
| 9109 | if (reset_phy) | 9490 | if (reset_phy) |
| 9110 | tg3_phy_reset(tp); | 9491 | tg3_phy_reset(tp); |
| 9111 | 9492 | ||
| @@ -9444,7 +9825,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) · 332 unmodified lines | |||
| 9444 | tg3_rings_reset(tp); | 9825 | tg3_rings_reset(tp); |
| 9445 | 9826 | ||
| 9446 | /* Initialize MAC address and backoff seed. */ | 9827 | /* Initialize MAC address and backoff seed. */ |
| 9447 | __tg3_set_mac_addr(tp, 0); | 9828 | __tg3_set_mac_addr(tp, false); |
| 9448 | 9829 | ||
| 9449 | /* MTU + ethernet header + FCS + optional VLAN tag */ | 9830 | /* MTU + ethernet header + FCS + optional VLAN tag */ |
| 9450 | tw32(MAC_RX_MTU_SIZE, | 9831 | tw32(MAC_RX_MTU_SIZE, |
| @@ -9781,6 +10162,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) · 330 unmodified lines | |||
| 9781 | return err; | 10162 | return err; |
| 9782 | } | 10163 | } |
| 9783 | 10164 | ||
| 10165 | if (tg3_asic_rev(tp) == ASIC_REV_57766) { | ||
| 10166 | /* Ignore any errors for the firmware download. If download | ||
| 10167 | * fails, the device will operate with EEE disabled | ||
| 10168 | */ | ||
| 10169 | tg3_load_57766_firmware(tp); | ||
| 10170 | } | ||
| 10171 | |||
| 9784 | if (tg3_flag(tp, TSO_CAPABLE)) { | 10172 | if (tg3_flag(tp, TSO_CAPABLE)) { |
| 9785 | err = tg3_load_tso_firmware(tp); | 10173 | err = tg3_load_tso_firmware(tp); |
| 9786 | if (err) | 10174 | if (err) |
| @@ -9888,7 +10276,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) · 101 unmodified lines | |||
| 9888 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) | 10276 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
| 9889 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; | 10277 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; |
| 9890 | 10278 | ||
| 9891 | err = tg3_setup_phy(tp, 0); | 10279 | err = tg3_setup_phy(tp, false); |
| 9892 | if (err) | 10280 | if (err) |
| 9893 | return err; | 10281 | return err; |
| 9894 | 10282 | ||
| @@ -9968,7 +10356,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) · 73 unmodified lines | |||
| 9968 | /* Called at device open time to get the chip ready for | 10356 | /* Called at device open time to get the chip ready for |
| 9969 | * packet processing. Invoked with tp->lock held. | 10357 | * packet processing. Invoked with tp->lock held. |
| 9970 | */ | 10358 | */ |
| 9971 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) | 10359 | static int tg3_init_hw(struct tg3 *tp, bool reset_phy) |
| 9972 | { | 10360 | { |
| 9973 | tg3_switch_clocks(tp); | 10361 | tg3_switch_clocks(tp); |
| 9974 | 10362 | ||
| @@ -10229,7 +10617,7 @@ static void tg3_timer(unsigned long __opaque) · 254 unmodified lines | |||
| 10229 | phy_event = 1; | 10617 | phy_event = 1; |
| 10230 | 10618 | ||
| 10231 | if (phy_event) | 10619 | if (phy_event) |
| 10232 | tg3_setup_phy(tp, 0); | 10620 | tg3_setup_phy(tp, false); |
| 10233 | } else if (tg3_flag(tp, POLL_SERDES)) { | 10621 | } else if (tg3_flag(tp, POLL_SERDES)) { |
| 10234 | u32 mac_stat = tr32(MAC_STATUS); | 10622 | u32 mac_stat = tr32(MAC_STATUS); |
| 10235 | int need_setup = 0; | 10623 | int need_setup = 0; |
| @@ -10252,7 +10640,7 @@ static void tg3_timer(unsigned long __opaque) · 16 unmodified lines | |||
| 10252 | tw32_f(MAC_MODE, tp->mac_mode); | 10640 | tw32_f(MAC_MODE, tp->mac_mode); |
| 10253 | udelay(40); | 10641 | udelay(40); |
| 10254 | } | 10642 | } |
| 10255 | tg3_setup_phy(tp, 0); | 10643 | tg3_setup_phy(tp, false); |
| 10256 | } | 10644 | } |
| 10257 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && | 10645 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
| 10258 | tg3_flag(tp, 5780_CLASS)) { | 10646 | tg3_flag(tp, 5780_CLASS)) { |
| @@ -10338,7 +10726,7 @@ static void tg3_timer_stop(struct tg3 *tp) · 79 unmodified lines | |||
| 10338 | /* Restart hardware after configuration changes, self-test, etc. | 10726 | /* Restart hardware after configuration changes, self-test, etc. |
| 10339 | * Invoked with tp->lock held. | 10727 | * Invoked with tp->lock held. |
| 10340 | */ | 10728 | */ |
| 10341 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | 10729 | static int tg3_restart_hw(struct tg3 *tp, bool reset_phy) |
| 10342 | __releases(tp->lock) | 10730 | __releases(tp->lock) |
| 10343 | __acquires(tp->lock) | 10731 | __acquires(tp->lock) |
| 10344 | { | 10732 | { |
| @@ -10388,7 +10776,7 @@ static void tg3_reset_task(struct work_struct *work) · 43 unmodified lines | |||
| 10388 | } | 10776 | } |
| 10389 | 10777 | ||
| 10390 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | 10778 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
| 10391 | err = tg3_init_hw(tp, 1); | 10779 | err = tg3_init_hw(tp, true); |
| 10392 | if (err) | 10780 | if (err) |
| 10393 | goto out; | 10781 | goto out; |
| 10394 | 10782 | ||
| @@ -10558,7 +10946,7 @@ static int tg3_test_msi(struct tg3 *tp) · 163 unmodified lines | |||
| 10558 | tg3_full_lock(tp, 1); | 10946 | tg3_full_lock(tp, 1); |
| 10559 | 10947 | ||
| 10560 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | 10948 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
| 10561 | err = tg3_init_hw(tp, 1); | 10949 | err = tg3_init_hw(tp, true); |
| 10562 | 10950 | ||
| 10563 | tg3_full_unlock(tp); | 10951 | tg3_full_unlock(tp); |
| 10564 | 10952 | ||
| @@ -10570,7 +10958,7 @@ static int tg3_test_msi(struct tg3 *tp) · 5 unmodified lines | |||
| 10570 | 10958 | ||
| 10571 | static int tg3_request_firmware(struct tg3 *tp) | 10959 | static int tg3_request_firmware(struct tg3 *tp) |
| 10572 | { | 10960 | { |
| 10573 | const __be32 *fw_data; | 10961 | const struct tg3_firmware_hdr *fw_hdr; |
| 10574 | 10962 | ||
| 10575 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | 10963 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { |
| 10576 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", | 10964 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
| @@ -10578,15 +10966,15 @@ static int tg3_request_firmware(struct tg3 *tp) · 1 unmodified line | |||
| 10578 | return -ENOENT; | 10966 | return -ENOENT; |
| 10579 | } | 10967 | } |
| 10580 | 10968 | ||
| 10581 | fw_data = (void *)tp->fw->data; | 10969 | fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; |
| 10582 | 10970 | ||
| 10583 | /* Firmware blob starts with version numbers, followed by | 10971 | /* Firmware blob starts with version numbers, followed by |
| 10584 | * start address and _full_ length including BSS sections | 10972 | * start address and _full_ length including BSS sections |
| 10585 | * (which must be longer than the actual data, of course | 10973 | * (which must be longer than the actual data, of course |
| 10586 | */ | 10974 | */ |
| 10587 | 10975 | ||
| 10588 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | 10976 | tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ |
| 10589 | if (tp->fw_len < (tp->fw->size - 12)) { | 10977 | if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { |
| 10590 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", | 10978 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
| 10591 | tp->fw_len, tp->fw_needed); | 10979 | tp->fw_len, tp->fw_needed); |
| 10592 | release_firmware(tp->fw); | 10980 | release_firmware(tp->fw); |
| @@ -10885,7 +11273,15 @@ static int tg3_open(struct net_device *dev) · 292 unmodified lines | |||
| 10885 | 11273 | ||
| 10886 | if (tp->fw_needed) { | 11274 | if (tp->fw_needed) { |
| 10887 | err = tg3_request_firmware(tp); | 11275 | err = tg3_request_firmware(tp); |
| 10888 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { | 11276 | if (tg3_asic_rev(tp) == ASIC_REV_57766) { |
| 11277 | if (err) { | ||
| 11278 | netdev_warn(tp->dev, "EEE capability disabled\n"); | ||
| 11279 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; | ||
| 11280 | } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { | ||
| 11281 | netdev_warn(tp->dev, "EEE capability restored\n"); | ||
| 11282 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; | ||
| 11283 | } | ||
| 11284 | } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { | ||
| 10889 | if (err) | 11285 | if (err) |
| 10890 | return err; | 11286 | return err; |
| 10891 | } else if (err) { | 11287 | } else if (err) { |
| @@ -10910,7 +11306,9 @@ static int tg3_open(struct net_device *dev) · 18 unmodified lines | |||
| 10910 | 11306 | ||
| 10911 | tg3_full_unlock(tp); | 11307 | tg3_full_unlock(tp); |
| 10912 | 11308 | ||
| 10913 | err = tg3_start(tp, true, true, true); | 11309 | err = tg3_start(tp, |
| 11310 | !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), | ||
| 11311 | true, true); | ||
| 10914 | if (err) { | 11312 | if (err) { |
| 10915 | tg3_frob_aux_power(tp, false); | 11313 | tg3_frob_aux_power(tp, false); |
| 10916 | pci_set_power_state(tp->pdev, PCI_D3hot); | 11314 | pci_set_power_state(tp->pdev, PCI_D3hot); |
| @@ -11416,8 +11814,12 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) · 499 unmodified lines | |||
| 11416 | tp->link_config.duplex = cmd->duplex; | 11814 | tp->link_config.duplex = cmd->duplex; |
| 11417 | } | 11815 | } |
| 11418 | 11816 | ||
| 11817 | tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; | ||
| 11818 | |||
| 11819 | tg3_warn_mgmt_link_flap(tp); | ||
| 11820 | |||
| 11419 | if (netif_running(dev)) | 11821 | if (netif_running(dev)) |
| 11420 | tg3_setup_phy(tp, 1); | 11822 | tg3_setup_phy(tp, true); |
| 11421 | 11823 | ||
| 11422 | tg3_full_unlock(tp); | 11824 | tg3_full_unlock(tp); |
| 11423 | 11825 | ||
| @@ -11494,6 +11896,8 @@ static int tg3_nway_reset(struct net_device *dev) · 70 unmodified lines | |||
| 11494 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) | 11896 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
| 11495 | return -EINVAL; | 11897 | return -EINVAL; |
| 11496 | 11898 | ||
| 11899 | tg3_warn_mgmt_link_flap(tp); | ||
| 11900 | |||
| 11497 | if (tg3_flag(tp, USE_PHYLIB)) { | 11901 | if (tg3_flag(tp, USE_PHYLIB)) { |
| 11498 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) | 11902 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
| 11499 | return -EAGAIN; | 11903 | return -EAGAIN; |
| @@ -11571,7 +11975,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e · 71 unmodified lines | |||
| 11571 | 11975 | ||
| 11572 | if (netif_running(dev)) { | 11976 | if (netif_running(dev)) { |
| 11573 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | 11977 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
| 11574 | err = tg3_restart_hw(tp, 1); | 11978 | err = tg3_restart_hw(tp, false); |
| 11575 | if (!err) | 11979 | if (!err) |
| 11576 | tg3_netif_start(tp); | 11980 | tg3_netif_start(tp); |
| 11577 | } | 11981 | } |
| @@ -11606,6 +12010,9 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam · 28 unmodified lines | |||
| 11606 | struct tg3 *tp = netdev_priv(dev); | 12010 | struct tg3 *tp = netdev_priv(dev); |
| 11607 | int err = 0; | 12011 | int err = 0; |
| 11608 | 12012 | ||
| 12013 | if (tp->link_config.autoneg == AUTONEG_ENABLE) | ||
| 12014 | tg3_warn_mgmt_link_flap(tp); | ||
| 12015 | |||
| 11609 | if (tg3_flag(tp, USE_PHYLIB)) { | 12016 | if (tg3_flag(tp, USE_PHYLIB)) { |
| 11610 | u32 newadv; | 12017 | u32 newadv; |
| 11611 | struct phy_device *phydev; | 12018 | struct phy_device *phydev; |
| @@ -11692,7 +12099,7 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam · 80 unmodified lines | |||
| 11692 | 12099 | ||
| 11693 | if (netif_running(dev)) { | 12100 | if (netif_running(dev)) { |
| 11694 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | 12101 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
| 11695 | err = tg3_restart_hw(tp, 1); | 12102 | err = tg3_restart_hw(tp, false); |
| 11696 | if (!err) | 12103 | if (!err) |
| 11697 | tg3_netif_start(tp); | 12104 | tg3_netif_start(tp); |
| 11698 | } | 12105 | } |
| @@ -11700,6 +12107,8 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam · 1 unmodified line | |||
| 11700 | tg3_full_unlock(tp); | 12107 | tg3_full_unlock(tp); |
| 11701 | } | 12108 | } |
| 11702 | 12109 | ||
| 12110 | tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; | ||
| 12111 | |||
| 11703 | return err; | 12112 | return err; |
| 11704 | } | 12113 | } |
| 11705 | 12114 | ||
| @@ -12760,7 +13169,7 @@ static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) · 1054 unmodified lines | |||
| 12760 | goto done; | 13169 | goto done; |
| 12761 | } | 13170 | } |
| 12762 | 13171 | ||
| 12763 | err = tg3_reset_hw(tp, 1); | 13172 | err = tg3_reset_hw(tp, true); |
| 12764 | if (err) { | 13173 | if (err) { |
| 12765 | data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED; | 13174 | data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED; |
| 12766 | data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED; | 13175 | data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED; |
| @@ -12927,7 +13336,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, · 160 unmodified lines | |||
| 12927 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | 13336 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
| 12928 | if (netif_running(dev)) { | 13337 | if (netif_running(dev)) { |
| 12929 | tg3_flag_set(tp, INIT_COMPLETE); | 13338 | tg3_flag_set(tp, INIT_COMPLETE); |
| 12930 | err2 = tg3_restart_hw(tp, 1); | 13339 | err2 = tg3_restart_hw(tp, true); |
| 12931 | if (!err2) | 13340 | if (!err2) |
| 12932 | tg3_netif_start(tp); | 13341 | tg3_netif_start(tp); |
| 12933 | } | 13342 | } |
| @@ -13244,7 +13653,8 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, · 310 unmodified lines | |||
| 13244 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | 13653 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) |
| 13245 | { | 13654 | { |
| 13246 | struct tg3 *tp = netdev_priv(dev); | 13655 | struct tg3 *tp = netdev_priv(dev); |
| 13247 | int err, reset_phy = 0; | 13656 | int err; |
| 13657 | bool reset_phy = false; | ||
| 13248 | 13658 | ||
| 13249 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | 13659 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) |
| 13250 | return -EINVAL; | 13660 | return -EINVAL; |
| @@ -13271,7 +13681,7 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu) · 20 unmodified lines | |||
| 13271 | * breaks all requests to 256 bytes. | 13681 | * breaks all requests to 256 bytes. |
| 13272 | */ | 13682 | */ |
| 13273 | if (tg3_asic_rev(tp) == ASIC_REV_57766) | 13683 | if (tg3_asic_rev(tp) == ASIC_REV_57766) |
| 13274 | reset_phy = 1; | 13684 | reset_phy = true; |
| 13275 | 13685 | ||
| 13276 | err = tg3_restart_hw(tp, reset_phy); | 13686 | err = tg3_restart_hw(tp, reset_phy); |
| 13277 | 13687 | ||
| @@ -13837,6 +14247,12 @@ static void tg3_get_5720_nvram_info(struct tg3 *tp) · 559 unmodified lines | |||
| 13837 | case FLASH_5762_EEPROM_LD: | 14247 | case FLASH_5762_EEPROM_LD: |
| 13838 | nvmpinstrp = FLASH_5720_EEPROM_LD; | 14248 | nvmpinstrp = FLASH_5720_EEPROM_LD; |
| 13839 | break; | 14249 | break; |
| 14250 | case FLASH_5720VENDOR_M_ST_M45PE20: | ||
| 14251 | /* This pinstrap supports multiple sizes, so force it | ||
| 14252 | * to read the actual size from location 0xf0. | ||
| 14253 | */ | ||
| 14254 | nvmpinstrp = FLASH_5720VENDOR_ST_45USPT; | ||
| 14255 | break; | ||
| 13840 | } | 14256 | } |
| 13841 | } | 14257 | } |
| 13842 | 14258 | ||
| @@ -14289,14 +14705,18 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) · 446 unmodified lines | |||
| 14289 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) | 14705 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
| 14290 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; | 14706 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
| 14291 | 14707 | ||
| 14292 | if (tg3_flag(tp, PCI_EXPRESS) && | 14708 | if (tg3_flag(tp, PCI_EXPRESS)) { |
| 14293 | tg3_asic_rev(tp) != ASIC_REV_5785 && | ||
| 14294 | !tg3_flag(tp, 57765_PLUS)) { | ||
| 14295 | u32 cfg3; | 14709 | u32 cfg3; |
| 14296 | 14710 | ||
| 14297 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | 14711 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); |
| 14298 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | 14712 | if (tg3_asic_rev(tp) != ASIC_REV_5785 && |
| 14713 | !tg3_flag(tp, 57765_PLUS) && | ||
| 14714 | (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)) | ||
| 14299 | tg3_flag_set(tp, ASPM_WORKAROUND); | 14715 | tg3_flag_set(tp, ASPM_WORKAROUND); |
| 14716 | if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID) | ||
| 14717 | tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; | ||
| 14718 | if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK) | ||
| 14719 | tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; | ||
| 14300 | } | 14720 | } |
| 14301 | 14721 | ||
| 14302 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) | 14722 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
| @@ -14450,6 +14870,12 @@ static int tg3_phy_probe(struct tg3 *tp) · 147 unmodified lines | |||
| 14450 | } | 14870 | } |
| 14451 | } | 14871 | } |
| 14452 | 14872 | ||
| 14873 | if (!tg3_flag(tp, ENABLE_ASF) && | ||
| 14874 | !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && | ||
| 14875 | !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) | ||
| 14876 | tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | | ||
| 14877 | TG3_PHYFLG_KEEP_LINK_ON_PWRDN); | ||
| 14878 | |||
| 14453 | if (tg3_flag(tp, USE_PHYLIB)) | 14879 | if (tg3_flag(tp, USE_PHYLIB)) |
| 14454 | return tg3_phy_init(tp); | 14880 | return tg3_phy_init(tp); |
| 14455 | 14881 | ||
| @@ -14515,6 +14941,7 @@ static int tg3_phy_probe(struct tg3 *tp) · 59 unmodified lines | |||
| 14515 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && | 14941 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
| 14516 | (tg3_asic_rev(tp) == ASIC_REV_5719 || | 14942 | (tg3_asic_rev(tp) == ASIC_REV_5719 || |
| 14517 | tg3_asic_rev(tp) == ASIC_REV_5720 || | 14943 | tg3_asic_rev(tp) == ASIC_REV_5720 || |
| 14944 | tg3_asic_rev(tp) == ASIC_REV_57766 || | ||
| 14518 | tg3_asic_rev(tp) == ASIC_REV_5762 || | 14945 | tg3_asic_rev(tp) == ASIC_REV_5762 || |
| 14519 | (tg3_asic_rev(tp) == ASIC_REV_5717 && | 14946 | (tg3_asic_rev(tp) == ASIC_REV_5717 && |
| 14520 | tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) || | 14947 | tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) || |
| @@ -14524,7 +14951,8 @@ static int tg3_phy_probe(struct tg3 *tp) · 3 unmodified lines | |||
| 14524 | 14951 | ||
| 14525 | tg3_phy_init_link_config(tp); | 14952 | tg3_phy_init_link_config(tp); |
| 14526 | 14953 | ||
| 14527 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && | 14954 | if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && |
| 14955 | !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && | ||
| 14528 | !tg3_flag(tp, ENABLE_APE) && | 14956 | !tg3_flag(tp, ENABLE_APE) && |
| 14529 | !tg3_flag(tp, ENABLE_ASF)) { | 14957 | !tg3_flag(tp, ENABLE_ASF)) { |
| 14530 | u32 bmsr, dummy; | 14958 | u32 bmsr, dummy; |
| @@ -15300,7 +15728,8 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) · 769 unmodified lines | |||
| 15300 | } else if (tg3_asic_rev(tp) != ASIC_REV_5700 && | 15728 | } else if (tg3_asic_rev(tp) != ASIC_REV_5700 && |
| 15301 | tg3_asic_rev(tp) != ASIC_REV_5701 && | 15729 | tg3_asic_rev(tp) != ASIC_REV_5701 && |
| 15302 | tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { | 15730 | tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { |
| 15303 | tg3_flag_set(tp, TSO_BUG); | 15731 | tg3_flag_set(tp, FW_TSO); |
| 15732 | tg3_flag_set(tp, TSO_BUG); | ||
| 15304 | if (tg3_asic_rev(tp) == ASIC_REV_5705) | 15733 | if (tg3_asic_rev(tp) == ASIC_REV_5705) |
| 15305 | tp->fw_needed = FIRMWARE_TG3TSO5; | 15734 | tp->fw_needed = FIRMWARE_TG3TSO5; |
| 15306 | else | 15735 | else |
| @@ -15311,7 +15740,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) · 4 unmodified lines | |||
| 15311 | if (tg3_flag(tp, HW_TSO_1) || | 15740 | if (tg3_flag(tp, HW_TSO_1) || |
| 15312 | tg3_flag(tp, HW_TSO_2) || | 15741 | tg3_flag(tp, HW_TSO_2) || |
| 15313 | tg3_flag(tp, HW_TSO_3) || | 15742 | tg3_flag(tp, HW_TSO_3) || |
| 15314 | tp->fw_needed) { | 15743 | tg3_flag(tp, FW_TSO)) { |
| 15315 | /* For firmware TSO, assume ASF is disabled. | 15744 | /* For firmware TSO, assume ASF is disabled. |
| 15316 | * We'll disable TSO later if we discover ASF | 15745 | * We'll disable TSO later if we discover ASF |
| 15317 | * is enabled in tg3_get_eeprom_hw_cfg(). | 15746 | * is enabled in tg3_get_eeprom_hw_cfg(). |
| @@ -15326,6 +15755,9 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) · 8 unmodified lines | |||
| 15326 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) | 15755 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) |
| 15327 | tp->fw_needed = FIRMWARE_TG3; | 15756 | tp->fw_needed = FIRMWARE_TG3; |
| 15328 | 15757 | ||
| 15758 | if (tg3_asic_rev(tp) == ASIC_REV_57766) | ||
| 15759 | tp->fw_needed = FIRMWARE_TG357766; | ||
| 15760 | |||
| 15329 | tp->irq_max = 1; | 15761 | tp->irq_max = 1; |
| 15330 | 15762 | ||
| 15331 | if (tg3_flag(tp, 5750_PLUS)) { | 15763 | if (tg3_flag(tp, 5750_PLUS)) { |
| @@ -15598,7 +16030,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) · 266 unmodified lines | |||
| 15598 | */ | 16030 | */ |
| 15599 | tg3_get_eeprom_hw_cfg(tp); | 16031 | tg3_get_eeprom_hw_cfg(tp); |
| 15600 | 16032 | ||
| 15601 | if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) { | 16033 | if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) { |
| 15602 | tg3_flag_clear(tp, TSO_CAPABLE); | 16034 | tg3_flag_clear(tp, TSO_CAPABLE); |
| 15603 | tg3_flag_clear(tp, TSO_BUG); | 16035 | tg3_flag_clear(tp, TSO_BUG); |
| 15604 | tp->fw_needed = NULL; | 16036 | tp->fw_needed = NULL; |
| @@ -15786,6 +16218,11 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) · 181 unmodified lines | |||
| 15786 | udelay(50); | 16218 | udelay(50); |
| 15787 | tg3_nvram_init(tp); | 16219 | tg3_nvram_init(tp); |
| 15788 | 16220 | ||
| 16221 | /* If the device has an NVRAM, no need to load patch firmware */ | ||
| 16222 | if (tg3_asic_rev(tp) == ASIC_REV_57766 && | ||
| 16223 | !tg3_flag(tp, NO_NVRAM)) | ||
| 16224 | tp->fw_needed = NULL; | ||
| 16225 | |||
| 15789 | grc_misc_cfg = tr32(GRC_MISC_CFG); | 16226 | grc_misc_cfg = tr32(GRC_MISC_CFG); |
| 15790 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | 16227 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; |
| 15791 | 16228 | ||
| @@ -16144,7 +16581,7 @@ out: · 352 unmodified lines | |||
| 16144 | } | 16581 | } |
| 16145 | 16582 | ||
| 16146 | static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, | 16583 | static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, |
| 16147 | int size, int to_device) | 16584 | int size, bool to_device) |
| 16148 | { | 16585 | { |
| 16149 | struct tg3_internal_buffer_desc test_desc; | 16586 | struct tg3_internal_buffer_desc test_desc; |
| 16150 | u32 sram_dma_descs; | 16587 | u32 sram_dma_descs; |
| @@ -16344,7 +16781,7 @@ static int tg3_test_dma(struct tg3 *tp) · 193 unmodified lines | |||
| 16344 | p[i] = i; | 16781 | p[i] = i; |
| 16345 | 16782 | ||
| 16346 | /* Send the buffer to the chip. */ | 16783 | /* Send the buffer to the chip. */ |
| 16347 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | 16784 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true); |
| 16348 | if (ret) { | 16785 | if (ret) { |
| 16349 | dev_err(&tp->pdev->dev, | 16786 | dev_err(&tp->pdev->dev, |
| 16350 | "%s: Buffer write failed. err = %d\n", | 16787 | "%s: Buffer write failed. err = %d\n", |
| @@ -16367,7 +16804,7 @@ static int tg3_test_dma(struct tg3 *tp) · 16 unmodified lines | |||
| 16367 | } | 16804 | } |
| 16368 | #endif | 16805 | #endif |
| 16369 | /* Now read it back. */ | 16806 | /* Now read it back. */ |
| 16370 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | 16807 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false); |
| 16371 | if (ret) { | 16808 | if (ret) { |
| 16372 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " | 16809 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
| 16373 | "err = %d\n", __func__, ret); | 16810 | "err = %d\n", __func__, ret); |
| @@ -16763,7 +17200,7 @@ static int tg3_init_one(struct pci_dev *pdev, · 389 unmodified lines | |||
| 16763 | 17200 | ||
| 16764 | tg3_init_bufmgr_config(tp); | 17201 | tg3_init_bufmgr_config(tp); |
| 16765 | 17202 | ||
| 16766 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | 17203 | features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
| 16767 | 17204 | ||
| 16768 | /* 5700 B0 chips do not support checksumming correctly due | 17205 | /* 5700 B0 chips do not support checksumming correctly due |
| 16769 | * to hardware bugs. | 17206 | * to hardware bugs. |
| @@ -17048,7 +17485,7 @@ static int tg3_suspend(struct device *device) · 278 unmodified lines | |||
| 17048 | tg3_full_lock(tp, 0); | 17485 | tg3_full_lock(tp, 0); |
| 17049 | 17486 | ||
| 17050 | tg3_flag_set(tp, INIT_COMPLETE); | 17487 | tg3_flag_set(tp, INIT_COMPLETE); |
| 17051 | err2 = tg3_restart_hw(tp, 1); | 17488 | err2 = tg3_restart_hw(tp, true); |
| 17052 | if (err2) | 17489 | if (err2) |
| 17053 | goto out; | 17490 | goto out; |
| 17054 | 17491 | ||
| @@ -17082,7 +17519,8 @@ static int tg3_resume(struct device *device) · 27 unmodified lines | |||
| 17082 | tg3_full_lock(tp, 0); | 17519 | tg3_full_lock(tp, 0); |
| 17083 | 17520 | ||
| 17084 | tg3_flag_set(tp, INIT_COMPLETE); | 17521 | tg3_flag_set(tp, INIT_COMPLETE); |
| 17085 | err = tg3_restart_hw(tp, 1); | 17522 | err = tg3_restart_hw(tp, |
| 17523 | !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); | ||
| 17086 | if (err) | 17524 | if (err) |
| 17087 | goto out; | 17525 | goto out; |
| 17088 | 17526 | ||
| @@ -17098,15 +17536,9 @@ out: · 9 unmodified lines | |||
| 17098 | 17536 | ||
| 17099 | return err; | 17537 | return err; |
| 17100 | } | 17538 | } |
| 17539 | #endif /* CONFIG_PM_SLEEP */ | ||
| 17101 | 17540 | ||
| 17102 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); | 17541 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
| 17103 | #define TG3_PM_OPS (&tg3_pm_ops) | ||
| 17104 | |||
| 17105 | #else | ||
| 17106 | |||
| 17107 | #define TG3_PM_OPS NULL | ||
| 17108 | |||
| 17109 | #endif /* CONFIG_PM_SLEEP */ | ||
| 17110 | 17542 | ||
| 17111 | /** | 17543 | /** |
| 17112 | * tg3_io_error_detected - called when PCI error is detected | 17544 | * tg3_io_error_detected - called when PCI error is detected |
| @@ -17221,7 +17653,7 @@ static void tg3_io_resume(struct pci_dev *pdev) · 108 unmodified lines | |||
| 17221 | 17653 | ||
| 17222 | tg3_full_lock(tp, 0); | 17654 | tg3_full_lock(tp, 0); |
| 17223 | tg3_flag_set(tp, INIT_COMPLETE); | 17655 | tg3_flag_set(tp, INIT_COMPLETE); |
| 17224 | err = tg3_restart_hw(tp, 1); | 17656 | err = tg3_restart_hw(tp, true); |
| 17225 | if (err) { | 17657 | if (err) { |
| 17226 | tg3_full_unlock(tp); | 17658 | tg3_full_unlock(tp); |
| 17227 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); | 17659 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); |
| @@ -17254,7 +17686,7 @@ static struct pci_driver tg3_driver = { · 26 unmodified lines | |||
| 17254 | .probe = tg3_init_one, | 17686 | .probe = tg3_init_one, |
| 17255 | .remove = tg3_remove_one, | 17687 | .remove = tg3_remove_one, |
| 17256 | .err_handler = &tg3_err_handler, | 17688 | .err_handler = &tg3_err_handler, |
| 17257 | .driver.pm = TG3_PM_OPS, | 17689 | .driver.pm = &tg3_pm_ops, |
| 17258 | }; | 17690 | }; |
| 17259 | 17691 | ||
| 17260 | static int __init tg3_init(void) | 17692 | static int __init tg3_init(void) |
| @@ -2198,6 +2198,8 @@ · 2197 unmodified lines | |||
| 2198 | 2198 | ||
| 2199 | #define NIC_SRAM_DATA_CFG_3 0x00000d3c | 2199 | #define NIC_SRAM_DATA_CFG_3 0x00000d3c |
| 2200 | #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 | 2200 | #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 |
| 2201 | #define NIC_SRAM_LNK_FLAP_AVOID 0x00400000 | ||
| 2202 | #define NIC_SRAM_1G_ON_VAUX_OK 0x00800000 | ||
| 2201 | 2203 | ||
| 2202 | #define NIC_SRAM_DATA_CFG_4 0x00000d60 | 2204 | #define NIC_SRAM_DATA_CFG_4 0x00000d60 |
| 2203 | #define NIC_SRAM_GMII_MODE 0x00000002 | 2205 | #define NIC_SRAM_GMII_MODE 0x00000002 |
| @@ -2222,6 +2224,12 @@ · 18 unmodified lines | |||
| 2222 | #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 | 2224 | #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 |
| 2223 | #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 | 2225 | #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 |
| 2224 | 2226 | ||
| 2227 | #define TG3_SRAM_RXCPU_SCRATCH_BASE_57766 0x00030000 | ||
| 2228 | #define TG3_SRAM_RXCPU_SCRATCH_SIZE_57766 0x00010000 | ||
| 2229 | #define TG3_57766_FW_BASE_ADDR 0x00030000 | ||
| 2230 | #define TG3_57766_FW_HANDSHAKE 0x0003fccc | ||
| 2231 | #define TG3_SBROM_IN_SERVICE_LOOP 0x51 | ||
| 2232 | |||
| 2225 | #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128 | 2233 | #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128 |
| 2226 | #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64 | 2234 | #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64 |
| 2227 | #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32 | 2235 | #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32 |
| @@ -2365,6 +2373,13 @@ · 137 unmodified lines | |||
| 2365 | #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b | 2373 | #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b |
| 2366 | #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 | 2374 | #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 |
| 2367 | 2375 | ||
| 2376 | /* Serdes PHY Register Definitions */ | ||
| 2377 | #define SERDES_TG3_1000X_STATUS 0x14 | ||
| 2378 | #define SERDES_TG3_SGMII_MODE 0x0001 | ||
| 2379 | #define SERDES_TG3_LINK_UP 0x0002 | ||
| 2380 | #define SERDES_TG3_FULL_DUPLEX 0x0004 | ||
| 2381 | #define SERDES_TG3_SPEED_100 0x0008 | ||
| 2382 | #define SERDES_TG3_SPEED_1000 0x0010 | ||
| 2368 | 2383 | ||
| 2369 | /* APE registers. Accessible through BAR1 */ | 2384 | /* APE registers. Accessible through BAR1 */ |
| 2370 | #define TG3_APE_GPIO_MSG 0x0008 | 2385 | #define TG3_APE_GPIO_MSG 0x0008 |
| @@ -3009,17 +3024,18 @@ enum TG3_FLAGS { · 638 unmodified lines | |||
| 3009 | TG3_FLAG_JUMBO_CAPABLE, | 3024 | TG3_FLAG_JUMBO_CAPABLE, |
| 3010 | TG3_FLAG_CHIP_RESETTING, | 3025 | TG3_FLAG_CHIP_RESETTING, |
| 3011 | TG3_FLAG_INIT_COMPLETE, | 3026 | TG3_FLAG_INIT_COMPLETE, |
| 3012 | TG3_FLAG_TSO_BUG, | ||
| 3013 | TG3_FLAG_MAX_RXPEND_64, | 3027 | TG3_FLAG_MAX_RXPEND_64, |
| 3014 | TG3_FLAG_TSO_CAPABLE, | ||
| 3015 | TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */ | 3028 | TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */ |
| 3016 | TG3_FLAG_ASF_NEW_HANDSHAKE, | 3029 | TG3_FLAG_ASF_NEW_HANDSHAKE, |
| 3017 | TG3_FLAG_HW_AUTONEG, | 3030 | TG3_FLAG_HW_AUTONEG, |
| 3018 | TG3_FLAG_IS_NIC, | 3031 | TG3_FLAG_IS_NIC, |
| 3019 | TG3_FLAG_FLASH, | 3032 | TG3_FLAG_FLASH, |
| 3033 | TG3_FLAG_FW_TSO, | ||
| 3020 | TG3_FLAG_HW_TSO_1, | 3034 | TG3_FLAG_HW_TSO_1, |
| 3021 | TG3_FLAG_HW_TSO_2, | 3035 | TG3_FLAG_HW_TSO_2, |
| 3022 | TG3_FLAG_HW_TSO_3, | 3036 | TG3_FLAG_HW_TSO_3, |
| 3037 | TG3_FLAG_TSO_CAPABLE, | ||
| 3038 | TG3_FLAG_TSO_BUG, | ||
| 3023 | TG3_FLAG_ICH_WORKAROUND, | 3039 | TG3_FLAG_ICH_WORKAROUND, |
| 3024 | TG3_FLAG_1SHOT_MSI, | 3040 | TG3_FLAG_1SHOT_MSI, |
| 3025 | TG3_FLAG_NO_FWARE_REPORTED, | 3041 | TG3_FLAG_NO_FWARE_REPORTED, |
| @@ -3064,6 +3080,13 @@ enum TG3_FLAGS { · 38 unmodified lines | |||
| 3064 | TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */ | 3080 | TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */ |
| 3065 | }; | 3081 | }; |
| 3066 | 3082 | ||
| 3083 | struct tg3_firmware_hdr { | ||
| 3084 | __be32 version; /* unused for fragments */ | ||
| 3085 | __be32 base_addr; | ||
| 3086 | __be32 len; | ||
| 3087 | }; | ||
| 3088 | #define TG3_FW_HDR_LEN (sizeof(struct tg3_firmware_hdr)) | ||
| 3089 | |||
| 3067 | struct tg3 { | 3090 | struct tg3 { |
| 3068 | /* begin "general, frequently-used members" cacheline section */ | 3091 | /* begin "general, frequently-used members" cacheline section */ |
| 3069 | 3092 | ||
| @@ -3267,6 +3290,7 @@ struct tg3 { · 197 unmodified lines | |||
| 3267 | #define TG3_PHYFLG_IS_LOW_POWER 0x00000001 | 3290 | #define TG3_PHYFLG_IS_LOW_POWER 0x00000001 |
| 3268 | #define TG3_PHYFLG_IS_CONNECTED 0x00000002 | 3291 | #define TG3_PHYFLG_IS_CONNECTED 0x00000002 |
| 3269 | #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004 | 3292 | #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004 |
| 3293 | #define TG3_PHYFLG_USER_CONFIGURED 0x00000008 | ||
| 3270 | #define TG3_PHYFLG_PHY_SERDES 0x00000010 | 3294 | #define TG3_PHYFLG_PHY_SERDES 0x00000010 |
| 3271 | #define TG3_PHYFLG_MII_SERDES 0x00000020 | 3295 | #define TG3_PHYFLG_MII_SERDES 0x00000020 |
| 3272 | #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \ | 3296 | #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \ |
| @@ -3284,6 +3308,8 @@ struct tg3 { · 11 unmodified lines | |||
| 3284 | #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000 | 3308 | #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000 |
| 3285 | #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000 | 3309 | #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000 |
| 3286 | #define TG3_PHYFLG_EEE_CAP 0x00040000 | 3310 | #define TG3_PHYFLG_EEE_CAP 0x00040000 |
| 3311 | #define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000 | ||
| 3312 | #define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000 | ||
| 3287 | #define TG3_PHYFLG_MDIX_STATE 0x00200000 | 3313 | #define TG3_PHYFLG_MDIX_STATE 0x00200000 |
| 3288 | 3314 | ||
| 3289 | u32 led_ctrl; | 3315 | u32 led_ctrl; |
| @@ -76,7 +76,7 @@ static void bfa_ioc_pf_disabled(struct bfa_ioc *ioc); · 75 unmodified lines | |||
| 76 | static void bfa_ioc_pf_failed(struct bfa_ioc *ioc); | 76 | static void bfa_ioc_pf_failed(struct bfa_ioc *ioc); |
| 77 | static void bfa_ioc_pf_hwfailed(struct bfa_ioc *ioc); | 77 | static void bfa_ioc_pf_hwfailed(struct bfa_ioc *ioc); |
| 78 | static void bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc); | 78 | static void bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc); |
| 79 | static void bfa_ioc_boot(struct bfa_ioc *ioc, u32 boot_type, | 79 | static void bfa_ioc_boot(struct bfa_ioc *ioc, enum bfi_fwboot_type boot_type, |
| 80 | u32 boot_param); | 80 | u32 boot_param); |
| 81 | static u32 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr); | 81 | static u32 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr); |
| 82 | static void bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, | 82 | static void bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, |
| @@ -610,7 +610,7 @@ bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget) · 609 unmodified lines | |||
| 610 | rcb->rxq->rx_bytes += length; | 610 | rcb->rxq->rx_bytes += length; |
| 611 | 611 | ||
| 612 | if (flags & BNA_CQ_EF_VLAN) | 612 | if (flags & BNA_CQ_EF_VLAN) |
| 613 | __vlan_hwaccel_put_tag(skb, ntohs(cmpl->vlan_tag)); | 613 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cmpl->vlan_tag)); |
| 614 | 614 | ||
| 615 | if (BNAD_RXBUF_IS_PAGE(unmap_q->type)) | 615 | if (BNAD_RXBUF_IS_PAGE(unmap_q->type)) |
| 616 | napi_gro_frags(&rx_ctrl->napi); | 616 | napi_gro_frags(&rx_ctrl->napi); |
| @@ -1264,9 +1264,8 @@ bnad_mem_alloc(struct bnad *bnad, · 647 unmodified lines | |||
| 1264 | mem_info->mdl[i].len = mem_info->len; | 1264 | mem_info->mdl[i].len = mem_info->len; |
| 1265 | mem_info->mdl[i].kva = | 1265 | mem_info->mdl[i].kva = |
| 1266 | dma_alloc_coherent(&bnad->pcidev->dev, | 1266 | dma_alloc_coherent(&bnad->pcidev->dev, |
| 1267 | mem_info->len, &dma_pa, | 1267 | mem_info->len, &dma_pa, |
| 1268 | GFP_KERNEL); | 1268 | GFP_KERNEL); |
| 1269 | |||
| 1270 | if (mem_info->mdl[i].kva == NULL) | 1269 | if (mem_info->mdl[i].kva == NULL) |
| 1271 | goto err_return; | 1270 | goto err_return; |
| 1272 | 1271 | ||
| @@ -3069,8 +3068,7 @@ bnad_change_mtu(struct net_device *netdev, int new_mtu) · 1796 unmodified lines | |||
| 3069 | } | 3068 | } |
| 3070 | 3069 | ||
| 3071 | static int | 3070 | static int |
| 3072 | bnad_vlan_rx_add_vid(struct net_device *netdev, | 3071 | bnad_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid) |
| 3073 | unsigned short vid) | ||
| 3074 | { | 3072 | { |
| 3075 | struct bnad *bnad = netdev_priv(netdev); | 3073 | struct bnad *bnad = netdev_priv(netdev); |
| 3076 | unsigned long flags; | 3074 | unsigned long flags; |
| @@ -3091,8 +3089,7 @@ bnad_vlan_rx_add_vid(struct net_device *netdev, · 14 unmodified lines | |||
| 3091 | } | 3089 | } |
| 3092 | 3090 | ||
| 3093 | static int | 3091 | static int |
| 3094 | bnad_vlan_rx_kill_vid(struct net_device *netdev, | 3092 | bnad_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) |
| 3095 | unsigned short vid) | ||
| 3096 | { | 3093 | { |
| 3097 | struct bnad *bnad = netdev_priv(netdev); | 3094 | struct bnad *bnad = netdev_priv(netdev); |
| 3098 | unsigned long flags; | 3095 | unsigned long flags; |
| @@ -3171,14 +3168,14 @@ bnad_netdev_init(struct bnad *bnad, bool using_dac) · 72 unmodified lines | |||
| 3171 | 3168 | ||
| 3172 | netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | | 3169 | netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | |
| 3173 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | 3170 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
| 3174 | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_TX; | 3171 | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_TX; |
| 3175 | 3172 | ||
| 3176 | netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA | | 3173 | netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA | |
| 3177 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | 3174 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
| 3178 | NETIF_F_TSO | NETIF_F_TSO6; | 3175 | NETIF_F_TSO | NETIF_F_TSO6; |
| 3179 | 3176 | ||
| 3180 | netdev->features |= netdev->hw_features | | 3177 | netdev->features |= netdev->hw_features | |
| 3181 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER; | 3178 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER; |
| 3182 | 3179 | ||
| 3183 | if (using_dac) | 3180 | if (using_dac) |
| 3184 | netdev->features |= NETIF_F_HIGHDMA; | 3181 | netdev->features |= NETIF_F_HIGHDMA; |
| @@ -47,22 +47,19 @@ static int at91ether_start(struct net_device *dev) · 46 unmodified lines | |||
| 47 | int i; | 47 | int i; |
| 48 | 48 | ||
| 49 | lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev, | 49 | lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev, |
| 50 | MAX_RX_DESCR * sizeof(struct macb_dma_desc), | 50 | (MAX_RX_DESCR * |
| 51 | &lp->rx_ring_dma, GFP_KERNEL); | 51 | sizeof(struct macb_dma_desc)), |
| 52 | if (!lp->rx_ring) { | 52 | &lp->rx_ring_dma, GFP_KERNEL); |
| 53 | netdev_err(dev, "unable to alloc rx ring DMA buffer\n"); | 53 | if (!lp->rx_ring) |
| 54 | return -ENOMEM; | 54 | return -ENOMEM; |
| 55 | } | ||
| 56 | 55 | ||
| 57 | lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev, | 56 | lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev, |
| 58 | MAX_RX_DESCR * MAX_RBUFF_SZ, | 57 | MAX_RX_DESCR * MAX_RBUFF_SZ, |
| 59 | &lp->rx_buffers_dma, GFP_KERNEL); | 58 | &lp->rx_buffers_dma, GFP_KERNEL); |
| 60 | if (!lp->rx_buffers) { | 59 | if (!lp->rx_buffers) { |
| 61 | netdev_err(dev, "unable to alloc rx data DMA buffer\n"); | ||
| 62 | |||
| 63 | dma_free_coherent(&lp->pdev->dev, | 60 | dma_free_coherent(&lp->pdev->dev, |
| 64 | MAX_RX_DESCR * sizeof(struct macb_dma_desc), | 61 | MAX_RX_DESCR * sizeof(struct macb_dma_desc), |
| 65 | lp->rx_ring, lp->rx_ring_dma); | 62 | lp->rx_ring, lp->rx_ring_dma); |
| 66 | lp->rx_ring = NULL; | 63 | lp->rx_ring = NULL; |
| 67 | return -ENOMEM; | 64 | return -ENOMEM; |
| 68 | } | 65 | } |
| @@ -209,7 +206,6 @@ static void at91ether_rx(struct net_device *dev) · 140 unmodified lines | |||
| 209 | netif_rx(skb); | 206 | netif_rx(skb); |
| 210 | } else { | 207 | } else { |
| 211 | lp->stats.rx_dropped++; | 208 | lp->stats.rx_dropped++; |
| 212 | netdev_notice(dev, "Memory squeeze, dropping packet.\n"); | ||
| 213 | } | 209 | } |
| 214 | 210 | ||
| 215 | if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH)) | 211 | if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH)) |
| @@ -303,42 +299,7 @@ static const struct of_device_id at91ether_dt_ids[] = { · 87 unmodified lines | |||
| 303 | { .compatible = "cdns,emac" }, | 299 | { .compatible = "cdns,emac" }, |
| 304 | { /* sentinel */ } | 300 | { /* sentinel */ } |
| 305 | }; | 301 | }; |
| 306 | |||
| 307 | MODULE_DEVICE_TABLE(of, at91ether_dt_ids); | 302 | MODULE_DEVICE_TABLE(of, at91ether_dt_ids); |
| 308 | |||
| 309 | static int at91ether_get_phy_mode_dt(struct platform_device *pdev) | ||
| 310 | { | ||
| 311 | struct device_node *np = pdev->dev.of_node; | ||
| 312 | |||
| 313 | if (np) | ||
| 314 | return of_get_phy_mode(np); | ||
| 315 | |||
| 316 | return -ENODEV; | ||
| 317 | } | ||
| 318 | |||
| 319 | static int at91ether_get_hwaddr_dt(struct macb *bp) | ||
| 320 | { | ||
| 321 | struct device_node *np = bp->pdev->dev.of_node; | ||
| 322 | |||
| 323 | if (np) { | ||
| 324 | const char *mac = of_get_mac_address(np); | ||
| 325 | if (mac) { | ||
| 326 | memcpy(bp->dev->dev_addr, mac, ETH_ALEN); | ||
| 327 | return 0; | ||
| 328 | } | ||
| 329 | } | ||
| 330 | |||
| 331 | return -ENODEV; | ||
| 332 | } | ||
| 333 | #else | ||
| 334 | static int at91ether_get_phy_mode_dt(struct platform_device *pdev) | ||
| 335 | { | ||
| 336 | return -ENODEV; | ||
| 337 | } | ||
| 338 | static int at91ether_get_hwaddr_dt(struct macb *bp) | ||
| 339 | { | ||
| 340 | return -ENODEV; | ||
| 341 | } | ||
| 342 | #endif | 303 | #endif |
| 343 | 304 | ||
| 344 | /* Detect MAC & PHY and perform ethernet interface initialization */ | 305 | /* Detect MAC & PHY and perform ethernet interface initialization */ |
| @@ -352,6 +313,7 @@ static int __init at91ether_probe(struct platform_device *pdev) · 7 unmodified lines | |||
| 352 | struct macb *lp; | 313 | struct macb *lp; |
| 353 | int res; | 314 | int res; |
| 354 | u32 reg; | 315 | u32 reg; |
| 316 | const char *mac; | ||
| 355 | 317 | ||
| 356 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 318 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 357 | if (!regs) | 319 | if (!regs) |
| @@ -403,11 +365,13 @@ static int __init at91ether_probe(struct platform_device *pdev) · 45 unmodified lines | |||
| 403 | platform_set_drvdata(pdev, dev); | 365 | platform_set_drvdata(pdev, dev); |
| 404 | SET_NETDEV_DEV(dev, &pdev->dev); | 366 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 405 | 367 | ||
| 406 | res = at91ether_get_hwaddr_dt(lp); | 368 | mac = of_get_mac_address(pdev->dev.of_node); |
| 407 | if (res < 0) | 369 | if (mac) |
| 370 | memcpy(lp->dev->dev_addr, mac, ETH_ALEN); | ||
| 371 | else | ||
| 408 | macb_get_hwaddr(lp); | 372 | macb_get_hwaddr(lp); |
| 409 | 373 | ||
| 410 | res = at91ether_get_phy_mode_dt(pdev); | 374 | res = of_get_phy_mode(pdev->dev.of_node); |
| 411 | if (res < 0) { | 375 | if (res < 0) { |
| 412 | if (board_data && board_data->is_rmii) | 376 | if (board_data && board_data->is_rmii) |
| 413 | lp->phy_interface = PHY_INTERFACE_MODE_RMII; | 377 | lp->phy_interface = PHY_INTERFACE_MODE_RMII; |
| @@ -430,7 +394,8 @@ static int __init at91ether_probe(struct platform_device *pdev) · 16 unmodified lines | |||
| 430 | if (res) | 394 | if (res) |
| 431 | goto err_disable_clock; | 395 | goto err_disable_clock; |
| 432 | 396 | ||
| 433 | if (macb_mii_init(lp) != 0) | 397 | res = macb_mii_init(lp); |
| 398 | if (res) | ||
| 434 | goto err_out_unregister_netdev; | 399 | goto err_out_unregister_netdev; |
| 435 | 400 | ||
| 436 | /* will be enabled in open() */ | 401 | /* will be enabled in open() */ |
| @@ -519,18 +484,7 @@ static struct platform_driver at91ether_driver = { · 82 unmodified lines | |||
| 519 | }, | 484 | }, |
| 520 | }; | 485 | }; |
| 521 | 486 | ||
| 522 | static int __init at91ether_init(void) | 487 | module_platform_driver_probe(at91ether_driver, at91ether_probe); |
| 523 | { | ||
| 524 | return platform_driver_probe(&at91ether_driver, at91ether_probe); | ||
| 525 | } | ||
| 526 | |||
| 527 | static void __exit at91ether_exit(void) | ||
| 528 | { | ||
| 529 | platform_driver_unregister(&at91ether_driver); | ||
| 530 | } | ||
| 531 | |||
| 532 | module_init(at91ether_init) | ||
| 533 | module_exit(at91ether_exit) | ||
| 534 | 488 | ||
| 535 | MODULE_LICENSE("GPL"); | 489 | MODULE_LICENSE("GPL"); |
| 536 | MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver"); | 490 | MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver"); |
| @@ -485,6 +485,8 @@ static void macb_tx_interrupt(struct macb *bp) · 484 unmodified lines | |||
| 485 | status = macb_readl(bp, TSR); | 485 | status = macb_readl(bp, TSR); |
| 486 | macb_writel(bp, TSR, status); | 486 | macb_writel(bp, TSR, status); |
| 487 | 487 | ||
| 488 | macb_writel(bp, ISR, MACB_BIT(TCOMP)); | ||
| 489 | |||
| 488 | netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", | 490 | netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", |
| 489 | (unsigned long)status); | 491 | (unsigned long)status); |
| 490 | 492 | ||
| @@ -736,6 +738,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id) · 245 unmodified lines | |||
| 736 | * now. | 738 | * now. |
| 737 | */ | 739 | */ |
| 738 | macb_writel(bp, IDR, MACB_RX_INT_FLAGS); | 740 | macb_writel(bp, IDR, MACB_RX_INT_FLAGS); |
| 741 | macb_writel(bp, ISR, MACB_BIT(RCOMP)); | ||
| 739 | 742 | ||
| 740 | if (napi_schedule_prep(&bp->napi)) { | 743 | if (napi_schedule_prep(&bp->napi)) { |
| 741 | netdev_vdbg(bp->dev, "scheduling RX softirq\n"); | 744 | netdev_vdbg(bp->dev, "scheduling RX softirq\n"); |
| @@ -1054,6 +1057,7 @@ static void macb_configure_dma(struct macb *bp) · 312 unmodified lines | |||
| 1054 | dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); | 1057 | dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); |
| 1055 | dmacfg |= GEM_BF(FBLDO, 16); | 1058 | dmacfg |= GEM_BF(FBLDO, 16); |
| 1056 | dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); | 1059 | dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); |
| 1060 | dmacfg &= ~GEM_BIT(ENDIA); | ||
| 1057 | gem_writel(bp, DMACFG, dmacfg); | 1061 | gem_writel(bp, DMACFG, dmacfg); |
| 1058 | } | 1062 | } |
| 1059 | } | 1063 | } |
| @@ -1472,41 +1476,7 @@ static const struct of_device_id macb_dt_ids[] = { · 412 unmodified lines | |||
| 1472 | { .compatible = "cdns,gem" }, | 1476 | { .compatible = "cdns,gem" }, |
| 1473 | { /* sentinel */ } | 1477 | { /* sentinel */ } |
| 1474 | }; | 1478 | }; |
| 1475 | |||
| 1476 | MODULE_DEVICE_TABLE(of, macb_dt_ids); | 1479 | MODULE_DEVICE_TABLE(of, macb_dt_ids); |
| 1477 | |||
| 1478 | static int macb_get_phy_mode_dt(struct platform_device *pdev) | ||
| 1479 | { | ||
| 1480 | struct device_node *np = pdev->dev.of_node; | ||
| 1481 | |||
| 1482 | if (np) | ||
| 1483 | return of_get_phy_mode(np); | ||
| 1484 | |||
| 1485 | return -ENODEV; | ||
| 1486 | } | ||
| 1487 | |||
| 1488 | static int macb_get_hwaddr_dt(struct macb *bp) | ||
| 1489 | { | ||
| 1490 | struct device_node *np = bp->pdev->dev.of_node; | ||
| 1491 | if (np) { | ||
| 1492 | const char *mac = of_get_mac_address(np); | ||
| 1493 | if (mac) { | ||
| 1494 | memcpy(bp->dev->dev_addr, mac, ETH_ALEN); | ||
| 1495 | return 0; | ||
| 1496 | } | ||
| 1497 | } | ||
| 1498 | |||
| 1499 | return -ENODEV; | ||
| 1500 | } | ||
| 1501 | #else | ||
| 1502 | static int macb_get_phy_mode_dt(struct platform_device *pdev) | ||
| 1503 | { | ||
| 1504 | return -ENODEV; | ||
| 1505 | } | ||
| 1506 | static int macb_get_hwaddr_dt(struct macb *bp) | ||
| 1507 | { | ||
| 1508 | return -ENODEV; | ||
| 1509 | } | ||
| 1510 | #endif | 1480 | #endif |
| 1511 | 1481 | ||
| 1512 | static int __init macb_probe(struct platform_device *pdev) | 1482 | static int __init macb_probe(struct platform_device *pdev) |
| @@ -1519,6 +1489,7 @@ static int __init macb_probe(struct platform_device *pdev) · 6 unmodified lines | |||
| 1519 | u32 config; | 1489 | u32 config; |
| 1520 | int err = -ENXIO; | 1490 | int err = -ENXIO; |
| 1521 | struct pinctrl *pinctrl; | 1491 | struct pinctrl *pinctrl; |
| 1492 | const char *mac; | ||
| 1522 | 1493 | ||
| 1523 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1494 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1524 | if (!regs) { | 1495 | if (!regs) { |
| @@ -1557,14 +1528,14 @@ static int __init macb_probe(struct platform_device *pdev) · 32 unmodified lines | |||
| 1557 | dev_err(&pdev->dev, "failed to get macb_clk\n"); | 1528 | dev_err(&pdev->dev, "failed to get macb_clk\n"); |
| 1558 | goto err_out_free_dev; | 1529 | goto err_out_free_dev; |
| 1559 | } | 1530 | } |
| 1560 | clk_enable(bp->pclk); | 1531 | clk_prepare_enable(bp->pclk); |
| 1561 | 1532 | ||
| 1562 | bp->hclk = clk_get(&pdev->dev, "hclk"); | 1533 | bp->hclk = clk_get(&pdev->dev, "hclk"); |
| 1563 | if (IS_ERR(bp->hclk)) { | 1534 | if (IS_ERR(bp->hclk)) { |
| 1564 | dev_err(&pdev->dev, "failed to get hclk\n"); | 1535 | dev_err(&pdev->dev, "failed to get hclk\n"); |
| 1565 | goto err_out_put_pclk; | 1536 | goto err_out_put_pclk; |
| 1566 | } | 1537 | } |
| 1567 | clk_enable(bp->hclk); | 1538 | clk_prepare_enable(bp->hclk); |
| 1568 | 1539 | ||
| 1569 | bp->regs = ioremap(regs->start, resource_size(regs)); | 1540 | bp->regs = ioremap(regs->start, resource_size(regs)); |
| 1570 | if (!bp->regs) { | 1541 | if (!bp->regs) { |
| @@ -1592,11 +1563,13 @@ static int __init macb_probe(struct platform_device *pdev) · 21 unmodified lines | |||
| 1592 | config |= macb_dbw(bp); | 1563 | config |= macb_dbw(bp); |
| 1593 | macb_writel(bp, NCFGR, config); | 1564 | macb_writel(bp, NCFGR, config); |
| 1594 | 1565 | ||
| 1595 | err = macb_get_hwaddr_dt(bp); | 1566 | mac = of_get_mac_address(pdev->dev.of_node); |
| 1596 | if (err < 0) | 1567 | if (mac) |
| 1568 | memcpy(bp->dev->dev_addr, mac, ETH_ALEN); | ||
| 1569 | else | ||
| 1597 | macb_get_hwaddr(bp); | 1570 | macb_get_hwaddr(bp); |
| 1598 | 1571 | ||
| 1599 | err = macb_get_phy_mode_dt(pdev); | 1572 | err = of_get_phy_mode(pdev->dev.of_node); |
| 1600 | if (err < 0) { | 1573 | if (err < 0) { |
| 1601 | pdata = pdev->dev.platform_data; | 1574 | pdata = pdev->dev.platform_data; |
| 1602 | if (pdata && pdata->is_rmii) | 1575 | if (pdata && pdata->is_rmii) |
| @@ -1629,9 +1602,9 @@ static int __init macb_probe(struct platform_device *pdev) · 26 unmodified lines | |||
| 1629 | goto err_out_free_irq; | 1602 | goto err_out_free_irq; |
| 1630 | } | 1603 | } |
| 1631 | 1604 | ||
| 1632 | if (macb_mii_init(bp) != 0) { | 1605 | err = macb_mii_init(bp); |
| 1606 | if (err) | ||
| 1633 | goto err_out_unregister_netdev; | 1607 | goto err_out_unregister_netdev; |
| 1634 | } | ||
| 1635 | 1608 | ||
| 1636 | platform_set_drvdata(pdev, dev); | 1609 | platform_set_drvdata(pdev, dev); |
| 1637 | 1610 | ||
| @@ -1654,9 +1627,9 @@ err_out_free_irq: · 16 unmodified lines | |||
| 1654 | err_out_iounmap: | 1627 | err_out_iounmap: |
| 1655 | iounmap(bp->regs); | 1628 | iounmap(bp->regs); |
| 1656 | err_out_disable_clocks: | 1629 | err_out_disable_clocks: |
| 1657 | clk_disable(bp->hclk); | 1630 | clk_disable_unprepare(bp->hclk); |
| 1658 | clk_put(bp->hclk); | 1631 | clk_put(bp->hclk); |
| 1659 | clk_disable(bp->pclk); | 1632 | clk_disable_unprepare(bp->pclk); |
| 1660 | err_out_put_pclk: | 1633 | err_out_put_pclk: |
| 1661 | clk_put(bp->pclk); | 1634 | clk_put(bp->pclk); |
| 1662 | err_out_free_dev: | 1635 | err_out_free_dev: |
| @@ -1683,9 +1656,9 @@ static int __exit macb_remove(struct platform_device *pdev) · 20 unmodified lines | |||
| 1683 | unregister_netdev(dev); | 1656 | unregister_netdev(dev); |
| 1684 | free_irq(dev->irq, dev); | 1657 | free_irq(dev->irq, dev); |
| 1685 | iounmap(bp->regs); | 1658 | iounmap(bp->regs); |
| 1686 | clk_disable(bp->hclk); | 1659 | clk_disable_unprepare(bp->hclk); |
| 1687 | clk_put(bp->hclk); | 1660 | clk_put(bp->hclk); |
| 1688 | clk_disable(bp->pclk); | 1661 | clk_disable_unprepare(bp->pclk); |
| 1689 | clk_put(bp->pclk); | 1662 | clk_put(bp->pclk); |
| 1690 | free_netdev(dev); | 1663 | free_netdev(dev); |
| 1691 | platform_set_drvdata(pdev, NULL); | 1664 | platform_set_drvdata(pdev, NULL); |
| @@ -1703,8 +1676,8 @@ static int macb_suspend(struct platform_device *pdev, pm_message_t state) · 11 unmodified lines | |||
| 1703 | netif_carrier_off(netdev); | 1676 | netif_carrier_off(netdev); |
| 1704 | netif_device_detach(netdev); | 1677 | netif_device_detach(netdev); |
| 1705 | 1678 | ||
| 1706 | clk_disable(bp->hclk); | 1679 | clk_disable_unprepare(bp->hclk); |
| 1707 | clk_disable(bp->pclk); | 1680 | clk_disable_unprepare(bp->pclk); |
| 1708 | 1681 | ||
| 1709 | return 0; | 1682 | return 0; |
| 1710 | } | 1683 | } |
| @@ -1714,8 +1687,8 @@ static int macb_resume(struct platform_device *pdev) · 3 unmodified lines | |||
| 1714 | struct net_device *netdev = platform_get_drvdata(pdev); | 1687 | struct net_device *netdev = platform_get_drvdata(pdev); |
| 1715 | struct macb *bp = netdev_priv(netdev); | 1688 | struct macb *bp = netdev_priv(netdev); |
| 1716 | 1689 | ||
| 1717 | clk_enable(bp->pclk); | 1690 | clk_prepare_enable(bp->pclk); |
| 1718 | clk_enable(bp->hclk); | 1691 | clk_prepare_enable(bp->hclk); |
| 1719 | 1692 | ||
| 1720 | netif_device_attach(netdev); | 1693 | netif_device_attach(netdev); |
| 1721 | 1694 | ||
| @@ -1737,18 +1710,7 @@ static struct platform_driver macb_driver = { · 15 unmodified lines | |||
| 1737 | }, | 1710 | }, |
| 1738 | }; | 1711 | }; |
| 1739 | 1712 | ||
| 1740 | static int __init macb_init(void) | 1713 | module_platform_driver_probe(macb_driver, macb_probe); |
| 1741 | { | ||
| 1742 | return platform_driver_probe(&macb_driver, macb_probe); | ||
| 1743 | } | ||
| 1744 | |||
| 1745 | static void __exit macb_exit(void) | ||
| 1746 | { | ||
| 1747 | platform_driver_unregister(&macb_driver); | ||
| 1748 | } | ||
| 1749 | |||
| 1750 | module_init(macb_init); | ||
| 1751 | module_exit(macb_exit); | ||
| 1752 | 1714 | ||
| 1753 | MODULE_LICENSE("GPL"); | 1715 | MODULE_LICENSE("GPL"); |
| 1754 | MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); | 1716 | MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); |
| @@ -173,6 +173,8 @@ · 172 unmodified lines | |||
| 173 | /* Bitfields in DMACFG. */ | 173 | /* Bitfields in DMACFG. */ |
| 174 | #define GEM_FBLDO_OFFSET 0 | 174 | #define GEM_FBLDO_OFFSET 0 |
| 175 | #define GEM_FBLDO_SIZE 5 | 175 | #define GEM_FBLDO_SIZE 5 |
| 176 | #define GEM_ENDIA_OFFSET 7 | ||
| 177 | #define GEM_ENDIA_SIZE 1 | ||
| 176 | #define GEM_RXBMS_OFFSET 8 | 178 | #define GEM_RXBMS_OFFSET 8 |
| 177 | #define GEM_RXBMS_SIZE 2 | 179 | #define GEM_RXBMS_SIZE 2 |
| 178 | #define GEM_TXPBMS_OFFSET 10 | 180 | #define GEM_TXPBMS_OFFSET 10 |
| @@ -1482,7 +1482,7 @@ static int xgmac_set_features(struct net_device *dev, netdev_features_t features · 1481 unmodified lines | |||
| 1482 | u32 ctrl; | 1482 | u32 ctrl; |
| 1483 | struct xgmac_priv *priv = netdev_priv(dev); | 1483 | struct xgmac_priv *priv = netdev_priv(dev); |
| 1484 | void __iomem *ioaddr = priv->base; | 1484 | void __iomem *ioaddr = priv->base; |
| 1485 | u32 changed = dev->features ^ features; | 1485 | netdev_features_t changed = dev->features ^ features; |
| 1486 | 1486 | ||
| 1487 | if (!(changed & NETIF_F_RXCSUM)) | 1487 | if (!(changed & NETIF_F_RXCSUM)) |
| 1488 | return 0; | 1488 | return 0; |
| @@ -1886,12 +1886,9 @@ static int xgmac_resume(struct device *dev) · 397 unmodified lines | |||
| 1886 | 1886 | ||
| 1887 | return 0; | 1887 | return 0; |
| 1888 | } | 1888 | } |
| 1889 | #endif /* CONFIG_PM_SLEEP */ | ||
| 1889 | 1890 | ||
| 1890 | static SIMPLE_DEV_PM_OPS(xgmac_pm_ops, xgmac_suspend, xgmac_resume); | 1891 | static SIMPLE_DEV_PM_OPS(xgmac_pm_ops, xgmac_suspend, xgmac_resume); |
| 1891 | #define XGMAC_PM_OPS (&xgmac_pm_ops) | ||
| 1892 | #else | ||
| 1893 | #define XGMAC_PM_OPS NULL | ||
| 1894 | #endif /* CONFIG_PM_SLEEP */ | ||
| 1895 | 1892 | ||
| 1896 | static const struct of_device_id xgmac_of_match[] = { | 1893 | static const struct of_device_id xgmac_of_match[] = { |
| 1897 | { .compatible = "calxeda,hb-xgmac", }, | 1894 | { .compatible = "calxeda,hb-xgmac", }, |
| @@ -1906,7 +1903,7 @@ static struct platform_driver xgmac_driver = { · 8 unmodified lines | |||
| 1906 | }, | 1903 | }, |
| 1907 | .probe = xgmac_probe, | 1904 | .probe = xgmac_probe, |
| 1908 | .remove = xgmac_remove, | 1905 | .remove = xgmac_remove, |
| 1909 | .driver.pm = XGMAC_PM_OPS, | 1906 | .driver.pm = &xgmac_pm_ops, |
| 1910 | }; | 1907 | }; |
| 1911 | 1908 | ||
| 1912 | module_platform_driver(xgmac_driver); | 1909 | module_platform_driver(xgmac_driver); |
| @@ -856,10 +856,10 @@ static netdev_features_t t1_fix_features(struct net_device *dev, · 855 unmodified lines | |||
| 856 | * Since there is no support for separate rx/tx vlan accel | 856 | * Since there is no support for separate rx/tx vlan accel |
| 857 | * enable/disable make sure tx flag is always in same state as rx. | 857 | * enable/disable make sure tx flag is always in same state as rx. |
| 858 | */ | 858 | */ |
| 859 | if (features & NETIF_F_HW_VLAN_RX) | 859 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 860 | features |= NETIF_F_HW_VLAN_TX; | 860 | features |= NETIF_F_HW_VLAN_CTAG_TX; |
| 861 | else | 861 | else |
| 862 | features &= ~NETIF_F_HW_VLAN_TX; | 862 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 863 | 863 | ||
| 864 | return features; | 864 | return features; |
| 865 | } | 865 | } |
| @@ -869,7 +869,7 @@ static int t1_set_features(struct net_device *dev, netdev_features_t features) · 3 unmodified lines | |||
| 869 | netdev_features_t changed = dev->features ^ features; | 869 | netdev_features_t changed = dev->features ^ features; |
| 870 | struct adapter *adapter = dev->ml_priv; | 870 | struct adapter *adapter = dev->ml_priv; |
| 871 | 871 | ||
| 872 | if (changed & NETIF_F_HW_VLAN_RX) | 872 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
| 873 | t1_vlan_mode(adapter, features); | 873 | t1_vlan_mode(adapter, features); |
| 874 | 874 | ||
| 875 | return 0; | 875 | return 0; |
| @@ -1085,8 +1085,9 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 209 unmodified lines | |||
| 1085 | netdev->features |= NETIF_F_HIGHDMA; | 1085 | netdev->features |= NETIF_F_HIGHDMA; |
| 1086 | if (vlan_tso_capable(adapter)) { | 1086 | if (vlan_tso_capable(adapter)) { |
| 1087 | netdev->features |= | 1087 | netdev->features |= |
| 1088 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | 1088 | NETIF_F_HW_VLAN_CTAG_TX | |
| 1089 | netdev->hw_features |= NETIF_F_HW_VLAN_RX; | 1089 | NETIF_F_HW_VLAN_CTAG_RX; |
| 1090 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; | ||
| 1090 | 1091 | ||
| 1091 | /* T204: disable TSO */ | 1092 | /* T204: disable TSO */ |
| 1092 | if (!(is_T2(adapter)) || bi->port_number != 4) { | 1093 | if (!(is_T2(adapter)) || bi->port_number != 4) { |
| @@ -734,7 +734,7 @@ void t1_vlan_mode(struct adapter *adapter, netdev_features_t features) · 733 unmodified lines | |||
| 734 | { | 734 | { |
| 735 | struct sge *sge = adapter->sge; | 735 | struct sge *sge = adapter->sge; |
| 736 | 736 | ||
| 737 | if (features & NETIF_F_HW_VLAN_RX) | 737 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 738 | sge->sge_control |= F_VLAN_XTRACT; | 738 | sge->sge_control |= F_VLAN_XTRACT; |
| 739 | else | 739 | else |
| 740 | sge->sge_control &= ~F_VLAN_XTRACT; | 740 | sge->sge_control &= ~F_VLAN_XTRACT; |
| @@ -835,7 +835,7 @@ static void refill_free_list(struct sge *sge, struct freelQ *q) · 94 unmodified lines | |||
| 835 | struct sk_buff *skb; | 835 | struct sk_buff *skb; |
| 836 | dma_addr_t mapping; | 836 | dma_addr_t mapping; |
| 837 | 837 | ||
| 838 | skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC); | 838 | skb = dev_alloc_skb(q->rx_buffer_size); |
| 839 | if (!skb) | 839 | if (!skb) |
| 840 | break; | 840 | break; |
| 841 | 841 | ||
| @@ -1046,11 +1046,10 @@ static inline struct sk_buff *get_packet(struct pci_dev *pdev, · 204 unmodified lines | |||
| 1046 | const struct freelQ_ce *ce = &fl->centries[fl->cidx]; | 1046 | const struct freelQ_ce *ce = &fl->centries[fl->cidx]; |
| 1047 | 1047 | ||
| 1048 | if (len < copybreak) { | 1048 | if (len < copybreak) { |
| 1049 | skb = alloc_skb(len + 2, GFP_ATOMIC); | 1049 | skb = netdev_alloc_skb_ip_align(NULL, len); |
| 1050 | if (!skb) | 1050 | if (!skb) |
| 1051 | goto use_orig_buf; | 1051 | goto use_orig_buf; |
| 1052 | 1052 | ||
| 1053 | skb_reserve(skb, 2); /* align IP header */ | ||
| 1054 | skb_put(skb, len); | 1053 | skb_put(skb, len); |
| 1055 | pci_dma_sync_single_for_cpu(pdev, | 1054 | pci_dma_sync_single_for_cpu(pdev, |
| 1056 | dma_unmap_addr(ce, dma_addr), | 1055 | dma_unmap_addr(ce, dma_addr), |
| @@ -1387,7 +1386,7 @@ static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len) · 330 unmodified lines | |||
| 1387 | 1386 | ||
| 1388 | if (p->vlan_valid) { | 1387 | if (p->vlan_valid) { |
| 1389 | st->vlan_xtract++; | 1388 | st->vlan_xtract++; |
| 1390 | __vlan_hwaccel_put_tag(skb, ntohs(p->vlan)); | 1389 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(p->vlan)); |
| 1391 | } | 1390 | } |
| 1392 | netif_receive_skb(skb); | 1391 | netif_receive_skb(skb); |
| 1393 | } | 1392 | } |
| @@ -1181,14 +1181,15 @@ static void cxgb_vlan_mode(struct net_device *dev, netdev_features_t features) · 1180 unmodified lines | |||
| 1181 | 1181 | ||
| 1182 | if (adapter->params.rev > 0) { | 1182 | if (adapter->params.rev > 0) { |
| 1183 | t3_set_vlan_accel(adapter, 1 << pi->port_id, | 1183 | t3_set_vlan_accel(adapter, 1 << pi->port_id, |
| 1184 | features & NETIF_F_HW_VLAN_RX); | 1184 | features & NETIF_F_HW_VLAN_CTAG_RX); |
| 1185 | } else { | 1185 | } else { |
| 1186 | /* single control for all ports */ | 1186 | /* single control for all ports */ |
| 1187 | unsigned int i, have_vlans = features & NETIF_F_HW_VLAN_RX; | 1187 | unsigned int i, have_vlans = features & NETIF_F_HW_VLAN_CTAG_RX; |
| 1188 | 1188 | ||
| 1189 | for_each_port(adapter, i) | 1189 | for_each_port(adapter, i) |
| 1190 | have_vlans |= | 1190 | have_vlans |= |
| 1191 | adapter->port[i]->features & NETIF_F_HW_VLAN_RX; | 1191 | adapter->port[i]->features & |
| 1192 | NETIF_F_HW_VLAN_CTAG_RX; | ||
| 1192 | 1193 | ||
| 1193 | t3_set_vlan_accel(adapter, 1, have_vlans); | 1194 | t3_set_vlan_accel(adapter, 1, have_vlans); |
| 1194 | } | 1195 | } |
| @@ -2563,10 +2564,10 @@ static netdev_features_t cxgb_fix_features(struct net_device *dev, · 1368 unmodified lines | |||
| 2563 | * Since there is no support for separate rx/tx vlan accel | 2564 | * Since there is no support for separate rx/tx vlan accel |
| 2564 | * enable/disable make sure tx flag is always in same state as rx. | 2565 | * enable/disable make sure tx flag is always in same state as rx. |
| 2565 | */ | 2566 | */ |
| 2566 | if (features & NETIF_F_HW_VLAN_RX) | 2567 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 2567 | features |= NETIF_F_HW_VLAN_TX; | 2568 | features |= NETIF_F_HW_VLAN_CTAG_TX; |
| 2568 | else | 2569 | else |
| 2569 | features &= ~NETIF_F_HW_VLAN_TX; | 2570 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 2570 | 2571 | ||
| 2571 | return features; | 2572 | return features; |
| 2572 | } | 2573 | } |
| @@ -2575,7 +2576,7 @@ static int cxgb_set_features(struct net_device *dev, netdev_features_t features) · 2 unmodified lines | |||
| 2575 | { | 2576 | { |
| 2576 | netdev_features_t changed = dev->features ^ features; | 2577 | netdev_features_t changed = dev->features ^ features; |
| 2577 | 2578 | ||
| 2578 | if (changed & NETIF_F_HW_VLAN_RX) | 2579 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
| 2579 | cxgb_vlan_mode(dev, features); | 2580 | cxgb_vlan_mode(dev, features); |
| 2580 | 2581 | ||
| 2581 | return 0; | 2582 | return 0; |
| @@ -3288,8 +3289,9 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 706 unmodified lines | |||
| 3288 | netdev->mem_start = mmio_start; | 3289 | netdev->mem_start = mmio_start; |
| 3289 | netdev->mem_end = mmio_start + mmio_len - 1; | 3290 | netdev->mem_end = mmio_start + mmio_len - 1; |
| 3290 | netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | | 3291 | netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | |
| 3291 | NETIF_F_TSO | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX; | 3292 | NETIF_F_TSO | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX; |
| 3292 | netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_TX; | 3293 | netdev->features |= netdev->hw_features | |
| 3294 | NETIF_F_HW_VLAN_CTAG_TX; | ||
| 3293 | netdev->vlan_features |= netdev->features & VLAN_FEAT; | 3295 | netdev->vlan_features |= netdev->features & VLAN_FEAT; |
| 3294 | if (pci_using_dac) | 3296 | if (pci_using_dac) |
| 3295 | netdev->features |= NETIF_F_HIGHDMA; | 3297 | netdev->features |= NETIF_F_HIGHDMA; |
| @@ -185,7 +185,7 @@ static struct net_device *get_iff_from_mac(struct adapter *adapter, · 184 unmodified lines | |||
| 185 | if (!memcmp(dev->dev_addr, mac, ETH_ALEN)) { | 185 | if (!memcmp(dev->dev_addr, mac, ETH_ALEN)) { |
| 186 | rcu_read_lock(); | 186 | rcu_read_lock(); |
| 187 | if (vlan && vlan != VLAN_VID_MASK) { | 187 | if (vlan && vlan != VLAN_VID_MASK) { |
| 188 | dev = __vlan_find_dev_deep(dev, vlan); | 188 | dev = __vlan_find_dev_deep(dev, htons(ETH_P_8021Q), vlan); |
| 189 | } else if (netif_is_bond_slave(dev)) { | 189 | } else if (netif_is_bond_slave(dev)) { |
| 190 | struct net_device *upper_dev; | 190 | struct net_device *upper_dev; |
| 191 | 191 | ||
| @@ -2030,7 +2030,7 @@ static void rx_eth(struct adapter *adap, struct sge_rspq *rq, · 2029 unmodified lines | |||
| 2030 | 2030 | ||
| 2031 | if (p->vlan_valid) { | 2031 | if (p->vlan_valid) { |
| 2032 | qs->port_stats[SGE_PSTAT_VLANEX]++; | 2032 | qs->port_stats[SGE_PSTAT_VLANEX]++; |
| 2033 | __vlan_hwaccel_put_tag(skb, ntohs(p->vlan)); | 2033 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(p->vlan)); |
| 2034 | } | 2034 | } |
| 2035 | if (rq->polling) { | 2035 | if (rq->polling) { |
| 2036 | if (lro) | 2036 | if (lro) |
| @@ -2132,7 +2132,7 @@ static void lro_add_page(struct adapter *adap, struct sge_qset *qs, · 95 unmodified lines | |||
| 2132 | 2132 | ||
| 2133 | if (cpl->vlan_valid) { | 2133 | if (cpl->vlan_valid) { |
| 2134 | qs->port_stats[SGE_PSTAT_VLANEX]++; | 2134 | qs->port_stats[SGE_PSTAT_VLANEX]++; |
| 2135 | __vlan_hwaccel_put_tag(skb, ntohs(cpl->vlan)); | 2135 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cpl->vlan)); |
| 2136 | } | 2136 | } |
| 2137 | napi_gro_frags(&qs->napi); | 2137 | napi_gro_frags(&qs->napi); |
| 2138 | } | 2138 | } |
| @@ -54,6 +54,10 @@ · 53 unmodified lines | |||
| 54 | #define FW_VERSION_MINOR 1 | 54 | #define FW_VERSION_MINOR 1 |
| 55 | #define FW_VERSION_MICRO 0 | 55 | #define FW_VERSION_MICRO 0 |
| 56 | 56 | ||
| 57 | #define FW_VERSION_MAJOR_T5 0 | ||
| 58 | #define FW_VERSION_MINOR_T5 0 | ||
| 59 | #define FW_VERSION_MICRO_T5 0 | ||
| 60 | |||
| 57 | #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) | 61 | #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) |
| 58 | 62 | ||
| 59 | enum { | 63 | enum { |
| @@ -66,7 +70,9 @@ enum { · 6 unmodified lines | |||
| 66 | enum { | 70 | enum { |
| 67 | MEM_EDC0, | 71 | MEM_EDC0, |
| 68 | MEM_EDC1, | 72 | MEM_EDC1, |
| 69 | MEM_MC | 73 | MEM_MC, |
| 74 | MEM_MC0 = MEM_MC, | ||
| 75 | MEM_MC1 | ||
| 70 | }; | 76 | }; |
| 71 | 77 | ||
| 72 | enum { | 78 | enum { |
| @@ -74,8 +80,10 @@ enum { · 1 unmodified line | |||
| 74 | MEMWIN0_BASE = 0x1b800, | 80 | MEMWIN0_BASE = 0x1b800, |
| 75 | MEMWIN1_APERTURE = 32768, | 81 | MEMWIN1_APERTURE = 32768, |
| 76 | MEMWIN1_BASE = 0x28000, | 82 | MEMWIN1_BASE = 0x28000, |
| 83 | MEMWIN1_BASE_T5 = 0x52000, | ||
| 77 | MEMWIN2_APERTURE = 65536, | 84 | MEMWIN2_APERTURE = 65536, |
| 78 | MEMWIN2_BASE = 0x30000, | 85 | MEMWIN2_BASE = 0x30000, |
| 86 | MEMWIN2_BASE_T5 = 0x54000, | ||
| 79 | }; | 87 | }; |
| 80 | 88 | ||
| 81 | enum dev_master { | 89 | enum dev_master { |
| @@ -431,6 +439,7 @@ struct sge_txq { · 349 unmodified lines | |||
| 431 | spinlock_t db_lock; | 439 | spinlock_t db_lock; |
| 432 | int db_disabled; | 440 | int db_disabled; |
| 433 | unsigned short db_pidx; | 441 | unsigned short db_pidx; |
| 442 | u64 udb; | ||
| 434 | }; | 443 | }; |
| 435 | 444 | ||
| 436 | struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ | 445 | struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ |
| @@ -504,13 +513,44 @@ struct sge { · 67 unmodified lines | |||
| 504 | 513 | ||
| 505 | struct l2t_data; | 514 | struct l2t_data; |
| 506 | 515 | ||
| 516 | #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) | ||
| 517 | #define CHELSIO_CHIP_VERSION(code) ((code) >> 4) | ||
| 518 | #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) | ||
| 519 | |||
| 520 | #define CHELSIO_T4 0x4 | ||
| 521 | #define CHELSIO_T5 0x5 | ||
| 522 | |||
| 523 | enum chip_type { | ||
| 524 | T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 0), | ||
| 525 | T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), | ||
| 526 | T4_A3 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), | ||
| 527 | T4_FIRST_REV = T4_A1, | ||
| 528 | T4_LAST_REV = T4_A3, | ||
| 529 | |||
| 530 | T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), | ||
| 531 | T5_FIRST_REV = T5_A1, | ||
| 532 | T5_LAST_REV = T5_A1, | ||
| 533 | }; | ||
| 534 | |||
| 535 | #ifdef CONFIG_PCI_IOV | ||
| 536 | |||
| 537 | /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial | ||
| 538 | * Configuration initialization for T5 only has SR-IOV functionality enabled | ||
| 539 | * on PF0-3 in order to simplify everything. | ||
| 540 | */ | ||
| 541 | #define NUM_OF_PF_WITH_SRIOV 4 | ||
| 542 | |||
| 543 | #endif | ||
| 544 | |||
| 507 | struct adapter { | 545 | struct adapter { |
| 508 | void __iomem *regs; | 546 | void __iomem *regs; |
| 547 | void __iomem *bar2; | ||
| 509 | struct pci_dev *pdev; | 548 | struct pci_dev *pdev; |
| 510 | struct device *pdev_dev; | 549 | struct device *pdev_dev; |
| 511 | unsigned int mbox; | 550 | unsigned int mbox; |
| 512 | unsigned int fn; | 551 | unsigned int fn; |
| 513 | unsigned int flags; | 552 | unsigned int flags; |
| 553 | enum chip_type chip; | ||
| 514 | 554 | ||
| 515 | int msg_enable; | 555 | int msg_enable; |
| 516 | 556 | ||
| @@ -673,6 +713,16 @@ enum { · 156 unmodified lines | |||
| 673 | VLAN_REWRITE | 713 | VLAN_REWRITE |
| 674 | }; | 714 | }; |
| 675 | 715 | ||
| 716 | static inline int is_t5(enum chip_type chip) | ||
| 717 | { | ||
| 718 | return (chip >= T5_FIRST_REV && chip <= T5_LAST_REV); | ||
| 719 | } | ||
| 720 | |||
| 721 | static inline int is_t4(enum chip_type chip) | ||
| 722 | { | ||
| 723 | return (chip >= T4_FIRST_REV && chip <= T4_LAST_REV); | ||
| 724 | } | ||
| 725 | |||
| 676 | static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) | 726 | static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) |
| 677 | { | 727 | { |
| 678 | return readl(adap->regs + reg_addr); | 728 | return readl(adap->regs + reg_addr); |
| @@ -858,7 +908,8 @@ int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, · 179 unmodified lines | |||
| 858 | int start, int n, const u16 *rspq, unsigned int nrspq); | 908 | int start, int n, const u16 *rspq, unsigned int nrspq); |
| 859 | int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, | 909 | int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, |
| 860 | unsigned int flags); | 910 | unsigned int flags); |
| 861 | int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity); | 911 | int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, |
| 912 | u64 *parity); | ||
| 862 | int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, | 913 | int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, |
| 863 | u64 *parity); | 914 | u64 *parity); |
| 864 | 915 | ||
| @@ -68,8 +68,8 @@ · 67 unmodified lines | |||
| 68 | #include "t4fw_api.h" | 68 | #include "t4fw_api.h" |
| 69 | #include "l2t.h" | 69 | #include "l2t.h" |
| 70 | 70 | ||
| 71 | #define DRV_VERSION "1.3.0-ko" | 71 | #define DRV_VERSION "2.0.0-ko" |
| 72 | #define DRV_DESC "Chelsio T4 Network Driver" | 72 | #define DRV_DESC "Chelsio T4/T5 Network Driver" |
| 73 | 73 | ||
| 74 | /* | 74 | /* |
| 75 | * Max interrupt hold-off timer value in us. Queues fall back to this value | 75 | * Max interrupt hold-off timer value in us. Queues fall back to this value |
| @@ -229,11 +229,51 @@ static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl) = { · 153 unmodified lines | |||
| 229 | CH_DEVICE(0x440a, 4), | 229 | CH_DEVICE(0x440a, 4), |
| 230 | CH_DEVICE(0x440d, 4), | 230 | CH_DEVICE(0x440d, 4), |
| 231 | CH_DEVICE(0x440e, 4), | 231 | CH_DEVICE(0x440e, 4), |
| 232 | CH_DEVICE(0x5001, 4), | ||
| 233 | CH_DEVICE(0x5002, 4), | ||
| 234 | CH_DEVICE(0x5003, 4), | ||
| 235 | CH_DEVICE(0x5004, 4), | ||
| 236 | CH_DEVICE(0x5005, 4), | ||
| 237 | CH_DEVICE(0x5006, 4), | ||
| 238 | CH_DEVICE(0x5007, 4), | ||
| 239 | CH_DEVICE(0x5008, 4), | ||
| 240 | CH_DEVICE(0x5009, 4), | ||
| 241 | CH_DEVICE(0x500A, 4), | ||
| 242 | CH_DEVICE(0x500B, 4), | ||
| 243 | CH_DEVICE(0x500C, 4), | ||
| 244 | CH_DEVICE(0x500D, 4), | ||
| 245 | CH_DEVICE(0x500E, 4), | ||
| 246 | CH_DEVICE(0x500F, 4), | ||
| 247 | CH_DEVICE(0x5010, 4), | ||
| 248 | CH_DEVICE(0x5011, 4), | ||
| 249 | CH_DEVICE(0x5012, 4), | ||
| 250 | CH_DEVICE(0x5013, 4), | ||
| 251 | CH_DEVICE(0x5401, 4), | ||
| 252 | CH_DEVICE(0x5402, 4), | ||
| 253 | CH_DEVICE(0x5403, 4), | ||
| 254 | CH_DEVICE(0x5404, 4), | ||
| 255 | CH_DEVICE(0x5405, 4), | ||
| 256 | CH_DEVICE(0x5406, 4), | ||
| 257 | CH_DEVICE(0x5407, 4), | ||
| 258 | CH_DEVICE(0x5408, 4), | ||
| 259 | CH_DEVICE(0x5409, 4), | ||
| 260 | CH_DEVICE(0x540A, 4), | ||
| 261 | CH_DEVICE(0x540B, 4), | ||
| 262 | CH_DEVICE(0x540C, 4), | ||
| 263 | CH_DEVICE(0x540D, 4), | ||
| 264 | CH_DEVICE(0x540E, 4), | ||
| 265 | CH_DEVICE(0x540F, 4), | ||
| 266 | CH_DEVICE(0x5410, 4), | ||
| 267 | CH_DEVICE(0x5411, 4), | ||
| 268 | CH_DEVICE(0x5412, 4), | ||
| 269 | CH_DEVICE(0x5413, 4), | ||
| 232 | { 0, } | 270 | { 0, } |
| 233 | }; | 271 | }; |
| 234 | 272 | ||
| 235 | #define FW_FNAME "cxgb4/t4fw.bin" | 273 | #define FW_FNAME "cxgb4/t4fw.bin" |
| 274 | #define FW5_FNAME "cxgb4/t5fw.bin" | ||
| 236 | #define FW_CFNAME "cxgb4/t4-config.txt" | 275 | #define FW_CFNAME "cxgb4/t4-config.txt" |
| 276 | #define FW5_CFNAME "cxgb4/t5-config.txt" | ||
| 237 | 277 | ||
| 238 | MODULE_DESCRIPTION(DRV_DESC); | 278 | MODULE_DESCRIPTION(DRV_DESC); |
| 239 | MODULE_AUTHOR("Chelsio Communications"); | 279 | MODULE_AUTHOR("Chelsio Communications"); |
| @@ -241,6 +281,7 @@ MODULE_LICENSE("Dual BSD/GPL"); · 1 unmodified line | |||
| 241 | MODULE_VERSION(DRV_VERSION); | 281 | MODULE_VERSION(DRV_VERSION); |
| 242 | MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); | 282 | MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); |
| 243 | MODULE_FIRMWARE(FW_FNAME); | 283 | MODULE_FIRMWARE(FW_FNAME); |
| 284 | MODULE_FIRMWARE(FW5_FNAME); | ||
| 244 | 285 | ||
| 245 | /* | 286 | /* |
| 246 | * Normally we're willing to become the firmware's Master PF but will be happy | 287 | * Normally we're willing to become the firmware's Master PF but will be happy |
| @@ -319,7 +360,10 @@ static bool vf_acls; · 72 unmodified lines | |||
| 319 | module_param(vf_acls, bool, 0644); | 360 | module_param(vf_acls, bool, 0644); |
| 320 | MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement"); | 361 | MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement"); |
| 321 | 362 | ||
| 322 | static unsigned int num_vf[4]; | 363 | /* Configure the number of PCI-E Virtual Function which are to be instantiated |
| 364 | * on SR-IOV Capable Physical Functions. | ||
| 365 | */ | ||
| 366 | static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV]; | ||
| 323 | 367 | ||
| 324 | module_param_array(num_vf, uint, NULL, 0644); | 368 | module_param_array(num_vf, uint, NULL, 0644); |
| 325 | MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3"); | 369 | MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3"); |
| @@ -515,7 +559,7 @@ static int link_start(struct net_device *dev) · 189 unmodified lines | |||
| 515 | * that step explicitly. | 559 | * that step explicitly. |
| 516 | */ | 560 | */ |
| 517 | ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, | 561 | ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, |
| 518 | !!(dev->features & NETIF_F_HW_VLAN_RX), true); | 562 | !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); |
| 519 | if (ret == 0) { | 563 | if (ret == 0) { |
| 520 | ret = t4_change_mac(pi->adapter, mb, pi->viid, | 564 | ret = t4_change_mac(pi->adapter, mb, pi->viid, |
| 521 | pi->xact_addr_filt, dev->dev_addr, true, | 565 | pi->xact_addr_filt, dev->dev_addr, true, |
| @@ -601,6 +645,21 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, · 79 unmodified lines | |||
| 601 | u8 opcode = ((const struct rss_header *)rsp)->opcode; | 645 | u8 opcode = ((const struct rss_header *)rsp)->opcode; |
| 602 | 646 | ||
| 603 | rsp++; /* skip RSS header */ | 647 | rsp++; /* skip RSS header */ |
| 648 | |||
| 649 | /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. | ||
| 650 | */ | ||
| 651 | if (unlikely(opcode == CPL_FW4_MSG && | ||
| 652 | ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { | ||
| 653 | rsp++; | ||
| 654 | opcode = ((const struct rss_header *)rsp)->opcode; | ||
| 655 | rsp++; | ||
| 656 | if (opcode != CPL_SGE_EGR_UPDATE) { | ||
| 657 | dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" | ||
| 658 | , opcode); | ||
| 659 | goto out; | ||
| 660 | } | ||
| 661 | } | ||
| 662 | |||
| 604 | if (likely(opcode == CPL_SGE_EGR_UPDATE)) { | 663 | if (likely(opcode == CPL_SGE_EGR_UPDATE)) { |
| 605 | const struct cpl_sge_egr_update *p = (void *)rsp; | 664 | const struct cpl_sge_egr_update *p = (void *)rsp; |
| 606 | unsigned int qid = EGR_QID(ntohl(p->opcode_qid)); | 665 | unsigned int qid = EGR_QID(ntohl(p->opcode_qid)); |
| @@ -635,6 +694,7 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, · 28 unmodified lines | |||
| 635 | } else | 694 | } else |
| 636 | dev_err(q->adap->pdev_dev, | 695 | dev_err(q->adap->pdev_dev, |
| 637 | "unexpected CPL %#x on FW event queue\n", opcode); | 696 | "unexpected CPL %#x on FW event queue\n", opcode); |
| 697 | out: | ||
| 638 | return 0; | 698 | return 0; |
| 639 | } | 699 | } |
| 640 | 700 | ||
| @@ -652,6 +712,12 @@ static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp, · 11 unmodified lines | |||
| 652 | { | 712 | { |
| 653 | struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq); | 713 | struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq); |
| 654 | 714 | ||
| 715 | /* FW can send CPLs encapsulated in a CPL_FW4_MSG. | ||
| 716 | */ | ||
| 717 | if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG && | ||
| 718 | ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL) | ||
| 719 | rsp += 2; | ||
| 720 | |||
| 655 | if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) { | 721 | if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) { |
| 656 | rxq->stats.nomem++; | 722 | rxq->stats.nomem++; |
| 657 | return -1; | 723 | return -1; |
| @@ -1002,21 +1068,36 @@ freeout: t4_free_sge_resources(adap); · 344 unmodified lines | |||
| 1002 | static int upgrade_fw(struct adapter *adap) | 1068 | static int upgrade_fw(struct adapter *adap) |
| 1003 | { | 1069 | { |
| 1004 | int ret; | 1070 | int ret; |
| 1005 | u32 vers; | 1071 | u32 vers, exp_major; |
| 1006 | const struct fw_hdr *hdr; | 1072 | const struct fw_hdr *hdr; |
| 1007 | const struct firmware *fw; | 1073 | const struct firmware *fw; |
| 1008 | struct device *dev = adap->pdev_dev; | 1074 | struct device *dev = adap->pdev_dev; |
| 1075 | char *fw_file_name; | ||
| 1009 | 1076 | ||
| 1010 | ret = request_firmware(&fw, FW_FNAME, dev); | 1077 | switch (CHELSIO_CHIP_VERSION(adap->chip)) { |
| 1078 | case CHELSIO_T4: | ||
| 1079 | fw_file_name = FW_FNAME; | ||
| 1080 | exp_major = FW_VERSION_MAJOR; | ||
| 1081 | break; | ||
| 1082 | case CHELSIO_T5: | ||
| 1083 | fw_file_name = FW5_FNAME; | ||
| 1084 | exp_major = FW_VERSION_MAJOR_T5; | ||
| 1085 | break; | ||
| 1086 | default: | ||
| 1087 | dev_err(dev, "Unsupported chip type, %x\n", adap->chip); | ||
| 1088 | return -EINVAL; | ||
| 1089 | } | ||
| 1090 | |||
| 1091 | ret = request_firmware(&fw, fw_file_name, dev); | ||
| 1011 | if (ret < 0) { | 1092 | if (ret < 0) { |
| 1012 | dev_err(dev, "unable to load firmware image " FW_FNAME | 1093 | dev_err(dev, "unable to load firmware image %s, error %d\n", |
| 1013 | ", error %d\n", ret); | 1094 | fw_file_name, ret); |
| 1014 | return ret; | 1095 | return ret; |
| 1015 | } | 1096 | } |
| 1016 | 1097 | ||
| 1017 | hdr = (const struct fw_hdr *)fw->data; | 1098 | hdr = (const struct fw_hdr *)fw->data; |
| 1018 | vers = ntohl(hdr->fw_ver); | 1099 | vers = ntohl(hdr->fw_ver); |
| 1019 | if (FW_HDR_FW_VER_MAJOR_GET(vers) != FW_VERSION_MAJOR) { | 1100 | if (FW_HDR_FW_VER_MAJOR_GET(vers) != exp_major) { |
| 1020 | ret = -EINVAL; /* wrong major version, won't do */ | 1101 | ret = -EINVAL; /* wrong major version, won't do */ |
| 1021 | goto out; | 1102 | goto out; |
| 1022 | } | 1103 | } |
| @@ -1024,18 +1105,15 @@ static int upgrade_fw(struct adapter *adap) · 1 unmodified line | |||
| 1024 | /* | 1105 | /* |
| 1025 | * If the flash FW is unusable or we found something newer, load it. | 1106 | * If the flash FW is unusable or we found something newer, load it. |
| 1026 | */ | 1107 | */ |
| 1027 | if (FW_HDR_FW_VER_MAJOR_GET(adap->params.fw_vers) != FW_VERSION_MAJOR || | 1108 | if (FW_HDR_FW_VER_MAJOR_GET(adap->params.fw_vers) != exp_major || |
| 1028 | vers > adap->params.fw_vers) { | 1109 | vers > adap->params.fw_vers) { |
| 1029 | dev_info(dev, "upgrading firmware ...\n"); | 1110 | dev_info(dev, "upgrading firmware ...\n"); |
| 1030 | ret = t4_fw_upgrade(adap, adap->mbox, fw->data, fw->size, | 1111 | ret = t4_fw_upgrade(adap, adap->mbox, fw->data, fw->size, |
| 1031 | /*force=*/false); | 1112 | /*force=*/false); |
| 1032 | if (!ret) | 1113 | if (!ret) |
| 1033 | dev_info(dev, "firmware successfully upgraded to " | 1114 | dev_info(dev, |
| 1034 | FW_FNAME " (%d.%d.%d.%d)\n", | 1115 | "firmware upgraded to version %pI4 from %s\n", |
| 1035 | FW_HDR_FW_VER_MAJOR_GET(vers), | 1116 | &hdr->fw_ver, fw_file_name); |
| 1036 | FW_HDR_FW_VER_MINOR_GET(vers), | ||
| 1037 | FW_HDR_FW_VER_MICRO_GET(vers), | ||
| 1038 | FW_HDR_FW_VER_BUILD_GET(vers)); | ||
| 1039 | else | 1117 | else |
| 1040 | dev_err(dev, "firmware upgrade failed! err=%d\n", -ret); | 1118 | dev_err(dev, "firmware upgrade failed! err=%d\n", -ret); |
| 1041 | } else { | 1119 | } else { |
| @@ -1308,6 +1386,8 @@ static char stats_strings[][ETH_GSTRING_LEN] = { · 266 unmodified lines | |||
| 1308 | "VLANinsertions ", | 1386 | "VLANinsertions ", |
| 1309 | "GROpackets ", | 1387 | "GROpackets ", |
| 1310 | "GROmerged ", | 1388 | "GROmerged ", |
| 1389 | "WriteCoalSuccess ", | ||
| 1390 | "WriteCoalFail ", | ||
| 1311 | }; | 1391 | }; |
| 1312 | 1392 | ||
| 1313 | static int get_sset_count(struct net_device *dev, int sset) | 1393 | static int get_sset_count(struct net_device *dev, int sset) |
| @@ -1321,10 +1401,15 @@ static int get_sset_count(struct net_device *dev, int sset) · 7 unmodified lines | |||
| 1321 | } | 1401 | } |
| 1322 | 1402 | ||
| 1323 | #define T4_REGMAP_SIZE (160 * 1024) | 1403 | #define T4_REGMAP_SIZE (160 * 1024) |
| 1404 | #define T5_REGMAP_SIZE (332 * 1024) | ||
| 1324 | 1405 | ||
| 1325 | static int get_regs_len(struct net_device *dev) | 1406 | static int get_regs_len(struct net_device *dev) |
| 1326 | { | 1407 | { |
| 1327 | return T4_REGMAP_SIZE; | 1408 | struct adapter *adap = netdev2adap(dev); |
| 1409 | if (is_t4(adap->chip)) | ||
| 1410 | return T4_REGMAP_SIZE; | ||
| 1411 | else | ||
| 1412 | return T5_REGMAP_SIZE; | ||
| 1328 | } | 1413 | } |
| 1329 | 1414 | ||
| 1330 | static int get_eeprom_len(struct net_device *dev) | 1415 | static int get_eeprom_len(struct net_device *dev) |
| @@ -1398,11 +1483,25 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats, · 67 unmodified lines | |||
| 1398 | { | 1483 | { |
| 1399 | struct port_info *pi = netdev_priv(dev); | 1484 | struct port_info *pi = netdev_priv(dev); |
| 1400 | struct adapter *adapter = pi->adapter; | 1485 | struct adapter *adapter = pi->adapter; |
| 1486 | u32 val1, val2; | ||
| 1401 | 1487 | ||
| 1402 | t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data); | 1488 | t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data); |
| 1403 | 1489 | ||
| 1404 | data += sizeof(struct port_stats) / sizeof(u64); | 1490 | data += sizeof(struct port_stats) / sizeof(u64); |
| 1405 | collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data); | 1491 | collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data); |
| 1492 | data += sizeof(struct queue_port_stats) / sizeof(u64); | ||
| 1493 | if (!is_t4(adapter->chip)) { | ||
| 1494 | t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7)); | ||
| 1495 | val1 = t4_read_reg(adapter, SGE_STAT_TOTAL); | ||
| 1496 | val2 = t4_read_reg(adapter, SGE_STAT_MATCH); | ||
| 1497 | *data = val1 - val2; | ||
| 1498 | data++; | ||
| 1499 | *data = val2; | ||
| 1500 | data++; | ||
| 1501 | } else { | ||
| 1502 | memset(data, 0, 2 * sizeof(u64)); | ||
| 1503 | *data += 2; | ||
| 1504 | } | ||
| 1406 | } | 1505 | } |
| 1407 | 1506 | ||
| 1408 | /* | 1507 | /* |
| @@ -1413,7 +1512,8 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats, · 4 unmodified lines | |||
| 1413 | */ | 1512 | */ |
| 1414 | static inline unsigned int mk_adap_vers(const struct adapter *ap) | 1513 | static inline unsigned int mk_adap_vers(const struct adapter *ap) |
| 1415 | { | 1514 | { |
| 1416 | return 4 | (ap->params.rev << 10) | (1 << 16); | 1515 | return CHELSIO_CHIP_VERSION(ap->chip) | |
| 1516 | (CHELSIO_CHIP_RELEASE(ap->chip) << 10) | (1 << 16); | ||
| 1417 | } | 1517 | } |
| 1418 | 1518 | ||
| 1419 | static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start, | 1519 | static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start, |
| @@ -1428,7 +1528,7 @@ static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start, · 8 unmodified lines | |||
| 1428 | static void get_regs(struct net_device *dev, struct ethtool_regs *regs, | 1528 | static void get_regs(struct net_device *dev, struct ethtool_regs *regs, |
| 1429 | void *buf) | 1529 | void *buf) |
| 1430 | { | 1530 | { |
| 1431 | static const unsigned int reg_ranges[] = { | 1531 | static const unsigned int t4_reg_ranges[] = { |
| 1432 | 0x1008, 0x1108, | 1532 | 0x1008, 0x1108, |
| 1433 | 0x1180, 0x11b4, | 1533 | 0x1180, 0x11b4, |
| 1434 | 0x11fc, 0x123c, | 1534 | 0x11fc, 0x123c, |
| @@ -1648,13 +1748,452 @@ static void get_regs(struct net_device *dev, struct ethtool_regs *regs, · 213 unmodified lines | |||
| 1648 | 0x27e00, 0x27e04 | 1748 | 0x27e00, 0x27e04 |
| 1649 | }; | 1749 | }; |
| 1650 | 1750 | ||
| 1751 | static const unsigned int t5_reg_ranges[] = { | ||
| 1752 | 0x1008, 0x1148, | ||
| 1753 | 0x1180, 0x11b4, | ||
| 1754 | 0x11fc, 0x123c, | ||
| 1755 | 0x1280, 0x173c, | ||
| 1756 | 0x1800, 0x18fc, | ||
| 1757 | 0x3000, 0x3028, | ||
| 1758 | 0x3060, 0x30d8, | ||
| 1759 | 0x30e0, 0x30fc, | ||
| 1760 | 0x3140, 0x357c, | ||
| 1761 | 0x35a8, 0x35cc, | ||
| 1762 | 0x35ec, 0x35ec, | ||
| 1763 | 0x3600, 0x5624, | ||
| 1764 | 0x56cc, 0x575c, | ||
| 1765 | 0x580c, 0x5814, | ||
| 1766 | 0x5890, 0x58bc, | ||
| 1767 | 0x5940, 0x59dc, | ||
| 1768 | 0x59fc, 0x5a18, | ||
| 1769 | 0x5a60, 0x5a9c, | ||
| 1770 | 0x5b9c, 0x5bfc, | ||
| 1771 | 0x6000, 0x6040, | ||
| 1772 | 0x6058, 0x614c, | ||
| 1773 | 0x7700, 0x7798, | ||
| 1774 | 0x77c0, 0x78fc, | ||
| 1775 | 0x7b00, 0x7c54, | ||
| 1776 | 0x7d00, 0x7efc, | ||
| 1777 | 0x8dc0, 0x8de0, | ||
| 1778 | 0x8df8, 0x8e84, | ||
| 1779 | 0x8ea0, 0x8f84, | ||
| 1780 | 0x8fc0, 0x90f8, | ||
| 1781 | 0x9400, 0x9470, | ||
| 1782 | 0x9600, 0x96f4, | ||
| 1783 | 0x9800, 0x9808, | ||
| 1784 | 0x9820, 0x983c, | ||
| 1785 | 0x9850, 0x9864, | ||
| 1786 | 0x9c00, 0x9c6c, | ||
| 1787 | 0x9c80, 0x9cec, | ||
| 1788 | 0x9d00, 0x9d6c, | ||
| 1789 | 0x9d80, 0x9dec, | ||
| 1790 | 0x9e00, 0x9e6c, | ||
| 1791 | 0x9e80, 0x9eec, | ||
| 1792 | 0x9f00, 0x9f6c, | ||
| 1793 | 0x9f80, 0xa020, | ||
| 1794 | 0xd004, 0xd03c, | ||
| 1795 | 0xdfc0, 0xdfe0, | ||
| 1796 | 0xe000, 0x11088, | ||
| 1797 | 0x1109c, 0x1117c, | ||
| 1798 | 0x11190, 0x11204, | ||
| 1799 | 0x19040, 0x1906c, | ||
| 1800 | 0x19078, 0x19080, | ||
| 1801 | 0x1908c, 0x19124, | ||
| 1802 | 0x19150, 0x191b0, | ||
| 1803 | 0x191d0, 0x191e8, | ||
| 1804 | 0x19238, 0x19290, | ||
| 1805 | 0x193f8, 0x19474, | ||
| 1806 | 0x19490, 0x194cc, | ||
| 1807 | 0x194f0, 0x194f8, | ||
| 1808 | 0x19c00, 0x19c60, | ||
| 1809 | 0x19c94, 0x19e10, | ||
| 1810 | 0x19e50, 0x19f34, | ||
| 1811 | 0x19f40, 0x19f50, | ||
| 1812 | 0x19f90, 0x19fe4, | ||
| 1813 | 0x1a000, 0x1a06c, | ||
| 1814 | 0x1a0b0, 0x1a120, | ||
| 1815 | 0x1a128, 0x1a138, | ||
| 1816 | 0x1a190, 0x1a1c4, | ||
| 1817 | 0x1a1fc, 0x1a1fc, | ||
| 1818 | 0x1e008, 0x1e00c, | ||
| 1819 | 0x1e040, 0x1e04c, | ||
| 1820 | 0x1e284, 0x1e290, | ||
| 1821 | 0x1e2c0, 0x1e2c0, | ||
| 1822 | 0x1e2e0, 0x1e2e0, | ||
| 1823 | 0x1e300, 0x1e384, | ||
| 1824 | 0x1e3c0, 0x1e3c8, | ||
| 1825 | 0x1e408, 0x1e40c, | ||
| 1826 | 0x1e440, 0x1e44c, | ||
| 1827 | 0x1e684, 0x1e690, | ||
| 1828 | 0x1e6c0, 0x1e6c0, | ||
| 1829 | 0x1e6e0, 0x1e6e0, | ||
| 1830 | 0x1e700, 0x1e784, | ||
| 1831 | 0x1e7c0, 0x1e7c8, | ||
| 1832 | 0x1e808, 0x1e80c, | ||
| 1833 | 0x1e840, 0x1e84c, | ||
| 1834 | 0x1ea84, 0x1ea90, | ||
| 1835 | 0x1eac0, 0x1eac0, | ||
| 1836 | 0x1eae0, 0x1eae0, | ||
| 1837 | 0x1eb00, 0x1eb84, | ||
| 1838 | 0x1ebc0, 0x1ebc8, | ||
| 1839 | 0x1ec08, 0x1ec0c, | ||
| 1840 | 0x1ec40, 0x1ec4c, | ||
| 1841 | 0x1ee84, 0x1ee90, | ||
| 1842 | 0x1eec0, 0x1eec0, | ||
| 1843 | 0x1eee0, 0x1eee0, | ||
| 1844 | 0x1ef00, 0x1ef84, | ||
| 1845 | 0x1efc0, 0x1efc8, | ||
| 1846 | 0x1f008, 0x1f00c, | ||
| 1847 | 0x1f040, 0x1f04c, | ||
| 1848 | 0x1f284, 0x1f290, | ||
| 1849 | 0x1f2c0, 0x1f2c0, | ||
| 1850 | 0x1f2e0, 0x1f2e0, | ||
| 1851 | 0x1f300, 0x1f384, | ||
| 1852 | 0x1f3c0, 0x1f3c8, | ||
| 1853 | 0x1f408, 0x1f40c, | ||
| 1854 | 0x1f440, 0x1f44c, | ||
| 1855 | 0x1f684, 0x1f690, | ||
| 1856 | 0x1f6c0, 0x1f6c0, | ||
| 1857 | 0x1f6e0, 0x1f6e0, | ||
| 1858 | 0x1f700, 0x1f784, | ||
| 1859 | 0x1f7c0, 0x1f7c8, | ||
| 1860 | 0x1f808, 0x1f80c, | ||
| 1861 | 0x1f840, 0x1f84c, | ||
| 1862 | 0x1fa84, 0x1fa90, | ||
| 1863 | 0x1fac0, 0x1fac0, | ||
| 1864 | 0x1fae0, 0x1fae0, | ||
| 1865 | 0x1fb00, 0x1fb84, | ||
| 1866 | 0x1fbc0, 0x1fbc8, | ||
| 1867 | 0x1fc08, 0x1fc0c, | ||
| 1868 | 0x1fc40, 0x1fc4c, | ||
| 1869 | 0x1fe84, 0x1fe90, | ||
| 1870 | 0x1fec0, 0x1fec0, | ||
| 1871 | 0x1fee0, 0x1fee0, | ||
| 1872 | 0x1ff00, 0x1ff84, | ||
| 1873 | 0x1ffc0, 0x1ffc8, | ||
| 1874 | 0x30000, 0x30030, | ||
| 1875 | 0x30100, 0x30144, | ||
| 1876 | 0x30190, 0x301d0, | ||
| 1877 | 0x30200, 0x30318, | ||
| 1878 | 0x30400, 0x3052c, | ||
| 1879 | 0x30540, 0x3061c, | ||
| 1880 | 0x30800, 0x30834, | ||
| 1881 | 0x308c0, 0x30908, | ||
| 1882 | 0x30910, 0x309ac, | ||
| 1883 | 0x30a00, 0x30a04, | ||
| 1884 | 0x30a0c, 0x30a2c, | ||
| 1885 | 0x30a44, 0x30a50, | ||
| 1886 | 0x30a74, 0x30c24, | ||
| 1887 | 0x30d08, 0x30d14, | ||
| 1888 | 0x30d1c, 0x30d20, | ||
| 1889 | 0x30d3c, 0x30d50, | ||
| 1890 | 0x31200, 0x3120c, | ||
| 1891 | 0x31220, 0x31220, | ||
| 1892 | 0x31240, 0x31240, | ||
| 1893 | 0x31600, 0x31600, | ||
| 1894 | 0x31608, 0x3160c, | ||
| 1895 | 0x31a00, 0x31a1c, | ||
| 1896 | 0x31e04, 0x31e20, | ||
| 1897 | 0x31e38, 0x31e3c, | ||
| 1898 | 0x31e80, 0x31e80, | ||
| 1899 | 0x31e88, 0x31ea8, | ||
| 1900 | 0x31eb0, 0x31eb4, | ||
| 1901 | 0x31ec8, 0x31ed4, | ||
| 1902 | 0x31fb8, 0x32004, | ||
| 1903 | 0x32208, 0x3223c, | ||
| 1904 | 0x32600, 0x32630, | ||
| 1905 | 0x32a00, 0x32abc, | ||
| 1906 | 0x32b00, 0x32b70, | ||
| 1907 | 0x33000, 0x33048, | ||
| 1908 | 0x33060, 0x3309c, | ||
| 1909 | 0x330f0, 0x33148, | ||
| 1910 | 0x33160, 0x3319c, | ||
| 1911 | 0x331f0, 0x332e4, | ||
| 1912 | 0x332f8, 0x333e4, | ||
| 1913 | 0x333f8, 0x33448, | ||
| 1914 | 0x33460, 0x3349c, | ||
| 1915 | 0x334f0, 0x33548, | ||
| 1916 | 0x33560, 0x3359c, | ||
| 1917 | 0x335f0, 0x336e4, | ||
| 1918 | 0x336f8, 0x337e4, | ||
| 1919 | 0x337f8, 0x337fc, | ||
| 1920 | 0x33814, 0x33814, | ||
| 1921 | 0x3382c, 0x3382c, | ||
| 1922 | 0x33880, 0x3388c, | ||
| 1923 | 0x338e8, 0x338ec, | ||
| 1924 | 0x33900, 0x33948, | ||
| 1925 | 0x33960, 0x3399c, | ||
| 1926 | 0x339f0, 0x33ae4, | ||
| 1927 | 0x33af8, 0x33b10, | ||
| 1928 | 0x33b28, 0x33b28, | ||
| 1929 | 0x33b3c, 0x33b50, | ||
| 1930 | 0x33bf0, 0x33c10, | ||
| 1931 | 0x33c28, 0x33c28, | ||
| 1932 | 0x33c3c, 0x33c50, | ||
| 1933 | 0x33cf0, 0x33cfc, | ||
| 1934 | 0x34000, 0x34030, | ||
| 1935 | 0x34100, 0x34144, | ||
| 1936 | 0x34190, 0x341d0, | ||
| 1937 | 0x34200, 0x34318, | ||
| 1938 | 0x34400, 0x3452c, | ||
| 1939 | 0x34540, 0x3461c, | ||
| 1940 | 0x34800, 0x34834, | ||
| 1941 | 0x348c0, 0x34908, | ||
| 1942 | 0x34910, 0x349ac, | ||
| 1943 | 0x34a00, 0x34a04, | ||
| 1944 | 0x34a0c, 0x34a2c, | ||
| 1945 | 0x34a44, 0x34a50, | ||
| 1946 | 0x34a74, 0x34c24, | ||
| 1947 | 0x34d08, 0x34d14, | ||
| 1948 | 0x34d1c, 0x34d20, | ||
| 1949 | 0x34d3c, 0x34d50, | ||
| 1950 | 0x35200, 0x3520c, | ||
| 1951 | 0x35220, 0x35220, | ||
| 1952 | 0x35240, 0x35240, | ||
| 1953 | 0x35600, 0x35600, | ||
| 1954 | 0x35608, 0x3560c, | ||
| 1955 | 0x35a00, 0x35a1c, | ||
| 1956 | 0x35e04, 0x35e20, | ||
| 1957 | 0x35e38, 0x35e3c, | ||
| 1958 | 0x35e80, 0x35e80, | ||
| 1959 | 0x35e88, 0x35ea8, | ||
| 1960 | 0x35eb0, 0x35eb4, | ||
| 1961 | 0x35ec8, 0x35ed4, | ||
| 1962 | 0x35fb8, 0x36004, | ||
| 1963 | 0x36208, 0x3623c, | ||
| 1964 | 0x36600, 0x36630, | ||
| 1965 | 0x36a00, 0x36abc, | ||
| 1966 | 0x36b00, 0x36b70, | ||
| 1967 | 0x37000, 0x37048, | ||
| 1968 | 0x37060, 0x3709c, | ||
| 1969 | 0x370f0, 0x37148, | ||
| 1970 | 0x37160, 0x3719c, | ||
| 1971 | 0x371f0, 0x372e4, | ||
| 1972 | 0x372f8, 0x373e4, | ||
| 1973 | 0x373f8, 0x37448, | ||
| 1974 | 0x37460, 0x3749c, | ||
| 1975 | 0x374f0, 0x37548, | ||
| 1976 | 0x37560, 0x3759c, | ||
| 1977 | 0x375f0, 0x376e4, | ||
| 1978 | 0x376f8, 0x377e4, | ||
| 1979 | 0x377f8, 0x377fc, | ||
| 1980 | 0x37814, 0x37814, | ||
| 1981 | 0x3782c, 0x3782c, | ||
| 1982 | 0x37880, 0x3788c, | ||
| 1983 | 0x378e8, 0x378ec, | ||
| 1984 | 0x37900, 0x37948, | ||
| 1985 | 0x37960, 0x3799c, | ||
| 1986 | 0x379f0, 0x37ae4, | ||
| 1987 | 0x37af8, 0x37b10, | ||
| 1988 | 0x37b28, 0x37b28, | ||
| 1989 | 0x37b3c, 0x37b50, | ||
| 1990 | 0x37bf0, 0x37c10, | ||
| 1991 | 0x37c28, 0x37c28, | ||
| 1992 | 0x37c3c, 0x37c50, | ||
| 1993 | 0x37cf0, 0x37cfc, | ||
| 1994 | 0x38000, 0x38030, | ||
| 1995 | 0x38100, 0x38144, | ||
| 1996 | 0x38190, 0x381d0, | ||
| 1997 | 0x38200, 0x38318, | ||
| 1998 | 0x38400, 0x3852c, | ||
| 1999 | 0x38540, 0x3861c, | ||
| 2000 | 0x38800, 0x38834, | ||
| 2001 | 0x388c0, 0x38908, | ||
| 2002 | 0x38910, 0x389ac, | ||
| 2003 | 0x38a00, 0x38a04, | ||
| 2004 | 0x38a0c, 0x38a2c, | ||
| 2005 | 0x38a44, 0x38a50, | ||
| 2006 | 0x38a74, 0x38c24, | ||
| 2007 | 0x38d08, 0x38d14, | ||
| 2008 | 0x38d1c, 0x38d20, | ||
| 2009 | 0x38d3c, 0x38d50, | ||
| 2010 | 0x39200, 0x3920c, | ||
| 2011 | 0x39220, 0x39220, | ||
| 2012 | 0x39240, 0x39240, | ||
| 2013 | 0x39600, 0x39600, | ||
| 2014 | 0x39608, 0x3960c, | ||
| 2015 | 0x39a00, 0x39a1c, | ||
| 2016 | 0x39e04, 0x39e20, | ||
| 2017 | 0x39e38, 0x39e3c, | ||
| 2018 | 0x39e80, 0x39e80, | ||
| 2019 | 0x39e88, 0x39ea8, | ||
| 2020 | 0x39eb0, 0x39eb4, | ||
| 2021 | 0x39ec8, 0x39ed4, | ||
| 2022 | 0x39fb8, 0x3a004, | ||
| 2023 | 0x3a208, 0x3a23c, | ||
| 2024 | 0x3a600, 0x3a630, | ||
| 2025 | 0x3aa00, 0x3aabc, | ||
| 2026 | 0x3ab00, 0x3ab70, | ||
| 2027 | 0x3b000, 0x3b048, | ||
| 2028 | 0x3b060, 0x3b09c, | ||
| 2029 | 0x3b0f0, 0x3b148, | ||
| 2030 | 0x3b160, 0x3b19c, | ||
| 2031 | 0x3b1f0, 0x3b2e4, | ||
| 2032 | 0x3b2f8, 0x3b3e4, | ||
| 2033 | 0x3b3f8, 0x3b448, | ||
| 2034 | 0x3b460, 0x3b49c, | ||
| 2035 | 0x3b4f0, 0x3b548, | ||
| 2036 | 0x3b560, 0x3b59c, | ||
| 2037 | 0x3b5f0, 0x3b6e4, | ||
| 2038 | 0x3b6f8, 0x3b7e4, | ||
| 2039 | 0x3b7f8, 0x3b7fc, | ||
| 2040 | 0x3b814, 0x3b814, | ||
| 2041 | 0x3b82c, 0x3b82c, | ||
| 2042 | 0x3b880, 0x3b88c, | ||
| 2043 | 0x3b8e8, 0x3b8ec, | ||
| 2044 | 0x3b900, 0x3b948, | ||
| 2045 | 0x3b960, 0x3b99c, | ||
| 2046 | 0x3b9f0, 0x3bae4, | ||
| 2047 | 0x3baf8, 0x3bb10, | ||
| 2048 | 0x3bb28, 0x3bb28, | ||
| 2049 | 0x3bb3c, 0x3bb50, | ||
| 2050 | 0x3bbf0, 0x3bc10, | ||
| 2051 | 0x3bc28, 0x3bc28, | ||
| 2052 | 0x3bc3c, 0x3bc50, | ||
| 2053 | 0x3bcf0, 0x3bcfc, | ||
| 2054 | 0x3c000, 0x3c030, | ||
| 2055 | 0x3c100, 0x3c144, | ||
| 2056 | 0x3c190, 0x3c1d0, | ||
| 2057 | 0x3c200, 0x3c318, | ||
| 2058 | 0x3c400, 0x3c52c, | ||
| 2059 | 0x3c540, 0x3c61c, | ||
| 2060 | 0x3c800, 0x3c834, | ||
| 2061 | 0x3c8c0, 0x3c908, | ||
| 2062 | 0x3c910, 0x3c9ac, | ||
| 2063 | 0x3ca00, 0x3ca04, | ||
| 2064 | 0x3ca0c, 0x3ca2c, | ||
| 2065 | 0x3ca44, 0x3ca50, | ||
| 2066 | 0x3ca74, 0x3cc24, | ||
| 2067 | 0x3cd08, 0x3cd14, | ||
| 2068 | 0x3cd1c, 0x3cd20, | ||
| 2069 | 0x3cd3c, 0x3cd50, | ||
| 2070 | 0x3d200, 0x3d20c, | ||
| 2071 | 0x3d220, 0x3d220, | ||
| 2072 | 0x3d240, 0x3d240, | ||
| 2073 | 0x3d600, 0x3d600, | ||
| 2074 | 0x3d608, 0x3d60c, | ||
| 2075 | 0x3da00, 0x3da1c, | ||
| 2076 | 0x3de04, 0x3de20, | ||
| 2077 | 0x3de38, 0x3de3c, | ||
| 2078 | 0x3de80, 0x3de80, | ||
| 2079 | 0x3de88, 0x3dea8, | ||
| 2080 | 0x3deb0, 0x3deb4, | ||
| 2081 | 0x3dec8, 0x3ded4, | ||
| 2082 | 0x3dfb8, 0x3e004, | ||
| 2083 | 0x3e208, 0x3e23c, | ||
| 2084 | 0x3e600, 0x3e630, | ||
| 2085 | 0x3ea00, 0x3eabc, | ||
| 2086 | 0x3eb00, 0x3eb70, | ||
| 2087 | 0x3f000, 0x3f048, | ||
| 2088 | 0x3f060, 0x3f09c, | ||
| 2089 | 0x3f0f0, 0x3f148, | ||
| 2090 | 0x3f160, 0x3f19c, | ||
| 2091 | 0x3f1f0, 0x3f2e4, | ||
| 2092 | 0x3f2f8, 0x3f3e4, | ||
| 2093 | 0x3f3f8, 0x3f448, | ||
| 2094 | 0x3f460, 0x3f49c, | ||
| 2095 | 0x3f4f0, 0x3f548, | ||
| 2096 | 0x3f560, 0x3f59c, | ||
| 2097 | 0x3f5f0, 0x3f6e4, | ||
| 2098 | 0x3f6f8, 0x3f7e4, | ||
| 2099 | 0x3f7f8, 0x3f7fc, | ||
| 2100 | 0x3f814, 0x3f814, | ||
| 2101 | 0x3f82c, 0x3f82c, | ||
| 2102 | 0x3f880, 0x3f88c, | ||
| 2103 | 0x3f8e8, 0x3f8ec, | ||
| 2104 | 0x3f900, 0x3f948, | ||
| 2105 | 0x3f960, 0x3f99c, | ||
| 2106 | 0x3f9f0, 0x3fae4, | ||
| 2107 | 0x3faf8, 0x3fb10, | ||
| 2108 | 0x3fb28, 0x3fb28, | ||
| 2109 | 0x3fb3c, 0x3fb50, | ||
| 2110 | 0x3fbf0, 0x3fc10, | ||
| 2111 | 0x3fc28, 0x3fc28, | ||
| 2112 | 0x3fc3c, 0x3fc50, | ||
| 2113 | 0x3fcf0, 0x3fcfc, | ||
| 2114 | 0x40000, 0x4000c, | ||
| 2115 | 0x40040, 0x40068, | ||
| 2116 | 0x40080, 0x40144, | ||
| 2117 | 0x40180, 0x4018c, | ||
| 2118 | 0x40200, 0x40298, | ||
| 2119 | 0x402ac, 0x4033c, | ||
| 2120 | 0x403f8, 0x403fc, | ||
| 2121 | 0x41300, 0x413c4, | ||
| 2122 | 0x41400, 0x4141c, | ||
| 2123 | 0x41480, 0x414d0, | ||
| 2124 | 0x44000, 0x44078, | ||
| 2125 | 0x440c0, 0x44278, | ||
| 2126 | 0x442c0, 0x44478, | ||
| 2127 | 0x444c0, 0x44678, | ||
| 2128 | 0x446c0, 0x44878, | ||
| 2129 | 0x448c0, 0x449fc, | ||
| 2130 | 0x45000, 0x45068, | ||
| 2131 | 0x45080, 0x45084, | ||
| 2132 | 0x450a0, 0x450b0, | ||
| 2133 | 0x45200, 0x45268, | ||
| 2134 | 0x45280, 0x45284, | ||
| 2135 | 0x452a0, 0x452b0, | ||
| 2136 | 0x460c0, 0x460e4, | ||
| 2137 | 0x47000, 0x4708c, | ||
| 2138 | 0x47200, 0x47250, | ||
| 2139 | 0x47400, 0x47420, | ||
| 2140 | 0x47600, 0x47618, | ||
| 2141 | 0x47800, 0x47814, | ||
| 2142 | 0x48000, 0x4800c, | ||
| 2143 | 0x48040, 0x48068, | ||
| 2144 | 0x48080, 0x48144, | ||
| 2145 | 0x48180, 0x4818c, | ||
| 2146 | 0x48200, 0x48298, | ||
| 2147 | 0x482ac, 0x4833c, | ||
| 2148 | 0x483f8, 0x483fc, | ||
| 2149 | 0x49300, 0x493c4, | ||
| 2150 | 0x49400, 0x4941c, | ||
| 2151 | 0x49480, 0x494d0, | ||
| 2152 | 0x4c000, 0x4c078, | ||
| 2153 | 0x4c0c0, 0x4c278, | ||
| 2154 | 0x4c2c0, 0x4c478, | ||
| 2155 | 0x4c4c0, 0x4c678, | ||
| 2156 | 0x4c6c0, 0x4c878, | ||
| 2157 | 0x4c8c0, 0x4c9fc, | ||
| 2158 | 0x4d000, 0x4d068, | ||
| 2159 | 0x4d080, 0x4d084, | ||
| 2160 | 0x4d0a0, 0x4d0b0, | ||
| 2161 | 0x4d200, 0x4d268, | ||
| 2162 | 0x4d280, 0x4d284, | ||
| 2163 | 0x4d2a0, 0x4d2b0, | ||
| 2164 | 0x4e0c0, 0x4e0e4, | ||
| 2165 | 0x4f000, 0x4f08c, | ||
| 2166 | 0x4f200, 0x4f250, | ||
| 2167 | 0x4f400, 0x4f420, | ||
| 2168 | 0x4f600, 0x4f618, | ||
| 2169 | 0x4f800, 0x4f814, | ||
| 2170 | 0x50000, 0x500cc, | ||
| 2171 | 0x50400, 0x50400, | ||
| 2172 | 0x50800, 0x508cc, | ||
| 2173 | 0x50c00, 0x50c00, | ||
| 2174 | 0x51000, 0x5101c, | ||
| 2175 | 0x51300, 0x51308, | ||
| 2176 | }; | ||
| 2177 | |||
| 1651 | int i; | 2178 | int i; |
| 1652 | struct adapter *ap = netdev2adap(dev); | 2179 | struct adapter *ap = netdev2adap(dev); |
| 2180 | static const unsigned int *reg_ranges; | ||
| 2181 | int arr_size = 0, buf_size = 0; | ||
| 2182 | |||
| 2183 | if (is_t4(ap->chip)) { | ||
| 2184 | reg_ranges = &t4_reg_ranges[0]; | ||
| 2185 | arr_size = ARRAY_SIZE(t4_reg_ranges); | ||
| 2186 | buf_size = T4_REGMAP_SIZE; | ||
| 2187 | } else { | ||
| 2188 | reg_ranges = &t5_reg_ranges[0]; | ||
| 2189 | arr_size = ARRAY_SIZE(t5_reg_ranges); | ||
| 2190 | buf_size = T5_REGMAP_SIZE; | ||
| 2191 | } | ||
| 1653 | 2192 | ||
| 1654 | regs->version = mk_adap_vers(ap); | 2193 | regs->version = mk_adap_vers(ap); |
| 1655 | 2194 | ||
| 1656 | memset(buf, 0, T4_REGMAP_SIZE); | 2195 | memset(buf, 0, buf_size); |
| 1657 | for (i = 0; i < ARRAY_SIZE(reg_ranges); i += 2) | 2196 | for (i = 0; i < arr_size; i += 2) |
| 1658 | reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]); | 2197 | reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]); |
| 1659 | } | 2198 | } |
| 1660 | 2199 | ||
| @@ -2205,14 +2744,14 @@ static int cxgb_set_features(struct net_device *dev, netdev_features_t features) · 544 unmodified lines | |||
| 2205 | netdev_features_t changed = dev->features ^ features; | 2744 | netdev_features_t changed = dev->features ^ features; |
| 2206 | int err; | 2745 | int err; |
| 2207 | 2746 | ||
| 2208 | if (!(changed & NETIF_F_HW_VLAN_RX)) | 2747 | if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) |
| 2209 | return 0; | 2748 | return 0; |
| 2210 | 2749 | ||
| 2211 | err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1, | 2750 | err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1, |
| 2212 | -1, -1, -1, | 2751 | -1, -1, -1, |
| 2213 | !!(features & NETIF_F_HW_VLAN_RX), true); | 2752 | !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); |
| 2214 | if (unlikely(err)) | 2753 | if (unlikely(err)) |
| 2215 | dev->features = features ^ NETIF_F_HW_VLAN_RX; | 2754 | dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; |
| 2216 | return err; | 2755 | return err; |
| 2217 | } | 2756 | } |
| 2218 | 2757 | ||
| @@ -2363,8 +2902,8 @@ static ssize_t mem_read(struct file *file, char __user *buf, size_t count, · 144 unmodified lines | |||
| 2363 | int ret, ofst; | 2902 | int ret, ofst; |
| 2364 | __be32 data[16]; | 2903 | __be32 data[16]; |
| 2365 | 2904 | ||
| 2366 | if (mem == MEM_MC) | 2905 | if ((mem == MEM_MC) || (mem == MEM_MC1)) |
| 2367 | ret = t4_mc_read(adap, pos, data, NULL); | 2906 | ret = t4_mc_read(adap, mem % MEM_MC, pos, data, NULL); |
| 2368 | else | 2907 | else |
| 2369 | ret = t4_edc_read(adap, mem, pos, data, NULL); | 2908 | ret = t4_edc_read(adap, mem, pos, data, NULL); |
| 2370 | if (ret) | 2909 | if (ret) |
| @@ -2405,18 +2944,37 @@ static void add_debugfs_mem(struct adapter *adap, const char *name, · 34 unmodified lines | |||
| 2405 | static int setup_debugfs(struct adapter *adap) | 2944 | static int setup_debugfs(struct adapter *adap) |
| 2406 | { | 2945 | { |
| 2407 | int i; | 2946 | int i; |
| 2947 | u32 size; | ||
| 2408 | 2948 | ||
| 2409 | if (IS_ERR_OR_NULL(adap->debugfs_root)) | 2949 | if (IS_ERR_OR_NULL(adap->debugfs_root)) |
| 2410 | return -1; | 2950 | return -1; |
| 2411 | 2951 | ||
| 2412 | i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE); | 2952 | i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE); |
| 2413 | if (i & EDRAM0_ENABLE) | 2953 | if (i & EDRAM0_ENABLE) { |
| 2414 | add_debugfs_mem(adap, "edc0", MEM_EDC0, 5); | 2954 | size = t4_read_reg(adap, MA_EDRAM0_BAR); |
| 2415 | if (i & EDRAM1_ENABLE) | 2955 | add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM_SIZE_GET(size)); |
| 2416 | add_debugfs_mem(adap, "edc1", MEM_EDC1, 5); | 2956 | } |
| 2417 | if (i & EXT_MEM_ENABLE) | 2957 | if (i & EDRAM1_ENABLE) { |
| 2418 | add_debugfs_mem(adap, "mc", MEM_MC, | 2958 | size = t4_read_reg(adap, MA_EDRAM1_BAR); |
| 2419 | EXT_MEM_SIZE_GET(t4_read_reg(adap, MA_EXT_MEMORY_BAR))); | 2959 | add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM_SIZE_GET(size)); |
| 2960 | } | ||
| 2961 | if (is_t4(adap->chip)) { | ||
| 2962 | size = t4_read_reg(adap, MA_EXT_MEMORY_BAR); | ||
| 2963 | if (i & EXT_MEM_ENABLE) | ||
| 2964 | add_debugfs_mem(adap, "mc", MEM_MC, | ||
| 2965 | EXT_MEM_SIZE_GET(size)); | ||
| 2966 | } else { | ||
| 2967 | if (i & EXT_MEM_ENABLE) { | ||
| 2968 | size = t4_read_reg(adap, MA_EXT_MEMORY_BAR); | ||
| 2969 | add_debugfs_mem(adap, "mc0", MEM_MC0, | ||
| 2970 | EXT_MEM_SIZE_GET(size)); | ||
| 2971 | } | ||
| 2972 | if (i & EXT_MEM1_ENABLE) { | ||
| 2973 | size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR); | ||
| 2974 | add_debugfs_mem(adap, "mc1", MEM_MC1, | ||
| 2975 | EXT_MEM_SIZE_GET(size)); | ||
| 2976 | } | ||
| 2977 | } | ||
| 2420 | if (adap->l2t) | 2978 | if (adap->l2t) |
| 2421 | debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap, | 2979 | debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap, |
| 2422 | &t4_l2t_fops); | 2980 | &t4_l2t_fops); |
| @@ -2747,10 +3305,18 @@ EXPORT_SYMBOL(cxgb4_port_chan); · 324 unmodified lines | |||
| 2747 | unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) | 3305 | unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) |
| 2748 | { | 3306 | { |
| 2749 | struct adapter *adap = netdev2adap(dev); | 3307 | struct adapter *adap = netdev2adap(dev); |
| 2750 | u32 v; | 3308 | u32 v1, v2, lp_count, hp_count; |
| 2751 | 3309 | ||
| 2752 | v = t4_read_reg(adap, A_SGE_DBFIFO_STATUS); | 3310 | v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS); |
| 2753 | return lpfifo ? G_LP_COUNT(v) : G_HP_COUNT(v); | 3311 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2); |
| 3312 | if (is_t4(adap->chip)) { | ||
| 3313 | lp_count = G_LP_COUNT(v1); | ||
| 3314 | hp_count = G_HP_COUNT(v1); | ||
| 3315 | } else { | ||
| 3316 | lp_count = G_LP_COUNT_T5(v1); | ||
| 3317 | hp_count = G_HP_COUNT_T5(v2); | ||
| 3318 | } | ||
| 3319 | return lpfifo ? lp_count : hp_count; | ||
| 2754 | } | 3320 | } |
| 2755 | EXPORT_SYMBOL(cxgb4_dbfifo_count); | 3321 | EXPORT_SYMBOL(cxgb4_dbfifo_count); |
| 2756 | 3322 | ||
| @@ -2853,6 +3419,25 @@ out: · 96 unmodified lines | |||
| 2853 | } | 3419 | } |
| 2854 | EXPORT_SYMBOL(cxgb4_sync_txq_pidx); | 3420 | EXPORT_SYMBOL(cxgb4_sync_txq_pidx); |
| 2855 | 3421 | ||
| 3422 | void cxgb4_disable_db_coalescing(struct net_device *dev) | ||
| 3423 | { | ||
| 3424 | struct adapter *adap; | ||
| 3425 | |||
| 3426 | adap = netdev2adap(dev); | ||
| 3427 | t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, | ||
| 3428 | F_NOCOALESCE); | ||
| 3429 | } | ||
| 3430 | EXPORT_SYMBOL(cxgb4_disable_db_coalescing); | ||
| 3431 | |||
| 3432 | void cxgb4_enable_db_coalescing(struct net_device *dev) | ||
| 3433 | { | ||
| 3434 | struct adapter *adap; | ||
| 3435 | |||
| 3436 | adap = netdev2adap(dev); | ||
| 3437 | t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0); | ||
| 3438 | } | ||
| 3439 | EXPORT_SYMBOL(cxgb4_enable_db_coalescing); | ||
| 3440 | |||
| 2856 | static struct pci_driver cxgb4_driver; | 3441 | static struct pci_driver cxgb4_driver; |
| 2857 | 3442 | ||
| 2858 | static void check_neigh_update(struct neighbour *neigh) | 3443 | static void check_neigh_update(struct neighbour *neigh) |
| @@ -2888,14 +3473,23 @@ static struct notifier_block cxgb4_netevent_nb = { · 29 unmodified lines | |||
| 2888 | 3473 | ||
| 2889 | static void drain_db_fifo(struct adapter *adap, int usecs) | 3474 | static void drain_db_fifo(struct adapter *adap, int usecs) |
| 2890 | { | 3475 | { |
| 2891 | u32 v; | 3476 | u32 v1, v2, lp_count, hp_count; |
| 2892 | 3477 | ||
| 2893 | do { | 3478 | do { |
| 3479 | v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS); | ||
| 3480 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2); | ||
| 3481 | if (is_t4(adap->chip)) { | ||
| 3482 | lp_count = G_LP_COUNT(v1); | ||
| 3483 | hp_count = G_HP_COUNT(v1); | ||
| 3484 | } else { | ||
| 3485 | lp_count = G_LP_COUNT_T5(v1); | ||
| 3486 | hp_count = G_HP_COUNT_T5(v2); | ||
| 3487 | } | ||
| 3488 | |||
| 3489 | if (lp_count == 0 && hp_count == 0) | ||
| 3490 | break; | ||
| 2894 | set_current_state(TASK_UNINTERRUPTIBLE); | 3491 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 2895 | schedule_timeout(usecs_to_jiffies(usecs)); | 3492 | schedule_timeout(usecs_to_jiffies(usecs)); |
| 2896 | v = t4_read_reg(adap, A_SGE_DBFIFO_STATUS); | ||
| 2897 | if (G_LP_COUNT(v) == 0 && G_HP_COUNT(v) == 0) | ||
| 2898 | break; | ||
| 2899 | } while (1); | 3493 | } while (1); |
| 2900 | } | 3494 | } |
| 2901 | 3495 | ||
| @@ -3004,24 +3598,62 @@ static void process_db_drop(struct work_struct *work) · 102 unmodified lines | |||
| 3004 | 3598 | ||
| 3005 | adap = container_of(work, struct adapter, db_drop_task); | 3599 | adap = container_of(work, struct adapter, db_drop_task); |
| 3006 | 3600 | ||
| 3601 | if (is_t4(adap->chip)) { | ||
| 3602 | disable_dbs(adap); | ||
| 3603 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); | ||
| 3604 | drain_db_fifo(adap, 1); | ||
| 3605 | recover_all_queues(adap); | ||
| 3606 | enable_dbs(adap); | ||
| 3607 | } else { | ||
| 3608 | u32 dropped_db = t4_read_reg(adap, 0x010ac); | ||
| 3609 | u16 qid = (dropped_db >> 15) & 0x1ffff; | ||
| 3610 | u16 pidx_inc = dropped_db & 0x1fff; | ||
| 3611 | unsigned int s_qpp; | ||
| 3612 | unsigned short udb_density; | ||
| 3613 | unsigned long qpshift; | ||
| 3614 | int page; | ||
| 3615 | u32 udb; | ||
| 3616 | |||
| 3617 | dev_warn(adap->pdev_dev, | ||
| 3618 | "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n", | ||
| 3619 | dropped_db, qid, | ||
| 3620 | (dropped_db >> 14) & 1, | ||
| 3621 | (dropped_db >> 13) & 1, | ||
| 3622 | pidx_inc); | ||
| 3623 | |||
| 3624 | drain_db_fifo(adap, 1); | ||
| 3625 | |||
| 3626 | s_qpp = QUEUESPERPAGEPF1 * adap->fn; | ||
| 3627 | udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap, | ||
| 3628 | SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp); | ||
| 3629 | qpshift = PAGE_SHIFT - ilog2(udb_density); | ||
| 3630 | udb = qid << qpshift; | ||
| 3631 | udb &= PAGE_MASK; | ||
| 3632 | page = udb / PAGE_SIZE; | ||
| 3633 | udb += (qid - (page * udb_density)) * 128; | ||
| 3634 | |||
| 3635 | writel(PIDX(pidx_inc), adap->bar2 + udb + 8); | ||
| 3636 | |||
| 3637 | /* Re-enable BAR2 WC */ | ||
| 3638 | t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); | ||
| 3639 | } | ||
| 3640 | |||
| 3007 | t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0); | 3641 | t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0); |
| 3008 | disable_dbs(adap); | ||
| 3009 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); | ||
| 3010 | drain_db_fifo(adap, 1); | ||
| 3011 | recover_all_queues(adap); | ||
| 3012 | enable_dbs(adap); | ||
| 3013 | } | 3642 | } |
| 3014 | 3643 | ||
| 3015 | void t4_db_full(struct adapter *adap) | 3644 | void t4_db_full(struct adapter *adap) |
| 3016 | { | 3645 | { |
| 3017 | t4_set_reg_field(adap, SGE_INT_ENABLE3, | 3646 | if (is_t4(adap->chip)) { |
| 3018 | DBFIFO_HP_INT | DBFIFO_LP_INT, 0); | 3647 | t4_set_reg_field(adap, SGE_INT_ENABLE3, |
| 3019 | queue_work(workq, &adap->db_full_task); | 3648 | DBFIFO_HP_INT | DBFIFO_LP_INT, 0); |
| 3649 | queue_work(workq, &adap->db_full_task); | ||
| 3650 | } | ||
| 3020 | } | 3651 | } |
| 3021 | 3652 | ||
| 3022 | void t4_db_dropped(struct adapter *adap) | 3653 | void t4_db_dropped(struct adapter *adap) |
| 3023 | { | 3654 | { |
| 3024 | queue_work(workq, &adap->db_drop_task); | 3655 | if (is_t4(adap->chip)) |
| 3656 | queue_work(workq, &adap->db_drop_task); | ||
| 3025 | } | 3657 | } |
| 3026 | 3658 | ||
| 3027 | static void uld_attach(struct adapter *adap, unsigned int uld) | 3659 | static void uld_attach(struct adapter *adap, unsigned int uld) |
| @@ -3566,17 +4198,27 @@ void t4_fatal_err(struct adapter *adap) · 538 unmodified lines | |||
| 3566 | 4198 | ||
| 3567 | static void setup_memwin(struct adapter *adap) | 4199 | static void setup_memwin(struct adapter *adap) |
| 3568 | { | 4200 | { |
| 3569 | u32 bar0; | 4201 | u32 bar0, mem_win0_base, mem_win1_base, mem_win2_base; |
| 3570 | 4202 | ||
| 3571 | bar0 = pci_resource_start(adap->pdev, 0); /* truncation intentional */ | 4203 | bar0 = pci_resource_start(adap->pdev, 0); /* truncation intentional */ |
| 4204 | if (is_t4(adap->chip)) { | ||
| 4205 | mem_win0_base = bar0 + MEMWIN0_BASE; | ||
| 4206 | mem_win1_base = bar0 + MEMWIN1_BASE; | ||
| 4207 | mem_win2_base = bar0 + MEMWIN2_BASE; | ||
| 4208 | } else { | ||
| 4209 | /* For T5, only relative offset inside the PCIe BAR is passed */ | ||
| 4210 | mem_win0_base = MEMWIN0_BASE; | ||
| 4211 | mem_win1_base = MEMWIN1_BASE_T5; | ||
| 4212 | mem_win2_base = MEMWIN2_BASE_T5; | ||
| 4213 | } | ||
| 3572 | t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0), | 4214 | t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0), |
| 3573 | (bar0 + MEMWIN0_BASE) | BIR(0) | | 4215 | mem_win0_base | BIR(0) | |
| 3574 | WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); | 4216 | WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); |
| 3575 | t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1), | 4217 | t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1), |
| 3576 | (bar0 + MEMWIN1_BASE) | BIR(0) | | 4218 | mem_win1_base | BIR(0) | |
| 3577 | WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); | 4219 | WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); |
| 3578 | t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2), | 4220 | t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2), |
| 3579 | (bar0 + MEMWIN2_BASE) | BIR(0) | | 4221 | mem_win2_base | BIR(0) | |
| 3580 | WINDOW(ilog2(MEMWIN2_APERTURE) - 10)); | 4222 | WINDOW(ilog2(MEMWIN2_APERTURE) - 10)); |
| 3581 | } | 4223 | } |
| 3582 | 4224 | ||
| @@ -3745,6 +4387,7 @@ static int adap_init0_config(struct adapter *adapter, int reset) · 162 unmodified lines | |||
| 3745 | unsigned long mtype = 0, maddr = 0; | 4387 | unsigned long mtype = 0, maddr = 0; |
| 3746 | u32 finiver, finicsum, cfcsum; | 4388 | u32 finiver, finicsum, cfcsum; |
| 3747 | int ret, using_flash; | 4389 | int ret, using_flash; |
| 4390 | char *fw_config_file, fw_config_file_path[256]; | ||
| 3748 | 4391 | ||
| 3749 | /* | 4392 | /* |
| 3750 | * Reset device if necessary. | 4393 | * Reset device if necessary. |
| @@ -3761,7 +4404,21 @@ static int adap_init0_config(struct adapter *adapter, int reset) · 10 unmodified lines | |||
| 3761 | * then use that. Otherwise, use the configuration file stored | 4404 | * then use that. Otherwise, use the configuration file stored |
| 3762 | * in the adapter flash ... | 4405 | * in the adapter flash ... |
| 3763 | */ | 4406 | */ |
| 3764 | ret = request_firmware(&cf, FW_CFNAME, adapter->pdev_dev); | 4407 | switch (CHELSIO_CHIP_VERSION(adapter->chip)) { |
| 4408 | case CHELSIO_T4: | ||
| 4409 | fw_config_file = FW_CFNAME; | ||
| 4410 | break; | ||
| 4411 | case CHELSIO_T5: | ||
| 4412 | fw_config_file = FW5_CFNAME; | ||
| 4413 | break; | ||
| 4414 | default: | ||
| 4415 | dev_err(adapter->pdev_dev, "Device %d is not supported\n", | ||
| 4416 | adapter->pdev->device); | ||
| 4417 | ret = -EINVAL; | ||
| 4418 | goto bye; | ||
| 4419 | } | ||
| 4420 | |||
| 4421 | ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); | ||
| 3765 | if (ret < 0) { | 4422 | if (ret < 0) { |
| 3766 | using_flash = 1; | 4423 | using_flash = 1; |
| 3767 | mtype = FW_MEMTYPE_CF_FLASH; | 4424 | mtype = FW_MEMTYPE_CF_FLASH; |
| @@ -3877,6 +4534,7 @@ static int adap_init0_config(struct adapter *adapter, int reset) · 109 unmodified lines | |||
| 3877 | if (ret < 0) | 4534 | if (ret < 0) |
| 3878 | goto bye; | 4535 | goto bye; |
| 3879 | 4536 | ||
| 4537 | sprintf(fw_config_file_path, "/lib/firmware/%s", fw_config_file); | ||
| 3880 | /* | 4538 | /* |
| 3881 | * Return successfully and note that we're operating with parameters | 4539 | * Return successfully and note that we're operating with parameters |
| 3882 | * not supplied by the driver, rather than from hard-wired | 4540 | * not supplied by the driver, rather than from hard-wired |
| @@ -3887,7 +4545,7 @@ static int adap_init0_config(struct adapter *adapter, int reset) · 4 unmodified lines | |||
| 3887 | "Configuration File %s, version %#x, computed checksum %#x\n", | 4545 | "Configuration File %s, version %#x, computed checksum %#x\n", |
| 3888 | (using_flash | 4546 | (using_flash |
| 3889 | ? "in device FLASH" | 4547 | ? "in device FLASH" |
| 3890 | : "/lib/firmware/" FW_CFNAME), | 4548 | : fw_config_file_path), |
| 3891 | finiver, cfcsum); | 4549 | finiver, cfcsum); |
| 3892 | return 0; | 4550 | return 0; |
| 3893 | 4551 | ||
| @@ -4354,6 +5012,15 @@ static int adap_init0(struct adapter *adap) · 460 unmodified lines | |||
| 4354 | adap->tids.aftid_end = val[1]; | 5012 | adap->tids.aftid_end = val[1]; |
| 4355 | } | 5013 | } |
| 4356 | 5014 | ||
| 5015 | /* If we're running on newer firmware, let it know that we're | ||
| 5016 | * prepared to deal with encapsulated CPL messages. Older | ||
| 5017 | * firmware won't understand this and we'll just get | ||
| 5018 | * unencapsulated messages ... | ||
| 5019 | */ | ||
| 5020 | params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); | ||
| 5021 | val[0] = 1; | ||
| 5022 | (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val); | ||
| 5023 | |||
| 4357 | /* | 5024 | /* |
| 4358 | * Get device capabilities so we can determine what resources we need | 5025 | * Get device capabilities so we can determine what resources we need |
| 4359 | * to manage. | 5026 | * to manage. |
| @@ -4814,7 +5481,8 @@ static void print_port_info(const struct net_device *dev) · 454 unmodified lines | |||
| 4814 | sprintf(bufp, "BASE-%s", base[pi->port_type]); | 5481 | sprintf(bufp, "BASE-%s", base[pi->port_type]); |
| 4815 | 5482 | ||
| 4816 | netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n", | 5483 | netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n", |
| 4817 | adap->params.vpd.id, adap->params.rev, buf, | 5484 | adap->params.vpd.id, |
| 5485 | CHELSIO_CHIP_RELEASE(adap->params.rev), buf, | ||
| 4818 | is_offload(adap) ? "R" : "", adap->params.pci.width, spd, | 5486 | is_offload(adap) ? "R" : "", adap->params.pci.width, spd, |
| 4819 | (adap->flags & USING_MSIX) ? " MSI-X" : | 5487 | (adap->flags & USING_MSIX) ? " MSI-X" : |
| 4820 | (adap->flags & USING_MSI) ? " MSI" : ""); | 5488 | (adap->flags & USING_MSI) ? " MSI" : ""); |
| @@ -4854,10 +5522,11 @@ static void free_some_resources(struct adapter *adapter) · 33 unmodified lines | |||
| 4854 | #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) | 5522 | #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) |
| 4855 | #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ | 5523 | #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ |
| 4856 | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) | 5524 | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) |
| 5525 | #define SEGMENT_SIZE 128 | ||
| 4857 | 5526 | ||
| 4858 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | 5527 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 4859 | { | 5528 | { |
| 4860 | int func, i, err; | 5529 | int func, i, err, s_qpp, qpp, num_seg; |
| 4861 | struct port_info *pi; | 5530 | struct port_info *pi; |
| 4862 | bool highdma = false; | 5531 | bool highdma = false; |
| 4863 | struct adapter *adapter = NULL; | 5532 | struct adapter *adapter = NULL; |
| @@ -4934,7 +5603,34 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 70 unmodified lines | |||
| 4934 | 5603 | ||
| 4935 | err = t4_prep_adapter(adapter); | 5604 | err = t4_prep_adapter(adapter); |
| 4936 | if (err) | 5605 | if (err) |
| 4937 | goto out_unmap_bar; | 5606 | goto out_unmap_bar0; |
| 5607 | |||
| 5608 | if (!is_t4(adapter->chip)) { | ||
| 5609 | s_qpp = QUEUESPERPAGEPF1 * adapter->fn; | ||
| 5610 | qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter, | ||
| 5611 | SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp); | ||
| 5612 | num_seg = PAGE_SIZE / SEGMENT_SIZE; | ||
| 5613 | |||
| 5614 | /* Each segment size is 128B. Write coalescing is enabled only | ||
| 5615 | * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the | ||
| 5616 | * queue is less no of segments that can be accommodated in | ||
| 5617 | * a page size. | ||
| 5618 | */ | ||
| 5619 | if (qpp > num_seg) { | ||
| 5620 | dev_err(&pdev->dev, | ||
| 5621 | "Incorrect number of egress queues per page\n"); | ||
| 5622 | err = -EINVAL; | ||
| 5623 | goto out_unmap_bar0; | ||
| 5624 | } | ||
| 5625 | adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), | ||
| 5626 | pci_resource_len(pdev, 2)); | ||
| 5627 | if (!adapter->bar2) { | ||
| 5628 | dev_err(&pdev->dev, "cannot map device bar2 region\n"); | ||
| 5629 | err = -ENOMEM; | ||
| 5630 | goto out_unmap_bar0; | ||
| 5631 | } | ||
| 5632 | } | ||
| 5633 | |||
| 4938 | setup_memwin(adapter); | 5634 | setup_memwin(adapter); |
| 4939 | err = adap_init0(adapter); | 5635 | err = adap_init0(adapter); |
| 4940 | setup_memwin_rdma(adapter); | 5636 | setup_memwin_rdma(adapter); |
| @@ -4963,7 +5659,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) · 22 unmodified lines | |||
| 4963 | netdev->hw_features = NETIF_F_SG | TSO_FLAGS | | 5659 | netdev->hw_features = NETIF_F_SG | TSO_FLAGS | |
| 4964 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | 5660 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
| 4965 | NETIF_F_RXCSUM | NETIF_F_RXHASH | | 5661 | NETIF_F_RXCSUM | NETIF_F_RXHASH | |
| 4966 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | 5662 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
| 4967 | if (highdma) | 5663 | if (highdma) |
| 4968 | netdev->hw_features |= NETIF_F_HIGHDMA; | 5664 | netdev->hw_features |= NETIF_F_HIGHDMA; |
| 4969 | netdev->features |= netdev->hw_features; | 5665 | netdev->features |= netdev->hw_features; |
| @@ -5063,6 +5759,9 @@ sriov: · 93 unmodified lines | |||
| 5063 | out_free_dev: | 5759 | out_free_dev: |
| 5064 | free_some_resources(adapter); | 5760 | free_some_resources(adapter); |
| 5065 | out_unmap_bar: | 5761 | out_unmap_bar: |
| 5762 | if (!is_t4(adapter->chip)) | ||
| 5763 | iounmap(adapter->bar2); | ||
| 5764 | out_unmap_bar0: | ||
| 5066 | iounmap(adapter->regs); | 5765 | iounmap(adapter->regs); |
| 5067 | out_free_adapter: | 5766 | out_free_adapter: |
| 5068 | kfree(adapter); | 5767 | kfree(adapter); |
| @@ -5113,6 +5812,8 @@ static void remove_one(struct pci_dev *pdev) · 44 unmodified lines | |||
| 5113 | 5812 | ||
| 5114 | free_some_resources(adapter); | 5813 | free_some_resources(adapter); |
| 5115 | iounmap(adapter->regs); | 5814 | iounmap(adapter->regs); |
| 5815 | if (!is_t4(adapter->chip)) | ||
| 5816 | iounmap(adapter->bar2); | ||
| 5116 | kfree(adapter); | 5817 | kfree(adapter); |
| 5117 | pci_disable_pcie_error_reporting(pdev); | 5818 | pci_disable_pcie_error_reporting(pdev); |
| 5118 | pci_disable_device(pdev); | 5819 | pci_disable_device(pdev); |
| @@ -269,4 +269,7 @@ struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl, · 268 unmodified lines | |||
| 269 | unsigned int skb_len, unsigned int pull_len); | 269 | unsigned int skb_len, unsigned int pull_len); |
| 270 | int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, u16 size); | 270 | int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, u16 size); |
| 271 | int cxgb4_flush_eq_cache(struct net_device *dev); | 271 | int cxgb4_flush_eq_cache(struct net_device *dev); |
| 272 | void cxgb4_disable_db_coalescing(struct net_device *dev); | ||
| 273 | void cxgb4_enable_db_coalescing(struct net_device *dev); | ||
| 274 | |||
| 272 | #endif /* !__CXGB4_OFLD_H */ | 275 | #endif /* !__CXGB4_OFLD_H */ |
| @@ -506,10 +506,14 @@ static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q) · 505 unmodified lines | |||
| 506 | 506 | ||
| 507 | static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) | 507 | static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) |
| 508 | { | 508 | { |
| 509 | u32 val; | ||
| 509 | if (q->pend_cred >= 8) { | 510 | if (q->pend_cred >= 8) { |
| 511 | val = PIDX(q->pend_cred / 8); | ||
| 512 | if (!is_t4(adap->chip)) | ||
| 513 | val |= DBTYPE(1); | ||
| 510 | wmb(); | 514 | wmb(); |
| 511 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO(1) | | 515 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO(1) | |
| 512 | QID(q->cntxt_id) | PIDX(q->pend_cred / 8)); | 516 | QID(q->cntxt_id) | val); |
| 513 | q->pend_cred &= 7; | 517 | q->pend_cred &= 7; |
| 514 | } | 518 | } |
| 515 | } | 519 | } |
| @@ -812,6 +816,22 @@ static void write_sgl(const struct sk_buff *skb, struct sge_txq *q, · 296 unmodified lines | |||
| 812 | *end = 0; | 816 | *end = 0; |
| 813 | } | 817 | } |
| 814 | 818 | ||
| 819 | /* This function copies 64 byte coalesced work request to | ||
| 820 | * memory mapped BAR2 space(user space writes). | ||
| 821 | * For coalesced WR SGE, fetches data from the FIFO instead of from Host. | ||
| 822 | */ | ||
| 823 | static void cxgb_pio_copy(u64 __iomem *dst, u64 *src) | ||
| 824 | { | ||
| 825 | int count = 8; | ||
| 826 | |||
| 827 | while (count) { | ||
| 828 | writeq(*src, dst); | ||
| 829 | src++; | ||
| 830 | dst++; | ||
| 831 | count--; | ||
| 832 | } | ||
| 833 | } | ||
| 834 | |||
| 815 | /** | 835 | /** |
| 816 | * ring_tx_db - check and potentially ring a Tx queue's doorbell | 836 | * ring_tx_db - check and potentially ring a Tx queue's doorbell |
| 817 | * @adap: the adapter | 837 | * @adap: the adapter |
| @@ -822,11 +842,25 @@ static void write_sgl(const struct sk_buff *skb, struct sge_txq *q, · 4 unmodified lines | |||
| 822 | */ | 842 | */ |
| 823 | static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) | 843 | static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) |
| 824 | { | 844 | { |
| 845 | unsigned int *wr, index; | ||
| 846 | |||
| 825 | wmb(); /* write descriptors before telling HW */ | 847 | wmb(); /* write descriptors before telling HW */ |
| 826 | spin_lock(&q->db_lock); | 848 | spin_lock(&q->db_lock); |
| 827 | if (!q->db_disabled) { | 849 | if (!q->db_disabled) { |
| 828 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), | 850 | if (is_t4(adap->chip)) { |
| 829 | QID(q->cntxt_id) | PIDX(n)); | 851 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), |
| 852 | QID(q->cntxt_id) | PIDX(n)); | ||
| 853 | } else { | ||
| 854 | if (n == 1) { | ||
| 855 | index = q->pidx ? (q->pidx - 1) : (q->size - 1); | ||
| 856 | wr = (unsigned int *)&q->desc[index]; | ||
| 857 | cxgb_pio_copy((u64 __iomem *) | ||
| 858 | (adap->bar2 + q->udb + 64), | ||
| 859 | (u64 *)wr); | ||
| 860 | } else | ||
| 861 | writel(n, adap->bar2 + q->udb + 8); | ||
| 862 | wmb(); | ||
| 863 | } | ||
| 830 | } | 864 | } |
| 831 | q->db_pidx = q->pidx; | 865 | q->db_pidx = q->pidx; |
| 832 | spin_unlock(&q->db_lock); | 866 | spin_unlock(&q->db_lock); |
| @@ -1555,7 +1589,6 @@ static noinline int handle_trace_pkt(struct adapter *adap, · 722 unmodified lines | |||
| 1555 | const struct pkt_gl *gl) | 1589 | const struct pkt_gl *gl) |
| 1556 | { | 1590 | { |
| 1557 | struct sk_buff *skb; | 1591 | struct sk_buff *skb; |
| 1558 | struct cpl_trace_pkt *p; | ||
| 1559 | 1592 | ||
| 1560 | skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN); | 1593 | skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN); |
| 1561 | if (unlikely(!skb)) { | 1594 | if (unlikely(!skb)) { |
| @@ -1563,8 +1596,11 @@ static noinline int handle_trace_pkt(struct adapter *adap, · 1 unmodified line | |||
| 1563 | return 0; | 1596 | return 0; |
| 1564 | } | 1597 | } |
| 1565 | 1598 | ||
| 1566 | p = (struct cpl_trace_pkt *)skb->data; | 1599 | if (is_t4(adap->chip)) |
| 1567 | __skb_pull(skb, sizeof(*p)); | 1600 | __skb_pull(skb, sizeof(struct cpl_trace_pkt)); |
| 1601 | else | ||
| 1602 | __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt)); | ||
| 1603 | |||
| 1568 | skb_reset_mac_header(skb); | 1604 | skb_reset_mac_header(skb); |
| 1569 | skb->protocol = htons(0xffff); | 1605 | skb->protocol = htons(0xffff); |
| 1570 | skb->dev = adap->port[0]; | 1606 | skb->dev = adap->port[0]; |
| @@ -1597,7 +1633,7 @@ static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl, · 26 unmodified lines | |||
| 1597 | skb->rxhash = (__force u32)pkt->rsshdr.hash_val; | 1633 | skb->rxhash = (__force u32)pkt->rsshdr.hash_val; |
| 1598 | 1634 | ||
| 1599 | if (unlikely(pkt->vlan_ex)) { | 1635 | if (unlikely(pkt->vlan_ex)) { |
| 1600 | __vlan_hwaccel_put_tag(skb, ntohs(pkt->vlan)); | 1636 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); |
| 1601 | rxq->stats.vlan_ex++; | 1637 | rxq->stats.vlan_ex++; |
| 1602 | } | 1638 | } |
| 1603 | ret = napi_gro_frags(&rxq->rspq.napi); | 1639 | ret = napi_gro_frags(&rxq->rspq.napi); |
| @@ -1625,8 +1661,10 @@ int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, · 21 unmodified lines | |||
| 1625 | const struct cpl_rx_pkt *pkt; | 1661 | const struct cpl_rx_pkt *pkt; |
| 1626 | struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); | 1662 | struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); |
| 1627 | struct sge *s = &q->adap->sge; | 1663 | struct sge *s = &q->adap->sge; |
| 1664 | int cpl_trace_pkt = is_t4(q->adap->chip) ? | ||
| 1665 | CPL_TRACE_PKT : CPL_TRACE_PKT_T5; | ||
| 1628 | 1666 | ||
| 1629 | if (unlikely(*(u8 *)rsp == CPL_TRACE_PKT)) | 1667 | if (unlikely(*(u8 *)rsp == cpl_trace_pkt)) |
| 1630 | return handle_trace_pkt(q->adap, si); | 1668 | return handle_trace_pkt(q->adap, si); |
| 1631 | 1669 | ||
| 1632 | pkt = (const struct cpl_rx_pkt *)rsp; | 1670 | pkt = (const struct cpl_rx_pkt *)rsp; |
| @@ -1667,7 +1705,7 @@ int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, · 34 unmodified lines | |||
| 1667 | skb_checksum_none_assert(skb); | 1705 | skb_checksum_none_assert(skb); |
| 1668 | 1706 | ||
| 1669 | if (unlikely(pkt->vlan_ex)) { | 1707 | if (unlikely(pkt->vlan_ex)) { |
| 1670 | __vlan_hwaccel_put_tag(skb, ntohs(pkt->vlan)); | 1708 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); |
| 1671 | rxq->stats.vlan_ex++; | 1709 | rxq->stats.vlan_ex++; |
| 1672 | } | 1710 | } |
| 1673 | netif_receive_skb(skb); | 1711 | netif_receive_skb(skb); |
| @@ -2143,11 +2181,27 @@ err: · 469 unmodified lines | |||
| 2143 | 2181 | ||
| 2144 | static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id) | 2182 | static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id) |
| 2145 | { | 2183 | { |
| 2184 | q->cntxt_id = id; | ||
| 2185 | if (!is_t4(adap->chip)) { | ||
| 2186 | unsigned int s_qpp; | ||
| 2187 | unsigned short udb_density; | ||
| 2188 | unsigned long qpshift; | ||
| 2189 | int page; | ||
| 2190 | |||
| 2191 | s_qpp = QUEUESPERPAGEPF1 * adap->fn; | ||
| 2192 | udb_density = 1 << QUEUESPERPAGEPF0_GET((t4_read_reg(adap, | ||
| 2193 | SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)); | ||
| 2194 | qpshift = PAGE_SHIFT - ilog2(udb_density); | ||
| 2195 | q->udb = q->cntxt_id << qpshift; | ||
| 2196 | q->udb &= PAGE_MASK; | ||
| 2197 | page = q->udb / PAGE_SIZE; | ||
| 2198 | q->udb += (q->cntxt_id - (page * udb_density)) * 128; | ||
| 2199 | } | ||
| 2200 | |||
| 2146 | q->in_use = 0; | 2201 | q->in_use = 0; |
| 2147 | q->cidx = q->pidx = 0; | 2202 | q->cidx = q->pidx = 0; |
| 2148 | q->stops = q->restarts = 0; | 2203 | q->stops = q->restarts = 0; |
| 2149 | q->stat = (void *)&q->desc[q->size]; | 2204 | q->stat = (void *)&q->desc[q->size]; |
| 2150 | q->cntxt_id = id; | ||
| 2151 | spin_lock_init(&q->db_lock); | 2205 | spin_lock_init(&q->db_lock); |
| 2152 | adap->sge.egr_map[id - adap->sge.egr_start] = q; | 2206 | adap->sge.egr_map[id - adap->sge.egr_start] = q; |
| 2153 | } | 2207 | } |
| @@ -2587,11 +2641,20 @@ static int t4_sge_init_hard(struct adapter *adap) · 433 unmodified lines | |||
| 2587 | * Set up to drop DOORBELL writes when the DOORBELL FIFO overflows | 2641 | * Set up to drop DOORBELL writes when the DOORBELL FIFO overflows |
| 2588 | * and generate an interrupt when this occurs so we can recover. | 2642 | * and generate an interrupt when this occurs so we can recover. |
| 2589 | */ | 2643 | */ |
| 2590 | t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS, | 2644 | if (is_t4(adap->chip)) { |
| 2591 | V_HP_INT_THRESH(M_HP_INT_THRESH) | | 2645 | t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS, |
| 2592 | V_LP_INT_THRESH(M_LP_INT_THRESH), | 2646 | V_HP_INT_THRESH(M_HP_INT_THRESH) | |
| 2593 | V_HP_INT_THRESH(dbfifo_int_thresh) | | 2647 | V_LP_INT_THRESH(M_LP_INT_THRESH), |
| 2594 | V_LP_INT_THRESH(dbfifo_int_thresh)); | 2648 | V_HP_INT_THRESH(dbfifo_int_thresh) | |
| 2649 | V_LP_INT_THRESH(dbfifo_int_thresh)); | ||
| 2650 | } else { | ||
| 2651 | t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS, | ||
| 2652 | V_LP_INT_THRESH_T5(M_LP_INT_THRESH_T5), | ||
| 2653 | V_LP_INT_THRESH_T5(dbfifo_int_thresh)); | ||
| 2654 | t4_set_reg_field(adap, SGE_DBFIFO_STATUS2, | ||
| 2655 | V_HP_INT_THRESH_T5(M_HP_INT_THRESH_T5), | ||
| 2656 | V_HP_INT_THRESH_T5(dbfifo_int_thresh)); | ||
| 2657 | } | ||
| 2595 | t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP, | 2658 | t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP, |
| 2596 | F_ENABLE_DROP); | 2659 | F_ENABLE_DROP); |
| 2597 | 2660 | ||
| @@ -282,6 +282,7 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, · 281 unmodified lines | |||
| 282 | * t4_mc_read - read from MC through backdoor accesses | 282 | * t4_mc_read - read from MC through backdoor accesses |
| 283 | * @adap: the adapter | 283 | * @adap: the adapter |
| 284 | * @addr: address of first byte requested | 284 | * @addr: address of first byte requested |
| 285 | * @idx: which MC to access | ||
| 285 | * @data: 64 bytes of data containing the requested address | 286 | * @data: 64 bytes of data containing the requested address |
| 286 | * @ecc: where to store the corresponding 64-bit ECC word | 287 | * @ecc: where to store the corresponding 64-bit ECC word |
| 287 | * | 288 | * |
| @@ -289,22 +290,38 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, · 1 unmodified line | |||
| 289 | * that covers the requested address @addr. If @parity is not %NULL it | 290 | * that covers the requested address @addr. If @parity is not %NULL it |
| 290 | * is assigned the 64-bit ECC word for the read data. | 291 | * is assigned the 64-bit ECC word for the read data. |
| 291 | */ | 292 | */ |
| 292 | int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc) | 293 | int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) |
| 293 | { | 294 | { |
| 294 | int i; | 295 | int i; |
| 296 | u32 mc_bist_cmd, mc_bist_cmd_addr, mc_bist_cmd_len; | ||
| 297 | u32 mc_bist_status_rdata, mc_bist_data_pattern; | ||
| 298 | |||
| 299 | if (is_t4(adap->chip)) { | ||
| 300 | mc_bist_cmd = MC_BIST_CMD; | ||
| 301 | mc_bist_cmd_addr = MC_BIST_CMD_ADDR; | ||
| 302 | mc_bist_cmd_len = MC_BIST_CMD_LEN; | ||
| 303 | mc_bist_status_rdata = MC_BIST_STATUS_RDATA; | ||
| 304 | mc_bist_data_pattern = MC_BIST_DATA_PATTERN; | ||
| 305 | } else { | ||
| 306 | mc_bist_cmd = MC_REG(MC_P_BIST_CMD, idx); | ||
| 307 | mc_bist_cmd_addr = MC_REG(MC_P_BIST_CMD_ADDR, idx); | ||
| 308 | mc_bist_cmd_len = MC_REG(MC_P_BIST_CMD_LEN, idx); | ||
| 309 | mc_bist_status_rdata = MC_REG(MC_P_BIST_STATUS_RDATA, idx); | ||
| 310 | mc_bist_data_pattern = MC_REG(MC_P_BIST_DATA_PATTERN, idx); | ||
| 311 | } | ||
| 295 | 312 | ||
| 296 | if (t4_read_reg(adap, MC_BIST_CMD) & START_BIST) | 313 | if (t4_read_reg(adap, mc_bist_cmd) & START_BIST) |
| 297 | return -EBUSY; | 314 | return -EBUSY; |
| 298 | t4_write_reg(adap, MC_BIST_CMD_ADDR, addr & ~0x3fU); | 315 | t4_write_reg(adap, mc_bist_cmd_addr, addr & ~0x3fU); |
| 299 | t4_write_reg(adap, MC_BIST_CMD_LEN, 64); | 316 | t4_write_reg(adap, mc_bist_cmd_len, 64); |
| 300 | t4_write_reg(adap, MC_BIST_DATA_PATTERN, 0xc); | 317 | t4_write_reg(adap, mc_bist_data_pattern, 0xc); |
| 301 | t4_write_reg(adap, MC_BIST_CMD, BIST_OPCODE(1) | START_BIST | | 318 | t4_write_reg(adap, mc_bist_cmd, BIST_OPCODE(1) | START_BIST | |
| 302 | BIST_CMD_GAP(1)); | 319 | BIST_CMD_GAP(1)); |
| 303 | i = t4_wait_op_done(adap, MC_BIST_CMD, START_BIST, 0, 10, 1); | 320 | i = t4_wait_op_done(adap, mc_bist_cmd, START_BIST, 0, 10, 1); |
| 304 | if (i) | 321 | if (i) |
| 305 | return i; | 322 | return i; |
| 306 | 323 | ||
| 307 | #define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i) | 324 | #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata, i) |
| 308 | 325 | ||
| 309 | for (i = 15; i >= 0; i--) | 326 | for (i = 15; i >= 0; i--) |
| 310 | *data++ = htonl(t4_read_reg(adap, MC_DATA(i))); | 327 | *data++ = htonl(t4_read_reg(adap, MC_DATA(i))); |
| @@ -329,20 +346,39 @@ int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc) · 18 unmodified lines | |||
| 329 | int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) | 346 | int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) |
| 330 | { | 347 | { |
| 331 | int i; | 348 | int i; |
| 349 | u32 edc_bist_cmd, edc_bist_cmd_addr, edc_bist_cmd_len; | ||
| 350 | u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata; | ||
| 351 | |||
| 352 | if (is_t4(adap->chip)) { | ||
| 353 | edc_bist_cmd = EDC_REG(EDC_BIST_CMD, idx); | ||
| 354 | edc_bist_cmd_addr = EDC_REG(EDC_BIST_CMD_ADDR, idx); | ||
| 355 | edc_bist_cmd_len = EDC_REG(EDC_BIST_CMD_LEN, idx); | ||
| 356 | edc_bist_cmd_data_pattern = EDC_REG(EDC_BIST_DATA_PATTERN, | ||
| 357 | idx); | ||
| 358 | edc_bist_status_rdata = EDC_REG(EDC_BIST_STATUS_RDATA, | ||
| 359 | idx); | ||
| 360 | } else { | ||
| 361 | edc_bist_cmd = EDC_REG_T5(EDC_H_BIST_CMD, idx); | ||
| 362 | edc_bist_cmd_addr = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx); | ||
| 363 | edc_bist_cmd_len = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx); | ||
| 364 | edc_bist_cmd_data_pattern = | ||
| 365 | EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx); | ||
| 366 | edc_bist_status_rdata = | ||
| 367 | EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx); | ||
| 368 | } | ||
| 332 | 369 | ||
| 333 | idx *= EDC_STRIDE; | 370 | if (t4_read_reg(adap, edc_bist_cmd) & START_BIST) |
| 334 | if (t4_read_reg(adap, EDC_BIST_CMD + idx) & START_BIST) | ||
| 335 | return -EBUSY; | 371 | return -EBUSY; |
| 336 | t4_write_reg(adap, EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU); | 372 | t4_write_reg(adap, edc_bist_cmd_addr, addr & ~0x3fU); |
| 337 | t4_write_reg(adap, EDC_BIST_CMD_LEN + idx, 64); | 373 | t4_write_reg(adap, edc_bist_cmd_len, 64); |
| 338 | t4_write_reg(adap, EDC_BIST_DATA_PATTERN + idx, 0xc); | 374 | t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); |
| 339 | t4_write_reg(adap, EDC_BIST_CMD + idx, | 375 | t4_write_reg(adap, edc_bist_cmd, |
| 340 | BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST); | 376 | BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST); |
| 341 | i = t4_wait_op_done(adap, EDC_BIST_CMD + idx, START_BIST, 0, 10, 1); | 377 | i = t4_wait_op_done(adap, edc_bist_cmd, START_BIST, 0, 10, 1); |
| 342 | if (i) | 378 | if (i) |
| 343 | return i; | 379 | return i; |
| 344 | 380 | ||
| 345 | #define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx) | 381 | #define EDC_DATA(i) (EDC_BIST_STATUS_REG(edc_bist_status_rdata, i)) |
| 346 | 382 | ||
| 347 | for (i = 15; i >= 0; i--) | 383 | for (i = 15; i >= 0; i--) |
| 348 | *data++ = htonl(t4_read_reg(adap, EDC_DATA(i))); | 384 | *data++ = htonl(t4_read_reg(adap, EDC_DATA(i))); |
| @@ -366,6 +402,7 @@ int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) · 17 unmodified lines | |||
| 366 | static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir) | 402 | static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir) |
| 367 | { | 403 | { |
| 368 | int i; | 404 | int i; |
| 405 | u32 win_pf = is_t4(adap->chip) ? 0 : V_PFNUM(adap->fn); | ||
| 369 | 406 | ||
| 370 | /* | 407 | /* |
| 371 | * Setup offset into PCIE memory window. Address must be a | 408 | * Setup offset into PCIE memory window. Address must be a |
| @@ -374,7 +411,7 @@ static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir) · 2 unmodified lines | |||
| 374 | * values.) | 411 | * values.) |
| 375 | */ | 412 | */ |
| 376 | t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET, | 413 | t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET, |
| 377 | addr & ~(MEMWIN0_APERTURE - 1)); | 414 | (addr & ~(MEMWIN0_APERTURE - 1)) | win_pf); |
| 378 | t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET); | 415 | t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET); |
| 379 | 416 | ||
| 380 | /* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */ | 417 | /* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */ |
| @@ -410,6 +447,7 @@ static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len, · 29 unmodified lines | |||
| 410 | __be32 *buf, int dir) | 447 | __be32 *buf, int dir) |
| 411 | { | 448 | { |
| 412 | u32 pos, start, end, offset, memoffset; | 449 | u32 pos, start, end, offset, memoffset; |
| 450 | u32 edc_size, mc_size; | ||
| 413 | int ret = 0; | 451 | int ret = 0; |
| 414 | __be32 *data; | 452 | __be32 *data; |
| 415 | 453 | ||
| @@ -423,13 +461,21 @@ static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len, · 7 unmodified lines | |||
| 423 | if (!data) | 461 | if (!data) |
| 424 | return -ENOMEM; | 462 | return -ENOMEM; |
| 425 | 463 | ||
| 426 | /* | 464 | /* Offset into the region of memory which is being accessed |
| 427 | * Offset into the region of memory which is being accessed | ||
| 428 | * MEM_EDC0 = 0 | 465 | * MEM_EDC0 = 0 |
| 429 | * MEM_EDC1 = 1 | 466 | * MEM_EDC1 = 1 |
| 430 | * MEM_MC = 2 | 467 | * MEM_MC = 2 -- T4 |
| 468 | * MEM_MC0 = 2 -- For T5 | ||
| 469 | * MEM_MC1 = 3 -- For T5 | ||
| 431 | */ | 470 | */ |
| 432 | memoffset = (mtype * (5 * 1024 * 1024)); | 471 | edc_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM0_BAR)); |
| 472 | if (mtype != MEM_MC1) | ||
| 473 | memoffset = (mtype * (edc_size * 1024 * 1024)); | ||
| 474 | else { | ||
| 475 | mc_size = EXT_MEM_SIZE_GET(t4_read_reg(adap, | ||
| 476 | MA_EXT_MEMORY_BAR)); | ||
| 477 | memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; | ||
| 478 | } | ||
| 433 | 479 | ||
| 434 | /* Determine the PCIE_MEM_ACCESS_OFFSET */ | 480 | /* Determine the PCIE_MEM_ACCESS_OFFSET */ |
| 435 | addr = addr + memoffset; | 481 | addr = addr + memoffset; |
| @@ -497,9 +543,9 @@ int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len, · 61 unmodified lines | |||
| 497 | } | 543 | } |
| 498 | 544 | ||
| 499 | #define EEPROM_STAT_ADDR 0x7bfc | 545 | #define EEPROM_STAT_ADDR 0x7bfc |
| 500 | #define VPD_LEN 512 | ||
| 501 | #define VPD_BASE 0x400 | 546 | #define VPD_BASE 0x400 |
| 502 | #define VPD_BASE_OLD 0 | 547 | #define VPD_BASE_OLD 0 |
| 548 | #define VPD_LEN 1024 | ||
| 503 | 549 | ||
| 504 | /** | 550 | /** |
| 505 | * t4_seeprom_wp - enable/disable EEPROM write protection | 551 | * t4_seeprom_wp - enable/disable EEPROM write protection |
| @@ -856,6 +902,7 @@ int t4_check_fw_version(struct adapter *adapter) · 350 unmodified lines | |||
| 856 | { | 902 | { |
| 857 | u32 api_vers[2]; | 903 | u32 api_vers[2]; |
| 858 | int ret, major, minor, micro; | 904 | int ret, major, minor, micro; |
| 905 | int exp_major, exp_minor, exp_micro; | ||
| 859 | 906 | ||
| 860 | ret = get_fw_version(adapter, &adapter->params.fw_vers); | 907 | ret = get_fw_version(adapter, &adapter->params.fw_vers); |
| 861 | if (!ret) | 908 | if (!ret) |
| @@ -870,17 +917,35 @@ int t4_check_fw_version(struct adapter *adapter) · 8 unmodified lines | |||
| 870 | major = FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers); | 917 | major = FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers); |
| 871 | minor = FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers); | 918 | minor = FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers); |
| 872 | micro = FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers); | 919 | micro = FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers); |
| 920 | |||
| 921 | switch (CHELSIO_CHIP_VERSION(adapter->chip)) { | ||
| 922 | case CHELSIO_T4: | ||
| 923 | exp_major = FW_VERSION_MAJOR; | ||
| 924 | exp_minor = FW_VERSION_MINOR; | ||
| 925 | exp_micro = FW_VERSION_MICRO; | ||
| 926 | break; | ||
| 927 | case CHELSIO_T5: | ||
| 928 | exp_major = FW_VERSION_MAJOR_T5; | ||
| 929 | exp_minor = FW_VERSION_MINOR_T5; | ||
| 930 | exp_micro = FW_VERSION_MICRO_T5; | ||
| 931 | break; | ||
| 932 | default: | ||
| 933 | dev_err(adapter->pdev_dev, "Unsupported chip type, %x\n", | ||
| 934 | adapter->chip); | ||
| 935 | return -EINVAL; | ||
| 936 | } | ||
| 937 | |||
| 873 | memcpy(adapter->params.api_vers, api_vers, | 938 | memcpy(adapter->params.api_vers, api_vers, |
| 874 | sizeof(adapter->params.api_vers)); | 939 | sizeof(adapter->params.api_vers)); |
| 875 | 940 | ||
| 876 | if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */ | 941 | if (major != exp_major) { /* major mismatch - fail */ |
| 877 | dev_err(adapter->pdev_dev, | 942 | dev_err(adapter->pdev_dev, |
| 878 | "card FW has major version %u, driver wants %u\n", | 943 | "card FW has major version %u, driver wants %u\n", |
| 879 | major, FW_VERSION_MAJOR); | 944 | major, exp_major); |
| 880 | return -EINVAL; | 945 | return -EINVAL; |
| 881 | } | 946 | } |
| 882 | 947 | ||
| 883 | if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO) | 948 | if (minor == exp_minor && micro == exp_micro) |
| 884 | return 0; /* perfect match */ | 949 | return 0; /* perfect match */ |
| 885 | 950 | ||
| 886 | /* Minor/micro version mismatch. Report it but often it's OK. */ | 951 | /* Minor/micro version mismatch. Report it but often it's OK. */ |
| @@ -1246,6 +1311,45 @@ static void pcie_intr_handler(struct adapter *adapter) · 359 unmodified lines | |||
| 1246 | { 0 } | 1311 | { 0 } |
| 1247 | }; | 1312 | }; |
| 1248 | 1313 | ||
| 1314 | static struct intr_info t5_pcie_intr_info[] = { | ||
| 1315 | { MSTGRPPERR, "Master Response Read Queue parity error", | ||
| 1316 | -1, 1 }, | ||
| 1317 | { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, | ||
| 1318 | { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, | ||
| 1319 | { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, | ||
| 1320 | { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, | ||
| 1321 | { MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, | ||
| 1322 | { MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, | ||
| 1323 | { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", | ||
| 1324 | -1, 1 }, | ||
| 1325 | { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", | ||
| 1326 | -1, 1 }, | ||
| 1327 | { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, | ||
| 1328 | { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, | ||
| 1329 | { CREQPERR, "PCI CMD channel request parity error", -1, 1 }, | ||
| 1330 | { CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, | ||
| 1331 | { DREQWRPERR, "PCI DMA channel write request parity error", | ||
| 1332 | -1, 1 }, | ||
| 1333 | { DREQPERR, "PCI DMA channel request parity error", -1, 1 }, | ||
| 1334 | { DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, | ||
| 1335 | { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, | ||
| 1336 | { HREQPERR, "PCI HMA channel request parity error", -1, 1 }, | ||
| 1337 | { HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, | ||
| 1338 | { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, | ||
| 1339 | { FIDPERR, "PCI FID parity error", -1, 1 }, | ||
| 1340 | { VFIDPERR, "PCI INTx clear parity error", -1, 1 }, | ||
| 1341 | { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, | ||
| 1342 | { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, | ||
| 1343 | { IPRXHDRGRPPERR, "PCI IP Rx header group parity error", | ||
| 1344 | -1, 1 }, | ||
| 1345 | { IPRXDATAGRPPERR, "PCI IP Rx data group parity error", -1, 1 }, | ||
| 1346 | { RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, | ||
| 1347 | { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, | ||
| 1348 | { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, | ||
| 1349 | { READRSPERR, "Outbound read error", -1, 0 }, | ||
| 1350 | { 0 } | ||
| 1351 | }; | ||
| 1352 | |||
| 1249 | int fat; | 1353 | int fat; |
| 1250 | 1354 | ||
| 1251 | fat = t4_handle_intr_status(adapter, | 1355 | fat = t4_handle_intr_status(adapter, |
| @@ -1254,7 +1358,10 @@ static void pcie_intr_handler(struct adapter *adapter) · 2 unmodified lines | |||
| 1254 | t4_handle_intr_status(adapter, | 1358 | t4_handle_intr_status(adapter, |
| 1255 | PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, | 1359 | PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, |
| 1256 | pcie_port_intr_info) + | 1360 | pcie_port_intr_info) + |
| 1257 | t4_handle_intr_status(adapter, PCIE_INT_CAUSE, pcie_intr_info); | 1361 | t4_handle_intr_status(adapter, PCIE_INT_CAUSE, |
| 1362 | is_t4(adapter->chip) ? | ||
| 1363 | pcie_intr_info : t5_pcie_intr_info); | ||
| 1364 | |||
| 1258 | if (fat) | 1365 | if (fat) |
| 1259 | t4_fatal_err(adapter); | 1366 | t4_fatal_err(adapter); |
| 1260 | } | 1367 | } |
| @@ -1664,7 +1771,14 @@ static void ncsi_intr_handler(struct adapter *adap) · 403 unmodified lines | |||
| 1664 | */ | 1771 | */ |
| 1665 | static void xgmac_intr_handler(struct adapter *adap, int port) | 1772 | static void xgmac_intr_handler(struct adapter *adap, int port) |
| 1666 | { | 1773 | { |
| 1667 | u32 v = t4_read_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE)); | 1774 | u32 v, int_cause_reg; |
| 1775 | |||
| 1776 | if (is_t4(adap->chip)) | ||
| 1777 | int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE); | ||
| 1778 | else | ||
| 1779 | int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE); | ||
| 1780 | |||
| 1781 | v = t4_read_reg(adap, int_cause_reg); | ||
| 1668 | 1782 | ||
| 1669 | v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR; | 1783 | v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR; |
| 1670 | if (!v) | 1784 | if (!v) |
| @@ -2126,7 +2240,9 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) · 455 unmodified lines | |||
| 2126 | u32 bgmap = get_mps_bg_map(adap, idx); | 2240 | u32 bgmap = get_mps_bg_map(adap, idx); |
| 2127 | 2241 | ||
| 2128 | #define GET_STAT(name) \ | 2242 | #define GET_STAT(name) \ |
| 2129 | t4_read_reg64(adap, PORT_REG(idx, MPS_PORT_STAT_##name##_L)) | 2243 | t4_read_reg64(adap, \ |
| 2244 | (is_t4(adap->chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ | ||
| 2245 | T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L))) | ||
| 2130 | #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) | 2246 | #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) |
| 2131 | 2247 | ||
| 2132 | p->tx_octets = GET_STAT(TX_PORT_BYTES); | 2248 | p->tx_octets = GET_STAT(TX_PORT_BYTES); |
| @@ -2205,14 +2321,26 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) · 72 unmodified lines | |||
| 2205 | void t4_wol_magic_enable(struct adapter *adap, unsigned int port, | 2321 | void t4_wol_magic_enable(struct adapter *adap, unsigned int port, |
| 2206 | const u8 *addr) | 2322 | const u8 *addr) |
| 2207 | { | 2323 | { |
| 2324 | u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; | ||
| 2325 | |||
| 2326 | if (is_t4(adap->chip)) { | ||
| 2327 | mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO); | ||
| 2328 | mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI); | ||
| 2329 | port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2); | ||
| 2330 | } else { | ||
| 2331 | mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO); | ||
| 2332 | mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI); | ||
| 2333 | port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2); | ||
| 2334 | } | ||
| 2335 | |||
| 2208 | if (addr) { | 2336 | if (addr) { |
| 2209 | t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO), | 2337 | t4_write_reg(adap, mag_id_reg_l, |
| 2210 | (addr[2] << 24) | (addr[3] << 16) | | 2338 | (addr[2] << 24) | (addr[3] << 16) | |
| 2211 | (addr[4] << 8) | addr[5]); | 2339 | (addr[4] << 8) | addr[5]); |
| 2212 | t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI), | 2340 | t4_write_reg(adap, mag_id_reg_h, |
| 2213 | (addr[0] << 8) | addr[1]); | 2341 | (addr[0] << 8) | addr[1]); |
| 2214 | } | 2342 | } |
| 2215 | t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), MAGICEN, | 2343 | t4_set_reg_field(adap, port_cfg_reg, MAGICEN, |
| 2216 | addr ? MAGICEN : 0); | 2344 | addr ? MAGICEN : 0); |
| 2217 | } | 2345 | } |
| 2218 | 2346 | ||
| @@ -2235,16 +2363,23 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, · 16 unmodified lines | |||
| 2235 | u64 mask0, u64 mask1, unsigned int crc, bool enable) | 2363 | u64 mask0, u64 mask1, unsigned int crc, bool enable) |
| 2236 | { | 2364 | { |
| 2237 | int i; | 2365 | int i; |
| 2366 | u32 port_cfg_reg; | ||
| 2367 | |||
| 2368 | if (is_t4(adap->chip)) | ||
| 2369 | port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2); | ||
| 2370 | else | ||
| 2371 | port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2); | ||
| 2238 | 2372 | ||
| 2239 | if (!enable) { | 2373 | if (!enable) { |
| 2240 | t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), | 2374 | t4_set_reg_field(adap, port_cfg_reg, PATEN, 0); |
| 2241 | PATEN, 0); | ||
| 2242 | return 0; | 2375 | return 0; |
| 2243 | } | 2376 | } |
| 2244 | if (map > 0xff) | 2377 | if (map > 0xff) |
| 2245 | return -EINVAL; | 2378 | return -EINVAL; |
| 2246 | 2379 | ||
| 2247 | #define EPIO_REG(name) PORT_REG(port, XGMAC_PORT_EPIO_##name) | 2380 | #define EPIO_REG(name) \ |
| 2381 | (is_t4(adap->chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \ | ||
| 2382 | T5_PORT_REG(port, MAC_PORT_EPIO_##name)) | ||
| 2248 | 2383 | ||
| 2249 | t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); | 2384 | t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); |
| 2250 | t4_write_reg(adap, EPIO_REG(DATA2), mask1); | 2385 | t4_write_reg(adap, EPIO_REG(DATA2), mask1); |
| @@ -2322,24 +2457,24 @@ int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, · 71 unmodified lines | |||
| 2322 | * @addr: address of first byte requested aligned on 32b. | 2457 | * @addr: address of first byte requested aligned on 32b. |
| 2323 | * @data: len bytes to hold the data read | 2458 | * @data: len bytes to hold the data read |
| 2324 | * @len: amount of data to read from window. Must be <= | 2459 | * @len: amount of data to read from window. Must be <= |
| 2325 | * MEMWIN0_APERATURE after adjusting for 16B alignment | 2460 | * MEMWIN0_APERATURE after adjusting for 16B for T4 and |
| 2326 | * requirements of the the memory window. | 2461 | * 128B for T5 alignment requirements of the the memory window. |
| 2327 | * | 2462 | * |
| 2328 | * Read len bytes of data from MC starting at @addr. | 2463 | * Read len bytes of data from MC starting at @addr. |
| 2329 | */ | 2464 | */ |
| 2330 | int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len) | 2465 | int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len) |
| 2331 | { | 2466 | { |
| 2332 | int i; | 2467 | int i, off; |
| 2333 | int off; | 2468 | u32 win_pf = is_t4(adap->chip) ? 0 : V_PFNUM(adap->fn); |
| 2334 | 2469 | ||
| 2335 | /* | 2470 | /* Align on a 2KB boundary. |
| 2336 | * Align on a 16B boundary. | ||
| 2337 | */ | 2471 | */ |
| 2338 | off = addr & 15; | 2472 | off = addr & MEMWIN0_APERTURE; |
| 2339 | if ((addr & 3) || (len + off) > MEMWIN0_APERTURE) | 2473 | if ((addr & 3) || (len + off) > MEMWIN0_APERTURE) |
| 2340 | return -EINVAL; | 2474 | return -EINVAL; |
| 2341 | 2475 | ||
| 2342 | t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET, addr & ~15); | 2476 | t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET, |
| 2477 | (addr & ~MEMWIN0_APERTURE) | win_pf); | ||
| 2343 | t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET); | 2478 | t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET); |
| 2344 | 2479 | ||
| 2345 | for (i = 0; i < len; i += 4) | 2480 | for (i = 0; i < len; i += 4) |
| @@ -3162,6 +3297,9 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, · 816 unmodified lines | |||
| 3162 | int i, ret; | 3297 | int i, ret; |
| 3163 | struct fw_vi_mac_cmd c; | 3298 | struct fw_vi_mac_cmd c; |
| 3164 | struct fw_vi_mac_exact *p; | 3299 | struct fw_vi_mac_exact *p; |
| 3300 | unsigned int max_naddr = is_t4(adap->chip) ? | ||
| 3301 | NUM_MPS_CLS_SRAM_L_INSTANCES : | ||
| 3302 | NUM_MPS_T5_CLS_SRAM_L_INSTANCES; | ||
| 3165 | 3303 | ||
| 3166 | if (naddr > 7) | 3304 | if (naddr > 7) |
| 3167 | return -EINVAL; | 3305 | return -EINVAL; |
| @@ -3187,8 +3325,8 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, · 19 unmodified lines | |||
| 3187 | u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx)); | 3325 | u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx)); |
| 3188 | 3326 | ||
| 3189 | if (idx) | 3327 | if (idx) |
| 3190 | idx[i] = index >= NEXACT_MAC ? 0xffff : index; | 3328 | idx[i] = index >= max_naddr ? 0xffff : index; |
| 3191 | if (index < NEXACT_MAC) | 3329 | if (index < max_naddr) |
| 3192 | ret++; | 3330 | ret++; |
| 3193 | else if (hash) | 3331 | else if (hash) |
| 3194 | *hash |= (1ULL << hash_mac_addr(addr[i])); | 3332 | *hash |= (1ULL << hash_mac_addr(addr[i])); |
| @@ -3221,6 +3359,9 @@ int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, · 26 unmodified lines | |||
| 3221 | int ret, mode; | 3359 | int ret, mode; |
| 3222 | struct fw_vi_mac_cmd c; | 3360 | struct fw_vi_mac_cmd c; |
| 3223 | struct fw_vi_mac_exact *p = c.u.exact; | 3361 | struct fw_vi_mac_exact *p = c.u.exact; |
| 3362 | unsigned int max_mac_addr = is_t4(adap->chip) ? | ||
| 3363 | NUM_MPS_CLS_SRAM_L_INSTANCES : | ||
| 3364 | NUM_MPS_T5_CLS_SRAM_L_INSTANCES; | ||
| 3224 | 3365 | ||
| 3225 | if (idx < 0) /* new allocation */ | 3366 | if (idx < 0) /* new allocation */ |
| 3226 | idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; | 3367 | idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; |
| @@ -3238,7 +3379,7 @@ int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, · 11 unmodified lines | |||
| 3238 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | 3379 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); |
| 3239 | if (ret == 0) { | 3380 | if (ret == 0) { |
| 3240 | ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx)); | 3381 | ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx)); |
| 3241 | if (ret >= NEXACT_MAC) | 3382 | if (ret >= max_mac_addr) |
| 3242 | ret = -ENOMEM; | 3383 | ret = -ENOMEM; |
| 3243 | } | 3384 | } |
| 3244 | return ret; | 3385 | return ret; |
| @@ -3547,7 +3688,8 @@ static int get_flash_params(struct adapter *adap) · 302 unmodified lines | |||
| 3547 | */ | 3688 | */ |
| 3548 | int t4_prep_adapter(struct adapter *adapter) | 3689 | int t4_prep_adapter(struct adapter *adapter) |
| 3549 | { | 3690 | { |
| 3550 | int ret; | 3691 | int ret, ver; |
| 3692 | uint16_t device_id; | ||
| 3551 | 3693 | ||
| 3552 | ret = t4_wait_dev_ready(adapter); | 3694 | ret = t4_wait_dev_ready(adapter); |
| 3553 | if (ret < 0) | 3695 | if (ret < 0) |
| @@ -3562,6 +3704,28 @@ int t4_prep_adapter(struct adapter *adapter) · 8 unmodified lines | |||
| 3562 | return ret; | 3704 | return ret; |
| 3563 | } | 3705 | } |
| 3564 | 3706 | ||
| 3707 | /* Retrieve adapter's device ID | ||
| 3708 | */ | ||
| 3709 | pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id); | ||
| 3710 | ver = device_id >> 12; | ||
| 3711 | switch (ver) { | ||
| 3712 | case CHELSIO_T4: | ||
| 3713 | adapter->chip = CHELSIO_CHIP_CODE(CHELSIO_T4, | ||
| 3714 | adapter->params.rev); | ||
| 3715 | break; | ||
| 3716 | case CHELSIO_T5: | ||
| 3717 | adapter->chip = CHELSIO_CHIP_CODE(CHELSIO_T5, | ||
| 3718 | adapter->params.rev); | ||
| 3719 | break; | ||
| 3720 | default: | ||
| 3721 | dev_err(adapter->pdev_dev, "Device %d is not supported\n", | ||
| 3722 | device_id); | ||
| 3723 | return -EINVAL; | ||
| 3724 | } | ||
| 3725 | |||
| 3726 | /* Reassign the updated revision field */ | ||
| 3727 | adapter->params.rev = adapter->chip; | ||
| 3728 | |||
| 3565 | init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); | 3729 | init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); |
| 3566 | 3730 | ||
| 3567 | /* | 3731 | /* |
| @@ -47,7 +47,6 @@ enum { · 46 unmodified lines | |||
| 47 | TCB_SIZE = 128, /* TCB size */ | 47 | TCB_SIZE = 128, /* TCB size */ |
| 48 | NMTUS = 16, /* size of MTU table */ | 48 | NMTUS = 16, /* size of MTU table */ |
| 49 | NCCTRL_WIN = 32, /* # of congestion control windows */ | 49 | NCCTRL_WIN = 32, /* # of congestion control windows */ |
| 50 | NEXACT_MAC = 336, /* # of exact MAC address filters */ | ||
| 51 | L2T_SIZE = 4096, /* # of L2T entries */ | 50 | L2T_SIZE = 4096, /* # of L2T entries */ |
| 52 | MBOX_LEN = 64, /* mailbox size in bytes */ | 51 | MBOX_LEN = 64, /* mailbox size in bytes */ |
| 53 | TRACE_LEN = 112, /* length of trace data and mask */ | 52 | TRACE_LEN = 112, /* length of trace data and mask */ |
| @@ -74,6 +74,7 @@ enum { · 73 unmodified lines | |||
| 74 | CPL_PASS_ESTABLISH = 0x41, | 74 | CPL_PASS_ESTABLISH = 0x41, |
| 75 | CPL_RX_DATA_DDP = 0x42, | 75 | CPL_RX_DATA_DDP = 0x42, |
| 76 | CPL_PASS_ACCEPT_REQ = 0x44, | 76 | CPL_PASS_ACCEPT_REQ = 0x44, |
| 77 | CPL_TRACE_PKT_T5 = 0x48, | ||
| 77 | 78 | ||
| 78 | CPL_RDMA_READ_REQ = 0x60, | 79 | CPL_RDMA_READ_REQ = 0x60, |
| 79 | 80 | ||
| @@ -157,6 +158,7 @@ union opcode_tid { · 77 unmodified lines | |||
| 157 | }; | 158 | }; |
| 158 | 159 | ||
| 159 | #define CPL_OPCODE(x) ((x) << 24) | 160 | #define CPL_OPCODE(x) ((x) << 24) |
| 161 | #define G_CPL_OPCODE(x) (((x) >> 24) & 0xFF) | ||
| 160 | #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid)) | 162 | #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid)) |
| 161 | #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) | 163 | #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) |
| 162 | #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF) | 164 | #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF) |
| @@ -287,6 +289,23 @@ struct cpl_act_open_req { · 124 unmodified lines | |||
| 287 | __be32 opt2; | 289 | __be32 opt2; |
| 288 | }; | 290 | }; |
| 289 | 291 | ||
| 292 | #define S_FILTER_TUPLE 24 | ||
| 293 | #define M_FILTER_TUPLE 0xFFFFFFFFFF | ||
| 294 | #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) | ||
| 295 | #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) | ||
| 296 | struct cpl_t5_act_open_req { | ||
| 297 | WR_HDR; | ||
| 298 | union opcode_tid ot; | ||
| 299 | __be16 local_port; | ||
| 300 | __be16 peer_port; | ||
| 301 | __be32 local_ip; | ||
| 302 | __be32 peer_ip; | ||
| 303 | __be64 opt0; | ||
| 304 | __be32 rsvd; | ||
| 305 | __be32 opt2; | ||
| 306 | __be64 params; | ||
| 307 | }; | ||
| 308 | |||
| 290 | struct cpl_act_open_req6 { | 309 | struct cpl_act_open_req6 { |
| 291 | WR_HDR; | 310 | WR_HDR; |
| 292 | union opcode_tid ot; | 311 | union opcode_tid ot; |
| @@ -566,6 +585,11 @@ struct cpl_rx_pkt { · 273 unmodified lines | |||
| 566 | #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) | 585 | #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) |
| 567 | #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) | 586 | #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) |
| 568 | 587 | ||
| 588 | #define S_RX_T5_ETHHDR_LEN 0 | ||
| 589 | #define M_RX_T5_ETHHDR_LEN 0x3F | ||
| 590 | #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) | ||
| 591 | #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) | ||
| 592 | |||
| 569 | #define S_RX_MACIDX 8 | 593 | #define S_RX_MACIDX 8 |
| 570 | #define M_RX_MACIDX 0x1FF | 594 | #define M_RX_MACIDX 0x1FF |
| 571 | #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) | 595 | #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) |
| @@ -612,6 +636,28 @@ struct cpl_trace_pkt { · 40 unmodified lines | |||
| 612 | __be64 tstamp; | 636 | __be64 tstamp; |
| 613 | }; | 637 | }; |
| 614 | 638 | ||
| 639 | struct cpl_t5_trace_pkt { | ||
| 640 | __u8 opcode; | ||
| 641 | __u8 intf; | ||
| 642 | #if defined(__LITTLE_ENDIAN_BITFIELD) | ||
| 643 | __u8 runt:4; | ||
| 644 | __u8 filter_hit:4; | ||
| 645 | __u8:6; | ||
| 646 | __u8 err:1; | ||
| 647 | __u8 trunc:1; | ||
| 648 | #else | ||
| 649 | __u8 filter_hit:4; | ||
| 650 | __u8 runt:4; | ||
| 651 | __u8 trunc:1; | ||
| 652 | __u8 err:1; | ||
| 653 | __u8:6; | ||
| 654 | #endif | ||
| 655 | __be16 rsvd; | ||
| 656 | __be16 len; | ||
| 657 | __be64 tstamp; | ||
| 658 | __be64 rsvd1; | ||
| 659 | }; | ||
| 660 | |||
| 615 | struct cpl_l2t_write_req { | 661 | struct cpl_l2t_write_req { |
| 616 | WR_HDR; | 662 | WR_HDR; |
| 617 | union opcode_tid ot; | 663 | union opcode_tid ot; |
| @@ -643,6 +689,15 @@ struct cpl_sge_egr_update { · 25 unmodified lines | |||
| 643 | __be16 pidx; | 689 | __be16 pidx; |
| 644 | }; | 690 | }; |
| 645 | 691 | ||
| 692 | /* cpl_fw*.type values */ | ||
| 693 | enum { | ||
| 694 | FW_TYPE_CMD_RPL = 0, | ||
| 695 | FW_TYPE_WR_RPL = 1, | ||
| 696 | FW_TYPE_CQE = 2, | ||
| 697 | FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, | ||
| 698 | FW_TYPE_RSSCPL = 4, | ||
| 699 | }; | ||
| 700 | |||
| 646 | struct cpl_fw4_pld { | 701 | struct cpl_fw4_pld { |
| 647 | u8 opcode; | 702 | u8 opcode; |
| 648 | u8 rsvd0[3]; | 703 | u8 rsvd0[3]; |
| @@ -692,6 +747,7 @@ enum { · 43 unmodified lines | |||
| 692 | FW6_TYPE_WR_RPL = 1, | 747 | FW6_TYPE_WR_RPL = 1, |
| 693 | FW6_TYPE_CQE = 2, | 748 | FW6_TYPE_CQE = 2, |
| 694 | FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, | 749 | FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, |
| 750 | FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, | ||
| 695 | }; | 751 | }; |
| 696 | 752 | ||
| 697 | struct cpl_fw6_msg_ofld_connection_wr_rpl { | 753 | struct cpl_fw6_msg_ofld_connection_wr_rpl { |
| @@ -742,4 +798,12 @@ struct ulp_mem_io { · 44 unmodified lines | |||
| 742 | #define ULP_MEMIO_LOCK(x) ((x) << 31) | 798 | #define ULP_MEMIO_LOCK(x) ((x) << 31) |
| 743 | }; | 799 | }; |
| 744 | 800 | ||
| 801 | #define S_T5_ULP_MEMIO_IMM 23 | ||
| 802 | #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) | ||
| 803 | #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) | ||
| 804 | |||
| 805 | #define S_T5_ULP_MEMIO_ORDER 22 | ||
| 806 | #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) | ||
| 807 | #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) | ||
| 808 | |||
| 745 | #endif /* __T4_MSG_H */ | 809 | #endif /* __T4_MSG_H */ |
| @@ -68,9 +68,14 @@ · 67 unmodified lines | |||
| 68 | #define QID_SHIFT 15 | 68 | #define QID_SHIFT 15 |
| 69 | #define QID(x) ((x) << QID_SHIFT) | 69 | #define QID(x) ((x) << QID_SHIFT) |
| 70 | #define DBPRIO(x) ((x) << 14) | 70 | #define DBPRIO(x) ((x) << 14) |
| 71 | #define DBTYPE(x) ((x) << 13) | ||
| 71 | #define PIDX_MASK 0x00003fffU | 72 | #define PIDX_MASK 0x00003fffU |
| 72 | #define PIDX_SHIFT 0 | 73 | #define PIDX_SHIFT 0 |
| 73 | #define PIDX(x) ((x) << PIDX_SHIFT) | 74 | #define PIDX(x) ((x) << PIDX_SHIFT) |
| 75 | #define S_PIDX_T5 0 | ||
| 76 | #define M_PIDX_T5 0x1fffU | ||
| 77 | #define PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5) | ||
| 78 | |||
| 74 | 79 | ||
| 75 | #define SGE_PF_GTS 0x4 | 80 | #define SGE_PF_GTS 0x4 |
| 76 | #define INGRESSQID_MASK 0xffff0000U | 81 | #define INGRESSQID_MASK 0xffff0000U |
| @@ -152,6 +157,8 @@ · 75 unmodified lines | |||
| 152 | #define QUEUESPERPAGEPF0_MASK 0x0000000fU | 157 | #define QUEUESPERPAGEPF0_MASK 0x0000000fU |
| 153 | #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK) | 158 | #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK) |
| 154 | 159 | ||
| 160 | #define QUEUESPERPAGEPF1 4 | ||
| 161 | |||
| 155 | #define SGE_INT_CAUSE1 0x1024 | 162 | #define SGE_INT_CAUSE1 0x1024 |
| 156 | #define SGE_INT_CAUSE2 0x1030 | 163 | #define SGE_INT_CAUSE2 0x1030 |
| 157 | #define SGE_INT_CAUSE3 0x103c | 164 | #define SGE_INT_CAUSE3 0x103c |
| @@ -234,6 +241,10 @@ · 76 unmodified lines | |||
| 234 | #define SGE_DOORBELL_CONTROL 0x10a8 | 241 | #define SGE_DOORBELL_CONTROL 0x10a8 |
| 235 | #define ENABLE_DROP (1 << 13) | 242 | #define ENABLE_DROP (1 << 13) |
| 236 | 243 | ||
| 244 | #define S_NOCOALESCE 26 | ||
| 245 | #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE) | ||
| 246 | #define F_NOCOALESCE V_NOCOALESCE(1U) | ||
| 247 | |||
| 237 | #define SGE_TIMER_VALUE_0_AND_1 0x10b8 | 248 | #define SGE_TIMER_VALUE_0_AND_1 0x10b8 |
| 238 | #define TIMERVALUE0_MASK 0xffff0000U | 249 | #define TIMERVALUE0_MASK 0xffff0000U |
| 239 | #define TIMERVALUE0_SHIFT 16 | 250 | #define TIMERVALUE0_SHIFT 16 |
| @@ -272,17 +283,36 @@ · 32 unmodified lines | |||
| 272 | #define S_HP_INT_THRESH 28 | 283 | #define S_HP_INT_THRESH 28 |
| 273 | #define M_HP_INT_THRESH 0xfU | 284 | #define M_HP_INT_THRESH 0xfU |
| 274 | #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) | 285 | #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) |
| 286 | #define S_LP_INT_THRESH_T5 18 | ||
| 287 | #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5) | ||
| 288 | #define M_LP_COUNT_T5 0x3ffffU | ||
| 289 | #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5) | ||
| 275 | #define M_HP_COUNT 0x7ffU | 290 | #define M_HP_COUNT 0x7ffU |
| 276 | #define S_HP_COUNT 16 | 291 | #define S_HP_COUNT 16 |
| 277 | #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) | 292 | #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) |
| 278 | #define S_LP_INT_THRESH 12 | 293 | #define S_LP_INT_THRESH 12 |
| 279 | #define M_LP_INT_THRESH 0xfU | 294 | #define M_LP_INT_THRESH 0xfU |
| 295 | #define M_LP_INT_THRESH_T5 0xfffU | ||
| 280 | #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) | 296 | #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) |
| 281 | #define M_LP_COUNT 0x7ffU | 297 | #define M_LP_COUNT 0x7ffU |
| 282 | #define S_LP_COUNT 0 | 298 | #define S_LP_COUNT 0 |
| 283 | #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) | 299 | #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) |
| 284 | #define A_SGE_DBFIFO_STATUS 0x10a4 | 300 | #define A_SGE_DBFIFO_STATUS 0x10a4 |
| 285 | 301 | ||
| 302 | #define SGE_STAT_TOTAL 0x10e4 | ||
| 303 | #define SGE_STAT_MATCH 0x10e8 | ||
| 304 | |||
| 305 | #define SGE_STAT_CFG 0x10ec | ||
| 306 | #define S_STATSOURCE_T5 9 | ||
| 307 | #define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5) | ||
| 308 | |||
| 309 | #define SGE_DBFIFO_STATUS2 0x1118 | ||
| 310 | #define M_HP_COUNT_T5 0x3ffU | ||
| 311 | #define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5) | ||
| 312 | #define S_HP_INT_THRESH_T5 10 | ||
| 313 | #define M_HP_INT_THRESH_T5 0xfU | ||
| 314 | #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5) | ||
| 315 | |||
| 286 | #define S_ENABLE_DROP 13 | 316 | #define S_ENABLE_DROP 13 |
| 287 | #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) | 317 | #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) |
| 288 | #define F_ENABLE_DROP V_ENABLE_DROP(1U) | 318 | #define F_ENABLE_DROP V_ENABLE_DROP(1U) |
| @@ -331,8 +361,27 @@ · 42 unmodified lines | |||
| 331 | #define MSIADDRHPERR 0x00000002U | 361 | #define MSIADDRHPERR 0x00000002U |
| 332 | #define MSIADDRLPERR 0x00000001U | 362 | #define MSIADDRLPERR 0x00000001U |
| 333 | 363 | ||
| 364 | #define READRSPERR 0x20000000U | ||
| 365 | #define TRGT1GRPPERR 0x10000000U | ||
| 366 | #define IPSOTPERR 0x08000000U | ||
| 367 | #define IPRXDATAGRPPERR 0x02000000U | ||
| 368 | #define IPRXHDRGRPPERR 0x01000000U | ||
| 369 | #define MAGRPPERR 0x00400000U | ||
| 370 | #define VFIDPERR 0x00200000U | ||
| 371 | #define HREQWRPERR 0x00010000U | ||
| 372 | #define DREQWRPERR 0x00002000U | ||
| 373 | #define MSTTAGQPERR 0x00000400U | ||
| 374 | #define PIOREQGRPPERR 0x00000100U | ||
| 375 | #define PIOCPLGRPPERR 0x00000080U | ||
| 376 | #define MSIXSTIPERR 0x00000004U | ||
| 377 | #define MSTTIMEOUTPERR 0x00000002U | ||
| 378 | #define MSTGRPPERR 0x00000001U | ||
| 379 | |||
| 334 | #define PCIE_NONFAT_ERR 0x3010 | 380 | #define PCIE_NONFAT_ERR 0x3010 |
| 335 | #define PCIE_MEM_ACCESS_BASE_WIN 0x3068 | 381 | #define PCIE_MEM_ACCESS_BASE_WIN 0x3068 |
| 382 | #define S_PCIEOFST 10 | ||
| 383 | #define M_PCIEOFST 0x3fffffU | ||
| 384 | #define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST) | ||
| 336 | #define PCIEOFST_MASK 0xfffffc00U | 385 | #define PCIEOFST_MASK 0xfffffc00U |
| 337 | #define BIR_MASK 0x00000300U | 386 | #define BIR_MASK 0x00000300U |
| 338 | #define BIR_SHIFT 8 | 387 | #define BIR_SHIFT 8 |
| @@ -342,6 +391,9 @@ · 3 unmodified lines | |||
| 342 | #define WINDOW(x) ((x) << WINDOW_SHIFT) | 391 | #define WINDOW(x) ((x) << WINDOW_SHIFT) |
| 343 | #define PCIE_MEM_ACCESS_OFFSET 0x306c | 392 | #define PCIE_MEM_ACCESS_OFFSET 0x306c |
| 344 | 393 | ||
| 394 | #define S_PFNUM 0 | ||
| 395 | #define V_PFNUM(x) ((x) << S_PFNUM) | ||
| 396 | |||
| 345 | #define PCIE_FW 0x30b8 | 397 | #define PCIE_FW 0x30b8 |
| 346 | #define PCIE_FW_ERR 0x80000000U | 398 | #define PCIE_FW_ERR 0x80000000U |
| 347 | #define PCIE_FW_INIT 0x40000000U | 399 | #define PCIE_FW_INIT 0x40000000U |
| @@ -407,12 +459,18 @@ · 59 unmodified lines | |||
| 407 | 459 | ||
| 408 | #define MC_BIST_STATUS_RDATA 0x7688 | 460 | #define MC_BIST_STATUS_RDATA 0x7688 |
| 409 | 461 | ||
| 462 | #define MA_EDRAM0_BAR 0x77c0 | ||
| 463 | #define MA_EDRAM1_BAR 0x77c4 | ||
| 464 | #define EDRAM_SIZE_MASK 0xfffU | ||
| 465 | #define EDRAM_SIZE_GET(x) ((x) & EDRAM_SIZE_MASK) | ||
| 466 | |||
| 410 | #define MA_EXT_MEMORY_BAR 0x77c8 | 467 | #define MA_EXT_MEMORY_BAR 0x77c8 |
| 411 | #define EXT_MEM_SIZE_MASK 0x00000fffU | 468 | #define EXT_MEM_SIZE_MASK 0x00000fffU |
| 412 | #define EXT_MEM_SIZE_SHIFT 0 | 469 | #define EXT_MEM_SIZE_SHIFT 0 |
| 413 | #define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT) | 470 | #define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT) |
| 414 | 471 | ||
| 415 | #define MA_TARGET_MEM_ENABLE 0x77d8 | 472 | #define MA_TARGET_MEM_ENABLE 0x77d8 |
| 473 | #define EXT_MEM1_ENABLE 0x00000010U | ||
| 416 | #define EXT_MEM_ENABLE 0x00000004U | 474 | #define EXT_MEM_ENABLE 0x00000004U |
| 417 | #define EDRAM1_ENABLE 0x00000002U | 475 | #define EDRAM1_ENABLE 0x00000002U |
| 418 | #define EDRAM0_ENABLE 0x00000001U | 476 | #define EDRAM0_ENABLE 0x00000001U |
| @@ -431,6 +489,7 @@ · 12 unmodified lines | |||
| 431 | #define MA_PCIE_FW 0x30b8 | 489 | #define MA_PCIE_FW 0x30b8 |
| 432 | #define MA_PARITY_ERROR_STATUS 0x77f4 | 490 | #define MA_PARITY_ERROR_STATUS 0x77f4 |
| 433 | 491 | ||
| 492 | #define MA_EXT_MEMORY1_BAR 0x7808 | ||
| 434 | #define EDC_0_BASE_ADDR 0x7900 | 493 | #define EDC_0_BASE_ADDR 0x7900 |
| 435 | 494 | ||
| 436 | #define EDC_BIST_CMD 0x7904 | 495 | #define EDC_BIST_CMD 0x7904 |
| @@ -801,6 +860,15 @@ · 364 unmodified lines | |||
| 801 | #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c | 860 | #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c |
| 802 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 | 861 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 |
| 803 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 | 862 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 |
| 863 | #define MAC_PORT_CFG2 0x818 | ||
| 864 | #define MAC_PORT_MAGIC_MACID_LO 0x824 | ||
| 865 | #define MAC_PORT_MAGIC_MACID_HI 0x828 | ||
| 866 | #define MAC_PORT_EPIO_DATA0 0x8c0 | ||
| 867 | #define MAC_PORT_EPIO_DATA1 0x8c4 | ||
| 868 | #define MAC_PORT_EPIO_DATA2 0x8c8 | ||
| 869 | #define MAC_PORT_EPIO_DATA3 0x8cc | ||
| 870 | #define MAC_PORT_EPIO_OP 0x8d0 | ||
| 871 | |||
| 804 | #define MPS_CMN_CTL 0x9000 | 872 | #define MPS_CMN_CTL 0x9000 |
| 805 | #define NUMPORTS_MASK 0x00000003U | 873 | #define NUMPORTS_MASK 0x00000003U |
| 806 | #define NUMPORTS_SHIFT 0 | 874 | #define NUMPORTS_SHIFT 0 |
| @@ -1063,6 +1131,7 @@ · 256 unmodified lines | |||
| 1063 | #define ADDRESS_SHIFT 0 | 1131 | #define ADDRESS_SHIFT 0 |
| 1064 | #define ADDRESS(x) ((x) << ADDRESS_SHIFT) | 1132 | #define ADDRESS(x) ((x) << ADDRESS_SHIFT) |
| 1065 | 1133 | ||
| 1134 | #define MAC_PORT_INT_CAUSE 0x8dc | ||
| 1066 | #define XGMAC_PORT_INT_CAUSE 0x10dc | 1135 | #define XGMAC_PORT_INT_CAUSE 0x10dc |
| 1067 | 1136 | ||
| 1068 | #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28 | 1137 | #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28 |
| @@ -1101,4 +1170,33 @@ · 32 unmodified lines | |||
| 1101 | #define V_PORT(x) ((x) << S_PORT) | 1170 | #define V_PORT(x) ((x) << S_PORT) |
| 1102 | #define F_PORT V_PORT(1U) | 1171 | #define F_PORT V_PORT(1U) |
| 1103 | 1172 | ||
| 1173 | #define NUM_MPS_CLS_SRAM_L_INSTANCES 336 | ||
| 1174 | #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 | ||
| 1175 | |||
| 1176 | #define T5_PORT0_BASE 0x30000 | ||
| 1177 | #define T5_PORT_STRIDE 0x4000 | ||
| 1178 | #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) | ||
| 1179 | #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) | ||
| 1180 | |||
| 1181 | #define MC_0_BASE_ADDR 0x40000 | ||
| 1182 | #define MC_1_BASE_ADDR 0x48000 | ||
| 1183 | #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) | ||
| 1184 | #define MC_REG(reg, idx) (reg + MC_STRIDE * idx) | ||
| 1185 | |||
| 1186 | #define MC_P_BIST_CMD 0x41400 | ||
| 1187 | #define MC_P_BIST_CMD_ADDR 0x41404 | ||
| 1188 | #define MC_P_BIST_CMD_LEN 0x41408 | ||
| 1189 | #define MC_P_BIST_DATA_PATTERN 0x4140c | ||
| 1190 | #define MC_P_BIST_STATUS_RDATA 0x41488 | ||
| 1191 | #define EDC_T50_BASE_ADDR 0x50000 | ||
| 1192 | #define EDC_H_BIST_CMD 0x50004 | ||
| 1193 | #define EDC_H_BIST_CMD_ADDR 0x50008 | ||
| 1194 | #define EDC_H_BIST_CMD_LEN 0x5000c | ||
| 1195 | #define EDC_H_BIST_DATA_PATTERN 0x50010 | ||
| 1196 | #define EDC_H_BIST_STATUS_RDATA 0x50028 | ||
| 1197 | |||
| 1198 | #define EDC_T51_BASE_ADDR 0x50800 | ||
| 1199 | #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) | ||
| 1200 | #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) | ||
| 1201 | |||
| 1104 | #endif /* __T4_REGS_H */ | 1202 | #endif /* __T4_REGS_H */ |
| @@ -574,7 +574,7 @@ struct fw_eth_tx_pkt_vm_wr { · 573 unmodified lines | |||
| 574 | __be16 vlantci; | 574 | __be16 vlantci; |
| 575 | }; | 575 | }; |
| 576 | 576 | ||
| 577 | #define FW_CMD_MAX_TIMEOUT 3000 | 577 | #define FW_CMD_MAX_TIMEOUT 10000 |
| 578 | 578 | ||
| 579 | /* | 579 | /* |
| 580 | * If a host driver does a HELLO and discovers that there's already a MASTER | 580 | * If a host driver does a HELLO and discovers that there's already a MASTER |
| @@ -973,7 +973,9 @@ enum fw_params_param_pfvf { · 392 unmodified lines | |||
| 973 | FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, | 973 | FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, |
| 974 | FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, | 974 | FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, |
| 975 | FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, | 975 | FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, |
| 976 | FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E | 976 | FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, |
| 977 | FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, | ||
| 978 | FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 | ||
| 977 | }; | 979 | }; |
| 978 | 980 | ||
| 979 | /* | 981 | /* |
| @@ -1758,6 +1760,25 @@ enum fw_port_module_type { · 778 unmodified lines | |||
| 1758 | FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK | 1760 | FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK |
| 1759 | }; | 1761 | }; |
| 1760 | 1762 | ||
| 1763 | enum fw_port_mod_sub_type { | ||
| 1764 | FW_PORT_MOD_SUB_TYPE_NA, | ||
| 1765 | FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, | ||
| 1766 | FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, | ||
| 1767 | FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, | ||
| 1768 | FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, | ||
| 1769 | FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, | ||
| 1770 | FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, | ||
| 1771 | |||
| 1772 | /* The following will never been in the VPD. They are TWINAX cable | ||
| 1773 | * lengths decoded from SFP+ module i2c PROMs. These should | ||
| 1774 | * almost certainly go somewhere else ... | ||
| 1775 | */ | ||
| 1776 | FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, | ||
| 1777 | FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, | ||
| 1778 | FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, | ||
| 1779 | FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, | ||
| 1780 | }; | ||
| 1781 | |||
| 1761 | /* port stats */ | 1782 | /* port stats */ |
| 1762 | #define FW_NUM_PORT_STATS 50 | 1783 | #define FW_NUM_PORT_STATS 50 |
| 1763 | #define FW_NUM_PORT_TX_STATS 23 | 1784 | #define FW_NUM_PORT_TX_STATS 23 |
| @@ -2123,11 +2144,11 @@ struct fw_hdr { · 359 unmodified lines | |||
| 2123 | u8 intfver_ri; | 2144 | u8 intfver_ri; |
| 2124 | u8 intfver_iscsipdu; | 2145 | u8 intfver_iscsipdu; |
| 2125 | u8 intfver_iscsi; | 2146 | u8 intfver_iscsi; |
| 2147 | u8 intfver_fcoepdu; | ||
| 2126 | u8 intfver_fcoe; | 2148 | u8 intfver_fcoe; |
| 2127 | u8 reserved2; | 2149 | __u32 reserved2; |
| 2128 | __u32 reserved3; | 2150 | __u32 reserved3; |
| 2129 | __u32 reserved4; | 2151 | __u32 reserved4; |
| 2130 | __u32 reserved5; | ||
| 2131 | __be32 flags; | 2152 | __be32 flags; |
| 2132 | __be32 reserved6[23]; | 2153 | __be32 reserved6[23]; |
| 2133 | }; | 2154 | }; |
| @@ -2137,6 +2158,17 @@ struct fw_hdr { · 3 unmodified lines | |||
| 2137 | #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff) | 2158 | #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff) |
| 2138 | #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff) | 2159 | #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff) |
| 2139 | 2160 | ||
| 2161 | enum fw_hdr_intfver { | ||
| 2162 | FW_HDR_INTFVER_NIC = 0x00, | ||
| 2163 | FW_HDR_INTFVER_VNIC = 0x00, | ||
| 2164 | FW_HDR_INTFVER_OFLD = 0x00, | ||
| 2165 | FW_HDR_INTFVER_RI = 0x00, | ||
| 2166 | FW_HDR_INTFVER_ISCSIPDU = 0x00, | ||
| 2167 | FW_HDR_INTFVER_ISCSI = 0x00, | ||
| 2168 | FW_HDR_INTFVER_FCOEPDU = 0x00, | ||
| 2169 | FW_HDR_INTFVER_FCOE = 0x00, | ||
| 2170 | }; | ||
| 2171 | |||
| 2140 | enum fw_hdr_flags { | 2172 | enum fw_hdr_flags { |
| 2141 | FW_HDR_FLAGS_RESET_HALT = 0x00000001, | 2173 | FW_HDR_FLAGS_RESET_HALT = 0x00000001, |
| 2142 | }; | 2174 | }; |
| @@ -344,6 +344,7 @@ struct adapter { · 343 unmodified lines | |||
| 344 | unsigned long registered_device_map; | 344 | unsigned long registered_device_map; |
| 345 | unsigned long open_device_map; | 345 | unsigned long open_device_map; |
| 346 | unsigned long flags; | 346 | unsigned long flags; |
| 347 | enum chip_type chip; | ||
| 347 | struct adapter_params params; | 348 | struct adapter_params params; |
| 348 | 349 | ||
| 349 | /* queue and interrupt resources */ | 350 | /* queue and interrupt resources */ |
| @@ -54,8 +54,8 @@ · 53 unmodified lines | |||
| 54 | /* | 54 | /* |
| 55 | * Generic information about the driver. | 55 | * Generic information about the driver. |
| 56 | */ | 56 | */ |
| 57 | #define DRV_VERSION "1.0.0" | 57 | #define DRV_VERSION "2.0.0-ko" |
| 58 | #define DRV_DESC "Chelsio T4 Virtual Function (VF) Network Driver" | 58 | #define DRV_DESC "Chelsio T4/T5 Virtual Function (VF) Network Driver" |
| 59 | 59 | ||
| 60 | /* | 60 | /* |
| 61 | * Module Parameters. | 61 | * Module Parameters. |
| @@ -409,6 +409,20 @@ static int fwevtq_handler(struct sge_rspq *rspq, const __be64 *rsp, · 347 unmodified lines | |||
| 409 | break; | 409 | break; |
| 410 | } | 410 | } |
| 411 | 411 | ||
| 412 | case CPL_FW4_MSG: { | ||
| 413 | /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. | ||
| 414 | */ | ||
| 415 | const struct cpl_sge_egr_update *p = (void *)(rsp + 3); | ||
| 416 | opcode = G_CPL_OPCODE(ntohl(p->opcode_qid)); | ||
| 417 | if (opcode != CPL_SGE_EGR_UPDATE) { | ||
| 418 | dev_err(adapter->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" | ||
| 419 | , opcode); | ||
| 420 | break; | ||
| 421 | } | ||
| 422 | cpl = (void *)p; | ||
| 423 | /*FALLTHROUGH*/ | ||
| 424 | } | ||
| 425 | |||
| 412 | case CPL_SGE_EGR_UPDATE: { | 426 | case CPL_SGE_EGR_UPDATE: { |
| 413 | /* | 427 | /* |
| 414 | * We've received an Egress Queue Status Update message. We | 428 | * We've received an Egress Queue Status Update message. We |
| @@ -1050,7 +1064,7 @@ static inline unsigned int mk_adap_vers(const struct adapter *adapter) · 635 unmodified lines | |||
| 1050 | /* | 1064 | /* |
| 1051 | * Chip version 4, revision 0x3f (cxgb4vf). | 1065 | * Chip version 4, revision 0x3f (cxgb4vf). |
| 1052 | */ | 1066 | */ |
| 1053 | return 4 | (0x3f << 10); | 1067 | return CHELSIO_CHIP_VERSION(adapter->chip) | (0x3f << 10); |
| 1054 | } | 1068 | } |
| 1055 | 1069 | ||
| 1056 | /* | 1070 | /* |
| @@ -1100,10 +1114,10 @@ static netdev_features_t cxgb4vf_fix_features(struct net_device *dev, · 43 unmodified lines | |||
| 1100 | * Since there is no support for separate rx/tx vlan accel | 1114 | * Since there is no support for separate rx/tx vlan accel |
| 1101 | * enable/disable make sure tx flag is always in same state as rx. | 1115 | * enable/disable make sure tx flag is always in same state as rx. |
| 1102 | */ | 1116 | */ |
| 1103 | if (features & NETIF_F_HW_VLAN_RX) | 1117 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 1104 | features |= NETIF_F_HW_VLAN_TX; | 1118 | features |= NETIF_F_HW_VLAN_CTAG_TX; |
| 1105 | else | 1119 | else |
| 1106 | features &= ~NETIF_F_HW_VLAN_TX; | 1120 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 1107 | 1121 | ||
| 1108 | return features; | 1122 | return features; |
| 1109 | } | 1123 | } |
| @@ -1114,9 +1128,9 @@ static int cxgb4vf_set_features(struct net_device *dev, · 4 unmodified lines | |||
| 1114 | struct port_info *pi = netdev_priv(dev); | 1128 | struct port_info *pi = netdev_priv(dev); |
| 1115 | netdev_features_t changed = dev->features ^ features; | 1129 | netdev_features_t changed = dev->features ^ features; |
| 1116 | 1130 | ||
| 1117 | if (changed & NETIF_F_HW_VLAN_RX) | 1131 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
| 1118 | t4vf_set_rxmode(pi->adapter, pi->viid, -1, -1, -1, -1, | 1132 | t4vf_set_rxmode(pi->adapter, pi->viid, -1, -1, -1, -1, |
| 1119 | features & NETIF_F_HW_VLAN_TX, 0); | 1133 | features & NETIF_F_HW_VLAN_CTAG_TX, 0); |
| 1120 | 1134 | ||
| 1121 | return 0; | 1135 | return 0; |
| 1122 | } | 1136 | } |
| @@ -2072,6 +2086,7 @@ static int adap_init0(struct adapter *adapter) · 949 unmodified lines | |||
| 2072 | struct sge *s = &adapter->sge; | 2086 | struct sge *s = &adapter->sge; |
| 2073 | unsigned int ethqsets; | 2087 | unsigned int ethqsets; |
| 2074 | int err; | 2088 | int err; |
| 2089 | u32 param, val = 0; | ||
| 2075 | 2090 | ||
| 2076 | /* | 2091 | /* |
| 2077 | * Wait for the device to become ready before proceeding ... | 2092 | * Wait for the device to become ready before proceeding ... |
| @@ -2099,6 +2114,15 @@ static int adap_init0(struct adapter *adapter) · 21 unmodified lines | |||
| 2099 | return err; | 2114 | return err; |
| 2100 | } | 2115 | } |
| 2101 | 2116 | ||
| 2117 | switch (adapter->pdev->device >> 12) { | ||
| 2118 | case CHELSIO_T4: | ||
| 2119 | adapter->chip = CHELSIO_CHIP_CODE(CHELSIO_T4, 0); | ||
| 2120 | break; | ||
| 2121 | case CHELSIO_T5: | ||
| 2122 | adapter->chip = CHELSIO_CHIP_CODE(CHELSIO_T5, 0); | ||
| 2123 | break; | ||
| 2124 | } | ||
| 2125 | |||
| 2102 | /* | 2126 | /* |
| 2103 | * Grab basic operational parameters. These will predominantly have | 2127 | * Grab basic operational parameters. These will predominantly have |
| 2104 | * been set up by the Physical Function Driver or will be hard coded | 2128 | * been set up by the Physical Function Driver or will be hard coded |
| @@ -2144,6 +2168,16 @@ static int adap_init0(struct adapter *adapter) · 39 unmodified lines | |||
| 2144 | return err; | 2168 | return err; |
| 2145 | } | 2169 | } |
| 2146 | 2170 | ||
| 2171 | /* If we're running on newer firmware, let it know that we're | ||
| 2172 | * prepared to deal with encapsulated CPL messages. Older | ||
| 2173 | * firmware won't understand this and we'll just get | ||
| 2174 | * unencapsulated messages ... | ||
| 2175 | */ | ||
| 2176 | param = FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | | ||
| 2177 | FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP); | ||
| 2178 | val = 1; | ||
| 2179 | (void) t4vf_set_params(adapter, 1, ¶m, &val); | ||
| 2180 | |||
| 2147 | /* | 2181 | /* |
| 2148 | * Retrieve our RX interrupt holdoff timer values and counter | 2182 | * Retrieve our RX interrupt holdoff timer values and counter |
| 2149 | * threshold values from the SGE parameters. | 2183 | * threshold values from the SGE parameters. |
| @@ -2614,11 +2648,12 @@ static int cxgb4vf_pci_probe(struct pci_dev *pdev, · 464 unmodified lines | |||
| 2614 | 2648 | ||
| 2615 | netdev->hw_features = NETIF_F_SG | TSO_FLAGS | | 2649 | netdev->hw_features = NETIF_F_SG | TSO_FLAGS | |
| 2616 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | 2650 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
| 2617 | NETIF_F_HW_VLAN_RX | NETIF_F_RXCSUM; | 2651 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_RXCSUM; |
| 2618 | netdev->vlan_features = NETIF_F_SG | TSO_FLAGS | | 2652 | netdev->vlan_features = NETIF_F_SG | TSO_FLAGS | |
| 2619 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | 2653 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
| 2620 | NETIF_F_HIGHDMA; | 2654 | NETIF_F_HIGHDMA; |
| 2621 | netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_TX; | 2655 | netdev->features = netdev->hw_features | |
| 2656 | NETIF_F_HW_VLAN_CTAG_TX; | ||
| 2622 | if (pci_using_dac) | 2657 | if (pci_using_dac) |
| 2623 | netdev->features |= NETIF_F_HIGHDMA; | 2658 | netdev->features |= NETIF_F_HIGHDMA; |
| 2624 | 2659 | ||
| @@ -2888,6 +2923,26 @@ static struct pci_device_id cxgb4vf_pci_tbl[] = { · 263 unmodified lines | |||
| 2888 | CH_DEVICE(0x480a, 0), /* T404-bt */ | 2923 | CH_DEVICE(0x480a, 0), /* T404-bt */ |
| 2889 | CH_DEVICE(0x480d, 0), /* T480-cr */ | 2924 | CH_DEVICE(0x480d, 0), /* T480-cr */ |
| 2890 | CH_DEVICE(0x480e, 0), /* T440-lp-cr */ | 2925 | CH_DEVICE(0x480e, 0), /* T440-lp-cr */ |
| 2926 | CH_DEVICE(0x5800, 0), /* T580-dbg */ | ||
| 2927 | CH_DEVICE(0x5801, 0), /* T520-cr */ | ||
| 2928 | CH_DEVICE(0x5802, 0), /* T522-cr */ | ||
| 2929 | CH_DEVICE(0x5803, 0), /* T540-cr */ | ||
| 2930 | CH_DEVICE(0x5804, 0), /* T520-bch */ | ||
| 2931 | CH_DEVICE(0x5805, 0), /* T540-bch */ | ||
| 2932 | CH_DEVICE(0x5806, 0), /* T540-ch */ | ||
| 2933 | CH_DEVICE(0x5807, 0), /* T520-so */ | ||
| 2934 | CH_DEVICE(0x5808, 0), /* T520-cx */ | ||
| 2935 | CH_DEVICE(0x5809, 0), /* T520-bt */ | ||
| 2936 | CH_DEVICE(0x580a, 0), /* T504-bt */ | ||
| 2937 | CH_DEVICE(0x580b, 0), /* T520-sr */ | ||
| 2938 | CH_DEVICE(0x580c, 0), /* T504-bt */ | ||
| 2939 | CH_DEVICE(0x580d, 0), /* T580-cr */ | ||
| 2940 | CH_DEVICE(0x580e, 0), /* T540-lp-cr */ | ||
| 2941 | CH_DEVICE(0x580f, 0), /* Amsterdam */ | ||
| 2942 | CH_DEVICE(0x5810, 0), /* T580-lp-cr */ | ||
| 2943 | CH_DEVICE(0x5811, 0), /* T520-lp-cr */ | ||
| 2944 | CH_DEVICE(0x5812, 0), /* T560-cr */ | ||
| 2945 | CH_DEVICE(0x5813, 0), /* T580-cr */ | ||
| 2891 | { 0, } | 2946 | { 0, } |
| 2892 | }; | 2947 | }; |
| 2893 | 2948 | ||
| @@ -528,17 +528,21 @@ static void unmap_rx_buf(struct adapter *adapter, struct sge_fl *fl) · 527 unmodified lines | |||
| 528 | */ | 528 | */ |
| 529 | static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl) | 529 | static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl) |
| 530 | { | 530 | { |
| 531 | u32 val; | ||
| 532 | |||
| 531 | /* | 533 | /* |
| 532 | * The SGE keeps track of its Producer and Consumer Indices in terms | 534 | * The SGE keeps track of its Producer and Consumer Indices in terms |
| 533 | * of Egress Queue Units so we can only tell it about integral numbers | 535 | * of Egress Queue Units so we can only tell it about integral numbers |
| 534 | * of multiples of Free List Entries per Egress Queue Units ... | 536 | * of multiples of Free List Entries per Egress Queue Units ... |
| 535 | */ | 537 | */ |
| 536 | if (fl->pend_cred >= FL_PER_EQ_UNIT) { | 538 | if (fl->pend_cred >= FL_PER_EQ_UNIT) { |
| 539 | val = PIDX(fl->pend_cred / FL_PER_EQ_UNIT); | ||
| 540 | if (!is_t4(adapter->chip)) | ||
| 541 | val |= DBTYPE(1); | ||
| 537 | wmb(); | 542 | wmb(); |
| 538 | t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL, | 543 | t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL, |
| 539 | DBPRIO(1) | | 544 | DBPRIO(1) | |
| 540 | QID(fl->cntxt_id) | | 545 | QID(fl->cntxt_id) | val); |
| 541 | PIDX(fl->pend_cred / FL_PER_EQ_UNIT)); | ||
| 542 | fl->pend_cred %= FL_PER_EQ_UNIT; | 546 | fl->pend_cred %= FL_PER_EQ_UNIT; |
| 543 | } | 547 | } |
| 544 | } | 548 | } |
| @@ -1478,7 +1482,8 @@ static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl, · 933 unmodified lines | |||
| 1478 | skb_record_rx_queue(skb, rxq->rspq.idx); | 1482 | skb_record_rx_queue(skb, rxq->rspq.idx); |
| 1479 | 1483 | ||
| 1480 | if (pkt->vlan_ex) { | 1484 | if (pkt->vlan_ex) { |
| 1481 | __vlan_hwaccel_put_tag(skb, be16_to_cpu(pkt->vlan)); | 1485 | __vlan_hwaccel_put_tag(skb, cpu_to_be16(ETH_P_8021Q), |
| 1486 | be16_to_cpu(pkt->vlan)); | ||
| 1482 | rxq->stats.vlan_ex++; | 1487 | rxq->stats.vlan_ex++; |
| 1483 | } | 1488 | } |
| 1484 | ret = napi_gro_frags(&rxq->rspq.napi); | 1489 | ret = napi_gro_frags(&rxq->rspq.napi); |
| @@ -1547,7 +1552,7 @@ int t4vf_ethrx_handler(struct sge_rspq *rspq, const __be64 *rsp, · 62 unmodified lines | |||
| 1547 | 1552 | ||
| 1548 | if (pkt->vlan_ex) { | 1553 | if (pkt->vlan_ex) { |
| 1549 | rxq->stats.vlan_ex++; | 1554 | rxq->stats.vlan_ex++; |
| 1550 | __vlan_hwaccel_put_tag(skb, be16_to_cpu(pkt->vlan)); | 1555 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(pkt->vlan)); |
| 1551 | } | 1556 | } |
| 1552 | 1557 | ||
| 1553 | netif_receive_skb(skb); | 1558 | netif_receive_skb(skb); |
| @@ -38,6 +38,25 @@ · 37 unmodified lines | |||
| 38 | 38 | ||
| 39 | #include "../cxgb4/t4fw_api.h" | 39 | #include "../cxgb4/t4fw_api.h" |
| 40 | 40 | ||
| 41 | #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) | ||
| 42 | #define CHELSIO_CHIP_VERSION(code) ((code) >> 4) | ||
| 43 | #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) | ||
| 44 | |||
| 45 | #define CHELSIO_T4 0x4 | ||
| 46 | #define CHELSIO_T5 0x5 | ||
| 47 | |||
| 48 | enum chip_type { | ||
| 49 | T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 0), | ||
| 50 | T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), | ||
| 51 | T4_A3 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), | ||
| 52 | T4_FIRST_REV = T4_A1, | ||
| 53 | T4_LAST_REV = T4_A3, | ||
| 54 | |||
| 55 | T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), | ||
| 56 | T5_FIRST_REV = T5_A1, | ||
| 57 | T5_LAST_REV = T5_A1, | ||
| 58 | }; | ||
| 59 | |||
| 41 | /* | 60 | /* |
| 42 | * The "len16" field of a Firmware Command Structure ... | 61 | * The "len16" field of a Firmware Command Structure ... |
| 43 | */ | 62 | */ |
| @@ -232,6 +251,11 @@ static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd, · 188 unmodified lines | |||
| 232 | return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false); | 251 | return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false); |
| 233 | } | 252 | } |
| 234 | 253 | ||
| 254 | static inline int is_t4(enum chip_type chip) | ||
| 255 | { | ||
| 256 | return (chip >= T4_FIRST_REV && chip <= T4_LAST_REV); | ||
| 257 | } | ||
| 258 | |||
| 235 | int t4vf_wait_dev_ready(struct adapter *); | 259 | int t4vf_wait_dev_ready(struct adapter *); |
| 236 | int t4vf_port_init(struct adapter *, int); | 260 | int t4vf_port_init(struct adapter *, int); |
| 237 | 261 | ||
| @@ -1027,8 +1027,11 @@ int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free, · 1026 unmodified lines | |||
| 1027 | unsigned nfilters = 0; | 1027 | unsigned nfilters = 0; |
| 1028 | unsigned int rem = naddr; | 1028 | unsigned int rem = naddr; |
| 1029 | struct fw_vi_mac_cmd cmd, rpl; | 1029 | struct fw_vi_mac_cmd cmd, rpl; |
| 1030 | unsigned int max_naddr = is_t4(adapter->chip) ? | ||
| 1031 | NUM_MPS_CLS_SRAM_L_INSTANCES : | ||
| 1032 | NUM_MPS_T5_CLS_SRAM_L_INSTANCES; | ||
| 1030 | 1033 | ||
| 1031 | if (naddr > FW_CLS_TCAM_NUM_ENTRIES) | 1034 | if (naddr > max_naddr) |
| 1032 | return -EINVAL; | 1035 | return -EINVAL; |
| 1033 | 1036 | ||
| 1034 | for (offset = 0; offset < naddr; /**/) { | 1037 | for (offset = 0; offset < naddr; /**/) { |
| @@ -1069,10 +1072,10 @@ int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free, · 34 unmodified lines | |||
| 1069 | 1072 | ||
| 1070 | if (idx) | 1073 | if (idx) |
| 1071 | idx[offset+i] = | 1074 | idx[offset+i] = |
| 1072 | (index >= FW_CLS_TCAM_NUM_ENTRIES | 1075 | (index >= max_naddr |
| 1073 | ? 0xffff | 1076 | ? 0xffff |
| 1074 | : index); | 1077 | : index); |
| 1075 | if (index < FW_CLS_TCAM_NUM_ENTRIES) | 1078 | if (index < max_naddr) |
| 1076 | nfilters++; | 1079 | nfilters++; |
| 1077 | else if (hash) | 1080 | else if (hash) |
| 1078 | *hash |= (1ULL << hash_mac_addr(addr[offset+i])); | 1081 | *hash |= (1ULL << hash_mac_addr(addr[offset+i])); |
| @@ -1118,6 +1121,9 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid, · 39 unmodified lines | |||
| 1118 | struct fw_vi_mac_exact *p = &cmd.u.exact[0]; | 1121 | struct fw_vi_mac_exact *p = &cmd.u.exact[0]; |
| 1119 | size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, | 1122 | size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, |
| 1120 | u.exact[1]), 16); | 1123 | u.exact[1]), 16); |
| 1124 | unsigned int max_naddr = is_t4(adapter->chip) ? | ||
| 1125 | NUM_MPS_CLS_SRAM_L_INSTANCES : | ||
| 1126 | NUM_MPS_T5_CLS_SRAM_L_INSTANCES; | ||
| 1121 | 1127 | ||
| 1122 | /* | 1128 | /* |
| 1123 | * If this is a new allocation, determine whether it should be | 1129 | * If this is a new allocation, determine whether it should be |
| @@ -1140,7 +1146,7 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid, · 16 unmodified lines | |||
| 1140 | if (ret == 0) { | 1146 | if (ret == 0) { |
| 1141 | p = &rpl.u.exact[0]; | 1147 | p = &rpl.u.exact[0]; |
| 1142 | ret = FW_VI_MAC_CMD_IDX_GET(be16_to_cpu(p->valid_to_idx)); | 1148 | ret = FW_VI_MAC_CMD_IDX_GET(be16_to_cpu(p->valid_to_idx)); |
| 1143 | if (ret >= FW_CLS_TCAM_NUM_ENTRIES) | 1149 | if (ret >= max_naddr) |
| 1144 | ret = -ENOMEM; | 1150 | ret = -ENOMEM; |
| 1145 | } | 1151 | } |
| 1146 | return ret; | 1152 | return ret; |
| @@ -101,23 +101,6 @@ static char version[] __initdata = · 100 unmodified lines | |||
| 101 | * them to system IRQ numbers. This mapping is card specific and is set to | 101 | * them to system IRQ numbers. This mapping is card specific and is set to |
| 102 | * the configuration of the Cirrus Eval board for this chip. | 102 | * the configuration of the Cirrus Eval board for this chip. |
| 103 | */ | 103 | */ |
| 104 | #if defined(CONFIG_MACH_IXDP2351) | ||
| 105 | #define CS89x0_NONISA_IRQ | ||
| 106 | static unsigned int netcard_portlist[] __used __initdata = { | ||
| 107 | IXDP2351_VIRT_CS8900_BASE, 0 | ||
| 108 | }; | ||
| 109 | static unsigned int cs8900_irq_map[] = { | ||
| 110 | IRQ_IXDP2351_CS8900, 0, 0, 0 | ||
| 111 | }; | ||
| 112 | #elif defined(CONFIG_ARCH_IXDP2X01) | ||
| 113 | #define CS89x0_NONISA_IRQ | ||
| 114 | static unsigned int netcard_portlist[] __used __initdata = { | ||
| 115 | IXDP2X01_CS8900_VIRT_BASE, 0 | ||
| 116 | }; | ||
| 117 | static unsigned int cs8900_irq_map[] = { | ||
| 118 | IRQ_IXDP2X01_CS8900, 0, 0, 0 | ||
| 119 | }; | ||
| 120 | #else | ||
| 121 | #ifndef CONFIG_CS89x0_PLATFORM | 104 | #ifndef CONFIG_CS89x0_PLATFORM |
| 122 | static unsigned int netcard_portlist[] __used __initdata = { | 105 | static unsigned int netcard_portlist[] __used __initdata = { |
| 123 | 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, | 106 | 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, |
| @@ -127,7 +110,6 @@ static unsigned int cs8900_irq_map[] = { · 3 unmodified lines | |||
| 127 | 10, 11, 12, 5 | 110 | 10, 11, 12, 5 |
| 128 | }; | 111 | }; |
| 129 | #endif | 112 | #endif |
| 130 | #endif | ||
| 131 | 113 | ||
| 132 | #if DEBUGGING | 114 | #if DEBUGGING |
| 133 | static unsigned int net_debug = DEBUGGING; | 115 | static unsigned int net_debug = DEBUGGING; |
| @@ -210,32 +192,6 @@ static int __init media_fn(char *str) · 76 unmodified lines | |||
| 210 | __setup("cs89x0_media=", media_fn); | 192 | __setup("cs89x0_media=", media_fn); |
| 211 | #endif | 193 | #endif |
| 212 | 194 | ||
| 213 | #if defined(CONFIG_MACH_IXDP2351) | ||
| 214 | static u16 | ||
| 215 | readword(unsigned long base_addr, int portno) | ||
| 216 | { | ||
| 217 | return __raw_readw(base_addr + (portno << 1)); | ||
| 218 | } | ||
| 219 | |||
| 220 | static void | ||
| 221 | writeword(unsigned long base_addr, int portno, u16 value) | ||
| 222 | { | ||
| 223 | __raw_writew(value, base_addr + (portno << 1)); | ||
| 224 | } | ||
| 225 | #elif defined(CONFIG_ARCH_IXDP2X01) | ||
| 226 | static u16 | ||
| 227 | readword(unsigned long base_addr, int portno) | ||
| 228 | { | ||
| 229 | return __raw_readl(base_addr + (portno << 1)); | ||
| 230 | } | ||
| 231 | |||
| 232 | static void | ||
| 233 | writeword(unsigned long base_addr, int portno, u16 value) | ||
| 234 | { | ||
| 235 | __raw_writel(value, base_addr + (portno << 1)); | ||
| 236 | } | ||
| 237 | #endif | ||
| 238 | |||
| 239 | static void readwords(struct net_local *lp, int portno, void *buf, int length) | 195 | static void readwords(struct net_local *lp, int portno, void *buf, int length) |
| 240 | { | 196 | { |
| 241 | u8 *buf8 = (u8 *)buf; | 197 | u8 *buf8 = (u8 *)buf; |
| @@ -478,9 +434,6 @@ dma_rx(struct net_device *dev) · 236 unmodified lines | |||
| 478 | /* Malloc up new buffer. */ | 434 | /* Malloc up new buffer. */ |
| 479 | skb = netdev_alloc_skb(dev, length + 2); | 435 | skb = netdev_alloc_skb(dev, length + 2); |
| 480 | if (skb == NULL) { | 436 | if (skb == NULL) { |
| 481 | /* I don't think we want to do this to a stressed system */ | ||
| 482 | cs89_dbg(0, err, "%s: Memory squeeze, dropping packet\n", | ||
| 483 | dev->name); | ||
| 484 | dev->stats.rx_dropped++; | 437 | dev->stats.rx_dropped++; |
| 485 | 438 | ||
| 486 | /* AKPM: advance bp to the next frame */ | 439 | /* AKPM: advance bp to the next frame */ |
| @@ -731,9 +684,6 @@ net_rx(struct net_device *dev) · 244 unmodified lines | |||
| 731 | /* Malloc up new buffer. */ | 684 | /* Malloc up new buffer. */ |
| 732 | skb = netdev_alloc_skb(dev, length + 2); | 685 | skb = netdev_alloc_skb(dev, length + 2); |
| 733 | if (skb == NULL) { | 686 | if (skb == NULL) { |
| 734 | #if 0 /* Again, this seems a cruel thing to do */ | ||
| 735 | pr_warn("%s: Memory squeeze, dropping packet\n", dev->name); | ||
| 736 | #endif | ||
| 737 | dev->stats.rx_dropped++; | 687 | dev->stats.rx_dropped++; |
| 738 | return; | 688 | return; |
| 739 | } | 689 | } |
| @@ -908,7 +858,7 @@ net_open(struct net_device *dev) · 168 unmodified lines | |||
| 908 | goto bad_out; | 858 | goto bad_out; |
| 909 | } | 859 | } |
| 910 | } else { | 860 | } else { |
| 911 | #if !defined(CS89x0_NONISA_IRQ) && !defined(CONFIG_CS89x0_PLATFORM) | 861 | #if !defined(CONFIG_CS89x0_PLATFORM) |
| 912 | if (((1 << dev->irq) & lp->irq_map) == 0) { | 862 | if (((1 << dev->irq) & lp->irq_map) == 0) { |
| 913 | pr_err("%s: IRQ %d is not in our map of allowable IRQs, which is %x\n", | 863 | pr_err("%s: IRQ %d is not in our map of allowable IRQs, which is %x\n", |
| 914 | dev->name, dev->irq, lp->irq_map); | 864 | dev->name, dev->irq, lp->irq_map); |
| @@ -1321,9 +1271,7 @@ static const struct net_device_ops net_ops = { · 406 unmodified lines | |||
| 1321 | static void __init reset_chip(struct net_device *dev) | 1271 | static void __init reset_chip(struct net_device *dev) |
| 1322 | { | 1272 | { |
| 1323 | #if !defined(CONFIG_MACH_MX31ADS) | 1273 | #if !defined(CONFIG_MACH_MX31ADS) |
| 1324 | #if !defined(CS89x0_NONISA_IRQ) | ||
| 1325 | struct net_local *lp = netdev_priv(dev); | 1274 | struct net_local *lp = netdev_priv(dev); |
| 1326 | #endif /* CS89x0_NONISA_IRQ */ | ||
| 1327 | int reset_start_time; | 1275 | int reset_start_time; |
| 1328 | 1276 | ||
| 1329 | writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET); | 1277 | writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET); |
| @@ -1331,7 +1279,6 @@ static void __init reset_chip(struct net_device *dev) · 1 unmodified line | |||
| 1331 | /* wait 30 ms */ | 1279 | /* wait 30 ms */ |
| 1332 | msleep(30); | 1280 | msleep(30); |
| 1333 | 1281 | ||
| 1334 | #if !defined(CS89x0_NONISA_IRQ) | ||
| 1335 | if (lp->chip_type != CS8900) { | 1282 | if (lp->chip_type != CS8900) { |
| 1336 | /* Hardware problem requires PNP registers to be reconfigured after a reset */ | 1283 | /* Hardware problem requires PNP registers to be reconfigured after a reset */ |
| 1337 | iowrite16(PP_CS8920_ISAINT, lp->virt_addr + ADD_PORT); | 1284 | iowrite16(PP_CS8920_ISAINT, lp->virt_addr + ADD_PORT); |
| @@ -1344,7 +1291,6 @@ static void __init reset_chip(struct net_device *dev) · 6 unmodified lines | |||
| 1344 | iowrite8((dev->mem_start >> 8) & 0xff, | 1291 | iowrite8((dev->mem_start >> 8) & 0xff, |
| 1345 | lp->virt_addr + DATA_PORT + 1); | 1292 | lp->virt_addr + DATA_PORT + 1); |
| 1346 | } | 1293 | } |
| 1347 | #endif /* CS89x0_NONISA_IRQ */ | ||
| 1348 | 1294 | ||
| 1349 | /* Wait until the chip is reset */ | 1295 | /* Wait until the chip is reset */ |
| 1350 | reset_start_time = jiffies; | 1296 | reset_start_time = jiffies; |
| @@ -1579,9 +1525,6 @@ cs89x0_probe1(struct net_device *dev, void __iomem *ioaddr, int modular) · 228 unmodified lines | |||
| 1579 | i = lp->isa_config & INT_NO_MASK; | 1525 | i = lp->isa_config & INT_NO_MASK; |
| 1580 | #ifndef CONFIG_CS89x0_PLATFORM | 1526 | #ifndef CONFIG_CS89x0_PLATFORM |
| 1581 | if (lp->chip_type == CS8900) { | 1527 | if (lp->chip_type == CS8900) { |
| 1582 | #ifdef CS89x0_NONISA_IRQ | ||
| 1583 | i = cs8900_irq_map[0]; | ||
| 1584 | #else | ||
| 1585 | /* Translate the IRQ using the IRQ mapping table. */ | 1528 | /* Translate the IRQ using the IRQ mapping table. */ |
| 1586 | if (i >= ARRAY_SIZE(cs8900_irq_map)) | 1529 | if (i >= ARRAY_SIZE(cs8900_irq_map)) |
| 1587 | pr_err("invalid ISA interrupt number %d\n", i); | 1530 | pr_err("invalid ISA interrupt number %d\n", i); |
| @@ -1599,7 +1542,6 @@ cs89x0_probe1(struct net_device *dev, void __iomem *ioaddr, int modular) · 11 unmodified lines | |||
| 1599 | lp->irq_map = ((irq_map_buff[0] >> 8) | | 1542 | lp->irq_map = ((irq_map_buff[0] >> 8) | |
| 1600 | (irq_map_buff[1] << 8)); | 1543 | (irq_map_buff[1] << 8)); |
| 1601 | } | 1544 | } |
| 1602 | #endif | ||
| 1603 | } | 1545 | } |
| 1604 | #endif | 1546 | #endif |
| 1605 | if (!dev->irq) | 1547 | if (!dev->irq) |
| @@ -1978,18 +1920,6 @@ static struct platform_driver cs89x0_driver = { · 372 unmodified lines | |||
| 1978 | .remove = cs89x0_platform_remove, | 1920 | .remove = cs89x0_platform_remove, |
| 1979 | }; | 1921 | }; |
| 1980 | 1922 | ||
| 1981 | static int __init cs89x0_init(void) | 1923 | module_platform_driver_probe(cs89x0_driver, cs89x0_platform_probe); |
| 1982 | { | ||
| 1983 | return platform_driver_probe(&cs89x0_driver, cs89x0_platform_probe); | ||
| 1984 | } | ||
| 1985 | |||
| 1986 | module_init(cs89x0_init); | ||
| 1987 | |||
| 1988 | static void __exit cs89x0_cleanup(void) | ||
| 1989 | { | ||
| 1990 | platform_driver_unregister(&cs89x0_driver); | ||
| 1991 | } | ||
| 1992 | |||
| 1993 | module_exit(cs89x0_cleanup); | ||
| 1994 | 1924 | ||
| 1995 | #endif /* CONFIG_CS89x0_PLATFORM */ | 1925 | #endif /* CONFIG_CS89x0_PLATFORM */ |
| @@ -887,18 +887,7 @@ static struct platform_driver ep93xx_eth_driver = { · 886 unmodified lines | |||
| 887 | }, | 887 | }, |
| 888 | }; | 888 | }; |
| 889 | 889 | ||
| 890 | static int __init ep93xx_eth_init_module(void) | 890 | module_platform_driver(ep93xx_eth_driver); |
| 891 | { | ||
| 892 | printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n"); | ||
| 893 | return platform_driver_register(&ep93xx_eth_driver); | ||
| 894 | } | ||
| 895 | |||
| 896 | static void __exit ep93xx_eth_cleanup_module(void) | ||
| 897 | { | ||
| 898 | platform_driver_unregister(&ep93xx_eth_driver); | ||
| 899 | } | ||
| 900 | 891 | ||
| 901 | module_init(ep93xx_eth_init_module); | ||
| 902 | module_exit(ep93xx_eth_cleanup_module); | ||
| 903 | MODULE_LICENSE("GPL"); | 892 | MODULE_LICENSE("GPL"); |
| 904 | MODULE_ALIAS("platform:ep93xx-eth"); | 893 | MODULE_ALIAS("platform:ep93xx-eth"); |
| @@ -212,7 +212,7 @@ int enic_dev_deinit_done(struct enic *enic, int *status) · 211 unmodified lines | |||
| 212 | } | 212 | } |
| 213 | 213 | ||
| 214 | /* rtnl lock is held */ | 214 | /* rtnl lock is held */ |
| 215 | int enic_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | 215 | int enic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid) |
| 216 | { | 216 | { |
| 217 | struct enic *enic = netdev_priv(netdev); | 217 | struct enic *enic = netdev_priv(netdev); |
| 218 | int err; | 218 | int err; |
| @@ -225,7 +225,7 @@ int enic_vlan_rx_add_vid(struct net_device *netdev, u16 vid) · 6 unmodified lines | |||
| 225 | } | 225 | } |
| 226 | 226 | ||
| 227 | /* rtnl lock is held */ | 227 | /* rtnl lock is held */ |
| 228 | int enic_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | 228 | int enic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) |
| 229 | { | 229 | { |
| 230 | struct enic *enic = netdev_priv(netdev); | 230 | struct enic *enic = netdev_priv(netdev); |
| 231 | int err; | 231 | int err; |
| @@ -46,8 +46,8 @@ int enic_dev_packet_filter(struct enic *enic, int directed, int multicast, · 45 unmodified lines | |||
| 46 | int broadcast, int promisc, int allmulti); | 46 | int broadcast, int promisc, int allmulti); |
| 47 | int enic_dev_add_addr(struct enic *enic, u8 *addr); | 47 | int enic_dev_add_addr(struct enic *enic, u8 *addr); |
| 48 | int enic_dev_del_addr(struct enic *enic, u8 *addr); | 48 | int enic_dev_del_addr(struct enic *enic, u8 *addr); |
| 49 | int enic_vlan_rx_add_vid(struct net_device *netdev, u16 vid); | 49 | int enic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid); |
| 50 | int enic_vlan_rx_kill_vid(struct net_device *netdev, u16 vid); | 50 | int enic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid); |
| 51 | int enic_dev_notify_unset(struct enic *enic); | 51 | int enic_dev_notify_unset(struct enic *enic); |
| 52 | int enic_dev_hang_notify(struct enic *enic); | 52 | int enic_dev_hang_notify(struct enic *enic); |
| 53 | int enic_dev_set_ig_vlan_rewrite_mode(struct enic *enic); | 53 | int enic_dev_set_ig_vlan_rewrite_mode(struct enic *enic); |
| @@ -1300,7 +1300,7 @@ static void enic_rq_indicate_buf(struct vnic_rq *rq, · 1299 unmodified lines | |||
| 1300 | } | 1300 | } |
| 1301 | 1301 | ||
| 1302 | if (vlan_stripped) | 1302 | if (vlan_stripped) |
| 1303 | __vlan_hwaccel_put_tag(skb, vlan_tci); | 1303 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci); |
| 1304 | 1304 | ||
| 1305 | if (netdev->features & NETIF_F_GRO) | 1305 | if (netdev->features & NETIF_F_GRO) |
| 1306 | napi_gro_receive(&enic->napi[q_number], skb); | 1306 | napi_gro_receive(&enic->napi[q_number], skb); |
| @@ -2496,9 +2496,9 @@ static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) · 1189 unmodified lines | |||
| 2496 | netdev->watchdog_timeo = 2 * HZ; | 2496 | netdev->watchdog_timeo = 2 * HZ; |
| 2497 | netdev->ethtool_ops = &enic_ethtool_ops; | 2497 | netdev->ethtool_ops = &enic_ethtool_ops; |
| 2498 | 2498 | ||
| 2499 | netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | 2499 | netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
| 2500 | if (ENIC_SETTING(enic, LOOP)) { | 2500 | if (ENIC_SETTING(enic, LOOP)) { |
| 2501 | netdev->features &= ~NETIF_F_HW_VLAN_TX; | 2501 | netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 2502 | enic->loop_enable = 1; | 2502 | enic->loop_enable = 1; |
| 2503 | enic->loop_tag = enic->config.loop_tag; | 2503 | enic->loop_tag = enic->config.loop_tag; |
| 2504 | dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag); | 2504 | dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag); |
| @@ -308,6 +308,9 @@ static int _vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd, · 307 unmodified lines | |||
| 308 | 308 | ||
| 309 | if (status & STAT_ERROR) { | 309 | if (status & STAT_ERROR) { |
| 310 | err = (int)readq(&devcmd->args[0]); | 310 | err = (int)readq(&devcmd->args[0]); |
| 311 | if (err == ERR_EINVAL && | ||
| 312 | cmd == CMD_CAPABILITY) | ||
| 313 | return err; | ||
| 311 | if (err != ERR_ECMDUNKNOWN || | 314 | if (err != ERR_ECMDUNKNOWN || |
| 312 | cmd != CMD_CAPABILITY) | 315 | cmd != CMD_CAPABILITY) |
| 313 | pr_err("Error %d devcmd %d\n", | 316 | pr_err("Error %d devcmd %d\n", |
| @@ -1693,22 +1693,7 @@ static struct platform_driver dm9000_driver = { · 1692 unmodified lines | |||
| 1693 | .remove = dm9000_drv_remove, | 1693 | .remove = dm9000_drv_remove, |
| 1694 | }; | 1694 | }; |
| 1695 | 1695 | ||
| 1696 | static int __init | 1696 | module_platform_driver(dm9000_driver); |
| 1697 | dm9000_init(void) | ||
| 1698 | { | ||
| 1699 | printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); | ||
| 1700 | |||
| 1701 | return platform_driver_register(&dm9000_driver); | ||
| 1702 | } | ||
| 1703 | |||
| 1704 | static void __exit | ||
| 1705 | dm9000_cleanup(void) | ||
| 1706 | { | ||
| 1707 | platform_driver_unregister(&dm9000_driver); | ||
| 1708 | } | ||
| 1709 | |||
| 1710 | module_init(dm9000_init); | ||
| 1711 | module_exit(dm9000_cleanup); | ||
| 1712 | 1697 | ||
| 1713 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); | 1698 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); |
| 1714 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); | 1699 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); |
| @@ -236,17 +236,14 @@ static int xircom_probe(struct pci_dev *pdev, const struct pci_device_id *id) · 235 unmodified lines | |||
| 236 | private->rx_buffer = dma_alloc_coherent(d, 8192, | 236 | private->rx_buffer = dma_alloc_coherent(d, 8192, |
| 237 | &private->rx_dma_handle, | 237 | &private->rx_dma_handle, |
| 238 | GFP_KERNEL); | 238 | GFP_KERNEL); |
| 239 | if (private->rx_buffer == NULL) { | 239 | if (private->rx_buffer == NULL) |
| 240 | pr_err("%s: no memory for rx buffer\n", __func__); | ||
| 241 | goto rx_buf_fail; | 240 | goto rx_buf_fail; |
| 242 | } | 241 | |
| 243 | private->tx_buffer = dma_alloc_coherent(d, 8192, | 242 | private->tx_buffer = dma_alloc_coherent(d, 8192, |
| 244 | &private->tx_dma_handle, | 243 | &private->tx_dma_handle, |
| 245 | GFP_KERNEL); | 244 | GFP_KERNEL); |
| 246 | if (private->tx_buffer == NULL) { | 245 | if (private->tx_buffer == NULL) |
| 247 | pr_err("%s: no memory for tx buffer\n", __func__); | ||
| 248 | goto tx_buf_fail; | 246 | goto tx_buf_fail; |
| 249 | } | ||
| 250 | 247 | ||
| 251 | SET_NETDEV_DEV(dev, &pdev->dev); | 248 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 252 | 249 | ||
| @@ -580,12 +580,9 @@ alloc_list (struct net_device *dev) · 579 unmodified lines | |||
| 580 | 580 | ||
| 581 | skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); | 581 | skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); |
| 582 | np->rx_skbuff[i] = skb; | 582 | np->rx_skbuff[i] = skb; |
| 583 | if (skb == NULL) { | 583 | if (skb == NULL) |
| 584 | printk (KERN_ERR | ||
| 585 | "%s: alloc_list: allocate Rx buffer error! ", | ||
| 586 | dev->name); | ||
| 587 | break; | 584 | break; |
| 588 | } | 585 | |
| 589 | /* Rubicon now supports 40 bits of addressing space. */ | 586 | /* Rubicon now supports 40 bits of addressing space. */ |
| 590 | np->rx_ring[i].fraginfo = | 587 | np->rx_ring[i].fraginfo = |
| 591 | cpu_to_le64 ( pci_map_single ( | 588 | cpu_to_le64 ( pci_map_single ( |
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2005 - 2011 Emulex | 2 | * Copyright (C) 2005 - 2013 Emulex |
| 3 | * All rights reserved. | 3 | * All rights reserved. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
| @@ -214,6 +214,7 @@ struct be_tx_stats { · 208 unmodified lines | |||
| 214 | }; | 214 | }; |
| 215 | 215 | ||
| 216 | struct be_tx_obj { | 216 | struct be_tx_obj { |
| 217 | u32 db_offset; | ||
| 217 | struct be_queue_info q; | 218 | struct be_queue_info q; |
| 218 | struct be_queue_info cq; | 219 | struct be_queue_info cq; |
| 219 | /* Remember the skbs that were transmitted */ | 220 | /* Remember the skbs that were transmitted */ |
| @@ -292,7 +293,7 @@ struct be_drv_stats { · 72 unmodified lines | |||
| 292 | u32 rx_in_range_errors; | 293 | u32 rx_in_range_errors; |
| 293 | u32 rx_out_range_errors; | 294 | u32 rx_out_range_errors; |
| 294 | u32 rx_frame_too_long; | 295 | u32 rx_frame_too_long; |
| 295 | u32 rx_address_mismatch_drops; | 296 | u32 rx_address_filtered; |
| 296 | u32 rx_dropped_too_small; | 297 | u32 rx_dropped_too_small; |
| 297 | u32 rx_dropped_too_short; | 298 | u32 rx_dropped_too_short; |
| 298 | u32 rx_dropped_header_too_small; | 299 | u32 rx_dropped_header_too_small; |
| @@ -328,6 +329,7 @@ enum vf_state { · 29 unmodified lines | |||
| 328 | #define BE_FLAGS_WORKER_SCHEDULED (1 << 3) | 329 | #define BE_FLAGS_WORKER_SCHEDULED (1 << 3) |
| 329 | #define BE_UC_PMAC_COUNT 30 | 330 | #define BE_UC_PMAC_COUNT 30 |
| 330 | #define BE_VF_UC_PMAC_COUNT 2 | 331 | #define BE_VF_UC_PMAC_COUNT 2 |
| 332 | #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD (1 << 11) | ||
| 331 | 333 | ||
| 332 | struct phy_info { | 334 | struct phy_info { |
| 333 | u8 transceiver; | 335 | u8 transceiver; |
| @@ -434,6 +436,8 @@ struct be_adapter { · 100 unmodified lines | |||
| 434 | u8 wol_cap; | 436 | u8 wol_cap; |
| 435 | bool wol; | 437 | bool wol; |
| 436 | u32 uc_macs; /* Count of secondary UC MAC programmed */ | 438 | u32 uc_macs; /* Count of secondary UC MAC programmed */ |
| 439 | u16 asic_rev; | ||
| 440 | u16 qnq_vid; | ||
| 437 | u32 msg_enable; | 441 | u32 msg_enable; |
| 438 | int be_get_temp_freq; | 442 | int be_get_temp_freq; |
| 439 | u16 max_mcast_mac; | 443 | u16 max_mcast_mac; |
| @@ -445,6 +449,7 @@ struct be_adapter { · 5 unmodified lines | |||
| 445 | u16 max_event_queues; | 449 | u16 max_event_queues; |
| 446 | u32 if_cap_flags; | 450 | u32 if_cap_flags; |
| 447 | u8 pf_number; | 451 | u8 pf_number; |
| 452 | u64 rss_flags; | ||
| 448 | }; | 453 | }; |
| 449 | 454 | ||
| 450 | #define be_physfn(adapter) (!adapter->virtfn) | 455 | #define be_physfn(adapter) (!adapter->virtfn) |
| @@ -648,6 +653,11 @@ static inline bool be_is_wol_excluded(struct be_adapter *adapter) · 197 unmodified lines | |||
| 648 | } | 653 | } |
| 649 | } | 654 | } |
| 650 | 655 | ||
| 656 | static inline int qnq_async_evt_rcvd(struct be_adapter *adapter) | ||
| 657 | { | ||
| 658 | return adapter->flags & BE_FLAGS_QNQ_ASYNC_EVT_RCVD; | ||
| 659 | } | ||
| 660 | |||
| 651 | extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, | 661 | extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, |
| 652 | u16 num_popped); | 662 | u16 num_popped); |
| 653 | extern void be_link_status_update(struct be_adapter *adapter, u8 link_status); | 663 | extern void be_link_status_update(struct be_adapter *adapter, u8 link_status); |
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2005 - 2011 Emulex | 2 | * Copyright (C) 2005 - 2013 Emulex |
| 3 | * All rights reserved. | 3 | * All rights reserved. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
| @@ -263,6 +263,27 @@ static void be_async_grp5_evt_process(struct be_adapter *adapter, · 257 unmodified lines | |||
| 263 | } | 263 | } |
| 264 | } | 264 | } |
| 265 | 265 | ||
| 266 | static void be_async_dbg_evt_process(struct be_adapter *adapter, | ||
| 267 | u32 trailer, struct be_mcc_compl *cmp) | ||
| 268 | { | ||
| 269 | u8 event_type = 0; | ||
| 270 | struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp; | ||
| 271 | |||
| 272 | event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) & | ||
| 273 | ASYNC_TRAILER_EVENT_TYPE_MASK; | ||
| 274 | |||
| 275 | switch (event_type) { | ||
| 276 | case ASYNC_DEBUG_EVENT_TYPE_QNQ: | ||
| 277 | if (evt->valid) | ||
| 278 | adapter->qnq_vid = le16_to_cpu(evt->vlan_tag); | ||
| 279 | adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD; | ||
| 280 | break; | ||
| 281 | default: | ||
| 282 | dev_warn(&adapter->pdev->dev, "Unknown debug event\n"); | ||
| 283 | break; | ||
| 284 | } | ||
| 285 | } | ||
| 286 | |||
| 266 | static inline bool is_link_state_evt(u32 trailer) | 287 | static inline bool is_link_state_evt(u32 trailer) |
| 267 | { | 288 | { |
| 268 | return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | 289 | return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & |
| @@ -277,6 +298,13 @@ static inline bool is_grp5_evt(u32 trailer) · 8 unmodified lines | |||
| 277 | ASYNC_EVENT_CODE_GRP_5); | 298 | ASYNC_EVENT_CODE_GRP_5); |
| 278 | } | 299 | } |
| 279 | 300 | ||
| 301 | static inline bool is_dbg_evt(u32 trailer) | ||
| 302 | { | ||
| 303 | return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | ||
| 304 | ASYNC_TRAILER_EVENT_CODE_MASK) == | ||
| 305 | ASYNC_EVENT_CODE_QNQ); | ||
| 306 | } | ||
| 307 | |||
| 280 | static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) | 308 | static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) |
| 281 | { | 309 | { |
| 282 | struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; | 310 | struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; |
| @@ -325,6 +353,9 @@ int be_process_mcc(struct be_adapter *adapter) · 42 unmodified lines | |||
| 325 | else if (is_grp5_evt(compl->flags)) | 353 | else if (is_grp5_evt(compl->flags)) |
| 326 | be_async_grp5_evt_process(adapter, | 354 | be_async_grp5_evt_process(adapter, |
| 327 | compl->flags, compl); | 355 | compl->flags, compl); |
| 356 | else if (is_dbg_evt(compl->flags)) | ||
| 357 | be_async_dbg_evt_process(adapter, | ||
| 358 | compl->flags, compl); | ||
| 328 | } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { | 359 | } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { |
| 329 | status = be_mcc_compl_process(adapter, compl); | 360 | status = be_mcc_compl_process(adapter, compl); |
| 330 | atomic_dec(&mcc_obj->q.used); | 361 | atomic_dec(&mcc_obj->q.used); |
| @@ -687,10 +718,8 @@ static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) · 356 unmodified lines | |||
| 687 | if (!mccq->created) | 718 | if (!mccq->created) |
| 688 | return NULL; | 719 | return NULL; |
| 689 | 720 | ||
| 690 | if (atomic_read(&mccq->used) >= mccq->len) { | 721 | if (atomic_read(&mccq->used) >= mccq->len) |
| 691 | dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n"); | ||
| 692 | return NULL; | 722 | return NULL; |
| 693 | } | ||
| 694 | 723 | ||
| 695 | wrb = queue_head_node(mccq); | 724 | wrb = queue_head_node(mccq); |
| 696 | queue_head_inc(mccq); | 725 | queue_head_inc(mccq); |
| @@ -1022,6 +1051,7 @@ int be_cmd_mccq_ext_create(struct be_adapter *adapter, · 325 unmodified lines | |||
| 1022 | 1051 | ||
| 1023 | /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */ | 1052 | /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */ |
| 1024 | req->async_event_bitmap[0] = cpu_to_le32(0x00000022); | 1053 | req->async_event_bitmap[0] = cpu_to_le32(0x00000022); |
| 1054 | req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ); | ||
| 1025 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | 1055 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
| 1026 | 1056 | ||
| 1027 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | 1057 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); |
| @@ -1095,15 +1125,14 @@ int be_cmd_mccq_create(struct be_adapter *adapter, · 67 unmodified lines | |||
| 1095 | return status; | 1125 | return status; |
| 1096 | } | 1126 | } |
| 1097 | 1127 | ||
| 1098 | int be_cmd_txq_create(struct be_adapter *adapter, | 1128 | int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo) |
| 1099 | struct be_queue_info *txq, | ||
| 1100 | struct be_queue_info *cq) | ||
| 1101 | { | 1129 | { |
| 1102 | struct be_mcc_wrb *wrb; | 1130 | struct be_mcc_wrb *wrb; |
| 1103 | struct be_cmd_req_eth_tx_create *req; | 1131 | struct be_cmd_req_eth_tx_create *req; |
| 1132 | struct be_queue_info *txq = &txo->q; | ||
| 1133 | struct be_queue_info *cq = &txo->cq; | ||
| 1104 | struct be_dma_mem *q_mem = &txq->dma_mem; | 1134 | struct be_dma_mem *q_mem = &txq->dma_mem; |
| 1105 | void *ctxt; | 1135 | int status, ver = 0; |
| 1106 | int status; | ||
| 1107 | 1136 | ||
| 1108 | spin_lock_bh(&adapter->mcc_lock); | 1137 | spin_lock_bh(&adapter->mcc_lock); |
| 1109 | 1138 | ||
| @@ -1114,34 +1143,37 @@ int be_cmd_txq_create(struct be_adapter *adapter, · 4 unmodified lines | |||
| 1114 | } | 1143 | } |
| 1115 | 1144 | ||
| 1116 | req = embedded_payload(wrb); | 1145 | req = embedded_payload(wrb); |
| 1117 | ctxt = &req->context; | ||
| 1118 | 1146 | ||
| 1119 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | 1147 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, |
| 1120 | OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL); | 1148 | OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL); |
| 1121 | 1149 | ||
| 1122 | if (lancer_chip(adapter)) { | 1150 | if (lancer_chip(adapter)) { |
| 1123 | req->hdr.version = 1; | 1151 | req->hdr.version = 1; |
| 1124 | AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt, | 1152 | req->if_id = cpu_to_le16(adapter->if_handle); |
| 1125 | adapter->if_handle); | 1153 | } else if (BEx_chip(adapter)) { |
| 1154 | if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC) | ||
| 1155 | req->hdr.version = 2; | ||
| 1156 | } else { /* For SH */ | ||
| 1157 | req->hdr.version = 2; | ||
| 1126 | } | 1158 | } |
| 1127 | 1159 | ||
| 1128 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | 1160 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); |
| 1129 | req->ulp_num = BE_ULP1_NUM; | 1161 | req->ulp_num = BE_ULP1_NUM; |
| 1130 | req->type = BE_ETH_TX_RING_TYPE_STANDARD; | 1162 | req->type = BE_ETH_TX_RING_TYPE_STANDARD; |
| 1131 | 1163 | req->cq_id = cpu_to_le16(cq->id); | |
| 1132 | AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, | 1164 | req->queue_size = be_encoded_q_len(txq->len); |
| 1133 | be_encoded_q_len(txq->len)); | ||
| 1134 | AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); | ||
| 1135 | AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); | ||
| 1136 | |||
| 1137 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | ||
| 1138 | |||
| 1139 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | 1165 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); |
| 1140 | 1166 | ||
| 1167 | ver = req->hdr.version; | ||
| 1168 | |||
| 1141 | status = be_mcc_notify_wait(adapter); | 1169 | status = be_mcc_notify_wait(adapter); |
| 1142 | if (!status) { | 1170 | if (!status) { |
| 1143 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); | 1171 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); |
| 1144 | txq->id = le16_to_cpu(resp->cid); | 1172 | txq->id = le16_to_cpu(resp->cid); |
| 1173 | if (ver == 2) | ||
| 1174 | txo->db_offset = le32_to_cpu(resp->db_offset); | ||
| 1175 | else | ||
| 1176 | txo->db_offset = DB_TXULP1_OFFSET; | ||
| 1145 | txq->created = true; | 1177 | txq->created = true; |
| 1146 | } | 1178 | } |
| 1147 | 1179 | ||
| @@ -1834,7 +1866,7 @@ err: · 686 unmodified lines | |||
| 1834 | 1866 | ||
| 1835 | /* Uses mbox */ | 1867 | /* Uses mbox */ |
| 1836 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, | 1868 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, |
| 1837 | u32 *mode, u32 *caps) | 1869 | u32 *mode, u32 *caps, u16 *asic_rev) |
| 1838 | { | 1870 | { |
| 1839 | struct be_mcc_wrb *wrb; | 1871 | struct be_mcc_wrb *wrb; |
| 1840 | struct be_cmd_req_query_fw_cfg *req; | 1872 | struct be_cmd_req_query_fw_cfg *req; |
| @@ -1855,6 +1887,7 @@ int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, · 14 unmodified lines | |||
| 1855 | *port_num = le32_to_cpu(resp->phys_port); | 1887 | *port_num = le32_to_cpu(resp->phys_port); |
| 1856 | *mode = le32_to_cpu(resp->function_mode); | 1888 | *mode = le32_to_cpu(resp->function_mode); |
| 1857 | *caps = le32_to_cpu(resp->function_caps); | 1889 | *caps = le32_to_cpu(resp->function_caps); |
| 1890 | *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF; | ||
| 1858 | } | 1891 | } |
| 1859 | 1892 | ||
| 1860 | mutex_unlock(&adapter->mbox_lock); | 1893 | mutex_unlock(&adapter->mbox_lock); |
| @@ -1897,7 +1930,8 @@ int be_cmd_reset_function(struct be_adapter *adapter) · 36 unmodified lines | |||
| 1897 | return status; | 1930 | return status; |
| 1898 | } | 1931 | } |
| 1899 | 1932 | ||
| 1900 | int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size) | 1933 | int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, |
| 1934 | u32 rss_hash_opts, u16 table_size) | ||
| 1901 | { | 1935 | { |
| 1902 | struct be_mcc_wrb *wrb; | 1936 | struct be_mcc_wrb *wrb; |
| 1903 | struct be_cmd_req_rss_config *req; | 1937 | struct be_cmd_req_rss_config *req; |
| @@ -1916,16 +1950,12 @@ int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size) · 12 unmodified lines | |||
| 1916 | OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL); | 1950 | OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL); |
| 1917 | 1951 | ||
| 1918 | req->if_id = cpu_to_le32(adapter->if_handle); | 1952 | req->if_id = cpu_to_le32(adapter->if_handle); |
| 1919 | req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 | | 1953 | req->enable_rss = cpu_to_le16(rss_hash_opts); |
| 1920 | RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6); | 1954 | req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); |
| 1921 | 1955 | ||
| 1922 | if (lancer_chip(adapter) || skyhawk_chip(adapter)) { | 1956 | if (lancer_chip(adapter) || skyhawk_chip(adapter)) |
| 1923 | req->hdr.version = 1; | 1957 | req->hdr.version = 1; |
| 1924 | req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 | | ||
| 1925 | RSS_ENABLE_UDP_IPV6); | ||
| 1926 | } | ||
| 1927 | 1958 | ||
| 1928 | req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); | ||
| 1929 | memcpy(req->cpu_table, rsstable, table_size); | 1959 | memcpy(req->cpu_table, rsstable, table_size); |
| 1930 | memcpy(req->hash, myhash, sizeof(myhash)); | 1960 | memcpy(req->hash, myhash, sizeof(myhash)); |
| 1931 | be_dws_cpu_to_le(req->hash, sizeof(req->hash)); | 1961 | be_dws_cpu_to_le(req->hash, sizeof(req->hash)); |
| @@ -2343,7 +2373,6 @@ int be_cmd_get_seeprom_data(struct be_adapter *adapter, · 411 unmodified lines | |||
| 2343 | { | 2373 | { |
| 2344 | struct be_mcc_wrb *wrb; | 2374 | struct be_mcc_wrb *wrb; |
| 2345 | struct be_cmd_req_seeprom_read *req; | 2375 | struct be_cmd_req_seeprom_read *req; |
| 2346 | struct be_sge *sge; | ||
| 2347 | int status; | 2376 | int status; |
| 2348 | 2377 | ||
| 2349 | spin_lock_bh(&adapter->mcc_lock); | 2378 | spin_lock_bh(&adapter->mcc_lock); |
| @@ -2354,7 +2383,6 @@ int be_cmd_get_seeprom_data(struct be_adapter *adapter, · 4 unmodified lines | |||
| 2354 | goto err; | 2383 | goto err; |
| 2355 | } | 2384 | } |
| 2356 | req = nonemb_cmd->va; | 2385 | req = nonemb_cmd->va; |
| 2357 | sge = nonembedded_sgl(wrb); | ||
| 2358 | 2386 | ||
| 2359 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | 2387 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
| 2360 | OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb, | 2388 | OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb, |
| @@ -2461,6 +2489,9 @@ int be_cmd_get_cntl_attributes(struct be_adapter *adapter) · 100 unmodified lines | |||
| 2461 | struct mgmt_controller_attrib *attribs; | 2489 | struct mgmt_controller_attrib *attribs; |
| 2462 | struct be_dma_mem attribs_cmd; | 2490 | struct be_dma_mem attribs_cmd; |
| 2463 | 2491 | ||
| 2492 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | ||
| 2493 | return -1; | ||
| 2494 | |||
| 2464 | memset(&attribs_cmd, 0, sizeof(struct be_dma_mem)); | 2495 | memset(&attribs_cmd, 0, sizeof(struct be_dma_mem)); |
| 2465 | attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs); | 2496 | attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs); |
| 2466 | attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size, | 2497 | attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size, |
| @@ -2468,12 +2499,10 @@ int be_cmd_get_cntl_attributes(struct be_adapter *adapter) · 1 unmodified line | |||
| 2468 | if (!attribs_cmd.va) { | 2499 | if (!attribs_cmd.va) { |
| 2469 | dev_err(&adapter->pdev->dev, | 2500 | dev_err(&adapter->pdev->dev, |
| 2470 | "Memory allocation failure\n"); | 2501 | "Memory allocation failure\n"); |
| 2471 | return -ENOMEM; | 2502 | status = -ENOMEM; |
| 2503 | goto err; | ||
| 2472 | } | 2504 | } |
| 2473 | 2505 | ||
| 2474 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | ||
| 2475 | return -1; | ||
| 2476 | |||
| 2477 | wrb = wrb_from_mbox(adapter); | 2506 | wrb = wrb_from_mbox(adapter); |
| 2478 | if (!wrb) { | 2507 | if (!wrb) { |
| 2479 | status = -EBUSY; | 2508 | status = -EBUSY; |
| @@ -2493,8 +2522,9 @@ int be_cmd_get_cntl_attributes(struct be_adapter *adapter) · 13 unmodified lines | |||
| 2493 | 2522 | ||
| 2494 | err: | 2523 | err: |
| 2495 | mutex_unlock(&adapter->mbox_lock); | 2524 | mutex_unlock(&adapter->mbox_lock); |
| 2496 | pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va, | 2525 | if (attribs_cmd.va) |
| 2497 | attribs_cmd.dma); | 2526 | pci_free_consistent(adapter->pdev, attribs_cmd.size, |
| 2527 | attribs_cmd.va, attribs_cmd.dma); | ||
| 2498 | return status; | 2528 | return status; |
| 2499 | } | 2529 | } |
| 2500 | 2530 | ||
| @@ -2667,10 +2697,8 @@ int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, · 166 unmodified lines | |||
| 2667 | cmd.size = sizeof(struct be_cmd_req_set_mac_list); | 2697 | cmd.size = sizeof(struct be_cmd_req_set_mac_list); |
| 2668 | cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, | 2698 | cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, |
| 2669 | &cmd.dma, GFP_KERNEL); | 2699 | &cmd.dma, GFP_KERNEL); |
| 2670 | if (!cmd.va) { | 2700 | if (!cmd.va) |
| 2671 | dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); | ||
| 2672 | return -ENOMEM; | 2701 | return -ENOMEM; |
| 2673 | } | ||
| 2674 | 2702 | ||
| 2675 | spin_lock_bh(&adapter->mcc_lock); | 2703 | spin_lock_bh(&adapter->mcc_lock); |
| 2676 | 2704 | ||
| @@ -2794,6 +2822,9 @@ int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter) · 117 unmodified lines | |||
| 2794 | CMD_SUBSYSTEM_ETH)) | 2822 | CMD_SUBSYSTEM_ETH)) |
| 2795 | return -EPERM; | 2823 | return -EPERM; |
| 2796 | 2824 | ||
| 2825 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | ||
| 2826 | return -1; | ||
| 2827 | |||
| 2797 | memset(&cmd, 0, sizeof(struct be_dma_mem)); | 2828 | memset(&cmd, 0, sizeof(struct be_dma_mem)); |
| 2798 | cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1); | 2829 | cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1); |
| 2799 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, | 2830 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, |
| @@ -2801,12 +2832,10 @@ int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter) · 1 unmodified line | |||
| 2801 | if (!cmd.va) { | 2832 | if (!cmd.va) { |
| 2802 | dev_err(&adapter->pdev->dev, | 2833 | dev_err(&adapter->pdev->dev, |
| 2803 | "Memory allocation failure\n"); | 2834 | "Memory allocation failure\n"); |
| 2804 | return -ENOMEM; | 2835 | status = -ENOMEM; |
| 2836 | goto err; | ||
| 2805 | } | 2837 | } |
| 2806 | 2838 | ||
| 2807 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | ||
| 2808 | return -1; | ||
| 2809 | |||
| 2810 | wrb = wrb_from_mbox(adapter); | 2839 | wrb = wrb_from_mbox(adapter); |
| 2811 | if (!wrb) { | 2840 | if (!wrb) { |
| 2812 | status = -EBUSY; | 2841 | status = -EBUSY; |
| @@ -2837,7 +2866,8 @@ int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter) · 24 unmodified lines | |||
| 2837 | } | 2866 | } |
| 2838 | err: | 2867 | err: |
| 2839 | mutex_unlock(&adapter->mbox_lock); | 2868 | mutex_unlock(&adapter->mbox_lock); |
| 2840 | pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); | 2869 | if (cmd.va) |
| 2870 | pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); | ||
| 2841 | return status; | 2871 | return status; |
| 2842 | 2872 | ||
| 2843 | } | 2873 | } |
| @@ -2942,14 +2972,15 @@ static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count, · 98 unmodified lines | |||
| 2942 | int i; | 2972 | int i; |
| 2943 | 2973 | ||
| 2944 | for (i = 0; i < desc_count; i++) { | 2974 | for (i = 0; i < desc_count; i++) { |
| 2945 | desc->desc_len = RESOURCE_DESC_SIZE; | 2975 | desc->desc_len = desc->desc_len ? : RESOURCE_DESC_SIZE; |
| 2946 | if (((void *)desc + desc->desc_len) > | 2976 | if (((void *)desc + desc->desc_len) > |
| 2947 | (void *)(buf + max_buf_size)) { | 2977 | (void *)(buf + max_buf_size)) { |
| 2948 | desc = NULL; | 2978 | desc = NULL; |
| 2949 | break; | 2979 | break; |
| 2950 | } | 2980 | } |
| 2951 | 2981 | ||
| 2952 | if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_ID) | 2982 | if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_V0 || |
| 2983 | desc->desc_type == NIC_RESOURCE_DESC_TYPE_V1) | ||
| 2953 | break; | 2984 | break; |
| 2954 | 2985 | ||
| 2955 | desc = (void *)desc + desc->desc_len; | 2986 | desc = (void *)desc + desc->desc_len; |
| @@ -2969,16 +3000,18 @@ int be_cmd_get_func_config(struct be_adapter *adapter) · 13 unmodified lines | |||
| 2969 | int status; | 3000 | int status; |
| 2970 | struct be_dma_mem cmd; | 3001 | struct be_dma_mem cmd; |
| 2971 | 3002 | ||
| 3003 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | ||
| 3004 | return -1; | ||
| 3005 | |||
| 2972 | memset(&cmd, 0, sizeof(struct be_dma_mem)); | 3006 | memset(&cmd, 0, sizeof(struct be_dma_mem)); |
| 2973 | cmd.size = sizeof(struct be_cmd_resp_get_func_config); | 3007 | cmd.size = sizeof(struct be_cmd_resp_get_func_config); |
| 2974 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, | 3008 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, |
| 2975 | &cmd.dma); | 3009 | &cmd.dma); |
| 2976 | if (!cmd.va) { | 3010 | if (!cmd.va) { |
| 2977 | dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); | 3011 | dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); |
| 2978 | return -ENOMEM; | 3012 | status = -ENOMEM; |
| 3013 | goto err; | ||
| 2979 | } | 3014 | } |
| 2980 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | ||
| 2981 | return -1; | ||
| 2982 | 3015 | ||
| 2983 | wrb = wrb_from_mbox(adapter); | 3016 | wrb = wrb_from_mbox(adapter); |
| 2984 | if (!wrb) { | 3017 | if (!wrb) { |
| @@ -2992,6 +3025,9 @@ int be_cmd_get_func_config(struct be_adapter *adapter) · 7 unmodified lines | |||
| 2992 | OPCODE_COMMON_GET_FUNC_CONFIG, | 3025 | OPCODE_COMMON_GET_FUNC_CONFIG, |
| 2993 | cmd.size, wrb, &cmd); | 3026 | cmd.size, wrb, &cmd); |
| 2994 | 3027 | ||
| 3028 | if (skyhawk_chip(adapter)) | ||
| 3029 | req->hdr.version = 1; | ||
| 3030 | |||
| 2995 | status = be_mbox_notify_wait(adapter); | 3031 | status = be_mbox_notify_wait(adapter); |
| 2996 | if (!status) { | 3032 | if (!status) { |
| 2997 | struct be_cmd_resp_get_func_config *resp = cmd.va; | 3033 | struct be_cmd_resp_get_func_config *resp = cmd.va; |
| @@ -3018,28 +3054,46 @@ int be_cmd_get_func_config(struct be_adapter *adapter) · 20 unmodified lines | |||
| 3018 | } | 3054 | } |
| 3019 | err: | 3055 | err: |
| 3020 | mutex_unlock(&adapter->mbox_lock); | 3056 | mutex_unlock(&adapter->mbox_lock); |
| 3021 | pci_free_consistent(adapter->pdev, cmd.size, | 3057 | if (cmd.va) |
| 3022 | cmd.va, cmd.dma); | 3058 | pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); |
| 3023 | return status; | 3059 | return status; |
| 3024 | } | 3060 | } |
| 3025 | 3061 | ||
| 3026 | /* Uses sync mcc */ | 3062 | /* Uses mbox */ |
| 3027 | int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags, | 3063 | int be_cmd_get_profile_config_mbox(struct be_adapter *adapter, |
| 3028 | u8 domain) | 3064 | u8 domain, struct be_dma_mem *cmd) |
| 3029 | { | 3065 | { |
| 3030 | struct be_mcc_wrb *wrb; | 3066 | struct be_mcc_wrb *wrb; |
| 3031 | struct be_cmd_req_get_profile_config *req; | 3067 | struct be_cmd_req_get_profile_config *req; |
| 3032 | int status; | 3068 | int status; |
| 3033 | struct be_dma_mem cmd; | ||
| 3034 | 3069 | ||
| 3035 | memset(&cmd, 0, sizeof(struct be_dma_mem)); | 3070 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
| 3036 | cmd.size = sizeof(struct be_cmd_resp_get_profile_config); | 3071 | return -1; |
| 3037 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, | 3072 | wrb = wrb_from_mbox(adapter); |
| 3038 | &cmd.dma); | 3073 | |
| 3039 | if (!cmd.va) { | 3074 | req = cmd->va; |
| 3040 | dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); | 3075 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
| 3041 | return -ENOMEM; | 3076 | OPCODE_COMMON_GET_PROFILE_CONFIG, |
| 3042 | } | 3077 | cmd->size, wrb, cmd); |
| 3078 | |||
| 3079 | req->type = ACTIVE_PROFILE_TYPE; | ||
| 3080 | req->hdr.domain = domain; | ||
| 3081 | if (!lancer_chip(adapter)) | ||
| 3082 | req->hdr.version = 1; | ||
| 3083 | |||
| 3084 | status = be_mbox_notify_wait(adapter); | ||
| 3085 | |||
| 3086 | mutex_unlock(&adapter->mbox_lock); | ||
| 3087 | return status; | ||
| 3088 | } | ||
| 3089 | |||
| 3090 | /* Uses sync mcc */ | ||
| 3091 | int be_cmd_get_profile_config_mccq(struct be_adapter *adapter, | ||
| 3092 | u8 domain, struct be_dma_mem *cmd) | ||
| 3093 | { | ||
| 3094 | struct be_mcc_wrb *wrb; | ||
| 3095 | struct be_cmd_req_get_profile_config *req; | ||
| 3096 | int status; | ||
| 3043 | 3097 | ||
| 3044 | spin_lock_bh(&adapter->mcc_lock); | 3098 | spin_lock_bh(&adapter->mcc_lock); |
| 3045 | 3099 | ||
| @@ -3049,16 +3103,47 @@ int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags, · 3 unmodified lines | |||
| 3049 | goto err; | 3103 | goto err; |
| 3050 | } | 3104 | } |
| 3051 | 3105 | ||
| 3052 | req = cmd.va; | 3106 | req = cmd->va; |
| 3053 | |||
| 3054 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | 3107 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
| 3055 | OPCODE_COMMON_GET_PROFILE_CONFIG, | 3108 | OPCODE_COMMON_GET_PROFILE_CONFIG, |
| 3056 | cmd.size, wrb, &cmd); | 3109 | cmd->size, wrb, cmd); |
| 3057 | 3110 | ||
| 3058 | req->type = ACTIVE_PROFILE_TYPE; | 3111 | req->type = ACTIVE_PROFILE_TYPE; |
| 3059 | req->hdr.domain = domain; | 3112 | req->hdr.domain = domain; |
| 3113 | if (!lancer_chip(adapter)) | ||
| 3114 | req->hdr.version = 1; | ||
| 3060 | 3115 | ||
| 3061 | status = be_mcc_notify_wait(adapter); | 3116 | status = be_mcc_notify_wait(adapter); |
| 3117 | |||
| 3118 | err: | ||
| 3119 | spin_unlock_bh(&adapter->mcc_lock); | ||
| 3120 | return status; | ||
| 3121 | } | ||
| 3122 | |||
| 3123 | /* Uses sync mcc, if MCCQ is already created otherwise mbox */ | ||
| 3124 | int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags, | ||
| 3125 | u16 *txq_count, u8 domain) | ||
| 3126 | { | ||
| 3127 | struct be_queue_info *mccq = &adapter->mcc_obj.q; | ||
| 3128 | struct be_dma_mem cmd; | ||
| 3129 | int status; | ||
| 3130 | |||
| 3131 | memset(&cmd, 0, sizeof(struct be_dma_mem)); | ||
| 3132 | if (!lancer_chip(adapter)) | ||
| 3133 | cmd.size = sizeof(struct be_cmd_resp_get_profile_config_v1); | ||
| 3134 | else | ||
| 3135 | cmd.size = sizeof(struct be_cmd_resp_get_profile_config); | ||
| 3136 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, | ||
| 3137 | &cmd.dma); | ||
| 3138 | if (!cmd.va) { | ||
| 3139 | dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); | ||
| 3140 | return -ENOMEM; | ||
| 3141 | } | ||
| 3142 | |||
| 3143 | if (!mccq->created) | ||
| 3144 | status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd); | ||
| 3145 | else | ||
| 3146 | status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd); | ||
| 3062 | if (!status) { | 3147 | if (!status) { |
| 3063 | struct be_cmd_resp_get_profile_config *resp = cmd.va; | 3148 | struct be_cmd_resp_get_profile_config *resp = cmd.va; |
| 3064 | u32 desc_count = le32_to_cpu(resp->desc_count); | 3149 | u32 desc_count = le32_to_cpu(resp->desc_count); |
| @@ -3071,12 +3156,15 @@ int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags, · 6 unmodified lines | |||
| 3071 | status = -EINVAL; | 3156 | status = -EINVAL; |
| 3072 | goto err; | 3157 | goto err; |
| 3073 | } | 3158 | } |
| 3074 | *cap_flags = le32_to_cpu(desc->cap_flags); | 3159 | if (cap_flags) |
| 3160 | *cap_flags = le32_to_cpu(desc->cap_flags); | ||
| 3161 | if (txq_count) | ||
| 3162 | *txq_count = le32_to_cpu(desc->txq_count); | ||
| 3075 | } | 3163 | } |
| 3076 | err: | 3164 | err: |
| 3077 | spin_unlock_bh(&adapter->mcc_lock); | 3165 | if (cmd.va) |
| 3078 | pci_free_consistent(adapter->pdev, cmd.size, | 3166 | pci_free_consistent(adapter->pdev, cmd.size, |
| 3079 | cmd.va, cmd.dma); | 3167 | cmd.va, cmd.dma); |
| 3080 | return status; | 3168 | return status; |
| 3081 | } | 3169 | } |
| 3082 | 3170 | ||
| @@ -3105,7 +3193,7 @@ int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps, · 22 unmodified lines | |||
| 3105 | req->hdr.domain = domain; | 3193 | req->hdr.domain = domain; |
| 3106 | req->desc_count = cpu_to_le32(1); | 3194 | req->desc_count = cpu_to_le32(1); |
| 3107 | 3195 | ||
| 3108 | req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_ID; | 3196 | req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_V0; |
| 3109 | req->nic_desc.desc_len = RESOURCE_DESC_SIZE; | 3197 | req->nic_desc.desc_len = RESOURCE_DESC_SIZE; |
| 3110 | req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV); | 3198 | req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV); |
| 3111 | req->nic_desc.pf_num = adapter->pf_number; | 3199 | req->nic_desc.pf_num = adapter->pf_number; |
| @@ -3202,6 +3290,31 @@ err: · 90 unmodified lines | |||
| 3202 | return status; | 3290 | return status; |
| 3203 | } | 3291 | } |
| 3204 | 3292 | ||
| 3293 | int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable) | ||
| 3294 | { | ||
| 3295 | struct be_mcc_wrb *wrb; | ||
| 3296 | struct be_cmd_req_intr_set *req; | ||
| 3297 | int status; | ||
| 3298 | |||
| 3299 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | ||
| 3300 | return -1; | ||
| 3301 | |||
| 3302 | wrb = wrb_from_mbox(adapter); | ||
| 3303 | |||
| 3304 | req = embedded_payload(wrb); | ||
| 3305 | |||
| 3306 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 3307 | OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req), | ||
| 3308 | wrb, NULL); | ||
| 3309 | |||
| 3310 | req->intr_enabled = intr_enable; | ||
| 3311 | |||
| 3312 | status = be_mbox_notify_wait(adapter); | ||
| 3313 | |||
| 3314 | mutex_unlock(&adapter->mbox_lock); | ||
| 3315 | return status; | ||
| 3316 | } | ||
| 3317 | |||
| 3205 | int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload, | 3318 | int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload, |
| 3206 | int wrb_payload_size, u16 *cmd_status, u16 *ext_status) | 3319 | int wrb_payload_size, u16 *cmd_status, u16 *ext_status) |
| 3207 | { | 3320 | { |
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2005 - 2011 Emulex | 2 | * Copyright (C) 2005 - 2013 Emulex |
| 3 | * All rights reserved. | 3 | * All rights reserved. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
| @@ -84,6 +84,9 @@ struct be_mcc_compl { · 78 unmodified lines | |||
| 84 | #define ASYNC_EVENT_QOS_SPEED 0x1 | 84 | #define ASYNC_EVENT_QOS_SPEED 0x1 |
| 85 | #define ASYNC_EVENT_COS_PRIORITY 0x2 | 85 | #define ASYNC_EVENT_COS_PRIORITY 0x2 |
| 86 | #define ASYNC_EVENT_PVID_STATE 0x3 | 86 | #define ASYNC_EVENT_PVID_STATE 0x3 |
| 87 | #define ASYNC_EVENT_CODE_QNQ 0x6 | ||
| 88 | #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1 | ||
| 89 | |||
| 87 | struct be_async_event_trailer { | 90 | struct be_async_event_trailer { |
| 88 | u32 code; | 91 | u32 code; |
| 89 | }; | 92 | }; |
| @@ -144,6 +147,16 @@ struct be_async_event_grp5_pvid_state { · 54 unmodified lines | |||
| 144 | struct be_async_event_trailer trailer; | 147 | struct be_async_event_trailer trailer; |
| 145 | } __packed; | 148 | } __packed; |
| 146 | 149 | ||
| 150 | /* async event indicating outer VLAN tag in QnQ */ | ||
| 151 | struct be_async_event_qnq { | ||
| 152 | u8 valid; /* Indicates if outer VLAN is valid */ | ||
| 153 | u8 rsvd0; | ||
| 154 | u16 vlan_tag; | ||
| 155 | u32 event_tag; | ||
| 156 | u8 rsvd1[4]; | ||
| 157 | struct be_async_event_trailer trailer; | ||
| 158 | } __packed; | ||
| 159 | |||
| 147 | struct be_mcc_mailbox { | 160 | struct be_mcc_mailbox { |
| 148 | struct be_mcc_wrb wrb; | 161 | struct be_mcc_wrb wrb; |
| 149 | struct be_mcc_compl compl; | 162 | struct be_mcc_compl compl; |
| @@ -188,6 +201,7 @@ struct be_mcc_mailbox { · 38 unmodified lines | |||
| 188 | #define OPCODE_COMMON_GET_BEACON_STATE 70 | 201 | #define OPCODE_COMMON_GET_BEACON_STATE 70 |
| 189 | #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 | 202 | #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 |
| 190 | #define OPCODE_COMMON_GET_PORT_NAME 77 | 203 | #define OPCODE_COMMON_GET_PORT_NAME 77 |
| 204 | #define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89 | ||
| 191 | #define OPCODE_COMMON_GET_PHY_DETAILS 102 | 205 | #define OPCODE_COMMON_GET_PHY_DETAILS 102 |
| 192 | #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 | 206 | #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 |
| 193 | #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 | 207 | #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 |
| @@ -473,46 +487,27 @@ struct be_cmd_resp_mcc_create { · 279 unmodified lines | |||
| 473 | #define BE_ETH_TX_RING_TYPE_STANDARD 2 | 487 | #define BE_ETH_TX_RING_TYPE_STANDARD 2 |
| 474 | #define BE_ULP1_NUM 1 | 488 | #define BE_ULP1_NUM 1 |
| 475 | 489 | ||
| 476 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
| 477 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
| 478 | struct amap_tx_context { | ||
| 479 | u8 if_id[16]; /* dword 0 */ | ||
| 480 | u8 tx_ring_size[4]; /* dword 0 */ | ||
| 481 | u8 rsvd1[26]; /* dword 0 */ | ||
| 482 | u8 pci_func_id[8]; /* dword 1 */ | ||
| 483 | u8 rsvd2[9]; /* dword 1 */ | ||
| 484 | u8 ctx_valid; /* dword 1 */ | ||
| 485 | u8 cq_id_send[16]; /* dword 2 */ | ||
| 486 | u8 rsvd3[16]; /* dword 2 */ | ||
| 487 | u8 rsvd4[32]; /* dword 3 */ | ||
| 488 | u8 rsvd5[32]; /* dword 4 */ | ||
| 489 | u8 rsvd6[32]; /* dword 5 */ | ||
| 490 | u8 rsvd7[32]; /* dword 6 */ | ||
| 491 | u8 rsvd8[32]; /* dword 7 */ | ||
| 492 | u8 rsvd9[32]; /* dword 8 */ | ||
| 493 | u8 rsvd10[32]; /* dword 9 */ | ||
| 494 | u8 rsvd11[32]; /* dword 10 */ | ||
| 495 | u8 rsvd12[32]; /* dword 11 */ | ||
| 496 | u8 rsvd13[32]; /* dword 12 */ | ||
| 497 | u8 rsvd14[32]; /* dword 13 */ | ||
| 498 | u8 rsvd15[32]; /* dword 14 */ | ||
| 499 | u8 rsvd16[32]; /* dword 15 */ | ||
| 500 | } __packed; | ||
| 501 | |||
| 502 | struct be_cmd_req_eth_tx_create { | 490 | struct be_cmd_req_eth_tx_create { |
| 503 | struct be_cmd_req_hdr hdr; | 491 | struct be_cmd_req_hdr hdr; |
| 504 | u8 num_pages; | 492 | u8 num_pages; |
| 505 | u8 ulp_num; | 493 | u8 ulp_num; |
| 506 | u8 type; | 494 | u16 type; |
| 507 | u8 bound_port; | 495 | u16 if_id; |
| 508 | u8 context[sizeof(struct amap_tx_context) / 8]; | 496 | u8 queue_size; |
| 497 | u8 rsvd0; | ||
| 498 | u32 rsvd1; | ||
| 499 | u16 cq_id; | ||
| 500 | u16 rsvd2; | ||
| 501 | u32 rsvd3[13]; | ||
| 509 | struct phys_addr pages[8]; | 502 | struct phys_addr pages[8]; |
| 510 | } __packed; | 503 | } __packed; |
| 511 | 504 | ||
| 512 | struct be_cmd_resp_eth_tx_create { | 505 | struct be_cmd_resp_eth_tx_create { |
| 513 | struct be_cmd_resp_hdr hdr; | 506 | struct be_cmd_resp_hdr hdr; |
| 514 | u16 cid; | 507 | u16 cid; |
| 515 | u16 rsvd0; | 508 | u16 rid; |
| 509 | u32 db_offset; | ||
| 510 | u32 rsvd0[4]; | ||
| 516 | } __packed; | 511 | } __packed; |
| 517 | 512 | ||
| 518 | /******************** Create RxQ ***************************/ | 513 | /******************** Create RxQ ***************************/ |
| @@ -608,8 +603,8 @@ struct be_port_rxf_stats_v0 { · 89 unmodified lines | |||
| 608 | u32 rx_in_range_errors; /* dword 10*/ | 603 | u32 rx_in_range_errors; /* dword 10*/ |
| 609 | u32 rx_out_range_errors; /* dword 11*/ | 604 | u32 rx_out_range_errors; /* dword 11*/ |
| 610 | u32 rx_frame_too_long; /* dword 12*/ | 605 | u32 rx_frame_too_long; /* dword 12*/ |
| 611 | u32 rx_address_mismatch_drops; /* dword 13*/ | 606 | u32 rx_address_filtered; /* dword 13*/ |
| 612 | u32 rx_vlan_mismatch_drops; /* dword 14*/ | 607 | u32 rx_vlan_filtered; /* dword 14*/ |
| 613 | u32 rx_dropped_too_small; /* dword 15*/ | 608 | u32 rx_dropped_too_small; /* dword 15*/ |
| 614 | u32 rx_dropped_too_short; /* dword 16*/ | 609 | u32 rx_dropped_too_short; /* dword 16*/ |
| 615 | u32 rx_dropped_header_too_small; /* dword 17*/ | 610 | u32 rx_dropped_header_too_small; /* dword 17*/ |
| @@ -815,8 +810,8 @@ struct lancer_pport_stats { · 199 unmodified lines | |||
| 815 | u32 rx_control_frames_unknown_opcode_hi; | 810 | u32 rx_control_frames_unknown_opcode_hi; |
| 816 | u32 rx_in_range_errors; | 811 | u32 rx_in_range_errors; |
| 817 | u32 rx_out_of_range_errors; | 812 | u32 rx_out_of_range_errors; |
| 818 | u32 rx_address_mismatch_drops; | 813 | u32 rx_address_filtered; |
| 819 | u32 rx_vlan_mismatch_drops; | 814 | u32 rx_vlan_filtered; |
| 820 | u32 rx_dropped_too_small; | 815 | u32 rx_dropped_too_small; |
| 821 | u32 rx_dropped_too_short; | 816 | u32 rx_dropped_too_short; |
| 822 | u32 rx_dropped_header_too_small; | 817 | u32 rx_dropped_header_too_small; |
| @@ -1066,7 +1061,6 @@ struct be_cmd_resp_modify_eq_delay { · 243 unmodified lines | |||
| 1066 | } __packed; | 1061 | } __packed; |
| 1067 | 1062 | ||
| 1068 | /******************** Get FW Config *******************/ | 1063 | /******************** Get FW Config *******************/ |
| 1069 | #define BE_FUNCTION_CAPS_RSS 0x2 | ||
| 1070 | /* The HW can come up in either of the following multi-channel modes | 1064 | /* The HW can come up in either of the following multi-channel modes |
| 1071 | * based on the skew/IPL. | 1065 | * based on the skew/IPL. |
| 1072 | */ | 1066 | */ |
| @@ -1109,6 +1103,9 @@ struct be_cmd_resp_query_fw_cfg { · 36 unmodified lines | |||
| 1109 | #define RSS_ENABLE_UDP_IPV4 0x10 | 1103 | #define RSS_ENABLE_UDP_IPV4 0x10 |
| 1110 | #define RSS_ENABLE_UDP_IPV6 0x20 | 1104 | #define RSS_ENABLE_UDP_IPV6 0x20 |
| 1111 | 1105 | ||
| 1106 | #define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC) | ||
| 1107 | #define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3) | ||
| 1108 | |||
| 1112 | struct be_cmd_req_rss_config { | 1109 | struct be_cmd_req_rss_config { |
| 1113 | struct be_cmd_req_hdr hdr; | 1110 | struct be_cmd_req_hdr hdr; |
| 1114 | u32 if_id; | 1111 | u32 if_id; |
| @@ -1592,7 +1589,7 @@ struct be_port_rxf_stats_v1 { · 477 unmodified lines | |||
| 1592 | u32 rx_in_range_errors; | 1589 | u32 rx_in_range_errors; |
| 1593 | u32 rx_out_range_errors; | 1590 | u32 rx_out_range_errors; |
| 1594 | u32 rx_frame_too_long; | 1591 | u32 rx_frame_too_long; |
| 1595 | u32 rx_address_mismatch_drops; | 1592 | u32 rx_address_filtered; |
| 1596 | u32 rx_dropped_too_small; | 1593 | u32 rx_dropped_too_small; |
| 1597 | u32 rx_dropped_too_short; | 1594 | u32 rx_dropped_too_short; |
| 1598 | u32 rx_dropped_header_too_small; | 1595 | u32 rx_dropped_header_too_small; |
| @@ -1706,9 +1703,11 @@ struct be_cmd_req_set_ext_fat_caps { · 107 unmodified lines | |||
| 1706 | struct be_fat_conf_params set_params; | 1703 | struct be_fat_conf_params set_params; |
| 1707 | }; | 1704 | }; |
| 1708 | 1705 | ||
| 1709 | #define RESOURCE_DESC_SIZE 72 | 1706 | #define RESOURCE_DESC_SIZE 88 |
| 1710 | #define NIC_RESOURCE_DESC_TYPE_ID 0x41 | 1707 | #define NIC_RESOURCE_DESC_TYPE_V0 0x41 |
| 1708 | #define NIC_RESOURCE_DESC_TYPE_V1 0x51 | ||
| 1711 | #define MAX_RESOURCE_DESC 4 | 1709 | #define MAX_RESOURCE_DESC 4 |
| 1710 | #define MAX_RESOURCE_DESC_V1 32 | ||
| 1712 | 1711 | ||
| 1713 | /* QOS unit number */ | 1712 | /* QOS unit number */ |
| 1714 | #define QUN 4 | 1713 | #define QUN 4 |
| @@ -1755,7 +1754,7 @@ struct be_cmd_req_get_func_config { · 40 unmodified lines | |||
| 1755 | }; | 1754 | }; |
| 1756 | 1755 | ||
| 1757 | struct be_cmd_resp_get_func_config { | 1756 | struct be_cmd_resp_get_func_config { |
| 1758 | struct be_cmd_req_hdr hdr; | 1757 | struct be_cmd_resp_hdr hdr; |
| 1759 | u32 desc_count; | 1758 | u32 desc_count; |
| 1760 | u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE]; | 1759 | u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE]; |
| 1761 | }; | 1760 | }; |
| @@ -1774,6 +1773,12 @@ struct be_cmd_resp_get_profile_config { · 12 unmodified lines | |||
| 1774 | u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE]; | 1773 | u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE]; |
| 1775 | }; | 1774 | }; |
| 1776 | 1775 | ||
| 1776 | struct be_cmd_resp_get_profile_config_v1 { | ||
| 1777 | struct be_cmd_req_hdr hdr; | ||
| 1778 | u32 desc_count; | ||
| 1779 | u8 func_param[MAX_RESOURCE_DESC_V1 * RESOURCE_DESC_SIZE]; | ||
| 1780 | }; | ||
| 1781 | |||
| 1777 | struct be_cmd_req_set_profile_config { | 1782 | struct be_cmd_req_set_profile_config { |
| 1778 | struct be_cmd_req_hdr hdr; | 1783 | struct be_cmd_req_hdr hdr; |
| 1779 | u32 rsvd; | 1784 | u32 rsvd; |
| @@ -1791,6 +1796,12 @@ struct be_cmd_enable_disable_vf { · 11 unmodified lines | |||
| 1791 | u8 rsvd[3]; | 1796 | u8 rsvd[3]; |
| 1792 | }; | 1797 | }; |
| 1793 | 1798 | ||
| 1799 | struct be_cmd_req_intr_set { | ||
| 1800 | struct be_cmd_req_hdr hdr; | ||
| 1801 | u8 intr_enabled; | ||
| 1802 | u8 rsvd[3]; | ||
| 1803 | }; | ||
| 1804 | |||
| 1794 | static inline bool check_privilege(struct be_adapter *adapter, u32 flags) | 1805 | static inline bool check_privilege(struct be_adapter *adapter, u32 flags) |
| 1795 | { | 1806 | { |
| 1796 | return flags & adapter->cmd_privileges ? true : false; | 1807 | return flags & adapter->cmd_privileges ? true : false; |
| @@ -1834,8 +1845,7 @@ extern int be_cmd_mccq_create(struct be_adapter *adapter, · 37 unmodified lines | |||
| 1834 | struct be_queue_info *mccq, | 1845 | struct be_queue_info *mccq, |
| 1835 | struct be_queue_info *cq); | 1846 | struct be_queue_info *cq); |
| 1836 | extern int be_cmd_txq_create(struct be_adapter *adapter, | 1847 | extern int be_cmd_txq_create(struct be_adapter *adapter, |
| 1837 | struct be_queue_info *txq, | 1848 | struct be_tx_obj *txo); |
| 1838 | struct be_queue_info *cq); | ||
| 1839 | extern int be_cmd_rxq_create(struct be_adapter *adapter, | 1849 | extern int be_cmd_rxq_create(struct be_adapter *adapter, |
| 1840 | struct be_queue_info *rxq, u16 cq_id, | 1850 | struct be_queue_info *rxq, u16 cq_id, |
| 1841 | u16 frag_size, u32 if_id, u32 rss, u8 *rss_id); | 1851 | u16 frag_size, u32 if_id, u32 rss, u8 *rss_id); |
| @@ -1862,11 +1872,11 @@ extern int be_cmd_set_flow_control(struct be_adapter *adapter, · 20 unmodified lines | |||
| 1862 | u32 tx_fc, u32 rx_fc); | 1872 | u32 tx_fc, u32 rx_fc); |
| 1863 | extern int be_cmd_get_flow_control(struct be_adapter *adapter, | 1873 | extern int be_cmd_get_flow_control(struct be_adapter *adapter, |
| 1864 | u32 *tx_fc, u32 *rx_fc); | 1874 | u32 *tx_fc, u32 *rx_fc); |
| 1865 | extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, | 1875 | extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, |
| 1866 | u32 *port_num, u32 *function_mode, u32 *function_caps); | 1876 | u32 *function_mode, u32 *function_caps, u16 *asic_rev); |
| 1867 | extern int be_cmd_reset_function(struct be_adapter *adapter); | 1877 | extern int be_cmd_reset_function(struct be_adapter *adapter); |
| 1868 | extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, | 1878 | extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, |
| 1869 | u16 table_size); | 1879 | u32 rss_hash_opts, u16 table_size); |
| 1870 | extern int be_process_mcc(struct be_adapter *adapter); | 1880 | extern int be_process_mcc(struct be_adapter *adapter); |
| 1871 | extern int be_cmd_set_beacon_state(struct be_adapter *adapter, | 1881 | extern int be_cmd_set_beacon_state(struct be_adapter *adapter, |
| 1872 | u8 port_num, u8 beacon, u8 status, u8 state); | 1882 | u8 port_num, u8 beacon, u8 status, u8 state); |
| @@ -1931,10 +1941,11 @@ extern int lancer_test_and_set_rdy_state(struct be_adapter *adapter); · 58 unmodified lines | |||
| 1931 | extern int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name); | 1941 | extern int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name); |
| 1932 | extern int be_cmd_get_func_config(struct be_adapter *adapter); | 1942 | extern int be_cmd_get_func_config(struct be_adapter *adapter); |
| 1933 | extern int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags, | 1943 | extern int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags, |
| 1934 | u8 domain); | 1944 | u16 *txq_count, u8 domain); |
| 1935 | 1945 | ||
| 1936 | extern int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps, | 1946 | extern int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps, |
| 1937 | u8 domain); | 1947 | u8 domain); |
| 1938 | extern int be_cmd_get_if_id(struct be_adapter *adapter, | 1948 | extern int be_cmd_get_if_id(struct be_adapter *adapter, |
| 1939 | struct be_vf_cfg *vf_cfg, int vf_num); | 1949 | struct be_vf_cfg *vf_cfg, int vf_num); |
| 1940 | extern int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain); | 1950 | extern int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain); |
| 1951 | extern int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable); | ||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2005 - 2011 Emulex | 2 | * Copyright (C) 2005 - 2013 Emulex |
| 3 | * All rights reserved. | 3 | * All rights reserved. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
| @@ -54,7 +54,7 @@ static const struct be_ethtool_stat et_stats[] = { · 48 unmodified lines | |||
| 54 | /* Received packets dropped when they don't pass the unicast or | 54 | /* Received packets dropped when they don't pass the unicast or |
| 55 | * multicast address filtering. | 55 | * multicast address filtering. |
| 56 | */ | 56 | */ |
| 57 | {DRVSTAT_INFO(rx_address_mismatch_drops)}, | 57 | {DRVSTAT_INFO(rx_address_filtered)}, |
| 58 | /* Received packets dropped when IP packet length field is less than | 58 | /* Received packets dropped when IP packet length field is less than |
| 59 | * the IP header length field. | 59 | * the IP header length field. |
| 60 | */ | 60 | */ |
| @@ -680,7 +680,8 @@ be_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) · 619 unmodified lines | |||
| 680 | 680 | ||
| 681 | if (be_is_wol_supported(adapter)) { | 681 | if (be_is_wol_supported(adapter)) { |
| 682 | wol->supported |= WAKE_MAGIC; | 682 | wol->supported |= WAKE_MAGIC; |
| 683 | wol->wolopts |= WAKE_MAGIC; | 683 | if (adapter->wol) |
| 684 | wol->wolopts |= WAKE_MAGIC; | ||
| 684 | } else | 685 | } else |
| 685 | wol->wolopts = 0; | 686 | wol->wolopts = 0; |
| 686 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | 687 | memset(&wol->sopass, 0, sizeof(wol->sopass)); |
| @@ -719,10 +720,8 @@ be_test_ddr_dma(struct be_adapter *adapter) · 32 unmodified lines | |||
| 719 | ddrdma_cmd.size = sizeof(struct be_cmd_req_ddrdma_test); | 720 | ddrdma_cmd.size = sizeof(struct be_cmd_req_ddrdma_test); |
| 720 | ddrdma_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, ddrdma_cmd.size, | 721 | ddrdma_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, ddrdma_cmd.size, |
| 721 | &ddrdma_cmd.dma, GFP_KERNEL); | 722 | &ddrdma_cmd.dma, GFP_KERNEL); |
| 722 | if (!ddrdma_cmd.va) { | 723 | if (!ddrdma_cmd.va) |
| 723 | dev_err(&adapter->pdev->dev, "Memory allocation failure\n"); | ||
| 724 | return -ENOMEM; | 724 | return -ENOMEM; |
| 725 | } | ||
| 726 | 725 | ||
| 727 | for (i = 0; i < 2; i++) { | 726 | for (i = 0; i < 2; i++) { |
| 728 | ret = be_cmd_ddr_dma_test(adapter, pattern[i], | 727 | ret = be_cmd_ddr_dma_test(adapter, pattern[i], |
| @@ -757,6 +756,12 @@ be_self_test(struct net_device *netdev, struct ethtool_test *test, u64 *data) · 28 unmodified lines | |||
| 757 | int status; | 756 | int status; |
| 758 | u8 link_status = 0; | 757 | u8 link_status = 0; |
| 759 | 758 | ||
| 759 | if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC) { | ||
| 760 | dev_err(&adapter->pdev->dev, "Self test not supported\n"); | ||
| 761 | test->flags |= ETH_TEST_FL_FAILED; | ||
| 762 | return; | ||
| 763 | } | ||
| 764 | |||
| 760 | memset(data, 0, sizeof(u64) * ETHTOOL_TESTS_NUM); | 765 | memset(data, 0, sizeof(u64) * ETHTOOL_TESTS_NUM); |
| 761 | 766 | ||
| 762 | if (test->flags & ETH_TEST_FL_OFFLINE) { | 767 | if (test->flags & ETH_TEST_FL_OFFLINE) { |
| @@ -845,11 +850,8 @@ be_read_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, · 82 unmodified lines | |||
| 845 | eeprom_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, eeprom_cmd.size, | 850 | eeprom_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, eeprom_cmd.size, |
| 846 | &eeprom_cmd.dma, GFP_KERNEL); | 851 | &eeprom_cmd.dma, GFP_KERNEL); |
| 847 | 852 | ||
| 848 | if (!eeprom_cmd.va) { | 853 | if (!eeprom_cmd.va) |
| 849 | dev_err(&adapter->pdev->dev, | ||
| 850 | "Memory allocation failure. Could not read eeprom\n"); | ||
| 851 | return -ENOMEM; | 854 | return -ENOMEM; |
| 852 | } | ||
| 853 | 855 | ||
| 854 | status = be_cmd_get_seeprom_data(adapter, &eeprom_cmd); | 856 | status = be_cmd_get_seeprom_data(adapter, &eeprom_cmd); |
| 855 | 857 | ||
| @@ -939,6 +941,159 @@ static void be_set_msg_level(struct net_device *netdev, u32 level) · 83 unmodified lines | |||
| 939 | return; | 941 | return; |
| 940 | } | 942 | } |
| 941 | 943 | ||
| 944 | static u64 be_get_rss_hash_opts(struct be_adapter *adapter, u64 flow_type) | ||
| 945 | { | ||
| 946 | u64 data = 0; | ||
| 947 | |||
| 948 | switch (flow_type) { | ||
| 949 | case TCP_V4_FLOW: | ||
| 950 | if (adapter->rss_flags & RSS_ENABLE_IPV4) | ||
| 951 | data |= RXH_IP_DST | RXH_IP_SRC; | ||
| 952 | if (adapter->rss_flags & RSS_ENABLE_TCP_IPV4) | ||
| 953 | data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; | ||
| 954 | break; | ||
| 955 | case UDP_V4_FLOW: | ||
| 956 | if (adapter->rss_flags & RSS_ENABLE_IPV4) | ||
| 957 | data |= RXH_IP_DST | RXH_IP_SRC; | ||
| 958 | if (adapter->rss_flags & RSS_ENABLE_UDP_IPV4) | ||
| 959 | data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; | ||
| 960 | break; | ||
| 961 | case TCP_V6_FLOW: | ||
| 962 | if (adapter->rss_flags & RSS_ENABLE_IPV6) | ||
| 963 | data |= RXH_IP_DST | RXH_IP_SRC; | ||
| 964 | if (adapter->rss_flags & RSS_ENABLE_TCP_IPV6) | ||
| 965 | data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; | ||
| 966 | break; | ||
| 967 | case UDP_V6_FLOW: | ||
| 968 | if (adapter->rss_flags & RSS_ENABLE_IPV6) | ||
| 969 | data |= RXH_IP_DST | RXH_IP_SRC; | ||
| 970 | if (adapter->rss_flags & RSS_ENABLE_UDP_IPV6) | ||
| 971 | data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; | ||
| 972 | break; | ||
| 973 | } | ||
| 974 | |||
| 975 | return data; | ||
| 976 | } | ||
| 977 | |||
| 978 | static int be_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd, | ||
| 979 | u32 *rule_locs) | ||
| 980 | { | ||
| 981 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 982 | |||
| 983 | if (!be_multi_rxq(adapter)) { | ||
| 984 | dev_info(&adapter->pdev->dev, | ||
| 985 | "ethtool::get_rxnfc: RX flow hashing is disabled\n"); | ||
| 986 | return -EINVAL; | ||
| 987 | } | ||
| 988 | |||
| 989 | switch (cmd->cmd) { | ||
| 990 | case ETHTOOL_GRXFH: | ||
| 991 | cmd->data = be_get_rss_hash_opts(adapter, cmd->flow_type); | ||
| 992 | break; | ||
| 993 | case ETHTOOL_GRXRINGS: | ||
| 994 | cmd->data = adapter->num_rx_qs - 1; | ||
| 995 | break; | ||
| 996 | default: | ||
| 997 | return -EINVAL; | ||
| 998 | } | ||
| 999 | |||
| 1000 | return 0; | ||
| 1001 | } | ||
| 1002 | |||
| 1003 | static int be_set_rss_hash_opts(struct be_adapter *adapter, | ||
| 1004 | struct ethtool_rxnfc *cmd) | ||
| 1005 | { | ||
| 1006 | struct be_rx_obj *rxo; | ||
| 1007 | int status = 0, i, j; | ||
| 1008 | u8 rsstable[128]; | ||
| 1009 | u32 rss_flags = adapter->rss_flags; | ||
| 1010 | |||
| 1011 | if (cmd->data != L3_RSS_FLAGS && | ||
| 1012 | cmd->data != (L3_RSS_FLAGS | L4_RSS_FLAGS)) | ||
| 1013 | return -EINVAL; | ||
| 1014 | |||
| 1015 | switch (cmd->flow_type) { | ||
| 1016 | case TCP_V4_FLOW: | ||
| 1017 | if (cmd->data == L3_RSS_FLAGS) | ||
| 1018 | rss_flags &= ~RSS_ENABLE_TCP_IPV4; | ||
| 1019 | else if (cmd->data == (L3_RSS_FLAGS | L4_RSS_FLAGS)) | ||
| 1020 | rss_flags |= RSS_ENABLE_IPV4 | | ||
| 1021 | RSS_ENABLE_TCP_IPV4; | ||
| 1022 | break; | ||
| 1023 | case TCP_V6_FLOW: | ||
| 1024 | if (cmd->data == L3_RSS_FLAGS) | ||
| 1025 | rss_flags &= ~RSS_ENABLE_TCP_IPV6; | ||
| 1026 | else if (cmd->data == (L3_RSS_FLAGS | L4_RSS_FLAGS)) | ||
| 1027 | rss_flags |= RSS_ENABLE_IPV6 | | ||
| 1028 | RSS_ENABLE_TCP_IPV6; | ||
| 1029 | break; | ||
| 1030 | case UDP_V4_FLOW: | ||
| 1031 | if ((cmd->data == (L3_RSS_FLAGS | L4_RSS_FLAGS)) && | ||
| 1032 | BEx_chip(adapter)) | ||
| 1033 | return -EINVAL; | ||
| 1034 | |||
| 1035 | if (cmd->data == L3_RSS_FLAGS) | ||
| 1036 | rss_flags &= ~RSS_ENABLE_UDP_IPV4; | ||
| 1037 | else if (cmd->data == (L3_RSS_FLAGS | L4_RSS_FLAGS)) | ||
| 1038 | rss_flags |= RSS_ENABLE_IPV4 | | ||
| 1039 | RSS_ENABLE_UDP_IPV4; | ||
| 1040 | break; | ||
| 1041 | case UDP_V6_FLOW: | ||
| 1042 | if ((cmd->data == (L3_RSS_FLAGS | L4_RSS_FLAGS)) && | ||
| 1043 | BEx_chip(adapter)) | ||
| 1044 | return -EINVAL; | ||
| 1045 | |||
| 1046 | if (cmd->data == L3_RSS_FLAGS) | ||
| 1047 | rss_flags &= ~RSS_ENABLE_UDP_IPV6; | ||
| 1048 | else if (cmd->data == (L3_RSS_FLAGS | L4_RSS_FLAGS)) | ||
| 1049 | rss_flags |= RSS_ENABLE_IPV6 | | ||
| 1050 | RSS_ENABLE_UDP_IPV6; | ||
| 1051 | break; | ||
| 1052 | default: | ||
| 1053 | return -EINVAL; | ||
| 1054 | } | ||
| 1055 | |||
| 1056 | if (rss_flags == adapter->rss_flags) | ||
| 1057 | return status; | ||
| 1058 | |||
| 1059 | if (be_multi_rxq(adapter)) { | ||
| 1060 | for (j = 0; j < 128; j += adapter->num_rx_qs - 1) { | ||
| 1061 | for_all_rss_queues(adapter, rxo, i) { | ||
| 1062 | if ((j + i) >= 128) | ||
| 1063 | break; | ||
| 1064 | rsstable[j + i] = rxo->rss_id; | ||
| 1065 | } | ||
| 1066 | } | ||
| 1067 | } | ||
| 1068 | status = be_cmd_rss_config(adapter, rsstable, rss_flags, 128); | ||
| 1069 | if (!status) | ||
| 1070 | adapter->rss_flags = rss_flags; | ||
| 1071 | |||
| 1072 | return status; | ||
| 1073 | } | ||
| 1074 | |||
| 1075 | static int be_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd) | ||
| 1076 | { | ||
| 1077 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 1078 | int status = 0; | ||
| 1079 | |||
| 1080 | if (!be_multi_rxq(adapter)) { | ||
| 1081 | dev_err(&adapter->pdev->dev, | ||
| 1082 | "ethtool::set_rxnfc: RX flow hashing is disabled\n"); | ||
| 1083 | return -EINVAL; | ||
| 1084 | } | ||
| 1085 | |||
| 1086 | switch (cmd->cmd) { | ||
| 1087 | case ETHTOOL_SRXFH: | ||
| 1088 | status = be_set_rss_hash_opts(adapter, cmd); | ||
| 1089 | break; | ||
| 1090 | default: | ||
| 1091 | return -EINVAL; | ||
| 1092 | } | ||
| 1093 | |||
| 1094 | return status; | ||
| 1095 | } | ||
| 1096 | |||
| 942 | const struct ethtool_ops be_ethtool_ops = { | 1097 | const struct ethtool_ops be_ethtool_ops = { |
| 943 | .get_settings = be_get_settings, | 1098 | .get_settings = be_get_settings, |
| 944 | .get_drvinfo = be_get_drvinfo, | 1099 | .get_drvinfo = be_get_drvinfo, |
| @@ -962,4 +1117,6 @@ const struct ethtool_ops be_ethtool_ops = { · 17 unmodified lines | |||
| 962 | .get_regs = be_get_regs, | 1117 | .get_regs = be_get_regs, |
| 963 | .flash_device = be_do_flash, | 1118 | .flash_device = be_do_flash, |
| 964 | .self_test = be_self_test, | 1119 | .self_test = be_self_test, |
| 1120 | .get_rxnfc = be_get_rxnfc, | ||
| 1121 | .set_rxnfc = be_set_rxnfc, | ||
| 965 | }; | 1122 | }; |
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2005 - 2011 Emulex | 2 | * Copyright (C) 2005 - 2013 Emulex |
| 3 | * All rights reserved. | 3 | * All rights reserved. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
| @@ -72,6 +72,10 @@ · 66 unmodified lines | |||
| 72 | */ | 72 | */ |
| 73 | #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ | 73 | #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ |
| 74 | 74 | ||
| 75 | /********* PCI Function Capability *********/ | ||
| 76 | #define BE_FUNCTION_CAPS_RSS 0x2 | ||
| 77 | #define BE_FUNCTION_CAPS_SUPER_NIC 0x40 | ||
| 78 | |||
| 75 | /********* Power management (WOL) **********/ | 79 | /********* Power management (WOL) **********/ |
| 76 | #define PCICFG_PM_CONTROL_OFFSET 0x44 | 80 | #define PCICFG_PM_CONTROL_OFFSET 0x44 |
| 77 | #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */ | 81 | #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */ |
| @@ -495,7 +499,8 @@ struct flash_file_hdr_g3 { · 417 unmodified lines | |||
| 495 | u32 antidote; | 499 | u32 antidote; |
| 496 | u32 num_imgs; | 500 | u32 num_imgs; |
| 497 | u8 build[24]; | 501 | u8 build[24]; |
| 498 | u8 rsvd[32]; | 502 | u8 asic_type_rev; |
| 503 | u8 rsvd[31]; | ||
| 499 | }; | 504 | }; |
| 500 | 505 | ||
| 501 | struct flash_section_hdr { | 506 | struct flash_section_hdr { |
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2005 - 2011 Emulex | 2 | * Copyright (C) 2005 - 2013 Emulex |
| 3 | * All rights reserved. | 3 | * All rights reserved. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
| @@ -146,20 +146,16 @@ static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q, · 140 unmodified lines | |||
| 146 | q->entry_size = entry_size; | 146 | q->entry_size = entry_size; |
| 147 | mem->size = len * entry_size; | 147 | mem->size = len * entry_size; |
| 148 | mem->va = dma_alloc_coherent(&adapter->pdev->dev, mem->size, &mem->dma, | 148 | mem->va = dma_alloc_coherent(&adapter->pdev->dev, mem->size, &mem->dma, |
| 149 | GFP_KERNEL); | 149 | GFP_KERNEL | __GFP_ZERO); |
| 150 | if (!mem->va) | 150 | if (!mem->va) |
| 151 | return -ENOMEM; | 151 | return -ENOMEM; |
| 152 | memset(mem->va, 0, mem->size); | ||
| 153 | return 0; | 152 | return 0; |
| 154 | } | 153 | } |
| 155 | 154 | ||
| 156 | static void be_intr_set(struct be_adapter *adapter, bool enable) | 155 | static void be_reg_intr_set(struct be_adapter *adapter, bool enable) |
| 157 | { | 156 | { |
| 158 | u32 reg, enabled; | 157 | u32 reg, enabled; |
| 159 | 158 | ||
| 160 | if (adapter->eeh_error) | ||
| 161 | return; | ||
| 162 | |||
| 163 | pci_read_config_dword(adapter->pdev, PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET, | 159 | pci_read_config_dword(adapter->pdev, PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET, |
| 164 | ®); | 160 | ®); |
| 165 | enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | 161 | enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; |
| @@ -175,6 +171,22 @@ static void be_intr_set(struct be_adapter *adapter, bool enable) · 9 unmodified lines | |||
| 175 | PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET, reg); | 171 | PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET, reg); |
| 176 | } | 172 | } |
| 177 | 173 | ||
| 174 | static void be_intr_set(struct be_adapter *adapter, bool enable) | ||
| 175 | { | ||
| 176 | int status = 0; | ||
| 177 | |||
| 178 | /* On lancer interrupts can't be controlled via this register */ | ||
| 179 | if (lancer_chip(adapter)) | ||
| 180 | return; | ||
| 181 | |||
| 182 | if (adapter->eeh_error) | ||
| 183 | return; | ||
| 184 | |||
| 185 | status = be_cmd_intr_set(adapter, enable); | ||
| 186 | if (status) | ||
| 187 | be_reg_intr_set(adapter, enable); | ||
| 188 | } | ||
| 189 | |||
| 178 | static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted) | 190 | static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted) |
| 179 | { | 191 | { |
| 180 | u32 val = 0; | 192 | u32 val = 0; |
| @@ -185,14 +197,15 @@ static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted) · 4 unmodified lines | |||
| 185 | iowrite32(val, adapter->db + DB_RQ_OFFSET); | 197 | iowrite32(val, adapter->db + DB_RQ_OFFSET); |
| 186 | } | 198 | } |
| 187 | 199 | ||
| 188 | static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted) | 200 | static void be_txq_notify(struct be_adapter *adapter, struct be_tx_obj *txo, |
| 201 | u16 posted) | ||
| 189 | { | 202 | { |
| 190 | u32 val = 0; | 203 | u32 val = 0; |
| 191 | val |= qid & DB_TXULP_RING_ID_MASK; | 204 | val |= txo->q.id & DB_TXULP_RING_ID_MASK; |
| 192 | val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT; | 205 | val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT; |
| 193 | 206 | ||
| 194 | wmb(); | 207 | wmb(); |
| 195 | iowrite32(val, adapter->db + DB_TXULP1_OFFSET); | 208 | iowrite32(val, adapter->db + txo->db_offset); |
| 196 | } | 209 | } |
| 197 | 210 | ||
| 198 | static void be_eq_notify(struct be_adapter *adapter, u16 qid, | 211 | static void be_eq_notify(struct be_adapter *adapter, u16 qid, |
| @@ -340,9 +353,9 @@ static void populate_be_v0_stats(struct be_adapter *adapter) · 141 unmodified lines | |||
| 340 | drvs->rx_input_fifo_overflow_drop = port_stats->rx_input_fifo_overflow; | 353 | drvs->rx_input_fifo_overflow_drop = port_stats->rx_input_fifo_overflow; |
| 341 | drvs->rx_dropped_header_too_small = | 354 | drvs->rx_dropped_header_too_small = |
| 342 | port_stats->rx_dropped_header_too_small; | 355 | port_stats->rx_dropped_header_too_small; |
| 343 | drvs->rx_address_mismatch_drops = | 356 | drvs->rx_address_filtered = |
| 344 | port_stats->rx_address_mismatch_drops + | 357 | port_stats->rx_address_filtered + |
| 345 | port_stats->rx_vlan_mismatch_drops; | 358 | port_stats->rx_vlan_filtered; |
| 346 | drvs->rx_alignment_symbol_errors = | 359 | drvs->rx_alignment_symbol_errors = |
| 347 | port_stats->rx_alignment_symbol_errors; | 360 | port_stats->rx_alignment_symbol_errors; |
| 348 | 361 | ||
| @@ -391,7 +404,7 @@ static void populate_be_v1_stats(struct be_adapter *adapter) · 42 unmodified lines | |||
| 391 | port_stats->rx_dropped_header_too_small; | 404 | port_stats->rx_dropped_header_too_small; |
| 392 | drvs->rx_input_fifo_overflow_drop = | 405 | drvs->rx_input_fifo_overflow_drop = |
| 393 | port_stats->rx_input_fifo_overflow_drop; | 406 | port_stats->rx_input_fifo_overflow_drop; |
| 394 | drvs->rx_address_mismatch_drops = port_stats->rx_address_mismatch_drops; | 407 | drvs->rx_address_filtered = port_stats->rx_address_filtered; |
| 395 | drvs->rx_alignment_symbol_errors = | 408 | drvs->rx_alignment_symbol_errors = |
| 396 | port_stats->rx_alignment_symbol_errors; | 409 | port_stats->rx_alignment_symbol_errors; |
| 397 | drvs->rxpp_fifo_overflow_drop = port_stats->rxpp_fifo_overflow_drop; | 410 | drvs->rxpp_fifo_overflow_drop = port_stats->rxpp_fifo_overflow_drop; |
| @@ -432,9 +445,9 @@ static void populate_lancer_stats(struct be_adapter *adapter) · 34 unmodified lines | |||
| 432 | drvs->rx_dropped_header_too_small = | 445 | drvs->rx_dropped_header_too_small = |
| 433 | pport_stats->rx_dropped_header_too_small; | 446 | pport_stats->rx_dropped_header_too_small; |
| 434 | drvs->rx_input_fifo_overflow_drop = pport_stats->rx_fifo_overflow; | 447 | drvs->rx_input_fifo_overflow_drop = pport_stats->rx_fifo_overflow; |
| 435 | drvs->rx_address_mismatch_drops = | 448 | drvs->rx_address_filtered = |
| 436 | pport_stats->rx_address_mismatch_drops + | 449 | pport_stats->rx_address_filtered + |
| 437 | pport_stats->rx_vlan_mismatch_drops; | 450 | pport_stats->rx_vlan_filtered; |
| 438 | drvs->rx_alignment_symbol_errors = pport_stats->rx_symbol_errors_lo; | 451 | drvs->rx_alignment_symbol_errors = pport_stats->rx_symbol_errors_lo; |
| 439 | drvs->rxpp_fifo_overflow_drop = pport_stats->rx_fifo_overflow; | 452 | drvs->rxpp_fifo_overflow_drop = pport_stats->rx_fifo_overflow; |
| 440 | drvs->tx_pauseframes = pport_stats->tx_pause_frames_lo; | 453 | drvs->tx_pauseframes = pport_stats->tx_pause_frames_lo; |
| @@ -626,13 +639,8 @@ static inline u16 be_get_tx_vlan_tag(struct be_adapter *adapter, · 185 unmodified lines | |||
| 626 | return vlan_tag; | 639 | return vlan_tag; |
| 627 | } | 640 | } |
| 628 | 641 | ||
| 629 | static int be_vlan_tag_chk(struct be_adapter *adapter, struct sk_buff *skb) | ||
| 630 | { | ||
| 631 | return vlan_tx_tag_present(skb) || adapter->pvid; | ||
| 632 | } | ||
| 633 | |||
| 634 | static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr, | 642 | static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr, |
| 635 | struct sk_buff *skb, u32 wrb_cnt, u32 len) | 643 | struct sk_buff *skb, u32 wrb_cnt, u32 len, bool skip_hw_vlan) |
| 636 | { | 644 | { |
| 637 | u16 vlan_tag; | 645 | u16 vlan_tag; |
| 638 | 646 | ||
| @@ -659,8 +667,9 @@ static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr, · 20 unmodified lines | |||
| 659 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag); | 667 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag); |
| 660 | } | 668 | } |
| 661 | 669 | ||
| 670 | /* To skip HW VLAN tagging: evt = 1, compl = 0 */ | ||
| 671 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, !skip_hw_vlan); | ||
| 662 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1); | 672 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1); |
| 663 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1); | ||
| 664 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt); | 673 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt); |
| 665 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len); | 674 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len); |
| 666 | } | 675 | } |
| @@ -683,7 +692,8 @@ static void unmap_tx_frag(struct device *dev, struct be_eth_wrb *wrb, · 16 unmodified lines | |||
| 683 | } | 692 | } |
| 684 | 693 | ||
| 685 | static int make_tx_wrbs(struct be_adapter *adapter, struct be_queue_info *txq, | 694 | static int make_tx_wrbs(struct be_adapter *adapter, struct be_queue_info *txq, |
| 686 | struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb) | 695 | struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb, |
| 696 | bool skip_hw_vlan) | ||
| 687 | { | 697 | { |
| 688 | dma_addr_t busaddr; | 698 | dma_addr_t busaddr; |
| 689 | int i, copied = 0; | 699 | int i, copied = 0; |
| @@ -732,7 +742,7 @@ static int make_tx_wrbs(struct be_adapter *adapter, struct be_queue_info *txq, · 42 unmodified lines | |||
| 732 | queue_head_inc(txq); | 742 | queue_head_inc(txq); |
| 733 | } | 743 | } |
| 734 | 744 | ||
| 735 | wrb_fill_hdr(adapter, hdr, first_skb, wrb_cnt, copied); | 745 | wrb_fill_hdr(adapter, hdr, first_skb, wrb_cnt, copied, skip_hw_vlan); |
| 736 | be_dws_cpu_to_le(hdr, sizeof(*hdr)); | 746 | be_dws_cpu_to_le(hdr, sizeof(*hdr)); |
| 737 | 747 | ||
| 738 | return copied; | 748 | return copied; |
| @@ -749,7 +759,8 @@ dma_err: · 10 unmodified lines | |||
| 749 | } | 759 | } |
| 750 | 760 | ||
| 751 | static struct sk_buff *be_insert_vlan_in_pkt(struct be_adapter *adapter, | 761 | static struct sk_buff *be_insert_vlan_in_pkt(struct be_adapter *adapter, |
| 752 | struct sk_buff *skb) | 762 | struct sk_buff *skb, |
| 763 | bool *skip_hw_vlan) | ||
| 753 | { | 764 | { |
| 754 | u16 vlan_tag = 0; | 765 | u16 vlan_tag = 0; |
| 755 | 766 | ||
| @@ -759,14 +770,72 @@ static struct sk_buff *be_insert_vlan_in_pkt(struct be_adapter *adapter, · 3 unmodified lines | |||
| 759 | 770 | ||
| 760 | if (vlan_tx_tag_present(skb)) { | 771 | if (vlan_tx_tag_present(skb)) { |
| 761 | vlan_tag = be_get_tx_vlan_tag(adapter, skb); | 772 | vlan_tag = be_get_tx_vlan_tag(adapter, skb); |
| 762 | skb = __vlan_put_tag(skb, vlan_tag); | 773 | skb = __vlan_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); |
| 763 | if (skb) | 774 | if (skb) |
| 764 | skb->vlan_tci = 0; | 775 | skb->vlan_tci = 0; |
| 765 | } | 776 | } |
| 766 | 777 | ||
| 778 | if (qnq_async_evt_rcvd(adapter) && adapter->pvid) { | ||
| 779 | if (!vlan_tag) | ||
| 780 | vlan_tag = adapter->pvid; | ||
| 781 | if (skip_hw_vlan) | ||
| 782 | *skip_hw_vlan = true; | ||
| 783 | } | ||
| 784 | |||
| 785 | if (vlan_tag) { | ||
| 786 | skb = __vlan_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | ||
| 787 | if (unlikely(!skb)) | ||
| 788 | return skb; | ||
| 789 | |||
| 790 | skb->vlan_tci = 0; | ||
| 791 | } | ||
| 792 | |||
| 793 | /* Insert the outer VLAN, if any */ | ||
| 794 | if (adapter->qnq_vid) { | ||
| 795 | vlan_tag = adapter->qnq_vid; | ||
| 796 | skb = __vlan_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | ||
| 797 | if (unlikely(!skb)) | ||
| 798 | return skb; | ||
| 799 | if (skip_hw_vlan) | ||
| 800 | *skip_hw_vlan = true; | ||
| 801 | } | ||
| 802 | |||
| 767 | return skb; | 803 | return skb; |
| 768 | } | 804 | } |
| 769 | 805 | ||
| 806 | static bool be_ipv6_exthdr_check(struct sk_buff *skb) | ||
| 807 | { | ||
| 808 | struct ethhdr *eh = (struct ethhdr *)skb->data; | ||
| 809 | u16 offset = ETH_HLEN; | ||
| 810 | |||
| 811 | if (eh->h_proto == htons(ETH_P_IPV6)) { | ||
| 812 | struct ipv6hdr *ip6h = (struct ipv6hdr *)(skb->data + offset); | ||
| 813 | |||
| 814 | offset += sizeof(struct ipv6hdr); | ||
| 815 | if (ip6h->nexthdr != NEXTHDR_TCP && | ||
| 816 | ip6h->nexthdr != NEXTHDR_UDP) { | ||
| 817 | struct ipv6_opt_hdr *ehdr = | ||
| 818 | (struct ipv6_opt_hdr *) (skb->data + offset); | ||
| 819 | |||
| 820 | /* offending pkt: 2nd byte following IPv6 hdr is 0xff */ | ||
| 821 | if (ehdr->hdrlen == 0xff) | ||
| 822 | return true; | ||
| 823 | } | ||
| 824 | } | ||
| 825 | return false; | ||
| 826 | } | ||
| 827 | |||
| 828 | static int be_vlan_tag_tx_chk(struct be_adapter *adapter, struct sk_buff *skb) | ||
| 829 | { | ||
| 830 | return vlan_tx_tag_present(skb) || adapter->pvid || adapter->qnq_vid; | ||
| 831 | } | ||
| 832 | |||
| 833 | static int be_ipv6_tx_stall_chk(struct be_adapter *adapter, struct sk_buff *skb) | ||
| 834 | { | ||
| 835 | return BE3_chip(adapter) && | ||
| 836 | be_ipv6_exthdr_check(skb); | ||
| 837 | } | ||
| 838 | |||
| 770 | static netdev_tx_t be_xmit(struct sk_buff *skb, | 839 | static netdev_tx_t be_xmit(struct sk_buff *skb, |
| 771 | struct net_device *netdev) | 840 | struct net_device *netdev) |
| 772 | { | 841 | { |
| @@ -777,33 +846,64 @@ static netdev_tx_t be_xmit(struct sk_buff *skb, · 4 unmodified lines | |||
| 777 | u32 wrb_cnt = 0, copied = 0; | 846 | u32 wrb_cnt = 0, copied = 0; |
| 778 | u32 start = txq->head, eth_hdr_len; | 847 | u32 start = txq->head, eth_hdr_len; |
| 779 | bool dummy_wrb, stopped = false; | 848 | bool dummy_wrb, stopped = false; |
| 849 | bool skip_hw_vlan = false; | ||
| 850 | struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data; | ||
| 780 | 851 | ||
| 781 | eth_hdr_len = ntohs(skb->protocol) == ETH_P_8021Q ? | 852 | eth_hdr_len = ntohs(skb->protocol) == ETH_P_8021Q ? |
| 782 | VLAN_ETH_HLEN : ETH_HLEN; | 853 | VLAN_ETH_HLEN : ETH_HLEN; |
| 783 | 854 | ||
| 784 | /* HW has a bug which considers padding bytes as legal | 855 | /* For padded packets, BE HW modifies tot_len field in IP header |
| 785 | * and modifies the IPv4 hdr's 'tot_len' field | 856 | * incorrecly when VLAN tag is inserted by HW. |
| 786 | */ | 857 | */ |
| 787 | if (skb->len <= 60 && be_vlan_tag_chk(adapter, skb) && | 858 | if (skb->len <= 60 && vlan_tx_tag_present(skb) && is_ipv4_pkt(skb)) { |
| 788 | is_ipv4_pkt(skb)) { | ||
| 789 | ip = (struct iphdr *)ip_hdr(skb); | 859 | ip = (struct iphdr *)ip_hdr(skb); |
| 790 | pskb_trim(skb, eth_hdr_len + ntohs(ip->tot_len)); | 860 | pskb_trim(skb, eth_hdr_len + ntohs(ip->tot_len)); |
| 791 | } | 861 | } |
| 792 | 862 | ||
| 863 | /* If vlan tag is already inlined in the packet, skip HW VLAN | ||
| 864 | * tagging in UMC mode | ||
| 865 | */ | ||
| 866 | if ((adapter->function_mode & UMC_ENABLED) && | ||
| 867 | veh->h_vlan_proto == htons(ETH_P_8021Q)) | ||
| 868 | skip_hw_vlan = true; | ||
| 869 | |||
| 793 | /* HW has a bug wherein it will calculate CSUM for VLAN | 870 | /* HW has a bug wherein it will calculate CSUM for VLAN |
| 794 | * pkts even though it is disabled. | 871 | * pkts even though it is disabled. |
| 795 | * Manually insert VLAN in pkt. | 872 | * Manually insert VLAN in pkt. |
| 796 | */ | 873 | */ |
| 797 | if (skb->ip_summed != CHECKSUM_PARTIAL && | 874 | if (skb->ip_summed != CHECKSUM_PARTIAL && |
| 798 | be_vlan_tag_chk(adapter, skb)) { | 875 | vlan_tx_tag_present(skb)) { |
| 799 | skb = be_insert_vlan_in_pkt(adapter, skb); | 876 | skb = be_insert_vlan_in_pkt(adapter, skb, &skip_hw_vlan); |
| 877 | if (unlikely(!skb)) | ||
| 878 | goto tx_drop; | ||
| 879 | } | ||
| 880 | |||
| 881 | /* HW may lockup when VLAN HW tagging is requested on | ||
| 882 | * certain ipv6 packets. Drop such pkts if the HW workaround to | ||
| 883 | * skip HW tagging is not enabled by FW. | ||
| 884 | */ | ||
| 885 | if (unlikely(be_ipv6_tx_stall_chk(adapter, skb) && | ||
| 886 | (adapter->pvid || adapter->qnq_vid) && | ||
| 887 | !qnq_async_evt_rcvd(adapter))) | ||
| 888 | goto tx_drop; | ||
| 889 | |||
| 890 | /* Manual VLAN tag insertion to prevent: | ||
| 891 | * ASIC lockup when the ASIC inserts VLAN tag into | ||
| 892 | * certain ipv6 packets. Insert VLAN tags in driver, | ||
| 893 | * and set event, completion, vlan bits accordingly | ||
| 894 | * in the Tx WRB. | ||
| 895 | */ | ||
| 896 | if (be_ipv6_tx_stall_chk(adapter, skb) && | ||
| 897 | be_vlan_tag_tx_chk(adapter, skb)) { | ||
| 898 | skb = be_insert_vlan_in_pkt(adapter, skb, &skip_hw_vlan); | ||
| 800 | if (unlikely(!skb)) | 899 | if (unlikely(!skb)) |
| 801 | goto tx_drop; | 900 | goto tx_drop; |
| 802 | } | 901 | } |
| 803 | 902 | ||
| 804 | wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb); | 903 | wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb); |
| 805 | 904 | ||
| 806 | copied = make_tx_wrbs(adapter, txq, skb, wrb_cnt, dummy_wrb); | 905 | copied = make_tx_wrbs(adapter, txq, skb, wrb_cnt, dummy_wrb, |
| 906 | skip_hw_vlan); | ||
| 807 | if (copied) { | 907 | if (copied) { |
| 808 | int gso_segs = skb_shinfo(skb)->gso_segs; | 908 | int gso_segs = skb_shinfo(skb)->gso_segs; |
| 809 | 909 | ||
| @@ -822,7 +922,7 @@ static netdev_tx_t be_xmit(struct sk_buff *skb, · 12 unmodified lines | |||
| 822 | stopped = true; | 922 | stopped = true; |
| 823 | } | 923 | } |
| 824 | 924 | ||
| 825 | be_txq_notify(adapter, txq->id, wrb_cnt); | 925 | be_txq_notify(adapter, txo, wrb_cnt); |
| 826 | 926 | ||
| 827 | be_tx_stats_update(txo, wrb_cnt, copied, gso_segs, stopped); | 927 | be_tx_stats_update(txo, wrb_cnt, copied, gso_segs, stopped); |
| 828 | } else { | 928 | } else { |
| @@ -891,7 +991,7 @@ set_vlan_promisc: · 62 unmodified lines | |||
| 891 | return status; | 991 | return status; |
| 892 | } | 992 | } |
| 893 | 993 | ||
| 894 | static int be_vlan_add_vid(struct net_device *netdev, u16 vid) | 994 | static int be_vlan_add_vid(struct net_device *netdev, __be16 proto, u16 vid) |
| 895 | { | 995 | { |
| 896 | struct be_adapter *adapter = netdev_priv(netdev); | 996 | struct be_adapter *adapter = netdev_priv(netdev); |
| 897 | int status = 0; | 997 | int status = 0; |
| @@ -917,7 +1017,7 @@ ret: · 19 unmodified lines | |||
| 917 | return status; | 1017 | return status; |
| 918 | } | 1018 | } |
| 919 | 1019 | ||
| 920 | static int be_vlan_rem_vid(struct net_device *netdev, u16 vid) | 1020 | static int be_vlan_rem_vid(struct net_device *netdev, __be16 proto, u16 vid) |
| 921 | { | 1021 | { |
| 922 | struct be_adapter *adapter = netdev_priv(netdev); | 1022 | struct be_adapter *adapter = netdev_priv(netdev); |
| 923 | int status = 0; | 1023 | int status = 0; |
| @@ -1372,7 +1472,7 @@ static void be_rx_compl_process(struct be_rx_obj *rxo, · 448 unmodified lines | |||
| 1372 | 1472 | ||
| 1373 | 1473 | ||
| 1374 | if (rxcp->vlanf) | 1474 | if (rxcp->vlanf) |
| 1375 | __vlan_hwaccel_put_tag(skb, rxcp->vlan_tag); | 1475 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rxcp->vlan_tag); |
| 1376 | 1476 | ||
| 1377 | netif_receive_skb(skb); | 1477 | netif_receive_skb(skb); |
| 1378 | } | 1478 | } |
| @@ -1428,7 +1528,7 @@ void be_rx_compl_process_gro(struct be_rx_obj *rxo, struct napi_struct *napi, · 49 unmodified lines | |||
| 1428 | skb->rxhash = rxcp->rss_hash; | 1528 | skb->rxhash = rxcp->rss_hash; |
| 1429 | 1529 | ||
| 1430 | if (rxcp->vlanf) | 1530 | if (rxcp->vlanf) |
| 1431 | __vlan_hwaccel_put_tag(skb, rxcp->vlan_tag); | 1531 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rxcp->vlan_tag); |
| 1432 | 1532 | ||
| 1433 | napi_gro_frags(napi); | 1533 | napi_gro_frags(napi); |
| 1434 | } | 1534 | } |
| @@ -1958,7 +2058,7 @@ static int be_tx_qs_create(struct be_adapter *adapter) · 523 unmodified lines | |||
| 1958 | if (status) | 2058 | if (status) |
| 1959 | return status; | 2059 | return status; |
| 1960 | 2060 | ||
| 1961 | status = be_cmd_txq_create(adapter, &txo->q, &txo->cq); | 2061 | status = be_cmd_txq_create(adapter, txo); |
| 1962 | if (status) | 2062 | if (status) |
| 1963 | return status; | 2063 | return status; |
| 1964 | } | 2064 | } |
| @@ -2436,9 +2536,6 @@ static int be_close(struct net_device *netdev) · 471 unmodified lines | |||
| 2436 | 2536 | ||
| 2437 | be_roce_dev_close(adapter); | 2537 | be_roce_dev_close(adapter); |
| 2438 | 2538 | ||
| 2439 | if (!lancer_chip(adapter)) | ||
| 2440 | be_intr_set(adapter, false); | ||
| 2441 | |||
| 2442 | for_all_evt_queues(adapter, eqo, i) | 2539 | for_all_evt_queues(adapter, eqo, i) |
| 2443 | napi_disable(&eqo->napi); | 2540 | napi_disable(&eqo->napi); |
| 2444 | 2541 | ||
| @@ -2500,9 +2597,19 @@ static int be_rx_qs_create(struct be_adapter *adapter) · 55 unmodified lines | |||
| 2500 | rsstable[j + i] = rxo->rss_id; | 2597 | rsstable[j + i] = rxo->rss_id; |
| 2501 | } | 2598 | } |
| 2502 | } | 2599 | } |
| 2503 | rc = be_cmd_rss_config(adapter, rsstable, 128); | 2600 | adapter->rss_flags = RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 | |
| 2504 | if (rc) | 2601 | RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6; |
| 2602 | |||
| 2603 | if (!BEx_chip(adapter)) | ||
| 2604 | adapter->rss_flags |= RSS_ENABLE_UDP_IPV4 | | ||
| 2605 | RSS_ENABLE_UDP_IPV6; | ||
| 2606 | |||
| 2607 | rc = be_cmd_rss_config(adapter, rsstable, adapter->rss_flags, | ||
| 2608 | 128); | ||
| 2609 | if (rc) { | ||
| 2610 | adapter->rss_flags = 0; | ||
| 2505 | return rc; | 2611 | return rc; |
| 2612 | } | ||
| 2506 | } | 2613 | } |
| 2507 | 2614 | ||
| 2508 | /* First time posting */ | 2615 | /* First time posting */ |
| @@ -2526,9 +2633,6 @@ static int be_open(struct net_device *netdev) · 17 unmodified lines | |||
| 2526 | 2633 | ||
| 2527 | be_irq_register(adapter); | 2634 | be_irq_register(adapter); |
| 2528 | 2635 | ||
| 2529 | if (!lancer_chip(adapter)) | ||
| 2530 | be_intr_set(adapter, true); | ||
| 2531 | |||
| 2532 | for_all_rx_queues(adapter, rxo, i) | 2636 | for_all_rx_queues(adapter, rxo, i) |
| 2533 | be_cq_notify(adapter, rxo->cq.id, true, 0); | 2637 | be_cq_notify(adapter, rxo->cq.id, true, 0); |
| 2534 | 2638 | ||
| @@ -2563,10 +2667,9 @@ static int be_setup_wol(struct be_adapter *adapter, bool enable) · 28 unmodified lines | |||
| 2563 | 2667 | ||
| 2564 | cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config); | 2668 | cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config); |
| 2565 | cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma, | 2669 | cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma, |
| 2566 | GFP_KERNEL); | 2670 | GFP_KERNEL | __GFP_ZERO); |
| 2567 | if (cmd.va == NULL) | 2671 | if (cmd.va == NULL) |
| 2568 | return -1; | 2672 | return -1; |
| 2569 | memset(cmd.va, 0, cmd.size); | ||
| 2570 | 2673 | ||
| 2571 | if (enable) { | 2674 | if (enable) { |
| 2572 | status = pci_write_config_dword(adapter->pdev, | 2675 | status = pci_write_config_dword(adapter->pdev, |
| @@ -2714,7 +2817,8 @@ static int be_vfs_if_create(struct be_adapter *adapter) · 141 unmodified lines | |||
| 2714 | 2817 | ||
| 2715 | for_all_vfs(adapter, vf_cfg, vf) { | 2818 | for_all_vfs(adapter, vf_cfg, vf) { |
| 2716 | if (!BE3_chip(adapter)) | 2819 | if (!BE3_chip(adapter)) |
| 2717 | be_cmd_get_profile_config(adapter, &cap_flags, vf + 1); | 2820 | be_cmd_get_profile_config(adapter, &cap_flags, |
| 2821 | NULL, vf + 1); | ||
| 2718 | 2822 | ||
| 2719 | /* If a FW profile exists, then cap_flags are updated */ | 2823 | /* If a FW profile exists, then cap_flags are updated */ |
| 2720 | en_flags = cap_flags & (BE_IF_FLAGS_UNTAGGED | | 2824 | en_flags = cap_flags & (BE_IF_FLAGS_UNTAGGED | |
| @@ -2878,11 +2982,14 @@ static void be_get_resources(struct be_adapter *adapter) · 157 unmodified lines | |||
| 2878 | u16 dev_num_vfs; | 2982 | u16 dev_num_vfs; |
| 2879 | int pos, status; | 2983 | int pos, status; |
| 2880 | bool profile_present = false; | 2984 | bool profile_present = false; |
| 2985 | u16 txq_count = 0; | ||
| 2881 | 2986 | ||
| 2882 | if (!BEx_chip(adapter)) { | 2987 | if (!BEx_chip(adapter)) { |
| 2883 | status = be_cmd_get_func_config(adapter); | 2988 | status = be_cmd_get_func_config(adapter); |
| 2884 | if (!status) | 2989 | if (!status) |
| 2885 | profile_present = true; | 2990 | profile_present = true; |
| 2991 | } else if (BE3_chip(adapter) && be_physfn(adapter)) { | ||
| 2992 | be_cmd_get_profile_config(adapter, NULL, &txq_count, 0); | ||
| 2886 | } | 2993 | } |
| 2887 | 2994 | ||
| 2888 | if (profile_present) { | 2995 | if (profile_present) { |
| @@ -2920,7 +3027,9 @@ static void be_get_resources(struct be_adapter *adapter) · 31 unmodified lines | |||
| 2920 | adapter->max_vlans = BE_NUM_VLANS_SUPPORTED; | 3027 | adapter->max_vlans = BE_NUM_VLANS_SUPPORTED; |
| 2921 | 3028 | ||
| 2922 | adapter->max_mcast_mac = BE_MAX_MC; | 3029 | adapter->max_mcast_mac = BE_MAX_MC; |
| 2923 | adapter->max_tx_queues = MAX_TX_QS; | 3030 | adapter->max_tx_queues = txq_count ? txq_count : MAX_TX_QS; |
| 3031 | adapter->max_tx_queues = min_t(u16, adapter->max_tx_queues, | ||
| 3032 | MAX_TX_QS); | ||
| 2924 | adapter->max_rss_queues = (adapter->be3_native) ? | 3033 | adapter->max_rss_queues = (adapter->be3_native) ? |
| 2925 | BE3_MAX_RSS_QS : BE2_MAX_RSS_QS; | 3034 | BE3_MAX_RSS_QS : BE2_MAX_RSS_QS; |
| 2926 | adapter->max_event_queues = BE3_MAX_RSS_QS; | 3035 | adapter->max_event_queues = BE3_MAX_RSS_QS; |
| @@ -2954,7 +3063,8 @@ static int be_get_config(struct be_adapter *adapter) · 27 unmodified lines | |||
| 2954 | 3063 | ||
| 2955 | status = be_cmd_query_fw_cfg(adapter, &adapter->port_num, | 3064 | status = be_cmd_query_fw_cfg(adapter, &adapter->port_num, |
| 2956 | &adapter->function_mode, | 3065 | &adapter->function_mode, |
| 2957 | &adapter->function_caps); | 3066 | &adapter->function_caps, |
| 3067 | &adapter->asic_rev); | ||
| 2958 | if (status) | 3068 | if (status) |
| 2959 | goto err; | 3069 | goto err; |
| 2960 | 3070 | ||
| @@ -3215,7 +3325,7 @@ static int be_flash(struct be_adapter *adapter, const u8 *img, · 254 unmodified lines | |||
| 3215 | return 0; | 3325 | return 0; |
| 3216 | } | 3326 | } |
| 3217 | 3327 | ||
| 3218 | /* For BE2 and BE3 */ | 3328 | /* For BE2, BE3 and BE3-R */ |
| 3219 | static int be_flash_BEx(struct be_adapter *adapter, | 3329 | static int be_flash_BEx(struct be_adapter *adapter, |
| 3220 | const struct firmware *fw, | 3330 | const struct firmware *fw, |
| 3221 | struct be_dma_mem *flash_cmd, | 3331 | struct be_dma_mem *flash_cmd, |
| @@ -3458,11 +3568,9 @@ static int lancer_fw_download(struct be_adapter *adapter, · 236 unmodified lines | |||
| 3458 | flash_cmd.size = sizeof(struct lancer_cmd_req_write_object) | 3568 | flash_cmd.size = sizeof(struct lancer_cmd_req_write_object) |
| 3459 | + LANCER_FW_DOWNLOAD_CHUNK; | 3569 | + LANCER_FW_DOWNLOAD_CHUNK; |
| 3460 | flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size, | 3570 | flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size, |
| 3461 | &flash_cmd.dma, GFP_KERNEL); | 3571 | &flash_cmd.dma, GFP_KERNEL); |
| 3462 | if (!flash_cmd.va) { | 3572 | if (!flash_cmd.va) { |
| 3463 | status = -ENOMEM; | 3573 | status = -ENOMEM; |
| 3464 | dev_err(&adapter->pdev->dev, | ||
| 3465 | "Memory allocation failure while flashing\n"); | ||
| 3466 | goto lancer_fw_exit; | 3574 | goto lancer_fw_exit; |
| 3467 | } | 3575 | } |
| 3468 | 3576 | ||
| @@ -3530,18 +3638,22 @@ lancer_fw_exit: · 61 unmodified lines | |||
| 3530 | 3638 | ||
| 3531 | #define UFI_TYPE2 2 | 3639 | #define UFI_TYPE2 2 |
| 3532 | #define UFI_TYPE3 3 | 3640 | #define UFI_TYPE3 3 |
| 3641 | #define UFI_TYPE3R 10 | ||
| 3533 | #define UFI_TYPE4 4 | 3642 | #define UFI_TYPE4 4 |
| 3534 | static int be_get_ufi_type(struct be_adapter *adapter, | 3643 | static int be_get_ufi_type(struct be_adapter *adapter, |
| 3535 | struct flash_file_hdr_g2 *fhdr) | 3644 | struct flash_file_hdr_g3 *fhdr) |
| 3536 | { | 3645 | { |
| 3537 | if (fhdr == NULL) | 3646 | if (fhdr == NULL) |
| 3538 | goto be_get_ufi_exit; | 3647 | goto be_get_ufi_exit; |
| 3539 | 3648 | ||
| 3540 | if (skyhawk_chip(adapter) && fhdr->build[0] == '4') | 3649 | if (skyhawk_chip(adapter) && fhdr->build[0] == '4') |
| 3541 | return UFI_TYPE4; | 3650 | return UFI_TYPE4; |
| 3542 | else if (BE3_chip(adapter) && fhdr->build[0] == '3') | 3651 | else if (BE3_chip(adapter) && fhdr->build[0] == '3') { |
| 3543 | return UFI_TYPE3; | 3652 | if (fhdr->asic_type_rev == 0x10) |
| 3544 | else if (BE2_chip(adapter) && fhdr->build[0] == '2') | 3653 | return UFI_TYPE3R; |
| 3654 | else | ||
| 3655 | return UFI_TYPE3; | ||
| 3656 | } else if (BE2_chip(adapter) && fhdr->build[0] == '2') | ||
| 3545 | return UFI_TYPE2; | 3657 | return UFI_TYPE2; |
| 3546 | 3658 | ||
| 3547 | be_get_ufi_exit: | 3659 | be_get_ufi_exit: |
| @@ -3552,7 +3664,6 @@ be_get_ufi_exit: · 4 unmodified lines | |||
| 3552 | 3664 | ||
| 3553 | static int be_fw_download(struct be_adapter *adapter, const struct firmware* fw) | 3665 | static int be_fw_download(struct be_adapter *adapter, const struct firmware* fw) |
| 3554 | { | 3666 | { |
| 3555 | struct flash_file_hdr_g2 *fhdr; | ||
| 3556 | struct flash_file_hdr_g3 *fhdr3; | 3667 | struct flash_file_hdr_g3 *fhdr3; |
| 3557 | struct image_hdr *img_hdr_ptr = NULL; | 3668 | struct image_hdr *img_hdr_ptr = NULL; |
| 3558 | struct be_dma_mem flash_cmd; | 3669 | struct be_dma_mem flash_cmd; |
| @@ -3564,29 +3675,41 @@ static int be_fw_download(struct be_adapter *adapter, const struct firmware* fw) · 5 unmodified lines | |||
| 3564 | &flash_cmd.dma, GFP_KERNEL); | 3675 | &flash_cmd.dma, GFP_KERNEL); |
| 3565 | if (!flash_cmd.va) { | 3676 | if (!flash_cmd.va) { |
| 3566 | status = -ENOMEM; | 3677 | status = -ENOMEM; |
| 3567 | dev_err(&adapter->pdev->dev, | ||
| 3568 | "Memory allocation failure while flashing\n"); | ||
| 3569 | goto be_fw_exit; | 3678 | goto be_fw_exit; |
| 3570 | } | 3679 | } |
| 3571 | 3680 | ||
| 3572 | p = fw->data; | 3681 | p = fw->data; |
| 3573 | fhdr = (struct flash_file_hdr_g2 *)p; | 3682 | fhdr3 = (struct flash_file_hdr_g3 *)p; |
| 3574 | 3683 | ||
| 3575 | ufi_type = be_get_ufi_type(adapter, fhdr); | 3684 | ufi_type = be_get_ufi_type(adapter, fhdr3); |
| 3576 | 3685 | ||
| 3577 | fhdr3 = (struct flash_file_hdr_g3 *)fw->data; | ||
| 3578 | num_imgs = le32_to_cpu(fhdr3->num_imgs); | 3686 | num_imgs = le32_to_cpu(fhdr3->num_imgs); |
| 3579 | for (i = 0; i < num_imgs; i++) { | 3687 | for (i = 0; i < num_imgs; i++) { |
| 3580 | img_hdr_ptr = (struct image_hdr *)(fw->data + | 3688 | img_hdr_ptr = (struct image_hdr *)(fw->data + |
| 3581 | (sizeof(struct flash_file_hdr_g3) + | 3689 | (sizeof(struct flash_file_hdr_g3) + |
| 3582 | i * sizeof(struct image_hdr))); | 3690 | i * sizeof(struct image_hdr))); |
| 3583 | if (le32_to_cpu(img_hdr_ptr->imageid) == 1) { | 3691 | if (le32_to_cpu(img_hdr_ptr->imageid) == 1) { |
| 3584 | if (ufi_type == UFI_TYPE4) | 3692 | switch (ufi_type) { |
| 3693 | case UFI_TYPE4: | ||
| 3585 | status = be_flash_skyhawk(adapter, fw, | 3694 | status = be_flash_skyhawk(adapter, fw, |
| 3586 | &flash_cmd, num_imgs); | 3695 | &flash_cmd, num_imgs); |
| 3587 | else if (ufi_type == UFI_TYPE3) | 3696 | break; |
| 3697 | case UFI_TYPE3R: | ||
| 3588 | status = be_flash_BEx(adapter, fw, &flash_cmd, | 3698 | status = be_flash_BEx(adapter, fw, &flash_cmd, |
| 3589 | num_imgs); | 3699 | num_imgs); |
| 3700 | break; | ||
| 3701 | case UFI_TYPE3: | ||
| 3702 | /* Do not flash this ufi on BE3-R cards */ | ||
| 3703 | if (adapter->asic_rev < 0x10) | ||
| 3704 | status = be_flash_BEx(adapter, fw, | ||
| 3705 | &flash_cmd, | ||
| 3706 | num_imgs); | ||
| 3707 | else { | ||
| 3708 | status = -1; | ||
| 3709 | dev_err(&adapter->pdev->dev, | ||
| 3710 | "Can't load BE3 UFI on BE3R\n"); | ||
| 3711 | } | ||
| 3712 | } | ||
| 3590 | } | 3713 | } |
| 3591 | } | 3714 | } |
| 3592 | 3715 | ||
| @@ -3663,12 +3786,12 @@ static void be_netdev_init(struct net_device *netdev) · 70 unmodified lines | |||
| 3663 | 3786 | ||
| 3664 | netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | | 3787 | netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | |
| 3665 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | | 3788 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | |
| 3666 | NETIF_F_HW_VLAN_TX; | 3789 | NETIF_F_HW_VLAN_CTAG_TX; |
| 3667 | if (be_multi_rxq(adapter)) | 3790 | if (be_multi_rxq(adapter)) |
| 3668 | netdev->hw_features |= NETIF_F_RXHASH; | 3791 | netdev->hw_features |= NETIF_F_RXHASH; |
| 3669 | 3792 | ||
| 3670 | netdev->features |= netdev->hw_features | | 3793 | netdev->features |= netdev->hw_features | |
| 3671 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER; | 3794 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER; |
| 3672 | 3795 | ||
| 3673 | netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | | 3796 | netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | |
| 3674 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; | 3797 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
| @@ -3792,12 +3915,13 @@ static int be_ctrl_init(struct be_adapter *adapter) · 117 unmodified lines | |||
| 3792 | 3915 | ||
| 3793 | rx_filter->size = sizeof(struct be_cmd_req_rx_filter); | 3916 | rx_filter->size = sizeof(struct be_cmd_req_rx_filter); |
| 3794 | rx_filter->va = dma_alloc_coherent(&adapter->pdev->dev, rx_filter->size, | 3917 | rx_filter->va = dma_alloc_coherent(&adapter->pdev->dev, rx_filter->size, |
| 3795 | &rx_filter->dma, GFP_KERNEL); | 3918 | &rx_filter->dma, |
| 3919 | GFP_KERNEL | __GFP_ZERO); | ||
| 3796 | if (rx_filter->va == NULL) { | 3920 | if (rx_filter->va == NULL) { |
| 3797 | status = -ENOMEM; | 3921 | status = -ENOMEM; |
| 3798 | goto free_mbox; | 3922 | goto free_mbox; |
| 3799 | } | 3923 | } |
| 3800 | memset(rx_filter->va, 0, rx_filter->size); | 3924 | |
| 3801 | mutex_init(&adapter->mbox_lock); | 3925 | mutex_init(&adapter->mbox_lock); |
| 3802 | spin_lock_init(&adapter->mcc_lock); | 3926 | spin_lock_init(&adapter->mcc_lock); |
| 3803 | spin_lock_init(&adapter->mcc_cq_lock); | 3927 | spin_lock_init(&adapter->mcc_cq_lock); |
| @@ -3839,10 +3963,9 @@ static int be_stats_init(struct be_adapter *adapter) · 35 unmodified lines | |||
| 3839 | cmd->size = sizeof(struct be_cmd_req_get_stats_v1); | 3963 | cmd->size = sizeof(struct be_cmd_req_get_stats_v1); |
| 3840 | 3964 | ||
| 3841 | cmd->va = dma_alloc_coherent(&adapter->pdev->dev, cmd->size, &cmd->dma, | 3965 | cmd->va = dma_alloc_coherent(&adapter->pdev->dev, cmd->size, &cmd->dma, |
| 3842 | GFP_KERNEL); | 3966 | GFP_KERNEL | __GFP_ZERO); |
| 3843 | if (cmd->va == NULL) | 3967 | if (cmd->va == NULL) |
| 3844 | return -1; | 3968 | return -1; |
| 3845 | memset(cmd->va, 0, cmd->size); | ||
| 3846 | return 0; | 3969 | return 0; |
| 3847 | } | 3970 | } |
| 3848 | 3971 | ||
| @@ -3854,6 +3977,7 @@ static void be_remove(struct pci_dev *pdev) · 5 unmodified lines | |||
| 3854 | return; | 3977 | return; |
| 3855 | 3978 | ||
| 3856 | be_roce_dev_remove(adapter); | 3979 | be_roce_dev_remove(adapter); |
| 3980 | be_intr_set(adapter, false); | ||
| 3857 | 3981 | ||
| 3858 | cancel_delayed_work_sync(&adapter->func_recovery_work); | 3982 | cancel_delayed_work_sync(&adapter->func_recovery_work); |
| 3859 | 3983 | ||
| @@ -4108,6 +4232,11 @@ static int be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id) · 248 unmodified lines | |||
| 4108 | 4232 | ||
| 4109 | status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); | 4233 | status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
| 4110 | if (!status) { | 4234 | if (!status) { |
| 4235 | status = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | ||
| 4236 | if (status < 0) { | ||
| 4237 | dev_err(&pdev->dev, "dma_set_coherent_mask failed\n"); | ||
| 4238 | goto free_netdev; | ||
| 4239 | } | ||
| 4111 | netdev->features |= NETIF_F_HIGHDMA; | 4240 | netdev->features |= NETIF_F_HIGHDMA; |
| 4112 | } else { | 4241 | } else { |
| 4113 | status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); | 4242 | status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
| @@ -4132,22 +4261,22 @@ static int be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id) · 18 unmodified lines | |||
| 4132 | goto ctrl_clean; | 4261 | goto ctrl_clean; |
| 4133 | } | 4262 | } |
| 4134 | 4263 | ||
| 4135 | /* tell fw we're ready to fire cmds */ | ||
| 4136 | status = be_cmd_fw_init(adapter); | ||
| 4137 | if (status) | ||
| 4138 | goto ctrl_clean; | ||
| 4139 | |||
| 4140 | if (be_reset_required(adapter)) { | 4264 | if (be_reset_required(adapter)) { |
| 4141 | status = be_cmd_reset_function(adapter); | 4265 | status = be_cmd_reset_function(adapter); |
| 4142 | if (status) | 4266 | if (status) |
| 4143 | goto ctrl_clean; | 4267 | goto ctrl_clean; |
| 4268 | |||
| 4269 | /* Wait for interrupts to quiesce after an FLR */ | ||
| 4270 | msleep(100); | ||
| 4144 | } | 4271 | } |
| 4145 | 4272 | ||
| 4146 | /* The INTR bit may be set in the card when probed by a kdump kernel | 4273 | /* Allow interrupts for other ULPs running on NIC function */ |
| 4147 | * after a crash. | 4274 | be_intr_set(adapter, true); |
| 4148 | */ | 4275 | |
| 4149 | if (!lancer_chip(adapter)) | 4276 | /* tell fw we're ready to fire cmds */ |
| 4150 | be_intr_set(adapter, false); | 4277 | status = be_cmd_fw_init(adapter); |
| 4278 | if (status) | ||
| 4279 | goto ctrl_clean; | ||
| 4151 | 4280 | ||
| 4152 | status = be_stats_init(adapter); | 4281 | status = be_stats_init(adapter); |
| 4153 | if (status) | 4282 | if (status) |
| @@ -4358,12 +4487,12 @@ static void be_eeh_resume(struct pci_dev *pdev) · 204 unmodified lines | |||
| 4358 | 4487 | ||
| 4359 | pci_save_state(pdev); | 4488 | pci_save_state(pdev); |
| 4360 | 4489 | ||
| 4361 | /* tell fw we're ready to fire cmds */ | 4490 | status = be_cmd_reset_function(adapter); |
| 4362 | status = be_cmd_fw_init(adapter); | ||
| 4363 | if (status) | 4491 | if (status) |
| 4364 | goto err; | 4492 | goto err; |
| 4365 | 4493 | ||
| 4366 | status = be_cmd_reset_function(adapter); | 4494 | /* tell fw we're ready to fire cmds */ |
| 4495 | status = be_cmd_fw_init(adapter); | ||
| 4367 | if (status) | 4496 | if (status) |
| 4368 | goto err; | 4497 | goto err; |
| 4369 | 4498 | ||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2005 - 2011 Emulex | 2 | * Copyright (C) 2005 - 2013 Emulex |
| 3 | * All rights reserved. | 3 | * All rights reserved. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2005 - 2011 Emulex | 2 | * Copyright (C) 2005 - 2013 Emulex |
| 3 | * All rights reserved. | 3 | * All rights reserved. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
| @@ -780,12 +780,11 @@ static int ftgmac100_alloc_buffers(struct ftgmac100 *priv) · 779 unmodified lines | |||
| 780 | 780 | ||
| 781 | priv->descs = dma_alloc_coherent(priv->dev, | 781 | priv->descs = dma_alloc_coherent(priv->dev, |
| 782 | sizeof(struct ftgmac100_descs), | 782 | sizeof(struct ftgmac100_descs), |
| 783 | &priv->descs_dma_addr, GFP_KERNEL); | 783 | &priv->descs_dma_addr, |
| 784 | GFP_KERNEL | __GFP_ZERO); | ||
| 784 | if (!priv->descs) | 785 | if (!priv->descs) |
| 785 | return -ENOMEM; | 786 | return -ENOMEM; |
| 786 | 787 | ||
| 787 | memset(priv->descs, 0, sizeof(struct ftgmac100_descs)); | ||
| 788 | |||
| 789 | /* initialize RX ring */ | 788 | /* initialize RX ring */ |
| 790 | ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]); | 789 | ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]); |
| 791 | 790 | ||
| @@ -1350,22 +1349,7 @@ static struct platform_driver ftgmac100_driver = { · 558 unmodified lines | |||
| 1350 | }, | 1349 | }, |
| 1351 | }; | 1350 | }; |
| 1352 | 1351 | ||
| 1353 | /****************************************************************************** | 1352 | module_platform_driver(ftgmac100_driver); |
| 1354 | * initialization / finalization | ||
| 1355 | *****************************************************************************/ | ||
| 1356 | static int __init ftgmac100_init(void) | ||
| 1357 | { | ||
| 1358 | pr_info("Loading version " DRV_VERSION " ...\n"); | ||
| 1359 | return platform_driver_register(&ftgmac100_driver); | ||
| 1360 | } | ||
| 1361 | |||
| 1362 | static void __exit ftgmac100_exit(void) | ||
| 1363 | { | ||
| 1364 | platform_driver_unregister(&ftgmac100_driver); | ||
| 1365 | } | ||
| 1366 | |||
| 1367 | module_init(ftgmac100_init); | ||
| 1368 | module_exit(ftgmac100_exit); | ||
| 1369 | 1353 | ||
| 1370 | MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); | 1354 | MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); |
| 1371 | MODULE_DESCRIPTION("FTGMAC100 driver"); | 1355 | MODULE_DESCRIPTION("FTGMAC100 driver"); |
| @@ -732,13 +732,13 @@ static int ftmac100_alloc_buffers(struct ftmac100 *priv) · 731 unmodified lines | |||
| 732 | { | 732 | { |
| 733 | int i; | 733 | int i; |
| 734 | 734 | ||
| 735 | priv->descs = dma_alloc_coherent(priv->dev, sizeof(struct ftmac100_descs), | 735 | priv->descs = dma_alloc_coherent(priv->dev, |
| 736 | &priv->descs_dma_addr, GFP_KERNEL); | 736 | sizeof(struct ftmac100_descs), |
| 737 | &priv->descs_dma_addr, | ||
| 738 | GFP_KERNEL | __GFP_ZERO); | ||
| 737 | if (!priv->descs) | 739 | if (!priv->descs) |
| 738 | return -ENOMEM; | 740 | return -ENOMEM; |
| 739 | 741 | ||
| 740 | memset(priv->descs, 0, sizeof(struct ftmac100_descs)); | ||
| 741 | |||
| 742 | /* initialize RX ring */ | 742 | /* initialize RX ring */ |
| 743 | ftmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]); | 743 | ftmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]); |
| 744 | 744 | ||
| @@ -2,7 +2,8 @@ · 1 unmodified line | |||
| 2 | # Makefile for the Freescale network device drivers. | 2 | # Makefile for the Freescale network device drivers. |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-$(CONFIG_FEC) += fec.o fec_ptp.o | 5 | obj-$(CONFIG_FEC) += fec.o |
| 6 | fec-objs :=fec_main.o fec_ptp.o | ||
| 6 | obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx.o | 7 | obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx.o |
| 7 | ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y) | 8 | ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y) |
| 8 | obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx_phy.o | 9 | obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx_phy.o |
| @@ -52,6 +52,7 @@ · 51 unmodified lines | |||
| 52 | #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ | 52 | #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ |
| 53 | #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ | 53 | #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ |
| 54 | #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ | 54 | #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ |
| 55 | #define FEC_RACC 0x1C4 /* Receive Accelerator function */ | ||
| 55 | #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ | 56 | #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ |
| 56 | #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ | 57 | #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ |
| 57 | 58 | ||
| @@ -164,9 +165,11 @@ struct bufdesc_ex { · 106 unmodified lines | |||
| 164 | #define BD_ENET_TX_CSL ((ushort)0x0001) | 165 | #define BD_ENET_TX_CSL ((ushort)0x0001) |
| 165 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ | 166 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ |
| 166 | 167 | ||
| 167 | /*enhanced buffer desciptor control/status used by Ethernet transmit*/ | 168 | /*enhanced buffer descriptor control/status used by Ethernet transmit*/ |
| 168 | #define BD_ENET_TX_INT 0x40000000 | 169 | #define BD_ENET_TX_INT 0x40000000 |
| 169 | #define BD_ENET_TX_TS 0x20000000 | 170 | #define BD_ENET_TX_TS 0x20000000 |
| 171 | #define BD_ENET_TX_PINS 0x10000000 | ||
| 172 | #define BD_ENET_TX_IINS 0x08000000 | ||
| 170 | 173 | ||
| 171 | 174 | ||
| 172 | /* This device has up to three irqs on some platforms */ | 175 | /* This device has up to three irqs on some platforms */ |
| @@ -190,6 +193,10 @@ struct bufdesc_ex { · 17 unmodified lines | |||
| 190 | 193 | ||
| 191 | #define BD_ENET_RX_INT 0x00800000 | 194 | #define BD_ENET_RX_INT 0x00800000 |
| 192 | #define BD_ENET_RX_PTP ((ushort)0x0400) | 195 | #define BD_ENET_RX_PTP ((ushort)0x0400) |
| 196 | #define BD_ENET_RX_ICE 0x00000020 | ||
| 197 | #define BD_ENET_RX_PCR 0x00000010 | ||
| 198 | #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) | ||
| 199 | #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR) | ||
| 193 | 200 | ||
| 194 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | 201 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and |
| 195 | * tx_bd_base always point to the base of the buffer descriptors. The | 202 | * tx_bd_base always point to the base of the buffer descriptors. The |
| @@ -247,6 +254,7 @@ struct fec_enet_private { · 51 unmodified lines | |||
| 247 | int pause_flag; | 254 | int pause_flag; |
| 248 | 255 | ||
| 249 | struct napi_struct napi; | 256 | struct napi_struct napi; |
| 257 | int csum_flags; | ||
| 250 | 258 | ||
| 251 | struct ptp_clock *ptp_clock; | 259 | struct ptp_clock *ptp_clock; |
| 252 | struct ptp_clock_info ptp_caps; | 260 | struct ptp_clock_info ptp_caps; |
| @@ -29,12 +29,17 @@ · 28 unmodified lines | |||
| 29 | #include <linux/ioport.h> | 29 | #include <linux/ioport.h> |
| 30 | #include <linux/slab.h> | 30 | #include <linux/slab.h> |
| 31 | #include <linux/interrupt.h> | 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/pci.h> | ||
| 33 | #include <linux/init.h> | 32 | #include <linux/init.h> |
| 34 | #include <linux/delay.h> | 33 | #include <linux/delay.h> |
| 35 | #include <linux/netdevice.h> | 34 | #include <linux/netdevice.h> |
| 36 | #include <linux/etherdevice.h> | 35 | #include <linux/etherdevice.h> |
| 37 | #include <linux/skbuff.h> | 36 | #include <linux/skbuff.h> |
| 37 | #include <linux/in.h> | ||
| 38 | #include <linux/ip.h> | ||
| 39 | #include <net/ip.h> | ||
| 40 | #include <linux/tcp.h> | ||
| 41 | #include <linux/udp.h> | ||
| 42 | #include <linux/icmp.h> | ||
| 38 | #include <linux/spinlock.h> | 43 | #include <linux/spinlock.h> |
| 39 | #include <linux/workqueue.h> | 44 | #include <linux/workqueue.h> |
| 40 | #include <linux/bitops.h> | 45 | #include <linux/bitops.h> |
| @@ -53,11 +58,6 @@ · 12 unmodified lines | |||
| 53 | 58 | ||
| 54 | #include <asm/cacheflush.h> | 59 | #include <asm/cacheflush.h> |
| 55 | 60 | ||
| 56 | #ifndef CONFIG_ARM | ||
| 57 | #include <asm/coldfire.h> | ||
| 58 | #include <asm/mcfsim.h> | ||
| 59 | #endif | ||
| 60 | |||
| 61 | #include "fec.h" | 61 | #include "fec.h" |
| 62 | 62 | ||
| 63 | #if defined(CONFIG_ARM) | 63 | #if defined(CONFIG_ARM) |
| @@ -106,6 +106,9 @@ static struct platform_device_id fec_devtype[] = { · 42 unmodified lines | |||
| 106 | .name = "imx6q-fec", | 106 | .name = "imx6q-fec", |
| 107 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | | 107 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
| 108 | FEC_QUIRK_HAS_BUFDESC_EX, | 108 | FEC_QUIRK_HAS_BUFDESC_EX, |
| 109 | }, { | ||
| 110 | .name = "mvf-fec", | ||
| 111 | .driver_data = FEC_QUIRK_ENET_MAC, | ||
| 109 | }, { | 112 | }, { |
| 110 | /* sentinel */ | 113 | /* sentinel */ |
| 111 | } | 114 | } |
| @@ -117,6 +120,7 @@ enum imx_fec_type { · 5 unmodified lines | |||
| 117 | IMX27_FEC, /* runs on i.mx27/35/51 */ | 120 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
| 118 | IMX28_FEC, | 121 | IMX28_FEC, |
| 119 | IMX6Q_FEC, | 122 | IMX6Q_FEC, |
| 123 | MVF_FEC, | ||
| 120 | }; | 124 | }; |
| 121 | 125 | ||
| 122 | static const struct of_device_id fec_dt_ids[] = { | 126 | static const struct of_device_id fec_dt_ids[] = { |
| @@ -124,6 +128,7 @@ static const struct of_device_id fec_dt_ids[] = { · 1 unmodified line | |||
| 124 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | 128 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, |
| 125 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | 129 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, |
| 126 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, | 130 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
| 131 | { .compatible = "fsl,mvf-fec", .data = &fec_devtype[MVF_FEC], }, | ||
| 127 | { /* sentinel */ } | 132 | { /* sentinel */ } |
| 128 | }; | 133 | }; |
| 129 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | 134 | MODULE_DEVICE_TABLE(of, fec_dt_ids); |
| @@ -177,6 +182,11 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); · 47 unmodified lines | |||
| 177 | #define PKT_MINBUF_SIZE 64 | 182 | #define PKT_MINBUF_SIZE 64 |
| 178 | #define PKT_MAXBLR_SIZE 1520 | 183 | #define PKT_MAXBLR_SIZE 1520 |
| 179 | 184 | ||
| 185 | /* FEC receive acceleration */ | ||
| 186 | #define FEC_RACC_IPDIS (1 << 1) | ||
| 187 | #define FEC_RACC_PRODIS (1 << 2) | ||
| 188 | #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) | ||
| 189 | |||
| 180 | /* | 190 | /* |
| 181 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame | 191 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
| 182 | * size bits. Other FEC hardware does not, so we need to take that into | 192 | * size bits. Other FEC hardware does not, so we need to take that into |
| @@ -237,6 +247,21 @@ static void *swap_buffer(void *bufaddr, int len) · 54 unmodified lines | |||
| 237 | return bufaddr; | 247 | return bufaddr; |
| 238 | } | 248 | } |
| 239 | 249 | ||
| 250 | static int | ||
| 251 | fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) | ||
| 252 | { | ||
| 253 | /* Only run for packets requiring a checksum. */ | ||
| 254 | if (skb->ip_summed != CHECKSUM_PARTIAL) | ||
| 255 | return 0; | ||
| 256 | |||
| 257 | if (unlikely(skb_cow_head(skb, 0))) | ||
| 258 | return -1; | ||
| 259 | |||
| 260 | *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; | ||
| 261 | |||
| 262 | return 0; | ||
| 263 | } | ||
| 264 | |||
| 240 | static netdev_tx_t | 265 | static netdev_tx_t |
| 241 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) | 266 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
| 242 | { | 267 | { |
| @@ -249,7 +274,7 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) · 6 unmodified lines | |||
| 249 | unsigned int index; | 274 | unsigned int index; |
| 250 | 275 | ||
| 251 | if (!fep->link) { | 276 | if (!fep->link) { |
| 252 | /* Link is down or autonegotiation is in progress. */ | 277 | /* Link is down or auto-negotiation is in progress. */ |
| 253 | return NETDEV_TX_BUSY; | 278 | return NETDEV_TX_BUSY; |
| 254 | } | 279 | } |
| 255 | 280 | ||
| @@ -262,10 +287,16 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) · 6 unmodified lines | |||
| 262 | /* Ooops. All transmit buffers are full. Bail out. | 287 | /* Ooops. All transmit buffers are full. Bail out. |
| 263 | * This should not happen, since ndev->tbusy should be set. | 288 | * This should not happen, since ndev->tbusy should be set. |
| 264 | */ | 289 | */ |
| 265 | printk("%s: tx queue full!.\n", ndev->name); | 290 | netdev_err(ndev, "tx queue full!\n"); |
| 266 | return NETDEV_TX_BUSY; | 291 | return NETDEV_TX_BUSY; |
| 267 | } | 292 | } |
| 268 | 293 | ||
| 294 | /* Protocol checksum off-load for TCP and UDP. */ | ||
| 295 | if (fec_enet_clear_csum(skb, ndev)) { | ||
| 296 | kfree_skb(skb); | ||
| 297 | return NETDEV_TX_OK; | ||
| 298 | } | ||
| 299 | |||
| 269 | /* Clear all of the status flags */ | 300 | /* Clear all of the status flags */ |
| 270 | status &= ~BD_ENET_TX_STATS; | 301 | status &= ~BD_ENET_TX_STATS; |
| 271 | 302 | ||
| @@ -322,8 +353,14 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) · 50 unmodified lines | |||
| 322 | ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); | 353 | ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); |
| 323 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | 354 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
| 324 | } else { | 355 | } else { |
| 325 | |||
| 326 | ebdp->cbd_esc = BD_ENET_TX_INT; | 356 | ebdp->cbd_esc = BD_ENET_TX_INT; |
| 357 | |||
| 358 | /* Enable protocol checksum flags | ||
| 359 | * We do not bother with the IP Checksum bits as they | ||
| 360 | * are done by the kernel | ||
| 361 | */ | ||
| 362 | if (skb->ip_summed == CHECKSUM_PARTIAL) | ||
| 363 | ebdp->cbd_esc |= BD_ENET_TX_PINS; | ||
| 327 | } | 364 | } |
| 328 | } | 365 | } |
| 329 | /* If this was the last BD in the ring, start at the beginning again. */ | 366 | /* If this was the last BD in the ring, start at the beginning again. */ |
| @@ -403,6 +440,7 @@ fec_restart(struct net_device *ndev, int duplex) · 73 unmodified lines | |||
| 403 | const struct platform_device_id *id_entry = | 440 | const struct platform_device_id *id_entry = |
| 404 | platform_get_device_id(fep->pdev); | 441 | platform_get_device_id(fep->pdev); |
| 405 | int i; | 442 | int i; |
| 443 | u32 val; | ||
| 406 | u32 temp_mac[2]; | 444 | u32 temp_mac[2]; |
| 407 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | 445 | u32 rcntl = OPT_FRAME_SIZE | 0x04; |
| 408 | u32 ecntl = 0x2; /* ETHEREN */ | 446 | u32 ecntl = 0x2; /* ETHEREN */ |
| @@ -469,6 +507,14 @@ fec_restart(struct net_device *ndev, int duplex) · 60 unmodified lines | |||
| 469 | /* Set MII speed */ | 507 | /* Set MII speed */ |
| 470 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | 508 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
| 471 | 509 | ||
| 510 | /* set RX checksum */ | ||
| 511 | val = readl(fep->hwp + FEC_RACC); | ||
| 512 | if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) | ||
| 513 | val |= FEC_RACC_OPTIONS; | ||
| 514 | else | ||
| 515 | val &= ~FEC_RACC_OPTIONS; | ||
| 516 | writel(val, fep->hwp + FEC_RACC); | ||
| 517 | |||
| 472 | /* | 518 | /* |
| 473 | * The phy interface and speed need to get configured | 519 | * The phy interface and speed need to get configured |
| 474 | * differently on enet-mac. | 520 | * differently on enet-mac. |
| @@ -526,7 +572,7 @@ fec_restart(struct net_device *ndev, int duplex) · 51 unmodified lines | |||
| 526 | fep->phy_dev && fep->phy_dev->pause)) { | 572 | fep->phy_dev && fep->phy_dev->pause)) { |
| 527 | rcntl |= FEC_ENET_FCE; | 573 | rcntl |= FEC_ENET_FCE; |
| 528 | 574 | ||
| 529 | /* set FIFO thresh hold parameter to reduce overrun */ | 575 | /* set FIFO threshold parameter to reduce overrun */ |
| 530 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); | 576 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); |
| 531 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | 577 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); |
| 532 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | 578 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); |
| @@ -574,7 +620,7 @@ fec_stop(struct net_device *ndev) · 41 unmodified lines | |||
| 574 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | 620 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ |
| 575 | udelay(10); | 621 | udelay(10); |
| 576 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | 622 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) |
| 577 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | 623 | netdev_err(ndev, "Graceful transmit stop did not complete!\n"); |
| 578 | } | 624 | } |
| 579 | 625 | ||
| 580 | /* Whack a reset. We should wait for this. */ | 626 | /* Whack a reset. We should wait for this. */ |
| @@ -672,7 +718,7 @@ fec_enet_tx(struct net_device *ndev) · 91 unmodified lines | |||
| 672 | } | 718 | } |
| 673 | 719 | ||
| 674 | if (status & BD_ENET_TX_READY) | 720 | if (status & BD_ENET_TX_READY) |
| 675 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); | 721 | netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); |
| 676 | 722 | ||
| 677 | /* Deferred means some collisions occurred during transmit, | 723 | /* Deferred means some collisions occurred during transmit, |
| 678 | * but we eventually sent the packet OK. | 724 | * but we eventually sent the packet OK. |
| @@ -740,7 +786,7 @@ fec_enet_rx(struct net_device *ndev, int budget) · 61 unmodified lines | |||
| 740 | * the last indicator should be set. | 786 | * the last indicator should be set. |
| 741 | */ | 787 | */ |
| 742 | if ((status & BD_ENET_RX_LAST) == 0) | 788 | if ((status & BD_ENET_RX_LAST) == 0) |
| 743 | printk("FEC ENET: rcv is not +last\n"); | 789 | netdev_err(ndev, "rcv is not +last\n"); |
| 744 | 790 | ||
| 745 | if (!fep->opened) | 791 | if (!fep->opened) |
| 746 | goto rx_processing_done; | 792 | goto rx_processing_done; |
| @@ -791,8 +837,6 @@ fec_enet_rx(struct net_device *ndev, int budget) · 44 unmodified lines | |||
| 791 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); | 837 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
| 792 | 838 | ||
| 793 | if (unlikely(!skb)) { | 839 | if (unlikely(!skb)) { |
| 794 | printk("%s: Memory squeeze, dropping packet.\n", | ||
| 795 | ndev->name); | ||
| 796 | ndev->stats.rx_dropped++; | 840 | ndev->stats.rx_dropped++; |
| 797 | } else { | 841 | } else { |
| 798 | skb_reserve(skb, NET_IP_ALIGN); | 842 | skb_reserve(skb, NET_IP_ALIGN); |
| @@ -816,6 +860,18 @@ fec_enet_rx(struct net_device *ndev, int budget) · 17 unmodified lines | |||
| 816 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); | 860 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
| 817 | } | 861 | } |
| 818 | 862 | ||
| 863 | if (fep->bufdesc_ex && | ||
| 864 | (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { | ||
| 865 | struct bufdesc_ex *ebdp = | ||
| 866 | (struct bufdesc_ex *)bdp; | ||
| 867 | if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { | ||
| 868 | /* don't check it */ | ||
| 869 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 870 | } else { | ||
| 871 | skb_checksum_none_assert(skb); | ||
| 872 | } | ||
| 873 | } | ||
| 874 | |||
| 819 | if (!skb_defer_rx_timestamp(skb)) | 875 | if (!skb_defer_rx_timestamp(skb)) |
| 820 | napi_gro_receive(&fep->napi, skb); | 876 | napi_gro_receive(&fep->napi, skb); |
| 821 | } | 877 | } |
| @@ -916,7 +972,6 @@ static void fec_get_mac(struct net_device *ndev) · 94 unmodified lines | |||
| 916 | */ | 972 | */ |
| 917 | iap = macaddr; | 973 | iap = macaddr; |
| 918 | 974 | ||
| 919 | #ifdef CONFIG_OF | ||
| 920 | /* | 975 | /* |
| 921 | * 2) from device tree data | 976 | * 2) from device tree data |
| 922 | */ | 977 | */ |
| @@ -928,7 +983,6 @@ static void fec_get_mac(struct net_device *ndev) · 5 unmodified lines | |||
| 928 | iap = (unsigned char *) mac; | 983 | iap = (unsigned char *) mac; |
| 929 | } | 984 | } |
| 930 | } | 985 | } |
| 931 | #endif | ||
| 932 | 986 | ||
| 933 | /* | 987 | /* |
| 934 | * 3) from flash or fuse (via platform data) | 988 | * 3) from flash or fuse (via platform data) |
| @@ -1032,7 +1086,7 @@ static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) · 97 unmodified lines | |||
| 1032 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | 1086 | usecs_to_jiffies(FEC_MII_TIMEOUT)); |
| 1033 | if (time_left == 0) { | 1087 | if (time_left == 0) { |
| 1034 | fep->mii_timeout = 1; | 1088 | fep->mii_timeout = 1; |
| 1035 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | 1089 | netdev_err(fep->netdev, "MDIO read timeout\n"); |
| 1036 | return -ETIMEDOUT; | 1090 | return -ETIMEDOUT; |
| 1037 | } | 1091 | } |
| 1038 | 1092 | ||
| @@ -1060,7 +1114,7 @@ static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, · 21 unmodified lines | |||
| 1060 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | 1114 | usecs_to_jiffies(FEC_MII_TIMEOUT)); |
| 1061 | if (time_left == 0) { | 1115 | if (time_left == 0) { |
| 1062 | fep->mii_timeout = 1; | 1116 | fep->mii_timeout = 1; |
| 1063 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | 1117 | netdev_err(fep->netdev, "MDIO write timeout\n"); |
| 1064 | return -ETIMEDOUT; | 1118 | return -ETIMEDOUT; |
| 1065 | } | 1119 | } |
| 1066 | 1120 | ||
| @@ -1100,9 +1154,7 @@ static int fec_enet_mii_probe(struct net_device *ndev) · 33 unmodified lines | |||
| 1100 | } | 1154 | } |
| 1101 | 1155 | ||
| 1102 | if (phy_id >= PHY_MAX_ADDR) { | 1156 | if (phy_id >= PHY_MAX_ADDR) { |
| 1103 | printk(KERN_INFO | 1157 | netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); |
| 1104 | "%s: no PHY, assuming direct connection to switch\n", | ||
| 1105 | ndev->name); | ||
| 1106 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); | 1158 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
| 1107 | phy_id = 0; | 1159 | phy_id = 0; |
| 1108 | } | 1160 | } |
| @@ -1111,7 +1163,7 @@ static int fec_enet_mii_probe(struct net_device *ndev) · 2 unmodified lines | |||
| 1111 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, | 1163 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, |
| 1112 | fep->phy_interface); | 1164 | fep->phy_interface); |
| 1113 | if (IS_ERR(phy_dev)) { | 1165 | if (IS_ERR(phy_dev)) { |
| 1114 | printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name); | 1166 | netdev_err(ndev, "could not attach to PHY\n"); |
| 1115 | return PTR_ERR(phy_dev); | 1167 | return PTR_ERR(phy_dev); |
| 1116 | } | 1168 | } |
| 1117 | 1169 | ||
| @@ -1129,11 +1181,9 @@ static int fec_enet_mii_probe(struct net_device *ndev) · 11 unmodified lines | |||
| 1129 | fep->link = 0; | 1181 | fep->link = 0; |
| 1130 | fep->full_duplex = 0; | 1182 | fep->full_duplex = 0; |
| 1131 | 1183 | ||
| 1132 | printk(KERN_INFO | 1184 | netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
| 1133 | "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | 1185 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), |
| 1134 | ndev->name, | 1186 | fep->phy_dev->irq); |
| 1135 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), | ||
| 1136 | fep->phy_dev->irq); | ||
| 1137 | 1187 | ||
| 1138 | return 0; | 1188 | return 0; |
| 1139 | } | 1189 | } |
| @@ -1443,7 +1493,7 @@ static int fec_enet_alloc_buffers(struct net_device *ndev) · 303 unmodified lines | |||
| 1443 | 1493 | ||
| 1444 | if (fep->bufdesc_ex) { | 1494 | if (fep->bufdesc_ex) { |
| 1445 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | 1495 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
| 1446 | ebdp->cbd_esc = BD_ENET_RX_INT; | 1496 | ebdp->cbd_esc = BD_ENET_TX_INT; |
| 1447 | } | 1497 | } |
| 1448 | 1498 | ||
| 1449 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | 1499 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
| @@ -1608,7 +1658,7 @@ fec_set_mac_address(struct net_device *ndev, void *p) · 158 unmodified lines | |||
| 1608 | * Polled functionality used by netconsole and others in non interrupt mode | 1658 | * Polled functionality used by netconsole and others in non interrupt mode |
| 1609 | * | 1659 | * |
| 1610 | */ | 1660 | */ |
| 1611 | void fec_poll_controller(struct net_device *dev) | 1661 | static void fec_poll_controller(struct net_device *dev) |
| 1612 | { | 1662 | { |
| 1613 | int i; | 1663 | int i; |
| 1614 | struct fec_enet_private *fep = netdev_priv(dev); | 1664 | struct fec_enet_private *fep = netdev_priv(dev); |
| @@ -1623,6 +1673,33 @@ void fec_poll_controller(struct net_device *dev) · 8 unmodified lines | |||
| 1623 | } | 1673 | } |
| 1624 | #endif | 1674 | #endif |
| 1625 | 1675 | ||
| 1676 | static int fec_set_features(struct net_device *netdev, | ||
| 1677 | netdev_features_t features) | ||
| 1678 | { | ||
| 1679 | struct fec_enet_private *fep = netdev_priv(netdev); | ||
| 1680 | netdev_features_t changed = features ^ netdev->features; | ||
| 1681 | |||
| 1682 | netdev->features = features; | ||
| 1683 | |||
| 1684 | /* Receive checksum has been changed */ | ||
| 1685 | if (changed & NETIF_F_RXCSUM) { | ||
| 1686 | if (features & NETIF_F_RXCSUM) | ||
| 1687 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | ||
| 1688 | else | ||
| 1689 | fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; | ||
| 1690 | |||
| 1691 | if (netif_running(netdev)) { | ||
| 1692 | fec_stop(netdev); | ||
| 1693 | fec_restart(netdev, fep->phy_dev->duplex); | ||
| 1694 | netif_wake_queue(netdev); | ||
| 1695 | } else { | ||
| 1696 | fec_restart(netdev, fep->phy_dev->duplex); | ||
| 1697 | } | ||
| 1698 | } | ||
| 1699 | |||
| 1700 | return 0; | ||
| 1701 | } | ||
| 1702 | |||
| 1626 | static const struct net_device_ops fec_netdev_ops = { | 1703 | static const struct net_device_ops fec_netdev_ops = { |
| 1627 | .ndo_open = fec_enet_open, | 1704 | .ndo_open = fec_enet_open, |
| 1628 | .ndo_stop = fec_enet_close, | 1705 | .ndo_stop = fec_enet_close, |
| @@ -1636,6 +1713,7 @@ static const struct net_device_ops fec_netdev_ops = { · 7 unmodified lines | |||
| 1636 | #ifdef CONFIG_NET_POLL_CONTROLLER | 1713 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1637 | .ndo_poll_controller = fec_poll_controller, | 1714 | .ndo_poll_controller = fec_poll_controller, |
| 1638 | #endif | 1715 | #endif |
| 1716 | .ndo_set_features = fec_set_features, | ||
| 1639 | }; | 1717 | }; |
| 1640 | 1718 | ||
| 1641 | /* | 1719 | /* |
| @@ -1649,11 +1727,9 @@ static int fec_enet_init(struct net_device *ndev) · 7 unmodified lines | |||
| 1649 | 1727 | ||
| 1650 | /* Allocate memory for buffer descriptors. */ | 1728 | /* Allocate memory for buffer descriptors. */ |
| 1651 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | 1729 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, |
| 1652 | GFP_KERNEL); | 1730 | GFP_KERNEL); |
| 1653 | if (!cbd_base) { | 1731 | if (!cbd_base) |
| 1654 | printk("FEC: allocate descriptor memory failed?\n"); | ||
| 1655 | return -ENOMEM; | 1732 | return -ENOMEM; |
| 1656 | } | ||
| 1657 | 1733 | ||
| 1658 | memset(cbd_base, 0, PAGE_SIZE); | 1734 | memset(cbd_base, 0, PAGE_SIZE); |
| 1659 | spin_lock_init(&fep->hw_lock); | 1735 | spin_lock_init(&fep->hw_lock); |
| @@ -1679,22 +1755,19 @@ static int fec_enet_init(struct net_device *ndev) · 19 unmodified lines | |||
| 1679 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); | 1755 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
| 1680 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); | 1756 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); |
| 1681 | 1757 | ||
| 1758 | /* enable hw accelerator */ | ||
| 1759 | ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | ||
| 1760 | | NETIF_F_RXCSUM); | ||
| 1761 | ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | ||
| 1762 | | NETIF_F_RXCSUM); | ||
| 1763 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | ||
| 1764 | |||
| 1682 | fec_restart(ndev, 0); | 1765 | fec_restart(ndev, 0); |
| 1683 | 1766 | ||
| 1684 | return 0; | 1767 | return 0; |
| 1685 | } | 1768 | } |
| 1686 | 1769 | ||
| 1687 | #ifdef CONFIG_OF | 1770 | #ifdef CONFIG_OF |
| 1688 | static int fec_get_phy_mode_dt(struct platform_device *pdev) | ||
| 1689 | { | ||
| 1690 | struct device_node *np = pdev->dev.of_node; | ||
| 1691 | |||
| 1692 | if (np) | ||
| 1693 | return of_get_phy_mode(np); | ||
| 1694 | |||
| 1695 | return -ENODEV; | ||
| 1696 | } | ||
| 1697 | |||
| 1698 | static void fec_reset_phy(struct platform_device *pdev) | 1771 | static void fec_reset_phy(struct platform_device *pdev) |
| 1699 | { | 1772 | { |
| 1700 | int err, phy_reset; | 1773 | int err, phy_reset; |
| @@ -1723,11 +1796,6 @@ static void fec_reset_phy(struct platform_device *pdev) · 22 unmodified lines | |||
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