Renesas fixes for v6.6 (take three) - Sort out a few Kconfig dependency issues for the rich set of RISC-V non-coherent DMA support. * tag 'renesas-fixes-for-v6.6-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT
Unified · Split
| @@ -273,11 +273,9 @@ config RISCV_DMA_NONCOHERENT · 272 unmodified lines | ||
| 273 | 273 | select ARCH_HAS_SYNC_DMA_FOR_CPU |
| 274 | 274 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
| 275 | 275 | select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB |
| 276 | − select DMA_DIRECT_REMAP if MMU | |
| 277 | 276 | |
| 278 | 277 | config RISCV_NONSTANDARD_CACHE_OPS |
| 279 | 278 | bool |
| 280 | − depends on RISCV_DMA_NONCOHERENT | |
| 281 | 279 | help |
| 282 | 280 | This enables function pointer support for non-standard noncoherent |
| 283 | 281 | systems to handle cache management. |
| @@ -550,6 +548,7 @@ config RISCV_ISA_ZICBOM · 266 unmodified lines | ||
| 550 | 548 | depends on RISCV_ALTERNATIVE |
| 551 | 549 | default y |
| 552 | 550 | select RISCV_DMA_NONCOHERENT |
| 551 | + select DMA_DIRECT_REMAP | |
| 553 | 552 | help |
| 554 | 553 | Adds support to dynamically detect the presence of the ZICBOM |
| 555 | 554 | extension (Cache Block Management Operations) and enable its |
| @@ -77,6 +77,7 @@ config ERRATA_THEAD_PBMT · 76 unmodified lines | ||
| 77 | 77 | config ERRATA_THEAD_CMO |
| 78 | 78 | bool "Apply T-Head cache management errata" |
| 79 | 79 | depends on ERRATA_THEAD && MMU |
| 80 | + select DMA_DIRECT_REMAP | |
| 80 | 81 | select RISCV_DMA_NONCOHERENT |
| 81 | 82 | default y |
| 82 | 83 | help |
| @@ -3,7 +3,7 @@ menu "Cache Drivers" · 2 unmodified lines | ||
| 3 | 3 | |
| 4 | 4 | config AX45MP_L2_CACHE |
| 5 | 5 | bool "Andes Technology AX45MP L2 Cache controller" |
| 6 | − depends on RISCV_DMA_NONCOHERENT | |
| 6 | + depends on RISCV | |
| 7 | 7 | select RISCV_NONSTANDARD_CACHE_OPS |
| 8 | 8 | help |
| 9 | 9 | Support for the L2 cache controller on Andes Technology AX45MP platforms. |
| @@ -335,6 +335,7 @@ config ARCH_R9A07G043 · 334 unmodified lines | ||
| 335 | 335 | bool "RISC-V Platform support for RZ/Five" |
| 336 | 336 | depends on NONPORTABLE |
| 337 | 337 | depends on RISCV_ALTERNATIVE |
| 338 | + depends on !RISCV_ISA_ZICBOM | |
| 338 | 339 | depends on RISCV_SBI |
| 339 | 340 | select ARCH_RZG2L |
| 340 | 341 | select AX45MP_L2_CACHE |