Split resume into a 3rd step to handle displays when DCC is enabled on DCN 4.0.1. Move display after the buffer funcs have been re-enabled so that the GPU will do the move and properly set the DCC metadata for DCN. v2: fix fence irq resume ordering
Unified · Split
| @@ -3762,7 +3762,7 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) · 3761 unmodified lines | |||
| 3762 | * | 3762 | * |
| 3763 | * @adev: amdgpu_device pointer | 3763 | * @adev: amdgpu_device pointer |
| 3764 | * | 3764 | * |
| 3765 | * First resume function for hardware IPs. The list of all the hardware | 3765 | * Second resume function for hardware IPs. The list of all the hardware |
| 3766 | * IPs that make up the asic is walked and the resume callbacks are run for | 3766 | * IPs that make up the asic is walked and the resume callbacks are run for |
| 3767 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | 3767 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a |
| 3768 | * functional state after a suspend and updates the software state as | 3768 | * functional state after a suspend and updates the software state as |
| @@ -3780,6 +3780,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) · 11 unmodified lines | |||
| 3780 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | 3780 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
| 3781 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | 3781 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
| 3782 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || | 3782 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
| 3783 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE || | ||
| 3783 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | 3784 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) |
| 3784 | continue; | 3785 | continue; |
| 3785 | r = amdgpu_ip_block_resume(&adev->ip_blocks[i]); | 3786 | r = amdgpu_ip_block_resume(&adev->ip_blocks[i]); |
| @@ -3790,6 +3791,36 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) · 4 unmodified lines | |||
| 3790 | return 0; | 3791 | return 0; |
| 3791 | } | 3792 | } |
| 3792 | 3793 | ||
| 3794 | /** | ||
| 3795 | * amdgpu_device_ip_resume_phase3 - run resume for hardware IPs | ||
| 3796 | * | ||
| 3797 | * @adev: amdgpu_device pointer | ||
| 3798 | * | ||
| 3799 | * Third resume function for hardware IPs. The list of all the hardware | ||
| 3800 | * IPs that make up the asic is walked and the resume callbacks are run for | ||
| 3801 | * all DCE. resume puts the hardware into a functional state after a suspend | ||
| 3802 | * and updates the software state as necessary. This function is also used | ||
| 3803 | * for restoring the GPU after a GPU reset. | ||
| 3804 | * | ||
| 3805 | * Returns 0 on success, negative error code on failure. | ||
| 3806 | */ | ||
| 3807 | static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev) | ||
| 3808 | { | ||
| 3809 | int i, r; | ||
| 3810 | |||
| 3811 | for (i = 0; i < adev->num_ip_blocks; i++) { | ||
| 3812 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) | ||
| 3813 | continue; | ||
| 3814 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) { | ||
| 3815 | r = amdgpu_ip_block_resume(&adev->ip_blocks[i]); | ||
| 3816 | if (r) | ||
| 3817 | return r; | ||
| 3818 | } | ||
| 3819 | } | ||
| 3820 | |||
| 3821 | return 0; | ||
| 3822 | } | ||
| 3823 | |||
| 3793 | /** | 3824 | /** |
| 3794 | * amdgpu_device_ip_resume - run resume for hardware IPs | 3825 | * amdgpu_device_ip_resume - run resume for hardware IPs |
| 3795 | * | 3826 | * |
| @@ -3819,6 +3850,13 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev) · 23 unmodified lines | |||
| 3819 | if (adev->mman.buffer_funcs_ring->sched.ready) | 3850 | if (adev->mman.buffer_funcs_ring->sched.ready) |
| 3820 | amdgpu_ttm_set_buffer_funcs_status(adev, true); | 3851 | amdgpu_ttm_set_buffer_funcs_status(adev, true); |
| 3821 | 3852 | ||
| 3853 | if (r) | ||
| 3854 | return r; | ||
| 3855 | |||
| 3856 | amdgpu_fence_driver_hw_init(adev); | ||
| 3857 | |||
| 3858 | r = amdgpu_device_ip_resume_phase3(adev); | ||
| 3859 | |||
| 3822 | return r; | 3860 | return r; |
| 3823 | } | 3861 | } |
| 3824 | 3862 | ||
| @@ -4899,7 +4937,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool notify_clients) · 1074 unmodified lines | |||
| 4899 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); | 4937 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
| 4900 | goto exit; | 4938 | goto exit; |
| 4901 | } | 4939 | } |
| 4902 | amdgpu_fence_driver_hw_init(adev); | ||
| 4903 | 4940 | ||
| 4904 | if (!adev->in_s0ix) { | 4941 | if (!adev->in_s0ix) { |
| 4905 | r = amdgpu_amdkfd_resume(adev, adev->in_runpm); | 4942 | r = amdgpu_amdkfd_resume(adev, adev->in_runpm); |
| @@ -5484,6 +5521,10 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) · 578 unmodified lines | |||
| 5484 | if (tmp_adev->mman.buffer_funcs_ring->sched.ready) | 5521 | if (tmp_adev->mman.buffer_funcs_ring->sched.ready) |
| 5485 | amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); | 5522 | amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); |
| 5486 | 5523 | ||
| 5524 | r = amdgpu_device_ip_resume_phase3(tmp_adev); | ||
| 5525 | if (r) | ||
| 5526 | goto out; | ||
| 5527 | |||
| 5487 | if (vram_lost) | 5528 | if (vram_lost) |
| 5488 | amdgpu_device_fill_reset_magic(tmp_adev); | 5529 | amdgpu_device_fill_reset_magic(tmp_adev); |
| 5489 | 5530 | ||