- use the atomic helpers for plane_upate/disable hooks (Matt Roper) - refactor the initial plane config code (Damien) - ppgtt prep patches for dynamic pagetable alloc (Ben Widawsky, reworked and rebased by a lot of other people) - framebuffer modifier support from Tvrtko Ursulin, drm core code from Rob Clark - piles of workaround patches for skl from Damien and Nick Hoath - vGPU support for xengt on the client side (Yu Zhang) - and the usual smaller things all over * tag 'drm-intel-next-2015-02-14' of git://anongit.freedesktop.org/drm-intel: (88 commits) drm/i915: Update DRIVER_DATE to 20150214 drm/i915: Remove references to previously removed UMS config option drm/i915/skl: Use a LRI for WaDisableDgMirrorFixInHalfSliceChicken5 drm/i915/skl: Fix always true comparison in a revision id check drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrement drm/i915/skl: Implement WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken drm/i915: Add process identifier to requests drm/i915/skl: Implement WaBarrierPerformanceFixDisable drm/i915/skl: Implement WaCcsTlbPrefetchDisable:skl drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS drm/i915/skl: Implement WaDisableHDCInvalidation drm/i915/skl: Implement WaDisableLSQCROPERFforOCL drm/i915/skl: Implement WaDisablePartialResolveInVc drm/i915/skl: Introduce a SKL specific init_workarounds() drm/i915/skl: Document that we implement WaRsClearFWBitsAtReset drm/i915/skl: Implement WaSetGAPSunitClckGateDisable drm/i915/skl: Make the init clock gating function skylake specific drm/i915/skl: Provide a gen9 specific init_render_ring() drm/i915/skl: Document the WM read latency W/A with its name drm/i915/skl: Also detect eDRAM on SKL ...
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| @@ -630,6 +630,7 @@ struct drm_gem_open { · 629 unmodified lines | |||
| 630 | */ | 630 | */ |
| 631 | #define DRM_CAP_CURSOR_WIDTH 0x8 | 631 | #define DRM_CAP_CURSOR_WIDTH 0x8 |
| 632 | #define DRM_CAP_CURSOR_HEIGHT 0x9 | 632 | #define DRM_CAP_CURSOR_HEIGHT 0x9 |
| 633 | #define DRM_CAP_ADDFB2_MODIFIERS 0x10 | ||
| 633 | 634 | ||
| 634 | /** DRM_IOCTL_GET_CAP ioctl argument type */ | 635 | /** DRM_IOCTL_GET_CAP ioctl argument type */ |
| 635 | struct drm_get_cap { | 636 | struct drm_get_cap { |
| @@ -129,4 +129,67 @@ · 128 unmodified lines | |||
| 129 | #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ | 129 | #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ |
| 130 | #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ | 130 | #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ |
| 131 | 131 | ||
| 132 | |||
| 133 | /* | ||
| 134 | * Format Modifiers: | ||
| 135 | * | ||
| 136 | * Format modifiers describe, typically, a re-ordering or modification | ||
| 137 | * of the data in a plane of an FB. This can be used to express tiled/ | ||
| 138 | * swizzled formats, or compression, or a combination of the two. | ||
| 139 | * | ||
| 140 | * The upper 8 bits of the format modifier are a vendor-id as assigned | ||
| 141 | * below. The lower 56 bits are assigned as vendor sees fit. | ||
| 142 | */ | ||
| 143 | |||
| 144 | /* Vendor Ids: */ | ||
| 145 | #define DRM_FORMAT_MOD_NONE 0 | ||
| 146 | #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 | ||
| 147 | #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 | ||
| 148 | #define DRM_FORMAT_MOD_VENDOR_NV 0x03 | ||
| 149 | #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 | ||
| 150 | #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 | ||
| 151 | /* add more to the end as needed */ | ||
| 152 | |||
| 153 | #define fourcc_mod_code(vendor, val) \ | ||
| 154 | ((((u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffL)) | ||
| 155 | |||
| 156 | /* | ||
| 157 | * Format Modifier tokens: | ||
| 158 | * | ||
| 159 | * When adding a new token please document the layout with a code comment, | ||
| 160 | * similar to the fourcc codes above. drm_fourcc.h is considered the | ||
| 161 | * authoritative source for all of these. | ||
| 162 | */ | ||
| 163 | |||
| 164 | /* Intel framebuffer modifiers */ | ||
| 165 | |||
| 166 | /* | ||
| 167 | * Intel X-tiling layout | ||
| 168 | * | ||
| 169 | * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) | ||
| 170 | * in row-major layout. Within the tile bytes are laid out row-major, with | ||
| 171 | * a platform-dependent stride. On top of that the memory can apply | ||
| 172 | * platform-depending swizzling of some higher address bits into bit6. | ||
| 173 | * | ||
| 174 | * This format is highly platforms specific and not useful for cross-driver | ||
| 175 | * sharing. It exists since on a given platform it does uniquely identify the | ||
| 176 | * layout in a simple way for i915-specific userspace. | ||
| 177 | */ | ||
| 178 | #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) | ||
| 179 | |||
| 180 | /* | ||
| 181 | * Intel Y-tiling layout | ||
| 182 | * | ||
| 183 | * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) | ||
| 184 | * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) | ||
| 185 | * chunks column-major, with a platform-dependent height. On top of that the | ||
| 186 | * memory can apply platform-depending swizzling of some higher address bits | ||
| 187 | * into bit6. | ||
| 188 | * | ||
| 189 | * This format is highly platforms specific and not useful for cross-driver | ||
| 190 | * sharing. It exists since on a given platform it does uniquely identify the | ||
| 191 | * layout in a simple way for i915-specific userspace. | ||
| 192 | */ | ||
| 193 | #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) | ||
| 194 | |||
| 132 | #endif /* DRM_FOURCC_H */ | 195 | #endif /* DRM_FOURCC_H */ |
| @@ -336,6 +336,7 @@ struct drm_mode_fb_cmd { · 335 unmodified lines | |||
| 336 | }; | 336 | }; |
| 337 | 337 | ||
| 338 | #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ | 338 | #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ |
| 339 | #define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ | ||
| 339 | 340 | ||
| 340 | struct drm_mode_fb_cmd2 { | 341 | struct drm_mode_fb_cmd2 { |
| 341 | __u32 fb_id; | 342 | __u32 fb_id; |
| @@ -356,10 +357,18 @@ struct drm_mode_fb_cmd2 { · 14 unmodified lines | |||
| 356 | * So it would consist of Y as offsets[0] and UV as | 357 | * So it would consist of Y as offsets[0] and UV as |
| 357 | * offsets[1]. Note that offsets[0] will generally | 358 | * offsets[1]. Note that offsets[0] will generally |
| 358 | * be 0 (but this is not required). | 359 | * be 0 (but this is not required). |
| 360 | * | ||
| 361 | * To accommodate tiled, compressed, etc formats, a per-plane | ||
| 362 | * modifier can be specified. The default value of zero | ||
| 363 | * indicates "native" format as specified by the fourcc. | ||
| 364 | * Vendor specific modifier token. This allows, for example, | ||
| 365 | * different tiling/swizzling pattern on different planes. | ||
| 366 | * See discussion above of DRM_FORMAT_MOD_xxx. | ||
| 359 | */ | 367 | */ |
| 360 | __u32 handles[4]; | 368 | __u32 handles[4]; |
| 361 | __u32 pitches[4]; /* pitch for each plane */ | 369 | __u32 pitches[4]; /* pitch for each plane */ |
| 362 | __u32 offsets[4]; /* offset of each plane */ | 370 | __u32 offsets[4]; /* offset of each plane */ |
| 371 | __u64 modifier[4]; /* ie, tiling, compressed (per plane) */ | ||
| 363 | }; | 372 | }; |
| 364 | 373 | ||
| 365 | #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 | 374 | #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 |