History

ARM: OMAP2+: Drop sdma interrupt handling for mach-omap2

All device tree probing omap SoCs only have device drivers that are using Linux dmaengine API with the IRQENABLE_L1 interrupts. Only omap1 is still using old legacy dma. This means we can remove the legacy sdma interrupt handling for IRQENABLE_L0, and only rely on the dmaengine driver using IRQENABLE_L1. The legacy code still allocates the channels, but that will be deal with in the following patches.

Tony Lindgren committed 6 years ago

Commit 755cbfd1 parent 28b5afc3 files · +8 −244Browse files

Unified · Split

3 files
  1. arch/arm/mach-omap2/dma.c +0 −3
  2. arch/arm/plat-omap/dma.c +8 −237
  3. include/linux/omap-dma.h +0 −4
arch/arm/mach-omap2/dma.c+0−3
@@ -272,9 +272,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) · 271 unmodified lines
272272 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
273273 d->dev_caps |= HS_CHANNELS_RESERVED;
274274
275− if (platform_get_irq_byname(pdev, "0") < 0)
276− d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
277−
278275 /* Check the capabilities register for descriptor loading feature */
279276 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
280277 dma_common_ch_end = CCDN;
arch/arm/plat-omap/dma.c+8−237
@@ -88,22 +88,6 @@ struct dma_link_info { · 87 unmodified lines
8888
8989 };
9090
91−static struct dma_link_info *dma_linked_lch;
92−
93−#ifndef CONFIG_ARCH_OMAP1
94−
95−/* Chain handling macros */
96−#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
97− (0 == dma_linked_lch[chain_id].q_count)
98−#define __OMAP_DMA_CHAIN_INCQ(end) \
99− ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
100−#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
101− do { \
102− __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
103− dma_linked_lch[chain_id].q_count--; \
104− } while (0)
105−#endif
106−
10791 static int dma_lch_count;
10892 static int dma_chan_count;
10993 static int omap_dma_reserve_channels;
@@ -469,12 +453,6 @@ static inline void enable_lnk(int lch) · 359 unmodified lines
469453 if (dma_chan[lch].next_lch != -1)
470454 l = dma_chan[lch].next_lch | (1 << 15);
471455
472−#ifndef CONFIG_ARCH_OMAP1
473− if (dma_omap2plus())
474− if (dma_chan[lch].next_linked_ch != -1)
475− l = dma_chan[lch].next_linked_ch | (1 << 15);
476−#endif
477−
478456 p->dma_write(l, CLNK_CTRL, lch);
479457 }
480458
@@ -501,42 +479,6 @@ static inline void disable_lnk(int lch) · 20 unmodified lines
501479 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
502480 }
503481
504−static inline void omap2_enable_irq_lch(int lch)
505−{
506− u32 val;
507− unsigned long flags;
508−
509− if (dma_omap1())
510− return;
511−
512− spin_lock_irqsave(&dma_chan_lock, flags);
513− /* clear IRQ STATUS */
514− p->dma_write(1 << lch, IRQSTATUS_L0, lch);
515− /* Enable interrupt */
516− val = p->dma_read(IRQENABLE_L0, lch);
517− val |= 1 << lch;
518− p->dma_write(val, IRQENABLE_L0, lch);
519− spin_unlock_irqrestore(&dma_chan_lock, flags);
520−}
521−
522−static inline void omap2_disable_irq_lch(int lch)
523−{
524− u32 val;
525− unsigned long flags;
526−
527− if (dma_omap1())
528− return;
529−
530− spin_lock_irqsave(&dma_chan_lock, flags);
531− /* Disable interrupt */
532− val = p->dma_read(IRQENABLE_L0, lch);
533− val &= ~(1 << lch);
534− p->dma_write(val, IRQENABLE_L0, lch);
535− /* clear IRQ STATUS */
536− p->dma_write(1 << lch, IRQSTATUS_L0, lch);
537− spin_unlock_irqrestore(&dma_chan_lock, flags);
538−}
539−
540482 int omap_request_dma(int dev_id, const char *dev_name,
541483 void (*callback)(int lch, u16 ch_status, void *data),
542484 void *data, int *dma_ch_out)
@@ -565,9 +507,6 @@ int omap_request_dma(int dev_id, const char *dev_name, · 22 unmodified lines
565507 if (p->clear_lch_regs)
566508 p->clear_lch_regs(free_ch);
567509
568− if (dma_omap2plus())
569− omap_clear_dma(free_ch);
570−
571510 spin_unlock_irqrestore(&dma_chan_lock, flags);
572511
573512 chan->dev_name = dev_name;
@@ -575,20 +514,10 @@ int omap_request_dma(int dev_id, const char *dev_name, · 1 unmodified line
575514 chan->data = data;
576515 chan->flags = 0;
577516
578−#ifndef CONFIG_ARCH_OMAP1
579− if (dma_omap2plus()) {
580− chan->chain_id = -1;
581− chan->next_linked_ch = -1;
582− }
583−#endif
584−
585517 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
586518
587519 if (dma_omap1())
588520 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
589− else if (dma_omap2plus())
590− chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
591− OMAP2_DMA_TRANS_ERR_IRQ;
592521
593522 if (dma_omap16xx()) {
594523 /* If the sync device is set, configure it dynamically. */
@@ -605,11 +534,6 @@ int omap_request_dma(int dev_id, const char *dev_name, · 10 unmodified lines
605534 p->dma_write(dev_id, CCR, free_ch);
606535 }
607536
608− if (dma_omap2plus()) {
609− omap_enable_channel_irq(free_ch);
610− omap2_enable_irq_lch(free_ch);
611− }
612−
613537 *dma_ch_out = free_ch;
614538
615539 return 0;
@@ -626,20 +550,12 @@ void omap_free_dma(int lch) · 10 unmodified lines
626550 return;
627551 }
628552
629− /* Disable interrupt for logical channel */
630− if (dma_omap2plus())
631− omap2_disable_irq_lch(lch);
632−
633553 /* Disable all DMA interrupts for the channel. */
634554 omap_disable_channel_irq(lch);
635555
636556 /* Make sure the DMA transfer is stopped. */
637557 p->dma_write(0, CCR, lch);
638558
639− /* Clear registers */
640− if (dma_omap2plus())
641− omap_clear_dma(lch);
642−
643559 spin_lock_irqsave(&dma_chan_lock, flags);
644560 dma_chan[lch].dev_id = -1;
645561 dma_chan[lch].next_lch = -1;
@@ -989,109 +905,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) · 343 unmodified lines
989905 #define omap1_dma_irq_handler NULL
990906 #endif
991907
992−#ifdef CONFIG_ARCH_OMAP2PLUS
993−
994−static int omap2_dma_handle_ch(int ch)
995−{
996− u32 status = p->dma_read(CSR, ch);
997−
998− if (!status) {
999− if (printk_ratelimit())
1000− pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1001− p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1002− return 0;
1003− }
1004− if (unlikely(dma_chan[ch].dev_id == -1)) {
1005− if (printk_ratelimit())
1006− pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1007− status, ch);
1008− return 0;
1009− }
1010− if (unlikely(status & OMAP_DMA_DROP_IRQ))
1011− pr_info("DMA synchronization event drop occurred with device %d\n",
1012− dma_chan[ch].dev_id);
1013− if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1014− printk(KERN_INFO "DMA transaction error with device %d\n",
1015− dma_chan[ch].dev_id);
1016− if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1017− u32 ccr;
1018−
1019− ccr = p->dma_read(CCR, ch);
1020− ccr &= ~OMAP_DMA_CCR_EN;
1021− p->dma_write(ccr, CCR, ch);
1022− dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1023− }
1024− }
1025− if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1026− printk(KERN_INFO "DMA secure error with device %d\n",
1027− dma_chan[ch].dev_id);
1028− if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1029− printk(KERN_INFO "DMA misaligned error with device %d\n",
1030− dma_chan[ch].dev_id);
1031−
1032− p->dma_write(status, CSR, ch);
1033− p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1034− /* read back the register to flush the write */
1035− p->dma_read(IRQSTATUS_L0, ch);
1036−
1037− /* If the ch is not chained then chain_id will be -1 */
1038− if (dma_chan[ch].chain_id != -1) {
1039− int chain_id = dma_chan[ch].chain_id;
1040− dma_chan[ch].state = DMA_CH_NOTSTARTED;
1041− if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1042− dma_chan[dma_chan[ch].next_linked_ch].state =
1043− DMA_CH_STARTED;
1044− if (dma_linked_lch[chain_id].chain_mode ==
1045− OMAP_DMA_DYNAMIC_CHAIN)
1046− disable_lnk(ch);
1047−
1048− if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1049− OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1050−
1051− status = p->dma_read(CSR, ch);
1052− p->dma_write(status, CSR, ch);
1053− }
1054−
1055− if (likely(dma_chan[ch].callback != NULL))
1056− dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1057−
1058− return 0;
1059−}
1060−
1061−/* STATUS register count is from 1-32 while our is 0-31 */
1062−static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1063−{
1064− u32 val, enable_reg;
1065− int i;
1066−
1067− val = p->dma_read(IRQSTATUS_L0, 0);
1068− if (val == 0) {
1069− if (printk_ratelimit())
1070− printk(KERN_WARNING "Spurious DMA IRQ\n");
1071− return IRQ_HANDLED;
1072− }
1073− enable_reg = p->dma_read(IRQENABLE_L0, 0);
1074− val &= enable_reg; /* Dispatch only relevant interrupts */
1075− for (i = 0; i < dma_lch_count && val != 0; i++) {
1076− if (val & 1)
1077− omap2_dma_handle_ch(i);
1078− val >>= 1;
1079− }
1080−
1081− return IRQ_HANDLED;
1082−}
1083−
1084−static struct irqaction omap24xx_dma_irq = {
1085− .name = "DMA",
1086− .handler = omap2_dma_irq_handler,
1087−};
1088−
1089−#else
1090−static struct irqaction omap24xx_dma_irq;
1091−#endif
1092−
1093−/*----------------------------------------------------------------------------*/
1094−
1095908 /*
1096909 * Note that we are currently using only IRQENABLE_L0 and L1.
1097910 * As the DSP may be using IRQENABLE_L2 and L3, let's not
@@ -1139,7 +952,6 @@ static int omap_system_dma_probe(struct platform_device *pdev) · 41 unmodified lines
1139952 int ch, ret = 0;
1140953 int dma_irq;
1141954 char irq_name[4];
1142− int irq_rel;
1143955
1144956 p = pdev->dev.platform_data;
1145957 if (!p) {
@@ -1165,21 +977,9 @@ static int omap_system_dma_probe(struct platform_device *pdev) · 19 unmodified lines
1165977 if (!dma_chan)
1166978 return -ENOMEM;
1167979
1168− if (dma_omap2plus()) {
1169− dma_linked_lch = kcalloc(dma_lch_count,
1170− sizeof(*dma_linked_lch),
1171− GFP_KERNEL);
1172− if (!dma_linked_lch) {
1173− ret = -ENOMEM;
1174− goto exit_dma_lch_fail;
1175− }
1176− }
1177−
1178980 spin_lock_init(&dma_chan_lock);
1179981 for (ch = 0; ch < dma_chan_count; ch++) {
1180982 omap_clear_dma(ch);
1181− if (dma_omap2plus())
1182− omap2_disable_irq_lch(ch);
1183983
1184984 dma_chan[ch].dev_id = -1;
1185985 dma_chan[ch].next_lch = -1;
@@ -1216,22 +1016,6 @@ static int omap_system_dma_probe(struct platform_device *pdev) · 30 unmodified lines
12161016 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
12171017 DMA_DEFAULT_FIFO_DEPTH, 0);
12181018
1219− if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
1220− strcpy(irq_name, "0");
1221− dma_irq = platform_get_irq_byname(pdev, irq_name);
1222− if (dma_irq < 0) {
1223− dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
1224− ret = dma_irq;
1225− goto exit_dma_lch_fail;
1226− }
1227− ret = setup_irq(dma_irq, &omap24xx_dma_irq);
1228− if (ret) {
1229− dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
1230− dma_irq, ret);
1231− goto exit_dma_lch_fail;
1232− }
1233− }
1234−
12351019 /* reserve dma channels 0 and 1 in high security devices on 34xx */
12361020 if (d->dev_caps & HS_CHANNELS_RESERVED) {
12371021 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
@@ -1242,34 +1026,21 @@ static int omap_system_dma_probe(struct platform_device *pdev) · 4 unmodified lines
12421026 return 0;
12431027
12441028 exit_dma_irq_fail:
1245− dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
1246− dma_irq, ret);
1247− for (irq_rel = 0; irq_rel < ch; irq_rel++) {
1248− dma_irq = platform_get_irq(pdev, irq_rel);
1249− free_irq(dma_irq, (void *)(irq_rel + 1));
1250− }
1251−
1252−exit_dma_lch_fail:
12531029 return ret;
12541030 }
12551031
12561032 static int omap_system_dma_remove(struct platform_device *pdev)
12571033 {
1258− int dma_irq;
1034+ int dma_irq, irq_rel = 0;
12591035
1260− if (dma_omap2plus()) {
1261− char irq_name[4];
1262− strcpy(irq_name, "0");
1263− dma_irq = platform_get_irq_byname(pdev, irq_name);
1264− if (dma_irq >= 0)
1265− remove_irq(dma_irq, &omap24xx_dma_irq);
1266− } else {
1267− int irq_rel = 0;
1268− for ( ; irq_rel < dma_chan_count; irq_rel++) {
1269− dma_irq = platform_get_irq(pdev, irq_rel);
1270− free_irq(dma_irq, (void *)(irq_rel + 1));
1271− }
1036+ if (dma_omap2plus())
1037+ return 0;
1038+
1039+ for ( ; irq_rel < dma_chan_count; irq_rel++) {
1040+ dma_irq = platform_get_irq(pdev, irq_rel);
1041+ free_irq(dma_irq, (void *)(irq_rel + 1));
12721042 }
1043+
12731044 return 0;
12741045 }
12751046
include/linux/omap-dma.h+0−4
@@ -129,7 +129,6 @@ · 128 unmodified lines
129129 #define IS_WORD_16 BIT(0xd)
130130 #define ENABLE_16XX_MODE BIT(0xe)
131131 #define HS_CHANNELS_RESERVED BIT(0xf)
132−#define DMA_ENGINE_HANDLE_IRQ BIT(0x10)
133132
134133 /* Defines for DMA Capabilities */
135134 #define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
@@ -239,9 +238,6 @@ struct omap_dma_lch { · 103 unmodified lines
239238 void (*callback)(int lch, u16 ch_status, void *data);
240239 void *data;
241240 long flags;
242− /* required for Dynamic chaining */
243− int prev_linked_ch;
244− int next_linked_ch;
245241 int state;
246242 int chain_id;
247243 int status;