Merge tag 'drm-next-2025-04-05' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie: "Weekly fixes, mostly from the end of last week, this week was very quiet, maybe you scared everyone away. It's mostly amdgpu, and xe, with some i915, adp and bridge bits, since I think this is overly quiet I'd expect rc2 to be a bit more lively. bridge: - tda998x: Select CONFIG_DRM_KMS_HELPER amdgpu: - Guard against potential division by 0 in fan code - Zero RPM support for SMU 14.0.2 - Properly handle SI and CIK support being disabled - PSR fixes - DML2 fixes - DP Link training fix - Vblank fixes - RAS fixes - Partitioning fix - SDMA fix - SMU 13.0.x fixes - Rom fetching fix - MES fixes - Queue reset fix xe: - Fix NULL pointer dereference on error path - Add missing HW workaround for BMG - Fix survivability mode not triggering - Fix build warning when DRM_FBDEV_EMULATION is not set i915: - Bounds check for scalers in DSC prefill latency computation - Fix build by adding a missing include adp: - Fix error handling in plane setup" # -----BEGIN PGP SIGNATURE----- * tag 'drm-next-2025-04-05' of https://gitlab.freedesktop.org/drm/kernel: (34 commits) drm/i2c: tda998x: select CONFIG_DRM_KMS_HELPER drm/amdgpu/gfx12: fix num_mec drm/amdgpu/gfx11: fix num_mec drm/amd/pm: Add gpu_metrics_v1_8 drm/amdgpu: Prefer shadow rom when available drm/amd/pm: Update smu metrics table for smu_v13_0_6 drm/amd/pm: Remove host limit metrics support Remove unnecessary firmware version check for gc v9_4_2 drm/amdgpu: stop unmapping MQD for kernel queues v3 Revert "drm/amdgpu/sdma_v4_4_2: update VM flush implementation for SDMA" drm/amdgpu: Parse all deferred errors with UMC aca handle drm/amdgpu: Update ta ras block drm/amdgpu: Add NPS2 to DPX compatible mode drm/amdgpu: Use correct gfx deferred error count drm/amd/display: Actually do immediate vblank disable drm/amd/display: prevent hang on link training fail Revert "drm/amd/display: dml2 soc dscclk use DPM table clk setting" drm/amd/display: Increase vblank offdelay for PSR panels drm/amd: Handle being compiled without SI or CIK support better drm/amd/pm: Add zero RPM enabled OD setting support for SMU14.0.2 ...

Linus Torvalds committed 1 year ago

Commit 758e4c82 parents 56f9445 e2cb28e52 files · +539 −703Browse files

Unified · Split

52 files

drivers/gpu/drm/adp/adp_drv.c +2 −2
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +4 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h +0 −8
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +27 −7
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +24 −20
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +1 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +7 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +8 −50
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +1 −1
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +2 −1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +11 −77
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +11 −79
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +16 −88
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +5 −40
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +8 −50
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +14 −54
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +1 −1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c +1 −1
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +15 −64
drivers/gpu/drm/amd/amdgpu/ta_ras_if.h +3 −0
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c +2 −1
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +1 −1
drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h +0 −70
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +35 −8
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c +1 −1
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +5 −1
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +5 −2
drivers/gpu/drm/amd/include/kgd_pp_interface.h +114 −0
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c +2 −2
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c +2 −2
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c +1 −1
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h +5 −2
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +3 −0
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +1 −1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +0 −15
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +54 −1
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +3 −0
drivers/gpu/drm/bridge/Kconfig +7 −6
drivers/gpu/drm/i915/display/intel_fbdev.h +2 −0
drivers/gpu/drm/i915/display/skl_watermark.c +4 −1
drivers/gpu/drm/xe/Kconfig +1 −1
drivers/gpu/drm/xe/regs/xe_engine_regs.h +4 −0
drivers/gpu/drm/xe/xe_device.c +15 −2
drivers/gpu/drm/xe/xe_eu_stall.c +1 −7
drivers/gpu/drm/xe/xe_gt_clock.c +38 −16
drivers/gpu/drm/xe/xe_gt_types.h +2 −0
drivers/gpu/drm/xe/xe_hw_engine.c +33 −0
drivers/gpu/drm/xe/xe_pci.c +7 −9
drivers/gpu/drm/xe/xe_survivability_mode.c +22 −9
drivers/gpu/drm/xe/xe_survivability_mode.h +0 −1
drivers/gpu/drm/xe/xe_wa.c +6 −0
drivers/gpu/drm/xe/xe_wa_oob.rules +2 −0

drivers/gpu/drm/adp/adp_drv.c+2−2

@@ -232,9 +232,9 @@ static struct drm_plane adp_plane_new(struct adp_drv_private adp) · 231 unmodified lines
232	232	ALL_CRTCS, &adp_plane_funcs,
233	233	plane_formats, ARRAY_SIZE(plane_formats),
234	234	NULL, DRM_PLANE_TYPE_PRIMARY, "plane");
235		− if (!plane) {
	235	+ if (IS_ERR(plane)) {
236	236	drm_err(drm, "failed to allocate plane");
237		− return ERR_PTR(-ENOMEM);
	237	+ return plane;
238	238	}
239	239
240	240	drm_plane_helper_add(plane, &adp_plane_helper_funcs);

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c+4−0

@@ -195,6 +195,10 @@ static bool aca_bank_is_valid(struct aca_handle handle, struct aca_bank bank, · 194 unmodified lines
195	195	{
196	196	const struct aca_bank_ops *bank_ops = handle->bank_ops;
197	197
	198	+ /* Parse all deferred errors with UMC aca handle */
	199	+ if (ACA_BANK_ERR_IS_DEFFERED(bank))
	200	+ return handle->hwip == ACA_HWIP_TYPE_UMC;
	201	+
198	202	if (!aca_bank_hwip_is_matched(bank, handle->hwip))
199	203	return false;
200	204

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h+0−8

@@ -80,14 +80,6 @@ struct ras_query_context; · 79 unmodified lines
80	80	(ACA_REG__STATUS__POISON((bank)->regs[ACA_REG_IDX_STATUS]) \|\| \
81	81	ACA_REG__STATUS__DEFERRED((bank)->regs[ACA_REG_IDX_STATUS]))
82	82
83		−#define ACA_BANK_ERR_CE_DE_DECODE(bank) \
84		− (ACA_BANK_ERR_IS_DEFFERED(bank) ? ACA_ERROR_TYPE_DEFERRED : \
85		− ACA_ERROR_TYPE_CE)
86		−
87		−#define ACA_BANK_ERR_UE_DE_DECODE(bank) \
88		− (ACA_BANK_ERR_IS_DEFFERED(bank) ? ACA_ERROR_TYPE_DEFERRED : \
89		− ACA_ERROR_TYPE_UE)
90		−
91	83	enum aca_reg_idx {
92	84	ACA_REG_IDX_CTL = 0,
93	85	ACA_REG_IDX_STATUS = 1,

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c+27−7

@@ -447,6 +447,13 @@ success: · 446 unmodified lines
447	447	return true;
448	448	}
449	449
	450	+static bool amdgpu_prefer_rom_resource(struct amdgpu_device *adev)
	451	+{
	452	+ struct resource *res = &adev->pdev->resource[PCI_ROM_RESOURCE];
	453	+
	454	+ return (res->flags & IORESOURCE_ROM_SHADOW);
	455	+}
	456	+
450	457	static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev)
451	458	{
452	459	if (amdgpu_atrm_get_bios(adev)) {
@@ -465,14 +472,27 @@ static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev) · 12 unmodified lines
465	472	goto success;
466	473	}
467	474
468		− if (amdgpu_read_platform_bios(adev)) {
469		− dev_info(adev->dev, "Fetched VBIOS from platform\n");
470		− goto success;
471		− }
	475	+ if (amdgpu_prefer_rom_resource(adev)) {
	476	+ if (amdgpu_read_bios(adev)) {
	477	+ dev_info(adev->dev, "Fetched VBIOS from ROM BAR\n");
	478	+ goto success;
	479	+ }
472	480
473		− if (amdgpu_read_bios(adev)) {
474		− dev_info(adev->dev, "Fetched VBIOS from ROM BAR\n");
475		− goto success;
	481	+ if (amdgpu_read_platform_bios(adev)) {
	482	+ dev_info(adev->dev, "Fetched VBIOS from platform\n");
	483	+ goto success;
	484	+ }
	485	+
	486	+ } else {
	487	+ if (amdgpu_read_platform_bios(adev)) {
	488	+ dev_info(adev->dev, "Fetched VBIOS from platform\n");
	489	+ goto success;
	490	+ }
	491	+
	492	+ if (amdgpu_read_bios(adev)) {
	493	+ dev_info(adev->dev, "Fetched VBIOS from ROM BAR\n");
	494	+ goto success;
	495	+ }
476	496	}
477	497
478	498	if (amdgpu_read_bios_from_rom(adev)) {

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+24−20

@@ -1809,7 +1809,6 @@ static const u16 amdgpu_unsupported_pciidlist[] = { · 1808 unmodified lines
1809	1809	};
1810	1810
1811	1811	static const struct pci_device_id pciidlist[] = {
1812		−#ifdef CONFIG_DRM_AMDGPU_SI
1813	1812	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1814	1813	{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1815	1814	{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
@@ -1882,8 +1881,6 @@ static const struct pci_device_id pciidlist[] = { · 66 unmodified lines
1882	1881	{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN\|AMD_IS_MOBILITY},
1883	1882	{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN\|AMD_IS_MOBILITY},
1884	1883	{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN\|AMD_IS_MOBILITY},
1885		−#endif
1886		−#ifdef CONFIG_DRM_AMDGPU_CIK
1887	1884	/* Kaveri */
1888	1885	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI\|AMD_IS_MOBILITY\|AMD_IS_APU},
1889	1886	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI\|AMD_IS_APU},
@@ -1966,7 +1963,6 @@ static const struct pci_device_id pciidlist[] = { · 76 unmodified lines
1966	1963	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS\|AMD_IS_MOBILITY\|AMD_IS_APU},
1967	1964	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS\|AMD_IS_MOBILITY\|AMD_IS_APU},
1968	1965	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS\|AMD_IS_MOBILITY\|AMD_IS_APU},
1969		−#endif
1970	1966	/* topaz */
1971	1967	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1972	1968	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
@@ -2313,14 +2309,14 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, · 340 unmodified lines
2313	2309	return -ENOTSUPP;
2314	2310	}
2315	2311
	2312	+ switch (flags & AMD_ASIC_MASK) {
	2313	+ case CHIP_TAHITI:
	2314	+ case CHIP_PITCAIRN:
	2315	+ case CHIP_VERDE:
	2316	+ case CHIP_OLAND:
	2317	+ case CHIP_HAINAN:
2316	2318	#ifdef CONFIG_DRM_AMDGPU_SI
2317		− if (!amdgpu_si_support) {
2318		− switch (flags & AMD_ASIC_MASK) {
2319		− case CHIP_TAHITI:
2320		− case CHIP_PITCAIRN:
2321		− case CHIP_VERDE:
2322		− case CHIP_OLAND:
2323		− case CHIP_HAINAN:
	2319	+ if (!amdgpu_si_support) {
2324	2320	dev_info(&pdev->dev,
2325	2321	"SI support provided by radeon.\n");
2326	2322	dev_info(&pdev->dev,
@@ -2328,16 +2324,18 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, · 1 unmodified line
2328	2324	);
2329	2325	return -ENODEV;
2330	2326	}
2331		− }
	2327	+ break;
	2328	+#else
	2329	+ dev_info(&pdev->dev, "amdgpu is built without SI support.\n");
	2330	+ return -ENODEV;
2332	2331	#endif
	2332	+ case CHIP_KAVERI:
	2333	+ case CHIP_BONAIRE:
	2334	+ case CHIP_HAWAII:
	2335	+ case CHIP_KABINI:
	2336	+ case CHIP_MULLINS:
2333	2337	#ifdef CONFIG_DRM_AMDGPU_CIK
2334		− if (!amdgpu_cik_support) {
2335		− switch (flags & AMD_ASIC_MASK) {
2336		− case CHIP_KAVERI:
2337		− case CHIP_BONAIRE:
2338		− case CHIP_HAWAII:
2339		− case CHIP_KABINI:
2340		− case CHIP_MULLINS:
	2338	+ if (!amdgpu_cik_support) {
2341	2339	dev_info(&pdev->dev,
2342	2340	"CIK support provided by radeon.\n");
2343	2341	dev_info(&pdev->dev,
@@ -2345,8 +2343,14 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, · 1 unmodified line
2345	2343	);
2346	2344	return -ENODEV;
2347	2345	}
2348		− }
	2346	+ break;
	2347	+#else
	2348	+ dev_info(&pdev->dev, "amdgpu is built without CIK support.\n");
	2349	+ return -ENODEV;
2349	2350	#endif
	2351	+ default:
	2352	+ break;
	2353	+ }
2350	2354
2351	2355	adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2352	2356	if (IS_ERR(adev))

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c+1−0

@@ -77,6 +77,7 @@ const char *ras_block_string[] = { · 76 unmodified lines
77	77	"jpeg",
78	78	"ih",
79	79	"mpio",
	80	+ "mmsch",
80	81	};
81	82
82	83	const char *ras_mca_block_string[] = {

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h+7−0

@@ -98,6 +98,7 @@ enum amdgpu_ras_block { · 97 unmodified lines
98	98	AMDGPU_RAS_BLOCK__JPEG,
99	99	AMDGPU_RAS_BLOCK__IH,
100	100	AMDGPU_RAS_BLOCK__MPIO,
	101	+ AMDGPU_RAS_BLOCK__MMSCH,
101	102
102	103	AMDGPU_RAS_BLOCK__LAST,
103	104	AMDGPU_RAS_BLOCK__ANY = -1
@@ -795,6 +796,12 @@ amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { · 691 unmodified lines
795	796	return TA_RAS_BLOCK__VCN;
796	797	case AMDGPU_RAS_BLOCK__JPEG:
797	798	return TA_RAS_BLOCK__JPEG;
	799	+ case AMDGPU_RAS_BLOCK__IH:
	800	+ return TA_RAS_BLOCK__IH;
	801	+ case AMDGPU_RAS_BLOCK__MPIO:
	802	+ return TA_RAS_BLOCK__MPIO;
	803	+ case AMDGPU_RAS_BLOCK__MMSCH:
	804	+ return TA_RAS_BLOCK__MMSCH;
798	805	default:
799	806	WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
800	807	return TA_RAS_BLOCK__UMC;

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c+8−50

@@ -608,59 +608,17 @@ static ssize_t amdgpu_debugfs_mqd_read(struct file f, char __user buf, · 607 unmodified lines
608	608	size_t size, loff_t *pos)
609	609	{
610	610	struct amdgpu_ring *ring = file_inode(f)->i_private;
611		− volatile u32 *mqd;
612		− u32 *kbuf;
613		− int r, i;
614		− uint32_t value, result;
	611	+ ssize_t bytes = min_t(ssize_t, ring->mqd_size - *pos, size);
	612	+ void from = ((u8 )ring->mqd_ptr) + *pos;
615	613
616		− if (*pos & 3 \|\| size & 3)
617		− return -EINVAL;
618		−
619		− kbuf = kmalloc(ring->mqd_size, GFP_KERNEL);
620		− if (!kbuf)
621		− return -ENOMEM;
622		−
623		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
624		− if (unlikely(r != 0))
625		− goto err_free;
626		−
627		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&mqd);
628		− if (r)
629		− goto err_unreserve;
630		−
631		− /*
632		− * Copy to local buffer to avoid put_user(), which might fault
633		− * and acquire mmap_sem, under reservation_ww_class_mutex.
634		− */
635		− for (i = 0; i < ring->mqd_size/sizeof(u32); i++)
636		− kbuf[i] = mqd[i];
	614	+ if (*pos > ring->mqd_size)
	615	+ return 0;
637	616
638		− amdgpu_bo_kunmap(ring->mqd_obj);
639		− amdgpu_bo_unreserve(ring->mqd_obj);
	617	+ if (copy_to_user(buf, from, bytes))
	618	+ return -EFAULT;
640	619
641		− result = 0;
642		− while (size) {
643		− if (*pos >= ring->mqd_size)
644		− break;
645		−
646		− value = kbuf[*pos/4];
647		− r = put_user(value, (uint32_t *)buf);
648		− if (r)
649		− goto err_free;
650		− buf += 4;
651		− result += 4;
652		− size -= 4;
653		− *pos += 4;
654		− }
655		−
656		− kfree(kbuf);
657		− return result;
658		−
659		−err_unreserve:
660		− amdgpu_bo_unreserve(ring->mqd_obj);
661		−err_free:
662		− kfree(kbuf);
663		− return r;
	620	+ *pos += bytes;
	621	+ return bytes;
664	622	}
665	623
666	624	static const struct file_operations amdgpu_debugfs_mqd_fops = {

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c+1−1

@@ -1172,7 +1172,7 @@ static int xgmi_v6_4_0_aca_bank_parser(struct aca_handle *handle, struct aca_ban · 1171 unmodified lines
1172	1172	break;
1173	1173	case ACA_SMU_TYPE_CE:
1174	1174	count = ext_error_code == 6 ? count : 0ULL;
1175		− bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank);
	1175	+ bank->aca_err_type = ACA_ERROR_TYPE_CE;
1176	1176	ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, count);
1177	1177	break;
1178	1178	default:

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c+2−1

@@ -473,7 +473,8 @@ static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, · 472 unmodified lines
473	473	break;
474	474	case AMDGPU_DPX_PARTITION_MODE:
475	475	num_xcp = 2;
476		− nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE);
	476	+ nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) \|
	477	+ BIT(AMDGPU_NPS2_PARTITION_MODE);
477	478	break;
478	479	case AMDGPU_TPX_PARTITION_MODE:
479	480	num_xcp = 3;

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+11−77

@@ -6851,22 +6851,9 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) · 6850 unmodified lines
6851	6851	static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6852	6852	{
6853	6853	int r, i;
6854		− struct amdgpu_ring *ring;
6855	6854
6856	6855	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6857		− ring = &adev->gfx.gfx_ring[i];
6858		−
6859		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
6860		− if (unlikely(r != 0))
6861		− return r;
6862		−
6863		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6864		− if (!r) {
6865		− r = gfx_v10_0_kgq_init_queue(ring, false);
6866		− amdgpu_bo_kunmap(ring->mqd_obj);
6867		− ring->mqd_ptr = NULL;
6868		− }
6869		− amdgpu_bo_unreserve(ring->mqd_obj);
	6856	+ r = gfx_v10_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
6870	6857	if (r)
6871	6858	return r;
6872	6859	}
@@ -7173,55 +7160,24 @@ static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore) · 300 unmodified lines
7173	7160
7174	7161	static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7175	7162	{
7176		− struct amdgpu_ring *ring;
7177		− int r;
7178		−
7179		− ring = &adev->gfx.kiq[0].ring;
7180		−
7181		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
7182		− if (unlikely(r != 0))
7183		− return r;
7184		−
7185		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7186		− if (unlikely(r != 0)) {
7187		− amdgpu_bo_unreserve(ring->mqd_obj);
7188		− return r;
7189		− }
7190		−
7191		− gfx_v10_0_kiq_init_queue(ring);
7192		− amdgpu_bo_kunmap(ring->mqd_obj);
7193		− ring->mqd_ptr = NULL;
7194		− amdgpu_bo_unreserve(ring->mqd_obj);
	7163	+ gfx_v10_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
7195	7164	return 0;
7196	7165	}
7197	7166
7198	7167	static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7199	7168	{
7200		− struct amdgpu_ring *ring = NULL;
7201		− int r = 0, i;
	7169	+ int i, r;
7202	7170
7203	7171	gfx_v10_0_cp_compute_enable(adev, true);
7204	7172
7205	7173	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7206		− ring = &adev->gfx.compute_ring[i];
7207		−
7208		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
7209		− if (unlikely(r != 0))
7210		− goto done;
7211		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7212		− if (!r) {
7213		− r = gfx_v10_0_kcq_init_queue(ring, false);
7214		− amdgpu_bo_kunmap(ring->mqd_obj);
7215		− ring->mqd_ptr = NULL;
7216		− }
7217		− amdgpu_bo_unreserve(ring->mqd_obj);
	7174	+ r = gfx_v10_0_kcq_init_queue(&adev->gfx.compute_ring[i],
	7175	+ false);
7218	7176	if (r)
7219		− goto done;
	7177	+ return r;
7220	7178	}
7221	7179
7222		− r = amdgpu_gfx_enable_kcq(adev, 0);
7223		−done:
7224		− return r;
	7180	+ return amdgpu_gfx_enable_kcq(adev, 0);
7225	7181	}
7226	7182
7227	7183	static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
@@ -9579,20 +9535,9 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) · 2351 unmodified lines
9579	9535	if (r)
9580	9536	return r;
9581	9537
9582		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
9583		− if (unlikely(r != 0)) {
9584		− DRM_ERROR("fail to resv mqd_obj\n");
9585		− return r;
9586		− }
9587		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
9588		− if (!r) {
9589		− r = gfx_v10_0_kgq_init_queue(ring, true);
9590		− amdgpu_bo_kunmap(ring->mqd_obj);
9591		− ring->mqd_ptr = NULL;
9592		− }
9593		− amdgpu_bo_unreserve(ring->mqd_obj);
	9538	+ r = gfx_v10_0_kgq_init_queue(ring, true);
9594	9539	if (r) {
9595		− DRM_ERROR("fail to unresv mqd_obj\n");
	9540	+ DRM_ERROR("fail to init kgq\n");
9596	9541	return r;
9597	9542	}
9598	9543
@@ -9649,20 +9594,9 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, · 50 unmodified lines
9649	9594	return r;
9650	9595	}
9651	9596
9652		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
9653		− if (unlikely(r != 0)) {
9654		− dev_err(adev->dev, "fail to resv mqd_obj\n");
9655		− return r;
9656		− }
9657		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
9658		− if (!r) {
9659		− r = gfx_v10_0_kcq_init_queue(ring, true);
9660		− amdgpu_bo_kunmap(ring->mqd_obj);
9661		− ring->mqd_ptr = NULL;
9662		− }
9663		− amdgpu_bo_unreserve(ring->mqd_obj);
	9597	+ r = gfx_v10_0_kcq_init_queue(ring, true);
9664	9598	if (r) {
9665		− dev_err(adev->dev, "fail to unresv mqd_obj\n");
	9599	+ dev_err(adev->dev, "fail to init kcq\n");
9666	9600	return r;
9667	9601	}
9668	9602

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c+11−79

@@ -1581,7 +1581,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) · 1580 unmodified lines
1581	1581	adev->gfx.me.num_me = 1;
1582	1582	adev->gfx.me.num_pipe_per_me = 1;
1583	1583	adev->gfx.me.num_queue_per_pipe = 1;
1584		− adev->gfx.mec.num_mec = 2;
	1584	+ adev->gfx.mec.num_mec = 1;
1585	1585	adev->gfx.mec.num_pipe_per_mec = 4;
1586	1586	adev->gfx.mec.num_queue_per_pipe = 4;
1587	1587	break;
@@ -4115,22 +4115,9 @@ static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) · 2527 unmodified lines
4115	4115	static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
4116	4116	{
4117	4117	int r, i;
4118		− struct amdgpu_ring *ring;
4119	4118
4120	4119	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4121		− ring = &adev->gfx.gfx_ring[i];
4122		−
4123		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
4124		− if (unlikely(r != 0))
4125		− return r;
4126		−
4127		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4128		− if (!r) {
4129		− r = gfx_v11_0_kgq_init_queue(ring, false);
4130		− amdgpu_bo_kunmap(ring->mqd_obj);
4131		− ring->mqd_ptr = NULL;
4132		− }
4133		− amdgpu_bo_unreserve(ring->mqd_obj);
	4120	+ r = gfx_v11_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
4134	4121	if (r)
4135	4122	return r;
4136	4123	}
@@ -4452,57 +4439,24 @@ static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) · 315 unmodified lines
4452	4439
4453	4440	static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)
4454	4441	{
4455		− struct amdgpu_ring *ring;
4456		− int r;
4457		−
4458		− ring = &adev->gfx.kiq[0].ring;
4459		−
4460		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
4461		− if (unlikely(r != 0))
4462		− return r;
4463		−
4464		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4465		− if (unlikely(r != 0)) {
4466		− amdgpu_bo_unreserve(ring->mqd_obj);
4467		− return r;
4468		− }
4469		−
4470		− gfx_v11_0_kiq_init_queue(ring);
4471		− amdgpu_bo_kunmap(ring->mqd_obj);
4472		− ring->mqd_ptr = NULL;
4473		− amdgpu_bo_unreserve(ring->mqd_obj);
4474		− ring->sched.ready = true;
	4442	+ gfx_v11_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
4475	4443	return 0;
4476	4444	}
4477	4445
4478	4446	static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)
4479	4447	{
4480		− struct amdgpu_ring *ring = NULL;
4481		− int r = 0, i;
	4448	+ int i, r;
4482	4449
4483	4450	if (!amdgpu_async_gfx_ring)
4484	4451	gfx_v11_0_cp_compute_enable(adev, true);
4485	4452
4486	4453	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4487		− ring = &adev->gfx.compute_ring[i];
4488		−
4489		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
4490		− if (unlikely(r != 0))
4491		− goto done;
4492		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4493		− if (!r) {
4494		− r = gfx_v11_0_kcq_init_queue(ring, false);
4495		− amdgpu_bo_kunmap(ring->mqd_obj);
4496		− ring->mqd_ptr = NULL;
4497		− }
4498		− amdgpu_bo_unreserve(ring->mqd_obj);
	4454	+ r = gfx_v11_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
4499	4455	if (r)
4500		− goto done;
	4456	+ return r;
4501	4457	}
4502	4458
4503		− r = amdgpu_gfx_enable_kcq(adev, 0);
4504		−done:
4505		− return r;
	4459	+ return amdgpu_gfx_enable_kcq(adev, 0);
4506	4460	}
4507	4461
4508	4462	static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)
@@ -6667,20 +6621,9 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) · 2158 unmodified lines
6667	6621	if (r)
6668	6622	return r;
6669	6623
6670		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
6671		− if (unlikely(r != 0)) {
6672		− dev_err(adev->dev, "fail to resv mqd_obj\n");
6673		− return r;
6674		− }
6675		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6676		− if (!r) {
6677		− r = gfx_v11_0_kgq_init_queue(ring, true);
6678		− amdgpu_bo_kunmap(ring->mqd_obj);
6679		− ring->mqd_ptr = NULL;
6680		− }
6681		− amdgpu_bo_unreserve(ring->mqd_obj);
	6624	+ r = gfx_v11_0_kgq_init_queue(ring, true);
6682	6625	if (r) {
6683		− dev_err(adev->dev, "fail to unresv mqd_obj\n");
	6626	+ dev_err(adev->dev, "failed to init kgq\n");
6684	6627	return r;
6685	6628	}
6686	6629
@@ -6707,20 +6650,9 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) · 20 unmodified lines
6707	6650	return r;
6708	6651	}
6709	6652
6710		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
6711		− if (unlikely(r != 0)) {
6712		− dev_err(adev->dev, "fail to resv mqd_obj\n");
6713		− return r;
6714		− }
6715		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6716		− if (!r) {
6717		− r = gfx_v11_0_kcq_init_queue(ring, true);
6718		− amdgpu_bo_kunmap(ring->mqd_obj);
6719		− ring->mqd_ptr = NULL;
6720		− }
6721		− amdgpu_bo_unreserve(ring->mqd_obj);
	6653	+ r = gfx_v11_0_kcq_init_queue(ring, true);
6722	6654	if (r) {
6723		− dev_err(adev->dev, "fail to unresv mqd_obj\n");
	6655	+ dev_err(adev->dev, "fail to init kcq\n");
6724	6656	return r;
6725	6657	}
6726	6658	r = amdgpu_mes_map_legacy_queue(adev, ring);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c+16−88

@@ -1355,7 +1355,7 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) · 1354 unmodified lines
1355	1355	adev->gfx.me.num_me = 1;
1356	1356	adev->gfx.me.num_pipe_per_me = 1;
1357	1357	adev->gfx.me.num_queue_per_pipe = 1;
1358		− adev->gfx.mec.num_mec = 2;
	1358	+ adev->gfx.mec.num_mec = 1;
1359	1359	adev->gfx.mec.num_pipe_per_mec = 2;
1360	1360	adev->gfx.mec.num_queue_per_pipe = 4;
1361	1361	break;
@@ -3001,37 +3001,19 @@ static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) · 1639 unmodified lines
3001	3001
3002	3002	static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3003	3003	{
3004		− int r, i;
3005		− struct amdgpu_ring *ring;
	3004	+ int i, r;
3006	3005
3007	3006	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3008		− ring = &adev->gfx.gfx_ring[i];
3009		−
3010		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
3011		− if (unlikely(r != 0))
3012		− goto done;
3013		−
3014		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3015		− if (!r) {
3016		− r = gfx_v12_0_kgq_init_queue(ring, false);
3017		− amdgpu_bo_kunmap(ring->mqd_obj);
3018		− ring->mqd_ptr = NULL;
3019		− }
3020		− amdgpu_bo_unreserve(ring->mqd_obj);
	3007	+ r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
3021	3008	if (r)
3022		− goto done;
	3009	+ return r;
3023	3010	}
3024	3011
3025	3012	r = amdgpu_gfx_enable_kgq(adev, 0);
3026	3013	if (r)
3027		− goto done;
3028		−
3029		− r = gfx_v12_0_cp_gfx_start(adev);
3030		− if (r)
3031		− goto done;
	3014	+ return r;
3032	3015
3033		−done:
3034		− return r;
	3016	+ return gfx_v12_0_cp_gfx_start(adev);
3035	3017	}
3036	3018
3037	3019	static int gfx_v12_0_compute_mqd_init(struct amdgpu_device adev, void m,
@@ -3344,57 +3326,25 @@ static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) · 306 unmodified lines
3344	3326
3345	3327	static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev)
3346	3328	{
3347		− struct amdgpu_ring *ring;
3348		− int r;
3349		−
3350		− ring = &adev->gfx.kiq[0].ring;
3351		−
3352		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
3353		− if (unlikely(r != 0))
3354		− return r;
3355		−
3356		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3357		− if (unlikely(r != 0)) {
3358		− amdgpu_bo_unreserve(ring->mqd_obj);
3359		− return r;
3360		− }
3361		−
3362		− gfx_v12_0_kiq_init_queue(ring);
3363		− amdgpu_bo_kunmap(ring->mqd_obj);
3364		− ring->mqd_ptr = NULL;
3365		− amdgpu_bo_unreserve(ring->mqd_obj);
3366		− ring->sched.ready = true;
	3329	+ gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
	3330	+ adev->gfx.kiq[0].ring.sched.ready = true;
3367	3331	return 0;
3368	3332	}
3369	3333
3370	3334	static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev)
3371	3335	{
3372		− struct amdgpu_ring *ring = NULL;
3373		− int r = 0, i;
	3336	+ int i, r;
3374	3337
3375	3338	if (!amdgpu_async_gfx_ring)
3376	3339	gfx_v12_0_cp_compute_enable(adev, true);
3377	3340
3378	3341	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3379		− ring = &adev->gfx.compute_ring[i];
3380		−
3381		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
3382		− if (unlikely(r != 0))
3383		− goto done;
3384		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3385		− if (!r) {
3386		− r = gfx_v12_0_kcq_init_queue(ring, false);
3387		− amdgpu_bo_kunmap(ring->mqd_obj);
3388		− ring->mqd_ptr = NULL;
3389		− }
3390		− amdgpu_bo_unreserve(ring->mqd_obj);
	3342	+ r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
3391	3343	if (r)
3392		− goto done;
	3344	+ return r;
3393	3345	}
3394	3346
3395		− r = amdgpu_gfx_enable_kcq(adev, 0);
3396		−done:
3397		− return r;
	3347	+ return amdgpu_gfx_enable_kcq(adev, 0);
3398	3348	}
3399	3349
3400	3350	static int gfx_v12_0_cp_resume(struct amdgpu_device *adev)
@@ -5224,20 +5174,9 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) · 1823 unmodified lines
5224	5174	return r;
5225	5175	}
5226	5176
5227		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
5228		− if (unlikely(r != 0)) {
5229		− dev_err(adev->dev, "fail to resv mqd_obj\n");
5230		− return r;
5231		− }
5232		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
5233		− if (!r) {
5234		− r = gfx_v12_0_kgq_init_queue(ring, true);
5235		− amdgpu_bo_kunmap(ring->mqd_obj);
5236		− ring->mqd_ptr = NULL;
5237		− }
5238		− amdgpu_bo_unreserve(ring->mqd_obj);
	5177	+ r = gfx_v12_0_kgq_init_queue(ring, true);
5239	5178	if (r) {
5240		− DRM_ERROR("fail to unresv mqd_obj\n");
	5179	+ dev_err(adev->dev, "failed to init kgq\n");
5241	5180	return r;
5242	5181	}
5243	5182
@@ -5264,20 +5203,9 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) · 20 unmodified lines
5264	5203	return r;
5265	5204	}
5266	5205
5267		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
5268		− if (unlikely(r != 0)) {
5269		− DRM_ERROR("fail to resv mqd_obj\n");
5270		− return r;
5271		− }
5272		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
5273		− if (!r) {
5274		− r = gfx_v12_0_kcq_init_queue(ring, true);
5275		− amdgpu_bo_kunmap(ring->mqd_obj);
5276		− ring->mqd_ptr = NULL;
5277		− }
5278		− amdgpu_bo_unreserve(ring->mqd_obj);
	5206	+ r = gfx_v12_0_kcq_init_queue(ring, true);
5279	5207	if (r) {
5280		− DRM_ERROR("fail to unresv mqd_obj\n");
	5208	+ dev_err(adev->dev, "failed to init kcq\n");
5281	5209	return r;
5282	5210	}
5283	5211	r = amdgpu_mes_map_legacy_queue(adev, ring);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+5−40

@@ -4683,60 +4683,25 @@ static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev) · 4682 unmodified lines
4683	4683
4684	4684	static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
4685	4685	{
4686		− struct amdgpu_ring *ring;
4687		− int r;
4688		−
4689		− ring = &adev->gfx.kiq[0].ring;
4690		−
4691		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
4692		− if (unlikely(r != 0))
4693		− return r;
4694		−
4695		− r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4696		− if (unlikely(r != 0)) {
4697		− amdgpu_bo_unreserve(ring->mqd_obj);
4698		− return r;
4699		− }
4700		−
4701		− gfx_v8_0_kiq_init_queue(ring);
4702		− amdgpu_bo_kunmap(ring->mqd_obj);
4703		− ring->mqd_ptr = NULL;
4704		− amdgpu_bo_unreserve(ring->mqd_obj);
	4686	+ gfx_v8_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
4705	4687	return 0;
4706	4688	}
4707	4689
4708	4690	static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
4709	4691	{
4710		− struct amdgpu_ring *ring = NULL;
4711		− int r = 0, i;
	4692	+ int i, r;
4712	4693
4713	4694	gfx_v8_0_cp_compute_enable(adev, true);
4714	4695
4715	4696	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4716		− ring = &adev->gfx.compute_ring[i];
4717		−
4718		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
4719		− if (unlikely(r != 0))
4720		− goto done;
4721		− r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4722		− if (!r) {
4723		− r = gfx_v8_0_kcq_init_queue(ring);
4724		− amdgpu_bo_kunmap(ring->mqd_obj);
4725		− ring->mqd_ptr = NULL;
4726		− }
4727		− amdgpu_bo_unreserve(ring->mqd_obj);
	4697	+ r = gfx_v8_0_kcq_init_queue(&adev->gfx.compute_ring[i]);
4728	4698	if (r)
4729		− goto done;
	4699	+ return r;
4730	4700	}
4731	4701
4732	4702	gfx_v8_0_set_mec_doorbell_range(adev);
4733	4703
4734		− r = gfx_v8_0_kiq_kcq_enable(adev);
4735		− if (r)
4736		− goto done;
4737		−
4738		−done:
4739		− return r;
	4704	+ return gfx_v8_0_kiq_kcq_enable(adev);
4740	4705	}
4741	4706
4742	4707	static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+8−50

@@ -1269,6 +1269,7 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) · 1268 unmodified lines
1269	1269	adev->gfx.mec_fw_write_wait = false;
1270	1270
1271	1271	if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) &&
	1272	+ (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2)) &&
1272	1273	((adev->gfx.mec_fw_version < 0x000001a5) \|\|
1273	1274	(adev->gfx.mec_feature_version < 46) \|\|
1274	1275	(adev->gfx.pfp_fw_version < 0x000000b7) \|\|
@@ -3890,55 +3891,23 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore) · 2615 unmodified lines
3890	3891
3891	3892	static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3892	3893	{
3893		− struct amdgpu_ring *ring;
3894		− int r;
3895		−
3896		− ring = &adev->gfx.kiq[0].ring;
3897		−
3898		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
3899		− if (unlikely(r != 0))
3900		− return r;
3901		−
3902		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3903		− if (unlikely(r != 0)) {
3904		− amdgpu_bo_unreserve(ring->mqd_obj);
3905		− return r;
3906		− }
3907		−
3908		− gfx_v9_0_kiq_init_queue(ring);
3909		− amdgpu_bo_kunmap(ring->mqd_obj);
3910		− ring->mqd_ptr = NULL;
3911		− amdgpu_bo_unreserve(ring->mqd_obj);
	3894	+ gfx_v9_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
3912	3895	return 0;
3913	3896	}
3914	3897
3915	3898	static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3916	3899	{
3917		− struct amdgpu_ring *ring = NULL;
3918		− int r = 0, i;
	3900	+ int i, r;
3919	3901
3920	3902	gfx_v9_0_cp_compute_enable(adev, true);
3921	3903
3922	3904	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3923		− ring = &adev->gfx.compute_ring[i];
3924		−
3925		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
3926		− if (unlikely(r != 0))
3927		− goto done;
3928		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3929		− if (!r) {
3930		− r = gfx_v9_0_kcq_init_queue(ring, false);
3931		− amdgpu_bo_kunmap(ring->mqd_obj);
3932		− ring->mqd_ptr = NULL;
3933		− }
3934		− amdgpu_bo_unreserve(ring->mqd_obj);
	3905	+ r = gfx_v9_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
3935	3906	if (r)
3936		− goto done;
	3907	+ return r;
3937	3908	}
3938	3909
3939		− r = amdgpu_gfx_enable_kcq(adev, 0);
3940		−done:
3941		− return r;
	3910	+ return amdgpu_gfx_enable_kcq(adev, 0);
3942	3911	}
3943	3912
3944	3913	static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
@@ -7319,20 +7288,9 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, · 3374 unmodified lines
7319	7288	return r;
7320	7289	}
7321	7290
7322		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
7323		− if (unlikely(r != 0)){
7324		− dev_err(adev->dev, "fail to resv mqd_obj\n");
7325		− return r;
7326		− }
7327		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7328		− if (!r) {
7329		− r = gfx_v9_0_kcq_init_queue(ring, true);
7330		− amdgpu_bo_kunmap(ring->mqd_obj);
7331		− ring->mqd_ptr = NULL;
7332		− }
7333		− amdgpu_bo_unreserve(ring->mqd_obj);
	7291	+ r = gfx_v9_0_kcq_init_queue(ring, true);
7334	7292	if (r) {
7335		− dev_err(adev->dev, "fail to unresv mqd_obj\n");
	7293	+ dev_err(adev->dev, "fail to init kcq\n");
7336	7294	return r;
7337	7295	}
7338	7296	spin_lock_irqsave(&kiq->ring_lock, flags);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c+14−54

@@ -867,13 +867,12 @@ static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, · 866 unmodified lines
867	867
868	868	switch (type) {
869	869	case ACA_SMU_TYPE_UE:
870		− bank->aca_err_type = ACA_BANK_ERR_UE_DE_DECODE(bank);
	870	+ bank->aca_err_type = ACA_ERROR_TYPE_UE;
871	871	ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL);
872	872	break;
873	873	case ACA_SMU_TYPE_CE:
874		− bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank);
875		− ret = aca_error_cache_log_bank_error(handle, &info,
876		− bank->aca_err_type,
	874	+ bank->aca_err_type = ACA_ERROR_TYPE_CE;
	875	+ ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,
877	876	ACA_REG__MISC0__ERRCNT(misc0));
878	877	break;
879	878	default:
@@ -2168,55 +2167,27 @@ static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_ · 1288 unmodified lines
2168	2167
2169	2168	static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)
2170	2169	{
2171		− struct amdgpu_ring *ring;
2172		− int r;
2173		−
2174		− ring = &adev->gfx.kiq[xcc_id].ring;
2175		−
2176		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
2177		− if (unlikely(r != 0))
2178		− return r;
2179		−
2180		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2181		− if (unlikely(r != 0)) {
2182		− amdgpu_bo_unreserve(ring->mqd_obj);
2183		− return r;
2184		− }
2185		−
2186		− gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id);
2187		− amdgpu_bo_kunmap(ring->mqd_obj);
2188		− ring->mqd_ptr = NULL;
2189		− amdgpu_bo_unreserve(ring->mqd_obj);
	2170	+ gfx_v9_4_3_xcc_kiq_init_queue(&adev->gfx.kiq[xcc_id].ring, xcc_id);
2190	2171	return 0;
2191	2172	}
2192	2173
2193	2174	static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id)
2194	2175	{
2195		− struct amdgpu_ring *ring = NULL;
2196		− int r = 0, i;
	2176	+ struct amdgpu_ring *ring;
	2177	+ int i, r;
2197	2178
2198	2179	gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);
2199	2180
2200	2181	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2201		− ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings];
2202		−
2203		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
2204		− if (unlikely(r != 0))
2205		− goto done;
2206		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2207		− if (!r) {
2208		− r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false);
2209		− amdgpu_bo_kunmap(ring->mqd_obj);
2210		− ring->mqd_ptr = NULL;
2211		− }
2212		− amdgpu_bo_unreserve(ring->mqd_obj);
	2182	+ ring = &adev->gfx.compute_ring[i + xcc_id *
	2183	+ adev->gfx.num_compute_rings];
	2184	+
	2185	+ r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false);
2213	2186	if (r)
2214		− goto done;
	2187	+ return r;
2215	2188	}
2216	2189
2217		− r = amdgpu_gfx_enable_kcq(adev, xcc_id);
2218		−done:
2219		− return r;
	2190	+ return amdgpu_gfx_enable_kcq(adev, xcc_id);
2220	2191	}
2221	2192
2222	2193	static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)
@@ -3588,20 +3559,9 @@ pipe_reset: · 1365 unmodified lines
3588	3559	return r;
3589	3560	}
3590	3561
3591		− r = amdgpu_bo_reserve(ring->mqd_obj, false);
3592		− if (unlikely(r != 0)){
3593		− dev_err(adev->dev, "fail to resv mqd_obj\n");
3594		− return r;
3595		− }
3596		− r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3597		− if (!r) {
3598		− r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true);
3599		− amdgpu_bo_kunmap(ring->mqd_obj);
3600		− ring->mqd_ptr = NULL;
3601		− }
3602		− amdgpu_bo_unreserve(ring->mqd_obj);
	3562	+ r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true);
3603	3563	if (r) {
3604		− dev_err(adev->dev, "fail to unresv mqd_obj\n");
	3564	+ dev_err(adev->dev, "fail to init kcq\n");
3605	3565	return r;
3606	3566	}
3607	3567	spin_lock_irqsave(&kiq->ring_lock, flags);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c+1−1

@@ -1328,7 +1328,7 @@ static int jpeg_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_ban · 1327 unmodified lines
1328	1328	1ULL);
1329	1329	break;
1330	1330	case ACA_SMU_TYPE_CE:
1331		− bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank);
	1331	+ bank->aca_err_type = ACA_ERROR_TYPE_CE;
1332	1332	ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,
1333	1333	ACA_REG__MISC0__ERRCNT(misc0));
1334	1334	break;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c+1−1

@@ -751,7 +751,7 @@ static int mmhub_v1_8_aca_bank_parser(struct aca_handle *handle, struct aca_bank · 750 unmodified lines
751	751	1ULL);
752	752	break;
753	753	case ACA_SMU_TYPE_CE:
754		− bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank);
	754	+ bank->aca_err_type = ACA_ERROR_TYPE_CE;
755	755	ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,
756	756	ACA_REG__MISC0__ERRCNT(misc0));
757	757	break;

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c+15−64

@@ -31,7 +31,6 @@ · 30 unmodified lines
31	31	#include "amdgpu_ucode.h"
32	32	#include "amdgpu_trace.h"
33	33	#include "amdgpu_reset.h"
34		−#include "gc/gc_9_0_sh_mask.h"
35	34
36	35	#include "sdma/sdma_4_4_2_offset.h"
37	36	#include "sdma/sdma_4_4_2_sh_mask.h"
@@ -1291,71 +1290,21 @@ static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) · 1253 unmodified lines
1291	1290	seq, 0xffffffff, 4);
1292	1291	}
1293	1292
1294		−/*
1295		− * sdma_v4_4_2_get_invalidate_req - Construct the VM_INVALIDATE_ENG0_REQ register value
1296		− * @vmid: The VMID to invalidate
1297		− * @flush_type: The type of flush (0 = legacy, 1 = lightweight, 2 = heavyweight)
1298		− *
1299		− * This function constructs the VM_INVALIDATE_ENG0_REQ register value for the specified VMID
1300		− * and flush type. It ensures that all relevant page table cache levels (L1 PTEs, L2 PTEs, and
1301		− * L2 PDEs) are invalidated.
1302		− */
1303		−static uint32_t sdma_v4_4_2_get_invalidate_req(unsigned int vmid,
1304		− uint32_t flush_type)
1305		−{
1306		− u32 req = 0;
1307		−
1308		− req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
1309		− PER_VMID_INVALIDATE_REQ, 1 << vmid);
1310		− req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
1311		− req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
1312		− req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
1313		− req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
1314		− req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
1315		− req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
1316		− req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
1317		− CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
1318	1293
1319		− return req;
1320		−}
1321		−
1322		−/*
1323		− * sdma_v4_4_2_ring_emit_vm_flush - Emit VM flush commands for SDMA
1324		− * @ring: The SDMA ring
1325		− * @vmid: The VMID to flush
1326		− * @pd_addr: The page directory address
	1294	+/**
	1295	+ * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1327	1296	*
1328		− * This function emits the necessary register writes and waits to perform a VM flush for the
1329		− * specified VMID. It updates the PTB address registers and issues a VM invalidation request
1330		− * using the specified VM invalidation engine.
	1297	+ * @ring: amdgpu_ring pointer
	1298	+ * @vmid: vmid number to use
	1299	+ * @pd_addr: address
	1300	+ *
	1301	+ * Update the page table base and flush the VM TLB
	1302	+ * using sDMA.
1331	1303	*/
1332	1304	static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1333		− unsigned int vmid, uint64_t pd_addr)
	1305	+ unsigned vmid, uint64_t pd_addr)
1334	1306	{
1335		− struct amdgpu_device *adev = ring->adev;
1336		− uint32_t req = sdma_v4_4_2_get_invalidate_req(vmid, 0);
1337		− unsigned int eng = ring->vm_inv_eng;
1338		− struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub];
1339		−
1340		− amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1341		− (hub->ctx_addr_distance * vmid),
1342		− lower_32_bits(pd_addr));
1343		−
1344		− amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1345		− (hub->ctx_addr_distance * vmid),
1346		− upper_32_bits(pd_addr));
1347		− /*
1348		− * Construct and emit the VM invalidation packet
1349		− */
1350		− amdgpu_ring_write(ring,
1351		− SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_VM_INVALIDATE) \|
1352		− SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATE) \|
1353		− SDMA_PKT_VM_INVALIDATION_HEADER_XCC0_ENG_ID(0x1f) \|
1354		− SDMA_PKT_VM_INVALIDATION_HEADER_XCC1_ENG_ID(0x1f) \|
1355		− SDMA_PKT_VM_INVALIDATION_HEADER_MMHUB_ENG_ID(eng));
1356		− amdgpu_ring_write(ring, SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(req));
1357		− amdgpu_ring_write(ring, 0);
1358		− amdgpu_ring_write(ring, SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(BIT(vmid)));
	1307	+ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1359	1308	}
1360	1309
1361	1310	static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
@@ -2177,7 +2126,8 @@ static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { · 815 unmodified lines
2177	2126	3 + /* hdp invalidate */
2178	2127	6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
2179	2128	/* sdma_v4_4_2_ring_emit_vm_flush */
2180		− 4 + 2 * 3 +
	2129	+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
	2130	+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2181	2131	10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
2182	2132	.emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
2183	2133	.emit_ib = sdma_v4_4_2_ring_emit_ib,
@@ -2209,7 +2159,8 @@ static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { · 25 unmodified lines
2209	2159	3 + /* hdp invalidate */
2210	2160	6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
2211	2161	/* sdma_v4_4_2_ring_emit_vm_flush */
2212		− 4 + 2 * 3 +
	2162	+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
	2163	+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2213	2164	10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
2214	2165	.emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
2215	2166	.emit_ib = sdma_v4_4_2_ring_emit_ib,
@@ -2595,7 +2546,7 @@ static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_ban · 379 unmodified lines
2595	2546	1ULL);
2596	2547	break;
2597	2548	case ACA_SMU_TYPE_CE:
2598		− bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank);
	2549	+ bank->aca_err_type = ACA_ERROR_TYPE_CE;
2599	2550	ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,
2600	2551	ACA_REG__MISC0__ERRCNT(misc0));
2601	2552	break;

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h+3−0

@@ -92,6 +92,9 @@ enum ta_ras_block { · 91 unmodified lines
92	92	TA_RAS_BLOCK__MCA,
93	93	TA_RAS_BLOCK__VCN,
94	94	TA_RAS_BLOCK__JPEG,
	95	+ TA_RAS_BLOCK__IH,
	96	+ TA_RAS_BLOCK__MPIO,
	97	+ TA_RAS_BLOCK__MMSCH,
95	98	TA_NUM_BLOCK_MAX
96	99	};
97	100

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c+2−1

@@ -85,7 +85,8 @@ bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_sta · 84 unmodified lines
85	85
86	86	return (amdgpu_ras_is_poison_mode_supported(adev) &&
87	87	(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
88		− (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1));
	88	+ ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1) \|\|
	89	+ (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison) == 1)));
89	90	}
90	91
91	92	bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status)

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c+1−1

@@ -1965,7 +1965,7 @@ static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank · 1964 unmodified lines
1965	1965	1ULL);
1966	1966	break;
1967	1967	case ACA_SMU_TYPE_CE:
1968		− bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank);
	1968	+ bank->aca_err_type = ACA_ERROR_TYPE_CE;
1969	1969	ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,
1970	1970	ACA_REG__MISC0__ERRCNT(misc0));
1971	1971	break;

drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h+0−70

@@ -64,9 +64,6 @@ · 63 unmodified lines
64	64	#define HEADER_BARRIER 5
65	65	#define SDMA_OP_AQL_COPY 0
66	66	#define SDMA_OP_AQL_BARRIER_OR 0
67		−/* vm invalidation is only available for GC9.4.3/GC9.4.4/GC9.5.0 */
68		−#define SDMA_OP_VM_INVALIDATE 8
69		−#define SDMA_SUBOP_VM_INVALIDATE 4
70	67
71	68	/define for op field/
72	69	#define SDMA_PKT_HEADER_op_offset 0
@@ -3334,72 +3331,5 @@ · 3261 unmodified lines
3334	3331	#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0
3335	3332	#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)
3336	3333
3337		−/*
3338		−** Definitions for SDMA_PKT_VM_INVALIDATION packet
3339		−*/
3340		−
3341		−/define for HEADER word/
3342		−/define for op field/
3343		−#define SDMA_PKT_VM_INVALIDATION_HEADER_op_offset 0
3344		−#define SDMA_PKT_VM_INVALIDATION_HEADER_op_mask 0x000000FF
3345		−#define SDMA_PKT_VM_INVALIDATION_HEADER_op_shift 0
3346		−#define SDMA_PKT_VM_INVALIDATION_HEADER_OP(x) ((x & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift)
3347		−
3348		−/define for sub_op field/
3349		−#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset 0
3350		−#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask 0x000000FF
3351		−#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift 8
3352		−#define SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x) ((x & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift)
3353		−
3354		−/define for xcc0_eng_id field/
3355		−#define SDMA_PKT_VM_INVALIDATION_HEADER_xcc0_eng_id_offset 0
3356		−#define SDMA_PKT_VM_INVALIDATION_HEADER_xcc0_eng_id_mask 0x0000001F
3357		−#define SDMA_PKT_VM_INVALIDATION_HEADER_xcc0_eng_id_shift 16
3358		−#define SDMA_PKT_VM_INVALIDATION_HEADER_XCC0_ENG_ID(x) ((x & SDMA_PKT_VM_INVALIDATION_HEADER_xcc0_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_xcc0_eng_id_shift)
3359		−
3360		−/define for xcc1_eng_id field/
3361		−#define SDMA_PKT_VM_INVALIDATION_HEADER_xcc1_eng_id_offset 0
3362		−#define SDMA_PKT_VM_INVALIDATION_HEADER_xcc1_eng_id_mask 0x0000001F
3363		−#define SDMA_PKT_VM_INVALIDATION_HEADER_xcc1_eng_id_shift 21
3364		−#define SDMA_PKT_VM_INVALIDATION_HEADER_XCC1_ENG_ID(x) ((x & SDMA_PKT_VM_INVALIDATION_HEADER_xcc1_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_xcc1_eng_id_shift)
3365		−
3366		−/define for mmhub_eng_id field/
3367		−#define SDMA_PKT_VM_INVALIDATION_HEADER_mmhub_eng_id_offset 0
3368		−#define SDMA_PKT_VM_INVALIDATION_HEADER_mmhub_eng_id_mask 0x0000001F
3369		−#define SDMA_PKT_VM_INVALIDATION_HEADER_mmhub_eng_id_shift 26
3370		−#define SDMA_PKT_VM_INVALIDATION_HEADER_MMHUB_ENG_ID(x) ((x & SDMA_PKT_VM_INVALIDATION_HEADER_mmhub_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mmhub_eng_id_shift)
3371		−
3372		−/define for INVALIDATEREQ word/
3373		−/define for invalidatereq field/
3374		−#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset 1
3375		−#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask 0xFFFFFFFF
3376		−#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift 0
3377		−#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x) ((x & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift)
3378		−
3379		−/define for ADDRESSRANGELO word/
3380		−/define for addressrangelo field/
3381		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset 2
3382		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask 0xFFFFFFFF
3383		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift 0
3384		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x) ((x & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift)
3385		−
3386		−/define for ADDRESSRANGEHI word/
3387		−/define for invalidateack field/
3388		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset 3
3389		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask 0x0000FFFF
3390		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift 0
3391		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x) ((x & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift)
3392		−
3393		−/define for addressrangehi field/
3394		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset 3
3395		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask 0x0000001F
3396		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift 16
3397		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x) ((x & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift)
3398		−
3399		−/define for reserved field/
3400		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset 3
3401		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask 0x000001FF
3402		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift 23
3403		−#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x) ((x & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift)
3404	3334
3405	3335	#endif /* __SDMA_PKT_OPEN_H_ */

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+35−8

@@ -8707,14 +8707,39 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, · 8706 unmodified lines
8707	8707	int offdelay;
8708	8708
8709	8709	if (acrtc_state) {
8710		− if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
8711		− IP_VERSION(3, 5, 0) \|\|
8712		− acrtc_state->stream->link->psr_settings.psr_version <
8713		− DC_PSR_VERSION_UNSUPPORTED \|\|
8714		− !(adev->flags & AMD_IS_APU)) {
8715		− timing = &acrtc_state->stream->timing;
8716		−
8717		− /* at least 2 frames */
	8710	+ timing = &acrtc_state->stream->timing;
	8711	+
	8712	+ /*
	8713	+ * Depending on when the HW latching event of double-buffered
	8714	+ * registers happen relative to the PSR SDP deadline, and how
	8715	+ * bad the Panel clock has drifted since the last ALPM off
	8716	+ * event, there can be up to 3 frames of delay between sending
	8717	+ * the PSR exit cmd to DMUB fw, and when the panel starts
	8718	+ * displaying live frames.
	8719	+ *
	8720	+ * We can set:
	8721	+ *
	8722	+ * 20/100 * offdelay_ms = 3_frames_ms
	8723	+ * => offdelay_ms = 5 * 3_frames_ms
	8724	+ *
	8725	+ * This ensures that `3_frames_ms` will only be experienced as a
	8726	+ * 20% delay on top how long the display has been static, and
	8727	+ * thus make the delay less perceivable.
	8728	+ */
	8729	+ if (acrtc_state->stream->link->psr_settings.psr_version <
	8730	+ DC_PSR_VERSION_UNSUPPORTED) {
	8731	+ offdelay = DIV64_U64_ROUND_UP((u64)5 * 3 * 10 *
	8732	+ timing->v_total *
	8733	+ timing->h_total,
	8734	+ timing->pix_clk_100hz);
	8735	+ config.offdelay_ms = offdelay ?: 30;
	8736	+ } else if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
	8737	+ IP_VERSION(3, 5, 0) \|\|
	8738	+ !(adev->flags & AMD_IS_APU)) {
	8739	+ /*
	8740	+ * Older HW and DGPU have issues with instant off;
	8741	+ * use a 2 frame offdelay.
	8742	+ */
8718	8743	offdelay = DIV64_U64_ROUND_UP((u64)20 *
8719	8744	timing->v_total *
8720	8745	timing->h_total,
@@ -8722,6 +8747,8 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, · 1 unmodified line
8722	8747
8723	8748	config.offdelay_ms = offdelay ?: 30;
8724	8749	} else {
	8750	+ /* offdelay_ms = 0 will never disable vblank */
	8751	+ config.offdelay_ms = 1;
8725	8752	config.disable_immediate = true;
8726	8753	}
8727	8754

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c+1−1

@@ -590,11 +590,11 @@ void dml2_init_soc_states(struct dml2_context dml2, const struct dc in_dc, · 589 unmodified lines
590	590	p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;
591	591	p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;
592	592
	593	+ p->out_states->state_array[i].dscclk_mhz = max_dispclk_mhz / 3.0;
593	594	p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;
594	595	p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;
595	596
596	597	/* Dependent states. */
597		− p->out_states->state_array[i].dscclk_mhz = p->in_states->state_array[i].dscclk_mhz;
598	598	p->out_states->state_array[i].dram_speed_mts = p->in_states->state_array[i].dram_speed_mts;
599	599	p->out_states->state_array[i].fabricclk_mhz = p->in_states->state_array[i].fabricclk_mhz;
600	600	p->out_states->state_array[i].socclk_mhz = p->in_states->state_array[i].socclk_mhz;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c+5−1

@@ -3033,7 +3033,11 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) · 3032 unmodified lines
3033	3033	dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);
3034	3034
3035	3035	phyd32clk = get_phyd32clk_src(link);
3036		− dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
	3036	+ if (link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN) {
	3037	+ dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
	3038	+ } else {
	3039	+ dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
	3040	+ }
3037	3041	} else {
3038	3042	if (dccg->funcs->enable_symclk_se)
3039	3043	dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c+5−2

@@ -936,8 +936,11 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx) · 935 unmodified lines
936	936	if (dc_is_dp_signal(pipe_ctx->stream->signal) \|\| dc_is_virtual_signal(pipe_ctx->stream->signal)) {
937	937	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
938	938	dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst);
939		−
940		− dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
	939	+ if (link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN) {
	940	+ dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
	941	+ } else {
	942	+ dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
	943	+ }
941	944	} else {
942	945	dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,
943	946	link_enc->transmitter - TRANSMITTER_UNIPHY_A);

drivers/gpu/drm/amd/include/kgd_pp_interface.h+114−0

@@ -341,6 +341,7 @@ enum pp_policy_soc_pstate { · 340 unmodified lines
341	341	#define MAX_CLKS 4
342	342	#define NUM_VCN 4
343	343	#define NUM_JPEG_ENG 32
	344	+#define NUM_JPEG_ENG_V1 40
344	345	#define MAX_XCC 8
345	346	#define NUM_XCP 8
346	347	struct seq_file;
@@ -376,6 +377,20 @@ struct amdgpu_xcp_metrics_v1_1 { · 29 unmodified lines
376	377	uint64_t gfx_below_host_limit_acc[MAX_XCC];
377	378	};
378	379
	380	+struct amdgpu_xcp_metrics_v1_2 {
	381	+ /* Utilization Instantaneous (%) */
	382	+ uint32_t gfx_busy_inst[MAX_XCC];
	383	+ uint16_t jpeg_busy[NUM_JPEG_ENG_V1];
	384	+ uint16_t vcn_busy[NUM_VCN];
	385	+ /* Utilization Accumulated (%) */
	386	+ uint64_t gfx_busy_acc[MAX_XCC];
	387	+ /* Total App Clock Counter Accumulated */
	388	+ uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC];
	389	+ uint64_t gfx_below_host_limit_thm_acc[MAX_XCC];
	390	+ uint64_t gfx_low_utilization_acc[MAX_XCC];
	391	+ uint64_t gfx_below_host_limit_total_acc[MAX_XCC];
	392	+};
	393	+
379	394	struct amd_pm_funcs {
380	395	/* export for dpm on ci and si */
381	396	int (pre_set_power_state)(void handle);
@@ -1090,6 +1105,105 @@ struct gpu_metrics_v1_7 { · 708 unmodified lines
1090	1105	uint32_t pcie_lc_perf_other_end_recovery;
1091	1106	};
1092	1107
	1108	+struct gpu_metrics_v1_8 {
	1109	+ struct metrics_table_header common_header;
	1110	+
	1111	+ /* Temperature (Celsius) */
	1112	+ uint16_t temperature_hotspot;
	1113	+ uint16_t temperature_mem;
	1114	+ uint16_t temperature_vrsoc;
	1115	+
	1116	+ /* Power (Watts) */
	1117	+ uint16_t curr_socket_power;
	1118	+
	1119	+ /* Utilization (%) */
	1120	+ uint16_t average_gfx_activity;
	1121	+ uint16_t average_umc_activity; // memory controller
	1122	+
	1123	+ /* VRAM max bandwidthi (in GB/sec) at max memory clock */
	1124	+ uint64_t mem_max_bandwidth;
	1125	+
	1126	+ /* Energy (15.259uJ (2^-16) units) */
	1127	+ uint64_t energy_accumulator;
	1128	+
	1129	+ /* Driver attached timestamp (in ns) */
	1130	+ uint64_t system_clock_counter;
	1131	+
	1132	+ /* Accumulation cycle counter */
	1133	+ uint32_t accumulation_counter;
	1134	+
	1135	+ /* Accumulated throttler residencies */
	1136	+ uint32_t prochot_residency_acc;
	1137	+ uint32_t ppt_residency_acc;
	1138	+ uint32_t socket_thm_residency_acc;
	1139	+ uint32_t vr_thm_residency_acc;
	1140	+ uint32_t hbm_thm_residency_acc;
	1141	+
	1142	+ /* Clock Lock Status. Each bit corresponds to clock instance */
	1143	+ uint32_t gfxclk_lock_status;
	1144	+
	1145	+ /* Link width (number of lanes) and speed (in 0.1 GT/s) */
	1146	+ uint16_t pcie_link_width;
	1147	+ uint16_t pcie_link_speed;
	1148	+
	1149	+ /* XGMI bus width and bitrate (in Gbps) */
	1150	+ uint16_t xgmi_link_width;
	1151	+ uint16_t xgmi_link_speed;
	1152	+
	1153	+ /* Utilization Accumulated (%) */
	1154	+ uint32_t gfx_activity_acc;
	1155	+ uint32_t mem_activity_acc;
	1156	+
	1157	+ /PCIE accumulated bandwidth (GB/sec) /
	1158	+ uint64_t pcie_bandwidth_acc;
	1159	+
	1160	+ /PCIE instantaneous bandwidth (GB/sec) /
	1161	+ uint64_t pcie_bandwidth_inst;
	1162	+
	1163	+ /* PCIE L0 to recovery state transition accumulated count */
	1164	+ uint64_t pcie_l0_to_recov_count_acc;
	1165	+
	1166	+ /* PCIE replay accumulated count */
	1167	+ uint64_t pcie_replay_count_acc;
	1168	+
	1169	+ /* PCIE replay rollover accumulated count */
	1170	+ uint64_t pcie_replay_rover_count_acc;
	1171	+
	1172	+ /* PCIE NAK sent accumulated count */
	1173	+ uint32_t pcie_nak_sent_count_acc;
	1174	+
	1175	+ /* PCIE NAK received accumulated count */
	1176	+ uint32_t pcie_nak_rcvd_count_acc;
	1177	+
	1178	+ /* XGMI accumulated data transfer size(KiloBytes) */
	1179	+ uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
	1180	+ uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
	1181	+
	1182	+ /* XGMI link status(active/inactive) */
	1183	+ uint16_t xgmi_link_status[NUM_XGMI_LINKS];
	1184	+
	1185	+ uint16_t padding;
	1186	+
	1187	+ /* PMFW attached timestamp (10ns resolution) */
	1188	+ uint64_t firmware_timestamp;
	1189	+
	1190	+ /* Current clocks (Mhz) */
	1191	+ uint16_t current_gfxclk[MAX_GFX_CLKS];
	1192	+ uint16_t current_socclk[MAX_CLKS];
	1193	+ uint16_t current_vclk0[MAX_CLKS];
	1194	+ uint16_t current_dclk0[MAX_CLKS];
	1195	+ uint16_t current_uclk;
	1196	+
	1197	+ /* Number of current partition */
	1198	+ uint16_t num_partition;
	1199	+
	1200	+ /* XCP metrics stats */
	1201	+ struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP];
	1202	+
	1203	+ /* PCIE other end recovery counter */
	1204	+ uint32_t pcie_lc_perf_other_end_recovery;
	1205	+};
	1206	+
1093	1207	/*
1094	1208	* gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
1095	1209	* Use gpu_metrics_v2_1 or later instead.

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c+2−2

@@ -267,10 +267,10 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) · 266 unmodified lines
267	267	if (hwmgr->thermal_controller.fanInfo.bNoFan \|\|
268	268	(hwmgr->thermal_controller.fanInfo.
269	269	ucTachometerPulsesPerRevolution == 0) \|\|
270		− speed == 0 \|\|
	270	+ (!speed \|\| speed > UINT_MAX/8) \|\|
271	271	(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) \|\|
272	272	(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
273		− return 0;
	273	+ return -EINVAL;
274	274
275	275	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
276	276	smu7_fan_ctrl_stop_smc_fan_control(hwmgr);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c+2−2

@@ -307,10 +307,10 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) · 306 unmodified lines
307	307	int result = 0;
308	308
309	309	if (hwmgr->thermal_controller.fanInfo.bNoFan \|\|
310		− speed == 0 \|\|
	310	+ (!speed \|\| speed > UINT_MAX/8) \|\|
311	311	(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) \|\|
312	312	(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
313		− return -1;
	313	+ return -EINVAL;
314	314
315	315	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
316	316	result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c+1−1

@@ -191,7 +191,7 @@ int vega20_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) · 190 unmodified lines
191	191	uint32_t tach_period, crystal_clock_freq;
192	192	int result = 0;
193	193
194		− if (!speed)
	194	+ if (!speed \|\| speed > UINT_MAX/8)
195	195	return -EINVAL;
196	196
197	197	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h+5−2

@@ -127,7 +127,7 @@ typedef enum { · 126 unmodified lines
127	127	VOLTAGE_GUARDBAND_COUNT
128	128	} GFX_GUARDBAND_e;
129	129
130		−#define SMU_METRICS_TABLE_VERSION 0xF
	130	+#define SMU_METRICS_TABLE_VERSION 0x10
131	131
132	132	// Unified metrics table for smu_v13_0_6
133	133	typedef struct __attribute__((packed, aligned(4))) {
@@ -241,7 +241,10 @@ typedef struct __attribute__((packed, aligned(4))) { · 107 unmodified lines
241	241	uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated
242	242
243	243	//Total App Clock Counter
244		− uint64_t GfxclkBelowHostLimitAcc[8];
	244	+ uint64_t GfxclkBelowHostLimitPptAcc[8];
	245	+ uint64_t GfxclkBelowHostLimitThmAcc[8];
	246	+ uint64_t GfxclkBelowHostLimitTotalAcc[8];
	247	+ uint64_t GfxclkLowUtilizationAcc[8];
245	248	} MetricsTableV0_t;
246	249
247	250	// Metrics table for smu_v13_0_6 APUS

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c+3−0

@@ -1267,6 +1267,9 @@ static int arcturus_set_fan_speed_rpm(struct smu_context *smu, · 1266 unmodified lines
1267	1267	uint32_t crystal_clock_freq = 2500;
1268	1268	uint32_t tach_period;
1269	1269
	1270	+ if (!speed \|\| speed > UINT_MAX/8)
	1271	+ return -EINVAL;
	1272	+
1270	1273	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1271	1274	WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
1272	1275	REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c+1−1

@@ -1226,7 +1226,7 @@ int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, · 1225 unmodified lines
1226	1226	uint32_t tach_period;
1227	1227	int ret;
1228	1228
1229		− if (!speed)
	1229	+ if (!speed \|\| speed > UINT_MAX/8)
1230	1230	return -EINVAL;
1231	1231
1232	1232	ret = smu_v13_0_auto_fan_control(smu, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c+0−15

@@ -109,7 +109,6 @@ enum smu_v13_0_6_caps { · 108 unmodified lines
109	109	SMU_CAP(OTHER_END_METRICS),
110	110	SMU_CAP(SET_UCLK_MAX),
111	111	SMU_CAP(PCIE_METRICS),
112		− SMU_CAP(HST_LIMIT_METRICS),
113	112	SMU_CAP(MCA_DEBUG_MODE),
114	113	SMU_CAP(PER_INST_METRICS),
115	114	SMU_CAP(CTF_LIMIT),
@@ -325,8 +324,6 @@ static void smu_v13_0_14_init_caps(struct smu_context *smu) · 209 unmodified lines
325	324
326	325	if (fw_ver >= 0x05550E00)
327	326	smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
328		− if (fw_ver >= 0x05551000)
329		− smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
330	327	if (fw_ver >= 0x05550B00)
331	328	smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
332	329	if (fw_ver >= 0x5551200)
@@ -342,7 +339,6 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu) · 9 unmodified lines
342	339	SMU_CAP(RMA_MSG),
343	340	SMU_CAP(ACA_SYND),
344	341	SMU_CAP(OTHER_END_METRICS),
345		− SMU_CAP(HST_LIMIT_METRICS),
346	342	SMU_CAP(PER_INST_METRICS) };
347	343	uint32_t fw_ver = smu->smc_fw_version;
348	344
@@ -387,8 +383,6 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) · 38 unmodified lines
387	383	smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
388	384	smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
389	385
390		− if (fw_ver >= 0x04556F00)
391		− smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
392	386	if (fw_ver >= 0x04556A00)
393	387	smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
394	388	} else {
@@ -408,8 +402,6 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) · 13 unmodified lines
408	402	smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
409	403	if (fw_ver < 0x00555600)
410	404	smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
411		− if (pgm == 0 && fw_ver >= 0x557900)
412		− smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
413	405	}
414	406	if (((pgm == 7) && (fw_ver >= 0x7550700)) \|\|
415	407	((pgm == 0) && (fw_ver >= 0x00557900)) \|\|
@@ -2674,13 +2666,6 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context smu, void *table · 2258 unmodified lines
2674	2666	gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
2675	2667	SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc,
2676	2668	version)[inst]);
2677		−
2678		− if (smu_v13_0_6_cap_supported(
2679		− smu, SMU_CAP(HST_LIMIT_METRICS)))
2680		− gpu_metrics->xcp_stats[i].gfx_below_host_limit_acc[idx] =
2681		− SMUQ10_ROUND(GET_GPU_METRIC_FIELD
2682		− (GfxclkBelowHostLimitAcc, version)
2683		− [inst]);
2684	2669	idx++;
2685	2670	}
2686	2671	}

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c+54−1

@@ -79,6 +79,7 @@ · 78 unmodified lines
79	79	#define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
80	80	#define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
81	81	#define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
	82	+#define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11
82	83
83	84	static struct cmn2asic_msg_mapping smu_v14_0_2_message_map[SMU_MSG_MAX_COUNT] = {
84	85	MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
@@ -1052,6 +1053,10 @@ static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu, · 967 unmodified lines
1052	1053	od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1053	1054	od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1054	1055	break;
	1056	+ case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE:
	1057	+ od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable;
	1058	+ od_max_setting = overdrive_upperlimits->FanZeroRpmEnable;
	1059	+ break;
1055	1060	default:
1056	1061	od_min_setting = od_max_setting = INT_MAX;
1057	1062	break;
@@ -1330,6 +1335,24 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, · 272 unmodified lines
1330	1335	min_value, max_value);
1331	1336	break;
1332	1337
	1338	+ case SMU_OD_FAN_ZERO_RPM_ENABLE:
	1339	+ if (!smu_v14_0_2_is_od_feature_supported(smu,
	1340	+ PP_OD_FEATURE_ZERO_FAN_BIT))
	1341	+ break;
	1342	+
	1343	+ size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n");
	1344	+ size += sysfs_emit_at(buf, size, "%d\n",
	1345	+ (int)od_table->OverDriveTable.FanZeroRpmEnable);
	1346	+
	1347	+ size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
	1348	+ smu_v14_0_2_get_od_setting_limits(smu,
	1349	+ PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
	1350	+ &min_value,
	1351	+ &max_value);
	1352	+ size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n",
	1353	+ min_value, max_value);
	1354	+ break;
	1355	+
1333	1356	case SMU_OD_RANGE:
1334	1357	if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1335	1358	!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
@@ -2270,7 +2293,9 @@ static void smu_v14_0_2_set_supported_od_feature_mask(struct smu_context *smu) · 934 unmodified lines
2270	2293	OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE \|
2271	2294	OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET \|
2272	2295	OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE \|
2273		− OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET;
	2296	+ OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET \|
	2297	+ OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE \|
	2298	+ OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET;
2274	2299	}
2275	2300
2276	2301	static int smu_v14_0_2_get_overdrive_table(struct smu_context *smu,
@@ -2349,6 +2374,8 @@ static int smu_v14_0_2_set_default_od_settings(struct smu_context *smu) · 72 unmodified lines
2349	2374	user_od_table_bak.OverDriveTable.FanTargetTemperature;
2350	2375	user_od_table->OverDriveTable.FanMinimumPwm =
2351	2376	user_od_table_bak.OverDriveTable.FanMinimumPwm;
	2377	+ user_od_table->OverDriveTable.FanZeroRpmEnable =
	2378	+ user_od_table_bak.OverDriveTable.FanZeroRpmEnable;
2352	2379	}
2353	2380
2354	2381	smu_v14_0_2_set_supported_od_feature_mask(smu);
@@ -2396,6 +2423,11 @@ static int smu_v14_0_2_od_restore_table_single(struct smu_context *smu, long inp · 41 unmodified lines
2396	2423	od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2397	2424	od_table->OverDriveTable.FeatureCtrlMask \|= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2398	2425	break;
	2426	+ case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
	2427	+ od_table->OverDriveTable.FanZeroRpmEnable =
	2428	+ boot_overdrive_table->OverDriveTable.FanZeroRpmEnable;
	2429	+ od_table->OverDriveTable.FeatureCtrlMask \|= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
	2430	+ break;
2399	2431	case PP_OD_EDIT_ACOUSTIC_LIMIT:
2400	2432	od_table->OverDriveTable.AcousticLimitRpmThreshold =
2401	2433	boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
@@ -2678,6 +2710,27 @@ static int smu_v14_0_2_od_edit_dpm_table(struct smu_context *smu, · 276 unmodified lines
2678	2710	od_table->OverDriveTable.FeatureCtrlMask \|= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2679	2711	break;
2680	2712
	2713	+ case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
	2714	+ if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
	2715	+ dev_warn(adev->dev, "Zero RPM setting not supported!\n");
	2716	+ return -ENOTSUPP;
	2717	+ }
	2718	+
	2719	+ smu_v14_0_2_get_od_setting_limits(smu,
	2720	+ PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
	2721	+ &minimum,
	2722	+ &maximum);
	2723	+ if (input[0] < minimum \|\|
	2724	+ input[0] > maximum) {
	2725	+ dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n",
	2726	+ input[0], minimum, maximum);
	2727	+ return -EINVAL;
	2728	+ }
	2729	+
	2730	+ od_table->OverDriveTable.FanZeroRpmEnable = input[0];
	2731	+ od_table->OverDriveTable.FeatureCtrlMask \|= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
	2732	+ break;
	2733	+
2681	2734	case PP_OD_RESTORE_DEFAULT_TABLE:
2682	2735	if (size == 1) {
2683	2736	ret = smu_v14_0_2_od_restore_table_single(smu, input[0]);

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c+3−0

@@ -1083,6 +1083,9 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev) · 1082 unmodified lines
1083	1083	case METRICS_VERSION(1, 7):
1084	1084	structure_size = sizeof(struct gpu_metrics_v1_7);
1085	1085	break;
	1086	+ case METRICS_VERSION(1, 8):
	1087	+ structure_size = sizeof(struct gpu_metrics_v1_8);
	1088	+ break;
1086	1089	case METRICS_VERSION(2, 0):
1087	1090	structure_size = sizeof(struct gpu_metrics_v2_0);
1088	1091	break;

drivers/gpu/drm/bridge/Kconfig+7−6

@@ -91,12 +91,13 @@ config DRM_FSL_LDB · 90 unmodified lines
91	91	Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
92	92
93	93	config DRM_I2C_NXP_TDA998X
94		− tristate "NXP Semiconductors TDA998X HDMI encoder"
95		− default m if DRM_TILCDC
96		− select CEC_CORE if CEC_NOTIFIER
97		− select SND_SOC_HDMI_CODEC if SND_SOC
98		− help
99		− Support for NXP Semiconductors TDA998X HDMI encoders.
	94	+ tristate "NXP Semiconductors TDA998X HDMI encoder"
	95	+ default m if DRM_TILCDC
	96	+ select CEC_CORE if CEC_NOTIFIER
	97	+ select DRM_KMS_HELPER
	98	+ select SND_SOC_HDMI_CODEC if SND_SOC
	99	+ help
	100	+ Support for NXP Semiconductors TDA998X HDMI encoders.
100	101
101	102	config DRM_ITE_IT6263
102	103	tristate "ITE IT6263 LVDS/HDMI bridge"

drivers/gpu/drm/i915/display/intel_fbdev.h+2−0

@@ -6,6 +6,8 @@ · 5 unmodified lines
6	6	#ifndef __INTEL_FBDEV_H__
7	7	#define __INTEL_FBDEV_H__
8	8
	9	+#include <linux/types.h>
	10	+
9	11	struct drm_fb_helper;
10	12	struct drm_fb_helper_surface_size;
11	13	struct drm_i915_private;

drivers/gpu/drm/i915/display/skl_watermark.c+4−1

@@ -2314,6 +2314,7 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) · 2313 unmodified lines
2314	2314	static int
2315	2315	dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
2316	2316	{
	2317	+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2317	2318	const struct intel_crtc_scaler_state *scaler_state =
2318	2319	&crtc_state->scaler_state;
2319	2320	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
@@ -2323,7 +2324,9 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state) · 3 unmodified lines
2323	2324	crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
2324	2325	u32 dsc_prefill_latency = 0;
2325	2326
2326		− if (!crtc_state->dsc.compression_enable \|\| !num_scaler_users)
	2327	+ if (!crtc_state->dsc.compression_enable \|\|
	2328	+ !num_scaler_users \|\|
	2329	+ num_scaler_users > crtc->num_scalers)
2327	2330	return dsc_prefill_latency;
2328	2331
2329	2332	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);

drivers/gpu/drm/xe/Kconfig+1−1

@@ -53,7 +53,7 @@ config DRM_XE · 52 unmodified lines
53	53	config DRM_XE_DISPLAY
54	54	bool "Enable display support"
55	55	depends on DRM_XE && DRM_XE=m && HAS_IOPORT
56		− select FB_IOMEM_HELPERS
	56	+ select FB_IOMEM_HELPERS if DRM_FBDEV_EMULATION
57	57	select I2C
58	58	select I2C_ALGOBIT
59	59	default y

drivers/gpu/drm/xe/regs/xe_engine_regs.h+4−0

@@ -130,6 +130,10 @@ · 129 unmodified lines
130	130	#define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234)
131	131	#define RING_EXECLIST_STATUS_HI(base) XE_REG((base) + 0x234 + 4)
132	132
	133	+#define RING_IDLEDLY(base) XE_REG((base) + 0x23c)
	134	+#define INHIBIT_SWITCH_UNTIL_PREEMPTED REG_BIT(31)
	135	+#define IDLE_DELAY REG_GENMASK(20, 0)
	136	+
133	137	#define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
134	138	#define CTX_CTRL_PXP_ENABLE REG_BIT(10)
135	139	#define CTX_CTRL_OAC_CONTEXT_ENABLE REG_BIT(8)

drivers/gpu/drm/xe/xe_device.c+15−2

@@ -53,6 +53,7 @@ · 52 unmodified lines
53	53	#include "xe_pxp.h"
54	54	#include "xe_query.h"
55	55	#include "xe_shrinker.h"
	56	+#include "xe_survivability_mode.h"
56	57	#include "xe_sriov.h"
57	58	#include "xe_tile.h"
58	59	#include "xe_ttm_stolen_mgr.h"
@@ -705,8 +706,20 @@ int xe_device_probe_early(struct xe_device *xe) · 646 unmodified lines
705	706	sriov_update_device_info(xe);
706	707
707	708	err = xe_pcode_probe_early(xe);
708		− if (err)
709		− return err;
	709	+ if (err) {
	710	+ int save_err = err;
	711	+
	712	+ /*
	713	+ * Try to leave device in survivability mode if device is
	714	+ * possible, but still return the previous error for error
	715	+ * propagation
	716	+ */
	717	+ err = xe_survivability_mode_enable(xe);
	718	+ if (err)
	719	+ return err;
	720	+
	721	+ return save_err;
	722	+ }
710	723
711	724	err = wait_for_lmem_ready(xe);
712	725	if (err)

drivers/gpu/drm/xe/xe_eu_stall.c+1−7

@@ -222,13 +222,7 @@ int xe_eu_stall_init(struct xe_gt *gt) · 221 unmodified lines
222	222	goto exit_free;
223	223	}
224	224
225		− ret = devm_add_action_or_reset(xe->drm.dev, xe_eu_stall_fini, gt);
226		− if (ret)
227		− goto exit_destroy;
228		−
229		− return 0;
230		−exit_destroy:
231		− destroy_workqueue(gt->eu_stall->buf_ptr_poll_wq);
	225	+ return devm_add_action_or_reset(xe->drm.dev, xe_eu_stall_fini, gt);
232	226	exit_free:
233	227	mutex_destroy(&gt->eu_stall->stream_lock);
234	228	kfree(gt->eu_stall);

drivers/gpu/drm/xe/xe_gt_clock.c+38−16

@@ -16,35 +16,47 @@ · 15 unmodified lines
16	16	#include "xe_macros.h"
17	17	#include "xe_mmio.h"
18	18
19		−static u32 get_crystal_clock_freq(u32 rpm_config_reg)
	19	+#define f19_2_mhz 19200000
	20	+#define f24_mhz 24000000
	21	+#define f25_mhz 25000000
	22	+#define f38_4_mhz 38400000
	23	+#define ts_base_83 83333
	24	+#define ts_base_52 52083
	25	+#define ts_base_80 80000
	26	+
	27	+static void read_crystal_clock(struct xe_gt gt, u32 rpm_config_reg, u32 freq,
	28	+ u32 *timestamp_base)
20	29	{
21		− const u32 f19_2_mhz = 19200000;
22		− const u32 f24_mhz = 24000000;
23		− const u32 f25_mhz = 25000000;
24		− const u32 f38_4_mhz = 38400000;
25	30	u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,
26	31	rpm_config_reg);
27	32
28	33	switch (crystal_clock) {
29	34	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
30		− return f24_mhz;
	35	+ *freq = f24_mhz;
	36	+ *timestamp_base = ts_base_83;
	37	+ return;
31	38	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
32		− return f19_2_mhz;
	39	+ *freq = f19_2_mhz;
	40	+ *timestamp_base = ts_base_52;
	41	+ return;
33	42	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
34		− return f38_4_mhz;
	43	+ *freq = f38_4_mhz;
	44	+ *timestamp_base = ts_base_52;
	45	+ return;
35	46	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
36		− return f25_mhz;
	47	+ *freq = f25_mhz;
	48	+ *timestamp_base = ts_base_80;
	49	+ return;
37	50	default:
38		− XE_WARN_ON("NOT_POSSIBLE");
39		− return 0;
	51	+ xe_gt_warn(gt, "Invalid crystal clock frequency: %u", crystal_clock);
	52	+ *freq = 0;
	53	+ *timestamp_base = 0;
	54	+ return;
40	55	}
41	56	}
42	57
43		−int xe_gt_clock_init(struct xe_gt *gt)
	58	+static void check_ctc_mode(struct xe_gt *gt)
44	59	{
45		− u32 c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);
46		− u32 freq = 0;
47		−
48	60	/*
49	61	* CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
50	62	* platforms. In theory it could be a valid setting for pre-Xe2
@@ -57,8 +69,18 @@ int xe_gt_clock_init(struct xe_gt *gt) · 6 unmodified lines
57	69	*/
58	70	if (xe_mmio_read32(&gt->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC)
59	71	xe_gt_warn(gt, "CTC_MODE[0] is set; this is unexpected and undocumented\n");
	72	+}
	73	+
	74	+int xe_gt_clock_init(struct xe_gt *gt)
	75	+{
	76	+ u32 freq;
	77	+ u32 c0;
	78	+
	79	+ if (!IS_SRIOV_VF(gt_to_xe(gt)))
	80	+ check_ctc_mode(gt);
60	81
61		− freq = get_crystal_clock_freq(c0);
	82	+ c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);
	83	+ read_crystal_clock(gt, c0, &freq, &gt->info.timestamp_base);
62	84
63	85	/*
64	86	* Now figure out how the command stream's timestamp

drivers/gpu/drm/xe/xe_gt_types.h+2−0

@@ -121,6 +121,8 @@ struct xe_gt { · 120 unmodified lines
121	121	enum xe_gt_type type;
122	122	/** @info.reference_clock: clock frequency */
123	123	u32 reference_clock;
	124	+ /** @info.timestamp_base: GT timestamp base */
	125	+ u32 timestamp_base;
124	126	/**
125	127	* @info.engine_mask: mask of engines present on GT. Some of
126	128	* them may be reserved in runtime and not available for user.

drivers/gpu/drm/xe/xe_hw_engine.c+33−0

@@ -8,7 +8,9 @@ · 7 unmodified lines
8	8	#include <linux/nospec.h>
9	9
10	10	#include <drm/drm_managed.h>
	11	+#include <drm/drm_print.h>
11	12	#include <uapi/drm/xe_drm.h>
	13	+#include <generated/xe_wa_oob.h>
12	14
13	15	#include "regs/xe_engine_regs.h"
14	16	#include "regs/xe_gt_regs.h"
@@ -21,6 +23,7 @@ · 6 unmodified lines
21	23	#include "xe_gsc.h"
22	24	#include "xe_gt.h"
23	25	#include "xe_gt_ccs_mode.h"
	26	+#include "xe_gt_clock.h"
24	27	#include "xe_gt_printk.h"
25	28	#include "xe_gt_mcr.h"
26	29	#include "xe_gt_topology.h"
@@ -564,6 +567,33 @@ static void hw_engine_init_early(struct xe_gt gt, struct xe_hw_engine hwe, · 537 unmodified lines
564	567	xe_reg_whitelist_process_engine(hwe);
565	568	}
566	569
	570	+static void adjust_idledly(struct xe_hw_engine *hwe)
	571	+{
	572	+ struct xe_gt *gt = hwe->gt;
	573	+ u32 idledly, maxcnt;
	574	+ u32 idledly_units_ps = 8 * gt->info.timestamp_base;
	575	+ u32 maxcnt_units_ns = 640;
	576	+ bool inhibit_switch = 0;
	577	+
	578	+ if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_WA(gt, 16023105232)) {
	579	+ idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));
	580	+ maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
	581	+
	582	+ inhibit_switch = idledly & INHIBIT_SWITCH_UNTIL_PREEMPTED;
	583	+ idledly = REG_FIELD_GET(IDLE_DELAY, idledly);
	584	+ idledly = DIV_ROUND_CLOSEST(idledly * idledly_units_ps, 1000);
	585	+ maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
	586	+ maxcnt *= maxcnt_units_ns;
	587	+
	588	+ if (xe_gt_WARN_ON(gt, idledly >= maxcnt \|\| inhibit_switch)) {
	589	+ idledly = DIV_ROUND_CLOSEST(((maxcnt - 1) * maxcnt_units_ns),
	590	+ idledly_units_ps);
	591	+ idledly = DIV_ROUND_CLOSEST(idledly, 1000);
	592	+ xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);
	593	+ }
	594	+ }
	595	+}
	596	+
567	597	static int hw_engine_init(struct xe_gt gt, struct xe_hw_engine hwe,
568	598	enum xe_hw_engine_id id)
569	599	{
@@ -604,6 +634,9 @@ static int hw_engine_init(struct xe_gt gt, struct xe_hw_engine hwe, · 34 unmodified lines
604	634	if (xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY)
605	635	gt->usm.reserved_bcs_instance = hwe->instance;
606	636
	637	+ /* Ensure IDLEDLY is lower than MAXCNT */
	638	+ adjust_idledly(hwe);
	639	+
607	640	return devm_add_action_or_reset(xe->drm.dev, hw_engine_fini, hwe);
608	641
609	642	err_hwsp:

drivers/gpu/drm/xe/xe_pci.c+7−9

@@ -803,16 +803,14 @@ static int xe_pci_probe(struct pci_dev pdev, const struct pci_device_id ent) · 802 unmodified lines
803	803	return err;
804	804
805	805	err = xe_device_probe_early(xe);
806		−
807		− /*
808		− * In Boot Survivability mode, no drm card is exposed and driver is
809		− * loaded with bare minimum to allow for firmware to be flashed through
810		− * mei. If early probe fails, check if survivability mode is flagged by
811		− * HW to be enabled. In that case enable it and return success.
812		− */
813	806	if (err) {
814		− if (xe_survivability_mode_required(xe) &&
815		− xe_survivability_mode_enable(xe))
	807	+ /*
	808	+ * In Boot Survivability mode, no drm card is exposed and driver
	809	+ * is loaded with bare minimum to allow for firmware to be
	810	+ * flashed through mei. If early probe failed, but it managed to
	811	+ * enable survivability mode, return success.
	812	+ */
	813	+ if (xe_survivability_mode_is_enabled(xe))
816	814	return 0;
817	815
818	816	return err;

drivers/gpu/drm/xe/xe_survivability_mode.c+22−9

@@ -155,13 +155,21 @@ static int enable_survivability_mode(struct pci_dev *pdev) · 154 unmodified lines
155	155	if (ret)
156	156	return ret;
157	157
	158	+ /* Make sure xe_heci_gsc_init() knows about survivability mode */
	159	+ survivability->mode = true;
	160	+
158	161	ret = xe_heci_gsc_init(xe);
159		− if (ret)
	162	+ if (ret) {
	163	+ /*
	164	+ * But if it fails, device can't enter survivability
	165	+ * so move it back for correct error handling
	166	+ */
	167	+ survivability->mode = false;
160	168	return ret;
	169	+ }
161	170
162	171	xe_vsec_init(xe);
163	172
164		− survivability->mode = true;
165	173	dev_err(dev, "In Survivability Mode\n");
166	174
167	175	return 0;
@@ -178,15 +186,16 @@ bool xe_survivability_mode_is_enabled(struct xe_device *xe) · 10 unmodified lines
178	186	return xe->survivability.mode;
179	187	}
180	188
181		−/**
182		− * xe_survivability_mode_required - checks if survivability mode is required
183		− * @xe: xe device instance
	189	+/*
	190	+ * survivability_mode_requested - check if it's possible to enable
	191	+ * survivability mode and that was requested by firmware
184	192	*
185		− * This function reads the boot status from Pcode
	193	+ * This function reads the boot status from Pcode.
186	194	*
187		− * Return: true if boot status indicates failure, false otherwise
	195	+ * Return: true if platform support is available and boot status indicates
	196	+ * failure, false otherwise.
188	197	*/
189		−bool xe_survivability_mode_required(struct xe_device *xe)
	198	+static bool survivability_mode_requested(struct xe_device *xe)
190	199	{
191	200	struct xe_survivability *survivability = &xe->survivability;
192	201	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
@@ -208,7 +217,8 @@ bool xe_survivability_mode_required(struct xe_device *xe) · 15 unmodified lines
208	217	*
209	218	* Initialize survivability information and enable survivability mode
210	219	*
211		− * Return: 0 for success, negative error code otherwise.
	220	+ * Return: 0 if survivability mode is enabled or not requested; negative error
	221	+ * code otherwise.
212	222	*/
213	223	int xe_survivability_mode_enable(struct xe_device *xe)
214	224	{
@@ -216,6 +226,9 @@ int xe_survivability_mode_enable(struct xe_device *xe) · 1 unmodified line
216	226	struct xe_survivability_info *info;
217	227	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
218	228
	229	+ if (!survivability_mode_requested(xe))
	230	+ return 0;
	231	+
219	232	survivability->size = MAX_SCRATCH_MMIO;
220	233
221	234	info = devm_kcalloc(xe->drm.dev, survivability->size, sizeof(*info),

drivers/gpu/drm/xe/xe_survivability_mode.h+0−1

@@ -12,6 +12,5 @@ struct xe_device; · 11 unmodified lines
12	12
13	13	int xe_survivability_mode_enable(struct xe_device *xe);
14	14	bool xe_survivability_mode_is_enabled(struct xe_device *xe);
15		−bool xe_survivability_mode_required(struct xe_device *xe);
16	15
17	16	#endif /* _XE_SURVIVABILITY_MODE_H_ */

drivers/gpu/drm/xe/xe_wa.c+6−0

@@ -622,6 +622,12 @@ static const struct xe_rtp_entry_sr engine_was[] = { · 621 unmodified lines
622	622	FUNC(xe_rtp_match_first_render_or_compute)),
623	623	XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
624	624	},
	625	+ { XE_RTP_NAME("16023105232"),
	626	+ XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
	627	+ GRAPHICS_VERSION_RANGE(2001, 3001)),
	628	+ XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
	629	+ XE_RTP_ACTION_FLAG(ENGINE_BASE)))
	630	+ },
625	631	};
626	632
627	633	static const struct xe_rtp_entry_sr lrc_was[] = {

drivers/gpu/drm/xe/xe_wa_oob.rules+2−0

@@ -53,3 +53,5 @@ no_media_l3 MEDIA_VERSION(3000) · 52 unmodified lines
53	53	GRAPHICS_VERSION_RANGE(1270, 1274)
54	54	1508761755 GRAPHICS_VERSION(1255)
55	55	GRAPHICS_VERSION(1260), GRAPHICS_STEP(A0, B0)
	56	+16023105232 GRAPHICS_VERSION_RANGE(2001, 3001)
	57	+ MEDIA_VERSION_RANGE(1301, 3000)

Merge tag 'drm-next-2025-04-05' of https://gitlab.freedesktop.org/drm/kernel

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