History

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson: "This week's arm-soc fixes: - A set of of OMAP patches that we had missed Tony's pull request of: * Reset fix for am43xx * Proper OPP table for omap5 * Fix for SoC detection of one of the DRA7 SoCs * hwmod updates to get SATA and OCP to work on omap5 (drivers merged in 3.16) * ... plus a handful of smaller fixes - sunxi needed to re-add machine specific restart code that was removed in anticipation of a watchdog driver being merged for 3.16, and it didn't make it in. - Marvell fixes for PCIe on SMP and a big-endian fix. - A trivial defconfig update to make my capri test board boot with bcm_defconfig again. ... and a couple of MAINTAINERS updates, one to claim new Keystone drivers that have been merged, and one to merge MXS and i.MX (both Freescale platforms). The largest diffs come from the hwmod code for omap5 and the re-add of the restart code on sunxi. The hwmod stuff is quite late at this point but it slipped through cracks repeatedly while coming up the maintainer chain and only affects the one SoC so risk is low" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: MAINTAINERS: Add few more Keystone drivers MAINTAINERS: merge MXS entry into IMX one ARM: sunxi: Reintroduce the restart code for A10/A20 SoCs ARM: mvebu: fix cpuidle implementation to work on big-endian systems ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup ARM: mvebu: move Armada 375 external abort logic as a quirk ARM: bcm: Fix bcm and multi_v7 defconfigs ARM: dts: dra7-evm: remove interrupt binding ARM: OMAP2+: Fix parser-bug in platform muxing code ARM: DTS: dra7/dra7xx-clocks: ATL related changes ARM: OMAP2+: drop unused function ARM: dts: am43x-epos-evm: Add Missing cpsw-phy-sel for am43x-epos-evm ARM: dts: omap5: Update CPU OPP table as per final production Manual ARM: DRA722: add detection of SoC information ARM: dts: Enable twl4030 off-idle configuration for selected omaps ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods ARM: OMAP2+: hwmod: Change hardreset soc_ops for AM43XX

Linus Torvalds committed 12 years ago

Commit 75bf7572 parents 549f11c bc6aa5624 files · +292 −67Browse files

Unified · Split

24 files
  1. MAINTAINERS +26 −8
  2. arch/arm/boot/dts/am43x-epos-evm.dts +4 −0
  3. arch/arm/boot/dts/dra7.dtsi +11 −1
  4. arch/arm/boot/dts/dra7xx-clocks.dtsi +8 −8
  5. arch/arm/boot/dts/omap3-beagle-xm.dts +6 −0
  6. arch/arm/boot/dts/omap3-evm-common.dtsi +7 −0
  7. arch/arm/boot/dts/omap3-n900.dts +5 −0
  8. arch/arm/boot/dts/omap5.dtsi +0 −1
  9. arch/arm/configs/bcm_defconfig +1 −1
  10. arch/arm/configs/multi_v7_defconfig +2 −1
  11. arch/arm/mach-mvebu/Makefile +1 −1
  12. arch/arm/mach-mvebu/board-v7.c +19 −10
  13. arch/arm/mach-mvebu/pmsu.c +2 −7
  14. arch/arm/mach-mvebu/pmsu_ll.S +25 −0
  15. arch/arm/mach-omap2/Makefile +4 −2
  16. arch/arm/mach-omap2/cm33xx.h +1 −1
  17. arch/arm/mach-omap2/common.h +0 −1
  18. arch/arm/mach-omap2/id.c +12 −0
  19. arch/arm/mach-omap2/mux.c +4 −2
  20. arch/arm/mach-omap2/omap4-common.c +0 −20
  21. arch/arm/mach-omap2/omap_hwmod.c +3 −3
  22. arch/arm/mach-omap2/omap_hwmod_54xx_data.c +73 −0
  23. arch/arm/mach-omap2/soc.h +1 −0
  24. arch/arm/mach-sunxi/sunxi.c +77 −0
MAINTAINERS+26−8
@@ -943,16 +943,10 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) · 942 unmodified lines
943S: Maintained943S: Maintained
944T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git944T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
945F: arch/arm/mach-imx/945F: arch/arm/mach-imx/
946F: arch/arm/mach-mxs/
946F: arch/arm/boot/dts/imx*947F: arch/arm/boot/dts/imx*
947F: arch/arm/configs/imx*_defconfig948F: arch/arm/configs/imx*_defconfig
948 949
949ARM/FREESCALE MXS ARM ARCHITECTURE
950M: Shawn Guo <shawn.guo@linaro.org>
951L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
952S: Maintained
953T: git git://git.linaro.org/people/shawnguo/linux-2.6.git
954F: arch/arm/mach-mxs/
955
956ARM/GLOMATION GESBC9312SX MACHINE SUPPORT950ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
957M: Lennert Buytenhek <kernel@wantstofly.org>951M: Lennert Buytenhek <kernel@wantstofly.org>
958L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)952L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -1052,9 +1046,33 @@ M: Santosh Shilimkar <santosh.shilimkar@ti.com> · 93 unmodified lines
1052L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)1046L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1053S: Maintained1047S: Maintained
1054F: arch/arm/mach-keystone/1048F: arch/arm/mach-keystone/
1055F: drivers/clk/keystone/
1056T: git git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git1049T: git git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
1057 1050
1051ARM/TEXAS INSTRUMENT KEYSTONE CLOCK FRAMEWORK
1052M: Santosh Shilimkar <santosh.shilimkar@ti.com>
1053L: linux-kernel@vger.kernel.org
1054S: Maintained
1055F: drivers/clk/keystone/
1056
1057ARM/TEXAS INSTRUMENT KEYSTONE ClOCKSOURCE
1058M: Santosh Shilimkar <santosh.shilimkar@ti.com>
1059L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1060L: linux-kernel@vger.kernel.org
1061S: Maintained
1062F: drivers/clocksource/timer-keystone.c
1063
1064ARM/TEXAS INSTRUMENT KEYSTONE RESET DRIVER
1065M: Santosh Shilimkar <santosh.shilimkar@ti.com>
1066L: linux-kernel@vger.kernel.org
1067S: Maintained
1068F: drivers/power/reset/keystone-reset.c
1069
1070ARM/TEXAS INSTRUMENT AEMIF/EMIF DRIVERS
1071M: Santosh Shilimkar <santosh.shilimkar@ti.com>
1072L: linux-kernel@vger.kernel.org
1073S: Maintained
1074F: drivers/memory/*emif*
1075
1058ARM/LOGICPD PXA270 MACHINE SUPPORT1076ARM/LOGICPD PXA270 MACHINE SUPPORT
1059M: Lennert Buytenhek <kernel@wantstofly.org>1077M: Lennert Buytenhek <kernel@wantstofly.org>
1060L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)1078L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
arch/arm/boot/dts/am43x-epos-evm.dts+4−0
@@ -319,6 +319,10 @@ · 318 unmodified lines
319 phy-mode = "rmii";319 phy-mode = "rmii";
320};320};
321 321
322&phy_sel {
323 rmii-clock-ext;
324};
325
322&i2c0 {326&i2c0 {
323 status = "okay";327 status = "okay";
324 pinctrl-names = "default";328 pinctrl-names = "default";
arch/arm/boot/dts/dra7.dtsi+11−1
@@ -773,7 +773,6 @@ · 772 unmodified lines
773 clocks = <&qspi_gfclk_div>;773 clocks = <&qspi_gfclk_div>;
774 clock-names = "fck";774 clock-names = "fck";
775 num-cs = <4>;775 num-cs = <4>;
776 interrupts = <0 343 0x4>;
777 status = "disabled";776 status = "disabled";
778 };777 };
779 778
@@ -984,6 +983,17 @@ · 204 unmodified lines
984 #size-cells = <1>;983 #size-cells = <1>;
985 status = "disabled";984 status = "disabled";
986 };985 };
986
987 atl: atl@4843c000 {
988 compatible = "ti,dra7-atl";
989 reg = <0x4843c000 0x3ff>;
990 ti,hwmods = "atl";
991 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
992 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
993 clocks = <&atl_gfclk_mux>;
994 clock-names = "fck";
995 status = "disabled";
996 };
987 };997 };
988};998};
989 999
arch/arm/boot/dts/dra7xx-clocks.dtsi+8−8
@@ -10,26 +10,26 @@ · 9 unmodified lines
10&cm_core_aon_clocks {10&cm_core_aon_clocks {
11 atl_clkin0_ck: atl_clkin0_ck {11 atl_clkin0_ck: atl_clkin0_ck {
12 #clock-cells = <0>;12 #clock-cells = <0>;
13 compatible = "fixed-clock";13 compatible = "ti,dra7-atl-clock";
14 clock-frequency = <0>;14 clocks = <&atl_gfclk_mux>;
15 };15 };
16 16
17 atl_clkin1_ck: atl_clkin1_ck {17 atl_clkin1_ck: atl_clkin1_ck {
18 #clock-cells = <0>;18 #clock-cells = <0>;
19 compatible = "fixed-clock";19 compatible = "ti,dra7-atl-clock";
20 clock-frequency = <0>;20 clocks = <&atl_gfclk_mux>;
21 };21 };
22 22
23 atl_clkin2_ck: atl_clkin2_ck {23 atl_clkin2_ck: atl_clkin2_ck {
24 #clock-cells = <0>;24 #clock-cells = <0>;
25 compatible = "fixed-clock";25 compatible = "ti,dra7-atl-clock";
26 clock-frequency = <0>;26 clocks = <&atl_gfclk_mux>;
27 };27 };
28 28
29 atl_clkin3_ck: atl_clkin3_ck {29 atl_clkin3_ck: atl_clkin3_ck {
30 #clock-cells = <0>;30 #clock-cells = <0>;
31 compatible = "fixed-clock";31 compatible = "ti,dra7-atl-clock";
32 clock-frequency = <0>;32 clocks = <&atl_gfclk_mux>;
33 };33 };
34 34
35 hdmi_clkin_ck: hdmi_clkin_ck {35 hdmi_clkin_ck: hdmi_clkin_ck {
arch/arm/boot/dts/omap3-beagle-xm.dts+6−0
@@ -251,6 +251,11 @@ · 250 unmodified lines
251 codec {251 codec {
252 };252 };
253 };253 };
254
255 twl_power: power {
256 compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off";
257 ti,use_poweroff;
258 };
254 };259 };
255};260};
256 261
@@ -301,6 +306,7 @@ · 44 unmodified lines
301};306};
302 307
303&uart3 {308&uart3 {
309 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
304 pinctrl-names = "default";310 pinctrl-names = "default";
305 pinctrl-0 = <&uart3_pins>;311 pinctrl-0 = <&uart3_pins>;
306};312};
arch/arm/boot/dts/omap3-evm-common.dtsi+7−0
@@ -50,6 +50,13 @@ · 49 unmodified lines
50 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;50 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;
51};51};
52 52
53&twl {
54 twl_power: power {
55 compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle";
56 ti,use_poweroff;
57 };
58};
59
53&i2c2 {60&i2c2 {
54 clock-frequency = <400000>;61 clock-frequency = <400000>;
55};62};
arch/arm/boot/dts/omap3-n900.dts+5−0
@@ -351,6 +351,11 @@ · 350 unmodified lines
351 compatible = "ti,twl4030-audio";351 compatible = "ti,twl4030-audio";
352 ti,enable-vibra = <1>;352 ti,enable-vibra = <1>;
353 };353 };
354
355 twl_power: power {
356 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
357 ti,use_poweroff;
358 };
354};359};
355 360
356&twl_keypad {361&twl_keypad {
arch/arm/boot/dts/omap5.dtsi+0−1
@@ -45,7 +45,6 @@ · 44 unmodified lines
45 45
46 operating-points = <46 operating-points = <
47 /* kHz uV */47 /* kHz uV */
48 500000 880000
49 1000000 106000048 1000000 1060000
50 1500000 125000049 1500000 1250000
51 >;50 >;
arch/arm/configs/bcm_defconfig+1−1
@@ -94,10 +94,10 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y · 93 unmodified lines
94CONFIG_BACKLIGHT_PWM=y94CONFIG_BACKLIGHT_PWM=y
95# CONFIG_USB_SUPPORT is not set95# CONFIG_USB_SUPPORT is not set
96CONFIG_MMC=y96CONFIG_MMC=y
97CONFIG_MMC_UNSAFE_RESUME=y
98CONFIG_MMC_BLOCK_MINORS=3297CONFIG_MMC_BLOCK_MINORS=32
99CONFIG_MMC_TEST=y98CONFIG_MMC_TEST=y
100CONFIG_MMC_SDHCI=y99CONFIG_MMC_SDHCI=y
100CONFIG_MMC_SDHCI_PLTFM=y
101CONFIG_MMC_SDHCI_BCM_KONA=y101CONFIG_MMC_SDHCI_BCM_KONA=y
102CONFIG_NEW_LEDS=y102CONFIG_NEW_LEDS=y
103CONFIG_LEDS_CLASS=y103CONFIG_LEDS_CLASS=y
arch/arm/configs/multi_v7_defconfig+2−1
@@ -223,12 +223,12 @@ CONFIG_POWER_RESET_GPIO=y · 222 unmodified lines
223CONFIG_POWER_RESET_SUN6I=y223CONFIG_POWER_RESET_SUN6I=y
224CONFIG_SENSORS_LM90=y224CONFIG_SENSORS_LM90=y
225CONFIG_THERMAL=y225CONFIG_THERMAL=y
226CONFIG_DOVE_THERMAL=y
227CONFIG_ARMADA_THERMAL=y226CONFIG_ARMADA_THERMAL=y
228CONFIG_WATCHDOG=y227CONFIG_WATCHDOG=y
229CONFIG_ORION_WATCHDOG=y228CONFIG_ORION_WATCHDOG=y
230CONFIG_SUNXI_WATCHDOG=y229CONFIG_SUNXI_WATCHDOG=y
231CONFIG_MFD_AS3722=y230CONFIG_MFD_AS3722=y
231CONFIG_MFD_BCM590XX=y
232CONFIG_MFD_CROS_EC=y232CONFIG_MFD_CROS_EC=y
233CONFIG_MFD_CROS_EC_SPI=y233CONFIG_MFD_CROS_EC_SPI=y
234CONFIG_MFD_MAX8907=y234CONFIG_MFD_MAX8907=y
@@ -240,6 +240,7 @@ CONFIG_MFD_TPS65910=y · 5 unmodified lines
240CONFIG_REGULATOR_VIRTUAL_CONSUMER=y240CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
241CONFIG_REGULATOR_AB8500=y241CONFIG_REGULATOR_AB8500=y
242CONFIG_REGULATOR_AS3722=y242CONFIG_REGULATOR_AS3722=y
243CONFIG_REGULATOR_BCM590XX=y
243CONFIG_REGULATOR_GPIO=y244CONFIG_REGULATOR_GPIO=y
244CONFIG_REGULATOR_MAX8907=y245CONFIG_REGULATOR_MAX8907=y
245CONFIG_REGULATOR_PALMAS=y246CONFIG_REGULATOR_PALMAS=y
arch/arm/mach-mvebu/Makefile+1−1
@@ -7,7 +7,7 @@ CFLAGS_pmsu.o := -march=armv7-a · 6 unmodified lines
7obj-y += system-controller.o mvebu-soc-id.o7obj-y += system-controller.o mvebu-soc-id.o
8 8
9ifeq ($(CONFIG_MACH_MVEBU_V7),y)9ifeq ($(CONFIG_MACH_MVEBU_V7),y)
10obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o10obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o
11obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o11obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
12obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o12obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
13endif13endif
arch/arm/mach-mvebu/board-v7.c+19−10
@@ -23,6 +23,7 @@ · 22 unmodified lines
23#include <linux/mbus.h>23#include <linux/mbus.h>
24#include <linux/signal.h>24#include <linux/signal.h>
25#include <linux/slab.h>25#include <linux/slab.h>
26#include <linux/irqchip.h>
26#include <asm/hardware/cache-l2x0.h>27#include <asm/hardware/cache-l2x0.h>
27#include <asm/mach/arch.h>28#include <asm/mach/arch.h>
28#include <asm/mach/map.h>29#include <asm/mach/map.h>
@@ -71,17 +72,23 @@ static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr, · 42 unmodified lines
71 return 1;72 return 1;
72}73}
73 74
74static void __init mvebu_timer_and_clk_init(void)75static void __init mvebu_init_irq(void)
75{76{
76 of_clk_init(NULL);77 irqchip_init();
77 clocksource_of_init();
78 mvebu_scu_enable();78 mvebu_scu_enable();
79 coherency_init();79 coherency_init();
80 BUG_ON(mvebu_mbus_dt_init(coherency_available()));80 BUG_ON(mvebu_mbus_dt_init(coherency_available()));
81}
82
83static void __init external_abort_quirk(void)
84{
85 u32 dev, rev;
81 86
82 if (of_machine_is_compatible("marvell,armada375"))87 if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
83 hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,88 return;
84 "imprecise external abort");89
90 hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
91 "imprecise external abort");
85}92}
86 93
87static void __init i2c_quirk(void)94static void __init i2c_quirk(void)
@@ -169,8 +176,10 @@ static void __init mvebu_dt_init(void) · 81 unmodified lines
169{176{
170 if (of_machine_is_compatible("plathome,openblocks-ax3-4"))177 if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
171 i2c_quirk();178 i2c_quirk();
172 if (of_machine_is_compatible("marvell,a375-db"))179 if (of_machine_is_compatible("marvell,a375-db")) {
180 external_abort_quirk();
173 thermal_quirk();181 thermal_quirk();
182 }
174 183
175 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);184 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
176}185}
@@ -185,7 +194,7 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)") · 8 unmodified lines
185 .l2c_aux_mask = ~0,194 .l2c_aux_mask = ~0,
186 .smp = smp_ops(armada_xp_smp_ops),195 .smp = smp_ops(armada_xp_smp_ops),
187 .init_machine = mvebu_dt_init,196 .init_machine = mvebu_dt_init,
188 .init_time = mvebu_timer_and_clk_init,197 .init_irq = mvebu_init_irq,
189 .restart = mvebu_restart,198 .restart = mvebu_restart,
190 .dt_compat = armada_370_xp_dt_compat,199 .dt_compat = armada_370_xp_dt_compat,
191MACHINE_END200MACHINE_END
@@ -198,7 +207,7 @@ static const char * const armada_375_dt_compat[] = { · 6 unmodified lines
198DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")207DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
199 .l2c_aux_val = 0,208 .l2c_aux_val = 0,
200 .l2c_aux_mask = ~0,209 .l2c_aux_mask = ~0,
201 .init_time = mvebu_timer_and_clk_init,210 .init_irq = mvebu_init_irq,
202 .init_machine = mvebu_dt_init,211 .init_machine = mvebu_dt_init,
203 .restart = mvebu_restart,212 .restart = mvebu_restart,
204 .dt_compat = armada_375_dt_compat,213 .dt_compat = armada_375_dt_compat,
@@ -213,7 +222,7 @@ static const char * const armada_38x_dt_compat[] = { · 8 unmodified lines
213DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")222DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
214 .l2c_aux_val = 0,223 .l2c_aux_val = 0,
215 .l2c_aux_mask = ~0,224 .l2c_aux_mask = ~0,
216 .init_time = mvebu_timer_and_clk_init,225 .init_irq = mvebu_init_irq,
217 .restart = mvebu_restart,226 .restart = mvebu_restart,
218 .dt_compat = armada_38x_dt_compat,227 .dt_compat = armada_38x_dt_compat,
219MACHINE_END228MACHINE_END
arch/arm/mach-mvebu/pmsu.c+2−7
@@ -66,6 +66,8 @@ static void __iomem *pmsu_mp_base; · 65 unmodified lines
66extern void ll_disable_coherency(void);66extern void ll_disable_coherency(void);
67extern void ll_enable_coherency(void);67extern void ll_enable_coherency(void);
68 68
69extern void armada_370_xp_cpu_resume(void);
70
69static struct platform_device armada_xp_cpuidle_device = {71static struct platform_device armada_xp_cpuidle_device = {
70 .name = "cpuidle-armada-370-xp",72 .name = "cpuidle-armada-370-xp",
71};73};
@@ -140,13 +142,6 @@ static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void) · 68 unmodified lines
140 writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);142 writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
141}143}
142 144
143static void armada_370_xp_cpu_resume(void)
144{
145 asm volatile("bl ll_add_cpu_to_smp_group\n\t"
146 "bl ll_enable_coherency\n\t"
147 "b cpu_resume\n\t");
148}
149
150/* No locking is needed because we only access per-CPU registers */145/* No locking is needed because we only access per-CPU registers */
151void armada_370_xp_pmsu_idle_prepare(bool deepidle)146void armada_370_xp_pmsu_idle_prepare(bool deepidle)
152{147{
arch/arm/mach-mvebu/pmsu_ll.S+25−0
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2014 Marvell
3 *
4 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
5 * Gregory Clement <gregory.clement@free-electrons.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14
15/*
16 * This is the entry point through which CPUs exiting cpuidle deep
17 * idle state are going.
18 */
19ENTRY(armada_370_xp_cpu_resume)
20ARM_BE8(setend be ) @ go BE8 if entered LE
21 bl ll_add_cpu_to_smp_group
22 bl ll_enable_coherency
23 b cpu_resume
24ENDPROC(armada_370_xp_cpu_resume)
25
arch/arm/mach-omap2/Makefile+4−2
@@ -110,14 +110,16 @@ obj-y += prm_common.o cm_common.o · 109 unmodified lines
110obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o110obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
111obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o111obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
112obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o112obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
113obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
114omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \113omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
115 prcm_mpu44xx.o prminst44xx.o \114 prcm_mpu44xx.o prminst44xx.o \
116 vc44xx_data.o vp44xx_data.o115 vc44xx_data.o vp44xx_data.o
117obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)116obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
118obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)117obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
119obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)118obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
120obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common)119am33xx-43xx-prcm-common += prm33xx.o cm33xx.o
120obj-$(CONFIG_SOC_AM33XX) += $(am33xx-43xx-prcm-common)
121obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
122 $(am33xx-43xx-prcm-common)
121 123
122# OMAP voltage domains124# OMAP voltage domains
123voltagedomain-common := voltage.o vc.o vp.o125voltagedomain-common := voltage.o vc.o vp.o
arch/arm/mach-omap2/cm33xx.h+1−1
@@ -380,7 +380,7 @@ void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs); · 379 unmodified lines
380void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);380void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
381void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);381void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
382 382
383#ifdef CONFIG_SOC_AM33XX383#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
384extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,384extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
385 u16 clkctrl_offs);385 u16 clkctrl_offs);
386extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,386extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
arch/arm/mach-omap2/common.h+0−1
@@ -248,7 +248,6 @@ static inline void __iomem *omap4_get_scu_base(void) · 247 unmodified lines
248}248}
249#endif249#endif
250 250
251extern void __init gic_init_irq(void);
252extern void gic_dist_disable(void);251extern void gic_dist_disable(void);
253extern void gic_dist_enable(void);252extern void gic_dist_enable(void);
254extern bool gic_dist_disabled(void);253extern bool gic_dist_disabled(void);
arch/arm/mach-omap2/id.c+12−0
@@ -649,6 +649,18 @@ void __init dra7xxx_check_revision(void) · 648 unmodified lines
649 }649 }
650 break;650 break;
651 651
652 case 0xb9bc:
653 switch (rev) {
654 case 0:
655 omap_revision = DRA722_REV_ES1_0;
656 break;
657 default:
658 /* If we have no new revisions */
659 omap_revision = DRA722_REV_ES1_0;
660 break;
661 }
662 break;
663
652 default:664 default:
653 /* Unknown default to latest silicon rev as default*/665 /* Unknown default to latest silicon rev as default*/
654 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",666 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",
arch/arm/mach-omap2/mux.c+4−2
@@ -183,8 +183,10 @@ static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition, · 182 unmodified lines
183 m0_entry = mux->muxnames[0];183 m0_entry = mux->muxnames[0];
184 184
185 /* First check for full name in mode0.muxmode format */185 /* First check for full name in mode0.muxmode format */
186 if (mode0_len && strncmp(muxname, m0_entry, mode0_len))186 if (mode0_len)
187 continue;187 if (strncmp(muxname, m0_entry, mode0_len) ||
188 (strlen(m0_entry) != mode0_len))
189 continue;
188 190
189 /* Then check for muxmode only */191 /* Then check for muxmode only */
190 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {192 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
arch/arm/mach-omap2/omap4-common.c+0−20
@@ -102,26 +102,6 @@ void __init omap_barriers_init(void) · 101 unmodified lines
102{}102{}
103#endif103#endif
104 104
105void __init gic_init_irq(void)
106{
107 void __iomem *omap_irq_base;
108
109 /* Static mapping, never released */
110 gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
111 BUG_ON(!gic_dist_base_addr);
112
113 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
114 BUG_ON(!twd_base);
115
116 /* Static mapping, never released */
117 omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
118 BUG_ON(!omap_irq_base);
119
120 omap_wakeupgen_init();
121
122 gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
123}
124
125void gic_dist_disable(void)105void gic_dist_disable(void)
126{106{
127 if (gic_dist_base_addr)107 if (gic_dist_base_addr)
arch/arm/mach-omap2/omap_hwmod.c+3−3
@@ -4251,9 +4251,9 @@ void __init omap_hwmod_init(void) · 4250 unmodified lines
4251 soc_ops.enable_module = _omap4_enable_module;4251 soc_ops.enable_module = _omap4_enable_module;
4252 soc_ops.disable_module = _omap4_disable_module;4252 soc_ops.disable_module = _omap4_disable_module;
4253 soc_ops.wait_target_ready = _omap4_wait_target_ready;4253 soc_ops.wait_target_ready = _omap4_wait_target_ready;
4254 soc_ops.assert_hardreset = _omap4_assert_hardreset;4254 soc_ops.assert_hardreset = _am33xx_assert_hardreset;
4255 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;4255 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
4256 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;4256 soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
4257 soc_ops.init_clkdm = _init_clkdm;4257 soc_ops.init_clkdm = _init_clkdm;
4258 } else if (soc_is_am33xx()) {4258 } else if (soc_is_am33xx()) {
4259 soc_ops.enable_module = _am33xx_enable_module;4259 soc_ops.enable_module = _am33xx_enable_module;
arch/arm/mach-omap2/omap_hwmod_54xx_data.c+73−0
@@ -2020,6 +2020,77 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = { · 2019 unmodified lines
2020 },2020 },
2021};2021};
2022 2022
2023/*
2024 * 'ocp2scp' class
2025 * bridge to transform ocp interface protocol to scp (serial control port)
2026 * protocol
2027 */
2028/* ocp2scp3 */
2029static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2030/* l4_cfg -> ocp2scp3 */
2031static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2032 .master = &omap54xx_l4_cfg_hwmod,
2033 .slave = &omap54xx_ocp2scp3_hwmod,
2034 .clk = "l4_root_clk_div",
2035 .user = OCP_USER_MPU | OCP_USER_SDMA,
2036};
2037
2038static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2039 .name = "ocp2scp3",
2040 .class = &omap54xx_ocp2scp_hwmod_class,
2041 .clkdm_name = "l3init_clkdm",
2042 .prcm = {
2043 .omap4 = {
2044 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2045 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2046 .modulemode = MODULEMODE_HWCTRL,
2047 },
2048 },
2049};
2050
2051/*
2052 * 'sata' class
2053 * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
2054 */
2055
2056static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2057 .sysc_offs = 0x0000,
2058 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2059 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2060 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2061 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2062 .sysc_fields = &omap_hwmod_sysc_type2,
2063};
2064
2065static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2066 .name = "sata",
2067 .sysc = &omap54xx_sata_sysc,
2068};
2069
2070/* sata */
2071static struct omap_hwmod omap54xx_sata_hwmod = {
2072 .name = "sata",
2073 .class = &omap54xx_sata_hwmod_class,
2074 .clkdm_name = "l3init_clkdm",
2075 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2076 .main_clk = "func_48m_fclk",
2077 .mpu_rt_idx = 1,
2078 .prcm = {
2079 .omap4 = {
2080 .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2081 .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2082 .modulemode = MODULEMODE_SWCTRL,
2083 },
2084 },
2085};
2086
2087/* l4_cfg -> sata */
2088static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
2089 .master = &omap54xx_l4_cfg_hwmod,
2090 .slave = &omap54xx_sata_hwmod,
2091 .clk = "l3_iclk_div",
2092 .user = OCP_USER_MPU | OCP_USER_SDMA,
2093};
2023 2094
2024/*2095/*
2025 * Interfaces2096 * Interfaces
@@ -2765,6 +2836,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { · 739 unmodified lines
2765 &omap54xx_l4_cfg__usb_tll_hs,2836 &omap54xx_l4_cfg__usb_tll_hs,
2766 &omap54xx_l4_cfg__usb_otg_ss,2837 &omap54xx_l4_cfg__usb_otg_ss,
2767 &omap54xx_l4_wkup__wd_timer2,2838 &omap54xx_l4_wkup__wd_timer2,
2839 &omap54xx_l4_cfg__ocp2scp3,
2840 &omap54xx_l4_cfg__sata,
2768 NULL,2841 NULL,
2769};2842};
2770 2843
arch/arm/mach-omap2/soc.h+1−0
@@ -462,6 +462,7 @@ IS_OMAP_TYPE(3430, 0x3430) · 461 unmodified lines
462#define DRA7XX_CLASS 0x07000000462#define DRA7XX_CLASS 0x07000000
463#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))463#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
464#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))464#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))
465#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
465 466
466void omap2xxx_check_revision(void);467void omap2xxx_check_revision(void);
467void omap3xxx_check_revision(void);468void omap3xxx_check_revision(void);
arch/arm/mach-sunxi/sunxi.c+77−0
@@ -12,8 +12,81 @@ · 11 unmodified lines
12 12
13#include <linux/clk-provider.h>13#include <linux/clk-provider.h>
14#include <linux/clocksource.h>14#include <linux/clocksource.h>
15#include <linux/delay.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/io.h>
22#include <linux/reboot.h>
15 23
16#include <asm/mach/arch.h>24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/system_misc.h>
27
28#define SUN4I_WATCHDOG_CTRL_REG 0x00
29#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
30#define SUN4I_WATCHDOG_MODE_REG 0x04
31#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
32#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
33
34#define SUN6I_WATCHDOG1_IRQ_REG 0x00
35#define SUN6I_WATCHDOG1_CTRL_REG 0x10
36#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
37#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
38#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
39#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
40#define SUN6I_WATCHDOG1_MODE_REG 0x18
41#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
42
43static void __iomem *wdt_base;
44
45static void sun4i_restart(enum reboot_mode mode, const char *cmd)
46{
47 if (!wdt_base)
48 return;
49
50 /* Enable timer and set reset bit in the watchdog */
51 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
52 wdt_base + SUN4I_WATCHDOG_MODE_REG);
53
54 /*
55 * Restart the watchdog. The default (and lowest) interval
56 * value for the watchdog is 0.5s.
57 */
58 writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
59
60 while (1) {
61 mdelay(5);
62 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
63 wdt_base + SUN4I_WATCHDOG_MODE_REG);
64 }
65}
66
67static struct of_device_id sunxi_restart_ids[] = {
68 { .compatible = "allwinner,sun4i-a10-wdt" },
69 { /*sentinel*/ }
70};
71
72static void sunxi_setup_restart(void)
73{
74 struct device_node *np;
75
76 np = of_find_matching_node(NULL, sunxi_restart_ids);
77 if (WARN(!np, "unable to setup watchdog restart"))
78 return;
79
80 wdt_base = of_iomap(np, 0);
81 WARN(!wdt_base, "failed to map watchdog base address");
82}
83
84static void __init sunxi_dt_init(void)
85{
86 sunxi_setup_restart();
87
88 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
89}
17 90
18static const char * const sunxi_board_dt_compat[] = {91static const char * const sunxi_board_dt_compat[] = {
19 "allwinner,sun4i-a10",92 "allwinner,sun4i-a10",
@@ -23,7 +96,9 @@ static const char * const sunxi_board_dt_compat[] = { · 3 unmodified lines
23};96};
24 97
25DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")98DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
99 .init_machine = sunxi_dt_init,
26 .dt_compat = sunxi_board_dt_compat,100 .dt_compat = sunxi_board_dt_compat,
101 .restart = sun4i_restart,
27MACHINE_END102MACHINE_END
28 103
29static const char * const sun6i_board_dt_compat[] = {104static const char * const sun6i_board_dt_compat[] = {
@@ -51,5 +126,7 @@ static const char * const sun7i_board_dt_compat[] = { · 21 unmodified lines
51};126};
52 127
53DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")128DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
129 .init_machine = sunxi_dt_init,
54 .dt_compat = sun7i_board_dt_compat,130 .dt_compat = sun7i_board_dt_compat,
131 .restart = sun4i_restart,
55MACHINE_END132MACHINE_END

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