Merge branch 'from-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git

Patches for 4.16 that are dependent on patches sent to 4.15-rc. These are small clean ups for the vmw_pvrdma and i40iw drivers. * 'from-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git: RDMA/vmw_pvrdma: Remove usage of BIT() from UAPI header RDMA/vmw_pvrdma: Use refcount_t instead of atomic_t RDMA/vmw_pvrdma: Use more specific sizeof in kcalloc RDMA/vmw_pvrdma: Clarify QP and CQ is_kernel logic RDMA/vmw_pvrdma: Add UAR SRQ macros in ABI header file i40iw: Change accelerated flag to bool

Jason Gunthorpe committed 8 years ago

Commit 76a895d2 parents efac5ac d2acafe40 files · +422 −226Browse files

Unified · Split

40 files

drivers/infiniband/Kconfig +1 −1
drivers/infiniband/core/cma.c +2 −1
drivers/infiniband/core/device.c +2 −2
drivers/infiniband/core/iwcm.c +1 −1
drivers/infiniband/core/nldev.c +1 −1
drivers/infiniband/core/security.c +54 −6
drivers/infiniband/core/uverbs_cmd.c +8 −2
drivers/infiniband/core/verbs.c +2 −1
drivers/infiniband/hw/cxgb4/cq.c +9 −7
drivers/infiniband/hw/cxgb4/iw_cxgb4.h +0 −2
drivers/infiniband/hw/cxgb4/qp.c +83 −11
drivers/infiniband/hw/cxgb4/t4.h +6 −0
drivers/infiniband/hw/hfi1/hfi.h +0 −1
drivers/infiniband/hw/hfi1/pcie.c +12 −18
drivers/infiniband/hw/hfi1/rc.c +1 −1
drivers/infiniband/hw/hns/hns_roce_alloc.c +0 −23
drivers/infiniband/hw/hns/hns_roce_device.h +1 −3
drivers/infiniband/hw/hns/hns_roce_hem.c +13 −12
drivers/infiniband/hw/hns/hns_roce_hem.h +1 −0
drivers/infiniband/hw/hns/hns_roce_hw_v2.c +15 −7
drivers/infiniband/hw/i40iw/i40iw_cm.c +21 −12
drivers/infiniband/hw/i40iw/i40iw_cm.h +1 −1
drivers/infiniband/hw/i40iw/i40iw_ctrl.c +30 −13
drivers/infiniband/hw/i40iw/i40iw_d.h +4 −2
drivers/infiniband/hw/mlx4/qp.c +19 −7
drivers/infiniband/hw/mlx5/cmd.c +0 −11
drivers/infiniband/hw/mlx5/cmd.h +0 −2
drivers/infiniband/hw/mlx5/main.c +14 −29
drivers/infiniband/hw/mlx5/mlx5_ib.h +4 −0
drivers/infiniband/hw/mlx5/mr.c +1 −0
drivers/infiniband/hw/vmw_pvrdma/pvrdma.h +5 −5
drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c +9 −9
drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c +12 −15
drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c +15 −8
drivers/infiniband/hw/vmw_pvrdma/pvrdma_srq.c +4 −3
drivers/infiniband/ulp/ipoib/ipoib_cm.c +1 −0
drivers/infiniband/ulp/ipoib/ipoib_ib.c +3 −4
drivers/net/ethernet/mellanox/mlx5/core/lag.c +56 −0
include/linux/mlx5/driver.h +4 −0
include/uapi/rdma/vmw_pvrdma-abi.h +7 −5

drivers/infiniband/Kconfig+1−1

@@ -1,6 +1,6 @@
1	1	menuconfig INFINIBAND
2	2	tristate "InfiniBand support"
3		− depends on HAS_IOMEM
	3	+ depends on HAS_IOMEM && HAS_DMA
4	4	depends on NET
5	5	depends on INET
6	6	depends on m \|\| IPV6 != m

drivers/infiniband/core/cma.c+2−1

@@ -801,6 +801,7 @@ struct rdma_cm_id rdma_create_id(struct net net, · 800 unmodified lines
801	801	INIT_LIST_HEAD(&id_priv->mc_list);
802	802	get_random_bytes(&id_priv->seq_num, sizeof id_priv->seq_num);
803	803	id_priv->id.route.addr.dev_addr.net = get_net(net);
	804	+ id_priv->seq_num &= 0x00ffffff;
804	805
805	806	return &id_priv->id;
806	807	}
@@ -4453,7 +4454,7 @@ out: · 3646 unmodified lines
4453	4454	return skb->len;
4454	4455	}
4455	4456
4456		−static const struct rdma_nl_cbs cma_cb_table[] = {
	4457	+static const struct rdma_nl_cbs cma_cb_table[RDMA_NL_RDMA_CM_NUM_OPS] = {
4457	4458	[RDMA_NL_RDMA_CM_ID_STATS] = { .dump = cma_get_id_stats},
4458	4459	};
4459	4460

drivers/infiniband/core/device.c+2−2

@@ -1136,7 +1136,7 @@ struct net_device ib_get_net_dev_by_params(struct ib_device dev, · 1135 unmodified lines
1136	1136	}
1137	1137	EXPORT_SYMBOL(ib_get_net_dev_by_params);
1138	1138
1139		−static const struct rdma_nl_cbs ibnl_ls_cb_table[] = {
	1139	+static const struct rdma_nl_cbs ibnl_ls_cb_table[RDMA_NL_LS_NUM_OPS] = {
1140	1140	[RDMA_NL_LS_OP_RESOLVE] = {
1141	1141	.doit = ib_nl_handle_resolve_resp,
1142	1142	.flags = RDMA_NL_ADMIN_PERM,
@@ -1243,5 +1243,5 @@ static void __exit ib_core_cleanup(void) · 100 unmodified lines
1243	1243
1244	1244	MODULE_ALIAS_RDMA_NETLINK(RDMA_NL_LS, 4);
1245	1245
1246		−module_init(ib_core_init);
	1246	+subsys_initcall(ib_core_init);
1247	1247	module_exit(ib_core_cleanup);

drivers/infiniband/core/iwcm.c+1−1

@@ -80,7 +80,7 @@ const char *__attribute_const__ iwcm_reject_msg(int reason) · 79 unmodified lines
80	80	}
81	81	EXPORT_SYMBOL(iwcm_reject_msg);
82	82
83		−static struct rdma_nl_cbs iwcm_nl_cb_table[] = {
	83	+static struct rdma_nl_cbs iwcm_nl_cb_table[RDMA_NL_IWPM_NUM_OPS] = {
84	84	[RDMA_NL_IWPM_REG_PID] = {.dump = iwpm_register_pid_cb},
85	85	[RDMA_NL_IWPM_ADD_MAPPING] = {.dump = iwpm_add_mapping_cb},
86	86	[RDMA_NL_IWPM_QUERY_MAPPING] = {.dump = iwpm_add_and_query_mapping_cb},

drivers/infiniband/core/nldev.c+1−1

@@ -303,7 +303,7 @@ out: cb->args[0] = idx; · 302 unmodified lines
303	303	return skb->len;
304	304	}
305	305
306		−static const struct rdma_nl_cbs nldev_cb_table[] = {
	306	+static const struct rdma_nl_cbs nldev_cb_table[RDMA_NLDEV_NUM_OPS] = {
307	307	[RDMA_NLDEV_CMD_GET] = {
308	308	.doit = nldev_get_doit,
309	309	.dump = nldev_get_dumpit,

drivers/infiniband/core/security.c+54−6

@@ -386,6 +386,9 @@ int ib_open_shared_qp_security(struct ib_qp qp, struct ib_device dev) · 385 unmodified lines
386	386	if (ret)
387	387	return ret;
388	388
	389	+ if (!qp->qp_sec)
	390	+ return 0;
	391	+
389	392	mutex_lock(&real_qp->qp_sec->mutex);
390	393	ret = check_qp_port_pkey_settings(real_qp->qp_sec->ports_pkeys,
391	394	qp->qp_sec);
@@ -417,8 +420,17 @@ void ib_close_shared_qp_security(struct ib_qp_security *sec) · 25 unmodified lines
417	420
418	421	int ib_create_qp_security(struct ib_qp qp, struct ib_device dev)
419	422	{
	423	+ u8 i = rdma_start_port(dev);
	424	+ bool is_ib = false;
420	425	int ret;
421	426
	427	+ while (i <= rdma_end_port(dev) && !is_ib)
	428	+ is_ib = rdma_protocol_ib(dev, i++);
	429	+
	430	+ /* If this isn't an IB device don't create the security context */
	431	+ if (!is_ib)
	432	+ return 0;
	433	+
422	434	qp->qp_sec = kzalloc(sizeof(*qp->qp_sec), GFP_KERNEL);
423	435	if (!qp->qp_sec)
424	436	return -ENOMEM;
@@ -441,6 +453,10 @@ EXPORT_SYMBOL(ib_create_qp_security); · 16 unmodified lines
441	453
442	454	void ib_destroy_qp_security_begin(struct ib_qp_security *sec)
443	455	{
	456	+ /* Return if not IB */
	457	+ if (!sec)
	458	+ return;
	459	+
444	460	mutex_lock(&sec->mutex);
445	461
446	462	/* Remove the QP from the lists so it won't get added to
@@ -470,6 +486,10 @@ void ib_destroy_qp_security_abort(struct ib_qp_security *sec) · 23 unmodified lines
470	486	int ret;
471	487	int i;
472	488
	489	+ /* Return if not IB */
	490	+ if (!sec)
	491	+ return;
	492	+
473	493	/* If a concurrent cache update is in progress this
474	494	* QP security could be marked for an error state
475	495	* transition. Wait for this to complete.
@@ -505,6 +525,10 @@ void ib_destroy_qp_security_end(struct ib_qp_security *sec) · 29 unmodified lines
505	525	{
506	526	int i;
507	527
	528	+ /* Return if not IB */
	529	+ if (!sec)
	530	+ return;
	531	+
508	532	/* If a concurrent cache update is occurring we must
509	533	* wait until this QP security structure is processed
510	534	* in the QP to error flow before destroying it because
@@ -557,7 +581,7 @@ int ib_security_modify_qp(struct ib_qp *qp, · 46 unmodified lines
557	581	{
558	582	int ret = 0;
559	583	struct ib_ports_pkeys *tmp_pps;
560		− struct ib_ports_pkeys *new_pps;
	584	+ struct ib_ports_pkeys *new_pps = NULL;
561	585	struct ib_qp *real_qp = qp->real_qp;
562	586	bool special_qp = (real_qp->qp_type == IB_QPT_SMI \|\|
563	587	real_qp->qp_type == IB_QPT_GSI \|\|
@@ -565,18 +589,27 @@ int ib_security_modify_qp(struct ib_qp *qp, · 1 unmodified line
565	589	bool pps_change = ((qp_attr_mask & (IB_QP_PKEY_INDEX \| IB_QP_PORT)) \|\|
566	590	(qp_attr_mask & IB_QP_ALT_PATH));
567	591
	592	+ WARN_ONCE((qp_attr_mask & IB_QP_PORT &&
	593	+ rdma_protocol_ib(real_qp->device, qp_attr->port_num) &&
	594	+ !real_qp->qp_sec),
	595	+ "%s: QP security is not initialized for IB QP: %d\n",
	596	+ __func__, real_qp->qp_num);
	597	+
568	598	/* The port/pkey settings are maintained only for the real QP. Open
569	599	* handles on the real QP will be in the shared_qp_list. When
570	600	* enforcing security on the real QP all the shared QPs will be
571	601	* checked as well.
572	602	*/
573	603
574		− if (pps_change && !special_qp) {
	604	+ if (pps_change && !special_qp && real_qp->qp_sec) {
575	605	mutex_lock(&real_qp->qp_sec->mutex);
576	606	new_pps = get_new_pps(real_qp,
577	607	qp_attr,
578	608	qp_attr_mask);
579		−
	609	+ if (!new_pps) {
	610	+ mutex_unlock(&real_qp->qp_sec->mutex);
	611	+ return -ENOMEM;
	612	+ }
580	613	/* Add this QP to the lists for the new port
581	614	* and pkey settings before checking for permission
582	615	* in case there is a concurrent cache update
@@ -600,7 +633,7 @@ int ib_security_modify_qp(struct ib_qp *qp, · 17 unmodified lines
600	633	qp_attr_mask,
601	634	udata);
602	635
603		− if (pps_change && !special_qp) {
	636	+ if (new_pps) {
604	637	/* Clean up the lists and free the appropriate
605	638	* ports_pkeys structure.
606	639	*/
@@ -630,6 +663,9 @@ static int ib_security_pkey_access(struct ib_device *dev, · 23 unmodified lines
630	663	u16 pkey;
631	664	int ret;
632	665
	666	+ if (!rdma_protocol_ib(dev, port_num))
	667	+ return 0;
	668	+
633	669	ret = ib_get_cached_pkey(dev, port_num, pkey_index, &pkey);
634	670	if (ret)
635	671	return ret;
@@ -663,6 +699,9 @@ int ib_mad_agent_security_setup(struct ib_mad_agent *agent, · 27 unmodified lines
663	699	{
664	700	int ret;
665	701
	702	+ if (!rdma_protocol_ib(agent->device, agent->port_num))
	703	+ return 0;
	704	+
666	705	ret = security_ib_alloc_security(&agent->security);
667	706	if (ret)
668	707	return ret;
@@ -688,6 +727,9 @@ int ib_mad_agent_security_setup(struct ib_mad_agent *agent, · 19 unmodified lines
688	727
689	728	void ib_mad_agent_security_cleanup(struct ib_mad_agent *agent)
690	729	{
	730	+ if (!rdma_protocol_ib(agent->device, agent->port_num))
	731	+ return;
	732	+
691	733	security_ib_free_security(agent->security);
692	734	if (agent->lsm_nb_reg)
693	735	unregister_lsm_notifier(&agent->lsm_nb);
@@ -695,8 +737,14 @@ void ib_mad_agent_security_cleanup(struct ib_mad_agent *agent) · 1 unmodified line
695	737
696	738	int ib_mad_enforce_security(struct ib_mad_agent_private *map, u16 pkey_index)
697	739	{
698		− if (map->agent.qp->qp_type == IB_QPT_SMI && !map->agent.smp_allowed)
699		− return -EACCES;
	740	+ if (!rdma_protocol_ib(map->agent.device, map->agent.port_num))
	741	+ return 0;
	742	+
	743	+ if (map->agent.qp->qp_type == IB_QPT_SMI) {
	744	+ if (!map->agent.smp_allowed)
	745	+ return -EACCES;
	746	+ return 0;
	747	+ }
700	748
701	749	return ib_security_pkey_access(map->agent.device,
702	750	map->agent.port_num,

drivers/infiniband/core/uverbs_cmd.c+8−2

@@ -1968,6 +1968,12 @@ static int modify_qp(struct ib_uverbs_file *file, · 1967 unmodified lines
1968	1968	goto release_qp;
1969	1969	}
1970	1970
	1971	+ if ((cmd->base.attr_mask & IB_QP_ALT_PATH) &&
	1972	+ !rdma_is_port_valid(qp->device, cmd->base.alt_port_num)) {
	1973	+ ret = -EINVAL;
	1974	+ goto release_qp;
	1975	+ }
	1976	+
1971	1977	attr->qp_state = cmd->base.qp_state;
1972	1978	attr->cur_qp_state = cmd->base.cur_qp_state;
1973	1979	attr->path_mtu = cmd->base.path_mtu;
@@ -2065,8 +2071,8 @@ int ib_uverbs_ex_modify_qp(struct ib_uverbs_file *file, · 91 unmodified lines
2065	2071	return -EOPNOTSUPP;
2066	2072
2067	2073	if (ucore->inlen > sizeof(cmd)) {
2068		− if (ib_is_udata_cleared(ucore, sizeof(cmd),
2069		− ucore->inlen - sizeof(cmd)))
	2074	+ if (!ib_is_udata_cleared(ucore, sizeof(cmd),
	2075	+ ucore->inlen - sizeof(cmd)))
2070	2076	return -EOPNOTSUPP;
2071	2077	}
2072	2078

drivers/infiniband/core/verbs.c+2−1

@@ -1439,7 +1439,8 @@ int ib_close_qp(struct ib_qp *qp) · 1438 unmodified lines
1439	1439	spin_unlock_irqrestore(&real_qp->device->event_handler_lock, flags);
1440	1440
1441	1441	atomic_dec(&real_qp->usecnt);
1442		− ib_close_shared_qp_security(qp->qp_sec);
	1442	+ if (qp->qp_sec)
	1443	+ ib_close_shared_qp_security(qp->qp_sec);
1443	1444	kfree(qp);
1444	1445
1445	1446	return 0;

drivers/infiniband/hw/cxgb4/cq.c+9−7

@@ -395,6 +395,11 @@ next_cqe: · 394 unmodified lines
395	395
396	396	static int cqe_completes_wr(struct t4_cqe cqe, struct t4_wq wq)
397	397	{
	398	+ if (DRAIN_CQE(cqe)) {
	399	+ WARN_ONCE(1, "Unexpected DRAIN CQE qp id %u!\n", wq->sq.qid);
	400	+ return 0;
	401	+ }
	402	+
398	403	if (CQE_OPCODE(cqe) == FW_RI_TERMINATE)
399	404	return 0;
400	405
@@ -489,7 +494,7 @@ static int poll_cq(struct t4_wq wq, struct t4_cq cq, struct t4_cqe *cqe, · 88 unmodified lines
489	494	/*
490	495	* Special cqe for drain WR completions...
491	496	*/
492		− if (CQE_OPCODE(hw_cqe) == C4IW_DRAIN_OPCODE) {
	497	+ if (DRAIN_CQE(hw_cqe)) {
493	498	*cookie = CQE_DRAIN_COOKIE(hw_cqe);
494	499	cqe = hw_cqe;
495	500	goto skip_cqe;
@@ -566,10 +571,10 @@ static int poll_cq(struct t4_wq wq, struct t4_cq cq, struct t4_cqe *cqe, · 70 unmodified lines
566	571	ret = -EAGAIN;
567	572	goto skip_cqe;
568	573	}
569		− if (unlikely((CQE_WRID_MSN(hw_cqe) != (wq->rq.msn)))) {
	574	+ if (unlikely(!CQE_STATUS(hw_cqe) &&
	575	+ CQE_WRID_MSN(hw_cqe) != wq->rq.msn)) {
570	576	t4_set_wq_in_error(wq);
571		− hw_cqe->header \|= htonl(CQE_STATUS_V(T4_ERR_MSN));
572		− goto proc_cqe;
	577	+ hw_cqe->header \|= cpu_to_be32(CQE_STATUS_V(T4_ERR_MSN));
573	578	}
574	579	goto proc_cqe;
575	580	}
@@ -743,9 +748,6 @@ static int c4iw_poll_cq_one(struct c4iw_cq chp, struct ib_wc wc) · 167 unmodified lines
743	748	c4iw_invalidate_mr(qhp->rhp,
744	749	CQE_WRID_FR_STAG(&cqe));
745	750	break;
746		− case C4IW_DRAIN_OPCODE:
747		− wc->opcode = IB_WC_SEND;
748		− break;
749	751	default:
750	752	pr_err("Unexpected opcode %d in the CQE received for QPID=0x%0x\n",
751	753	CQE_OPCODE(&cqe), CQE_QPID(&cqe));

drivers/infiniband/hw/cxgb4/iw_cxgb4.h+0−2

@@ -693,8 +693,6 @@ static inline int to_ib_qp_state(int c4iw_qp_state) · 692 unmodified lines
693	693	return IB_QPS_ERR;
694	694	}
695	695
696		−#define C4IW_DRAIN_OPCODE FW_RI_SGE_EC_CR_RETURN
697		−
698	696	static inline u32 c4iw_ib_to_tpt_access(int a)
699	697	{
700	698	return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) \|

drivers/infiniband/hw/cxgb4/qp.c+83−11

@@ -790,21 +790,57 @@ static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc) · 789 unmodified lines
790	790	return 0;
791	791	}
792	792
793		−static void complete_sq_drain_wr(struct c4iw_qp qhp, struct ib_send_wr wr)
	793	+static int ib_to_fw_opcode(int ib_opcode)
	794	+{
	795	+ int opcode;
	796	+
	797	+ switch (ib_opcode) {
	798	+ case IB_WR_SEND_WITH_INV:
	799	+ opcode = FW_RI_SEND_WITH_INV;
	800	+ break;
	801	+ case IB_WR_SEND:
	802	+ opcode = FW_RI_SEND;
	803	+ break;
	804	+ case IB_WR_RDMA_WRITE:
	805	+ opcode = FW_RI_RDMA_WRITE;
	806	+ break;
	807	+ case IB_WR_RDMA_READ:
	808	+ case IB_WR_RDMA_READ_WITH_INV:
	809	+ opcode = FW_RI_READ_REQ;
	810	+ break;
	811	+ case IB_WR_REG_MR:
	812	+ opcode = FW_RI_FAST_REGISTER;
	813	+ break;
	814	+ case IB_WR_LOCAL_INV:
	815	+ opcode = FW_RI_LOCAL_INV;
	816	+ break;
	817	+ default:
	818	+ opcode = -EINVAL;
	819	+ }
	820	+ return opcode;
	821	+}
	822	+
	823	+static int complete_sq_drain_wr(struct c4iw_qp qhp, struct ib_send_wr wr)
794	824	{
795	825	struct t4_cqe cqe = {};
796	826	struct c4iw_cq *schp;
797	827	unsigned long flag;
798	828	struct t4_cq *cq;
	829	+ int opcode;
799	830
800	831	schp = to_c4iw_cq(qhp->ibqp.send_cq);
801	832	cq = &schp->cq;
802	833
	834	+ opcode = ib_to_fw_opcode(wr->opcode);
	835	+ if (opcode < 0)
	836	+ return opcode;
	837	+
803	838	cqe.u.drain_cookie = wr->wr_id;
804	839	cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) \|
805		− CQE_OPCODE_V(C4IW_DRAIN_OPCODE) \|
	840	+ CQE_OPCODE_V(opcode) \|
806	841	CQE_TYPE_V(1) \|
807	842	CQE_SWCQE_V(1) \|
	843	+ CQE_DRAIN_V(1) \|
808	844	CQE_QPID_V(qhp->wq.sq.qid));
809	845
810	846	spin_lock_irqsave(&schp->lock, flag);
@@ -819,6 +855,23 @@ static void complete_sq_drain_wr(struct c4iw_qp qhp, struct ib_send_wr wr) · 8 unmodified lines
819	855	schp->ibcq.cq_context);
820	856	spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
821	857	}
	858	+ return 0;
	859	+}
	860	+
	861	+static int complete_sq_drain_wrs(struct c4iw_qp qhp, struct ib_send_wr wr,
	862	+ struct ib_send_wr **bad_wr)
	863	+{
	864	+ int ret = 0;
	865	+
	866	+ while (wr) {
	867	+ ret = complete_sq_drain_wr(qhp, wr);
	868	+ if (ret) {
	869	+ *bad_wr = wr;
	870	+ break;
	871	+ }
	872	+ wr = wr->next;
	873	+ }
	874	+ return ret;
822	875	}
823	876
824	877	static void complete_rq_drain_wr(struct c4iw_qp qhp, struct ib_recv_wr wr)
@@ -833,9 +886,10 @@ static void complete_rq_drain_wr(struct c4iw_qp qhp, struct ib_recv_wr wr) · 8 unmodified lines
833	886
834	887	cqe.u.drain_cookie = wr->wr_id;
835	888	cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) \|
836		− CQE_OPCODE_V(C4IW_DRAIN_OPCODE) \|
	889	+ CQE_OPCODE_V(FW_RI_SEND) \|
837	890	CQE_TYPE_V(0) \|
838	891	CQE_SWCQE_V(1) \|
	892	+ CQE_DRAIN_V(1) \|
839	893	CQE_QPID_V(qhp->wq.sq.qid));
840	894
841	895	spin_lock_irqsave(&rchp->lock, flag);
@@ -852,6 +906,14 @@ static void complete_rq_drain_wr(struct c4iw_qp qhp, struct ib_recv_wr wr) · 10 unmodified lines
852	906	}
853	907	}
854	908
	909	+static void complete_rq_drain_wrs(struct c4iw_qp qhp, struct ib_recv_wr wr)
	910	+{
	911	+ while (wr) {
	912	+ complete_rq_drain_wr(qhp, wr);
	913	+ wr = wr->next;
	914	+ }
	915	+}
	916	+
855	917	int c4iw_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
856	918	struct ib_send_wr **bad_wr)
857	919	{
@@ -868,9 +930,14 @@ int c4iw_post_send(struct ib_qp ibqp, struct ib_send_wr wr, · 10 unmodified lines
868	930
869	931	qhp = to_c4iw_qp(ibqp);
870	932	spin_lock_irqsave(&qhp->lock, flag);
871		− if (t4_wq_in_error(&qhp->wq)) {
	933	+
	934	+ /*
	935	+ * If the qp has been flushed, then just insert a special
	936	+ * drain cqe.
	937	+ */
	938	+ if (qhp->wq.flushed) {
872	939	spin_unlock_irqrestore(&qhp->lock, flag);
873		− complete_sq_drain_wr(qhp, wr);
	940	+ err = complete_sq_drain_wrs(qhp, wr, bad_wr);
874	941	return err;
875	942	}
876	943	num_wrs = t4_sq_avail(&qhp->wq);
@@ -1011,9 +1078,14 @@ int c4iw_post_receive(struct ib_qp ibqp, struct ib_recv_wr wr, · 134 unmodified lines
1011	1078
1012	1079	qhp = to_c4iw_qp(ibqp);
1013	1080	spin_lock_irqsave(&qhp->lock, flag);
1014		− if (t4_wq_in_error(&qhp->wq)) {
	1081	+
	1082	+ /*
	1083	+ * If the qp has been flushed, then just insert a special
	1084	+ * drain cqe.
	1085	+ */
	1086	+ if (qhp->wq.flushed) {
1015	1087	spin_unlock_irqrestore(&qhp->lock, flag);
1016		− complete_rq_drain_wr(qhp, wr);
	1088	+ complete_rq_drain_wrs(qhp, wr);
1017	1089	return err;
1018	1090	}
1019	1091	num_wrs = t4_rq_avail(&qhp->wq);
@@ -1285,21 +1357,21 @@ static void __flush_qp(struct c4iw_qp qhp, struct c4iw_cq rchp, · 265 unmodified lines
1285	1357	spin_unlock_irqrestore(&rchp->lock, flag);
1286	1358
1287	1359	if (schp == rchp) {
1288		− if (t4_clear_cq_armed(&rchp->cq) &&
1289		− (rq_flushed \|\| sq_flushed)) {
	1360	+ if ((rq_flushed \|\| sq_flushed) &&
	1361	+ t4_clear_cq_armed(&rchp->cq)) {
1290	1362	spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1291	1363	(*rchp->ibcq.comp_handler)(&rchp->ibcq,
1292	1364	rchp->ibcq.cq_context);
1293	1365	spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1294	1366	}
1295	1367	} else {
1296		− if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) {
	1368	+ if (rq_flushed && t4_clear_cq_armed(&rchp->cq)) {
1297	1369	spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1298	1370	(*rchp->ibcq.comp_handler)(&rchp->ibcq,
1299	1371	rchp->ibcq.cq_context);
1300	1372	spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1301	1373	}
1302		− if (t4_clear_cq_armed(&schp->cq) && sq_flushed) {
	1374	+ if (sq_flushed && t4_clear_cq_armed(&schp->cq)) {
1303	1375	spin_lock_irqsave(&schp->comp_handler_lock, flag);
1304	1376	(*schp->ibcq.comp_handler)(&schp->ibcq,
1305	1377	schp->ibcq.cq_context);

drivers/infiniband/hw/cxgb4/t4.h+6−0

@@ -197,6 +197,11 @@ struct t4_cqe { · 196 unmodified lines
197	197	#define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M)
198	198	#define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S)
199	199
	200	+#define CQE_DRAIN_S 10
	201	+#define CQE_DRAIN_M 0x1
	202	+#define CQE_DRAIN_G(x) ((((x) >> CQE_DRAIN_S)) & CQE_DRAIN_M)
	203	+#define CQE_DRAIN_V(x) ((x)<<CQE_DRAIN_S)
	204	+
200	205	#define CQE_STATUS_S 5
201	206	#define CQE_STATUS_M 0x1F
202	207	#define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M)
@@ -213,6 +218,7 @@ struct t4_cqe { · 10 unmodified lines
213	218	#define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S)
214	219
215	220	#define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header)))
	221	+#define DRAIN_CQE(x) (CQE_DRAIN_G(be32_to_cpu((x)->header)))
216	222	#define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header)))
217	223	#define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header)))
218	224	#define SQ_TYPE(x) (CQE_TYPE((x)))

drivers/infiniband/hw/hfi1/hfi.h+0−1

@@ -1131,7 +1131,6 @@ struct hfi1_devdata { · 1130 unmodified lines
1131	1131	u16 pcie_lnkctl;
1132	1132	u16 pcie_devctl2;
1133	1133	u32 pci_msix0;
1134		− u32 pci_lnkctl3;
1135	1134	u32 pci_tph2;
1136	1135
1137	1136	/*

drivers/infiniband/hw/hfi1/pcie.c+12−18

@@ -411,15 +411,12 @@ int restore_pci_variables(struct hfi1_devdata *dd) · 410 unmodified lines
411	411	if (ret)
412	412	goto error;
413	413
414		− ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE1,
415		− dd->pci_lnkctl3);
416		− if (ret)
417		− goto error;
418		−
419		− ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, dd->pci_tph2);
420		− if (ret)
421		− goto error;
422		−
	414	+ if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
	415	+ ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2,
	416	+ dd->pci_tph2);
	417	+ if (ret)
	418	+ goto error;
	419	+ }
423	420	return 0;
424	421
425	422	error:
@@ -469,15 +466,12 @@ int save_pci_variables(struct hfi1_devdata *dd) · 43 unmodified lines
469	466	if (ret)
470	467	goto error;
471	468
472		− ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1,
473		− &dd->pci_lnkctl3);
474		− if (ret)
475		− goto error;
476		−
477		− ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2);
478		− if (ret)
479		− goto error;
480		−
	469	+ if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
	470	+ ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2,
	471	+ &dd->pci_tph2);
	472	+ if (ret)
	473	+ goto error;
	474	+ }
481	475	return 0;
482	476
483	477	error:

drivers/infiniband/hw/hfi1/rc.c+1−1

@@ -814,7 +814,7 @@ static inline void hfi1_make_rc_ack_16B(struct rvt_qp *qp, · 813 unmodified lines
814	814	struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
815	815	struct hfi1_16b_header *hdr = &opa_hdr->opah;
816	816	struct ib_other_headers *ohdr;
817		− u32 bth0, bth1;
	817	+ u32 bth0, bth1 = 0;
818	818	u16 len, pkey;
819	819	u8 becn = !!is_fecn;
820	820	u8 l4 = OPA_16B_L4_IB_LOCAL;

drivers/infiniband/hw/hns/hns_roce_alloc.c+0−23

@@ -162,14 +162,10 @@ void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size, · 161 unmodified lines
162	162	{
163	163	int i;
164	164	struct device *dev = hr_dev->dev;
165		− u32 bits_per_long = BITS_PER_LONG;
166	165
167	166	if (buf->nbufs == 1) {
168	167	dma_free_coherent(dev, size, buf->direct.buf, buf->direct.map);
169	168	} else {
170		− if (bits_per_long == 64 && buf->page_shift == PAGE_SHIFT)
171		− vunmap(buf->direct.buf);
172		−
173	169	for (i = 0; i < buf->nbufs; ++i)
174	170	if (buf->page_list[i].buf)
175	171	dma_free_coherent(dev, 1 << buf->page_shift,
@@ -185,9 +181,7 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, · 9 unmodified lines
185	181	{
186	182	int i = 0;
187	183	dma_addr_t t;
188		− struct page **pages;
189	184	struct device *dev = hr_dev->dev;
190		− u32 bits_per_long = BITS_PER_LONG;
191	185	u32 page_size = 1 << page_shift;
192	186	u32 order;
193	187
@@ -236,23 +230,6 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, · 42 unmodified lines
236	230	buf->page_list[i].map = t;
237	231	memset(buf->page_list[i].buf, 0, page_size);
238	232	}
239		− if (bits_per_long == 64 && page_shift == PAGE_SHIFT) {
240		− pages = kmalloc_array(buf->nbufs, sizeof(*pages),
241		− GFP_KERNEL);
242		− if (!pages)
243		− goto err_free;
244		−
245		− for (i = 0; i < buf->nbufs; ++i)
246		− pages[i] = virt_to_page(buf->page_list[i].buf);
247		−
248		− buf->direct.buf = vmap(pages, buf->nbufs, VM_MAP,
249		− PAGE_KERNEL);
250		− kfree(pages);
251		− if (!buf->direct.buf)
252		− goto err_free;
253		− } else {
254		− buf->direct.buf = NULL;
255		− }
256	233	}
257	234
258	235	return 0;

drivers/infiniband/hw/hns/hns_roce_device.h+1−3

@@ -795,11 +795,9 @@ static inline struct hns_roce_qp · 794 unmodified lines
795	795
796	796	static inline void hns_roce_buf_offset(struct hns_roce_buf buf, int offset)
797	797	{
798		− u32 bits_per_long_val = BITS_PER_LONG;
799	798	u32 page_size = 1 << buf->page_shift;
800	799
801		− if ((bits_per_long_val == 64 && buf->page_shift == PAGE_SHIFT) \|\|
802		− buf->nbufs == 1)
	800	+ if (buf->nbufs == 1)
803	801	return (char *)(buf->direct.buf) + offset;
804	802	else
805	803	return (char *)(buf->page_list[offset >> buf->page_shift].buf) +

drivers/infiniband/hw/hns/hns_roce_hem.c+13−12

@@ -224,6 +224,7 @@ static struct hns_roce_hem hns_roce_alloc_hem(struct hns_roce_dev hr_dev, · 223 unmodified lines
224	224	sg_init_table(chunk->mem, HNS_ROCE_HEM_CHUNK_LEN);
225	225	chunk->npages = 0;
226	226	chunk->nsg = 0;
	227	+ memset(chunk->buf, 0, sizeof(chunk->buf));
227	228	list_add_tail(&chunk->list, &hem->chunk_list);
228	229	}
229	230
@@ -240,8 +241,7 @@ static struct hns_roce_hem hns_roce_alloc_hem(struct hns_roce_dev hr_dev, · 10 unmodified lines
240	241	if (!buf)
241	242	goto fail;
242	243
243		− sg_set_buf(mem, buf, PAGE_SIZE << order);
244		− WARN_ON(mem->offset);
	244	+ chunk->buf[chunk->npages] = buf;
245	245	sg_dma_len(mem) = PAGE_SIZE << order;
246	246
247	247	++chunk->npages;
@@ -267,8 +267,8 @@ void hns_roce_free_hem(struct hns_roce_dev hr_dev, struct hns_roce_hem hem) · 19 unmodified lines
267	267	list_for_each_entry_safe(chunk, tmp, &hem->chunk_list, list) {
268	268	for (i = 0; i < chunk->npages; ++i)
269	269	dma_free_coherent(hr_dev->dev,
270		− chunk->mem[i].length,
271		− lowmem_page_address(sg_page(&chunk->mem[i])),
	270	+ sg_dma_len(&chunk->mem[i]),
	271	+ chunk->buf[i],
272	272	sg_dma_address(&chunk->mem[i]));
273	273	kfree(chunk);
274	274	}
@@ -722,11 +722,12 @@ void hns_roce_table_find(struct hns_roce_dev hr_dev, · 447 unmodified lines
722	722	struct hns_roce_hem_chunk *chunk;
723	723	struct hns_roce_hem_mhop mhop;
724	724	struct hns_roce_hem *hem;
725		− struct page *page = NULL;
	725	+ void *addr = NULL;
726	726	unsigned long mhop_obj = obj;
727	727	unsigned long obj_per_chunk;
728	728	unsigned long idx_offset;
729	729	int offset, dma_offset;
	730	+ int length;
730	731	int i, j;
731	732	u32 hem_idx = 0;
732	733
@@ -763,25 +764,25 @@ void hns_roce_table_find(struct hns_roce_dev hr_dev, · 30 unmodified lines
763	764
764	765	list_for_each_entry(chunk, &hem->chunk_list, list) {
765	766	for (i = 0; i < chunk->npages; ++i) {
	767	+ length = sg_dma_len(&chunk->mem[i]);
766	768	if (dma_handle && dma_offset >= 0) {
767		− if (sg_dma_len(&chunk->mem[i]) >
768		− (u32)dma_offset)
	769	+ if (length > (u32)dma_offset)
769	770	*dma_handle = sg_dma_address(
770	771	&chunk->mem[i]) + dma_offset;
771		− dma_offset -= sg_dma_len(&chunk->mem[i]);
	772	+ dma_offset -= length;
772	773	}
773	774
774		− if (chunk->mem[i].length > (u32)offset) {
775		− page = sg_page(&chunk->mem[i]);
	775	+ if (length > (u32)offset) {
	776	+ addr = chunk->buf[i] + offset;
776	777	goto out;
777	778	}
778		− offset -= chunk->mem[i].length;
	779	+ offset -= length;
779	780	}
780	781	}
781	782
782	783	out:
783	784	mutex_unlock(&table->mutex);
784		− return page ? lowmem_page_address(page) + offset : NULL;
	785	+ return addr;
785	786	}
786	787	EXPORT_SYMBOL_GPL(hns_roce_table_find);
787	788

drivers/infiniband/hw/hns/hns_roce_hem.h+1−0

@@ -78,6 +78,7 @@ struct hns_roce_hem_chunk { · 77 unmodified lines
78	78	int npages;
79	79	int nsg;
80	80	struct scatterlist mem[HNS_ROCE_HEM_CHUNK_LEN];
	81	+ void *buf[HNS_ROCE_HEM_CHUNK_LEN];
81	82	};
82	83
83	84	struct hns_roce_hem {

drivers/infiniband/hw/hns/hns_roce_hw_v2.c+15−7

@@ -1131,9 +1131,11 @@ static int hns_roce_v2_write_mtpt(void mb_buf, struct hns_roce_mr mr, · 1130 unmodified lines
1131	1131	{
1132	1132	struct hns_roce_v2_mpt_entry *mpt_entry;
1133	1133	struct scatterlist *sg;
	1134	+ u64 page_addr;
1134	1135	u64 *pages;
	1136	+ int i, j;
	1137	+ int len;
1135	1138	int entry;
1136		− int i;
1137	1139
1138	1140	mpt_entry = mb_buf;
1139	1141	memset(mpt_entry, 0, sizeof(*mpt_entry));
@@ -1191,14 +1193,20 @@ static int hns_roce_v2_write_mtpt(void mb_buf, struct hns_roce_mr mr, · 51 unmodified lines
1191	1193
1192	1194	i = 0;
1193	1195	for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1194		− pages[i] = ((u64)sg_dma_address(sg)) >> 6;
1195		−
1196		− /* Record the first 2 entry directly to MTPT table */
1197		− if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
1198		− break;
1199		− i++;
	1196	+ len = sg_dma_len(sg) >> PAGE_SHIFT;
	1197	+ for (j = 0; j < len; ++j) {
	1198	+ page_addr = sg_dma_address(sg) +
	1199	+ (j << mr->umem->page_shift);
	1200	+ pages[i] = page_addr >> 6;
	1201	+
	1202	+ /* Record the first 2 entry directly to MTPT table */
	1203	+ if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
	1204	+ goto found;
	1205	+ i++;
	1206	+ }
1200	1207	}
1201	1208
	1209	+found:
1202	1210	mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
1203	1211	roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
1204	1212	V2_MPT_BYTE_56_PA0_H_S,

drivers/infiniband/hw/i40iw/i40iw_cm.c+21−12

@@ -1041,7 +1041,7 @@ negotiate_done: · 1040 unmodified lines
1041	1041	* i40iw_schedule_cm_timer
1042	1042	* @@cm_node: connection's node
1043	1043	* @sqbuf: buffer to send
1044		− * @type: if it es send ot close
	1044	+ * @type: if it is send or close
1045	1045	* @send_retrans: if rexmits to be done
1046	1046	* @close_when_complete: is cm_node to be removed
1047	1047	*
@@ -1065,7 +1065,8 @@ int i40iw_schedule_cm_timer(struct i40iw_cm_node *cm_node, · 17 unmodified lines
1065	1065
1066	1066	new_send = kzalloc(sizeof(*new_send), GFP_ATOMIC);
1067	1067	if (!new_send) {
1068		− i40iw_free_sqbuf(vsi, (void *)sqbuf);
	1068	+ if (type != I40IW_TIMER_TYPE_CLOSE)
	1069	+ i40iw_free_sqbuf(vsi, (void *)sqbuf);
1069	1070	return -ENOMEM;
1070	1071	}
1071	1072	new_send->retrycount = I40IW_DEFAULT_RETRYS;
@@ -1080,7 +1081,6 @@ int i40iw_schedule_cm_timer(struct i40iw_cm_node *cm_node, · 8 unmodified lines
1080	1081	new_send->timetosend += (HZ / 10);
1081	1082	if (cm_node->close_entry) {
1082	1083	kfree(new_send);
1083		− i40iw_free_sqbuf(vsi, (void *)sqbuf);
1084	1084	i40iw_pr_err("already close entry\n");
1085	1085	return -EINVAL;
1086	1086	}
@@ -2952,8 +2952,6 @@ static struct i40iw_cm_node *i40iw_create_cm_node( · 1865 unmodified lines
2952	2952	loopback_remotenode->tcp_cntxt.snd_wnd = cm_node->tcp_cntxt.rcv_wnd;
2953	2953	cm_node->tcp_cntxt.snd_wscale = loopback_remotenode->tcp_cntxt.rcv_wscale;
2954	2954	loopback_remotenode->tcp_cntxt.snd_wscale = cm_node->tcp_cntxt.rcv_wscale;
2955		− loopback_remotenode->state = I40IW_CM_STATE_MPAREQ_RCVD;
2956		− i40iw_create_event(loopback_remotenode, I40IW_CM_EVENT_MPA_REQ);
2957	2955	}
2958	2956	return cm_node;
2959	2957	}
@@ -3694,11 +3692,16 @@ int i40iw_accept(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param) · 734 unmodified lines
3694	3692	cm_id->add_ref(cm_id);
3695	3693	i40iw_add_ref(&iwqp->ibqp);
3696	3694
3697		− i40iw_send_cm_event(cm_node, cm_id, IW_CM_EVENT_ESTABLISHED, 0);
3698		−
3699	3695	attr.qp_state = IB_QPS_RTS;
3700	3696	cm_node->qhash_set = false;
3701	3697	i40iw_modify_qp(&iwqp->ibqp, &attr, IB_QP_STATE, NULL);
	3698	+
	3699	+ cm_node->accelerated = true;
	3700	+ status =
	3701	+ i40iw_send_cm_event(cm_node, cm_id, IW_CM_EVENT_ESTABLISHED, 0);
	3702	+ if (status)
	3703	+ i40iw_debug(dev, I40IW_DEBUG_CM, "error sending cm event - ESTABLISHED\n");
	3704	+
3702	3705	if (cm_node->loopbackpartner) {
3703	3706	cm_node->loopbackpartner->pdata.size = conn_param->private_data_len;
3704	3707
@@ -3709,7 +3712,6 @@ int i40iw_accept(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param) · 4 unmodified lines
3709	3712	i40iw_create_event(cm_node->loopbackpartner, I40IW_CM_EVENT_CONNECTED);
3710	3713	}
3711	3714
3712		− cm_node->accelerated = 1;
3713	3715	if (cm_node->accept_pend) {
3714	3716	atomic_dec(&cm_node->listener->pend_accepts_cnt);
3715	3717	cm_node->accept_pend = 0;
@@ -3862,6 +3864,12 @@ int i40iw_connect(struct iw_cm_id cm_id, struct iw_cm_conn_param conn_param) · 146 unmodified lines
3862	3864	goto err;
3863	3865	}
3864	3866
	3867	+ if (cm_node->loopbackpartner) {
	3868	+ cm_node->loopbackpartner->state = I40IW_CM_STATE_MPAREQ_RCVD;
	3869	+ i40iw_create_event(cm_node->loopbackpartner,
	3870	+ I40IW_CM_EVENT_MPA_REQ);
	3871	+ }
	3872	+
3865	3873	i40iw_debug(cm_node->dev,
3866	3874	I40IW_DEBUG_CM,
3867	3875	"Api - connect(): port=0x%04x, cm_node=%p, cm_id = %p.\n",
@@ -4042,16 +4050,17 @@ static void i40iw_cm_event_connected(struct i40iw_cm_event *event) · 174 unmodified lines
4042	4050	dev->iw_priv_qp_ops->qp_send_rtt(&iwqp->sc_qp, read0);
4043	4051	if (iwqp->page)
4044	4052	kunmap(iwqp->page);
4045		− status = i40iw_send_cm_event(cm_node, cm_id, IW_CM_EVENT_CONNECT_REPLY, 0);
4046		− if (status)
4047		− i40iw_pr_err("send cm event\n");
4048	4053
4049	4054	memset(&attr, 0, sizeof(attr));
4050	4055	attr.qp_state = IB_QPS_RTS;
4051	4056	cm_node->qhash_set = false;
4052	4057	i40iw_modify_qp(&iwqp->ibqp, &attr, IB_QP_STATE, NULL);
4053	4058
4054		− cm_node->accelerated = 1;
	4059	+ cm_node->accelerated = true;
	4060	+ status = i40iw_send_cm_event(cm_node, cm_id, IW_CM_EVENT_CONNECT_REPLY,
	4061	+ 0);
	4062	+ if (status)
	4063	+ i40iw_debug(dev, I40IW_DEBUG_CM, "error sending cm event - CONNECT_REPLY\n");
4055	4064
4056	4065	return;
4057	4066

drivers/infiniband/hw/i40iw/i40iw_cm.h+1−1

@@ -335,7 +335,7 @@ struct i40iw_cm_node { · 334 unmodified lines
335	335	u16 mpav2_ird_ord;
336	336	struct iw_cm_id *cm_id;
337	337	struct list_head list;
338		− int accelerated;
	338	+ bool accelerated;
339	339	struct i40iw_cm_listener *listener;
340	340	int apbvt_set;
341	341	int accept_pend;

drivers/infiniband/hw/i40iw/i40iw_ctrl.c+30−13

@@ -513,7 +513,7 @@ static enum i40iw_status_code i40iw_sc_cqp_create(struct i40iw_sc_cqp *cqp, · 512 unmodified lines
513	513
514	514	ret_code = i40iw_allocate_dma_mem(cqp->dev->hw,
515	515	&cqp->sdbuf,
516		− 128,
	516	+ I40IW_UPDATE_SD_BUF_SIZE * cqp->sq_size,
517	517	I40IW_SD_BUF_ALIGNMENT);
518	518
519	519	if (ret_code)
@@ -596,14 +596,15 @@ void i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp *cqp) · 76 unmodified lines
596	596	}
597	597
598	598	/**
599		− * i40iw_sc_cqp_get_next_send_wqe - get next wqe on cqp sq
600		− * @cqp: struct for cqp hw
601		− * @wqe_idx: we index of cqp ring
	599	+ * i40iw_sc_cqp_get_next_send_wqe_idx - get next WQE on CQP SQ and pass back the index
	600	+ * @cqp: pointer to CQP structure
	601	+ * @scratch: private data for CQP WQE
	602	+ * @wqe_idx: WQE index for next WQE on CQP SQ
602	603	*/
603		−u64 i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp cqp, u64 scratch)
	604	+static u64 i40iw_sc_cqp_get_next_send_wqe_idx(struct i40iw_sc_cqp cqp,
	605	+ u64 scratch, u32 *wqe_idx)
604	606	{
605	607	u64 *wqe = NULL;
606		− u32 wqe_idx;
607	608	enum i40iw_status_code ret_code;
608	609
609	610	if (I40IW_RING_FULL_ERR(cqp->sq_ring)) {
@@ -616,20 +617,32 @@ u64 i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp cqp, u64 scratch) · 6 unmodified lines
616	617	cqp->sq_ring.size);
617	618	return NULL;
618	619	}
619		− I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, wqe_idx, ret_code);
	620	+ I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code);
620	621	cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS]++;
621	622	if (ret_code)
622	623	return NULL;
623		− if (!wqe_idx)
	624	+ if (!*wqe_idx)
624	625	cqp->polarity = !cqp->polarity;
625	626
626		− wqe = cqp->sq_base[wqe_idx].elem;
627		− cqp->scratch_array[wqe_idx] = scratch;
	627	+ wqe = cqp->sq_base[*wqe_idx].elem;
	628	+ cqp->scratch_array[*wqe_idx] = scratch;
628	629	I40IW_CQP_INIT_WQE(wqe);
629	630
630	631	return wqe;
631	632	}
632	633
	634	+/**
	635	+ * i40iw_sc_cqp_get_next_send_wqe - get next wqe on cqp sq
	636	+ * @cqp: struct for cqp hw
	637	+ * @scratch: private data for CQP WQE
	638	+ */
	639	+u64 i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp cqp, u64 scratch)
	640	+{
	641	+ u32 wqe_idx;
	642	+
	643	+ return i40iw_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
	644	+}
	645	+
633	646	/**
634	647	* i40iw_sc_cqp_destroy - destroy cqp during close
635	648	* @cqp: struct for cqp hw
@@ -3587,8 +3600,10 @@ static enum i40iw_status_code cqp_sds_wqe_fill(struct i40iw_sc_cqp *cqp, · 2951 unmodified lines
3587	3600	u64 *wqe;
3588	3601	int mem_entries, wqe_entries;
3589	3602	struct i40iw_dma_mem *sdbuf = &cqp->sdbuf;
	3603	+ u64 offset;
	3604	+ u32 wqe_idx;
3590	3605
3591		− wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
	3606	+ wqe = i40iw_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
3592	3607	if (!wqe)
3593	3608	return I40IW_ERR_RING_FULL;
3594	3609
@@ -3601,8 +3616,10 @@ static enum i40iw_status_code cqp_sds_wqe_fill(struct i40iw_sc_cqp *cqp, · 6 unmodified lines
3601	3616	LS_64(mem_entries, I40IW_CQPSQ_UPESD_ENTRY_COUNT);
3602	3617
3603	3618	if (mem_entries) {
3604		− memcpy(sdbuf->va, &info->entry[3], (mem_entries << 4));
3605		− data = sdbuf->pa;
	3619	+ offset = wqe_idx * I40IW_UPDATE_SD_BUF_SIZE;
	3620	+ memcpy((char *)sdbuf->va + offset, &info->entry[3],
	3621	+ mem_entries << 4);
	3622	+ data = (u64)sdbuf->pa + offset;
3606	3623	} else {
3607	3624	data = 0;
3608	3625	}

drivers/infiniband/hw/i40iw/i40iw_d.h+4−2

@@ -1115,7 +1115,7 @@ · 1114 unmodified lines
1115	1115	#define I40IWQPC_VLANTAG_MASK (0xffffULL << I40IWQPC_VLANTAG_SHIFT)
1116	1116
1117	1117	#define I40IWQPC_ARPIDX_SHIFT 48
1118		−#define I40IWQPC_ARPIDX_MASK (0xfffULL << I40IWQPC_ARPIDX_SHIFT)
	1118	+#define I40IWQPC_ARPIDX_MASK (0xffffULL << I40IWQPC_ARPIDX_SHIFT)
1119	1119
1120	1120	#define I40IWQPC_FLOWLABEL_SHIFT 0
1121	1121	#define I40IWQPC_FLOWLABEL_MASK (0xfffffUL << I40IWQPC_FLOWLABEL_SHIFT)
@@ -1527,7 +1527,7 @@ enum i40iw_alignment { · 405 unmodified lines
1527	1527	I40IW_AEQ_ALIGNMENT = 0x100,
1528	1528	I40IW_CEQ_ALIGNMENT = 0x100,
1529	1529	I40IW_CQ0_ALIGNMENT = 0x100,
1530		− I40IW_SD_BUF_ALIGNMENT = 0x100
	1530	+ I40IW_SD_BUF_ALIGNMENT = 0x80
1531	1531	};
1532	1532
1533	1533	#define I40IW_WQE_SIZE_64 64
@@ -1535,6 +1535,8 @@ enum i40iw_alignment { · 1 unmodified line
1535	1535	#define I40IW_QP_WQE_MIN_SIZE 32
1536	1536	#define I40IW_QP_WQE_MAX_SIZE 128
1537	1537
	1538	+#define I40IW_UPDATE_SD_BUF_SIZE 128
	1539	+
1538	1540	#define I40IW_CQE_QTYPE_RQ 0
1539	1541	#define I40IW_CQE_QTYPE_SQ 1
1540	1542

drivers/infiniband/hw/mlx4/qp.c+19−7

@@ -666,6 +666,19 @@ static int set_qp_rss(struct mlx4_ib_dev dev, struct mlx4_ib_rss rss_ctx, · 665 unmodified lines
666	666	return (-EOPNOTSUPP);
667	667	}
668	668
	669	+ if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 \|
	670	+ MLX4_IB_RX_HASH_DST_IPV4 \|
	671	+ MLX4_IB_RX_HASH_SRC_IPV6 \|
	672	+ MLX4_IB_RX_HASH_DST_IPV6 \|
	673	+ MLX4_IB_RX_HASH_SRC_PORT_TCP \|
	674	+ MLX4_IB_RX_HASH_DST_PORT_TCP \|
	675	+ MLX4_IB_RX_HASH_SRC_PORT_UDP \|
	676	+ MLX4_IB_RX_HASH_DST_PORT_UDP)) {
	677	+ pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
	678	+ ucmd->rx_hash_fields_mask);
	679	+ return (-EOPNOTSUPP);
	680	+ }
	681	+
669	682	if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
670	683	(ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
671	684	rss_ctx->flags = MLX4_RSS_IPV4;
@@ -691,11 +704,11 @@ static int set_qp_rss(struct mlx4_ib_dev dev, struct mlx4_ib_rss rss_ctx, · 19 unmodified lines
691	704	return (-EOPNOTSUPP);
692	705	}
693	706
694		− if (rss_ctx->flags & MLX4_RSS_IPV4) {
	707	+ if (rss_ctx->flags & MLX4_RSS_IPV4)
695	708	rss_ctx->flags \|= MLX4_RSS_UDP_IPV4;
696		− } else if (rss_ctx->flags & MLX4_RSS_IPV6) {
	709	+ if (rss_ctx->flags & MLX4_RSS_IPV6)
697	710	rss_ctx->flags \|= MLX4_RSS_UDP_IPV6;
698		− } else {
	711	+ if (!(rss_ctx->flags & (MLX4_RSS_IPV6 \| MLX4_RSS_IPV4))) {
699	712	pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
700	713	return (-EOPNOTSUPP);
701	714	}
@@ -707,15 +720,14 @@ static int set_qp_rss(struct mlx4_ib_dev dev, struct mlx4_ib_rss rss_ctx, · 5 unmodified lines
707	720
708	721	if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
709	722	(ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
710		− if (rss_ctx->flags & MLX4_RSS_IPV4) {
	723	+ if (rss_ctx->flags & MLX4_RSS_IPV4)
711	724	rss_ctx->flags \|= MLX4_RSS_TCP_IPV4;
712		− } else if (rss_ctx->flags & MLX4_RSS_IPV6) {
	725	+ if (rss_ctx->flags & MLX4_RSS_IPV6)
713	726	rss_ctx->flags \|= MLX4_RSS_TCP_IPV6;
714		− } else {
	727	+ if (!(rss_ctx->flags & (MLX4_RSS_IPV6 \| MLX4_RSS_IPV4))) {
715	728	pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
716	729	return (-EOPNOTSUPP);
717	730	}
718		−
719	731	} else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) \|\|
720	732	(ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
721	733	pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");

drivers/infiniband/hw/mlx5/cmd.c+0−11

@@ -47,17 +47,6 @@ int mlx5_cmd_null_mkey(struct mlx5_core_dev dev, u32 null_mkey) · 46 unmodified lines
47	47	return err;
48	48	}
49	49
50		−int mlx5_cmd_query_cong_counter(struct mlx5_core_dev *dev,
51		− bool reset, void *out, int out_size)
52		−{
53		− u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)] = { };
54		−
55		− MLX5_SET(query_cong_statistics_in, in, opcode,
56		− MLX5_CMD_OP_QUERY_CONG_STATISTICS);
57		− MLX5_SET(query_cong_statistics_in, in, clear, reset);
58		− return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size);
59		−}
60		−
61	50	int mlx5_cmd_query_cong_params(struct mlx5_core_dev *dev, int cong_point,
62	51	void *out, int out_size)
63	52	{

drivers/infiniband/hw/mlx5/cmd.h+0−2

@@ -37,8 +37,6 @@ · 36 unmodified lines
37	37	#include <linux/mlx5/driver.h>
38	38
39	39	int mlx5_cmd_null_mkey(struct mlx5_core_dev dev, u32 null_mkey);
40		−int mlx5_cmd_query_cong_counter(struct mlx5_core_dev *dev,
41		− bool reset, void *out, int out_size);
42	40	int mlx5_cmd_query_cong_params(struct mlx5_core_dev *dev, int cong_point,
43	41	void *out, int out_size);
44	42	int mlx5_cmd_modify_cong_params(struct mlx5_core_dev *mdev,

drivers/infiniband/hw/mlx5/main.c+14−29

@@ -1461,6 +1461,7 @@ static struct ib_ucontext mlx5_ib_alloc_ucontext(struct ib_device ibdev, · 1460 unmodified lines
1461	1461	}
1462	1462
1463	1463	INIT_LIST_HEAD(&context->vma_private_list);
	1464	+ mutex_init(&context->vma_private_list_mutex);
1464	1465	INIT_LIST_HEAD(&context->db_page_list);
1465	1466	mutex_init(&context->db_page_mutex);
1466	1467
@@ -1622,7 +1623,9 @@ static void mlx5_ib_vma_close(struct vm_area_struct *area) · 155 unmodified lines
1622	1623	* mlx5_ib_disassociate_ucontext().
1623	1624	*/
1624	1625	mlx5_ib_vma_priv_data->vma = NULL;
	1626	+ mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1625	1627	list_del(&mlx5_ib_vma_priv_data->list);
	1628	+ mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1626	1629	kfree(mlx5_ib_vma_priv_data);
1627	1630	}
1628	1631
@@ -1642,10 +1645,13 @@ static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, · 13 unmodified lines
1642	1645	return -ENOMEM;
1643	1646
1644	1647	vma_prv->vma = vma;
	1648	+ vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1645	1649	vma->vm_private_data = vma_prv;
1646	1650	vma->vm_ops = &mlx5_ib_vm_ops;
1647	1651
	1652	+ mutex_lock(&ctx->vma_private_list_mutex);
1648	1653	list_add(&vma_prv->list, vma_head);
	1654	+ mutex_unlock(&ctx->vma_private_list_mutex);
1649	1655
1650	1656	return 0;
1651	1657	}
@@ -1688,6 +1694,7 @@ static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) · 36 unmodified lines
1688	1694	* mlx5_ib_vma_close.
1689	1695	*/
1690	1696	down_write(&owning_mm->mmap_sem);
	1697	+ mutex_lock(&context->vma_private_list_mutex);
1691	1698	list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1692	1699	list) {
1693	1700	vma = vma_private->vma;
@@ -1702,6 +1709,7 @@ static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) · 8 unmodified lines
1702	1709	list_del(&vma_private->list);
1703	1710	kfree(vma_private);
1704	1711	}
	1712	+ mutex_unlock(&context->vma_private_list_mutex);
1705	1713	up_write(&owning_mm->mmap_sem);
1706	1714	mmput(owning_mm);
1707	1715	put_task_struct(owning_process);
@@ -3735,34 +3743,6 @@ free: · 2027 unmodified lines
3735	3743	return ret;
3736	3744	}
3737	3745
3738		−static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3739		− struct mlx5_ib_port *port,
3740		− struct rdma_hw_stats *stats)
3741		−{
3742		− int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3743		− void *out;
3744		− int ret, i;
3745		− int offset = port->cnts.num_q_counters;
3746		−
3747		− out = kvzalloc(outlen, GFP_KERNEL);
3748		− if (!out)
3749		− return -ENOMEM;
3750		−
3751		− ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3752		− if (ret)
3753		− goto free;
3754		−
3755		− for (i = 0; i < port->cnts.num_cong_counters; i++) {
3756		− stats->value[i + offset] =
3757		− be64_to_cpup((__be64 *)(out +
3758		− port->cnts.offsets[i + offset]));
3759		− }
3760		−
3761		−free:
3762		− kvfree(out);
3763		− return ret;
3764		−}
3765		−
3766	3746	static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3767	3747	struct rdma_hw_stats *stats,
3768	3748	u8 port_num, int index)
@@ -3780,7 +3760,12 @@ static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, · 11 unmodified lines
3780	3760	num_counters = port->cnts.num_q_counters;
3781	3761
3782	3762	if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3783		− ret = mlx5_ib_query_cong_counters(dev, port, stats);
	3763	+ ret = mlx5_lag_query_cong_counters(dev->mdev,
	3764	+ stats->value +
	3765	+ port->cnts.num_q_counters,
	3766	+ port->cnts.num_cong_counters,
	3767	+ port->cnts.offsets +
	3768	+ port->cnts.num_q_counters);
3784	3769	if (ret)
3785	3770	return ret;
3786	3771	num_counters += port->cnts.num_cong_counters;

drivers/infiniband/hw/mlx5/mlx5_ib.h+4−0

@@ -115,6 +115,8 @@ enum { · 114 unmodified lines
115	115	struct mlx5_ib_vma_private_data {
116	116	struct list_head list;
117	117	struct vm_area_struct *vma;
	118	+ /* protect vma_private_list add/del */
	119	+ struct mutex *vma_private_list_mutex;
118	120	};
119	121
120	122	struct mlx5_ib_ucontext {
@@ -129,6 +131,8 @@ struct mlx5_ib_ucontext { · 8 unmodified lines
129	131	/* Transport Domain number */
130	132	u32 tdn;
131	133	struct list_head vma_private_list;
	134	+ /* protect vma_private_list add/del */
	135	+ struct mutex vma_private_list_mutex;
132	136
133	137	unsigned long upd_xlt_page;
134	138	/* protect ODP/KSM */

drivers/infiniband/hw/mlx5/mr.c+1−0

@@ -1640,6 +1640,7 @@ struct ib_mr mlx5_ib_alloc_mr(struct ib_pd pd, · 1639 unmodified lines
1640	1640	MLX5_SET(mkc, mkc, access_mode, mr->access_mode);
1641	1641	MLX5_SET(mkc, mkc, umr_en, 1);
1642	1642
	1643	+ mr->ibmr.device = pd->device;
1643	1644	err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1644	1645	if (err)
1645	1646	goto err_destroy_psv;

drivers/infiniband/hw/vmw_pvrdma/pvrdma.h+5−5

@@ -93,8 +93,8 @@ struct pvrdma_cq { · 92 unmodified lines
93	93	struct pvrdma_page_dir pdir;
94	94	u32 cq_handle;
95	95	bool is_kernel;
96		− atomic_t refcnt;
97		− wait_queue_head_t wait;
	96	+ refcount_t refcnt;
	97	+ struct completion free;
98	98	};
99	99
100	100	struct pvrdma_id_table {
@@ -175,7 +175,7 @@ struct pvrdma_srq { · 74 unmodified lines
175	175	u32 srq_handle;
176	176	int npages;
177	177	refcount_t refcnt;
178		− wait_queue_head_t wait;
	178	+ struct completion free;
179	179	};
180	180
181	181	struct pvrdma_qp {
@@ -196,8 +196,8 @@ struct pvrdma_qp { · 14 unmodified lines
196	196	u8 state;
197	197	bool is_kernel;
198	198	struct mutex mutex; /* QP state mutex. */
199		− atomic_t refcnt;
200		− wait_queue_head_t wait;
	199	+ refcount_t refcnt;
	200	+ struct completion free;
201	201	};
202	202
203	203	struct pvrdma_dev {

drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c+9−9

@@ -132,8 +132,9 @@ struct ib_cq pvrdma_create_cq(struct ib_device ibdev, · 131 unmodified lines
132	132	}
133	133
134	134	cq->ibcq.cqe = entries;
	135	+ cq->is_kernel = !context;
135	136
136		− if (context) {
	137	+ if (!cq->is_kernel) {
137	138	if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
138	139	ret = -EFAULT;
139	140	goto err_cq;
@@ -148,8 +149,6 @@ struct ib_cq pvrdma_create_cq(struct ib_device ibdev, · 8 unmodified lines
148	149
149	150	npages = ib_umem_page_count(cq->umem);
150	151	} else {
151		− cq->is_kernel = true;
152		−
153	152	/* One extra page for shared ring state */
154	153	npages = 1 + (entries * sizeof(struct pvrdma_cqe) +
155	154	PAGE_SIZE - 1) / PAGE_SIZE;
@@ -178,8 +177,8 @@ struct ib_cq pvrdma_create_cq(struct ib_device ibdev, · 22 unmodified lines
178	177	else
179	178	pvrdma_page_dir_insert_umem(&cq->pdir, cq->umem, 0);
180	179
181		− atomic_set(&cq->refcnt, 1);
182		− init_waitqueue_head(&cq->wait);
	180	+ refcount_set(&cq->refcnt, 1);
	181	+ init_completion(&cq->free);
183	182	spin_lock_init(&cq->cq_lock);
184	183
185	184	memset(cmd, 0, sizeof(*cmd));
@@ -202,7 +201,7 @@ struct ib_cq pvrdma_create_cq(struct ib_device ibdev, · 16 unmodified lines
202	201	dev->cq_tbl[cq->cq_handle % dev->dsr->caps.max_cq] = cq;
203	202	spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
204	203
205		− if (context) {
	204	+ if (!cq->is_kernel) {
206	205	cq->uar = &(to_vucontext(context)->uar);
207	206
208	207	/* Copy udata back. */
@@ -219,7 +218,7 @@ struct ib_cq pvrdma_create_cq(struct ib_device ibdev, · 10 unmodified lines
219	218	err_page_dir:
220	219	pvrdma_page_dir_cleanup(dev, &cq->pdir);
221	220	err_umem:
222		− if (context)
	221	+ if (!cq->is_kernel)
223	222	ib_umem_release(cq->umem);
224	223	err_cq:
225	224	atomic_dec(&dev->num_cqs);
@@ -230,8 +229,9 @@ err_cq: · 4 unmodified lines
230	229
231	230	static void pvrdma_free_cq(struct pvrdma_dev dev, struct pvrdma_cq cq)
232	231	{
233		− atomic_dec(&cq->refcnt);
234		− wait_event(cq->wait, !atomic_read(&cq->refcnt));
	232	+ if (refcount_dec_and_test(&cq->refcnt))
	233	+ complete(&cq->free);
	234	+ wait_for_completion(&cq->free);
235	235
236	236	if (!cq->is_kernel)
237	237	ib_umem_release(cq->umem);

drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c+12−15

@@ -243,13 +243,13 @@ static int pvrdma_register_device(struct pvrdma_dev *dev) · 242 unmodified lines
243	243	mutex_init(&dev->port_mutex);
244	244	spin_lock_init(&dev->desc_lock);
245	245
246		− dev->cq_tbl = kcalloc(dev->dsr->caps.max_cq, sizeof(void *),
	246	+ dev->cq_tbl = kcalloc(dev->dsr->caps.max_cq, sizeof(struct pvrdma_cq *),
247	247	GFP_KERNEL);
248	248	if (!dev->cq_tbl)
249	249	return ret;
250	250	spin_lock_init(&dev->cq_tbl_lock);
251	251
252		− dev->qp_tbl = kcalloc(dev->dsr->caps.max_qp, sizeof(void *),
	252	+ dev->qp_tbl = kcalloc(dev->dsr->caps.max_qp, sizeof(struct pvrdma_qp *),
253	253	GFP_KERNEL);
254	254	if (!dev->qp_tbl)
255	255	goto err_cq_free;
@@ -333,7 +333,7 @@ static void pvrdma_qp_event(struct pvrdma_dev *dev, u32 qpn, int type) · 77 unmodified lines
333	333	spin_lock_irqsave(&dev->qp_tbl_lock, flags);
334	334	qp = dev->qp_tbl[qpn % dev->dsr->caps.max_qp];
335	335	if (qp)
336		− atomic_inc(&qp->refcnt);
	336	+ refcount_inc(&qp->refcnt);
337	337	spin_unlock_irqrestore(&dev->qp_tbl_lock, flags);
338	338
339	339	if (qp && qp->ibqp.event_handler) {
@@ -346,9 +346,8 @@ static void pvrdma_qp_event(struct pvrdma_dev *dev, u32 qpn, int type) · 6 unmodified lines
346	346	ibqp->event_handler(&e, ibqp->qp_context);
347	347	}
348	348	if (qp) {
349		− atomic_dec(&qp->refcnt);
350		− if (atomic_read(&qp->refcnt) == 0)
351		− wake_up(&qp->wait);
	349	+ if (refcount_dec_and_test(&qp->refcnt))
	350	+ complete(&qp->free);
352	351	}
353	352	}
354	353
@@ -360,7 +359,7 @@ static void pvrdma_cq_event(struct pvrdma_dev *dev, u32 cqn, int type) · 5 unmodified lines
360	359	spin_lock_irqsave(&dev->cq_tbl_lock, flags);
361	360	cq = dev->cq_tbl[cqn % dev->dsr->caps.max_cq];
362	361	if (cq)
363		− atomic_inc(&cq->refcnt);
	362	+ refcount_inc(&cq->refcnt);
364	363	spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
365	364
366	365	if (cq && cq->ibcq.event_handler) {
@@ -373,9 +372,8 @@ static void pvrdma_cq_event(struct pvrdma_dev *dev, u32 cqn, int type) · 6 unmodified lines
373	372	ibcq->event_handler(&e, ibcq->cq_context);
374	373	}
375	374	if (cq) {
376		− atomic_dec(&cq->refcnt);
377		− if (atomic_read(&cq->refcnt) == 0)
378		− wake_up(&cq->wait);
	375	+ if (refcount_dec_and_test(&cq->refcnt))
	376	+ complete(&cq->free);
379	377	}
380	378	}
381	379
@@ -404,7 +402,7 @@ static void pvrdma_srq_event(struct pvrdma_dev *dev, u32 srqn, int type) · 22 unmodified lines
404	402	}
405	403	if (srq) {
406	404	if (refcount_dec_and_test(&srq->refcnt))
407		− wake_up(&srq->wait);
	405	+ complete(&srq->free);
408	406	}
409	407	}
410	408
@@ -533,15 +531,14 @@ static irqreturn_t pvrdma_intrx_handler(int irq, void *dev_id) · 122 unmodified lines
533	531	spin_lock_irqsave(&dev->cq_tbl_lock, flags);
534	532	cq = dev->cq_tbl[cqne->info % dev->dsr->caps.max_cq];
535	533	if (cq)
536		− atomic_inc(&cq->refcnt);
	534	+ refcount_inc(&cq->refcnt);
537	535	spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
538	536
539	537	if (cq && cq->ibcq.comp_handler)
540	538	cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
541	539	if (cq) {
542		− atomic_dec(&cq->refcnt);
543		− if (atomic_read(&cq->refcnt))
544		− wake_up(&cq->wait);
	540	+ if (refcount_dec_and_test(&cq->refcnt))
	541	+ complete(&cq->free);
545	542	}
546	543	pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
547	544	}

drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c+15−8

@@ -245,12 +245,13 @@ struct ib_qp pvrdma_create_qp(struct ib_pd pd, · 244 unmodified lines
245	245	spin_lock_init(&qp->sq.lock);
246	246	spin_lock_init(&qp->rq.lock);
247	247	mutex_init(&qp->mutex);
248		− atomic_set(&qp->refcnt, 1);
249		− init_waitqueue_head(&qp->wait);
	248	+ refcount_set(&qp->refcnt, 1);
	249	+ init_completion(&qp->free);
250	250
251	251	qp->state = IB_QPS_RESET;
	252	+ qp->is_kernel = !(pd->uobject && udata);
252	253
253		− if (pd->uobject && udata) {
	254	+ if (!qp->is_kernel) {
254	255	dev_dbg(&dev->pdev->dev,
255	256	"create queuepair from user space\n");
256	257
@@ -291,8 +292,6 @@ struct ib_qp pvrdma_create_qp(struct ib_pd pd, · 34 unmodified lines
291	292	qp->npages_recv = 0;
292	293	qp->npages = qp->npages_send + qp->npages_recv;
293	294	} else {
294		− qp->is_kernel = true;
295		−
296	295	ret = pvrdma_set_sq_size(to_vdev(pd->device),
297	296	&init_attr->cap, qp);
298	297	if (ret)
@@ -394,7 +393,7 @@ struct ib_qp pvrdma_create_qp(struct ib_pd pd, · 95 unmodified lines
394	393	err_pdir:
395	394	pvrdma_page_dir_cleanup(dev, &qp->pdir);
396	395	err_umem:
397		− if (pd->uobject && udata) {
	396	+ if (!qp->is_kernel) {
398	397	if (qp->rumem)
399	398	ib_umem_release(qp->rumem);
400	399	if (qp->sumem)
@@ -428,8 +427,16 @@ static void pvrdma_free_qp(struct pvrdma_qp *qp) · 27 unmodified lines
428	427
429	428	pvrdma_unlock_cqs(scq, rcq, &scq_flags, &rcq_flags);
430	429
431		− atomic_dec(&qp->refcnt);
432		− wait_event(qp->wait, !atomic_read(&qp->refcnt));
	430	+ if (refcount_dec_and_test(&qp->refcnt))
	431	+ complete(&qp->free);
	432	+ wait_for_completion(&qp->free);
	433	+
	434	+ if (!qp->is_kernel) {
	435	+ if (qp->rumem)
	436	+ ib_umem_release(qp->rumem);
	437	+ if (qp->sumem)
	438	+ ib_umem_release(qp->sumem);
	439	+ }
433	440
434	441	pvrdma_page_dir_cleanup(dev, &qp->pdir);
435	442

drivers/infiniband/hw/vmw_pvrdma/pvrdma_srq.c+4−3

@@ -149,7 +149,7 @@ struct ib_srq pvrdma_create_srq(struct ib_pd pd, · 148 unmodified lines
149	149
150	150	spin_lock_init(&srq->lock);
151	151	refcount_set(&srq->refcnt, 1);
152		− init_waitqueue_head(&srq->wait);
	152	+ init_completion(&srq->free);
153	153
154	154	dev_dbg(&dev->pdev->dev,
155	155	"create shared receive queue from user space\n");
@@ -236,8 +236,9 @@ static void pvrdma_free_srq(struct pvrdma_dev dev, struct pvrdma_srq srq) · 80 unmodified lines
236	236	dev->srq_tbl[srq->srq_handle] = NULL;
237	237	spin_unlock_irqrestore(&dev->srq_tbl_lock, flags);
238	238
239		− refcount_dec(&srq->refcnt);
240		− wait_event(srq->wait, !refcount_read(&srq->refcnt));
	239	+ if (refcount_dec_and_test(&srq->refcnt))
	240	+ complete(&srq->free);
	241	+ wait_for_completion(&srq->free);
241	242
242	243	/* There is no support for kernel clients, so this is safe. */
243	244	ib_umem_release(srq->umem);

drivers/infiniband/ulp/ipoib/ipoib_cm.c+1−0

@@ -1145,6 +1145,7 @@ static int ipoib_cm_tx_init(struct ipoib_cm_tx *p, u32 qpn, · 1144 unmodified lines
1145	1145	noio_flag = memalloc_noio_save();
1146	1146	p->tx_ring = vzalloc(ipoib_sendq_size * sizeof(*p->tx_ring));
1147	1147	if (!p->tx_ring) {
	1148	+ memalloc_noio_restore(noio_flag);
1148	1149	ret = -ENOMEM;
1149	1150	goto err_tx;
1150	1151	}

drivers/infiniband/ulp/ipoib/ipoib_ib.c+3−4

@@ -1235,13 +1235,10 @@ static void __ipoib_ib_dev_flush(struct ipoib_dev_priv *priv, · 1234 unmodified lines
1235	1235	ipoib_ib_dev_down(dev);
1236	1236
1237	1237	if (level == IPOIB_FLUSH_HEAVY) {
1238		− rtnl_lock();
1239	1238	if (test_bit(IPOIB_FLAG_INITIALIZED, &priv->flags))
1240	1239	ipoib_ib_dev_stop(dev);
1241	1240
1242		− result = ipoib_ib_dev_open(dev);
1243		− rtnl_unlock();
1244		− if (result)
	1241	+ if (ipoib_ib_dev_open(dev))
1245	1242	return;
1246	1243
1247	1244	if (netif_queue_stopped(dev))
@@ -1281,7 +1278,9 @@ void ipoib_ib_dev_flush_heavy(struct work_struct *work) · 33 unmodified lines
1281	1278	struct ipoib_dev_priv *priv =
1282	1279	container_of(work, struct ipoib_dev_priv, flush_heavy);
1283	1280
	1281	+ rtnl_lock();
1284	1282	__ipoib_ib_dev_flush(priv, IPOIB_FLUSH_HEAVY, 0);
	1283	+ rtnl_unlock();
1285	1284	}
1286	1285
1287	1286	void ipoib_ib_dev_cleanup(struct net_device *dev)

drivers/net/ethernet/mellanox/mlx5/core/lag.c+56−0

@@ -137,6 +137,17 @@ int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev) · 136 unmodified lines
137	137	}
138	138	EXPORT_SYMBOL(mlx5_cmd_destroy_vport_lag);
139	139
	140	+static int mlx5_cmd_query_cong_counter(struct mlx5_core_dev *dev,
	141	+ bool reset, void *out, int out_size)
	142	+{
	143	+ u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)] = { };
	144	+
	145	+ MLX5_SET(query_cong_statistics_in, in, opcode,
	146	+ MLX5_CMD_OP_QUERY_CONG_STATISTICS);
	147	+ MLX5_SET(query_cong_statistics_in, in, clear, reset);
	148	+ return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size);
	149	+}
	150	+
140	151	static struct mlx5_lag mlx5_lag_dev_get(struct mlx5_core_dev dev)
141	152	{
142	153	return dev->priv.lag;
@@ -633,3 +644,48 @@ bool mlx5_lag_intf_add(struct mlx5_interface intf, struct mlx5_priv priv) · 490 unmodified lines
633	644	/* If bonded, we do not add an IB device for PF1. */
634	645	return false;
635	646	}
	647	+
	648	+int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
	649	+ u64 *values,
	650	+ int num_counters,
	651	+ size_t *offsets)
	652	+{
	653	+ int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
	654	+ struct mlx5_core_dev *mdev[MLX5_MAX_PORTS];
	655	+ struct mlx5_lag *ldev;
	656	+ int num_ports;
	657	+ int ret, i, j;
	658	+ void *out;
	659	+
	660	+ out = kvzalloc(outlen, GFP_KERNEL);
	661	+ if (!out)
	662	+ return -ENOMEM;
	663	+
	664	+ memset(values, 0, sizeof(values) num_counters);
	665	+
	666	+ mutex_lock(&lag_mutex);
	667	+ ldev = mlx5_lag_dev_get(dev);
	668	+ if (ldev && mlx5_lag_is_bonded(ldev)) {
	669	+ num_ports = MLX5_MAX_PORTS;
	670	+ mdev[0] = ldev->pf[0].dev;
	671	+ mdev[1] = ldev->pf[1].dev;
	672	+ } else {
	673	+ num_ports = 1;
	674	+ mdev[0] = dev;
	675	+ }
	676	+
	677	+ for (i = 0; i < num_ports; ++i) {
	678	+ ret = mlx5_cmd_query_cong_counter(mdev[i], false, out, outlen);
	679	+ if (ret)
	680	+ goto unlock;
	681	+
	682	+ for (j = 0; j < num_counters; ++j)
	683	+ values[j] += be64_to_cpup((__be64 *)(out + offsets[j]));
	684	+ }
	685	+
	686	+unlock:
	687	+ mutex_unlock(&lag_mutex);
	688	+ kvfree(out);
	689	+ return ret;
	690	+}
	691	+EXPORT_SYMBOL(mlx5_lag_query_cong_counters);

include/linux/mlx5/driver.h+4−0

@@ -1164,6 +1164,10 @@ int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); · 1163 unmodified lines
1164	1164	int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1165	1165	bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1166	1166	struct net_device mlx5_lag_get_roce_netdev(struct mlx5_core_dev dev);
	1167	+int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
	1168	+ u64 *values,
	1169	+ int num_counters,
	1170	+ size_t *offsets);
1167	1171	struct mlx5_uars_page mlx5_get_uars_page(struct mlx5_core_dev mdev);
1168	1172	void mlx5_put_uars_page(struct mlx5_core_dev mdev, struct mlx5_uars_page up);
1169	1173

include/uapi/rdma/vmw_pvrdma-abi.h+7−5

@@ -52,12 +52,14 @@ · 51 unmodified lines
52	52	#define PVRDMA_UVERBS_ABI_VERSION 3 /* ABI Version. */
53	53	#define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF /* Bottom 24 bits. */
54	54	#define PVRDMA_UAR_QP_OFFSET 0 /* QP doorbell. */
55		−#define PVRDMA_UAR_QP_SEND BIT(30) /* Send bit. */
56		−#define PVRDMA_UAR_QP_RECV BIT(31) /* Recv bit. */
	55	+#define PVRDMA_UAR_QP_SEND (1 << 30) /* Send bit. */
	56	+#define PVRDMA_UAR_QP_RECV (1 << 31) /* Recv bit. */
57	57	#define PVRDMA_UAR_CQ_OFFSET 4 /* CQ doorbell. */
58		−#define PVRDMA_UAR_CQ_ARM_SOL BIT(29) /* Arm solicited bit. */
59		−#define PVRDMA_UAR_CQ_ARM BIT(30) /* Arm bit. */
60		−#define PVRDMA_UAR_CQ_POLL BIT(31) /* Poll bit. */
	58	+#define PVRDMA_UAR_CQ_ARM_SOL (1 << 29) /* Arm solicited bit. */
	59	+#define PVRDMA_UAR_CQ_ARM (1 << 30) /* Arm bit. */
	60	+#define PVRDMA_UAR_CQ_POLL (1 << 31) /* Poll bit. */
	61	+#define PVRDMA_UAR_SRQ_OFFSET 8 /* SRQ doorbell. */
	62	+#define PVRDMA_UAR_SRQ_RECV (1 << 30) /* Recv bit. */
61	63
62	64	enum pvrdma_wr_opcode {
63	65	PVRDMA_WR_RDMA_WRITE,

Merge branch 'from-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git

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