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riscv: Setup exception vector for nommu platform

Exception vector is missing on nommu platform and that is an issue. This patch is tested in Sipeed Maix Bit Dev Board.

Qiu Wenbo committed 6 years ago

Commit 76d44671 parent dbf83811 file · +17 −8Browse files

Unified · Split

arch/riscv/kernel/head.S+17−8
@@ -77,16 +77,10 @@ relocate: · 76 unmodified lines
77 csrw CSR_SATP, a077 csrw CSR_SATP, a0
78.align 278.align 2
791:791:
80 /* Set trap vector to exception handler */80 /* Set trap vector to spin forever to help debug */
81 la a0, handle_exception81 la a0, .Lsecondary_park
82 csrw CSR_TVEC, a082 csrw CSR_TVEC, a0
83 83
84 /*
85 * Set sup0 scratch register to 0, indicating to exception vector that
86 * we are presently executing in kernel.
87 */
88 csrw CSR_SCRATCH, zero
89
90 /* Reload the global pointer */84 /* Reload the global pointer */
91.option push85.option push
92.option norelax86.option norelax
@@ -144,9 +138,23 @@ secondary_start_common: · 51 unmodified lines
144 la a0, swapper_pg_dir138 la a0, swapper_pg_dir
145 call relocate139 call relocate
146#endif140#endif
141 call setup_trap_vector
147 tail smp_callin142 tail smp_callin
148#endif /* CONFIG_SMP */143#endif /* CONFIG_SMP */
149 144
145.align 2
146setup_trap_vector:
147 /* Set trap vector to exception handler */
148 la a0, handle_exception
149 csrw CSR_TVEC, a0
150
151 /*
152 * Set sup0 scratch register to 0, indicating to exception vector that
153 * we are presently executing in kernel.
154 */
155 csrw CSR_SCRATCH, zero
156 ret
157
150.Lsecondary_park:158.Lsecondary_park:
151 /* We lack SMP support or have too many harts, so park this hart */159 /* We lack SMP support or have too many harts, so park this hart */
152 wfi160 wfi
@@ -240,6 +248,7 @@ clear_bss_done: · 87 unmodified lines
240 call relocate248 call relocate
241#endif /* CONFIG_MMU */249#endif /* CONFIG_MMU */
242 250
251 call setup_trap_vector
243 /* Restore C environment */252 /* Restore C environment */
244 la tp, init_task253 la tp, init_task
245 sw zero, TASK_TI_CPU(tp)254 sw zero, TASK_TI_CPU(tp)

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