Perf measurements rely on CPU and engine timestamps to correlate events of interest across these time domains. Current mechanisms get these timestamps separately and the calculated delta between these timestamps lack enough accuracy. To improve the accuracy of these time measurements to within a few us, add a query that returns the engine and cpu timestamps captured as close to each other as possible. Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24591 v2: - Fix kernel-doc warnings (CI) - Document input params and group them together (Jose) - s/cs/engine/ (Jose) - Remove padding in the query (Ashutosh)
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| @@ -128,6 +128,25 @@ struct xe_user_extension { · 127 unmodified lines | ||
| 128 | 128 | #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) |
| 129 | 129 | #define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise) |
| 130 | 130 | |
| 131 | +/** struct drm_xe_engine_class_instance - instance of an engine class */ | |
| 132 | +struct drm_xe_engine_class_instance { | |
| 133 | +#define DRM_XE_ENGINE_CLASS_RENDER 0 | |
| 134 | +#define DRM_XE_ENGINE_CLASS_COPY 1 | |
| 135 | +#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 | |
| 136 | +#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 | |
| 137 | +#define DRM_XE_ENGINE_CLASS_COMPUTE 4 | |
| 138 | + /* | |
| 139 | + * Kernel only class (not actual hardware engine class). Used for | |
| 140 | + * creating ordered queues of VM bind operations. | |
| 141 | + */ | |
| 142 | +#define DRM_XE_ENGINE_CLASS_VM_BIND 5 | |
| 143 | + __u16 engine_class; | |
| 144 | + | |
| 145 | + __u16 engine_instance; | |
| 146 | + __u16 gt_id; | |
| 147 | + __u16 rsvd; | |
| 148 | +}; | |
| 149 | + | |
| 131 | 150 | /** |
| 132 | 151 | * enum drm_xe_memory_class - Supported memory classes. |
| 133 | 152 | */ |
| @@ -219,6 +238,60 @@ struct drm_xe_query_mem_region { · 85 unmodified lines | ||
| 219 | 238 | __u64 reserved[6]; |
| 220 | 239 | }; |
| 221 | 240 | |
| 241 | +/** | |
| 242 | + * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps | |
| 243 | + * | |
| 244 | + * If a query is made with a struct drm_xe_device_query where .query is equal to | |
| 245 | + * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles | |
| 246 | + * in .data. struct drm_xe_query_engine_cycles is allocated by the user and | |
| 247 | + * .data points to this allocated structure. | |
| 248 | + * | |
| 249 | + * The query returns the engine cycles and the frequency that can | |
| 250 | + * be used to calculate the engine timestamp. In addition the | |
| 251 | + * query returns a set of cpu timestamps that indicate when the command | |
| 252 | + * streamer cycle count was captured. | |
| 253 | + */ | |
| 254 | +struct drm_xe_query_engine_cycles { | |
| 255 | + /** | |
| 256 | + * @eci: This is input by the user and is the engine for which command | |
| 257 | + * streamer cycles is queried. | |
| 258 | + */ | |
| 259 | + struct drm_xe_engine_class_instance eci; | |
| 260 | + | |
| 261 | + /** | |
| 262 | + * @clockid: This is input by the user and is the reference clock id for | |
| 263 | + * CPU timestamp. For definition, see clock_gettime(2) and | |
| 264 | + * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, | |
| 265 | + * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. | |
| 266 | + */ | |
| 267 | + __s32 clockid; | |
| 268 | + | |
| 269 | + /** @width: Width of the engine cycle counter in bits. */ | |
| 270 | + __u32 width; | |
| 271 | + | |
| 272 | + /** | |
| 273 | + * @engine_cycles: Engine cycles as read from its register | |
| 274 | + * at 0x358 offset. | |
| 275 | + */ | |
| 276 | + __u64 engine_cycles; | |
| 277 | + | |
| 278 | + /** @engine_frequency: Frequency of the engine cycles in Hz. */ | |
| 279 | + __u64 engine_frequency; | |
| 280 | + | |
| 281 | + /** | |
| 282 | + * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before | |
| 283 | + * reading the engine_cycles register using the reference clockid set by the | |
| 284 | + * user. | |
| 285 | + */ | |
| 286 | + __u64 cpu_timestamp; | |
| 287 | + | |
| 288 | + /** | |
| 289 | + * @cpu_delta: Time delta in ns captured around reading the lower dword | |
| 290 | + * of the engine_cycles register. | |
| 291 | + */ | |
| 292 | + __u64 cpu_delta; | |
| 293 | +}; | |
| 294 | + | |
| 222 | 295 | /** |
| 223 | 296 | * struct drm_xe_query_mem_usage - describe memory regions and usage |
| 224 | 297 | * |
| @@ -385,12 +458,13 @@ struct drm_xe_device_query { · 160 unmodified lines | ||
| 385 | 458 | /** @extensions: Pointer to the first extension struct, if any */ |
| 386 | 459 | __u64 extensions; |
| 387 | 460 | |
| 388 | −#define DRM_XE_DEVICE_QUERY_ENGINES 0 | |
| 389 | −#define DRM_XE_DEVICE_QUERY_MEM_USAGE 1 | |
| 390 | −#define DRM_XE_DEVICE_QUERY_CONFIG 2 | |
| 391 | −#define DRM_XE_DEVICE_QUERY_GTS 3 | |
| 392 | −#define DRM_XE_DEVICE_QUERY_HWCONFIG 4 | |
| 393 | −#define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 | |
| 461 | +#define DRM_XE_DEVICE_QUERY_ENGINES 0 | |
| 462 | +#define DRM_XE_DEVICE_QUERY_MEM_USAGE 1 | |
| 463 | +#define DRM_XE_DEVICE_QUERY_CONFIG 2 | |
| 464 | +#define DRM_XE_DEVICE_QUERY_GTS 3 | |
| 465 | +#define DRM_XE_DEVICE_QUERY_HWCONFIG 4 | |
| 466 | +#define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 | |
| 467 | +#define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 | |
| 394 | 468 | /** @query: The type of data to query */ |
| 395 | 469 | __u32 query; |
| 396 | 470 | |
| @@ -732,24 +806,6 @@ struct drm_xe_exec_queue_set_property { · 335 unmodified lines | ||
| 732 | 806 | __u64 reserved[2]; |
| 733 | 807 | }; |
| 734 | 808 | |
| 735 | −/** struct drm_xe_engine_class_instance - instance of an engine class */ | |
| 736 | −struct drm_xe_engine_class_instance { | |
| 737 | −#define DRM_XE_ENGINE_CLASS_RENDER 0 | |
| 738 | −#define DRM_XE_ENGINE_CLASS_COPY 1 | |
| 739 | −#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 | |
| 740 | −#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 | |
| 741 | −#define DRM_XE_ENGINE_CLASS_COMPUTE 4 | |
| 742 | − /* | |
| 743 | − * Kernel only class (not actual hardware engine class). Used for | |
| 744 | − * creating ordered queues of VM bind operations. | |
| 745 | − */ | |
| 746 | −#define DRM_XE_ENGINE_CLASS_VM_BIND 5 | |
| 747 | − __u16 engine_class; | |
| 748 | − | |
| 749 | − __u16 engine_instance; | |
| 750 | − __u16 gt_id; | |
| 751 | −}; | |
| 752 | − | |
| 753 | 809 | struct drm_xe_exec_queue_create { |
| 754 | 810 | #define XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 |
| 755 | 811 | /** @extensions: Pointer to the first extension struct, if any */ |