Add and use #defines for PCI-X Capability registers and fields. Note that the PCI-X Capability has a different layout for type 0 (endpoint) and type 1 (bridge) devices.
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| @@ -349,7 +349,7 @@ · 348 unmodified lines | ||
| 349 | 349 | #define PCI_AF_STATUS_TP 0x01 |
| 350 | 350 | #define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ |
| 351 | 351 | |
| 352 | −/* PCI-X registers */ | |
| 352 | +/* PCI-X registers (Type 0 (non-bridge) devices) */ | |
| 353 | 353 | |
| 354 | 354 | #define PCI_X_CMD 2 /* Modes & Features */ |
| 355 | 355 | #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ |
| @@ -389,6 +389,19 @@ · 33 unmodified lines | ||
| 389 | 389 | #define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ |
| 390 | 390 | #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ |
| 391 | 391 | |
| 392 | +/* PCI-X registers (Type 1 (bridge) devices) */ | |
| 393 | + | |
| 394 | +#define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */ | |
| 395 | +#define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */ | |
| 396 | +#define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */ | |
| 397 | +#define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */ | |
| 398 | +#define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */ | |
| 399 | +#define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */ | |
| 400 | +#define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */ | |
| 401 | +#define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */ | |
| 402 | +#define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */ | |
| 403 | +#define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */ | |
| 404 | + | |
| 392 | 405 | /* PCI Bridge Subsystem ID registers */ |
| 393 | 406 | |
| 394 | 407 | #define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */ |