Hexagon requires that register predicates in assembly be parenthesized.
Unified · Split
| @@ -91,7 +91,7 @@ static inline void atomic_##op(int i, atomic_t *v) \ · 90 unmodified lines | |||
| 91 | "1: %0 = memw_locked(%1);\n" \ | 91 | "1: %0 = memw_locked(%1);\n" \ |
| 92 | " %0 = "#op "(%0,%2);\n" \ | 92 | " %0 = "#op "(%0,%2);\n" \ |
| 93 | " memw_locked(%1,P3)=%0;\n" \ | 93 | " memw_locked(%1,P3)=%0;\n" \ |
| 94 | " if !P3 jump 1b;\n" \ | 94 | " if (!P3) jump 1b;\n" \ |
| 95 | : "=&r" (output) \ | 95 | : "=&r" (output) \ |
| 96 | : "r" (&v->counter), "r" (i) \ | 96 | : "r" (&v->counter), "r" (i) \ |
| 97 | : "memory", "p3" \ | 97 | : "memory", "p3" \ |
| @@ -107,7 +107,7 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \ · 9 unmodified lines | |||
| 107 | "1: %0 = memw_locked(%1);\n" \ | 107 | "1: %0 = memw_locked(%1);\n" \ |
| 108 | " %0 = "#op "(%0,%2);\n" \ | 108 | " %0 = "#op "(%0,%2);\n" \ |
| 109 | " memw_locked(%1,P3)=%0;\n" \ | 109 | " memw_locked(%1,P3)=%0;\n" \ |
| 110 | " if !P3 jump 1b;\n" \ | 110 | " if (!P3) jump 1b;\n" \ |
| 111 | : "=&r" (output) \ | 111 | : "=&r" (output) \ |
| 112 | : "r" (&v->counter), "r" (i) \ | 112 | : "r" (&v->counter), "r" (i) \ |
| 113 | : "memory", "p3" \ | 113 | : "memory", "p3" \ |
| @@ -124,7 +124,7 @@ static inline int atomic_fetch_##op(int i, atomic_t *v) \ · 10 unmodified lines | |||
| 124 | "1: %0 = memw_locked(%2);\n" \ | 124 | "1: %0 = memw_locked(%2);\n" \ |
| 125 | " %1 = "#op "(%0,%3);\n" \ | 125 | " %1 = "#op "(%0,%3);\n" \ |
| 126 | " memw_locked(%2,P3)=%1;\n" \ | 126 | " memw_locked(%2,P3)=%1;\n" \ |
| 127 | " if !P3 jump 1b;\n" \ | 127 | " if (!P3) jump 1b;\n" \ |
| 128 | : "=&r" (output), "=&r" (val) \ | 128 | : "=&r" (output), "=&r" (val) \ |
| 129 | : "r" (&v->counter), "r" (i) \ | 129 | : "r" (&v->counter), "r" (i) \ |
| 130 | : "memory", "p3" \ | 130 | : "memory", "p3" \ |
| @@ -173,7 +173,7 @@ static inline int atomic_fetch_add_unless(atomic_t *v, int a, int u) · 42 unmodified lines | |||
| 173 | " }" | 173 | " }" |
| 174 | " memw_locked(%2, p3) = %1;" | 174 | " memw_locked(%2, p3) = %1;" |
| 175 | " {" | 175 | " {" |
| 176 | " if !p3 jump 1b;" | 176 | " if (!p3) jump 1b;" |
| 177 | " }" | 177 | " }" |
| 178 | "2:" | 178 | "2:" |
| 179 | : "=&r" (__oldval), "=&r" (tmp) | 179 | : "=&r" (__oldval), "=&r" (tmp) |
| @@ -38,7 +38,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) · 37 unmodified lines | |||
| 38 | "1: R12 = memw_locked(R10);\n" | 38 | "1: R12 = memw_locked(R10);\n" |
| 39 | " { P0 = tstbit(R12,R11); R12 = clrbit(R12,R11); }\n" | 39 | " { P0 = tstbit(R12,R11); R12 = clrbit(R12,R11); }\n" |
| 40 | " memw_locked(R10,P1) = R12;\n" | 40 | " memw_locked(R10,P1) = R12;\n" |
| 41 | " {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n" | 41 | " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" |
| 42 | : "=&r" (oldval) | 42 | : "=&r" (oldval) |
| 43 | : "r" (addr), "r" (nr) | 43 | : "r" (addr), "r" (nr) |
| 44 | : "r10", "r11", "r12", "p0", "p1", "memory" | 44 | : "r10", "r11", "r12", "p0", "p1", "memory" |
| @@ -62,7 +62,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr) · 17 unmodified lines | |||
| 62 | "1: R12 = memw_locked(R10);\n" | 62 | "1: R12 = memw_locked(R10);\n" |
| 63 | " { P0 = tstbit(R12,R11); R12 = setbit(R12,R11); }\n" | 63 | " { P0 = tstbit(R12,R11); R12 = setbit(R12,R11); }\n" |
| 64 | " memw_locked(R10,P1) = R12;\n" | 64 | " memw_locked(R10,P1) = R12;\n" |
| 65 | " {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n" | 65 | " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" |
| 66 | : "=&r" (oldval) | 66 | : "=&r" (oldval) |
| 67 | : "r" (addr), "r" (nr) | 67 | : "r" (addr), "r" (nr) |
| 68 | : "r10", "r11", "r12", "p0", "p1", "memory" | 68 | : "r10", "r11", "r12", "p0", "p1", "memory" |
| @@ -88,7 +88,7 @@ static inline int test_and_change_bit(int nr, volatile void *addr) · 19 unmodified lines | |||
| 88 | "1: R12 = memw_locked(R10);\n" | 88 | "1: R12 = memw_locked(R10);\n" |
| 89 | " { P0 = tstbit(R12,R11); R12 = togglebit(R12,R11); }\n" | 89 | " { P0 = tstbit(R12,R11); R12 = togglebit(R12,R11); }\n" |
| 90 | " memw_locked(R10,P1) = R12;\n" | 90 | " memw_locked(R10,P1) = R12;\n" |
| 91 | " {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n" | 91 | " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" |
| 92 | : "=&r" (oldval) | 92 | : "=&r" (oldval) |
| 93 | : "r" (addr), "r" (nr) | 93 | : "r" (addr), "r" (nr) |
| 94 | : "r10", "r11", "r12", "p0", "p1", "memory" | 94 | : "r10", "r11", "r12", "p0", "p1", "memory" |
| @@ -223,7 +223,7 @@ static inline int ffs(int x) · 128 unmodified lines | |||
| 223 | int r; | 223 | int r; |
| 224 | 224 | ||
| 225 | asm("{ P0 = cmp.eq(%1,#0); %0 = ct0(%1);}\n" | 225 | asm("{ P0 = cmp.eq(%1,#0); %0 = ct0(%1);}\n" |
| 226 | "{ if P0 %0 = #0; if !P0 %0 = add(%0,#1);}\n" | 226 | "{ if (P0) %0 = #0; if (!P0) %0 = add(%0,#1);}\n" |
| 227 | : "=&r" (r) | 227 | : "=&r" (r) |
| 228 | : "r" (x) | 228 | : "r" (x) |
| 229 | : "p0"); | 229 | : "p0"); |
| @@ -30,7 +30,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, · 29 unmodified lines | |||
| 30 | __asm__ __volatile__ ( | 30 | __asm__ __volatile__ ( |
| 31 | "1: %0 = memw_locked(%1);\n" /* load into retval */ | 31 | "1: %0 = memw_locked(%1);\n" /* load into retval */ |
| 32 | " memw_locked(%1,P0) = %2;\n" /* store into memory */ | 32 | " memw_locked(%1,P0) = %2;\n" /* store into memory */ |
| 33 | " if !P0 jump 1b;\n" | 33 | " if (!P0) jump 1b;\n" |
| 34 | : "=&r" (retval) | 34 | : "=&r" (retval) |
| 35 | : "r" (ptr), "r" (x) | 35 | : "r" (ptr), "r" (x) |
| 36 | : "memory", "p0" | 36 | : "memory", "p0" |
| @@ -16,7 +16,7 @@ · 15 unmodified lines | |||
| 16 | /* For example: %1 = %4 */ \ | 16 | /* For example: %1 = %4 */ \ |
| 17 | insn \ | 17 | insn \ |
| 18 | "2: memw_locked(%3,p2) = %1;\n" \ | 18 | "2: memw_locked(%3,p2) = %1;\n" \ |
| 19 | " if !p2 jump 1b;\n" \ | 19 | " if (!p2) jump 1b;\n" \ |
| 20 | " %1 = #0;\n" \ | 20 | " %1 = #0;\n" \ |
| 21 | "3:\n" \ | 21 | "3:\n" \ |
| 22 | ".section .fixup,\"ax\"\n" \ | 22 | ".section .fixup,\"ax\"\n" \ |
| @@ -84,10 +84,10 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, · 61 unmodified lines | |||
| 84 | "1: %1 = memw_locked(%3)\n" | 84 | "1: %1 = memw_locked(%3)\n" |
| 85 | " {\n" | 85 | " {\n" |
| 86 | " p2 = cmp.eq(%1,%4)\n" | 86 | " p2 = cmp.eq(%1,%4)\n" |
| 87 | " if !p2.new jump:NT 3f\n" | 87 | " if (!p2.new) jump:NT 3f\n" |
| 88 | " }\n" | 88 | " }\n" |
| 89 | "2: memw_locked(%3,p2) = %5\n" | 89 | "2: memw_locked(%3,p2) = %5\n" |
| 90 | " if !p2 jump 1b\n" | 90 | " if (!p2) jump 1b\n" |
| 91 | "3:\n" | 91 | "3:\n" |
| 92 | ".section .fixup,\"ax\"\n" | 92 | ".section .fixup,\"ax\"\n" |
| 93 | "4: %0 = #%6\n" | 93 | "4: %0 = #%6\n" |
| @@ -30,9 +30,9 @@ static inline void arch_read_lock(arch_rwlock_t *lock) · 29 unmodified lines | |||
| 30 | __asm__ __volatile__( | 30 | __asm__ __volatile__( |
| 31 | "1: R6 = memw_locked(%0);\n" | 31 | "1: R6 = memw_locked(%0);\n" |
| 32 | " { P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n" | 32 | " { P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n" |
| 33 | " { if !P3 jump 1b; }\n" | 33 | " { if (!P3) jump 1b; }\n" |
| 34 | " memw_locked(%0,P3) = R6;\n" | 34 | " memw_locked(%0,P3) = R6;\n" |
| 35 | " { if !P3 jump 1b; }\n" | 35 | " { if (!P3) jump 1b; }\n" |
| 36 | : | 36 | : |
| 37 | : "r" (&lock->lock) | 37 | : "r" (&lock->lock) |
| 38 | : "memory", "r6", "p3" | 38 | : "memory", "r6", "p3" |
| @@ -46,7 +46,7 @@ static inline void arch_read_unlock(arch_rwlock_t *lock) · 7 unmodified lines | |||
| 46 | "1: R6 = memw_locked(%0);\n" | 46 | "1: R6 = memw_locked(%0);\n" |
| 47 | " R6 = add(R6,#-1);\n" | 47 | " R6 = add(R6,#-1);\n" |
| 48 | " memw_locked(%0,P3) = R6\n" | 48 | " memw_locked(%0,P3) = R6\n" |
| 49 | " if !P3 jump 1b;\n" | 49 | " if (!P3) jump 1b;\n" |
| 50 | : | 50 | : |
| 51 | : "r" (&lock->lock) | 51 | : "r" (&lock->lock) |
| 52 | : "memory", "r6", "p3" | 52 | : "memory", "r6", "p3" |
| @@ -61,7 +61,7 @@ static inline int arch_read_trylock(arch_rwlock_t *lock) · 8 unmodified lines | |||
| 61 | __asm__ __volatile__( | 61 | __asm__ __volatile__( |
| 62 | " R6 = memw_locked(%1);\n" | 62 | " R6 = memw_locked(%1);\n" |
| 63 | " { %0 = #0; P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n" | 63 | " { %0 = #0; P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n" |
| 64 | " { if !P3 jump 1f; }\n" | 64 | " { if (!P3) jump 1f; }\n" |
| 65 | " memw_locked(%1,P3) = R6;\n" | 65 | " memw_locked(%1,P3) = R6;\n" |
| 66 | " { %0 = P3 }\n" | 66 | " { %0 = P3 }\n" |
| 67 | "1:\n" | 67 | "1:\n" |
| @@ -78,9 +78,9 @@ static inline void arch_write_lock(arch_rwlock_t *lock) · 10 unmodified lines | |||
| 78 | __asm__ __volatile__( | 78 | __asm__ __volatile__( |
| 79 | "1: R6 = memw_locked(%0)\n" | 79 | "1: R6 = memw_locked(%0)\n" |
| 80 | " { P3 = cmp.eq(R6,#0); R6 = #-1;}\n" | 80 | " { P3 = cmp.eq(R6,#0); R6 = #-1;}\n" |
| 81 | " { if !P3 jump 1b; }\n" | 81 | " { if (!P3) jump 1b; }\n" |
| 82 | " memw_locked(%0,P3) = R6;\n" | 82 | " memw_locked(%0,P3) = R6;\n" |
| 83 | " { if !P3 jump 1b; }\n" | 83 | " { if (!P3) jump 1b; }\n" |
| 84 | : | 84 | : |
| 85 | : "r" (&lock->lock) | 85 | : "r" (&lock->lock) |
| 86 | : "memory", "r6", "p3" | 86 | : "memory", "r6", "p3" |
| @@ -94,7 +94,7 @@ static inline int arch_write_trylock(arch_rwlock_t *lock) · 7 unmodified lines | |||
| 94 | __asm__ __volatile__( | 94 | __asm__ __volatile__( |
| 95 | " R6 = memw_locked(%1)\n" | 95 | " R6 = memw_locked(%1)\n" |
| 96 | " { %0 = #0; P3 = cmp.eq(R6,#0); R6 = #-1;}\n" | 96 | " { %0 = #0; P3 = cmp.eq(R6,#0); R6 = #-1;}\n" |
| 97 | " { if !P3 jump 1f; }\n" | 97 | " { if (!P3) jump 1f; }\n" |
| 98 | " memw_locked(%1,P3) = R6;\n" | 98 | " memw_locked(%1,P3) = R6;\n" |
| 99 | " %0 = P3;\n" | 99 | " %0 = P3;\n" |
| 100 | "1:\n" | 100 | "1:\n" |
| @@ -117,9 +117,9 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) · 16 unmodified lines | |||
| 117 | __asm__ __volatile__( | 117 | __asm__ __volatile__( |
| 118 | "1: R6 = memw_locked(%0);\n" | 118 | "1: R6 = memw_locked(%0);\n" |
| 119 | " P3 = cmp.eq(R6,#0);\n" | 119 | " P3 = cmp.eq(R6,#0);\n" |
| 120 | " { if !P3 jump 1b; R6 = #1; }\n" | 120 | " { if (!P3) jump 1b; R6 = #1; }\n" |
| 121 | " memw_locked(%0,P3) = R6;\n" | 121 | " memw_locked(%0,P3) = R6;\n" |
| 122 | " { if !P3 jump 1b; }\n" | 122 | " { if (!P3) jump 1b; }\n" |
| 123 | : | 123 | : |
| 124 | : "r" (&lock->lock) | 124 | : "r" (&lock->lock) |
| 125 | : "memory", "r6", "p3" | 125 | : "memory", "r6", "p3" |
| @@ -139,7 +139,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) · 13 unmodified lines | |||
| 139 | __asm__ __volatile__( | 139 | __asm__ __volatile__( |
| 140 | " R6 = memw_locked(%1);\n" | 140 | " R6 = memw_locked(%1);\n" |
| 141 | " P3 = cmp.eq(R6,#0);\n" | 141 | " P3 = cmp.eq(R6,#0);\n" |
| 142 | " { if !P3 jump 1f; R6 = #1; %0 = #0; }\n" | 142 | " { if (!P3) jump 1f; R6 = #1; %0 = #0; }\n" |
| 143 | " memw_locked(%1,P3) = R6;\n" | 143 | " memw_locked(%1,P3) = R6;\n" |
| 144 | " %0 = P3;\n" | 144 | " %0 = P3;\n" |
| 145 | "1:\n" | 145 | "1:\n" |
| @@ -369,7 +369,7 @@ ret_from_fork: · 368 unmodified lines | |||
| 369 | R26.L = #LO(do_work_pending); | 369 | R26.L = #LO(do_work_pending); |
| 370 | R0 = #VM_INT_DISABLE; | 370 | R0 = #VM_INT_DISABLE; |
| 371 | } | 371 | } |
| 372 | if P0 jump check_work_pending | 372 | if (P0) jump check_work_pending |
| 373 | { | 373 | { |
| 374 | R0 = R25; | 374 | R0 = R25; |
| 375 | callr R24 | 375 | callr R24 |