Most notable addition this time is the support for the GPU performance counters by Christian. This has been in the making for some time and it has matured a lot. Since this is adding UAPI, the corresponding WIP userspace can be found at [1] mesa/libdrm repos. I expect that Christian sends out the final userspace patches for this once you have pulled the kernel bits. Philipp optimized the probe path, so etnaviv gets out of the way for systems that want to boot real quick. I've done mostly cleanups, disentangling etnaviv from the IOMMU API, with some MMUv1 optimizations on the way. * 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux: (36 commits) drm/etnaviv: remove unnecessary clock stabilization delay drm/etnaviv: reduce reset delay drm/etnaviv: remove unused function etnaviv_gem_new drm/etnaviv: remove stale comment drm/etnaviv: submit supports performance monitor requests drm/etnaviv: enable debug registers on demand drm/etnaviv: need to disable clock gating when doing profiling drm/etnaviv: add MC perf domain drm/etnaviv: add TX perf domain drm/etnaviv: add RA perf domain drm/etnaviv: add SE perf domain drm/etnaviv: add PA perf domain drm/etnaviv: add SH perf domain drm/etnaviv: add PE perf domain drm/etnaviv: add HI perf domain drm/etnaviv: use 'sync points' for performance monitor requests drm/etnaviv: clear alloced event drm/etnaviv: add 'sync point' support drm/etnaviv: add performance monitor request processing drm/etnaviv: copy pmrs from userspace ...
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| @@ -150,6 +150,19 @@ struct drm_etnaviv_gem_submit_bo { · 149 unmodified lines | |||
| 150 | __u64 presumed; /* in/out, presumed buffer address */ | 150 | __u64 presumed; /* in/out, presumed buffer address */ |
| 151 | }; | 151 | }; |
| 152 | 152 | ||
| 153 | /* performance monitor request (pmr) */ | ||
| 154 | #define ETNA_PM_PROCESS_PRE 0x0001 | ||
| 155 | #define ETNA_PM_PROCESS_POST 0x0002 | ||
| 156 | struct drm_etnaviv_gem_submit_pmr { | ||
| 157 | __u32 flags; /* in, when to process request (ETNA_PM_PROCESS_x) */ | ||
| 158 | __u8 domain; /* in, pm domain */ | ||
| 159 | __u8 pad; | ||
| 160 | __u16 signal; /* in, pm signal */ | ||
| 161 | __u32 sequence; /* in, sequence number */ | ||
| 162 | __u32 read_offset; /* in, offset from read_bo */ | ||
| 163 | __u32 read_idx; /* in, index of read_bo buffer */ | ||
| 164 | }; | ||
| 165 | |||
| 153 | /* Each cmdstream submit consists of a table of buffers involved, and | 166 | /* Each cmdstream submit consists of a table of buffers involved, and |
| 154 | * one or more cmdstream buffers. This allows for conditional execution | 167 | * one or more cmdstream buffers. This allows for conditional execution |
| 155 | * (context-restore), and IB buffers needed for per tile/bin draw cmds. | 168 | * (context-restore), and IB buffers needed for per tile/bin draw cmds. |
| @@ -175,6 +188,9 @@ struct drm_etnaviv_gem_submit { · 19 unmodified lines | |||
| 175 | __u64 stream; /* in, ptr to cmdstream */ | 188 | __u64 stream; /* in, ptr to cmdstream */ |
| 176 | __u32 flags; /* in, mask of ETNA_SUBMIT_x */ | 189 | __u32 flags; /* in, mask of ETNA_SUBMIT_x */ |
| 177 | __s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */ | 190 | __s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */ |
| 191 | __u64 pmrs; /* in, ptr to array of submit_pmr's */ | ||
| 192 | __u32 nr_pmrs; /* in, number of submit_pmr's */ | ||
| 193 | __u32 pad; | ||
| 178 | }; | 194 | }; |
| 179 | 195 | ||
| 180 | /* The normal way to synchronize with the GPU is just to CPU_PREP on | 196 | /* The normal way to synchronize with the GPU is just to CPU_PREP on |
| @@ -210,6 +226,27 @@ struct drm_etnaviv_gem_wait { · 29 unmodified lines | |||
| 210 | struct drm_etnaviv_timespec timeout; /* in */ | 226 | struct drm_etnaviv_timespec timeout; /* in */ |
| 211 | }; | 227 | }; |
| 212 | 228 | ||
| 229 | /* | ||
| 230 | * Performance Monitor (PM): | ||
| 231 | */ | ||
| 232 | |||
| 233 | struct drm_etnaviv_pm_domain { | ||
| 234 | __u32 pipe; /* in */ | ||
| 235 | __u8 iter; /* in/out, select pm domain at index iter */ | ||
| 236 | __u8 id; /* out, id of domain */ | ||
| 237 | __u16 nr_signals; /* out, how many signals does this domain provide */ | ||
| 238 | char name[64]; /* out, name of domain */ | ||
| 239 | }; | ||
| 240 | |||
| 241 | struct drm_etnaviv_pm_signal { | ||
| 242 | __u32 pipe; /* in */ | ||
| 243 | __u8 domain; /* in, pm domain index */ | ||
| 244 | __u8 pad; | ||
| 245 | __u16 iter; /* in/out, select pm source at index iter */ | ||
| 246 | __u16 id; /* out, id of signal */ | ||
| 247 | char name[64]; /* out, name of domain */ | ||
| 248 | }; | ||
| 249 | |||
| 213 | #define DRM_ETNAVIV_GET_PARAM 0x00 | 250 | #define DRM_ETNAVIV_GET_PARAM 0x00 |
| 214 | /* placeholder: | 251 | /* placeholder: |
| 215 | #define DRM_ETNAVIV_SET_PARAM 0x01 | 252 | #define DRM_ETNAVIV_SET_PARAM 0x01 |
| @@ -222,7 +259,9 @@ struct drm_etnaviv_gem_wait { · 6 unmodified lines | |||
| 222 | #define DRM_ETNAVIV_WAIT_FENCE 0x07 | 259 | #define DRM_ETNAVIV_WAIT_FENCE 0x07 |
| 223 | #define DRM_ETNAVIV_GEM_USERPTR 0x08 | 260 | #define DRM_ETNAVIV_GEM_USERPTR 0x08 |
| 224 | #define DRM_ETNAVIV_GEM_WAIT 0x09 | 261 | #define DRM_ETNAVIV_GEM_WAIT 0x09 |
| 225 | #define DRM_ETNAVIV_NUM_IOCTLS 0x0a | 262 | #define DRM_ETNAVIV_PM_QUERY_DOM 0x0a |
| 263 | #define DRM_ETNAVIV_PM_QUERY_SIG 0x0b | ||
| 264 | #define DRM_ETNAVIV_NUM_IOCTLS 0x0c | ||
| 226 | 265 | ||
| 227 | #define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) | 266 | #define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) |
| 228 | #define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) | 267 | #define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) |
| @@ -233,6 +272,8 @@ struct drm_etnaviv_gem_wait { · 4 unmodified lines | |||
| 233 | #define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) | 272 | #define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) |
| 234 | #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) | 273 | #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) |
| 235 | #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) | 274 | #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) |
| 275 | #define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain) | ||
| 276 | #define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal) | ||
| 236 | 277 | ||
| 237 | #if defined(__cplusplus) | 278 | #if defined(__cplusplus) |
| 238 | } | 279 | } |