History

Merge patch series "can: kvaser_pciefd: Fixes and improvements"

Jimmy Assarsson <extja@kvaser.com> says: This patch series contains various non critical fixes and improvements for the kvaser_pciefd driver.

Marc Kleine-Budde committed 3 years ago

Commit 790ef392 parents 735d86a 6fdcd642 files · +342 −616Browse files

Unified · Split

2 files
  1. drivers/net/can/Kconfig +1 −2
  2. drivers/net/can/kvaser_pciefd.c +341 −614
drivers/net/can/Kconfig+1−2
@@ -153,8 +153,7 @@ config CAN_JANZ_ICAN3 · 152 unmodified lines
153config CAN_KVASER_PCIEFD153config CAN_KVASER_PCIEFD
154 depends on PCI154 depends on PCI
155 tristate "Kvaser PCIe FD cards"155 tristate "Kvaser PCIe FD cards"
156 select CRC32156 help
157 help
158 This is a driver for the Kvaser PCI Express CAN FD family.157 This is a driver for the Kvaser PCI Express CAN FD family.
159 158
160 Supported devices:159 Supported devices:
drivers/net/can/kvaser_pciefd.c+341−614
@@ -3,19 +3,19 @@ · 2 unmodified lines
3 * Parts of this driver are based on the following:3 * Parts of this driver are based on the following:
4 * - Kvaser linux pciefd driver (version 5.25)4 * - Kvaser linux pciefd driver (version 5.25)
5 * - PEAK linux canfd driver5 * - PEAK linux canfd driver
6 * - Altera Avalon EPCS flash controller driver
7 */6 */
8 7
9#include <linux/kernel.h>8#include <linux/bitfield.h>
10#include <linux/module.h>9#include <linux/can/dev.h>
11#include <linux/device.h>10#include <linux/device.h>
12#include <linux/ethtool.h>11#include <linux/ethtool.h>
12#include <linux/iopoll.h>
13#include <linux/kernel.h>
14#include <linux/minmax.h>
15#include <linux/module.h>
16#include <linux/netdevice.h>
13#include <linux/pci.h>17#include <linux/pci.h>
14#include <linux/can/dev.h>
15#include <linux/timer.h>18#include <linux/timer.h>
16#include <linux/netdevice.h>
17#include <linux/crc32.h>
18#include <linux/iopoll.h>
19 19
20MODULE_LICENSE("Dual BSD/GPL");20MODULE_LICENSE("Dual BSD/GPL");
21MODULE_AUTHOR("Kvaser AB <support@kvaser.com>");21MODULE_AUTHOR("Kvaser AB <support@kvaser.com>");
@@ -25,42 +25,25 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices"); · 3 unmodified lines
25 25
26#define KVASER_PCIEFD_WAIT_TIMEOUT msecs_to_jiffies(1000)26#define KVASER_PCIEFD_WAIT_TIMEOUT msecs_to_jiffies(1000)
27#define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200))27#define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200))
28#define KVASER_PCIEFD_MAX_ERR_REP 25628#define KVASER_PCIEFD_MAX_ERR_REP 256U
29#define KVASER_PCIEFD_CAN_TX_MAX_COUNT 1729#define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17U
30#define KVASER_PCIEFD_MAX_CAN_CHANNELS 430#define KVASER_PCIEFD_MAX_CAN_CHANNELS 4UL
31#define KVASER_PCIEFD_DMA_COUNT 231#define KVASER_PCIEFD_DMA_COUNT 2U
32 32
33#define KVASER_PCIEFD_DMA_SIZE (4 * 1024)33#define KVASER_PCIEFD_DMA_SIZE (4U * 1024U)
34#define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0)
35 34
36#define KVASER_PCIEFD_VENDOR 0x1a0735#define KVASER_PCIEFD_VENDOR 0x1a07
37#define KVASER_PCIEFD_4HS_ID 0x0d36#define KVASER_PCIEFD_4HS_DEVICE_ID 0x000d
38#define KVASER_PCIEFD_2HS_ID 0x0e37#define KVASER_PCIEFD_2HS_V2_DEVICE_ID 0x000e
39#define KVASER_PCIEFD_HS_ID 0x0f38#define KVASER_PCIEFD_HS_V2_DEVICE_ID 0x000f
40#define KVASER_PCIEFD_MINIPCIE_HS_ID 0x1039#define KVASER_PCIEFD_MINIPCIE_HS_V2_DEVICE_ID 0x0010
41#define KVASER_PCIEFD_MINIPCIE_2HS_ID 0x1140#define KVASER_PCIEFD_MINIPCIE_2HS_V2_DEVICE_ID 0x0011
42 41
43/* PCIe IRQ registers */42/* PCIe IRQ registers */
44#define KVASER_PCIEFD_IRQ_REG 0x4043#define KVASER_PCIEFD_IRQ_REG 0x40
45#define KVASER_PCIEFD_IEN_REG 0x5044#define KVASER_PCIEFD_IEN_REG 0x50
46/* DMA map */45/* DMA address translation map register base */
47#define KVASER_PCIEFD_DMA_MAP_BASE 0x100046#define KVASER_PCIEFD_DMA_MAP_BASE 0x1000
48/* Kvaser KCAN CAN controller registers */
49#define KVASER_PCIEFD_KCAN0_BASE 0x10000
50#define KVASER_PCIEFD_KCAN_BASE_OFFSET 0x1000
51#define KVASER_PCIEFD_KCAN_FIFO_REG 0x100
52#define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180
53#define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0
54#define KVASER_PCIEFD_KCAN_CMD_REG 0x400
55#define KVASER_PCIEFD_KCAN_IEN_REG 0x408
56#define KVASER_PCIEFD_KCAN_IRQ_REG 0x410
57#define KVASER_PCIEFD_KCAN_TX_NPACKETS_REG 0x414
58#define KVASER_PCIEFD_KCAN_STAT_REG 0x418
59#define KVASER_PCIEFD_KCAN_MODE_REG 0x41c
60#define KVASER_PCIEFD_KCAN_BTRN_REG 0x420
61#define KVASER_PCIEFD_KCAN_BUS_LOAD_REG 0x424
62#define KVASER_PCIEFD_KCAN_BTRD_REG 0x428
63#define KVASER_PCIEFD_KCAN_PWM_REG 0x430
64/* Loopback control register */47/* Loopback control register */
65#define KVASER_PCIEFD_LOOP_REG 0x1f00048#define KVASER_PCIEFD_LOOP_REG 0x1f000
66/* System identification and information registers */49/* System identification and information registers */
@@ -78,183 +61,196 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices"); · 11 unmodified lines
78#define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210)61#define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210)
79#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG (KVASER_PCIEFD_SRB_BASE + 0x214)62#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG (KVASER_PCIEFD_SRB_BASE + 0x214)
80#define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218)63#define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218)
81/* EPCS flash controller registers */64/* Kvaser KCAN CAN controller registers */
82#define KVASER_PCIEFD_SPI_BASE 0x1fc0065#define KVASER_PCIEFD_KCAN0_BASE 0x10000
83#define KVASER_PCIEFD_SPI_RX_REG KVASER_PCIEFD_SPI_BASE66#define KVASER_PCIEFD_KCAN_BASE_OFFSET 0x1000
84#define KVASER_PCIEFD_SPI_TX_REG (KVASER_PCIEFD_SPI_BASE + 0x4)67#define KVASER_PCIEFD_KCAN_FIFO_REG 0x100
85#define KVASER_PCIEFD_SPI_STATUS_REG (KVASER_PCIEFD_SPI_BASE + 0x8)68#define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180
86#define KVASER_PCIEFD_SPI_CTRL_REG (KVASER_PCIEFD_SPI_BASE + 0xc)69#define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0
87#define KVASER_PCIEFD_SPI_SSEL_REG (KVASER_PCIEFD_SPI_BASE + 0x14)70#define KVASER_PCIEFD_KCAN_CMD_REG 0x400
88 71#define KVASER_PCIEFD_KCAN_IEN_REG 0x408
89#define KVASER_PCIEFD_IRQ_ALL_MSK 0x1f72#define KVASER_PCIEFD_KCAN_IRQ_REG 0x410
73#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG 0x414
74#define KVASER_PCIEFD_KCAN_STAT_REG 0x418
75#define KVASER_PCIEFD_KCAN_MODE_REG 0x41c
76#define KVASER_PCIEFD_KCAN_BTRN_REG 0x420
77#define KVASER_PCIEFD_KCAN_BUS_LOAD_REG 0x424
78#define KVASER_PCIEFD_KCAN_BTRD_REG 0x428
79#define KVASER_PCIEFD_KCAN_PWM_REG 0x430
80
81/* PCI interrupt fields */
90#define KVASER_PCIEFD_IRQ_SRB BIT(4)82#define KVASER_PCIEFD_IRQ_SRB BIT(4)
83#define KVASER_PCIEFD_IRQ_ALL_MASK GENMASK(4, 0)
91 84
92#define KVASER_PCIEFD_SYSID_NRCHAN_SHIFT 2485/* Enable 64-bit DMA address translation */
93#define KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT 1686#define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0)
94#define KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT 187
88/* System build information fields */
89#define KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK GENMASK(31, 24)
90#define KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK GENMASK(23, 16)
91#define KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK GENMASK(7, 0)
92#define KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK GENMASK(15, 1)
95 93
96/* Reset DMA buffer 0, 1 and FIFO offset */94/* Reset DMA buffer 0, 1 and FIFO offset */
97#define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4)
98#define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5)95#define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5)
96#define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4)
99#define KVASER_PCIEFD_SRB_CMD_FOR BIT(0)97#define KVASER_PCIEFD_SRB_CMD_FOR BIT(0)
100 98
101/* DMA packet done, buffer 0 and 1 */
102#define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8)
103#define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9)
104/* DMA overflow, buffer 0 and 1 */
105#define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10)
106#define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11)
107/* DMA underflow, buffer 0 and 1 */99/* DMA underflow, buffer 0 and 1 */
108#define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12)
109#define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13)100#define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13)
101#define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12)
102/* DMA overflow, buffer 0 and 1 */
103#define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11)
104#define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10)
105/* DMA packet done, buffer 0 and 1 */
106#define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9)
107#define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8)
110 108
109/* Got DMA support */
110#define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
111/* DMA idle */111/* DMA idle */
112#define KVASER_PCIEFD_SRB_STAT_DI BIT(15)112#define KVASER_PCIEFD_SRB_STAT_DI BIT(15)
113/* DMA support */
114#define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
115 113
116/* SRB current packet level */114/* SRB current packet level */
117#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK 0xff115#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK GENMASK(7, 0)
118 116
119/* DMA Enable */117/* DMA Enable */
120#define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)118#define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
121 119
122/* EPCS flash controller definitions */120/* KCAN CTRL packet types */
123#define KVASER_PCIEFD_CFG_IMG_SZ (64 * 1024)121#define KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK GENMASK(31, 29)
124#define KVASER_PCIEFD_CFG_IMG_OFFSET (31 * 65536L)122#define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH 0x4
125#define KVASER_PCIEFD_CFG_MAX_PARAMS 256123#define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFRAME 0x5
126#define KVASER_PCIEFD_CFG_MAGIC 0xcafef00d124
127#define KVASER_PCIEFD_CFG_PARAM_MAX_SZ 24125/* Command sequence number */
128#define KVASER_PCIEFD_CFG_SYS_VER 1126#define KVASER_PCIEFD_KCAN_CMD_SEQ_MASK GENMASK(23, 16)
129#define KVASER_PCIEFD_CFG_PARAM_NR_CHAN 130127/* Command bits */
130#define KVASER_PCIEFD_SPI_TMT BIT(5)128#define KVASER_PCIEFD_KCAN_CMD_MASK GENMASK(5, 0)
131#define KVASER_PCIEFD_SPI_TRDY BIT(6)
132#define KVASER_PCIEFD_SPI_RRDY BIT(7)
133#define KVASER_PCIEFD_FLASH_ID_EPCS16 0x14
134/* Commands for controlling the onboard flash */
135#define KVASER_PCIEFD_FLASH_RES_CMD 0xab
136#define KVASER_PCIEFD_FLASH_READ_CMD 0x3
137#define KVASER_PCIEFD_FLASH_STATUS_CMD 0x5
138
139/* Kvaser KCAN definitions */
140#define KVASER_PCIEFD_KCAN_CTRL_EFLUSH (4 << 29)
141#define KVASER_PCIEFD_KCAN_CTRL_EFRAME (5 << 29)
142
143#define KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT 16
144/* Request status packet */
145#define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0)
146/* Abort, flush and reset */129/* Abort, flush and reset */
147#define KVASER_PCIEFD_KCAN_CMD_AT BIT(1)130#define KVASER_PCIEFD_KCAN_CMD_AT BIT(1)
131/* Request status packet */
132#define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0)
148 133
149/* Tx FIFO unaligned read */
150#define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
151/* Tx FIFO unaligned end */
152#define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1)
153/* Bus parameter protection error */
154#define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2)
155/* FDF bit when controller is in classic mode */
156#define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3)
157/* Rx FIFO overflow */
158#define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5)
159/* Abort done */
160#define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13)
161/* Tx buffer flush done */
162#define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14)
163/* Tx FIFO overflow */
164#define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15)
165/* Tx FIFO empty */
166#define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16)
167/* Transmitter unaligned */134/* Transmitter unaligned */
168#define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17)135#define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17)
136/* Tx FIFO empty */
137#define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16)
138/* Tx FIFO overflow */
139#define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15)
140/* Tx buffer flush done */
141#define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14)
142/* Abort done */
143#define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13)
144/* Rx FIFO overflow */
145#define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5)
146/* FDF bit when controller is in classic CAN mode */
147#define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3)
148/* Bus parameter protection error */
149#define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2)
150/* Tx FIFO unaligned end */
151#define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1)
152/* Tx FIFO unaligned read */
153#define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
169 154
170#define KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT 16155/* Tx FIFO size */
156#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK GENMASK(23, 16)
157/* Tx FIFO current packet level */
158#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK GENMASK(7, 0)
171 159
172#define KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT 24160/* Current status packet sequence number */
173/* Abort request */161#define KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK GENMASK(31, 24)
174#define KVASER_PCIEFD_KCAN_STAT_AR BIT(7)
175/* Idle state. Controller in reset mode and no abort or flush pending */
176#define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10)
177/* Bus off */
178#define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11)
179/* Reset mode request */
180#define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14)
181/* Controller in reset mode */
182#define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15)
183/* Controller got one-shot capability */
184#define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16)
185/* Controller got CAN FD capability */162/* Controller got CAN FD capability */
186#define KVASER_PCIEFD_KCAN_STAT_FD BIT(19)163#define KVASER_PCIEFD_KCAN_STAT_FD BIT(19)
187#define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK (KVASER_PCIEFD_KCAN_STAT_AR | \164/* Controller got one-shot capability */
188 KVASER_PCIEFD_KCAN_STAT_BOFF | KVASER_PCIEFD_KCAN_STAT_RMR | \165#define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16)
189 KVASER_PCIEFD_KCAN_STAT_IRM)166/* Controller in reset mode */
167#define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15)
168/* Reset mode request */
169#define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14)
170/* Bus off */
171#define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11)
172/* Idle state. Controller in reset mode and no abort or flush pending */
173#define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10)
174/* Abort request */
175#define KVASER_PCIEFD_KCAN_STAT_AR BIT(7)
176/* Controller is bus off */
177#define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MASK \
178 (KVASER_PCIEFD_KCAN_STAT_AR | KVASER_PCIEFD_KCAN_STAT_BOFF | \
179 KVASER_PCIEFD_KCAN_STAT_RMR | KVASER_PCIEFD_KCAN_STAT_IRM)
190 180
191/* Reset mode */
192#define KVASER_PCIEFD_KCAN_MODE_RM BIT(8)
193/* Listen only mode */
194#define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9)
195/* Error packet enable */
196#define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12)
197/* CAN FD non-ISO */
198#define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15)
199/* Acknowledgment packet type */
200#define KVASER_PCIEFD_KCAN_MODE_APT BIT(20)
201/* Active error flag enable. Clear to force error passive */
202#define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23)
203/* Classic CAN mode */181/* Classic CAN mode */
204#define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31)182#define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31)
183/* Active error flag enable. Clear to force error passive */
184#define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23)
185/* Acknowledgment packet type */
186#define KVASER_PCIEFD_KCAN_MODE_APT BIT(20)
187/* CAN FD non-ISO */
188#define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15)
189/* Error packet enable */
190#define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12)
191/* Listen only mode */
192#define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9)
193/* Reset mode */
194#define KVASER_PCIEFD_KCAN_MODE_RM BIT(8)
205 195
206#define KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT 13196/* BTRN and BTRD fields */
207#define KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT 17197#define KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK GENMASK(30, 26)
208#define KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT 26198#define KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK GENMASK(25, 17)
209 199#define KVASER_PCIEFD_KCAN_BTRN_SJW_MASK GENMASK(16, 13)
210#define KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT 16200#define KVASER_PCIEFD_KCAN_BTRN_BRP_MASK GENMASK(12, 0)
211 201
212/* Kvaser KCAN packet types */202/* PWM Control fields */
213#define KVASER_PCIEFD_PACK_TYPE_DATA 0203#define KVASER_PCIEFD_KCAN_PWM_TOP_MASK GENMASK(23, 16)
214#define KVASER_PCIEFD_PACK_TYPE_ACK 1204#define KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK GENMASK(7, 0)
215#define KVASER_PCIEFD_PACK_TYPE_TXRQ 2205
216#define KVASER_PCIEFD_PACK_TYPE_ERROR 3206/* KCAN packet type IDs */
217#define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 4207#define KVASER_PCIEFD_PACK_TYPE_DATA 0x0
218#define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 5208#define KVASER_PCIEFD_PACK_TYPE_ACK 0x1
219#define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 6209#define KVASER_PCIEFD_PACK_TYPE_TXRQ 0x2
220#define KVASER_PCIEFD_PACK_TYPE_STATUS 8210#define KVASER_PCIEFD_PACK_TYPE_ERROR 0x3
221#define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 9211#define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 0x4
222 212#define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 0x5
223/* Kvaser KCAN packet common definitions */213#define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 0x6
224#define KVASER_PCIEFD_PACKET_SEQ_MSK 0xff214#define KVASER_PCIEFD_PACK_TYPE_STATUS 0x8
225#define KVASER_PCIEFD_PACKET_CHID_SHIFT 25215#define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 0x9
226#define KVASER_PCIEFD_PACKET_TYPE_SHIFT 28216
227 217/* Common KCAN packet definitions, second word */
228/* Kvaser KCAN TDATA and RDATA first word */218#define KVASER_PCIEFD_PACKET_TYPE_MASK GENMASK(31, 28)
219#define KVASER_PCIEFD_PACKET_CHID_MASK GENMASK(27, 25)
220#define KVASER_PCIEFD_PACKET_SEQ_MASK GENMASK(7, 0)
221
222/* KCAN Transmit/Receive data packet, first word */
229#define KVASER_PCIEFD_RPACKET_IDE BIT(30)223#define KVASER_PCIEFD_RPACKET_IDE BIT(30)
230#define KVASER_PCIEFD_RPACKET_RTR BIT(29)224#define KVASER_PCIEFD_RPACKET_RTR BIT(29)
231/* Kvaser KCAN TDATA and RDATA second word */225#define KVASER_PCIEFD_RPACKET_ID_MASK GENMASK(28, 0)
232#define KVASER_PCIEFD_RPACKET_ESI BIT(13)226/* KCAN Transmit data packet, second word */
233#define KVASER_PCIEFD_RPACKET_BRS BIT(14)
234#define KVASER_PCIEFD_RPACKET_FDF BIT(15)
235#define KVASER_PCIEFD_RPACKET_DLC_SHIFT 8
236/* Kvaser KCAN TDATA second word */
237#define KVASER_PCIEFD_TPACKET_SMS BIT(16)
238#define KVASER_PCIEFD_TPACKET_AREQ BIT(31)227#define KVASER_PCIEFD_TPACKET_AREQ BIT(31)
228#define KVASER_PCIEFD_TPACKET_SMS BIT(16)
229/* KCAN Transmit/Receive data packet, second word */
230#define KVASER_PCIEFD_RPACKET_FDF BIT(15)
231#define KVASER_PCIEFD_RPACKET_BRS BIT(14)
232#define KVASER_PCIEFD_RPACKET_ESI BIT(13)
233#define KVASER_PCIEFD_RPACKET_DLC_MASK GENMASK(11, 8)
239 234
240/* Kvaser KCAN APACKET */235/* KCAN Transmit acknowledge packet, first word */
241#define KVASER_PCIEFD_APACKET_FLU BIT(8)
242#define KVASER_PCIEFD_APACKET_CT BIT(9)
243#define KVASER_PCIEFD_APACKET_ABL BIT(10)
244#define KVASER_PCIEFD_APACKET_NACK BIT(11)236#define KVASER_PCIEFD_APACKET_NACK BIT(11)
237#define KVASER_PCIEFD_APACKET_ABL BIT(10)
238#define KVASER_PCIEFD_APACKET_CT BIT(9)
239#define KVASER_PCIEFD_APACKET_FLU BIT(8)
245 240
246/* Kvaser KCAN SPACK first word */241/* KCAN Status packet, first word */
247#define KVASER_PCIEFD_SPACK_RXERR_SHIFT 8
248#define KVASER_PCIEFD_SPACK_BOFF BIT(16)
249#define KVASER_PCIEFD_SPACK_IDET BIT(20)
250#define KVASER_PCIEFD_SPACK_IRM BIT(21)
251#define KVASER_PCIEFD_SPACK_RMCD BIT(22)242#define KVASER_PCIEFD_SPACK_RMCD BIT(22)
252/* Kvaser KCAN SPACK second word */243#define KVASER_PCIEFD_SPACK_IRM BIT(21)
253#define KVASER_PCIEFD_SPACK_AUTO BIT(21)244#define KVASER_PCIEFD_SPACK_IDET BIT(20)
254#define KVASER_PCIEFD_SPACK_EWLR BIT(23)245#define KVASER_PCIEFD_SPACK_BOFF BIT(16)
246#define KVASER_PCIEFD_SPACK_RXERR_MASK GENMASK(15, 8)
247#define KVASER_PCIEFD_SPACK_TXERR_MASK GENMASK(7, 0)
248/* KCAN Status packet, second word */
255#define KVASER_PCIEFD_SPACK_EPLR BIT(24)249#define KVASER_PCIEFD_SPACK_EPLR BIT(24)
250#define KVASER_PCIEFD_SPACK_EWLR BIT(23)
251#define KVASER_PCIEFD_SPACK_AUTO BIT(21)
256 252
257/* Kvaser KCAN_EPACK second word */253/* KCAN Error detected packet, second word */
258#define KVASER_PCIEFD_EPACK_DIR_TX BIT(0)254#define KVASER_PCIEFD_EPACK_DIR_TX BIT(0)
259 255
260struct kvaser_pciefd;256struct kvaser_pciefd;
@@ -306,195 +302,43 @@ static const struct can_bittiming_const kvaser_pciefd_bittiming_const = { · 45 unmodified lines
306 .brp_inc = 1,302 .brp_inc = 1,
307};303};
308 304
309struct kvaser_pciefd_cfg_param {
310 __le32 magic;
311 __le32 nr;
312 __le32 len;
313 u8 data[KVASER_PCIEFD_CFG_PARAM_MAX_SZ];
314};
315
316struct kvaser_pciefd_cfg_img {
317 __le32 version;
318 __le32 magic;
319 __le32 crc;
320 struct kvaser_pciefd_cfg_param params[KVASER_PCIEFD_CFG_MAX_PARAMS];
321};
322
323static struct pci_device_id kvaser_pciefd_id_table[] = {305static struct pci_device_id kvaser_pciefd_id_table[] = {
324 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_ID), },306 {
325 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_ID), },307 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_DEVICE_ID),
326 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_ID), },308 },
327 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_ID), },309 {
328 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_ID), },310 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_V2_DEVICE_ID),
329 { 0,},311 },
312 {
313 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_V2_DEVICE_ID),
314 },
315 {
316 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_V2_DEVICE_ID),
317 },
318 {
319 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_V2_DEVICE_ID),
320 },
321 {
322 0,
323 },
330};324};
331MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table);325MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table);
332 326
333/* Onboard flash memory functions */327static inline void kvaser_pciefd_send_kcan_cmd(struct kvaser_pciefd_can *can, u32 cmd)
334static int kvaser_pciefd_spi_wait_loop(struct kvaser_pciefd *pcie, int msk)
335{
336 u32 res;
337
338 return readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG,
339 res, res & msk, 0, 10);
340}
341
342static int kvaser_pciefd_spi_cmd(struct kvaser_pciefd *pcie, const u8 *tx,
343 u32 tx_len, u8 *rx, u32 rx_len)
344{
345 int c;
346
347 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG);
348 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
349 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
350
351 c = tx_len;
352 while (c--) {
353 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
354 return -EIO;
355
356 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
357
358 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
359 return -EIO;
360
361 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
362 }
363
364 c = rx_len;
365 while (c-- > 0) {
366 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
367 return -EIO;
368
369 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
370
371 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
372 return -EIO;
373
374 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
375 }
376
377 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TMT))
378 return -EIO;
379
380 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
381
382 if (c != -1) {
383 dev_err(&pcie->pci->dev, "Flash SPI transfer failed\n");
384 return -EIO;
385 }
386
387 return 0;
388}
389
390static int kvaser_pciefd_cfg_read_and_verify(struct kvaser_pciefd *pcie,
391 struct kvaser_pciefd_cfg_img *img)
392{
393 int offset = KVASER_PCIEFD_CFG_IMG_OFFSET;
394 int res, crc;
395 u8 *crc_buff;
396
397 u8 cmd[] = {
398 KVASER_PCIEFD_FLASH_READ_CMD,
399 (u8)((offset >> 16) & 0xff),
400 (u8)((offset >> 8) & 0xff),
401 (u8)(offset & 0xff)
402 };
403
404 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), (u8 *)img,
405 KVASER_PCIEFD_CFG_IMG_SZ);
406 if (res)
407 return res;
408
409 crc_buff = (u8 *)img->params;
410
411 if (le32_to_cpu(img->version) != KVASER_PCIEFD_CFG_SYS_VER) {
412 dev_err(&pcie->pci->dev,
413 "Config flash corrupted, version number is wrong\n");
414 return -ENODEV;
415 }
416
417 if (le32_to_cpu(img->magic) != KVASER_PCIEFD_CFG_MAGIC) {
418 dev_err(&pcie->pci->dev,
419 "Config flash corrupted, magic number is wrong\n");
420 return -ENODEV;
421 }
422
423 crc = ~crc32_be(0xffffffff, crc_buff, sizeof(img->params));
424 if (le32_to_cpu(img->crc) != crc) {
425 dev_err(&pcie->pci->dev,
426 "Stored CRC does not match flash image contents\n");
427 return -EIO;
428 }
429
430 return 0;
431}
432
433static void kvaser_pciefd_cfg_read_params(struct kvaser_pciefd *pcie,
434 struct kvaser_pciefd_cfg_img *img)
435{328{
436 struct kvaser_pciefd_cfg_param *param;329 iowrite32(FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_MASK, cmd) |
437 330 FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_SEQ_MASK, ++can->cmd_seq),
438 param = &img->params[KVASER_PCIEFD_CFG_PARAM_NR_CHAN];331 can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
439 memcpy(&pcie->nr_channels, param->data, le32_to_cpu(param->len));
440}332}
441 333
442static int kvaser_pciefd_read_cfg(struct kvaser_pciefd *pcie)334static inline void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can)
443{335{
444 int res;336 kvaser_pciefd_send_kcan_cmd(can, KVASER_PCIEFD_KCAN_CMD_SRQ);
445 struct kvaser_pciefd_cfg_img *img;
446
447 /* Read electronic signature */
448 u8 cmd[] = {KVASER_PCIEFD_FLASH_RES_CMD, 0, 0, 0};
449
450 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), cmd, 1);
451 if (res)
452 return -EIO;
453
454 img = kmalloc(KVASER_PCIEFD_CFG_IMG_SZ, GFP_KERNEL);
455 if (!img)
456 return -ENOMEM;
457
458 if (cmd[0] != KVASER_PCIEFD_FLASH_ID_EPCS16) {
459 dev_err(&pcie->pci->dev,
460 "Flash id is 0x%x instead of expected EPCS16 (0x%x)\n",
461 cmd[0], KVASER_PCIEFD_FLASH_ID_EPCS16);
462
463 res = -ENODEV;
464 goto image_free;
465 }
466
467 cmd[0] = KVASER_PCIEFD_FLASH_STATUS_CMD;
468 res = kvaser_pciefd_spi_cmd(pcie, cmd, 1, cmd, 1);
469 if (res) {
470 goto image_free;
471 } else if (cmd[0] & 1) {
472 res = -EIO;
473 /* No write is ever done, the WIP should never be set */
474 dev_err(&pcie->pci->dev, "Unexpected WIP bit set in flash\n");
475 goto image_free;
476 }
477
478 res = kvaser_pciefd_cfg_read_and_verify(pcie, img);
479 if (res) {
480 res = -EIO;
481 goto image_free;
482 }
483
484 kvaser_pciefd_cfg_read_params(pcie, img);
485
486image_free:
487 kfree(img);
488 return res;
489}337}
490 338
491static void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can)339static inline void kvaser_pciefd_abort_flush_reset(struct kvaser_pciefd_can *can)
492{340{
493 u32 cmd;341 kvaser_pciefd_send_kcan_cmd(can, KVASER_PCIEFD_KCAN_CMD_AT);
494
495 cmd = KVASER_PCIEFD_KCAN_CMD_SRQ;
496 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
497 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
498}342}
499 343
500static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can)344static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can)
@@ -523,7 +367,7 @@ static void kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can *can) · 22 unmodified lines
523 spin_unlock_irqrestore(&can->lock, irq);367 spin_unlock_irqrestore(&can->lock, irq);
524}368}
525 369
526static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can)370static void kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can)
527{371{
528 u32 msk;372 u32 msk;
529 373
@@ -534,8 +378,13 @@ static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can) · 4 unmodified lines
534 KVASER_PCIEFD_KCAN_IRQ_TAR;378 KVASER_PCIEFD_KCAN_IRQ_TAR;
535 379
536 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);380 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
381}
537 382
538 return 0;383static inline void kvaser_pciefd_set_skb_timestamp(const struct kvaser_pciefd *pcie,
384 struct sk_buff *skb, u64 timestamp)
385{
386 skb_hwtstamps(skb)->hwtstamp =
387 ns_to_ktime(div_u64(timestamp * 1000, pcie->freq_to_ticks_div));
539}388}
540 389
541static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can)390static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can)
@@ -544,7 +393,6 @@ static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can) · 2 unmodified lines
544 unsigned long irq;393 unsigned long irq;
545 394
546 spin_lock_irqsave(&can->lock, irq);395 spin_lock_irqsave(&can->lock, irq);
547
548 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);396 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
549 if (can->can.ctrlmode & CAN_CTRLMODE_FD) {397 if (can->can.ctrlmode & CAN_CTRLMODE_FD) {
550 mode &= ~KVASER_PCIEFD_KCAN_MODE_CCM;398 mode &= ~KVASER_PCIEFD_KCAN_MODE_CCM;
@@ -561,7 +409,6 @@ static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can) · 10 unmodified lines
561 mode |= KVASER_PCIEFD_KCAN_MODE_LOM;409 mode |= KVASER_PCIEFD_KCAN_MODE_LOM;
562 else410 else
563 mode &= ~KVASER_PCIEFD_KCAN_MODE_LOM;411 mode &= ~KVASER_PCIEFD_KCAN_MODE_LOM;
564
565 mode |= KVASER_PCIEFD_KCAN_MODE_EEN;412 mode |= KVASER_PCIEFD_KCAN_MODE_EEN;
566 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;413 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
567 /* Use ACK packet type */414 /* Use ACK packet type */
@@ -578,18 +425,13 @@ static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can) · 10 unmodified lines
578 unsigned long irq;425 unsigned long irq;
579 426
580 spin_lock_irqsave(&can->lock, irq);427 spin_lock_irqsave(&can->lock, irq);
581 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);428 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
582 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,429 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
583 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);430 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
584
585 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);431 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
586 if (status & KVASER_PCIEFD_KCAN_STAT_IDLE) {432 if (status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
587 u32 cmd;
588
589 /* If controller is already idle, run abort, flush and reset */433 /* If controller is already idle, run abort, flush and reset */
590 cmd = KVASER_PCIEFD_KCAN_CMD_AT;434 kvaser_pciefd_abort_flush_reset(can);
591 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
592 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
593 } else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) {435 } else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) {
594 u32 mode;436 u32 mode;
595 437
@@ -598,7 +440,6 @@ static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can) · 2 unmodified lines
598 mode |= KVASER_PCIEFD_KCAN_MODE_RM;440 mode |= KVASER_PCIEFD_KCAN_MODE_RM;
599 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);441 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
600 }442 }
601
602 spin_unlock_irqrestore(&can->lock, irq);443 spin_unlock_irqrestore(&can->lock, irq);
603}444}
604 445
@@ -608,7 +449,6 @@ static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) · 3 unmodified lines
608 unsigned long irq;449 unsigned long irq;
609 450
610 del_timer(&can->bec_poll_timer);451 del_timer(&can->bec_poll_timer);
611
612 if (!completion_done(&can->flush_comp))452 if (!completion_done(&can->flush_comp))
613 kvaser_pciefd_start_controller_flush(can);453 kvaser_pciefd_start_controller_flush(can);
614 454
@@ -620,11 +460,9 @@ static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) · 5 unmodified lines
620 460
621 spin_lock_irqsave(&can->lock, irq);461 spin_lock_irqsave(&can->lock, irq);
622 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);462 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
623 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);463 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
624
625 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,464 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
626 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);465 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
627
628 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);466 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
629 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;467 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
630 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);468 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
@@ -637,11 +475,10 @@ static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) · 6 unmodified lines
637 }475 }
638 /* Reset interrupt handling */476 /* Reset interrupt handling */
639 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);477 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
640 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);478 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
641 479
642 kvaser_pciefd_set_tx_irq(can);480 kvaser_pciefd_set_tx_irq(can);
643 kvaser_pciefd_setup_controller(can);481 kvaser_pciefd_setup_controller(can);
644
645 can->can.state = CAN_STATE_ERROR_ACTIVE;482 can->can.state = CAN_STATE_ERROR_ACTIVE;
646 netif_wake_queue(can->can.dev);483 netif_wake_queue(can->can.dev);
647 can->bec.txerr = 0;484 can->bec.txerr = 0;
@@ -659,10 +496,9 @@ static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can) · 11 unmodified lines
659 496
660 spin_lock_irqsave(&can->lock, irq);497 spin_lock_irqsave(&can->lock, irq);
661 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);498 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
662 top = (pwm_ctrl >> KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT) & 0xff;499 top = FIELD_GET(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, pwm_ctrl);
663
664 /* Set duty cycle to zero */500 /* Set duty cycle to zero */
665 pwm_ctrl |= top;501 pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, top);
666 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);502 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
667 spin_unlock_irqrestore(&can->lock, irq);503 spin_unlock_irqrestore(&can->lock, irq);
668}504}
@@ -675,18 +511,17 @@ static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can) · 6 unmodified lines
675 511
676 kvaser_pciefd_pwm_stop(can);512 kvaser_pciefd_pwm_stop(can);
677 spin_lock_irqsave(&can->lock, irq);513 spin_lock_irqsave(&can->lock, irq);
678 514 /* Set frequency to 500 KHz */
679 /* Set frequency to 500 KHz*/
680 top = can->kv_pcie->bus_freq / (2 * 500000) - 1;515 top = can->kv_pcie->bus_freq / (2 * 500000) - 1;
681 516
682 pwm_ctrl = top & 0xff;517 pwm_ctrl = FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, top);
683 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;518 pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, top);
684 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);519 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
685 520
686 /* Set duty cycle to 95 */521 /* Set duty cycle to 95 */
687 trigger = (100 * top - 95 * (top + 1) + 50) / 100;522 trigger = (100 * top - 95 * (top + 1) + 50) / 100;
688 pwm_ctrl = trigger & 0xff;523 pwm_ctrl = FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, trigger);
689 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;524 pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, top);
690 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);525 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
691 spin_unlock_irqrestore(&can->lock, irq);526 spin_unlock_irqrestore(&can->lock, irq);
692}527}
@@ -741,7 +576,6 @@ static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p, · 48 unmodified lines
741 int seq = can->echo_idx;576 int seq = can->echo_idx;
742 577
743 memset(p, 0, sizeof(*p));578 memset(p, 0, sizeof(*p));
744
745 if (can->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)579 if (can->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
746 p->header[1] |= KVASER_PCIEFD_TPACKET_SMS;580 p->header[1] |= KVASER_PCIEFD_TPACKET_SMS;
747 581
@@ -751,19 +585,24 @@ static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p, · 3 unmodified lines
751 if (cf->can_id & CAN_EFF_FLAG)585 if (cf->can_id & CAN_EFF_FLAG)
752 p->header[0] |= KVASER_PCIEFD_RPACKET_IDE;586 p->header[0] |= KVASER_PCIEFD_RPACKET_IDE;
753 587
754 p->header[0] |= cf->can_id & CAN_EFF_MASK;588 p->header[0] |= FIELD_PREP(KVASER_PCIEFD_RPACKET_ID_MASK, cf->can_id);
755 p->header[1] |= can_fd_len2dlc(cf->len) << KVASER_PCIEFD_RPACKET_DLC_SHIFT;
756 p->header[1] |= KVASER_PCIEFD_TPACKET_AREQ;589 p->header[1] |= KVASER_PCIEFD_TPACKET_AREQ;
757 590
758 if (can_is_canfd_skb(skb)) {591 if (can_is_canfd_skb(skb)) {
592 p->header[1] |= FIELD_PREP(KVASER_PCIEFD_RPACKET_DLC_MASK,
593 can_fd_len2dlc(cf->len));
759 p->header[1] |= KVASER_PCIEFD_RPACKET_FDF;594 p->header[1] |= KVASER_PCIEFD_RPACKET_FDF;
760 if (cf->flags & CANFD_BRS)595 if (cf->flags & CANFD_BRS)
761 p->header[1] |= KVASER_PCIEFD_RPACKET_BRS;596 p->header[1] |= KVASER_PCIEFD_RPACKET_BRS;
762 if (cf->flags & CANFD_ESI)597 if (cf->flags & CANFD_ESI)
763 p->header[1] |= KVASER_PCIEFD_RPACKET_ESI;598 p->header[1] |= KVASER_PCIEFD_RPACKET_ESI;
599 } else {
600 p->header[1] |=
601 FIELD_PREP(KVASER_PCIEFD_RPACKET_DLC_MASK,
602 can_get_cc_dlc((struct can_frame *)cf, can->can.ctrlmode));
764 }603 }
765 604
766 p->header[1] |= seq & KVASER_PCIEFD_PACKET_SEQ_MSK;605 p->header[1] |= FIELD_PREP(KVASER_PCIEFD_PACKET_SEQ_MASK, seq);
767 606
768 packet_size = cf->len;607 packet_size = cf->len;
769 memcpy(p->data, cf->data, packet_size);608 memcpy(p->data, cf->data, packet_size);
@@ -777,16 +616,15 @@ static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, · 7 unmodified lines
777 struct kvaser_pciefd_can *can = netdev_priv(netdev);616 struct kvaser_pciefd_can *can = netdev_priv(netdev);
778 unsigned long irq_flags;617 unsigned long irq_flags;
779 struct kvaser_pciefd_tx_packet packet;618 struct kvaser_pciefd_tx_packet packet;
780 int nwords;619 int nr_words;
781 u8 count;620 u8 count;
782 621
783 if (can_dev_dropped_skb(netdev, skb))622 if (can_dev_dropped_skb(netdev, skb))
784 return NETDEV_TX_OK;623 return NETDEV_TX_OK;
785 624
786 nwords = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);625 nr_words = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);
787 626
788 spin_lock_irqsave(&can->echo_lock, irq_flags);627 spin_lock_irqsave(&can->echo_lock, irq_flags);
789
790 /* Prepare and save echo skb in internal slot */628 /* Prepare and save echo skb in internal slot */
791 can_put_echo_skb(skb, netdev, can->echo_idx, 0);629 can_put_echo_skb(skb, netdev, can->echo_idx, 0);
792 630
@@ -799,13 +637,13 @@ static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, · 6 unmodified lines
799 iowrite32(packet.header[1],637 iowrite32(packet.header[1],
800 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);638 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
801 639
802 if (nwords) {640 if (nr_words) {
803 u32 data_last = ((u32 *)packet.data)[nwords - 1];641 u32 data_last = ((u32 *)packet.data)[nr_words - 1];
804 642
805 /* Write data to fifo, except last word */643 /* Write data to fifo, except last word */
806 iowrite32_rep(can->reg_base +644 iowrite32_rep(can->reg_base +
807 KVASER_PCIEFD_KCAN_FIFO_REG, packet.data,645 KVASER_PCIEFD_KCAN_FIFO_REG, packet.data,
808 nwords - 1);646 nr_words - 1);
809 /* Write last word to end of fifo */647 /* Write last word to end of fifo */
810 __raw_writel(data_last, can->reg_base +648 __raw_writel(data_last, can->reg_base +
811 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);649 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
@@ -815,14 +653,13 @@ static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, · 3 unmodified lines
815 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);653 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
816 }654 }
817 655
818 count = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);656 count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
657 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
819 /* No room for a new message, stop the queue until at least one658 /* No room for a new message, stop the queue until at least one
820 * successful transmit659 * successful transmit
821 */660 */
822 if (count >= KVASER_PCIEFD_CAN_TX_MAX_COUNT ||661 if (count >= can->can.echo_skb_max || can->can.echo_skb[can->echo_idx])
823 can->can.echo_skb[can->echo_idx])
824 netif_stop_queue(netdev);662 netif_stop_queue(netdev);
825
826 spin_unlock_irqrestore(&can->echo_lock, irq_flags);663 spin_unlock_irqrestore(&can->echo_lock, irq_flags);
827 664
828 return NETDEV_TX_OK;665 return NETDEV_TX_OK;
@@ -840,25 +677,20 @@ static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data) · 11 unmodified lines
840 else677 else
841 bt = &can->can.bittiming;678 bt = &can->can.bittiming;
842 679
843 btrn = ((bt->phase_seg2 - 1) & 0x1f) <<680 btrn = FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK, bt->phase_seg2 - 1) |
844 KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT |681 FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK, bt->prop_seg + bt->phase_seg1 - 1) |
845 (((bt->prop_seg + bt->phase_seg1) - 1) & 0x1ff) <<682 FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_SJW_MASK, bt->sjw - 1) |
846 KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT |683 FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_BRP_MASK, bt->brp - 1);
847 ((bt->sjw - 1) & 0xf) << KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT |
848 ((bt->brp - 1) & 0x1fff);
849 684
850 spin_lock_irqsave(&can->lock, irq_flags);685 spin_lock_irqsave(&can->lock, irq_flags);
851 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);686 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
852
853 /* Put the circuit in reset mode */687 /* Put the circuit in reset mode */
854 iowrite32(mode | KVASER_PCIEFD_KCAN_MODE_RM,688 iowrite32(mode | KVASER_PCIEFD_KCAN_MODE_RM,
855 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);689 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
856 690
857 /* Can only set bittiming if in reset mode */691 /* Can only set bittiming if in reset mode */
858 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG,692 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG,
859 test, test & KVASER_PCIEFD_KCAN_MODE_RM,693 test, test & KVASER_PCIEFD_KCAN_MODE_RM, 0, 10);
860 0, 10);
861
862 if (ret) {694 if (ret) {
863 spin_unlock_irqrestore(&can->lock, irq_flags);695 spin_unlock_irqrestore(&can->lock, irq_flags);
864 return -EBUSY;696 return -EBUSY;
@@ -868,11 +700,10 @@ static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data) · 3 unmodified lines
868 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG);700 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG);
869 else701 else
870 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG);702 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG);
871
872 /* Restore previous reset mode status */703 /* Restore previous reset mode status */
873 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);704 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
874
875 spin_unlock_irqrestore(&can->lock, irq_flags);705 spin_unlock_irqrestore(&can->lock, irq_flags);
706
876 return 0;707 return 0;
877}708}
878 709
@@ -910,6 +741,7 @@ static int kvaser_pciefd_get_berr_counter(const struct net_device *ndev, · 31 unmodified lines
910 741
911 bec->rxerr = can->bec.rxerr;742 bec->rxerr = can->bec.rxerr;
912 bec->txerr = can->bec.txerr;743 bec->txerr = can->bec.txerr;
744
913 return 0;745 return 0;
914}746}
915 747
@@ -941,7 +773,7 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) · 25 unmodified lines
941 for (i = 0; i < pcie->nr_channels; i++) {773 for (i = 0; i < pcie->nr_channels; i++) {
942 struct net_device *netdev;774 struct net_device *netdev;
943 struct kvaser_pciefd_can *can;775 struct kvaser_pciefd_can *can;
944 u32 status, tx_npackets;776 u32 status, tx_nr_packets_max;
945 777
946 netdev = alloc_candev(sizeof(struct kvaser_pciefd_can),778 netdev = alloc_candev(sizeof(struct kvaser_pciefd_can),
947 KVASER_PCIEFD_CAN_TX_MAX_COUNT);779 KVASER_PCIEFD_CAN_TX_MAX_COUNT);
@@ -953,7 +785,6 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) · 5 unmodified lines
953 netdev->ethtool_ops = &kvaser_pciefd_ethtool_ops;785 netdev->ethtool_ops = &kvaser_pciefd_ethtool_ops;
954 can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE +786 can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE +
955 i * KVASER_PCIEFD_KCAN_BASE_OFFSET;787 i * KVASER_PCIEFD_KCAN_BASE_OFFSET;
956
957 can->kv_pcie = pcie;788 can->kv_pcie = pcie;
958 can->cmd_seq = 0;789 can->cmd_seq = 0;
959 can->err_rep_cnt = 0;790 can->err_rep_cnt = 0;
@@ -962,41 +793,31 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) · 2 unmodified lines
962 793
963 init_completion(&can->start_comp);794 init_completion(&can->start_comp);
964 init_completion(&can->flush_comp);795 init_completion(&can->flush_comp);
965 timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer,796 timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer, 0);
966 0);
967 797
968 /* Disable Bus load reporting */798 /* Disable Bus load reporting */
969 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);799 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);
970 800
971 tx_npackets = ioread32(can->reg_base +801 tx_nr_packets_max =
972 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);802 FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK,
973 if (((tx_npackets >> KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT) &803 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
974 0xff) < KVASER_PCIEFD_CAN_TX_MAX_COUNT) {
975 dev_err(&pcie->pci->dev,
976 "Max Tx count is smaller than expected\n");
977
978 free_candev(netdev);
979 return -ENODEV;
980 }
981 804
982 can->can.clock.freq = pcie->freq;805 can->can.clock.freq = pcie->freq;
983 can->can.echo_skb_max = KVASER_PCIEFD_CAN_TX_MAX_COUNT;806 can->can.echo_skb_max = min(KVASER_PCIEFD_CAN_TX_MAX_COUNT, tx_nr_packets_max - 1);
984 can->echo_idx = 0;807 can->echo_idx = 0;
985 spin_lock_init(&can->echo_lock);808 spin_lock_init(&can->echo_lock);
986 spin_lock_init(&can->lock);809 spin_lock_init(&can->lock);
810
987 can->can.bittiming_const = &kvaser_pciefd_bittiming_const;811 can->can.bittiming_const = &kvaser_pciefd_bittiming_const;
988 can->can.data_bittiming_const = &kvaser_pciefd_bittiming_const;812 can->can.data_bittiming_const = &kvaser_pciefd_bittiming_const;
989
990 can->can.do_set_bittiming = kvaser_pciefd_set_nominal_bittiming;813 can->can.do_set_bittiming = kvaser_pciefd_set_nominal_bittiming;
991 can->can.do_set_data_bittiming =814 can->can.do_set_data_bittiming = kvaser_pciefd_set_data_bittiming;
992 kvaser_pciefd_set_data_bittiming;
993
994 can->can.do_set_mode = kvaser_pciefd_set_mode;815 can->can.do_set_mode = kvaser_pciefd_set_mode;
995 can->can.do_get_berr_counter = kvaser_pciefd_get_berr_counter;816 can->can.do_get_berr_counter = kvaser_pciefd_get_berr_counter;
996
997 can->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |817 can->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
998 CAN_CTRLMODE_FD |818 CAN_CTRLMODE_FD |
999 CAN_CTRLMODE_FD_NON_ISO;819 CAN_CTRLMODE_FD_NON_ISO |
820 CAN_CTRLMODE_CC_LEN8_DLC;
1000 821
1001 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);822 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1002 if (!(status & KVASER_PCIEFD_KCAN_STAT_FD)) {823 if (!(status & KVASER_PCIEFD_KCAN_STAT_FD)) {
@@ -1011,10 +832,9 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) · 8 unmodified lines
1011 can->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;832 can->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;
1012 833
1013 netdev->flags |= IFF_ECHO;834 netdev->flags |= IFF_ECHO;
1014
1015 SET_NETDEV_DEV(netdev, &pcie->pci->dev);835 SET_NETDEV_DEV(netdev, &pcie->pci->dev);
1016 836
1017 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);837 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1018 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,838 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
1019 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);839 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1020 840
@@ -1073,18 +893,16 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) · 52 unmodified lines
1073 for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) {893 for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) {
1074 unsigned int offset = KVASER_PCIEFD_DMA_MAP_BASE + 8 * i;894 unsigned int offset = KVASER_PCIEFD_DMA_MAP_BASE + 8 * i;
1075 895
1076 pcie->dma_data[i] =896 pcie->dma_data[i] = dmam_alloc_coherent(&pcie->pci->dev,
1077 dmam_alloc_coherent(&pcie->pci->dev,897 KVASER_PCIEFD_DMA_SIZE,
1078 KVASER_PCIEFD_DMA_SIZE,898 &dma_addr[i],
1079 &dma_addr[i],899 GFP_KERNEL);
1080 GFP_KERNEL);
1081 900
1082 if (!pcie->dma_data[i] || !dma_addr[i]) {901 if (!pcie->dma_data[i] || !dma_addr[i]) {
1083 dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n",902 dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n",
1084 KVASER_PCIEFD_DMA_SIZE);903 KVASER_PCIEFD_DMA_SIZE);
1085 return -ENOMEM;904 return -ENOMEM;
1086 }905 }
1087
1088 kvaser_pciefd_write_dma_map(pcie, dma_addr[i], offset);906 kvaser_pciefd_write_dma_map(pcie, dma_addr[i], offset);
1089 }907 }
1090 908
@@ -1092,10 +910,10 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) · 1 unmodified line
1092 iowrite32(KVASER_PCIEFD_SRB_CMD_FOR | KVASER_PCIEFD_SRB_CMD_RDB0 |910 iowrite32(KVASER_PCIEFD_SRB_CMD_FOR | KVASER_PCIEFD_SRB_CMD_RDB0 |
1093 KVASER_PCIEFD_SRB_CMD_RDB1,911 KVASER_PCIEFD_SRB_CMD_RDB1,
1094 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);912 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1095
1096 /* Empty Rx FIFO */913 /* Empty Rx FIFO */
1097 srb_packet_count = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG) &914 srb_packet_count =
1098 KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK;915 FIELD_GET(KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK,
916 ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG));
1099 while (srb_packet_count) {917 while (srb_packet_count) {
1100 /* Drop current packet in FIFO */918 /* Drop current packet in FIFO */
1101 ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG);919 ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG);
@@ -1117,37 +935,21 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) · 15 unmodified lines
1117 935
1118static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie)936static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie)
1119{937{
1120 u32 sysid, srb_status, build;938 u32 version, srb_status, build;
1121 u8 sysid_nr_chan;
1122 int ret;
1123
1124 ret = kvaser_pciefd_read_cfg(pcie);
1125 if (ret)
1126 return ret;
1127
1128 sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
1129 sysid_nr_chan = (sysid >> KVASER_PCIEFD_SYSID_NRCHAN_SHIFT) & 0xff;
1130 if (pcie->nr_channels != sysid_nr_chan) {
1131 dev_err(&pcie->pci->dev,
1132 "Number of channels does not match: %u vs %u\n",
1133 pcie->nr_channels,
1134 sysid_nr_chan);
1135 return -ENODEV;
1136 }
1137 939
1138 if (pcie->nr_channels > KVASER_PCIEFD_MAX_CAN_CHANNELS)940 version = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
1139 pcie->nr_channels = KVASER_PCIEFD_MAX_CAN_CHANNELS;941 pcie->nr_channels = min(KVASER_PCIEFD_MAX_CAN_CHANNELS,
942 FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK, version));
1140 943
1141 build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG);944 build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG);
1142 dev_dbg(&pcie->pci->dev, "Version %u.%u.%u\n",945 dev_dbg(&pcie->pci->dev, "Version %lu.%lu.%lu\n",
1143 (sysid >> KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT) & 0xff,946 FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK, version),
1144 sysid & 0xff,947 FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK, version),
1145 (build >> KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT) & 0x7fff);948 FIELD_GET(KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK, build));
1146 949
1147 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);950 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1148 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) {951 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) {
1149 dev_err(&pcie->pci->dev,952 dev_err(&pcie->pci->dev, "Hardware without DMA is not supported\n");
1150 "Hardware without DMA is not supported\n");
1151 return -ENODEV;953 return -ENODEV;
1152 }954 }
1153 955
@@ -1157,10 +959,10 @@ static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie) · 3 unmodified lines
1157 pcie->freq_to_ticks_div = pcie->freq / 1000000;959 pcie->freq_to_ticks_div = pcie->freq / 1000000;
1158 if (pcie->freq_to_ticks_div == 0)960 if (pcie->freq_to_ticks_div == 0)
1159 pcie->freq_to_ticks_div = 1;961 pcie->freq_to_ticks_div = 1;
1160
1161 /* Turn off all loopback functionality */962 /* Turn off all loopback functionality */
1162 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG);963 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG);
1163 return ret;964
965 return 0;
1164}966}
1165 967
1166static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,968static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,
@@ -1170,56 +972,48 @@ static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie, · 3 unmodified lines
1170 struct sk_buff *skb;972 struct sk_buff *skb;
1171 struct canfd_frame *cf;973 struct canfd_frame *cf;
1172 struct can_priv *priv;974 struct can_priv *priv;
1173 struct net_device_stats *stats;975 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1174 struct skb_shared_hwtstamps *shhwtstamps;976 u8 dlc;
1175 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1176 977
1177 if (ch_id >= pcie->nr_channels)978 if (ch_id >= pcie->nr_channels)
1178 return -EIO;979 return -EIO;
1179 980
1180 priv = &pcie->can[ch_id]->can;981 priv = &pcie->can[ch_id]->can;
1181 stats = &priv->dev->stats;982 dlc = FIELD_GET(KVASER_PCIEFD_RPACKET_DLC_MASK, p->header[1]);
1182 983
1183 if (p->header[1] & KVASER_PCIEFD_RPACKET_FDF) {984 if (p->header[1] & KVASER_PCIEFD_RPACKET_FDF) {
1184 skb = alloc_canfd_skb(priv->dev, &cf);985 skb = alloc_canfd_skb(priv->dev, &cf);
1185 if (!skb) {986 if (!skb) {
1186 stats->rx_dropped++;987 priv->dev->stats.rx_dropped++;
1187 return -ENOMEM;988 return -ENOMEM;
1188 }989 }
1189 990
991 cf->len = can_fd_dlc2len(dlc);
1190 if (p->header[1] & KVASER_PCIEFD_RPACKET_BRS)992 if (p->header[1] & KVASER_PCIEFD_RPACKET_BRS)
1191 cf->flags |= CANFD_BRS;993 cf->flags |= CANFD_BRS;
1192
1193 if (p->header[1] & KVASER_PCIEFD_RPACKET_ESI)994 if (p->header[1] & KVASER_PCIEFD_RPACKET_ESI)
1194 cf->flags |= CANFD_ESI;995 cf->flags |= CANFD_ESI;
1195 } else {996 } else {
1196 skb = alloc_can_skb(priv->dev, (struct can_frame **)&cf);997 skb = alloc_can_skb(priv->dev, (struct can_frame **)&cf);
1197 if (!skb) {998 if (!skb) {
1198 stats->rx_dropped++;999 priv->dev->stats.rx_dropped++;
1199 return -ENOMEM;1000 return -ENOMEM;
1200 }1001 }
1002 can_frame_set_cc_len((struct can_frame *)cf, dlc, priv->ctrlmode);
1201 }1003 }
1202 1004
1203 cf->can_id = p->header[0] & CAN_EFF_MASK;1005 cf->can_id = FIELD_GET(KVASER_PCIEFD_RPACKET_ID_MASK, p->header[0]);
1204 if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE)1006 if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE)
1205 cf->can_id |= CAN_EFF_FLAG;1007 cf->can_id |= CAN_EFF_FLAG;
1206 1008
1207 cf->len = can_fd_dlc2len(p->header[1] >> KVASER_PCIEFD_RPACKET_DLC_SHIFT);
1208
1209 if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR) {1009 if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR) {
1210 cf->can_id |= CAN_RTR_FLAG;1010 cf->can_id |= CAN_RTR_FLAG;
1211 } else {1011 } else {
1212 memcpy(cf->data, data, cf->len);1012 memcpy(cf->data, data, cf->len);
1213 1013 priv->dev->stats.rx_bytes += cf->len;
1214 stats->rx_bytes += cf->len;
1215 }1014 }
1216 stats->rx_packets++;1015 priv->dev->stats.rx_packets++;
1217 1016 kvaser_pciefd_set_skb_timestamp(pcie, skb, p->timestamp);
1218 shhwtstamps = skb_hwtstamps(skb);
1219
1220 shhwtstamps->hwtstamp =
1221 ns_to_ktime(div_u64(p->timestamp * 1000,
1222 pcie->freq_to_ticks_div));
1223 1017
1224 return netif_rx(skb);1018 return netif_rx(skb);
1225}1019}
@@ -1239,7 +1033,6 @@ static void kvaser_pciefd_change_state(struct kvaser_pciefd_can *can, · 13 unmodified lines
1239 spin_lock_irqsave(&can->lock, irq_flags);1033 spin_lock_irqsave(&can->lock, irq_flags);
1240 netif_stop_queue(can->can.dev);1034 netif_stop_queue(can->can.dev);
1241 spin_unlock_irqrestore(&can->lock, irq_flags);1035 spin_unlock_irqrestore(&can->lock, irq_flags);
1242
1243 /* Prevent CAN controller from auto recover from bus off */1036 /* Prevent CAN controller from auto recover from bus off */
1244 if (!can->can.restart_ms) {1037 if (!can->can.restart_ms) {
1245 kvaser_pciefd_start_controller_flush(can);1038 kvaser_pciefd_start_controller_flush(can);
@@ -1257,7 +1050,7 @@ static void kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet *p, · 11 unmodified lines
1257 if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF ||1050 if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF ||
1258 p->header[0] & KVASER_PCIEFD_SPACK_IRM)1051 p->header[0] & KVASER_PCIEFD_SPACK_IRM)
1259 *new_state = CAN_STATE_BUS_OFF;1052 *new_state = CAN_STATE_BUS_OFF;
1260 else if (bec->txerr >= 255 || bec->rxerr >= 255)1053 else if (bec->txerr >= 255 || bec->rxerr >= 255)
1261 *new_state = CAN_STATE_BUS_OFF;1054 *new_state = CAN_STATE_BUS_OFF;
1262 else if (p->header[1] & KVASER_PCIEFD_SPACK_EPLR)1055 else if (p->header[1] & KVASER_PCIEFD_SPACK_EPLR)
1263 *new_state = CAN_STATE_ERROR_PASSIVE;1056 *new_state = CAN_STATE_ERROR_PASSIVE;
@@ -1282,23 +1075,16 @@ static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can, · 18 unmodified lines
1282 struct net_device *ndev = can->can.dev;1075 struct net_device *ndev = can->can.dev;
1283 struct sk_buff *skb;1076 struct sk_buff *skb;
1284 struct can_frame *cf = NULL;1077 struct can_frame *cf = NULL;
1285 struct skb_shared_hwtstamps *shhwtstamps;
1286 struct net_device_stats *stats = &ndev->stats;
1287 1078
1288 old_state = can->can.state;1079 old_state = can->can.state;
1289 1080
1290 bec.txerr = p->header[0] & 0xff;1081 bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);
1291 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;1082 bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);
1292
1293 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
1294 &rx_state);
1295 1083
1084 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, &rx_state);
1296 skb = alloc_can_err_skb(ndev, &cf);1085 skb = alloc_can_err_skb(ndev, &cf);
1297
1298 if (new_state != old_state) {1086 if (new_state != old_state) {
1299 kvaser_pciefd_change_state(can, cf, new_state, tx_state,1087 kvaser_pciefd_change_state(can, cf, new_state, tx_state, rx_state);
1300 rx_state);
1301
1302 if (old_state == CAN_STATE_BUS_OFF &&1088 if (old_state == CAN_STATE_BUS_OFF &&
1303 new_state == CAN_STATE_ERROR_ACTIVE &&1089 new_state == CAN_STATE_ERROR_ACTIVE &&
1304 can->can.restart_ms) {1090 can->can.restart_ms) {
@@ -1311,28 +1097,25 @@ static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can, · 6 unmodified lines
1311 can->err_rep_cnt++;1097 can->err_rep_cnt++;
1312 can->can.can_stats.bus_error++;1098 can->can.can_stats.bus_error++;
1313 if (p->header[1] & KVASER_PCIEFD_EPACK_DIR_TX)1099 if (p->header[1] & KVASER_PCIEFD_EPACK_DIR_TX)
1314 stats->tx_errors++;1100 ndev->stats.tx_errors++;
1315 else1101 else
1316 stats->rx_errors++;1102 ndev->stats.rx_errors++;
1317 1103
1318 can->bec.txerr = bec.txerr;1104 can->bec.txerr = bec.txerr;
1319 can->bec.rxerr = bec.rxerr;1105 can->bec.rxerr = bec.rxerr;
1320 1106
1321 if (!skb) {1107 if (!skb) {
1322 stats->rx_dropped++;1108 ndev->stats.rx_dropped++;
1323 return -ENOMEM;1109 return -ENOMEM;
1324 }1110 }
1325 1111
1326 shhwtstamps = skb_hwtstamps(skb);1112 kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1327 shhwtstamps->hwtstamp =
1328 ns_to_ktime(div_u64(p->timestamp * 1000,
1329 can->kv_pcie->freq_to_ticks_div));
1330 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_CNT;1113 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_CNT;
1331
1332 cf->data[6] = bec.txerr;1114 cf->data[6] = bec.txerr;
1333 cf->data[7] = bec.rxerr;1115 cf->data[7] = bec.rxerr;
1334 1116
1335 netif_rx(skb);1117 netif_rx(skb);
1118
1336 return 0;1119 return 0;
1337}1120}
1338 1121
@@ -1340,19 +1123,19 @@ static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie, · 1 unmodified line
1340 struct kvaser_pciefd_rx_packet *p)1123 struct kvaser_pciefd_rx_packet *p)
1341{1124{
1342 struct kvaser_pciefd_can *can;1125 struct kvaser_pciefd_can *can;
1343 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;1126 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1344 1127
1345 if (ch_id >= pcie->nr_channels)1128 if (ch_id >= pcie->nr_channels)
1346 return -EIO;1129 return -EIO;
1347 1130
1348 can = pcie->can[ch_id];1131 can = pcie->can[ch_id];
1349
1350 kvaser_pciefd_rx_error_frame(can, p);1132 kvaser_pciefd_rx_error_frame(can, p);
1351 if (can->err_rep_cnt >= KVASER_PCIEFD_MAX_ERR_REP)1133 if (can->err_rep_cnt >= KVASER_PCIEFD_MAX_ERR_REP)
1352 /* Do not report more errors, until bec_poll_timer expires */1134 /* Do not report more errors, until bec_poll_timer expires */
1353 kvaser_pciefd_disable_err_gen(can);1135 kvaser_pciefd_disable_err_gen(can);
1354 /* Start polling the error counters */1136 /* Start polling the error counters */
1355 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);1137 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1138
1356 return 0;1139 return 0;
1357}1140}
1358 1141
@@ -1364,29 +1147,22 @@ static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can, · 5 unmodified lines
1364 1147
1365 old_state = can->can.state;1148 old_state = can->can.state;
1366 1149
1367 bec.txerr = p->header[0] & 0xff;1150 bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);
1368 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;1151 bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);
1369
1370 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
1371 &rx_state);
1372 1152
1153 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, &rx_state);
1373 if (new_state != old_state) {1154 if (new_state != old_state) {
1374 struct net_device *ndev = can->can.dev;1155 struct net_device *ndev = can->can.dev;
1375 struct sk_buff *skb;1156 struct sk_buff *skb;
1376 struct can_frame *cf;1157 struct can_frame *cf;
1377 struct skb_shared_hwtstamps *shhwtstamps;
1378 1158
1379 skb = alloc_can_err_skb(ndev, &cf);1159 skb = alloc_can_err_skb(ndev, &cf);
1380 if (!skb) {1160 if (!skb) {
1381 struct net_device_stats *stats = &ndev->stats;1161 ndev->stats.rx_dropped++;
1382
1383 stats->rx_dropped++;
1384 return -ENOMEM;1162 return -ENOMEM;
1385 }1163 }
1386 1164
1387 kvaser_pciefd_change_state(can, cf, new_state, tx_state,1165 kvaser_pciefd_change_state(can, cf, new_state, tx_state, rx_state);
1388 rx_state);
1389
1390 if (old_state == CAN_STATE_BUS_OFF &&1166 if (old_state == CAN_STATE_BUS_OFF &&
1391 new_state == CAN_STATE_ERROR_ACTIVE &&1167 new_state == CAN_STATE_ERROR_ACTIVE &&
1392 can->can.restart_ms) {1168 can->can.restart_ms) {
@@ -1394,10 +1170,7 @@ static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can, · 1 unmodified line
1394 cf->can_id |= CAN_ERR_RESTARTED;1170 cf->can_id |= CAN_ERR_RESTARTED;
1395 }1171 }
1396 1172
1397 shhwtstamps = skb_hwtstamps(skb);1173 kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1398 shhwtstamps->hwtstamp =
1399 ns_to_ktime(div_u64(p->timestamp * 1000,
1400 can->kv_pcie->freq_to_ticks_div));
1401 1174
1402 cf->data[6] = bec.txerr;1175 cf->data[6] = bec.txerr;
1403 cf->data[7] = bec.rxerr;1176 cf->data[7] = bec.rxerr;
@@ -1419,7 +1192,7 @@ static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie, · 15 unmodified lines
1419 struct kvaser_pciefd_can *can;1192 struct kvaser_pciefd_can *can;
1420 u8 cmdseq;1193 u8 cmdseq;
1421 u32 status;1194 u32 status;
1422 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;1195 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1423 1196
1424 if (ch_id >= pcie->nr_channels)1197 if (ch_id >= pcie->nr_channels)
1425 return -EIO;1198 return -EIO;
@@ -1427,43 +1200,40 @@ static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie, · 1 unmodified line
1427 can = pcie->can[ch_id];1200 can = pcie->can[ch_id];
1428 1201
1429 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);1202 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1430 cmdseq = (status >> KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT) & 0xff;1203 cmdseq = FIELD_GET(KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK, status);
1431 1204
1432 /* Reset done, start abort and flush */1205 /* Reset done, start abort and flush */
1433 if (p->header[0] & KVASER_PCIEFD_SPACK_IRM &&1206 if (p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1434 p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&1207 p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1435 p->header[1] & KVASER_PCIEFD_SPACK_AUTO &&1208 p->header[1] & KVASER_PCIEFD_SPACK_AUTO &&
1436 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&1209 cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1]) &&
1437 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {1210 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1438 u32 cmd;
1439
1440 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,1211 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
1441 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);1212 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1442 cmd = KVASER_PCIEFD_KCAN_CMD_AT;1213 kvaser_pciefd_abort_flush_reset(can);
1443 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
1444 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
1445 } else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&1214 } else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&
1446 p->header[0] & KVASER_PCIEFD_SPACK_IRM &&1215 p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1447 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&1216 cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1]) &&
1448 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {1217 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1449 /* Reset detected, send end of flush if no packet are in FIFO */1218 /* Reset detected, send end of flush if no packet are in FIFO */
1450 u8 count = ioread32(can->reg_base +1219 u8 count;
1451 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1452 1220
1221 count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
1222 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
1453 if (!count)1223 if (!count)
1454 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,1224 iowrite32(FIELD_PREP(KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK,
1225 KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH),
1455 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);1226 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1456 } else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) &&1227 } else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) &&
1457 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK)) {1228 cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1])) {
1458 /* Response to status request received */1229 /* Response to status request received */
1459 kvaser_pciefd_handle_status_resp(can, p);1230 kvaser_pciefd_handle_status_resp(can, p);
1460 if (can->can.state != CAN_STATE_BUS_OFF &&1231 if (can->can.state != CAN_STATE_BUS_OFF &&
1461 can->can.state != CAN_STATE_ERROR_ACTIVE) {1232 can->can.state != CAN_STATE_ERROR_ACTIVE) {
1462 mod_timer(&can->bec_poll_timer,1233 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1463 KVASER_PCIEFD_BEC_POLL_FREQ);
1464 }1234 }
1465 } else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&1235 } else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1466 !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK)) {1236 !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MASK)) {
1467 /* Reset to bus on detected */1237 /* Reset to bus on detected */
1468 if (!completion_done(&can->start_comp))1238 if (!completion_done(&can->start_comp))
1469 complete(&can->start_comp);1239 complete(&can->start_comp);
@@ -1472,50 +1242,14 @@ static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie, · 2 unmodified lines
1472 return 0;1242 return 0;
1473}1243}
1474 1244
1475static int kvaser_pciefd_handle_eack_packet(struct kvaser_pciefd *pcie,
1476 struct kvaser_pciefd_rx_packet *p)
1477{
1478 struct kvaser_pciefd_can *can;
1479 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1480
1481 if (ch_id >= pcie->nr_channels)
1482 return -EIO;
1483
1484 can = pcie->can[ch_id];
1485
1486 /* If this is the last flushed packet, send end of flush */
1487 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1488 u8 count = ioread32(can->reg_base +
1489 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1490
1491 if (count == 0)
1492 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
1493 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1494 } else {
1495 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;
1496 int dlc = can_get_echo_skb(can->can.dev, echo_idx, NULL);
1497 struct net_device_stats *stats = &can->can.dev->stats;
1498
1499 stats->tx_bytes += dlc;
1500 stats->tx_packets++;
1501
1502 if (netif_queue_stopped(can->can.dev))
1503 netif_wake_queue(can->can.dev);
1504 }
1505
1506 return 0;
1507}
1508
1509static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can,1245static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can,
1510 struct kvaser_pciefd_rx_packet *p)1246 struct kvaser_pciefd_rx_packet *p)
1511{1247{
1512 struct sk_buff *skb;1248 struct sk_buff *skb;
1513 struct net_device_stats *stats = &can->can.dev->stats;
1514 struct can_frame *cf;1249 struct can_frame *cf;
1515 1250
1516 skb = alloc_can_err_skb(can->can.dev, &cf);1251 skb = alloc_can_err_skb(can->can.dev, &cf);
1517 1252 can->can.dev->stats.tx_errors++;
1518 stats->tx_errors++;
1519 if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) {1253 if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) {
1520 if (skb)1254 if (skb)
1521 cf->can_id |= CAN_ERR_LOSTARB;1255 cf->can_id |= CAN_ERR_LOSTARB;
@@ -1526,9 +1260,10 @@ static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can, · 4 unmodified lines
1526 1260
1527 if (skb) {1261 if (skb) {
1528 cf->can_id |= CAN_ERR_BUSERROR;1262 cf->can_id |= CAN_ERR_BUSERROR;
1263 kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1529 netif_rx(skb);1264 netif_rx(skb);
1530 } else {1265 } else {
1531 stats->rx_dropped++;1266 can->can.dev->stats.rx_dropped++;
1532 netdev_warn(can->can.dev, "No memory left for err_skb\n");1267 netdev_warn(can->can.dev, "No memory left for err_skb\n");
1533 }1268 }
1534}1269}
@@ -1538,7 +1273,7 @@ static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie, · 3 unmodified lines
1538{1273{
1539 struct kvaser_pciefd_can *can;1274 struct kvaser_pciefd_can *can;
1540 bool one_shot_fail = false;1275 bool one_shot_fail = false;
1541 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;1276 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1542 1277
1543 if (ch_id >= pcie->nr_channels)1278 if (ch_id >= pcie->nr_channels)
1544 return -EIO;1279 return -EIO;
@@ -1556,20 +1291,24 @@ static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie, · 11 unmodified lines
1556 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {1291 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1557 netdev_dbg(can->can.dev, "Packet was flushed\n");1292 netdev_dbg(can->can.dev, "Packet was flushed\n");
1558 } else {1293 } else {
1559 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;1294 int echo_idx = FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[0]);
1560 int dlc = can_get_echo_skb(can->can.dev, echo_idx, NULL);1295 int len;
1561 u8 count = ioread32(can->reg_base +1296 u8 count;
1562 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;1297 struct sk_buff *skb;
1563 1298
1564 if (count < KVASER_PCIEFD_CAN_TX_MAX_COUNT &&1299 skb = can->can.echo_skb[echo_idx];
1565 netif_queue_stopped(can->can.dev))1300 if (skb)
1301 kvaser_pciefd_set_skb_timestamp(pcie, skb, p->timestamp);
1302 len = can_get_echo_skb(can->can.dev, echo_idx, NULL);
1303 count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
1304 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
1305
1306 if (count < can->can.echo_skb_max && netif_queue_stopped(can->can.dev))
1566 netif_wake_queue(can->can.dev);1307 netif_wake_queue(can->can.dev);
1567 1308
1568 if (!one_shot_fail) {1309 if (!one_shot_fail) {
1569 struct net_device_stats *stats = &can->can.dev->stats;1310 can->can.dev->stats.tx_bytes += len;
1570 1311 can->can.dev->stats.tx_packets++;
1571 stats->tx_bytes += dlc;
1572 stats->tx_packets++;
1573 }1312 }
1574 }1313 }
1575 1314
@@ -1580,7 +1319,7 @@ static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie, · 4 unmodified lines
1580 struct kvaser_pciefd_rx_packet *p)1319 struct kvaser_pciefd_rx_packet *p)
1581{1320{
1582 struct kvaser_pciefd_can *can;1321 struct kvaser_pciefd_can *can;
1583 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;1322 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1584 1323
1585 if (ch_id >= pcie->nr_channels)1324 if (ch_id >= pcie->nr_channels)
1586 return -EIO;1325 return -EIO;
@@ -1619,15 +1358,15 @@ static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos, · 32 unmodified lines
1619 pos += 2;1358 pos += 2;
1620 p->timestamp = le64_to_cpu(timestamp);1359 p->timestamp = le64_to_cpu(timestamp);
1621 1360
1622 type = (p->header[1] >> KVASER_PCIEFD_PACKET_TYPE_SHIFT) & 0xf;1361 type = FIELD_GET(KVASER_PCIEFD_PACKET_TYPE_MASK, p->header[1]);
1623 switch (type) {1362 switch (type) {
1624 case KVASER_PCIEFD_PACK_TYPE_DATA:1363 case KVASER_PCIEFD_PACK_TYPE_DATA:
1625 ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]);1364 ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]);
1626 if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) {1365 if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) {
1627 u8 data_len;1366 u8 data_len;
1628 1367
1629 data_len = can_fd_dlc2len(p->header[1] >>1368 data_len = can_fd_dlc2len(FIELD_GET(KVASER_PCIEFD_RPACKET_DLC_MASK,
1630 KVASER_PCIEFD_RPACKET_DLC_SHIFT);1369 p->header[1]));
1631 pos += DIV_ROUND_UP(data_len, 4);1370 pos += DIV_ROUND_UP(data_len, 4);
1632 }1371 }
1633 break;1372 break;
@@ -1644,16 +1383,13 @@ static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos, · 10 unmodified lines
1644 ret = kvaser_pciefd_handle_error_packet(pcie, p);1383 ret = kvaser_pciefd_handle_error_packet(pcie, p);
1645 break;1384 break;
1646 1385
1647 case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK:
1648 ret = kvaser_pciefd_handle_eack_packet(pcie, p);
1649 break;
1650
1651 case KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK:1386 case KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK:
1652 ret = kvaser_pciefd_handle_eflush_packet(pcie, p);1387 ret = kvaser_pciefd_handle_eflush_packet(pcie, p);
1653 break;1388 break;
1654 1389
1655 case KVASER_PCIEFD_PACK_TYPE_ACK_DATA:1390 case KVASER_PCIEFD_PACK_TYPE_ACK_DATA:
1656 case KVASER_PCIEFD_PACK_TYPE_BUS_LOAD:1391 case KVASER_PCIEFD_PACK_TYPE_BUS_LOAD:
1392 case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK:
1657 case KVASER_PCIEFD_PACK_TYPE_TXRQ:1393 case KVASER_PCIEFD_PACK_TYPE_TXRQ:
1658 dev_info(&pcie->pci->dev,1394 dev_info(&pcie->pci->dev,
1659 "Received unexpected packet type 0x%08X\n", type);1395 "Received unexpected packet type 0x%08X\n", type);
@@ -1692,7 +1428,7 @@ static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf) · 32 unmodified lines
1692 return res;1428 return res;
1693}1429}
1694 1430
1695static int kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie)1431static void kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie)
1696{1432{
1697 u32 irq;1433 u32 irq;
1698 1434
@@ -1718,10 +1454,9 @@ static int kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie) · 19 unmodified lines
1718 dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq);1454 dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq);
1719 1455
1720 iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);1456 iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1721 return 0;
1722}1457}
1723 1458
1724static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can)1459static void kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can)
1725{1460{
1726 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);1461 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1727 1462
@@ -1739,7 +1474,6 @@ static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can) · 11 unmodified lines
1739 netdev_err(can->can.dev, "Rx FIFO overflow\n");1474 netdev_err(can->can.dev, "Rx FIFO overflow\n");
1740 1475
1741 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);1476 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1742 return 0;
1743}1477}
1744 1478
1745static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)1479static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)
@@ -1750,7 +1484,7 @@ static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev) · 4 unmodified lines
1750 1484
1751 board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG);1485 board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1752 1486
1753 if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MSK))1487 if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MASK))
1754 return IRQ_NONE;1488 return IRQ_NONE;
1755 1489
1756 if (board_irq & KVASER_PCIEFD_IRQ_SRB)1490 if (board_irq & KVASER_PCIEFD_IRQ_SRB)
@@ -1768,20 +1502,18 @@ static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev) · 11 unmodified lines
1768 kvaser_pciefd_transmit_irq(pcie->can[i]);1502 kvaser_pciefd_transmit_irq(pcie->can[i]);
1769 }1503 }
1770 1504
1771 iowrite32(board_irq, pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1772 return IRQ_HANDLED;1505 return IRQ_HANDLED;
1773}1506}
1774 1507
1775static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie)1508static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie)
1776{1509{
1777 int i;1510 int i;
1778 struct kvaser_pciefd_can *can;
1779 1511
1780 for (i = 0; i < pcie->nr_channels; i++) {1512 for (i = 0; i < pcie->nr_channels; i++) {
1781 can = pcie->can[i];1513 struct kvaser_pciefd_can *can = pcie->can[i];
1514
1782 if (can) {1515 if (can) {
1783 iowrite32(0,1516 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1784 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1785 kvaser_pciefd_pwm_stop(can);1517 kvaser_pciefd_pwm_stop(can);
1786 free_candev(can->can.dev);1518 free_candev(can->can.dev);
1787 }1519 }
@@ -1842,10 +1574,8 @@ static int kvaser_pciefd_probe(struct pci_dev *pdev, · 54 unmodified lines
1842 KVASER_PCIEFD_SRB_IRQ_DUF0 | KVASER_PCIEFD_SRB_IRQ_DUF1,1574 KVASER_PCIEFD_SRB_IRQ_DUF0 | KVASER_PCIEFD_SRB_IRQ_DUF1,
1843 pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG);1575 pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG);
1844 1576
1845 /* Reset IRQ handling, expected to be off before */1577 /* Enable PCI interrupts */
1846 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,1578 iowrite32(KVASER_PCIEFD_IRQ_ALL_MASK,
1847 pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1848 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1849 pcie->reg_base + KVASER_PCIEFD_IEN_REG);1579 pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1850 1580
1851 /* Ready the DMA buffers */1581 /* Ready the DMA buffers */
@@ -1884,14 +1614,13 @@ err_disable_pci: · 32 unmodified lines
1884 1614
1885static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie)1615static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie)
1886{1616{
1887 struct kvaser_pciefd_can *can;
1888 int i;1617 int i;
1889 1618
1890 for (i = 0; i < pcie->nr_channels; i++) {1619 for (i = 0; i < pcie->nr_channels; i++) {
1891 can = pcie->can[i];1620 struct kvaser_pciefd_can *can = pcie->can[i];
1621
1892 if (can) {1622 if (can) {
1893 iowrite32(0,1623 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1894 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1895 unregister_candev(can->can.dev);1624 unregister_candev(can->can.dev);
1896 del_timer(&can->bec_poll_timer);1625 del_timer(&can->bec_poll_timer);
1897 kvaser_pciefd_pwm_stop(can);1626 kvaser_pciefd_pwm_stop(can);
@@ -1906,10 +1635,8 @@ static void kvaser_pciefd_remove(struct pci_dev *pdev) · 8 unmodified lines
1906 1635
1907 kvaser_pciefd_remove_all_ctrls(pcie);1636 kvaser_pciefd_remove_all_ctrls(pcie);
1908 1637
1909 /* Turn off IRQ generation */1638 /* Disable interrupts */
1910 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);1639 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1911 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1912 pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1913 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);1640 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1914 1641
1915 free_irq(pcie->pci->irq, pcie);1642 free_irq(pcie->pci->irq, pcie);

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