Move driver-private definitions out of the i2c-pxa.h platform data header file into the driver itself. Nothing outside of the driver makes use of these constants.
Unified · Split
| @@ -85,6 +85,49 @@ · 84 unmodified lines | |||
| 85 | #define IWCR_HS_CNT2_SHIFT 10 | 85 | #define IWCR_HS_CNT2_SHIFT 10 |
| 86 | #define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT) | 86 | #define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT) |
| 87 | 87 | ||
| 88 | /* need a longer timeout if we're dealing with the fact we may well be | ||
| 89 | * looking at a multi-master environment | ||
| 90 | */ | ||
| 91 | #define DEF_TIMEOUT 32 | ||
| 92 | |||
| 93 | #define BUS_ERROR (-EREMOTEIO) | ||
| 94 | #define XFER_NAKED (-ECONNREFUSED) | ||
| 95 | #define I2C_RETRY (-2000) /* an error has occurred retry transmit */ | ||
| 96 | |||
| 97 | /* ICR initialize bit values | ||
| 98 | * | ||
| 99 | * 15 FM 0 (100 kHz operation) | ||
| 100 | * 14 UR 0 (No unit reset) | ||
| 101 | * 13 SADIE 0 (Disables the unit from interrupting on slave addresses | ||
| 102 | * matching its slave address) | ||
| 103 | * 12 ALDIE 0 (Disables the unit from interrupt when it loses arbitration | ||
| 104 | * in master mode) | ||
| 105 | * 11 SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode) | ||
| 106 | * 10 BEIE 1 (Enable interrupts from detected bus errors, no ACK sent) | ||
| 107 | * 9 IRFIE 1 (Enable interrupts from full buffer received) | ||
| 108 | * 8 ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty) | ||
| 109 | * 7 GCD 1 (Disables i2c unit response to general call messages as a slave) | ||
| 110 | * 6 IUE 0 (Disable unit until we change settings) | ||
| 111 | * 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL) | ||
| 112 | * 4 MA 0 (Only send stop with the ICR stop bit) | ||
| 113 | * 3 TB 0 (We are not transmitting a byte initially) | ||
| 114 | * 2 ACKNAK 0 (Send an ACK after the unit receives a byte) | ||
| 115 | * 1 STOP 0 (Do not send a STOP) | ||
| 116 | * 0 START 0 (Do not send a START) | ||
| 117 | */ | ||
| 118 | #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) | ||
| 119 | |||
| 120 | /* I2C status register init values | ||
| 121 | * | ||
| 122 | * 10 BED 1 (Clear bus error detected) | ||
| 123 | * 9 SAD 1 (Clear slave address detected) | ||
| 124 | * 7 IRF 1 (Clear IDBR Receive Full) | ||
| 125 | * 6 ITE 1 (Clear IDBR Transmit Empty) | ||
| 126 | * 5 ALD 1 (Clear Arbitration Loss Detected) | ||
| 127 | * 4 SSD 1 (Clear Slave Stop Detected) | ||
| 128 | */ | ||
| 129 | #define I2C_ISR_INIT 0x7FF /* status register init */ | ||
| 130 | |||
| 88 | struct pxa_reg_layout { | 131 | struct pxa_reg_layout { |
| 89 | u32 ibmr; | 132 | u32 ibmr; |
| 90 | u32 idbr; | 133 | u32 idbr; |
| @@ -7,54 +7,6 @@ · 6 unmodified lines | |||
| 7 | #ifndef _I2C_PXA_H_ | 7 | #ifndef _I2C_PXA_H_ |
| 8 | #define _I2C_PXA_H_ | 8 | #define _I2C_PXA_H_ |
| 9 | 9 | ||
| 10 | #if 0 | ||
| 11 | #define DEF_TIMEOUT 3 | ||
| 12 | #else | ||
| 13 | /* need a longer timeout if we're dealing with the fact we may well be | ||
| 14 | * looking at a multi-master environment | ||
| 15 | */ | ||
| 16 | #define DEF_TIMEOUT 32 | ||
| 17 | #endif | ||
| 18 | |||
| 19 | #define BUS_ERROR (-EREMOTEIO) | ||
| 20 | #define XFER_NAKED (-ECONNREFUSED) | ||
| 21 | #define I2C_RETRY (-2000) /* an error has occurred retry transmit */ | ||
| 22 | |||
| 23 | /* ICR initialize bit values | ||
| 24 | * | ||
| 25 | * 15. FM 0 (100 Khz operation) | ||
| 26 | * 14. UR 0 (No unit reset) | ||
| 27 | * 13. SADIE 0 (Disables the unit from interrupting on slave addresses | ||
| 28 | * matching its slave address) | ||
| 29 | * 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration | ||
| 30 | * in master mode) | ||
| 31 | * 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode) | ||
| 32 | * 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent) | ||
| 33 | * 9. IRFIE 1 (Enable interrupts from full buffer received) | ||
| 34 | * 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty) | ||
| 35 | * 7. GCD 1 (Disables i2c unit response to general call messages as a slave) | ||
| 36 | * 6. IUE 0 (Disable unit until we change settings) | ||
| 37 | * 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL) | ||
| 38 | * 4. MA 0 (Only send stop with the ICR stop bit) | ||
| 39 | * 3. TB 0 (We are not transmitting a byte initially) | ||
| 40 | * 2. ACKNAK 0 (Send an ACK after the unit receives a byte) | ||
| 41 | * 1. STOP 0 (Do not send a STOP) | ||
| 42 | * 0. START 0 (Do not send a START) | ||
| 43 | * | ||
| 44 | */ | ||
| 45 | #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) | ||
| 46 | |||
| 47 | /* I2C status register init values | ||
| 48 | * | ||
| 49 | * 10. BED 1 (Clear bus error detected) | ||
| 50 | * 9. SAD 1 (Clear slave address detected) | ||
| 51 | * 7. IRF 1 (Clear IDBR Receive Full) | ||
| 52 | * 6. ITE 1 (Clear IDBR Transmit Empty) | ||
| 53 | * 5. ALD 1 (Clear Arbitration Loss Detected) | ||
| 54 | * 4. SSD 1 (Clear Slave Stop Detected) | ||
| 55 | */ | ||
| 56 | #define I2C_ISR_INIT 0x7FF /* status register init */ | ||
| 57 | |||
| 58 | struct i2c_pxa_platform_data { | 10 | struct i2c_pxa_platform_data { |
| 59 | unsigned int class; | 11 | unsigned int class; |
| 60 | unsigned int use_pio :1; | 12 | unsigned int use_pio :1; |