Merge tag 'drm-misc-next-2021-10-06' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

drm-misc-next for v5.16: UAPI Changes: - Allow empty drm leases for creating separate GEM namespaces. Cross-subsystem Changes: - Slightly rework dma_buf_poll. - Add dma_resv_for_each_fence_unlocked to iterate, and use it inside the lockless dma-resv functions. Core Changes: - Allow devm_drm_of_get_bridge to build without CONFIG_OF for compile testing. - Add more DP2 headers. - fix CONFIG_FB dependency in fb_helper. - Add DRM_FORMAT_R8 to drm_format_info, and helpers for RGB332 and RGB888. - Fix crash on a 0 or invalid EDID. Driver Changes: - Apply and revert DRM_MODESET_LOCK_ALL_BEGIN. - Add mode_valid to ti-sn65dsi86 bridge. - Support multiple syncobjs in v3d. - Add R8, RGB332 and RGB888 pixel formats to GUD. - Use devm_add_action_or_reset in dw-hdmi-cec. Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Wed 06 Oct 2021 20:48:12 AEST # gpg: using RSA key B97BD6A80CAC4981091AE547FE558C72A67013C3 # gpg: Good signature from "Maarten Lankhorst <maarten.lankhorst@linux.intel.com>" [expired] # gpg: aka "Maarten Lankhorst <maarten@debian.org>" [expired] # gpg: aka "Maarten Lankhorst <maarten.lankhorst@canonical.com>" [expired] # gpg: Note: This key has expired! # Primary key fingerprint: B97B D6A8 0CAC 4981 091A E547 FE55 8C72 A670 13C3 From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2602f4e9-a8ac-83f8-6c2a-39fd9ca2e1ba@linux.intel.com

Dave Airlie committed 5 years ago

Commit 797d72c2 parents b1f8166 996260199 files · +3148 −1131Browse files

Showing the changes to include/uapi (4 of 99 files). Show all

Unified · Split

4 files

include/uapi/drm/drm_mode.h +2 −1
include/uapi/drm/v3d_drm.h +78 −0
include/uapi/drm/virtgpu_drm.h +27 −0
include/uapi/linux/virtio_gpu.h +15 −3

include/uapi/drm/drm_mode.h+2−1

  * Lease mode resources, creating another drm_master.
  *
  * The @object_ids array must reference at least one CRTC, one connector and
- * one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled.
+ * one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled. Alternatively,
+ * the lease can be completely empty.
  */
 struct drm_mode_create_lease {
 	/** @object_ids: Pointer to array of object ids (__u32) */

include/uapi/drm/v3d_drm.h+78−0

@@ -58,6 +58,67 @@ extern "C" { · 57 unmodified lines
58	struct drm_v3d_perfmon_get_values)	58	struct drm_v3d_perfmon_get_values)
59		59
60	#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01	60	#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
		61	#define DRM_V3D_SUBMIT_EXTENSION 0x02
		62
		63	/* struct drm_v3d_extension - ioctl extensions
		64	*
		65	* Linked-list of generic extensions where the id identify which struct is
		66	* pointed by ext_data. Therefore, DRM_V3D_EXT_ID_* is used on id to identify
		67	* the extension type.
		68	*/
		69	struct drm_v3d_extension {
		70	__u64 next;
		71	__u32 id;
		72	#define DRM_V3D_EXT_ID_MULTI_SYNC 0x01
		73	__u32 flags; /* mbz */
		74	};
		75
		76	/* struct drm_v3d_sem - wait/signal semaphore
		77	*
		78	* If binary semaphore, it only takes syncobj handle and ignores flags and
		79	* point fields. Point is defined for timeline syncobj feature.
		80	*/
		81	struct drm_v3d_sem {
		82	__u32 handle; /* syncobj */
		83	/* rsv below, for future uses */
		84	__u32 flags;
		85	__u64 point; /* for timeline sem support */
		86	__u64 mbz[2]; /* must be zero, rsv */
		87	};
		88
		89	/* Enum for each of the V3D queues. */
		90	enum v3d_queue {
		91	V3D_BIN,
		92	V3D_RENDER,
		93	V3D_TFU,
		94	V3D_CSD,
		95	V3D_CACHE_CLEAN,
		96	};
		97
		98	/**
		99	* struct drm_v3d_multi_sync - ioctl extension to add support multiples
		100	* syncobjs for commands submission.
		101	*
		102	* When an extension of DRM_V3D_EXT_ID_MULTI_SYNC id is defined, it points to
		103	* this extension to define wait and signal dependencies, instead of single
		104	* in/out sync entries on submitting commands. The field flags is used to
		105	* determine the stage to set wait dependencies.
		106	*/
		107	struct drm_v3d_multi_sync {
		108	struct drm_v3d_extension base;
		109	/* Array of wait and signal semaphores */
		110	__u64 in_syncs;
		111	__u64 out_syncs;
		112
		113	/* Number of entries */
		114	__u32 in_sync_count;
		115	__u32 out_sync_count;
		116
		117	/* set the stage (v3d_queue) to sync */
		118	__u32 wait_stage;
		119
		120	__u32 pad; /* mbz */
		121	};
61		122
62	/**	123	/**
63	* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D	124	* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
@@ -135,12 +196,16 @@ struct drm_v3d_submit_cl { · 71 unmodified lines
135	/* Number of BO handles passed in (size is that times 4). */	196	/* Number of BO handles passed in (size is that times 4). */
136	__u32 bo_handle_count;	197	__u32 bo_handle_count;
137		198
		199	/* DRM_V3D_SUBMIT_* properties */
138	__u32 flags;	200	__u32 flags;
139		201
140	/* ID of the perfmon to attach to this job. 0 means no perfmon. */	202	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
141	__u32 perfmon_id;	203	__u32 perfmon_id;
142		204
143	__u32 pad;	205	__u32 pad;
		206
		207	/* Pointer to an array of ioctl extensions*/
		208	__u64 extensions;
144	};	209	};
145		210
146	/**	211	/**
@@ -210,6 +275,7 @@ enum drm_v3d_param { · 63 unmodified lines
210	DRM_V3D_PARAM_SUPPORTS_CSD,	275	DRM_V3D_PARAM_SUPPORTS_CSD,
211	DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,	276	DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
212	DRM_V3D_PARAM_SUPPORTS_PERFMON,	277	DRM_V3D_PARAM_SUPPORTS_PERFMON,
		278	DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
213	};	279	};
214		280
215	struct drm_v3d_get_param {	281	struct drm_v3d_get_param {
@@ -248,6 +314,11 @@ struct drm_v3d_submit_tfu { · 32 unmodified lines
248	__u32 in_sync;	314	__u32 in_sync;
249	/* Sync object to signal when the TFU job is done. */	315	/* Sync object to signal when the TFU job is done. */
250	__u32 out_sync;	316	__u32 out_sync;
		317
		318	__u32 flags;
		319
		320	/* Pointer to an array of ioctl extensions*/
		321	__u64 extensions;
251	};	322	};
252		323
253	/* Submits a compute shader for dispatch. This job will block on any	324	/* Submits a compute shader for dispatch. This job will block on any
@@ -276,6 +347,13 @@ struct drm_v3d_submit_csd { · 22 unmodified lines
276		347
277	/* ID of the perfmon to attach to this job. 0 means no perfmon. */	348	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
278	__u32 perfmon_id;	349	__u32 perfmon_id;
		350
		351	/* Pointer to an array of ioctl extensions*/
		352	__u64 extensions;
		353
		354	__u32 flags;
		355
		356	__u32 pad;
279	};	357	};
280		358
281	enum {	359	enum {

include/uapi/drm/virtgpu_drm.h+27−0

 #define DRM_VIRTGPU_WAIT     0x08
 #define DRM_VIRTGPU_GET_CAPS  0x09
 #define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
+#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
 #define VIRTGPU_EXECBUF_FENCE_FD_IN	0x01
 #define VIRTGPU_EXECBUF_FENCE_FD_OUT	0x02
+#define VIRTGPU_EXECBUF_RING_IDX	0x04
 #define VIRTGPU_EXECBUF_FLAGS  (\
 		VIRTGPU_EXECBUF_FENCE_FD_IN |\
 		VIRTGPU_EXECBUF_FENCE_FD_OUT |\
+		VIRTGPU_EXECBUF_RING_IDX |\
 		0)
 struct drm_virtgpu_map {
 	__u64 bo_handles;
 	__u32 num_bo_handles;
 	__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
+	__u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
+	__u32 pad;
 };
 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
 #define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
 #define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
 #define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing  */
+#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
+#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
 struct drm_virtgpu_getparam {
 	__u64 param;
 	__u64 blob_id;
 };
+#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID       0x0001
+#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS       0x0002
+#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
+struct drm_virtgpu_context_set_param {
+	__u64 param;
+	__u64 value;
+};
+struct drm_virtgpu_context_init {
+	__u32 num_params;
+	__u32 pad;
+	/* pointer to drm_virtgpu_context_set_param array */
+	__u64 ctx_set_params;
+};
 #define DRM_IOCTL_VIRTGPU_MAP \
 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB,	\
 		struct drm_virtgpu_resource_create_blob)
+#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT					\
+	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT,		\
+		struct drm_virtgpu_context_init)
 #if defined(__cplusplus)
 }
 #endif

include/uapi/linux/virtio_gpu.h+15−3

  * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
  */
 #define VIRTIO_GPU_F_RESOURCE_BLOB       3
+/*
+ * VIRTIO_GPU_CMD_CREATE_CONTEXT with
+ * context_init and multiple timelines
+ */
+#define VIRTIO_GPU_F_CONTEXT_INIT        4
 enum virtio_gpu_ctrl_type {
 	VIRTIO_GPU_UNDEFINED = 0,
 	VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
 };
-#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
+#define VIRTIO_GPU_FLAG_FENCE         (1 << 0)
+/*
+ * If the following flag is set, then ring_idx contains the index
+ * of the command ring that needs to used when creating the fence
+ */
+#define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1)
 struct virtio_gpu_ctrl_hdr {
 	__le32 type;
 	__le32 flags;
 	__le64 fence_id;
 	__le32 ctx_id;
-	__le32 padding;
+	__u8 ring_idx;
+	__u8 padding[3];
 };
 /* data passed in the cursor vq */
 };
 /* VIRTIO_GPU_CMD_CTX_CREATE */
+#define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff
 struct virtio_gpu_ctx_create {
 	struct virtio_gpu_ctrl_hdr hdr;
 	__le32 nlen;
-	__le32 padding;
+	__le32 context_init;
 	char debug_name[64];
 };