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Merge tag 'drm-misc-next-2021-10-06' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

drm-misc-next for v5.16: UAPI Changes: - Allow empty drm leases for creating separate GEM namespaces. Cross-subsystem Changes: - Slightly rework dma_buf_poll. - Add dma_resv_for_each_fence_unlocked to iterate, and use it inside the lockless dma-resv functions. Core Changes: - Allow devm_drm_of_get_bridge to build without CONFIG_OF for compile testing. - Add more DP2 headers. - fix CONFIG_FB dependency in fb_helper. - Add DRM_FORMAT_R8 to drm_format_info, and helpers for RGB332 and RGB888. - Fix crash on a 0 or invalid EDID. Driver Changes: - Apply and revert DRM_MODESET_LOCK_ALL_BEGIN. - Add mode_valid to ti-sn65dsi86 bridge. - Support multiple syncobjs in v3d. - Add R8, RGB332 and RGB888 pixel formats to GUD. - Use devm_add_action_or_reset in dw-hdmi-cec. Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Wed 06 Oct 2021 20:48:12 AEST # gpg: using RSA key B97BD6A80CAC4981091AE547FE558C72A67013C3 # gpg: Good signature from "Maarten Lankhorst <maarten.lankhorst@linux.intel.com>" [expired] # gpg: aka "Maarten Lankhorst <maarten@debian.org>" [expired] # gpg: aka "Maarten Lankhorst <maarten.lankhorst@canonical.com>" [expired] # gpg: Note: This key has expired! # Primary key fingerprint: B97B D6A8 0CAC 4981 091A E547 FE55 8C72 A670 13C3 From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2602f4e9-a8ac-83f8-6c2a-39fd9ca2e1ba@linux.intel.com

Dave Airlie committed 5 years ago

Commit 797d72c2 parents b1f8166 996260199 files · +3148 −1131Browse files

Showing the changes to include/uapi (4 of 99 files). Show all

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4 files
  1. include/uapi/drm/drm_mode.h +2 −1
  2. include/uapi/drm/v3d_drm.h +78 −0
  3. include/uapi/drm/virtgpu_drm.h +27 −0
  4. include/uapi/linux/virtio_gpu.h +15 −3
include/uapi/drm/drm_mode.h+2−1
@@ -1112,7 +1112,8 @@ struct drm_mode_destroy_blob { · 1111 unmodified lines
11121112 * Lease mode resources, creating another drm_master.
11131113 *
11141114 * The @object_ids array must reference at least one CRTC, one connector and
1115− * one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled.
1115+ * one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled. Alternatively,
1116+ * the lease can be completely empty.
11161117 */
11171118 struct drm_mode_create_lease {
11181119 /** @object_ids: Pointer to array of object ids (__u32) */
include/uapi/drm/v3d_drm.h+78−0
@@ -58,6 +58,67 @@ extern "C" { · 57 unmodified lines
5858 struct drm_v3d_perfmon_get_values)
5959
6060 #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
61+#define DRM_V3D_SUBMIT_EXTENSION 0x02
62+
63+/* struct drm_v3d_extension - ioctl extensions
64+ *
65+ * Linked-list of generic extensions where the id identify which struct is
66+ * pointed by ext_data. Therefore, DRM_V3D_EXT_ID_* is used on id to identify
67+ * the extension type.
68+ */
69+struct drm_v3d_extension {
70+ __u64 next;
71+ __u32 id;
72+#define DRM_V3D_EXT_ID_MULTI_SYNC 0x01
73+ __u32 flags; /* mbz */
74+};
75+
76+/* struct drm_v3d_sem - wait/signal semaphore
77+ *
78+ * If binary semaphore, it only takes syncobj handle and ignores flags and
79+ * point fields. Point is defined for timeline syncobj feature.
80+ */
81+struct drm_v3d_sem {
82+ __u32 handle; /* syncobj */
83+ /* rsv below, for future uses */
84+ __u32 flags;
85+ __u64 point; /* for timeline sem support */
86+ __u64 mbz[2]; /* must be zero, rsv */
87+};
88+
89+/* Enum for each of the V3D queues. */
90+enum v3d_queue {
91+ V3D_BIN,
92+ V3D_RENDER,
93+ V3D_TFU,
94+ V3D_CSD,
95+ V3D_CACHE_CLEAN,
96+};
97+
98+/**
99+ * struct drm_v3d_multi_sync - ioctl extension to add support multiples
100+ * syncobjs for commands submission.
101+ *
102+ * When an extension of DRM_V3D_EXT_ID_MULTI_SYNC id is defined, it points to
103+ * this extension to define wait and signal dependencies, instead of single
104+ * in/out sync entries on submitting commands. The field flags is used to
105+ * determine the stage to set wait dependencies.
106+ */
107+struct drm_v3d_multi_sync {
108+ struct drm_v3d_extension base;
109+ /* Array of wait and signal semaphores */
110+ __u64 in_syncs;
111+ __u64 out_syncs;
112+
113+ /* Number of entries */
114+ __u32 in_sync_count;
115+ __u32 out_sync_count;
116+
117+ /* set the stage (v3d_queue) to sync */
118+ __u32 wait_stage;
119+
120+ __u32 pad; /* mbz */
121+};
61122
62123 /**
63124 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
@@ -135,12 +196,16 @@ struct drm_v3d_submit_cl { · 71 unmodified lines
135196 /* Number of BO handles passed in (size is that times 4). */
136197 __u32 bo_handle_count;
137198
199+ /* DRM_V3D_SUBMIT_* properties */
138200 __u32 flags;
139201
140202 /* ID of the perfmon to attach to this job. 0 means no perfmon. */
141203 __u32 perfmon_id;
142204
143205 __u32 pad;
206+
207+ /* Pointer to an array of ioctl extensions*/
208+ __u64 extensions;
144209 };
145210
146211 /**
@@ -210,6 +275,7 @@ enum drm_v3d_param { · 63 unmodified lines
210275 DRM_V3D_PARAM_SUPPORTS_CSD,
211276 DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
212277 DRM_V3D_PARAM_SUPPORTS_PERFMON,
278+ DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
213279 };
214280
215281 struct drm_v3d_get_param {
@@ -248,6 +314,11 @@ struct drm_v3d_submit_tfu { · 32 unmodified lines
248314 __u32 in_sync;
249315 /* Sync object to signal when the TFU job is done. */
250316 __u32 out_sync;
317+
318+ __u32 flags;
319+
320+ /* Pointer to an array of ioctl extensions*/
321+ __u64 extensions;
251322 };
252323
253324 /* Submits a compute shader for dispatch. This job will block on any
@@ -276,6 +347,13 @@ struct drm_v3d_submit_csd { · 22 unmodified lines
276347
277348 /* ID of the perfmon to attach to this job. 0 means no perfmon. */
278349 __u32 perfmon_id;
350+
351+ /* Pointer to an array of ioctl extensions*/
352+ __u64 extensions;
353+
354+ __u32 flags;
355+
356+ __u32 pad;
279357 };
280358
281359 enum {
include/uapi/drm/virtgpu_drm.h+27−0
@@ -47,12 +47,15 @@ extern "C" { · 46 unmodified lines
4747 #define DRM_VIRTGPU_WAIT 0x08
4848 #define DRM_VIRTGPU_GET_CAPS 0x09
4949 #define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
50+#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
5051
5152 #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
5253 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
54+#define VIRTGPU_EXECBUF_RING_IDX 0x04
5355 #define VIRTGPU_EXECBUF_FLAGS (\
5456 VIRTGPU_EXECBUF_FENCE_FD_IN |\
5557 VIRTGPU_EXECBUF_FENCE_FD_OUT |\
58+ VIRTGPU_EXECBUF_RING_IDX |\
5659 0)
5760
5861 struct drm_virtgpu_map {
@@ -68,6 +71,8 @@ struct drm_virtgpu_execbuffer { · 9 unmodified lines
6871 __u64 bo_handles;
6972 __u32 num_bo_handles;
7073 __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
74+ __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
75+ __u32 pad;
7176 };
7277
7378 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
@@ -75,6 +80,8 @@ struct drm_virtgpu_execbuffer { · 1 unmodified line
7580 #define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
7681 #define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
7782 #define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */
83+#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
84+#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
7885
7986 struct drm_virtgpu_getparam {
8087 __u64 param;
@@ -173,6 +180,22 @@ struct drm_virtgpu_resource_create_blob { · 92 unmodified lines
173180 __u64 blob_id;
174181 };
175182
183+#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
184+#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
185+#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
186+struct drm_virtgpu_context_set_param {
187+ __u64 param;
188+ __u64 value;
189+};
190+
191+struct drm_virtgpu_context_init {
192+ __u32 num_params;
193+ __u32 pad;
194+
195+ /* pointer to drm_virtgpu_context_set_param array */
196+ __u64 ctx_set_params;
197+};
198+
176199 #define DRM_IOCTL_VIRTGPU_MAP \
177200 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
178201
@@ -212,6 +235,10 @@ struct drm_virtgpu_resource_create_blob { · 33 unmodified lines
212235 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \
213236 struct drm_virtgpu_resource_create_blob)
214237
238+#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \
239+ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \
240+ struct drm_virtgpu_context_init)
241+
215242 #if defined(__cplusplus)
216243 }
217244 #endif
include/uapi/linux/virtio_gpu.h+15−3
@@ -59,6 +59,11 @@ · 58 unmodified lines
5959 * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
6060 */
6161 #define VIRTIO_GPU_F_RESOURCE_BLOB 3
62+/*
63+ * VIRTIO_GPU_CMD_CREATE_CONTEXT with
64+ * context_init and multiple timelines
65+ */
66+#define VIRTIO_GPU_F_CONTEXT_INIT 4
6267
6368 enum virtio_gpu_ctrl_type {
6469 VIRTIO_GPU_UNDEFINED = 0,
@@ -122,14 +127,20 @@ enum virtio_gpu_shm_id { · 57 unmodified lines
122127 VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
123128 };
124129
125−#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
130+#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
131+/*
132+ * If the following flag is set, then ring_idx contains the index
133+ * of the command ring that needs to used when creating the fence
134+ */
135+#define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1)
126136
127137 struct virtio_gpu_ctrl_hdr {
128138 __le32 type;
129139 __le32 flags;
130140 __le64 fence_id;
131141 __le32 ctx_id;
132− __le32 padding;
142+ __u8 ring_idx;
143+ __u8 padding[3];
133144 };
134145
135146 /* data passed in the cursor vq */
@@ -269,10 +280,11 @@ struct virtio_gpu_resource_create_3d { · 133 unmodified lines
269280 };
270281
271282 /* VIRTIO_GPU_CMD_CTX_CREATE */
283+#define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff
272284 struct virtio_gpu_ctx_create {
273285 struct virtio_gpu_ctrl_hdr hdr;
274286 __le32 nlen;
275− __le32 padding;
287+ __le32 context_init;
276288 char debug_name[64];
277289 };
278290