lael-labs/linux

CREDITS+5−0

@@ -918,6 +918,11 @@ S: Ottawa, Ontario · 917 unmodified lines
918	S: K1N 6Z9	918	S: K1N 6Z9
919	S: CANADA	919	S: CANADA
920		920
		921	N: Vivien Didelot
		922	E: vivien.didelot@gmail.com
		923	D: DSA framework and MV88E6XXX driver
		924	S: Montreal, Quebec, Canada
		925
921	N: Jeff Dike	926	N: Jeff Dike
922	E: jdike@karaya.com	927	E: jdike@karaya.com
923	W: http://user-mode-linux.sourceforge.net	928	W: http://user-mode-linux.sourceforge.net

Documentation/dev-tools/kmsan.rst+1−0

@@ -67,6 +67,7 @@ uninitialized in the local variable, as well as the stack where the value was · 66 unmodified lines
67	copied to another memory location before use.	67	copied to another memory location before use.
68		68
69	A use of uninitialized value ``v`` is reported by KMSAN in the following cases:	69	A use of uninitialized value ``v`` is reported by KMSAN in the following cases:
		70
70	- in a condition, e.g. ``if (v) { ... }``;	71	- in a condition, e.g. ``if (v) { ... }``;
71	- in an indexing or pointer dereferencing, e.g. ``array[v]`` or ``*v``;	72	- in an indexing or pointer dereferencing, e.g. ``array[v]`` or ``*v``;
72	- when it is copied to userspace or hardware, e.g. ``copy_to_user(..., &v, ...)``;	73	- when it is copied to userspace or hardware, e.g. ``copy_to_user(..., &v, ...)``;

Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml+21−8

 properties:
   compatible:
-    enum:
+    oneOf:
-      - qcom,sfpb-mutex
+      - enum:
-      - qcom,tcsr-mutex
+          - qcom,sfpb-mutex
+          - qcom,tcsr-mutex
+      - items:
+          - enum:
+              - qcom,apq8084-tcsr-mutex
+              - qcom,ipq6018-tcsr-mutex
+              - qcom,msm8226-tcsr-mutex
+              - qcom,msm8994-tcsr-mutex
+          - const: qcom,tcsr-mutex
+      - items:
+          - enum:
+              - qcom,msm8974-tcsr-mutex
+          - const: qcom,tcsr-mutex
+          - const: syscon
   reg:
     maxItems: 1
 examples:
   - |
-        tcsr_mutex: hwlock@1f40000 {
+    hwlock@1f40000 {
-                compatible = "qcom,tcsr-mutex";
+        compatible = "qcom,tcsr-mutex";
-                reg = <0x01f40000 0x40000>;
+        reg = <0x01f40000 0x40000>;
-                #hwlock-cells = <1>;
+        #hwlock-cells = <1>;
-        };
+    };
 ...

Documentation/devicetree/bindings/net/engleder,tsnep.yaml+1−1

@@ -47,7 +47,7 @@ properties: · 46 unmodified lines
47		47
48	nvmem-cells: true	48	nvmem-cells: true
49		49
50	nvmem-cells-names: true	50	nvmem-cell-names: true
51		51
52	phy-connection-type:	52	phy-connection-type:
53	enum:	53	enum:

Documentation/virt/kvm/devices/vm.rst+3−0

 :Parameters: address of a buffer in user space to store the data (u8) to
 :Returns:   -EFAULT if the given address is not accessible from kernel space;
 	    -EINVAL if setting the TOD clock extension to != 0 is not supported
+	    -EOPNOTSUPP for a PV guest (TOD managed by the ultravisor)
 3.2. ATTRIBUTE: KVM_S390_VM_TOD_LOW
 -----------------------------------
 :Parameters: address of a buffer in user space to store the data (u64) to
 :Returns:    -EFAULT if the given address is not accessible from kernel space
+	     -EOPNOTSUPP for a PV guest (TOD managed by the ultravisor)
 3.3. ATTRIBUTE: KVM_S390_VM_TOD_EXT
 -----------------------------------
 	     (kvm_s390_vm_tod_clock) to
 :Returns:   -EFAULT if the given address is not accessible from kernel space;
 	    -EINVAL if setting the TOD clock extension to != 0 is not supported
+	    -EOPNOTSUPP for a PV guest (TOD managed by the ultravisor)
 4. GROUP: KVM_S390_VM_CRYPTO
 ============================

MAINTAINERS+2−5

 F:	include/uapi/asm-generic/
 GENERIC PHY FRAMEWORK
-M:	Kishon Vijay Abraham I <kishon@ti.com>
 M:	Vinod Koul <vkoul@kernel.org>
+M:	Kishon Vijay Abraham I <kishon@kernel.org>
 L:	linux-phy@lists.infradead.org
 S:	Supported
 Q:	https://patchwork.kernel.org/project/linux-phy/list/
 F:	drivers/crypto/hisilicon/trng/trng.c
 HISILICON V3XX SPI NOR FLASH Controller Driver
-M:	John Garry <john.garry@huawei.com>
+M:	Jay Fang <f.fangjian@huawei.com>
 S:	Maintained
 W:	http://www.hisilicon.com
 F:	drivers/spi/spi-hisi-sfc-v3xx.c
 Hyper-V/Azure CORE AND DRIVERS
 M:	"K. Y. Srinivasan" <kys@microsoft.com>
 M:	Haiyang Zhang <haiyangz@microsoft.com>
-M:	Stephen Hemminger <sthemmin@microsoft.com>
 M:	Wei Liu <wei.liu@kernel.org>
 M:	Dexuan Cui <decui@microsoft.com>
 L:	linux-hyperv@vger.kernel.org
 MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER
 M:	Andrew Lunn <andrew@lunn.ch>
-M:	Vivien Didelot <vivien.didelot@gmail.com>
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	Documentation/devicetree/bindings/net/dsa/marvell.txt
 NETWORKING [DSA]
 M:	Andrew Lunn <andrew@lunn.ch>
-M:	Vivien Didelot <vivien.didelot@gmail.com>
 M:	Florian Fainelli <f.fainelli@gmail.com>
 M:	Vladimir Oltean <olteanv@gmail.com>
 S:	Maintained

Makefile+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	VERSION = 6	2	VERSION = 6
3	PATCHLEVEL = 1	3	PATCHLEVEL = 1
4	SUBLEVEL = 0	4	SUBLEVEL = 0
5	EXTRAVERSION = -rc4	5	EXTRAVERSION = -rc5
6	NAME = Hurr durr I'ma ninja sloth	6	NAME = Hurr durr I'ma ninja sloth
7		7
8	# DOCUMENTATION	8	# DOCUMENTATION

arch/arm64/include/asm/cputype.h+1−1

@@ -41,7 +41,7 @@ · 40 unmodified lines
41	(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)	41	(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
42		42
43	#define MIDR_CPU_MODEL(imp, partnum) \	43	#define MIDR_CPU_MODEL(imp, partnum) \
44	(((imp) << MIDR_IMPLEMENTOR_SHIFT) \| \	44	((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) \| \
45	(0xf << MIDR_ARCHITECTURE_SHIFT) \| \	45	(0xf << MIDR_ARCHITECTURE_SHIFT) \| \
46	((partnum) << MIDR_PARTNUM_SHIFT))	46	((partnum) << MIDR_PARTNUM_SHIFT))
47		47

arch/arm64/include/asm/syscall_wrapper.h+1−1

@@ -8,7 +8,7 @@ · 7 unmodified lines
8	#ifndef __ASM_SYSCALL_WRAPPER_H	8	#ifndef __ASM_SYSCALL_WRAPPER_H
9	#define __ASM_SYSCALL_WRAPPER_H	9	#define __ASM_SYSCALL_WRAPPER_H
10		10
11	struct pt_regs;	11	#include <asm/ptrace.h>
12		12
13	#define SC_ARM64_REGS_TO_ARGS(x, ...) \	13	#define SC_ARM64_REGS_TO_ARGS(x, ...) \
14	__MAP(x,__SC_ARGS \	14	__MAP(x,__SC_ARGS \

arch/arm64/kernel/efi.c+34−18

 #include <asm/efi.h>
+static bool region_is_misaligned(const efi_memory_desc_t *md)
+{
+	if (PAGE_SIZE == EFI_PAGE_SIZE)
+		return false;
+	return !PAGE_ALIGNED(md->phys_addr) ||
+	       !PAGE_ALIGNED(md->num_pages << EFI_PAGE_SHIFT);
+}
 /*
  * Only regions of type EFI_RUNTIME_SERVICES_CODE need to be
  * executable, everything else can be mapped with the XN bits
 	if (type == EFI_MEMORY_MAPPED_IO)
 		return PROT_DEVICE_nGnRE;
-	if (WARN_ONCE(!PAGE_ALIGNED(md->phys_addr),
+	if (region_is_misaligned(md)) {
-		      "UEFI Runtime regions are not aligned to 64 KB -- buggy firmware?"))
+		static bool __initdata code_is_misaligned;
 		/*
-		 * If the region is not aligned to the page size of the OS, we
+		 * Regions that are not aligned to the OS page size cannot be
-		 * can not use strict permissions, since that would also affect
+		 * mapped with strict permissions, as those might interfere
-		 * the mapping attributes of the adjacent regions.
+		 * with the permissions that are needed by the adjacent
+		 * region's mapping. However, if we haven't encountered any
+		 * misaligned runtime code regions so far, we can safely use
+		 * non-executable permissions for non-code regions.
 		 */
-		return pgprot_val(PAGE_KERNEL_EXEC);
+		code_is_misaligned |= (type == EFI_RUNTIME_SERVICES_CODE);
+		return code_is_misaligned ? pgprot_val(PAGE_KERNEL_EXEC)
+					  : pgprot_val(PAGE_KERNEL);
+	}
 	/* R-- */
 	if ((attr & (EFI_MEMORY_XP | EFI_MEMORY_RO)) ==
 	bool page_mappings_only = (md->type == EFI_RUNTIME_SERVICES_CODE ||
 				   md->type == EFI_RUNTIME_SERVICES_DATA);
-	if (!PAGE_ALIGNED(md->phys_addr) ||
+	/*
-	    !PAGE_ALIGNED(md->num_pages << EFI_PAGE_SHIFT)) {
+	 * If this region is not aligned to the page size used by the OS, the
-		/*
+	 * mapping will be rounded outwards, and may end up sharing a page
-		 * If the end address of this region is not aligned to page
+	 * frame with an adjacent runtime memory region. Given that the page
-		 * size, the mapping is rounded up, and may end up sharing a
+	 * table descriptor covering the shared page will be rewritten when the
-		 * page frame with the next UEFI memory region. If we create
+	 * adjacent region gets mapped, we must avoid block mappings here so we
-		 * a block entry now, we may need to split it again when mapping
+	 * don't have to worry about splitting them when that happens.
-		 * the next region, and support for that is going to be removed
+	 */
-		 * from the MMU routines. So avoid block mappings altogether in
+	if (region_is_misaligned(md))
-		 * that case.
-		 */
 		page_mappings_only = true;
-	}
 	create_pgd_mapping(mm, md->phys_addr, md->virt_addr,
 			   md->num_pages << EFI_PAGE_SHIFT,
 	BUG_ON(md->type != EFI_RUNTIME_SERVICES_CODE &&
 	       md->type != EFI_RUNTIME_SERVICES_DATA);
+	if (region_is_misaligned(md))
+		return 0;
 	/*
 	 * Calling apply_to_page_range() is only safe on regions that are
 	 * guaranteed to be mapped down to pages. Since we are only called

arch/arm64/mm/pageattr.c+3−2

 	 * mapped at page granularity, so that it is possible to
 	 * protect/unprotect single pages.
 	 */
-	return rodata_full || debug_pagealloc_enabled() ||
+	return (rodata_enabled && rodata_full) || debug_pagealloc_enabled() ||
 		IS_ENABLED(CONFIG_KFENCE);
 }
 	 * If we are manipulating read-only permissions, apply the same
 	 * change to the linear mapping of the pages that back this VM area.
 	 */
-	if (rodata_full && (pgprot_val(set_mask) == PTE_RDONLY ||
+	if (rodata_enabled &&
+	    rodata_full && (pgprot_val(set_mask) == PTE_RDONLY ||
 			    pgprot_val(clear_mask) == PTE_RDONLY)) {
 		for (i = 0; i < area->nr_pages; i++) {
 			__change_memory_common((u64)page_address(area->pages[i]),

arch/mips/alchemy/common/gpiolib.c+1−1

@@ -31,7 +31,7 @@ · 30 unmodified lines
31	#include <linux/init.h>	31	#include <linux/init.h>
32	#include <linux/kernel.h>	32	#include <linux/kernel.h>
33	#include <linux/types.h>	33	#include <linux/types.h>
34	#include <linux/gpio.h>	34	#include <linux/gpio/driver.h>
35	#include <asm/mach-au1x00/gpio-au1000.h>	35	#include <asm/mach-au1x00/gpio-au1000.h>
36	#include <asm/mach-au1x00/gpio-au1300.h>	36	#include <asm/mach-au1x00/gpio-au1300.h>
37		37

arch/mips/boot/compressed/decompress.c+1−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9		9
10	#define DISABLE_BRANCH_PROFILING	10	#define DISABLE_BRANCH_PROFILING
11		11
		12	#define __NO_FORTIFY
12	#include <linux/types.h>	13	#include <linux/types.h>
13	#include <linux/kernel.h>	14	#include <linux/kernel.h>
14	#include <linux/string.h>	15	#include <linux/string.h>

arch/mips/include/asm/fw/fw.h+1−1

@@ -26,6 +26,6 @@ extern char *fw_getcmdline(void); · 25 unmodified lines
26	extern void fw_meminit(void);	26	extern void fw_meminit(void);
27	extern char fw_getenv(char name);	27	extern char fw_getenv(char name);
28	extern unsigned long fw_getenvl(char *name);	28	extern unsigned long fw_getenvl(char *name);
29	extern void fw_init_early_console(char port);	29	extern void fw_init_early_console(void);
30		30
31	#endif /* __ASM_FW_H_ */	31	#endif /* __ASM_FW_H_ */

arch/mips/kernel/jump_label.c+1−1

@@ -56,7 +56,7 @@ void arch_jump_label_transform(struct jump_entry *e, · 55 unmodified lines
56	* The branch offset must fit in the instruction's 26	56	* The branch offset must fit in the instruction's 26
57	* bit field.	57	* bit field.
58	*/	58	*/
59	WARN_ON((offset >= BIT(25)) \|\|	59	WARN_ON((offset >= (long)BIT(25)) \|\|
60	(offset < -(long)BIT(25)));	60	(offset < -(long)BIT(25)));
61		61
62	insn.j_format.opcode = bc6_op;	62	insn.j_format.opcode = bc6_op;

arch/mips/kernel/relocate_kernel.S+5−10

  * kexec_args[0..3] are used to prepare register values.
  */
-kexec_args:
+EXPORT(kexec_args)
-	EXPORT(kexec_args)
 arg0:	PTR_WD		0x0
 arg1:	PTR_WD		0x0
 arg2:	PTR_WD		0x0
  * their registers a0-a3. secondary_kexec_args[0..3] are used
  * to prepare register values.
  */
-secondary_kexec_args:
+EXPORT(secondary_kexec_args)
-	EXPORT(secondary_kexec_args)
 s_arg0: PTR_WD		0x0
 s_arg1: PTR_WD		0x0
 s_arg2: PTR_WD		0x0
 #endif
-kexec_start_address:
+EXPORT(kexec_start_address)
-	EXPORT(kexec_start_address)
 	PTR_WD		0x0
 	.size		kexec_start_address, PTRSIZE
-kexec_indirection_page:
+EXPORT(kexec_indirection_page)
-	EXPORT(kexec_indirection_page)
 	PTR_WD		0
 	.size		kexec_indirection_page, PTRSIZE
 relocate_new_kernel_end:
-relocate_new_kernel_size:
+EXPORT(relocate_new_kernel_size)
-	EXPORT(relocate_new_kernel_size)
 	PTR_WD		relocate_new_kernel_end - relocate_new_kernel
 	.size		relocate_new_kernel_size, PTRSIZE

arch/mips/loongson64/reset.c+10−0

 #include <asm/bootinfo.h>
 #include <asm/idle.h>
 #include <asm/reboot.h>
+#include <asm/bug.h>
 #include <loongson.h>
 #include <boot_param.h>
 #ifdef CONFIG_KEXEC
 	kexec_argv = kmalloc(KEXEC_ARGV_SIZE, GFP_KERNEL);
+	if (WARN_ON(!kexec_argv))
+		return -ENOMEM;
 	kdump_argv = kmalloc(KEXEC_ARGV_SIZE, GFP_KERNEL);
+	if (WARN_ON(!kdump_argv))
+		return -ENOMEM;
 	kexec_envp = kmalloc(KEXEC_ENVP_SIZE, GFP_KERNEL);
+	if (WARN_ON(!kexec_envp))
+		return -ENOMEM;
 	fw_arg1 = KEXEC_ARGV_ADDR;
 	memcpy(kexec_envp, (void *)fw_arg2, KEXEC_ENVP_SIZE);

arch/mips/pic32/pic32mzda/early_console.c+6−7

 #define U_BRG(x)	(UART_BASE(x) + 0x40)
 static void __iomem *uart_base;
-static char console_port = -1;
+static int console_port = -1;
 static int __init configure_uart_pins(int port)
 {
 	return 0;
 }
-static void __init configure_uart(char port, int baud)
+static void __init configure_uart(int port, int baud)
 {
 	u32 pbclk;
 		     uart_base + PIC32_SET(U_STA(port)));
 }
-static void __init setup_early_console(char port, int baud)
+static void __init setup_early_console(int port, int baud)
 {
 	if (configure_uart_pins(port))
 		return;
 	return baud;
 }
-void __init fw_init_early_console(char port)
+void __init fw_init_early_console(void)
 {
 	char *arch_cmdline = pic32_getcmdline();
-	int baud = -1;
+	int baud, port;
 	uart_base = ioremap(PIC32_BASE_UART, 0xc00);
 	baud = get_baud_from_cmdline(arch_cmdline);
-	if (port == -1)
+	port = get_port_from_cmdline(arch_cmdline);
-		port = get_port_from_cmdline(arch_cmdline);
 	if (port == -1)
 		port = EARLY_CONSOLE_PORT;

arch/mips/pic32/pic32mzda/init.c+1−1

@@ -47,7 +47,7 @@ void __init plat_mem_setup(void) · 46 unmodified lines
47	strscpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);	47	strscpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
48		48
49	#ifdef CONFIG_EARLY_PRINTK	49	#ifdef CONFIG_EARLY_PRINTK
50	fw_init_early_console(-1);	50	fw_init_early_console();
51	#endif	51	#endif
52	pic32_config_init();	52	pic32_config_init();
53	}	53	}

arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts+38−0

@@ -3,6 +3,8 @@ · 2 unmodified lines
3		3
4	#include "fu540-c000.dtsi"	4	#include "fu540-c000.dtsi"
5	#include <dt-bindings/gpio/gpio.h>	5	#include <dt-bindings/gpio/gpio.h>
		6	#include <dt-bindings/leds/common.h>
		7	#include <dt-bindings/pwm/pwm.h>
6		8
7	/* Clock frequency (in Hz) of the PCB crystal for rtcclk */	9	/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
8	#define RTCCLK_FREQ 1000000	10	#define RTCCLK_FREQ 1000000
@@ -42,6 +44,42 @@ · 33 unmodified lines
42	compatible = "gpio-restart";	44	compatible = "gpio-restart";
43	gpios = <&gpio 10 GPIO_ACTIVE_LOW>;	45	gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
44	};	46	};
		47
		48	led-controller {
		49	compatible = "pwm-leds";
		50
		51	led-d1 {
		52	pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>;
		53	active-low;
		54	color = <LED_COLOR_ID_GREEN>;
		55	max-brightness = <255>;
		56	label = "d1";
		57	};
		58
		59	led-d2 {
		60	pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>;
		61	active-low;
		62	color = <LED_COLOR_ID_GREEN>;
		63	max-brightness = <255>;
		64	label = "d2";
		65	};
		66
		67	led-d3 {
		68	pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>;
		69	active-low;
		70	color = <LED_COLOR_ID_GREEN>;
		71	max-brightness = <255>;
		72	label = "d3";
		73	};
		74
		75	led-d4 {
		76	pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>;
		77	active-low;
		78	color = <LED_COLOR_ID_GREEN>;
		79	max-brightness = <255>;
		80	label = "d4";
		81	};
		82	};
45	};	83	};
46		84
47	&uart0 {	85	&uart0 {

arch/riscv/kernel/process.c+2−0

@@ -164,6 +164,8 @@ int copy_thread(struct task_struct p, const struct kernel_clone_args args) · 163 unmodified lines
164	unsigned long tls = args->tls;	164	unsigned long tls = args->tls;
165	struct pt_regs *childregs = task_pt_regs(p);	165	struct pt_regs *childregs = task_pt_regs(p);
166		166
		167	memset(&p->thread.s, 0, sizeof(p->thread.s));
		168
167	/* p->thread holds context to be restored by __switch_to() */	169	/* p->thread holds context to be restored by __switch_to() */
168	if (unlikely(args->fn)) {	170	if (unlikely(args->fn)) {
169	/* Kernel thread */	171	/* Kernel thread */

arch/riscv/kernel/setup.c+1−0

@@ -283,6 +283,7 @@ void __init setup_arch(char **cmdline_p) · 282 unmodified lines
283	else	283	else
284	pr_err("No DTB found in kernel mappings\n");	284	pr_err("No DTB found in kernel mappings\n");
285	#endif	285	#endif
		286	early_init_fdt_scan_reserved_mem();
286	misc_mem_init();	287	misc_mem_init();
287		288
288	init_resources();	289	init_resources();

arch/riscv/kernel/vdso/Makefile+4−1

 obj-y += vdso.o
 CPPFLAGS_vdso.lds += -P -C -U$(ARCH)
+ifneq ($(filter vgettimeofday, $(vdso-syms)),)
+CPPFLAGS_vdso.lds += -DHAS_VGETTIMEOFDAY
+endif
 # Disable -pg to prevent insert call site
-CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE) -Os
+CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE)
 # Disable profiling and instrumentation for VDSO code
 GCOV_PROFILE := n

arch/riscv/kernel/vdso/vdso.lds.S+2−0

 	LINUX_4.15 {
 	global:
 		__vdso_rt_sigreturn;
+#ifdef HAS_VGETTIMEOFDAY
 		__vdso_gettimeofday;
 		__vdso_clock_gettime;
 		__vdso_clock_getres;
+#endif
 		__vdso_getcpu;
 		__vdso_flush_icache;
 	local: *;

arch/riscv/mm/init.c+0−1

@@ -262,7 +262,6 @@ static void __init setup_bootmem(void) · 261 unmodified lines
262	memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va));	262	memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va));
263	}	263	}
264		264
265	early_init_fdt_scan_reserved_mem();
266	dma_contiguous_reserve(dma32_phys_limit);	265	dma_contiguous_reserve(dma32_phys_limit);
267	if (IS_ENABLED(CONFIG_64BIT))	266	if (IS_ENABLED(CONFIG_64BIT))
268	hugetlb_cma_reserve(PUD_SHIFT - PAGE_SHIFT);	267	hugetlb_cma_reserve(PUD_SHIFT - PAGE_SHIFT);

arch/s390/Kconfig+3−3

 endchoice
 config RELOCATABLE
-	bool "Build a relocatable kernel"
+	def_bool y
-	default y
 	help
 	  This builds a kernel image that retains relocation information
 	  so it can be loaded at an arbitrary address.
 	  bootup process.
 	  The relocations make the kernel image about 15% larger (compressed
 	  10%), but are discarded at runtime.
+	  Note: this option exists only for documentation purposes, please do
+	  not remove it.
 config RANDOMIZE_BASE
 	bool "Randomize the address of the kernel image (KASLR)"
-	depends on RELOCATABLE
 	default y
 	help
 	  In support of Kernel Address Space Layout Randomization (KASLR),

arch/s390/Makefile+0−2

 KBUILD_CFLAGS_MODULE += -fPIC
 KBUILD_AFLAGS	+= -m64
 KBUILD_CFLAGS	+= -m64
-ifeq ($(CONFIG_RELOCATABLE),y)
 KBUILD_CFLAGS	+= -fPIE
 LDFLAGS_vmlinux	:= -pie
-endif
 aflags_dwarf	:= -Wa,-gdwarf-2
 KBUILD_AFLAGS_DECOMPRESSOR := $(CLANG_FLAGS) -m64 -D__ASSEMBLY__
 ifndef CONFIG_AS_IS_LLVM

arch/s390/boot/Makefile+1−2

 obj-y	:= head.o als.o startup.o mem_detect.o ipl_parm.o ipl_report.o
 obj-y	+= string.o ebcdic.o sclp_early_core.o mem.o ipl_vmparm.o cmdline.o
-obj-y	+= version.o pgm_check_info.o ctype.o ipl_data.o
+obj-y	+= version.o pgm_check_info.o ctype.o ipl_data.o machine_kexec_reloc.o
 obj-$(findstring y, $(CONFIG_PROTECTED_VIRTUALIZATION_GUEST) $(CONFIG_PGSTE))	+= uv.o
-obj-$(CONFIG_RELOCATABLE)	+= machine_kexec_reloc.o
 obj-$(CONFIG_RANDOMIZE_BASE)	+= kaslr.o
 obj-y	+= $(if $(CONFIG_KERNEL_UNCOMPRESSED),,decompressor.o) info.o
 obj-$(CONFIG_KERNEL_ZSTD) += clz_ctz.o

arch/s390/boot/startup.c+1−2

@@ -291,8 +291,7 @@ void startup_kernel(void) · 290 unmodified lines
291		291
292	clear_bss_section();	292	clear_bss_section();
293	copy_bootdata();	293	copy_bootdata();
294	if (IS_ENABLED(CONFIG_RELOCATABLE))	294	handle_relocs(__kaslr_offset);
295	handle_relocs(__kaslr_offset);
296		295
297	if (__kaslr_offset) {	296	if (__kaslr_offset) {
298	/*	297	/*

arch/s390/configs/btf.config+1−0

@@ -0,0 +1 @@
		1	CONFIG_DEBUG_INFO_BTF=y

arch/s390/configs/debug_defconfig+32−33

 CONFIG_CRYPTO_ECRDSA=m
 CONFIG_CRYPTO_SM2=m
 CONFIG_CRYPTO_CURVE25519=m
-CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_KEYWRAP=m
-CONFIG_CRYPTO_ADIANTUM=m
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-CONFIG_CRYPTO_CRC32=m
-CONFIG_CRYPTO_CRC32_S390=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_SHA512_S390=m
-CONFIG_CRYPTO_SHA1_S390=m
-CONFIG_CRYPTO_SHA256_S390=m
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SHA3_256_S390=m
-CONFIG_CRYPTO_SHA3_512_S390=m
-CONFIG_CRYPTO_SM3_GENERIC=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_GHASH_S390=m
 CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_AES_S390=m
 CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_ARIA=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_CAST5=m
 CONFIG_CRYPTO_CAST6=m
 CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_DES_S390=m
 CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_CHACHA_S390=m
 CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_ARIA=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_SM4_GENERIC=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_ADIANTUM=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_CFB=m
+CONFIG_CRYPTO_HCTR2=m
+CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_AEGIS128=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_SHA3=m
+CONFIG_CRYPTO_SM3_GENERIC=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_CRC32=m
 CONFIG_CRYPTO_842=m
 CONFIG_CRYPTO_LZ4=m
 CONFIG_CRYPTO_LZ4HC=m
 CONFIG_CRYPTO_USER_API_RNG=m
 CONFIG_CRYPTO_USER_API_AEAD=m
 CONFIG_CRYPTO_STATS=y
+CONFIG_CRYPTO_CRC32_S390=y
+CONFIG_CRYPTO_SHA512_S390=m
+CONFIG_CRYPTO_SHA1_S390=m
+CONFIG_CRYPTO_SHA256_S390=m
+CONFIG_CRYPTO_SHA3_256_S390=m
+CONFIG_CRYPTO_SHA3_512_S390=m
+CONFIG_CRYPTO_GHASH_S390=m
+CONFIG_CRYPTO_AES_S390=m
+CONFIG_CRYPTO_DES_S390=m
+CONFIG_CRYPTO_CHACHA_S390=m
 CONFIG_ZCRYPT=m
 CONFIG_PKEY=m
 CONFIG_CRYPTO_PAES_S390=m
 CONFIG_PRINTK_TIME=y
 CONFIG_DYNAMIC_DEBUG=y
 CONFIG_DEBUG_INFO_DWARF4=y
-CONFIG_DEBUG_INFO_BTF=y
 CONFIG_GDB_SCRIPTS=y
 CONFIG_HEADERS_INSTALL=y
 CONFIG_DEBUG_SECTION_MISMATCH=y

arch/s390/configs/defconfig+33−34

 CONFIG_CRYPTO_ECRDSA=m
 CONFIG_CRYPTO_SM2=m
 CONFIG_CRYPTO_CURVE25519=m
-CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_OFB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_KEYWRAP=m
-CONFIG_CRYPTO_ADIANTUM=m
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-CONFIG_CRYPTO_CRC32=m
-CONFIG_CRYPTO_CRC32_S390=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_SHA512_S390=m
-CONFIG_CRYPTO_SHA1_S390=m
-CONFIG_CRYPTO_SHA256_S390=m
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SHA3_256_S390=m
-CONFIG_CRYPTO_SHA3_512_S390=m
-CONFIG_CRYPTO_SM3_GENERIC=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_GHASH_S390=m
 CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_AES_S390=m
 CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_ARIA=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_CAST5=m
 CONFIG_CRYPTO_CAST6=m
 CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_DES_S390=m
 CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_CHACHA_S390=m
 CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_ARIA=m
 CONFIG_CRYPTO_SERPENT=m
 CONFIG_CRYPTO_SM4_GENERIC=m
 CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_ADIANTUM=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_CFB=m
+CONFIG_CRYPTO_HCTR2=m
+CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_OFB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_AEGIS128=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_SHA3=m
+CONFIG_CRYPTO_SM3_GENERIC=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_CRC32=m
 CONFIG_CRYPTO_842=m
 CONFIG_CRYPTO_LZ4=m
 CONFIG_CRYPTO_LZ4HC=m
 CONFIG_CRYPTO_USER_API_RNG=m
 CONFIG_CRYPTO_USER_API_AEAD=m
 CONFIG_CRYPTO_STATS=y
+CONFIG_CRYPTO_CRC32_S390=y
+CONFIG_CRYPTO_SHA512_S390=m
+CONFIG_CRYPTO_SHA1_S390=m
+CONFIG_CRYPTO_SHA256_S390=m
+CONFIG_CRYPTO_SHA3_256_S390=m
+CONFIG_CRYPTO_SHA3_512_S390=m
+CONFIG_CRYPTO_GHASH_S390=m
+CONFIG_CRYPTO_AES_S390=m
+CONFIG_CRYPTO_DES_S390=m
+CONFIG_CRYPTO_CHACHA_S390=m
 CONFIG_ZCRYPT=m
 CONFIG_PKEY=m
 CONFIG_CRYPTO_PAES_S390=m
 CONFIG_PRINTK_TIME=y
 CONFIG_DYNAMIC_DEBUG=y
 CONFIG_DEBUG_INFO_DWARF4=y
-CONFIG_DEBUG_INFO_BTF=y
 CONFIG_GDB_SCRIPTS=y
 CONFIG_DEBUG_SECTION_MISMATCH=y
 CONFIG_MAGIC_SYSRQ=y

arch/s390/configs/kasan.config+3−0

@@ -0,0 +1,3 @@
	1	CONFIG_KASAN=y
	2	CONFIG_KASAN_INLINE=y
	3	CONFIG_KASAN_VMALLOC=y

arch/s390/configs/zfcpdump_defconfig+0−1

@@ -74,7 +74,6 @@ CONFIG_PRINTK_TIME=y · 73 unmodified lines
74	# CONFIG_SYMBOLIC_ERRNAME is not set	74	# CONFIG_SYMBOLIC_ERRNAME is not set
75	CONFIG_DEBUG_KERNEL=y	75	CONFIG_DEBUG_KERNEL=y
76	CONFIG_DEBUG_INFO_DWARF4=y	76	CONFIG_DEBUG_INFO_DWARF4=y
77	CONFIG_DEBUG_INFO_BTF=y
78	CONFIG_DEBUG_FS=y	77	CONFIG_DEBUG_FS=y
79	CONFIG_PANIC_ON_OOPS=y	78	CONFIG_PANIC_ON_OOPS=y
80	# CONFIG_SCHED_DEBUG is not set	79	# CONFIG_SCHED_DEBUG is not set

arch/s390/kvm/kvm-s390.c+17−9

 	return 0;
 }
+static void __kvm_s390_set_tod_clock(struct kvm *kvm, const struct kvm_s390_vm_tod_clock *gtod);
 static int kvm_s390_set_tod_ext(struct kvm *kvm, struct kvm_device_attr *attr)
 {
 	struct kvm_s390_vm_tod_clock gtod;
 	if (!test_kvm_facility(kvm, 139) && gtod.epoch_idx)
 		return -EINVAL;
-	kvm_s390_set_tod_clock(kvm, &gtod);
+	__kvm_s390_set_tod_clock(kvm, &gtod);
 	VM_EVENT(kvm, 3, "SET: TOD extension: 0x%x, TOD base: 0x%llx",
 		gtod.epoch_idx, gtod.tod);
 			   sizeof(gtod.tod)))
 		return -EFAULT;
-	kvm_s390_set_tod_clock(kvm, &gtod);
+	__kvm_s390_set_tod_clock(kvm, &gtod);
 	VM_EVENT(kvm, 3, "SET: TOD base: 0x%llx", gtod.tod);
 	return 0;
 }
 	if (attr->flags)
 		return -EINVAL;
+	mutex_lock(&kvm->lock);
+	/*
+	 * For protected guests, the TOD is managed by the ultravisor, so trying
+	 * to change it will never bring the expected results.
+	 */
+	if (kvm_s390_pv_is_protected(kvm)) {
+		ret = -EOPNOTSUPP;
+		goto out_unlock;
+	}
 	switch (attr->attr) {
 	case KVM_S390_VM_TOD_EXT:
 		ret = kvm_s390_set_tod_ext(kvm, attr);
 		ret = -ENXIO;
 		break;
 	}
+out_unlock:
+	mutex_unlock(&kvm->lock);
 	return ret;
 }
 	preempt_enable();
 }
-void kvm_s390_set_tod_clock(struct kvm *kvm, const struct kvm_s390_vm_tod_clock *gtod)
-{
-	mutex_lock(&kvm->lock);
-	__kvm_s390_set_tod_clock(kvm, gtod);
-	mutex_unlock(&kvm->lock);
-}
 int kvm_s390_try_set_tod_clock(struct kvm *kvm, const struct kvm_s390_vm_tod_clock *gtod)
 {
 	if (!mutex_trylock(&kvm->lock))

arch/s390/kvm/kvm-s390.h+0−1

@@ -363,7 +363,6 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu); · 362 unmodified lines
363	int kvm_s390_handle_sigp_pei(struct kvm_vcpu *vcpu);	363	int kvm_s390_handle_sigp_pei(struct kvm_vcpu *vcpu);
364		364
365	/* implemented in kvm-s390.c */	365	/* implemented in kvm-s390.c */
366	void kvm_s390_set_tod_clock(struct kvm kvm, const struct kvm_s390_vm_tod_clock gtod);
367	int kvm_s390_try_set_tod_clock(struct kvm kvm, const struct kvm_s390_vm_tod_clock gtod);	366	int kvm_s390_try_set_tod_clock(struct kvm kvm, const struct kvm_s390_vm_tod_clock gtod);
368	long kvm_arch_fault_in_page(struct kvm_vcpu *vcpu, gpa_t gpa, int writable);	367	long kvm_arch_fault_in_page(struct kvm_vcpu *vcpu, gpa_t gpa, int writable);
369	int kvm_s390_store_status_unloaded(struct kvm_vcpu *vcpu, unsigned long addr);	368	int kvm_s390_store_status_unloaded(struct kvm_vcpu *vcpu, unsigned long addr);

arch/s390/kvm/pci.c+1−1

@@ -126,7 +126,7 @@ int kvm_s390_pci_aen_init(u8 nisc) · 125 unmodified lines
126	return -EPERM;	126	return -EPERM;
127		127
128	mutex_lock(&aift->aift_lock);	128	mutex_lock(&aift->aift_lock);
129	aift->kzdev = kcalloc(ZPCI_NR_DEVICES, sizeof(struct kvm_zdev),	129	aift->kzdev = kcalloc(ZPCI_NR_DEVICES, sizeof(struct kvm_zdev *),
130	GFP_KERNEL);	130	GFP_KERNEL);
131	if (!aift->kzdev) {	131	if (!aift->kzdev) {
132	rc = -ENOMEM;	132	rc = -ENOMEM;

arch/x86/hyperv/hv_init.c+10−9

 	if (hv_root_partition) {
 		struct page *pg;
-		void *src, *dst;
+		void *src;
 		/*
 		 * For the root partition, the hypervisor will set up its
 		wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
 		pg = vmalloc_to_page(hv_hypercall_pg);
-		dst = kmap_local_page(pg);
 		src = memremap(hypercall_msr.guest_physical_address << PAGE_SHIFT, PAGE_SIZE,
 				MEMREMAP_WB);
-		BUG_ON(!(src && dst));
+		BUG_ON(!src);
-		memcpy(dst, src, HV_HYP_PAGE_SIZE);
+		memcpy_to_page(pg, 0, src, HV_HYP_PAGE_SIZE);
 		memunmap(src);
-		kunmap_local(dst);
 	} else {
 		hypercall_msr.guest_physical_address = vmalloc_to_pfn(hv_hypercall_pg);
 		wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
 void hyperv_cleanup(void)
 {
 	union hv_x64_msr_hypercall_contents hypercall_msr;
+	union hv_reference_tsc_msr tsc_msr;
 	unregister_syscore_ops(&hv_syscore_ops);
 	hv_hypercall_pg = NULL;
 	/* Reset the hypercall page */
-	hypercall_msr.as_uint64 = 0;
+	hypercall_msr.as_uint64 = hv_get_register(HV_X64_MSR_HYPERCALL);
-	wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
+	hypercall_msr.enable = 0;
+	hv_set_register(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
 	/* Reset the TSC page */
-	hypercall_msr.as_uint64 = 0;
+	tsc_msr.as_uint64 = hv_get_register(HV_X64_MSR_REFERENCE_TSC);
-	wrmsrl(HV_X64_MSR_REFERENCE_TSC, hypercall_msr.as_uint64);
+	tsc_msr.enable = 0;
+	hv_set_register(HV_X64_MSR_REFERENCE_TSC, tsc_msr.as_uint64);
 }
 void hyperv_report_panic(struct pt_regs *regs, long err, bool in_die)

arch/x86/include/asm/kvm_host.h+6−1

 	bool intr;
 };
+/* More counters may conflict with other existing Architectural MSRs */
+#define KVM_INTEL_PMC_MAX_GENERIC	8
+#define MSR_ARCH_PERFMON_PERFCTR_MAX	(MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
+#define MSR_ARCH_PERFMON_EVENTSEL_MAX	(MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
 #define KVM_PMC_MAX_FIXED	3
+#define KVM_AMD_PMC_MAX_GENERIC	6
 struct kvm_pmu {
 	unsigned nr_arch_gp_counters;
 	unsigned nr_arch_fixed_counters;
 	u64 reserved_bits;
 	u64 raw_event_mask;
 	u8 version;
-	struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
+	struct kvm_pmc gp_counters[KVM_INTEL_PMC_MAX_GENERIC];
 	struct kvm_pmc fixed_counters[KVM_PMC_MAX_FIXED];
 	struct irq_work irq_work;
 	DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);

arch/x86/include/asm/spec-ctrl.h+5−5

@@ -13,7 +13,7 @@ · 12 unmodified lines
13	* Takes the guest view of SPEC_CTRL MSR as a parameter and also	13	* Takes the guest view of SPEC_CTRL MSR as a parameter and also
14	* the guest's version of VIRT_SPEC_CTRL, if emulated.	14	* the guest's version of VIRT_SPEC_CTRL, if emulated.
15	*/	15	*/
16	extern void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool guest);	16	extern void x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool guest);
17		17
18	/**	18	/**
19	* x86_spec_ctrl_set_guest - Set speculation control registers for the guest	19	* x86_spec_ctrl_set_guest - Set speculation control registers for the guest
@@ -24,9 +24,9 @@ extern void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bo · 4 unmodified lines
24	* Avoids writing to the MSR if the content/bits are the same	24	* Avoids writing to the MSR if the content/bits are the same
25	*/	25	*/
26	static inline	26	static inline
27	void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)	27	void x86_spec_ctrl_set_guest(u64 guest_virt_spec_ctrl)
28	{	28	{
29	x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, true);	29	x86_virt_spec_ctrl(guest_virt_spec_ctrl, true);
30	}	30	}
31		31
32	/**	32	/**
@@ -38,9 +38,9 @@ void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl) · 5 unmodified lines
38	* Avoids writing to the MSR if the content/bits are the same	38	* Avoids writing to the MSR if the content/bits are the same
39	*/	39	*/
40	static inline	40	static inline
41	void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)	41	void x86_spec_ctrl_restore_host(u64 guest_virt_spec_ctrl)
42	{	42	{
43	x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, false);	43	x86_virt_spec_ctrl(guest_virt_spec_ctrl, false);
44	}	44	}
45		45
46	/* AMD specific Speculative Store Bypass MSR data */	46	/* AMD specific Speculative Store Bypass MSR data */

arch/x86/kernel/asm-offsets.c+0−6

 #include <asm/suspend.h>
 #include <asm/tlbflush.h>
 #include <asm/tdx.h>
-#include "../kvm/vmx/vmx.h"
 #ifdef CONFIG_XEN
 #include <xen/interface/xen.h>
 	OFFSET(TSS_sp0, tss_struct, x86_tss.sp0);
 	OFFSET(TSS_sp1, tss_struct, x86_tss.sp1);
 	OFFSET(TSS_sp2, tss_struct, x86_tss.sp2);
-	if (IS_ENABLED(CONFIG_KVM_INTEL)) {
-		BLANK();
-		OFFSET(VMX_spec_ctrl, vcpu_vmx, spec_ctrl);
-	}
 }

arch/x86/kernel/cpu/bugs.c+4−11

 }
 /*
- * NOTE: This function is *only* called for SVM.  VMX spec_ctrl handling is
+ * NOTE: This function is *only* called for SVM, since Intel uses
- * done in vmenter.S.
+ * MSR_IA32_SPEC_CTRL for SSBD.
  */
 void
-x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
+x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool setguest)
 {
-	u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
+	u64 guestval, hostval;
 	struct thread_info *ti = current_thread_info();
-	if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
-		if (hostval != guestval) {
-			msrval = setguest ? guestval : hostval;
-			wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
-		}
-	}
 	/*
 	 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 	 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.

arch/x86/kernel/traps.c+7−0

 #include <linux/context_tracking.h>
 #include <linux/interrupt.h>
 #include <linux/kallsyms.h>
+#include <linux/kmsan.h>
 #include <linux/spinlock.h>
 #include <linux/kprobes.h>
 #include <linux/uaccess.h>
 {
 	bool handled = false;
+	/*
+	 * Normally @regs are unpoisoned by irqentry_enter(), but handle_bug()
+	 * is a rare case that uses @regs without passing them to
+	 * irqentry_enter().
+	 */
+	kmsan_unpoison_entry_regs(regs);
 	if (!is_valid_bugaddr(regs->ip))
 		return handled;

arch/x86/kvm/.gitignore+2−0

@@ -0,0 +1,2 @@
	1	/kvm-asm-offsets.s
	2	/kvm-asm-offsets.h

arch/x86/kvm/Makefile+12−0

@@ -34,3 +34,15 @@ endif · 33 unmodified lines
34	obj-$(CONFIG_KVM) += kvm.o	34	obj-$(CONFIG_KVM) += kvm.o
35	obj-$(CONFIG_KVM_INTEL) += kvm-intel.o	35	obj-$(CONFIG_KVM_INTEL) += kvm-intel.o
36	obj-$(CONFIG_KVM_AMD) += kvm-amd.o	36	obj-$(CONFIG_KVM_AMD) += kvm-amd.o
		37
		38	AFLAGS_svm/vmenter.o := -iquote $(obj)
		39	$(obj)/svm/vmenter.o: $(obj)/kvm-asm-offsets.h
		40
		41	AFLAGS_vmx/vmenter.o := -iquote $(obj)
		42	$(obj)/vmx/vmenter.o: $(obj)/kvm-asm-offsets.h
		43
		44	$(obj)/kvm-asm-offsets.h: $(obj)/kvm-asm-offsets.s FORCE
		45	$(call filechk,offsets,__KVM_ASM_OFFSETS_H__)
		46
		47	targets += kvm-asm-offsets.s
		48	clean-files += kvm-asm-offsets.h

arch/x86/kvm/kvm-asm-offsets.c+29−0

@@ -0,0 +1,29 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Generate definitions needed by assembly language modules.
	4	* This code generates raw asm output which is post-processed to extract
	5	* and format the required data.
	6	*/
	7	#define COMPILE_OFFSETS
	8
	9	#include <linux/kbuild.h>
	10	#include "vmx/vmx.h"
	11	#include "svm/svm.h"
	12
	13	static void __used common(void)
	14	{
	15	if (IS_ENABLED(CONFIG_KVM_AMD)) {
	16	BLANK();
	17	OFFSET(SVM_vcpu_arch_regs, vcpu_svm, vcpu.arch.regs);
	18	OFFSET(SVM_current_vmcb, vcpu_svm, current_vmcb);
	19	OFFSET(SVM_spec_ctrl, vcpu_svm, spec_ctrl);
	20	OFFSET(SVM_vmcb01, vcpu_svm, vmcb01);
	21	OFFSET(KVM_VMCB_pa, kvm_vmcb_info, pa);
	22	OFFSET(SD_save_area_pa, svm_cpu_data, save_area_pa);
	23	}
	24
	25	if (IS_ENABLED(CONFIG_KVM_INTEL)) {
	26	BLANK();
	27	OFFSET(VMX_spec_ctrl, vcpu_vmx, spec_ctrl);
	28	}
	29	}

arch/x86/kvm/mmu/mmu.c+2−2

@@ -6056,7 +6056,7 @@ void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) · 6055 unmodified lines
6056		6056
6057	write_lock(&kvm->mmu_lock);	6057	write_lock(&kvm->mmu_lock);
6058		6058
6059	kvm_mmu_invalidate_begin(kvm, gfn_start, gfn_end);	6059	kvm_mmu_invalidate_begin(kvm, 0, -1ul);
6060		6060
6061	flush = kvm_rmap_zap_gfn_range(kvm, gfn_start, gfn_end);	6061	flush = kvm_rmap_zap_gfn_range(kvm, gfn_start, gfn_end);
6062		6062
@@ -6070,7 +6070,7 @@ void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) · 7 unmodified lines
6070	kvm_flush_remote_tlbs_with_address(kvm, gfn_start,	6070	kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
6071	gfn_end - gfn_start);	6071	gfn_end - gfn_start);
6072		6072
6073	kvm_mmu_invalidate_end(kvm, gfn_start, gfn_end);	6073	kvm_mmu_invalidate_end(kvm, 0, -1ul);
6074		6074
6075	write_unlock(&kvm->mmu_lock);	6075	write_unlock(&kvm->mmu_lock);
6076	}	6076	}

arch/x86/kvm/pmu.c+1−1

@@ -56,7 +56,7 @@ static const struct x86_cpu_id vmx_icl_pebs_cpu[] = { · 55 unmodified lines
56	* code. Each pmc, stored in kvm_pmc.idx field, is unique across	56	* code. Each pmc, stored in kvm_pmc.idx field, is unique across
57	* all perf counters (both gp and fixed). The mapping relationship	57	* all perf counters (both gp and fixed). The mapping relationship
58	* between pmc and perf counters is as the following:	58	* between pmc and perf counters is as the following:
59	* * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters	59	* * Intel: [0 .. KVM_INTEL_PMC_MAX_GENERIC-1] <=> gp counters
60	* [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed	60	* [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
61	* * AMD: [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H	61	* * AMD: [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H
62	* and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=> gp counters	62	* and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=> gp counters

arch/x86/kvm/svm/pmu.c+4−3

 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 	int i;
-	BUILD_BUG_ON(AMD64_NUM_COUNTERS_CORE > INTEL_PMC_MAX_GENERIC);
+	BUILD_BUG_ON(KVM_AMD_PMC_MAX_GENERIC > AMD64_NUM_COUNTERS_CORE);
+	BUILD_BUG_ON(KVM_AMD_PMC_MAX_GENERIC > INTEL_PMC_MAX_GENERIC);
-	for (i = 0; i < AMD64_NUM_COUNTERS_CORE ; i++) {
+	for (i = 0; i < KVM_AMD_PMC_MAX_GENERIC ; i++) {
 		pmu->gp_counters[i].type = KVM_PMC_GP;
 		pmu->gp_counters[i].vcpu = vcpu;
 		pmu->gp_counters[i].idx = i;
 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 	int i;
-	for (i = 0; i < AMD64_NUM_COUNTERS_CORE; i++) {
+	for (i = 0; i < KVM_AMD_PMC_MAX_GENERIC; i++) {
 		struct kvm_pmc *pmc = &pmu->gp_counters[i];
 		pmc_stop_counter(pmc);

arch/x86/kvm/svm/sev.c+3−3

@@ -196,7 +196,7 @@ static void sev_asid_free(struct kvm_sev_info *sev) · 195 unmodified lines
196	__set_bit(sev->asid, sev_reclaim_asid_bitmap);	196	__set_bit(sev->asid, sev_reclaim_asid_bitmap);
197		197
198	for_each_possible_cpu(cpu) {	198	for_each_possible_cpu(cpu) {
199	sd = per_cpu(svm_data, cpu);	199	sd = per_cpu_ptr(&svm_data, cpu);
200	sd->sev_vmcbs[sev->asid] = NULL;	200	sd->sev_vmcbs[sev->asid] = NULL;
201	}	201	}
202		202
@@ -605,7 +605,7 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) · 402 unmodified lines
605	save->dr6 = svm->vcpu.arch.dr6;	605	save->dr6 = svm->vcpu.arch.dr6;
606		606
607	pr_debug("Virtual Machine Save Area (VMSA):\n");	607	pr_debug("Virtual Machine Save Area (VMSA):\n");
608	print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 1, save, sizeof(*save), false);	608	print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1, save, sizeof(*save), false);
609		609
610	return 0;	610	return 0;
611	}	611	}
@@ -2600,7 +2600,7 @@ void sev_es_unmap_ghcb(struct vcpu_svm *svm) · 1988 unmodified lines
2600		2600
2601	void pre_sev_run(struct vcpu_svm *svm, int cpu)	2601	void pre_sev_run(struct vcpu_svm *svm, int cpu)
2602	{	2602	{
2603	struct svm_cpu_data *sd = per_cpu(svm_data, cpu);	2603	struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
2604	int asid = sev_get_asid(svm->vcpu.kvm);	2604	int asid = sev_get_asid(svm->vcpu.kvm);
2605		2605
2606	/* Assign the asid allocated with this SEV guest */	2606	/* Assign the asid allocated with this SEV guest */

arch/x86/kvm/svm/svm.c+36−69

 	u32 zero1;
 } __attribute__((packed));
-DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
+DEFINE_PER_CPU(struct svm_cpu_data, svm_data);
 /*
  * Only MSR_TSC_AUX is switched via the user return hook.  EFER is switched via
 		pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 		return -EINVAL;
 	}
-	sd = per_cpu(svm_data, me);
+	sd = per_cpu_ptr(&svm_data, me);
-	if (!sd) {
-		pr_err("%s: svm_data is NULL on %d\n", __func__, me);
-		return -EINVAL;
-	}
 	sd->asid_generation = 1;
 	sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 	sd->next_asid = sd->max_asid + 1;
 	wrmsrl(MSR_EFER, efer | EFER_SVME);
-	wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
+	wrmsrl(MSR_VM_HSAVE_PA, sd->save_area_pa);
 	if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 		/*
 static void svm_cpu_uninit(int cpu)
 {
-	struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
+	struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
-	if (!sd)
+	if (!sd->save_area)
 		return;
-	per_cpu(svm_data, cpu) = NULL;
 	kfree(sd->sev_vmcbs);
 	__free_page(sd->save_area);
-	kfree(sd);
+	sd->save_area_pa = 0;
+	sd->save_area = NULL;
 }
 static int svm_cpu_init(int cpu)
 {
-	struct svm_cpu_data *sd;
+	struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
 	int ret = -ENOMEM;
-	sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
+	memset(sd, 0, sizeof(struct svm_cpu_data));
-	if (!sd)
-		return ret;
-	sd->cpu = cpu;
 	sd->save_area = alloc_page(GFP_KERNEL | __GFP_ZERO);
 	if (!sd->save_area)
-		goto free_cpu_data;
+		return ret;
 	ret = sev_cpu_init(sd);
 	if (ret)
 		goto free_save_area;
-	per_cpu(svm_data, cpu) = sd;
+	sd->save_area_pa = __sme_page_pa(sd->save_area);
 	return 0;
 free_save_area:
 	__free_page(sd->save_area);
-free_cpu_data:
+	sd->save_area = NULL;
-	kfree(sd);
 	return ret;
 }
 	u32 offset;
 	u32 *msrpm;
+	/*
+	 * For non-nested case:
+	 * If the L01 MSR bitmap does not intercept the MSR, then we need to
+	 * save it.
+	 *
+	 * For nested case:
+	 * If the L02 MSR bitmap does not intercept the MSR, then we need to
+	 * save it.
+	 */
 	msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 				      to_svm(vcpu)->msrpm;
 	int i;
 	for_each_online_cpu(i)
-		cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
+		cmpxchg(per_cpu_ptr(&svm_data.current_vmcb, i), vmcb, NULL);
 }
 static void svm_vcpu_free(struct kvm_vcpu *vcpu)
 static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
-	struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
+	struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
 	if (sev_es_guest(vcpu->kvm))
 		sev_es_unmap_ghcb(svm);
 	 * Save additional host state that will be restored on VMEXIT (sev-es)
 	 * or subsequent vmload of host save area.
 	 */
-	vmsave(__sme_page_pa(sd->save_area));
+	vmsave(sd->save_area_pa);
 	if (sev_es_guest(vcpu->kvm)) {
 		struct sev_es_save_area *hostsa;
 		hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400);
 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
-	struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
+	struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
 	if (sd->current_vmcb != svm->vmcb) {
 		sd->current_vmcb = svm->vmcb;
 static void reload_tss(struct kvm_vcpu *vcpu)
 {
-	struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
+	struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
 	sd->tss_desc->type = 9; /* available 32/64-bit TSS */
 	load_TR_desc();
 static void pre_svm_run(struct kvm_vcpu *vcpu)
 {
-	struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
+	struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
 	struct vcpu_svm *svm = to_svm(vcpu);
 	/*
 	return EXIT_FASTPATH_NONE;
 }
-static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
+static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_intercepted)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
-	unsigned long vmcb_pa = svm->current_vmcb->pa;
 	guest_state_enter_irqoff();
-	if (sev_es_guest(vcpu->kvm)) {
+	if (sev_es_guest(vcpu->kvm))
-		__svm_sev_es_vcpu_run(vmcb_pa);
+		__svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted);
-	} else {
+	else
-		struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
+		__svm_vcpu_run(svm, spec_ctrl_intercepted);
-		/*
-		 * Use a single vmcb (vmcb01 because it's always valid) for
-		 * context switching guest state via VMLOAD/VMSAVE, that way
-		 * the state doesn't need to be copied between vmcb01 and
-		 * vmcb02 when switching vmcbs for nested virtualization.
-		 */
-		vmload(svm->vmcb01.pa);
-		__svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
-		vmsave(svm->vmcb01.pa);
-		vmload(__sme_page_pa(sd->save_area));
-	}
 	guest_state_exit_irqoff();
 }
 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
+	bool spec_ctrl_intercepted = msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL);
 	trace_kvm_entry(vcpu);
 	 * being speculatively taken.
 	 */
 	if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
-		x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
+		x86_spec_ctrl_set_guest(svm->virt_spec_ctrl);
-	svm_vcpu_enter_exit(vcpu);
+	svm_vcpu_enter_exit(vcpu, spec_ctrl_intercepted);
-	/*
-	 * We do not use IBRS in the kernel. If this vCPU has used the
-	 * SPEC_CTRL MSR it may have left it on; save the value and
-	 * turn it off. This is much more efficient than blindly adding
-	 * it to the atomic save/restore list. Especially as the former
-	 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
-	 *
-	 * For non-nested case:
-	 * If the L01 MSR bitmap does not intercept the MSR, then we need to
-	 * save it.
-	 *
-	 * For nested case:
-	 * If the L02 MSR bitmap does not intercept the MSR, then we need to
-	 * save it.
-	 */
-	if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
-	    unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
-		svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
 	if (!sev_es_guest(vcpu->kvm))
 		reload_tss(vcpu);
 	if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
-		x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
+		x86_spec_ctrl_restore_host(svm->virt_spec_ctrl);
 	if (!sev_es_guest(vcpu->kvm)) {
 		vcpu->arch.cr2 = svm->vmcb->save.cr2;

arch/x86/kvm/svm/svm.h+5−6

 	struct vmcb *vmcb;
 	struct kvm_vmcb_info vmcb01;
 	struct kvm_vmcb_info *current_vmcb;
-	struct svm_cpu_data *svm_data;
 	u32 asid;
 	u32 sysenter_esp_hi;
 	u32 sysenter_eip_hi;
 };
 struct svm_cpu_data {
-	int cpu;
 	u64 asid_generation;
 	u32 max_asid;
 	u32 next_asid;
 	struct kvm_ldttss_desc *tss_desc;
 	struct page *save_area;
+	unsigned long save_area_pa;
 	struct vmcb *current_vmcb;
 	/* index = sev_asid, value = vmcb pointer */
 	struct vmcb **sev_vmcbs;
 };
-DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);
+DECLARE_PER_CPU(struct svm_cpu_data, svm_data);
 void recalc_intercepts(struct vcpu_svm *svm);
 /* vmenter.S */
-void __svm_sev_es_vcpu_run(unsigned long vmcb_pa);
+void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted);
-void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
+void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted);
 #endif

arch/x86/kvm/svm/svm_ops.h+0−5

@@ -61,9 +61,4 @@ static __always_inline void vmsave(unsigned long pa) · 60 unmodified lines
61	svm_asm1(vmsave, "a" (pa), "memory");	61	svm_asm1(vmsave, "a" (pa), "memory");
62	}	62	}
63		63
64	static __always_inline void vmload(unsigned long pa)
65	{
66	svm_asm1(vmload, "a" (pa), "memory");
67	}
68
69	#endif /* __KVM_X86_SVM_OPS_H */	64	#endif /* __KVM_X86_SVM_OPS_H */

arch/x86/kvm/svm/vmenter.S+209−51

@@ -4,35 +4,97 @@ · 3 unmodified lines
4	#include <asm/bitsperlong.h>	4	#include <asm/bitsperlong.h>
5	#include <asm/kvm_vcpu_regs.h>	5	#include <asm/kvm_vcpu_regs.h>
6	#include <asm/nospec-branch.h>	6	#include <asm/nospec-branch.h>
		7	#include "kvm-asm-offsets.h"
7		8
8	#define WORD_SIZE (BITS_PER_LONG / 8)	9	#define WORD_SIZE (BITS_PER_LONG / 8)
9		10
10	/* Intentionally omit RAX as it's context switched by hardware */	11	/* Intentionally omit RAX as it's context switched by hardware */
11	#define VCPU_RCX __VCPU_REGS_RCX * WORD_SIZE	12	#define VCPU_RCX (SVM_vcpu_arch_regs + __VCPU_REGS_RCX * WORD_SIZE)
12	#define VCPU_RDX __VCPU_REGS_RDX * WORD_SIZE	13	#define VCPU_RDX (SVM_vcpu_arch_regs + __VCPU_REGS_RDX * WORD_SIZE)
13	#define VCPU_RBX __VCPU_REGS_RBX * WORD_SIZE	14	#define VCPU_RBX (SVM_vcpu_arch_regs + __VCPU_REGS_RBX * WORD_SIZE)
14	/* Intentionally omit RSP as it's context switched by hardware */	15	/* Intentionally omit RSP as it's context switched by hardware */
15	#define VCPU_RBP __VCPU_REGS_RBP * WORD_SIZE	16	#define VCPU_RBP (SVM_vcpu_arch_regs + __VCPU_REGS_RBP * WORD_SIZE)
16	#define VCPU_RSI __VCPU_REGS_RSI * WORD_SIZE	17	#define VCPU_RSI (SVM_vcpu_arch_regs + __VCPU_REGS_RSI * WORD_SIZE)
17	#define VCPU_RDI __VCPU_REGS_RDI * WORD_SIZE	18	#define VCPU_RDI (SVM_vcpu_arch_regs + __VCPU_REGS_RDI * WORD_SIZE)
18		19
19	#ifdef CONFIG_X86_64	20	#ifdef CONFIG_X86_64
20	#define VCPU_R8 __VCPU_REGS_R8 * WORD_SIZE	21	#define VCPU_R8 (SVM_vcpu_arch_regs + __VCPU_REGS_R8 * WORD_SIZE)
21	#define VCPU_R9 __VCPU_REGS_R9 * WORD_SIZE	22	#define VCPU_R9 (SVM_vcpu_arch_regs + __VCPU_REGS_R9 * WORD_SIZE)
22	#define VCPU_R10 __VCPU_REGS_R10 * WORD_SIZE	23	#define VCPU_R10 (SVM_vcpu_arch_regs + __VCPU_REGS_R10 * WORD_SIZE)
23	#define VCPU_R11 __VCPU_REGS_R11 * WORD_SIZE	24	#define VCPU_R11 (SVM_vcpu_arch_regs + __VCPU_REGS_R11 * WORD_SIZE)
24	#define VCPU_R12 __VCPU_REGS_R12 * WORD_SIZE	25	#define VCPU_R12 (SVM_vcpu_arch_regs + __VCPU_REGS_R12 * WORD_SIZE)
25	#define VCPU_R13 __VCPU_REGS_R13 * WORD_SIZE	26	#define VCPU_R13 (SVM_vcpu_arch_regs + __VCPU_REGS_R13 * WORD_SIZE)
26	#define VCPU_R14 __VCPU_REGS_R14 * WORD_SIZE	27	#define VCPU_R14 (SVM_vcpu_arch_regs + __VCPU_REGS_R14 * WORD_SIZE)
27	#define VCPU_R15 __VCPU_REGS_R15 * WORD_SIZE	28	#define VCPU_R15 (SVM_vcpu_arch_regs + __VCPU_REGS_R15 * WORD_SIZE)
28	#endif	29	#endif
29		30
		31	#define SVM_vmcb01_pa (SVM_vmcb01 + KVM_VMCB_pa)
		32
30	.section .noinstr.text, "ax"	33	.section .noinstr.text, "ax"
31		34
		35	.macro RESTORE_GUEST_SPEC_CTRL
		36	/* No need to do anything if SPEC_CTRL is unset or V_SPEC_CTRL is set */
		37	ALTERNATIVE_2 "", \
		38	"jmp 800f", X86_FEATURE_MSR_SPEC_CTRL, \
		39	"", X86_FEATURE_V_SPEC_CTRL
		40	801:
		41	.endm
		42	.macro RESTORE_GUEST_SPEC_CTRL_BODY
		43	800:
		44	/*
		45	* SPEC_CTRL handling: if the guest's SPEC_CTRL value differs from the
		46	* host's, write the MSR. This is kept out-of-line so that the common
		47	* case does not have to jump.
		48	*
		49	* IMPORTANT: To avoid RSB underflow attacks and any other nastiness,
		50	* there must not be any returns or indirect branches between this code
		51	* and vmentry.
		52	*/
		53	movl SVM_spec_ctrl(%_ASM_DI), %eax
		54	cmp PER_CPU_VAR(x86_spec_ctrl_current), %eax
		55	je 801b
		56	mov $MSR_IA32_SPEC_CTRL, %ecx
		57	xor %edx, %edx
		58	wrmsr
		59	jmp 801b
		60	.endm
		61
		62	.macro RESTORE_HOST_SPEC_CTRL
		63	/* No need to do anything if SPEC_CTRL is unset or V_SPEC_CTRL is set */
		64	ALTERNATIVE_2 "", \
		65	"jmp 900f", X86_FEATURE_MSR_SPEC_CTRL, \
		66	"", X86_FEATURE_V_SPEC_CTRL
		67	901:
		68	.endm
		69	.macro RESTORE_HOST_SPEC_CTRL_BODY
		70	900:
		71	/* Same for after vmexit. */
		72	mov $MSR_IA32_SPEC_CTRL, %ecx
		73
		74	/*
		75	* Load the value that the guest had written into MSR_IA32_SPEC_CTRL,
		76	* if it was not intercepted during guest execution.
		77	*/
		78	cmpb $0, (%_ASM_SP)
		79	jnz 998f
		80	rdmsr
		81	movl %eax, SVM_spec_ctrl(%_ASM_DI)
		82	998:
		83
		84	/* Now restore the host value of the MSR if different from the guest's. */
		85	movl PER_CPU_VAR(x86_spec_ctrl_current), %eax
		86	cmp SVM_spec_ctrl(%_ASM_DI), %eax
		87	je 901b
		88	xor %edx, %edx
		89	wrmsr
		90	jmp 901b
		91	.endm
		92
		93
32	/**	94	/**
33	* __svm_vcpu_run - Run a vCPU via a transition to SVM guest mode	95	* __svm_vcpu_run - Run a vCPU via a transition to SVM guest mode
34	* @vmcb_pa: unsigned long	96	* @svm: struct vcpu_svm *
35	* @regs: unsigned long * (to guest registers)	97	* @spec_ctrl_intercepted: bool
36	*/	98	*/
37	SYM_FUNC_START(__svm_vcpu_run)	99	SYM_FUNC_START(__svm_vcpu_run)
38	push %_ASM_BP	100	push %_ASM_BP
@@ -47,49 +109,71 @@ SYM_FUNC_START(__svm_vcpu_run) · 8 unmodified lines
47	#endif	109	#endif
48	push %_ASM_BX	110	push %_ASM_BX
49		111
50	/* Save @regs. */	112	/*
		113	* Save variables needed after vmexit on the stack, in inverse
		114	* order compared to when they are needed.
		115	*/
		116
		117	/* Accessed directly from the stack in RESTORE_HOST_SPEC_CTRL. */
51	push %_ASM_ARG2	118	push %_ASM_ARG2
52		119
53	/* Save @vmcb. */	120	/* Needed to restore access to percpu variables. */
		121	__ASM_SIZE(push) PER_CPU_VAR(svm_data + SD_save_area_pa)
		122
		123	/* Finally save @svm. */
54	push %_ASM_ARG1	124	push %_ASM_ARG1
55		125
56	/* Move @regs to RAX. */	126	.ifnc _ASM_ARG1, _ASM_DI
57	mov %_ASM_ARG2, %_ASM_AX	127	/*
		128	* Stash @svm in RDI early. On 32-bit, arguments are in RAX, RCX
		129	* and RDX which are clobbered by RESTORE_GUEST_SPEC_CTRL.
		130	*/
		131	mov %_ASM_ARG1, %_ASM_DI
		132	.endif
		133
		134	/* Clobbers RAX, RCX, RDX. */
		135	RESTORE_GUEST_SPEC_CTRL
		136
		137	/*
		138	* Use a single vmcb (vmcb01 because it's always valid) for
		139	* context switching guest state via VMLOAD/VMSAVE, that way
		140	* the state doesn't need to be copied between vmcb01 and
		141	* vmcb02 when switching vmcbs for nested virtualization.
		142	*/
		143	mov SVM_vmcb01_pa(%_ASM_DI), %_ASM_AX
		144	1: vmload %_ASM_AX
		145	2:
		146
		147	/* Get svm->current_vmcb->pa into RAX. */
		148	mov SVM_current_vmcb(%_ASM_DI), %_ASM_AX
		149	mov KVM_VMCB_pa(%_ASM_AX), %_ASM_AX
58		150
59	/* Load guest registers. */	151	/* Load guest registers. */
60	mov VCPU_RCX(%_ASM_AX), %_ASM_CX	152	mov VCPU_RCX(%_ASM_DI), %_ASM_CX
61	mov VCPU_RDX(%_ASM_AX), %_ASM_DX	153	mov VCPU_RDX(%_ASM_DI), %_ASM_DX
62	mov VCPU_RBX(%_ASM_AX), %_ASM_BX	154	mov VCPU_RBX(%_ASM_DI), %_ASM_BX
63	mov VCPU_RBP(%_ASM_AX), %_ASM_BP	155	mov VCPU_RBP(%_ASM_DI), %_ASM_BP
64	mov VCPU_RSI(%_ASM_AX), %_ASM_SI	156	mov VCPU_RSI(%_ASM_DI), %_ASM_SI
65	mov VCPU_RDI(%_ASM_AX), %_ASM_DI
66	#ifdef CONFIG_X86_64	157	#ifdef CONFIG_X86_64
67	mov VCPU_R8 (%_ASM_AX), %r8	158	mov VCPU_R8 (%_ASM_DI), %r8
68	mov VCPU_R9 (%_ASM_AX), %r9	159	mov VCPU_R9 (%_ASM_DI), %r9
69	mov VCPU_R10(%_ASM_AX), %r10	160	mov VCPU_R10(%_ASM_DI), %r10
70	mov VCPU_R11(%_ASM_AX), %r11	161	mov VCPU_R11(%_ASM_DI), %r11
71	mov VCPU_R12(%_ASM_AX), %r12	162	mov VCPU_R12(%_ASM_DI), %r12
72	mov VCPU_R13(%_ASM_AX), %r13	163	mov VCPU_R13(%_ASM_DI), %r13
73	mov VCPU_R14(%_ASM_AX), %r14	164	mov VCPU_R14(%_ASM_DI), %r14
74	mov VCPU_R15(%_ASM_AX), %r15	165	mov VCPU_R15(%_ASM_DI), %r15
75	#endif	166	#endif
76		167	mov VCPU_RDI(%_ASM_DI), %_ASM_DI
77	/* "POP" @vmcb to RAX. */
78	pop %_ASM_AX
79		168
80	/* Enter guest mode */	169	/* Enter guest mode */
81	sti	170	sti
82		171
83	1: vmrun %_ASM_AX	172	3: vmrun %_ASM_AX
84		173	4:
85	2: cli	174	cli
86
87	#ifdef CONFIG_RETPOLINE
88	/* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
89	FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
90	#endif
91		175
92	/* "POP" @regs to RAX. */	176	/* Pop @svm to RAX while it's the only available register. */
93	pop %_ASM_AX	177	pop %_ASM_AX
94		178
95	/* Save all guest registers. */	179	/* Save all guest registers. */
@@ -110,6 +194,26 @@ SYM_FUNC_START(__svm_vcpu_run) · 14 unmodified lines
110	mov %r15, VCPU_R15(%_ASM_AX)	194	mov %r15, VCPU_R15(%_ASM_AX)
111	#endif	195	#endif
112		196
		197	/* @svm can stay in RDI from now on. */
		198	mov %_ASM_AX, %_ASM_DI
		199
		200	mov SVM_vmcb01_pa(%_ASM_DI), %_ASM_AX
		201	5: vmsave %_ASM_AX
		202	6:
		203
		204	/* Restores GSBASE among other things, allowing access to percpu data. */
		205	pop %_ASM_AX
		206	7: vmload %_ASM_AX
		207	8:
		208
		209	#ifdef CONFIG_RETPOLINE
		210	/* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
		211	FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
		212	#endif
		213
		214	/* Clobbers RAX, RCX, RDX. */
		215	RESTORE_HOST_SPEC_CTRL
		216
113	/*	217	/*
114	* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be	218	* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
115	* untrained as soon as we exit the VM and are back to the	219	* untrained as soon as we exit the VM and are back to the
@@ -145,6 +249,9 @@ SYM_FUNC_START(__svm_vcpu_run) · 29 unmodified lines
145	xor %r15d, %r15d	249	xor %r15d, %r15d
146	#endif	250	#endif
147		251
		252	/* "Pop" @spec_ctrl_intercepted. */
		253	pop %_ASM_BX
		254
148	pop %_ASM_BX	255	pop %_ASM_BX
149		256
150	#ifdef CONFIG_X86_64	257	#ifdef CONFIG_X86_64
@@ -159,17 +266,33 @@ SYM_FUNC_START(__svm_vcpu_run) · 8 unmodified lines
159	pop %_ASM_BP	266	pop %_ASM_BP
160	RET	267	RET
161		268
162	3: cmpb $0, kvm_rebooting	269	RESTORE_GUEST_SPEC_CTRL_BODY
		270	RESTORE_HOST_SPEC_CTRL_BODY
		271
		272	10: cmpb $0, kvm_rebooting
163	jne 2b	273	jne 2b
164	ud2	274	ud2
		275	30: cmpb $0, kvm_rebooting
		276	jne 4b
		277	ud2
		278	50: cmpb $0, kvm_rebooting
		279	jne 6b
		280	ud2
		281	70: cmpb $0, kvm_rebooting
		282	jne 8b
		283	ud2
165		284
166	_ASM_EXTABLE(1b, 3b)	285	_ASM_EXTABLE(1b, 10b)
		286	_ASM_EXTABLE(3b, 30b)
		287	_ASM_EXTABLE(5b, 50b)
		288	_ASM_EXTABLE(7b, 70b)
167		289
168	SYM_FUNC_END(__svm_vcpu_run)	290	SYM_FUNC_END(__svm_vcpu_run)
169		291
170	/**	292	/**
171	* __svm_sev_es_vcpu_run - Run a SEV-ES vCPU via a transition to SVM guest mode	293	* __svm_sev_es_vcpu_run - Run a SEV-ES vCPU via a transition to SVM guest mode
172	* @vmcb_pa: unsigned long	294	* @svm: struct vcpu_svm *
		295	* @spec_ctrl_intercepted: bool
173	*/	296	*/
174	SYM_FUNC_START(__svm_sev_es_vcpu_run)	297	SYM_FUNC_START(__svm_sev_es_vcpu_run)
175	push %_ASM_BP	298	push %_ASM_BP
@@ -184,8 +307,31 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run) · 8 unmodified lines
184	#endif	307	#endif
185	push %_ASM_BX	308	push %_ASM_BX
186		309
187	/* Move @vmcb to RAX. */	310	/*
188	mov %_ASM_ARG1, %_ASM_AX	311	* Save variables needed after vmexit on the stack, in inverse
		312	* order compared to when they are needed.
		313	*/
		314
		315	/* Accessed directly from the stack in RESTORE_HOST_SPEC_CTRL. */
		316	push %_ASM_ARG2
		317
		318	/* Save @svm. */
		319	push %_ASM_ARG1
		320
		321	.ifnc _ASM_ARG1, _ASM_DI
		322	/*
		323	* Stash @svm in RDI early. On 32-bit, arguments are in RAX, RCX
		324	* and RDX which are clobbered by RESTORE_GUEST_SPEC_CTRL.
		325	*/
		326	mov %_ASM_ARG1, %_ASM_DI
		327	.endif
		328
		329	/* Clobbers RAX, RCX, RDX. */
		330	RESTORE_GUEST_SPEC_CTRL
		331
		332	/* Get svm->current_vmcb->pa into RAX. */
		333	mov SVM_current_vmcb(%_ASM_DI), %_ASM_AX
		334	mov KVM_VMCB_pa(%_ASM_AX), %_ASM_AX
189		335
190	/* Enter guest mode */	336	/* Enter guest mode */
191	sti	337	sti
@@ -194,11 +340,17 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run) · 2 unmodified lines
194		340
195	2: cli	341	2: cli
196		342
		343	/* Pop @svm to RDI, guest registers have been saved already. */
		344	pop %_ASM_DI
		345
197	#ifdef CONFIG_RETPOLINE	346	#ifdef CONFIG_RETPOLINE
198	/* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */	347	/* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
199	FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE	348	FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RETPOLINE
200	#endif	349	#endif
201		350
		351	/* Clobbers RAX, RCX, RDX. */
		352	RESTORE_HOST_SPEC_CTRL
		353
202	/*	354	/*
203	* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be	355	* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
204	* untrained as soon as we exit the VM and are back to the	356	* untrained as soon as we exit the VM and are back to the
@@ -208,6 +360,9 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run) · 3 unmodified lines
208	*/	360	*/
209	UNTRAIN_RET	361	UNTRAIN_RET
210		362
		363	/* "Pop" @spec_ctrl_intercepted. */
		364	pop %_ASM_BX
		365
211	pop %_ASM_BX	366	pop %_ASM_BX
212		367
213	#ifdef CONFIG_X86_64	368	#ifdef CONFIG_X86_64
@@ -222,6 +377,9 @@ SYM_FUNC_START(__svm_sev_es_vcpu_run) · 8 unmodified lines
222	pop %_ASM_BP	377	pop %_ASM_BP
223	RET	378	RET
224		379
		380	RESTORE_GUEST_SPEC_CTRL_BODY
		381	RESTORE_HOST_SPEC_CTRL_BODY
		382
225	3: cmpb $0, kvm_rebooting	383	3: cmpb $0, kvm_rebooting
226	jne 2b	384	jne 2b
227	ud2	385	ud2

arch/x86/kvm/vmx/pmu_intel.c+2−2

@@ -617,7 +617,7 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) · 616 unmodified lines
617	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);	617	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
618	struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);	618	struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
619		619
620	for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {	620	for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) {
621	pmu->gp_counters[i].type = KVM_PMC_GP;	621	pmu->gp_counters[i].type = KVM_PMC_GP;
622	pmu->gp_counters[i].vcpu = vcpu;	622	pmu->gp_counters[i].vcpu = vcpu;
623	pmu->gp_counters[i].idx = i;	623	pmu->gp_counters[i].idx = i;
@@ -643,7 +643,7 @@ static void intel_pmu_reset(struct kvm_vcpu *vcpu) · 19 unmodified lines
643	struct kvm_pmc *pmc = NULL;	643	struct kvm_pmc *pmc = NULL;
644	int i;	644	int i;
645		645
646	for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {	646	for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) {
647	pmc = &pmu->gp_counters[i];	647	pmc = &pmu->gp_counters[i];
648		648
649	pmc_stop_counter(pmc);	649	pmc_stop_counter(pmc);

arch/x86/kvm/vmx/vmenter.S+1−1

 /* SPDX-License-Identifier: GPL-2.0 */
 #include <linux/linkage.h>
 #include <asm/asm.h>
-#include <asm/asm-offsets.h>
 #include <asm/bitsperlong.h>
 #include <asm/kvm_vcpu_regs.h>
 #include <asm/nospec-branch.h>
 #include <asm/percpu.h>
 #include <asm/segment.h>
+#include "kvm-asm-offsets.h"
 #include "run_flags.h"
 #define WORD_SIZE (BITS_PER_LONG / 8)

arch/x86/kvm/x86.c+10−15

 	MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
 	MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
 	MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
+	MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
+	/* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
 	MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
 	MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
 	MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
 	MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
-	MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
-	MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
-	MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
-	MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
-	MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
 	MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
 	MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
 	MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
 	MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
-	MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
-	MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
-	MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
-	MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
-	MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
-	MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
 	MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
 	MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
+	/* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
 	MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
 	MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
 	MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
 	MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
 	MSR_IA32_XFD, MSR_IA32_XFD_ERR,
 };
 				intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
 				continue;
 			break;
-		case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
+		case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
 			if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
-			    min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
+			    min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
 				continue;
 			break;
-		case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
+		case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
 			if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
-			    min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
+			    min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
 				continue;
 			break;
 		case MSR_IA32_XFD:

arch/x86/lib/usercopy.c+3−0

 #include <linux/uaccess.h>
 #include <linux/export.h>
+#include <linux/instrumented.h>
 #include <asm/tlbflush.h>
 	 * called from other contexts.
 	 */
 	pagefault_disable();
+	instrument_copy_from_user_before(to, from, n);
 	ret = raw_copy_from_user(to, from, n);
+	instrument_copy_from_user_after(to, from, n, ret);
 	pagefault_enable();
 	return ret;

arch/x86/mm/hugetlbpage.c+4−0

  */
 int pud_huge(pud_t pud)
 {
+#if CONFIG_PGTABLE_LEVELS > 2
 	return !pud_none(pud) &&
 		(pud_val(pud) & (_PAGE_PRESENT|_PAGE_PSE)) != _PAGE_PRESENT;
+#else
+	return 0;
+#endif
 }
 #ifdef CONFIG_HUGETLB_PAGE

block/bfq-cgroup.c+4−0

 	struct bfq_group *bfqg;
 	while (blkg) {
+		if (!blkg->online) {
+			blkg = blkg->parent;
+			continue;
+		}
 		bfqg = blkg_to_bfqg(blkg);
 		if (bfqg->online) {
 			bio_associate_blkg_from_css(bio, &blkg->blkcg->css);

block/sed-opal.c+28−4

 	u64 lowest_lba;
 	size_t pos;
-	u8 cmd[IO_BUFFER_LENGTH];
+	u8 *cmd;
-	u8 resp[IO_BUFFER_LENGTH];
+	u8 *resp;
 	struct parsed_resp parsed;
 	size_t prev_d_len;
 		return;
 	clean_opal_dev(dev);
+	kfree(dev->resp);
+	kfree(dev->cmd);
 	kfree(dev);
 }
 EXPORT_SYMBOL(free_opal_dev);
 	if (!dev)
 		return NULL;
+	/*
+	 * Presumably DMA-able buffers must be cache-aligned. Kmalloc makes
+	 * sure the allocated buffer is DMA-safe in that regard.
+	 */
+	dev->cmd = kmalloc(IO_BUFFER_LENGTH, GFP_KERNEL);
+	if (!dev->cmd)
+		goto err_free_dev;
+	dev->resp = kmalloc(IO_BUFFER_LENGTH, GFP_KERNEL);
+	if (!dev->resp)
+		goto err_free_cmd;
 	INIT_LIST_HEAD(&dev->unlk_lst);
 	mutex_init(&dev->dev_lock);
 	dev->flags = 0;
 	dev->send_recv = send_recv;
 	if (check_opal_support(dev) != 0) {
 		pr_debug("Opal is not supported on this device\n");
-		kfree(dev);
+		goto err_free_resp;
-		return NULL;
 	}
 	return dev;
+err_free_resp:
+	kfree(dev->resp);
+err_free_cmd:
+	kfree(dev->cmd);
+err_free_dev:
+	kfree(dev);
+	return NULL;
 }
 EXPORT_SYMBOL(init_opal_dev);

drivers/acpi/video_detect.c+32−9

 		},
 	},
+	/*
+	 * Models which have nvidia-ec-wmi support, but should not use it.
+	 * Note this indicates a likely firmware bug on these models and should
+	 * be revisited if/when Linux gets support for dynamic mux mode.
+	 */
+	{
+	 .callback = video_detect_force_native,
+	 /* Dell G15 5515 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Dell G15 5515"),
+		},
+	},
 	/*
 	 * Desktops which falsely report a backlight and which our heuristics
 	 * for this do not catch.
 static bool google_cros_ec_present(void)
 {
-	return acpi_dev_found("GOOG0004");
+	return acpi_dev_found("GOOG0004") || acpi_dev_found("GOOG000C");
 }
 /*
 	if (apple_gmux_present())
 		return acpi_backlight_apple_gmux;
+	/* Chromebooks should always prefer native backlight control. */
+	if (google_cros_ec_present() && native_available)
+		return acpi_backlight_native;
 	/* On systems with ACPI video use either native or ACPI video. */
 	if (video_caps & ACPI_VIDEO_BACKLIGHT) {
 		/*
 			return acpi_backlight_video;
 	}
-	/*
-	 * Chromebooks that don't have backlight handle in ACPI table
-	 * are supposed to use native backlight if it's available.
-	 */
-	if (google_cros_ec_present() && native_available)
-		return acpi_backlight_native;
 	/* No ACPI video (old hw), use vendor specific fw methods. */
 	return acpi_backlight_vendor;
 }
 bool acpi_video_backlight_use_native(void)
 {
-	return __acpi_video_get_backlight_type(true) == acpi_backlight_native;
+	/*
+	 * Call __acpi_video_get_backlight_type() to let it know that
+	 * a native backlight is available.
+	 */
+	__acpi_video_get_backlight_type(true);
+	/*
+	 * For now just always return true. There is a whole bunch of laptop
+	 * models where (video_caps & ACPI_VIDEO_BACKLIGHT) is false causing
+	 * __acpi_video_get_backlight_type() to return vendor, while these
+	 * models only have a native backlight control.
+	 */
+	return true;
 }
 EXPORT_SYMBOL(acpi_video_backlight_use_native);

drivers/ata/libata-scsi.c+13−0

 	case REPORT_LUNS:
 	case REQUEST_SENSE:
 	case SYNCHRONIZE_CACHE:
+	case SYNCHRONIZE_CACHE_16:
 	case REZERO_UNIT:
 	case SEEK_6:
 	case SEEK_10:
 		return ata_scsi_write_same_xlat;
 	case SYNCHRONIZE_CACHE:
+	case SYNCHRONIZE_CACHE_16:
 		if (ata_try_flush_cache(dev))
 			return ata_scsi_flush_xlat;
 		break;
 int __ata_scsi_queuecmd(struct scsi_cmnd *scmd, struct ata_device *dev)
 {
+	struct ata_port *ap = dev->link->ap;
 	u8 scsi_op = scmd->cmnd[0];
 	ata_xlat_func_t xlat_func;
+	/*
+	 * scsi_queue_rq() will defer commands if scsi_host_in_recovery().
+	 * However, this check is done without holding the ap->lock (a libata
+	 * specific lock), so we can have received an error irq since then,
+	 * therefore we must check if EH is pending, while holding ap->lock.
+	 */
+	if (ap->pflags & (ATA_PFLAG_EH_PENDING | ATA_PFLAG_EH_IN_PROGRESS))
+		return SCSI_MLQUEUE_DEVICE_BUSY;
 	if (unlikely(!scmd->cmd_len))
 		goto bad_cdb_len;
 	 * turning this into a no-op.
 	 */
 	case SYNCHRONIZE_CACHE:
+	case SYNCHRONIZE_CACHE_16:
 		fallthrough;
 	/* no-op's, complete with success */

drivers/ata/libata-transport.c+15−4

 	pm_runtime_enable(dev);
 	pm_runtime_forbid(dev);
-	transport_add_device(dev);
+	error = transport_add_device(dev);
+	if (error)
+		goto tport_transport_add_err;
 	transport_configure_device(dev);
 	error = ata_tlink_add(&ap->link);
  tport_link_err:
 	transport_remove_device(dev);
+ tport_transport_add_err:
 	device_del(dev);
  tport_err:
 	transport_destroy_device(dev);
 	put_device(dev);
-	ata_host_put(ap->host);
 	return error;
 }
 		goto tlink_err;
 	}
-	transport_add_device(dev);
+	error = transport_add_device(dev);
+	if (error)
+		goto tlink_transport_err;
 	transport_configure_device(dev);
 	ata_for_each_dev(ata_dev, link, ALL) {
 		ata_tdev_delete(ata_dev);
 	}
 	transport_remove_device(dev);
+  tlink_transport_err:
 	device_del(dev);
   tlink_err:
 	transport_destroy_device(dev);
 		return error;
 	}
-	transport_add_device(dev);
+	error = transport_add_device(dev);
+	if (error) {
+		device_del(dev);
+		ata_tdev_free(ata_dev);
+		return error;
+	}
 	transport_configure_device(dev);
 	return 0;
 }

drivers/clocksource/hyperv_timer.c+15−14

 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/acpi.h>
+#include <linux/hyperv.h>
 #include <clocksource/hyperv_timer.h>
 #include <asm/hyperv-tlfs.h>
 #include <asm/mshyperv.h>
 static void suspend_hv_clock_tsc(struct clocksource *arg)
 {
-	u64 tsc_msr;
+	union hv_reference_tsc_msr tsc_msr;
 	/* Disable the TSC page */
-	tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC);
+	tsc_msr.as_uint64 = hv_get_register(HV_REGISTER_REFERENCE_TSC);
-	tsc_msr &= ~BIT_ULL(0);
+	tsc_msr.enable = 0;
-	hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr);
+	hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64);
 }
 static void resume_hv_clock_tsc(struct clocksource *arg)
 {
 	phys_addr_t phys_addr = virt_to_phys(&tsc_pg);
-	u64 tsc_msr;
+	union hv_reference_tsc_msr tsc_msr;
 	/* Re-enable the TSC page */
-	tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC);
+	tsc_msr.as_uint64 = hv_get_register(HV_REGISTER_REFERENCE_TSC);
-	tsc_msr &= GENMASK_ULL(11, 0);
+	tsc_msr.enable = 1;
-	tsc_msr |= BIT_ULL(0) | (u64)phys_addr;
+	tsc_msr.pfn = HVPFN_DOWN(phys_addr);
-	hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr);
+	hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64);
 }
 #ifdef HAVE_VDSO_CLOCKMODE_HVCLOCK
 static bool __init hv_init_tsc_clocksource(void)
 {
-	u64		tsc_msr;
+	union hv_reference_tsc_msr tsc_msr;
 	phys_addr_t	phys_addr;
 	if (!(ms_hyperv.features & HV_MSR_REFERENCE_TSC_AVAILABLE))
 	 * (which already has at least the low 12 bits set to zero since
 	 * it is page aligned). Also set the "enable" bit, which is bit 0.
 	 */
-	tsc_msr = hv_get_register(HV_REGISTER_REFERENCE_TSC);
+	tsc_msr.as_uint64 = hv_get_register(HV_REGISTER_REFERENCE_TSC);
-	tsc_msr &= GENMASK_ULL(11, 0);
+	tsc_msr.enable = 1;
-	tsc_msr = tsc_msr | 0x1 | (u64)phys_addr;
+	tsc_msr.pfn = HVPFN_DOWN(phys_addr);
-	hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr);
+	hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64);
 	clocksource_register_hz(&hyperv_cs_tsc, NSEC_PER_SEC/100);

drivers/dma/apple-admac.c+1−1

@@ -493,7 +493,7 @@ static struct dma_chan admac_dma_of_xlate(struct of_phandle_args dma_spec, · 492 unmodified lines
493	return NULL;	493	return NULL;
494	}	494	}
495		495
496	return &ad->channels[index].chan;	496	return dma_get_slave_channel(&ad->channels[index].chan);
497	}	497	}
498		498
499	static int admac_drain_reports(struct admac_data *ad, int channo)	499	static int admac_drain_reports(struct admac_data *ad, int channo)

drivers/dma/at_hdmac.c+60−93

@@ -256,6 +256,8 @@ static void atc_dostart(struct at_dma_chan atchan, struct at_desc first) · 255 unmodified lines
256	ATC_SPIP_BOUNDARY(first->boundary));	256	ATC_SPIP_BOUNDARY(first->boundary));
257	channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) \|	257	channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) \|
258	ATC_DPIP_BOUNDARY(first->boundary));	258	ATC_DPIP_BOUNDARY(first->boundary));
		259	/* Don't allow CPU to reorder channel enable. */
		260	wmb();
259	dma_writel(atdma, CHER, atchan->mask);	261	dma_writel(atdma, CHER, atchan->mask);
260		262
261	vdbg_dump_regs(atchan);	263	vdbg_dump_regs(atchan);
@@ -316,7 +318,8 @@ static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie) · 54 unmodified lines
316	struct at_desc *desc_first = atc_first_active(atchan);	318	struct at_desc *desc_first = atc_first_active(atchan);
317	struct at_desc *desc;	319	struct at_desc *desc;
318	int ret;	320	int ret;
319	u32 ctrla, dscr, trials;	321	u32 ctrla, dscr;
		322	unsigned int i;
320		323
321	/*	324	/*
322	* If the cookie doesn't match to the currently running transfer then	325	* If the cookie doesn't match to the currently running transfer then
@@ -386,7 +389,7 @@ static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie) · 63 unmodified lines
386	dscr = channel_readl(atchan, DSCR);	389	dscr = channel_readl(atchan, DSCR);
387	rmb(); /* ensure DSCR is read before CTRLA */	390	rmb(); /* ensure DSCR is read before CTRLA */
388	ctrla = channel_readl(atchan, CTRLA);	391	ctrla = channel_readl(atchan, CTRLA);
389	for (trials = 0; trials < ATC_MAX_DSCR_TRIALS; ++trials) {	392	for (i = 0; i < ATC_MAX_DSCR_TRIALS; ++i) {
390	u32 new_dscr;	393	u32 new_dscr;
391		394
392	rmb(); /* ensure DSCR is read after CTRLA */	395	rmb(); /* ensure DSCR is read after CTRLA */
@@ -412,7 +415,7 @@ static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie) · 19 unmodified lines
412	rmb(); /* ensure DSCR is read before CTRLA */	415	rmb(); /* ensure DSCR is read before CTRLA */
413	ctrla = channel_readl(atchan, CTRLA);	416	ctrla = channel_readl(atchan, CTRLA);
414	}	417	}
415	if (unlikely(trials >= ATC_MAX_DSCR_TRIALS))	418	if (unlikely(i == ATC_MAX_DSCR_TRIALS))
416	return -ETIMEDOUT;	419	return -ETIMEDOUT;
417		420
418	/* for the first descriptor we can be more accurate */	421	/* for the first descriptor we can be more accurate */
@@ -462,18 +465,6 @@ atc_chain_complete(struct at_dma_chan atchan, struct at_desc desc) · 43 unmodified lines
462	if (!atc_chan_is_cyclic(atchan))	465	if (!atc_chan_is_cyclic(atchan))
463	dma_cookie_complete(txd);	466	dma_cookie_complete(txd);
464		467
465	/* If the transfer was a memset, free our temporary buffer */
466	if (desc->memset_buffer) {
467	dma_pool_free(atdma->memset_pool, desc->memset_vaddr,
468	desc->memset_paddr);
469	desc->memset_buffer = false;
470	}
471
472	/* move children to free_list */
473	list_splice_init(&desc->tx_list, &atchan->free_list);
474	/* move myself to free_list */
475	list_move(&desc->desc_node, &atchan->free_list);
476
477	spin_unlock_irqrestore(&atchan->lock, flags);	468	spin_unlock_irqrestore(&atchan->lock, flags);
478		469
479	dma_descriptor_unmap(txd);	470	dma_descriptor_unmap(txd);
@@ -483,42 +474,20 @@ atc_chain_complete(struct at_dma_chan atchan, struct at_desc desc) · 3 unmodified lines
483	dmaengine_desc_get_callback_invoke(txd, NULL);	474	dmaengine_desc_get_callback_invoke(txd, NULL);
484		475
485	dma_run_dependencies(txd);	476	dma_run_dependencies(txd);
486	}
487
488	/**
489	* atc_complete_all - finish work for all transactions
490	* @atchan: channel to complete transactions for
491	*
492	* Eventually submit queued descriptors if any
493	*
494	* Assume channel is idle while calling this function
495	* Called with atchan->lock held and bh disabled
496	*/
497	static void atc_complete_all(struct at_dma_chan *atchan)
498	{
499	struct at_desc desc, _desc;
500	LIST_HEAD(list);
501	unsigned long flags;
502
503	dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
504		477
505	spin_lock_irqsave(&atchan->lock, flags);	478	spin_lock_irqsave(&atchan->lock, flags);
506		479	/* move children to free_list */
507	/*	480	list_splice_init(&desc->tx_list, &atchan->free_list);
508	* Submit queued descriptors ASAP, i.e. before we go through	481	/* add myself to free_list */
509	* the completed ones.	482	list_add(&desc->desc_node, &atchan->free_list);
510	*/
511	if (!list_empty(&atchan->queue))
512	atc_dostart(atchan, atc_first_queued(atchan));
513	/* empty active_list now it is completed */
514	list_splice_init(&atchan->active_list, &list);
515	/* empty queue list by moving descriptors (if any) to active_list */
516	list_splice_init(&atchan->queue, &atchan->active_list);
517
518	spin_unlock_irqrestore(&atchan->lock, flags);	483	spin_unlock_irqrestore(&atchan->lock, flags);
519		484
520	list_for_each_entry_safe(desc, _desc, &list, desc_node)	485	/* If the transfer was a memset, free our temporary buffer */
521	atc_chain_complete(atchan, desc);	486	if (desc->memset_buffer) {
		487	dma_pool_free(atdma->memset_pool, desc->memset_vaddr,
		488	desc->memset_paddr);
		489	desc->memset_buffer = false;
		490	}
522	}	491	}
523		492
524	/**	493	/**
@@ -527,26 +496,28 @@ static void atc_complete_all(struct at_dma_chan *atchan) · 2 unmodified lines
527	*/	496	*/
528	static void atc_advance_work(struct at_dma_chan *atchan)	497	static void atc_advance_work(struct at_dma_chan *atchan)
529	{	498	{
		499	struct at_desc *desc;
530	unsigned long flags;	500	unsigned long flags;
531	int ret;
532		501
533	dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");	502	dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
534		503
535	spin_lock_irqsave(&atchan->lock, flags);	504	spin_lock_irqsave(&atchan->lock, flags);
536	ret = atc_chan_is_enabled(atchan);	505	if (atc_chan_is_enabled(atchan) \|\| list_empty(&atchan->active_list))
537	spin_unlock_irqrestore(&atchan->lock, flags);	506	return spin_unlock_irqrestore(&atchan->lock, flags);
538	if (ret)
539	return;
540
541	if (list_empty(&atchan->active_list) \|\|
542	list_is_singular(&atchan->active_list))
543	return atc_complete_all(atchan);
544		507
545	atc_chain_complete(atchan, atc_first_active(atchan));	508	desc = atc_first_active(atchan);
		509	/* Remove the transfer node from the active list. */
		510	list_del_init(&desc->desc_node);
		511	spin_unlock_irqrestore(&atchan->lock, flags);
		512	atc_chain_complete(atchan, desc);
546		513
547	/* advance work */	514	/* advance work */
548	spin_lock_irqsave(&atchan->lock, flags);	515	spin_lock_irqsave(&atchan->lock, flags);
549	atc_dostart(atchan, atc_first_active(atchan));	516	if (!list_empty(&atchan->active_list)) {
		517	desc = atc_first_queued(atchan);
		518	list_move_tail(&desc->desc_node, &atchan->active_list);
		519	atc_dostart(atchan, desc);
		520	}
550	spin_unlock_irqrestore(&atchan->lock, flags);	521	spin_unlock_irqrestore(&atchan->lock, flags);
551	}	522	}
552		523
@@ -558,6 +529,7 @@ static void atc_advance_work(struct at_dma_chan *atchan) · 5 unmodified lines
558	static void atc_handle_error(struct at_dma_chan *atchan)	529	static void atc_handle_error(struct at_dma_chan *atchan)
559	{	530	{
560	struct at_desc *bad_desc;	531	struct at_desc *bad_desc;
		532	struct at_desc *desc;
561	struct at_desc *child;	533	struct at_desc *child;
562	unsigned long flags;	534	unsigned long flags;
563		535
@@ -570,13 +542,12 @@ static void atc_handle_error(struct at_dma_chan *atchan) · 6 unmodified lines
570	bad_desc = atc_first_active(atchan);	542	bad_desc = atc_first_active(atchan);
571	list_del_init(&bad_desc->desc_node);	543	list_del_init(&bad_desc->desc_node);
572		544
573	/* As we are stopped, take advantage to push queued descriptors
574	* in active_list */
575	list_splice_init(&atchan->queue, atchan->active_list.prev);
576
577	/* Try to restart the controller */	545	/* Try to restart the controller */
578	if (!list_empty(&atchan->active_list))	546	if (!list_empty(&atchan->active_list)) {
579	atc_dostart(atchan, atc_first_active(atchan));	547	desc = atc_first_queued(atchan);
		548	list_move_tail(&desc->desc_node, &atchan->active_list);
		549	atc_dostart(atchan, desc);
		550	}
580		551
581	/*	552	/*
582	* KERN_CRITICAL may seem harsh, but since this only happens	553	* KERN_CRITICAL may seem harsh, but since this only happens
@@ -691,19 +662,11 @@ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) · 108 unmodified lines
691	spin_lock_irqsave(&atchan->lock, flags);	662	spin_lock_irqsave(&atchan->lock, flags);
692	cookie = dma_cookie_assign(tx);	663	cookie = dma_cookie_assign(tx);
693		664
694	if (list_empty(&atchan->active_list)) {	665	list_add_tail(&desc->desc_node, &atchan->queue);
695	dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
696	desc->txd.cookie);
697	atc_dostart(atchan, desc);
698	list_add_tail(&desc->desc_node, &atchan->active_list);
699	} else {
700	dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
701	desc->txd.cookie);
702	list_add_tail(&desc->desc_node, &atchan->queue);
703	}
704
705	spin_unlock_irqrestore(&atchan->lock, flags);	666	spin_unlock_irqrestore(&atchan->lock, flags);
706		667
		668	dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
		669	desc->txd.cookie);
707	return cookie;	670	return cookie;
708	}	671	}
709		672
@@ -1445,11 +1408,8 @@ static int atc_terminate_all(struct dma_chan *chan) · 735 unmodified lines
1445	struct at_dma_chan *atchan = to_at_dma_chan(chan);	1408	struct at_dma_chan *atchan = to_at_dma_chan(chan);
1446	struct at_dma *atdma = to_at_dma(chan->device);	1409	struct at_dma *atdma = to_at_dma(chan->device);
1447	int chan_id = atchan->chan_common.chan_id;	1410	int chan_id = atchan->chan_common.chan_id;
1448	struct at_desc desc, _desc;
1449	unsigned long flags;	1411	unsigned long flags;
1450		1412
1451	LIST_HEAD(list);
1452
1453	dev_vdbg(chan2dev(chan), "%s\n", __func__);	1413	dev_vdbg(chan2dev(chan), "%s\n", __func__);
1454		1414
1455	/*	1415	/*
@@ -1468,19 +1428,15 @@ static int atc_terminate_all(struct dma_chan *chan) · 12 unmodified lines
1468	cpu_relax();	1428	cpu_relax();
1469		1429
1470	/* active_list entries will end up before queued entries */	1430	/* active_list entries will end up before queued entries */
1471	list_splice_init(&atchan->queue, &list);	1431	list_splice_tail_init(&atchan->queue, &atchan->free_list);
1472	list_splice_init(&atchan->active_list, &list);	1432	list_splice_tail_init(&atchan->active_list, &atchan->free_list);
1473
1474	spin_unlock_irqrestore(&atchan->lock, flags);
1475
1476	/* Flush all pending and queued descriptors */
1477	list_for_each_entry_safe(desc, _desc, &list, desc_node)
1478	atc_chain_complete(atchan, desc);
1479		1433
1480	clear_bit(ATC_IS_PAUSED, &atchan->status);	1434	clear_bit(ATC_IS_PAUSED, &atchan->status);
1481	/* if channel dedicated to cyclic operations, free it */	1435	/* if channel dedicated to cyclic operations, free it */
1482	clear_bit(ATC_IS_CYCLIC, &atchan->status);	1436	clear_bit(ATC_IS_CYCLIC, &atchan->status);
1483		1437
		1438	spin_unlock_irqrestore(&atchan->lock, flags);
		1439
1484	return 0;	1440	return 0;
1485	}	1441	}
1486		1442
@@ -1535,20 +1491,26 @@ atc_tx_status(struct dma_chan *chan, · 48 unmodified lines
1535	}	1491	}
1536		1492
1537	/**	1493	/**
1538	* atc_issue_pending - try to finish work	1494	* atc_issue_pending - takes the first transaction descriptor in the pending
		1495	* queue and starts the transfer.
1539	* @chan: target DMA channel	1496	* @chan: target DMA channel
1540	*/	1497	*/
1541	static void atc_issue_pending(struct dma_chan *chan)	1498	static void atc_issue_pending(struct dma_chan *chan)
1542	{	1499	{
1543	struct at_dma_chan *atchan = to_at_dma_chan(chan);	1500	struct at_dma_chan *atchan = to_at_dma_chan(chan);
		1501	struct at_desc *desc;
		1502	unsigned long flags;
1544		1503
1545	dev_vdbg(chan2dev(chan), "issue_pending\n");	1504	dev_vdbg(chan2dev(chan), "issue_pending\n");
1546		1505
1547	/* Not needed for cyclic transfers */	1506	spin_lock_irqsave(&atchan->lock, flags);
1548	if (atc_chan_is_cyclic(atchan))	1507	if (atc_chan_is_enabled(atchan) \|\| list_empty(&atchan->queue))
1549	return;	1508	return spin_unlock_irqrestore(&atchan->lock, flags);
1550		1509
1551	atc_advance_work(atchan);	1510	desc = atc_first_queued(atchan);
		1511	list_move_tail(&desc->desc_node, &atchan->active_list);
		1512	atc_dostart(atchan, desc);
		1513	spin_unlock_irqrestore(&atchan->lock, flags);
1552	}	1514	}
1553		1515
1554	/**	1516	/**
@@ -1966,7 +1928,11 @@ static int __init at_dma_probe(struct platform_device *pdev) · 411 unmodified lines
1966	dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",	1928	dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
1967	plat_dat->nr_channels);	1929	plat_dat->nr_channels);
1968		1930
1969	dma_async_device_register(&atdma->dma_common);	1931	err = dma_async_device_register(&atdma->dma_common);
		1932	if (err) {
		1933	dev_err(&pdev->dev, "Unable to register: %d.\n", err);
		1934	goto err_dma_async_device_register;
		1935	}
1970		1936
1971	/*	1937	/*
1972	* Do not return an error if the dmac node is not present in order to	1938	* Do not return an error if the dmac node is not present in order to
@@ -1986,6 +1952,7 @@ static int __init at_dma_probe(struct platform_device *pdev) · 13 unmodified lines
1986		1952
1987	err_of_dma_controller_register:	1953	err_of_dma_controller_register:
1988	dma_async_device_unregister(&atdma->dma_common);	1954	dma_async_device_unregister(&atdma->dma_common);
		1955	err_dma_async_device_register:
1989	dma_pool_destroy(atdma->memset_pool);	1956	dma_pool_destroy(atdma->memset_pool);
1990	err_memset_pool_create:	1957	err_memset_pool_create:
1991	dma_pool_destroy(atdma->dma_desc_pool);	1958	dma_pool_destroy(atdma->dma_desc_pool);

drivers/dma/at_hdmac_regs.h+5−5

@@ -186,13 +186,13 @@ · 185 unmodified lines
186	/* LLI == Linked List Item; aka DMA buffer descriptor */	186	/* LLI == Linked List Item; aka DMA buffer descriptor */
187	struct at_lli {	187	struct at_lli {
188	/* values that are not changed by hardware */	188	/* values that are not changed by hardware */
189	dma_addr_t saddr;	189	u32 saddr;
190	dma_addr_t daddr;	190	u32 daddr;
191	/* value that may get written back: */	191	/* value that may get written back: */
192	u32 ctrla;	192	u32 ctrla;
193	/* more values that are not changed by hardware */	193	/* more values that are not changed by hardware */
194	u32 ctrlb;	194	u32 ctrlb;
195	dma_addr_t dscr; /* chain to next lli */	195	u32 dscr; /* chain to next lli */
196	};	196	};
197		197
198	/**	198	/**

drivers/dma/idxd/cdev.c+18−0

@@ -312,6 +312,24 @@ static int idxd_user_drv_probe(struct idxd_dev *idxd_dev) · 311 unmodified lines
312	if (idxd->state != IDXD_DEV_ENABLED)	312	if (idxd->state != IDXD_DEV_ENABLED)
313	return -ENXIO;	313	return -ENXIO;
314		314
		315	/*
		316	* User type WQ is enabled only when SVA is enabled for two reasons:
		317	* - If no IOMMU or IOMMU Passthrough without SVA, userspace
		318	* can directly access physical address through the WQ.
		319	* - The IDXD cdev driver does not provide any ways to pin
		320	* user pages and translate the address from user VA to IOVA or
		321	* PA without IOMMU SVA. Therefore the application has no way
		322	* to instruct the device to perform DMA function. This makes
		323	* the cdev not usable for normal application usage.
		324	*/
		325	if (!device_user_pasid_enabled(idxd)) {
		326	idxd->cmd_status = IDXD_SCMD_WQ_USER_NO_IOMMU;
		327	dev_dbg(&idxd->pdev->dev,
		328	"User type WQ cannot be enabled without SVA.\n");
		329
		330	return -EOPNOTSUPP;
		331	}
		332
315	mutex_lock(&wq->wq_lock);	333	mutex_lock(&wq->wq_lock);
316	wq->type = IDXD_WQT_USER;	334	wq->type = IDXD_WQT_USER;
317	rc = drv_enable_wq(wq);	335	rc = drv_enable_wq(wq);

drivers/dma/idxd/device.c+17−9

 	clear_bit(WQ_FLAG_ATS_DISABLE, &wq->flags);
 	memset(wq->name, 0, WQ_NAME_SIZE);
 	wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
-	wq->max_batch_size = WQ_DEFAULT_MAX_BATCH;
+	idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
 	if (wq->opcap_bmap)
 		bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS);
 }
 void idxd_device_clear_state(struct idxd_device *idxd)
 {
-	if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
+	/* IDXD is always disabled. Other states are cleared only when IDXD is configurable. */
-		return;
+	if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
+		/*
+		 * Clearing wq state is protected by wq lock.
+		 * So no need to be protected by device lock.
+		 */
+		idxd_device_wqs_clear_state(idxd);
+		spin_lock(&idxd->dev_lock);
+		idxd_groups_clear_state(idxd);
+		idxd_engines_clear_state(idxd);
+	} else {
+		spin_lock(&idxd->dev_lock);
+	}
-	idxd_device_wqs_clear_state(idxd);
-	spin_lock(&idxd->dev_lock);
-	idxd_groups_clear_state(idxd);
-	idxd_engines_clear_state(idxd);
 	idxd->state = IDXD_DEV_DISABLED;
 	spin_unlock(&idxd->dev_lock);
 }
 	/* bytes 12-15 */
 	wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
-	wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size);
+	idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max_batch_size));
 	/* bytes 32-63 */
 	if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) {
 	wq->priority = wq->wqcfg->priority;
 	wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift;
-	wq->max_batch_size = 1ULL << wq->wqcfg->max_batch_shift;
+	idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_batch_shift);
 	for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
 		wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);

drivers/dma/idxd/idxd.h+32−0

@@ -548,6 +548,38 @@ static inline int idxd_wq_refcount(struct idxd_wq *wq) · 547 unmodified lines
548	return wq->client_count;	548	return wq->client_count;
549	};	549	};
550		550
		551	/*
		552	* Intel IAA does not support batch processing.
		553	* The max batch size of device, max batch size of wq and
		554	* max batch shift of wqcfg should be always 0 on IAA.
		555	*/
		556	static inline void idxd_set_max_batch_size(int idxd_type, struct idxd_device *idxd,
		557	u32 max_batch_size)
		558	{
		559	if (idxd_type == IDXD_TYPE_IAX)
		560	idxd->max_batch_size = 0;
		561	else
		562	idxd->max_batch_size = max_batch_size;
		563	}
		564
		565	static inline void idxd_wq_set_max_batch_size(int idxd_type, struct idxd_wq *wq,
		566	u32 max_batch_size)
		567	{
		568	if (idxd_type == IDXD_TYPE_IAX)
		569	wq->max_batch_size = 0;
		570	else
		571	wq->max_batch_size = max_batch_size;
		572	}
		573
		574	static inline void idxd_wqcfg_set_max_batch_shift(int idxd_type, union wqcfg *wqcfg,
		575	u32 max_batch_shift)
		576	{
		577	if (idxd_type == IDXD_TYPE_IAX)
		578	wqcfg->max_batch_shift = 0;
		579	else
		580	wqcfg->max_batch_shift = max_batch_shift;
		581	}
		582
551	int __must_check __idxd_driver_register(struct idxd_device_driver *idxd_drv,	583	int __must_check __idxd_driver_register(struct idxd_device_driver *idxd_drv,
552	struct module module, const char mod_name);	584	struct module module, const char mod_name);
553	#define idxd_driver_register(driver) \	585	#define idxd_driver_register(driver) \

drivers/dma/idxd/init.c+2−2

drivers/dma/idxd/sysfs.c+1−1

@@ -1046,7 +1046,7 @@ static ssize_t wq_max_batch_size_store(struct device *dev, struct device_attribu · 1045 unmodified lines
1046	if (batch_size > idxd->max_batch_size)	1046	if (batch_size > idxd->max_batch_size)
1047	return -EINVAL;	1047	return -EINVAL;
1048		1048
1049	wq->max_batch_size = (u32)batch_size;	1049	idxd_wq_set_max_batch_size(idxd->data->type, wq, (u32)batch_size);
1050		1050
1051	return count;	1051	return count;
1052	}	1052	}

drivers/dma/mv_xor_v2.c+1−0

@@ -893,6 +893,7 @@ static int mv_xor_v2_remove(struct platform_device *pdev) · 892 unmodified lines
893	tasklet_kill(&xor_dev->irq_tasklet);	893	tasklet_kill(&xor_dev->irq_tasklet);
894		894
895	clk_disable_unprepare(xor_dev->clk);	895	clk_disable_unprepare(xor_dev->clk);
		896	clk_disable_unprepare(xor_dev->reg_clk);
896		897
897	return 0;	898	return 0;
898	}	899	}

drivers/dma/pxa_dma.c+2−2

@@ -1247,14 +1247,14 @@ static int pxad_init_phys(struct platform_device *op, · 1246 unmodified lines
1247	return -ENOMEM;	1247	return -ENOMEM;
1248		1248
1249	for (i = 0; i < nb_phy_chans; i++)	1249	for (i = 0; i < nb_phy_chans; i++)
1250	if (platform_get_irq(op, i) > 0)	1250	if (platform_get_irq_optional(op, i) > 0)
1251	nr_irq++;	1251	nr_irq++;
1252		1252
1253	for (i = 0; i < nb_phy_chans; i++) {	1253	for (i = 0; i < nb_phy_chans; i++) {
1254	phy = &pdev->phys[i];	1254	phy = &pdev->phys[i];
1255	phy->base = pdev->base;	1255	phy->base = pdev->base;
1256	phy->idx = i;	1256	phy->idx = i;
1257	irq = platform_get_irq(op, i);	1257	irq = platform_get_irq_optional(op, i);
1258	if ((nr_irq > 1) && (irq > 0))	1258	if ((nr_irq > 1) && (irq > 0))
1259	ret = devm_request_irq(&op->dev, irq,	1259	ret = devm_request_irq(&op->dev, irq,
1260	pxad_chan_handler,	1260	pxad_chan_handler,

drivers/dma/stm32-dma.c+6−8

 	chan->chan_reg.dma_sndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
+	chan->status = DMA_PAUSED;
 	dev_dbg(chan2dev(chan), "vchan %pK: paused\n", &chan->vchan);
 }
 	if (status & STM32_DMA_TCI) {
 		stm32_dma_irq_clear(chan, STM32_DMA_TCI);
 		if (scr & STM32_DMA_SCR_TCIE) {
-			if (chan->status == DMA_PAUSED && !(scr & STM32_DMA_SCR_EN))
+			if (chan->status != DMA_PAUSED)
-				stm32_dma_handle_chan_paused(chan);
-			else
 				stm32_dma_handle_chan_done(chan, scr);
 		}
 		status &= ~STM32_DMA_TCI;
 		return -EPERM;
 	spin_lock_irqsave(&chan->vchan.lock, flags);
 	ret = stm32_dma_disable_chan(chan);
-	/*
-	 * A transfer complete flag is set to indicate the end of transfer due to the stream
-	 * interruption, so wait for interrupt
-	 */
 	if (!ret)
-		chan->status = DMA_PAUSED;
+		stm32_dma_handle_chan_paused(chan);
 	spin_unlock_irqrestore(&chan->vchan.lock, flags);
 	return ret;

drivers/dma/stm32-mdma.c+1−0

@@ -1539,6 +1539,7 @@ static struct dma_chan stm32_mdma_of_xlate(struct of_phandle_args dma_spec, · 1538 unmodified lines
1539	return NULL;	1539	return NULL;
1540	}	1540	}
1541		1541
		1542	memset(&config, 0, sizeof(config));
1542	config.request = dma_spec->args[0];	1543	config.request = dma_spec->args[0];
1543	config.priority_level = dma_spec->args[1];	1544	config.priority_level = dma_spec->args[1];
1544	config.transfer_config = dma_spec->args[2];	1545	config.transfer_config = dma_spec->args[2];

drivers/dma/ti/k3-udma-glue.c+3−0

 	ret = device_register(&tx_chn->common.chan_dev);
 	if (ret) {
 		dev_err(dev, "Channel Device registration failed %d\n", ret);
+		put_device(&tx_chn->common.chan_dev);
 		tx_chn->common.chan_dev.parent = NULL;
 		goto err;
 	}
 	ret = device_register(&rx_chn->common.chan_dev);
 	if (ret) {
 		dev_err(dev, "Channel Device registration failed %d\n", ret);
+		put_device(&rx_chn->common.chan_dev);
 		rx_chn->common.chan_dev.parent = NULL;
 		goto err;
 	}
 	ret = device_register(&rx_chn->common.chan_dev);
 	if (ret) {
 		dev_err(dev, "Channel Device registration failed %d\n", ret);
+		put_device(&rx_chn->common.chan_dev);
 		rx_chn->common.chan_dev.parent = NULL;
 		goto err;
 	}

drivers/firmware/efi/libstub/Makefile+1−1

@@ -82,7 +82,7 @@ $(obj)/lib-%.o: $(srctree)/lib/%.c FORCE · 81 unmodified lines
82	lib-$(CONFIG_EFI_GENERIC_STUB) += efi-stub.o string.o intrinsics.o systable.o	82	lib-$(CONFIG_EFI_GENERIC_STUB) += efi-stub.o string.o intrinsics.o systable.o
83		83
84	lib-$(CONFIG_ARM) += arm32-stub.o	84	lib-$(CONFIG_ARM) += arm32-stub.o
85	lib-$(CONFIG_ARM64) += arm64-stub.o	85	lib-$(CONFIG_ARM64) += arm64-stub.o smbios.o
86	lib-$(CONFIG_X86) += x86-stub.o	86	lib-$(CONFIG_X86) += x86-stub.o
87	lib-$(CONFIG_RISCV) += riscv-stub.o	87	lib-$(CONFIG_RISCV) += riscv-stub.o
88	lib-$(CONFIG_LOONGARCH) += loongarch-stub.o	88	lib-$(CONFIG_LOONGARCH) += loongarch-stub.o

drivers/firmware/efi/libstub/arm64-stub.c+16−1

@@ -15,6 +15,21 @@ · 14 unmodified lines
15		15
16	#include "efistub.h"	16	#include "efistub.h"
17		17
		18	static bool system_needs_vamap(void)
		19	{
		20	const u8 *type1_family = efi_get_smbios_string(1, family);
		21
		22	/*
		23	* Ampere Altra machines crash in SetTime() if SetVirtualAddressMap()
		24	* has not been called prior.
		25	*/
		26	if (!type1_family \|\| strcmp(type1_family, "Altra"))
		27	return false;
		28
		29	efi_warn("Working around broken SetVirtualAddressMap()\n");
		30	return true;
		31	}
		32
18	efi_status_t check_platform_features(void)	33	efi_status_t check_platform_features(void)
19	{	34	{
20	u64 tg;	35	u64 tg;
@@ -24,7 +39,7 @@ efi_status_t check_platform_features(void) · 3 unmodified lines
24	* UEFI runtime regions 1:1 and so calling SetVirtualAddressMap() is	39	* UEFI runtime regions 1:1 and so calling SetVirtualAddressMap() is
25	* unnecessary.	40	* unnecessary.
26	*/	41	*/
27	if (VA_BITS_MIN >= 48)	42	if (VA_BITS_MIN >= 48 && !system_needs_vamap())
28	efi_novamap = true;	43	efi_novamap = true;
29		44
30	/* UEFI mandates support for 4 KB granularity, no need to check */	45	/* UEFI mandates support for 4 KB granularity, no need to check */

drivers/firmware/efi/libstub/efistub.h+28−0

@@ -975,4 +975,32 @@ efi_enable_reset_attack_mitigation(void) { } · 974 unmodified lines
975		975
976	void efi_retrieve_tpm2_eventlog(void);	976	void efi_retrieve_tpm2_eventlog(void);
977		977
		978	struct efi_smbios_record {
		979	u8 type;
		980	u8 length;
		981	u16 handle;
		982	};
		983
		984	struct efi_smbios_type1_record {
		985	struct efi_smbios_record header;
		986
		987	u8 manufacturer;
		988	u8 product_name;
		989	u8 version;
		990	u8 serial_number;
		991	efi_guid_t uuid;
		992	u8 wakeup_type;
		993	u8 sku_number;
		994	u8 family;
		995	};
		996
		997	#define efi_get_smbios_string(__type, __name) ({ \
		998	int size = sizeof(struct efi_smbios_type ## __type ## _record); \
		999	int off = offsetof(struct efi_smbios_type ## __type ## _record, \
		1000	__name); \
		1001	__efi_get_smbios_string(__type, off, size); \
		1002	})
		1003
		1004	const u8 *__efi_get_smbios_string(u8 type, int offset, int recsize);
		1005
978	#endif	1006	#endif

drivers/firmware/efi/libstub/smbios.c+48−0

@@ -0,0 +1,48 @@
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	// Copyright 2022 Google LLC
	3	// Author: Ard Biesheuvel <ardb@google.com>
	4
	5	#include <linux/efi.h>
	6
	7	#include "efistub.h"
	8
	9	typedef struct efi_smbios_protocol efi_smbios_protocol_t;
	10
	11	struct efi_smbios_protocol {
	12	efi_status_t (__efiapi add)(efi_smbios_protocol_t , efi_handle_t,
	13	u16 , struct efi_smbios_record );
	14	efi_status_t (__efiapi update_string)(efi_smbios_protocol_t , u16 *,
	15	unsigned long , u8 );
	16	efi_status_t (__efiapi remove)(efi_smbios_protocol_t , u16);
	17	efi_status_t (__efiapi get_next)(efi_smbios_protocol_t , u16 , u8 ,
	18	struct efi_smbios_record **,
	19	efi_handle_t *);
	20
	21	u8 major_version;
	22	u8 minor_version;
	23	};
	24
	25	const u8 *__efi_get_smbios_string(u8 type, int offset, int recsize)
	26	{
	27	struct efi_smbios_record *record;
	28	efi_smbios_protocol_t *smbios;
	29	efi_status_t status;
	30	u16 handle = 0xfffe;
	31	const u8 *strtable;
	32
	33	status = efi_bs_call(locate_protocol, &EFI_SMBIOS_PROTOCOL_GUID, NULL,
	34	(void **)&smbios) ?:
	35	efi_call_proto(smbios, get_next, &handle, &type, &record, NULL);
	36	if (status != EFI_SUCCESS)
	37	return NULL;
	38
	39	strtable = (u8 *)record + recsize;
	40	for (int i = 1; i < ((u8 *)record)[offset]; i++) {
	41	int len = strlen(strtable);
	42
	43	if (!len)
	44	return NULL;
	45	strtable += len + 1;
	46	}
	47	return strtable;
	48	}

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+1−0

@@ -992,6 +992,7 @@ out_free_user_pages: · 991 unmodified lines
992	kvfree(e->user_pages);	992	kvfree(e->user_pages);
993	e->user_pages = NULL;	993	e->user_pages = NULL;
994	}	994	}
		995	mutex_unlock(&p->bo_list->bo_list_mutex);
995	return r;	996	return r;
996	}	997	}
997		998

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+0−26

@@ -143,32 +143,6 @@ int amdgpu_vm_set_pasid(struct amdgpu_device adev, struct amdgpu_vm vm, · 142 unmodified lines
143	return 0;	143	return 0;
144	}	144	}
145		145
146	/*
147	* vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
148	* happens while holding this lock anywhere to prevent deadlocks when
149	* an MMU notifier runs in reclaim-FS context.
150	*/
151	static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
152	{
153	mutex_lock(&vm->eviction_lock);
154	vm->saved_flags = memalloc_noreclaim_save();
155	}
156
157	static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
158	{
159	if (mutex_trylock(&vm->eviction_lock)) {
160	vm->saved_flags = memalloc_noreclaim_save();
161	return 1;
162	}
163	return 0;
164	}
165
166	static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
167	{
168	memalloc_noreclaim_restore(vm->saved_flags);
169	mutex_unlock(&vm->eviction_lock);
170	}
171
172	/**	146	/**
173	* amdgpu_vm_bo_evicted - vm_bo is evicted	147	* amdgpu_vm_bo_evicted - vm_bo is evicted
174	*	148	*

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+41−0

@@ -492,7 +492,48 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm vm, struct seq_file m); · 491 unmodified lines
492	*/	492	*/
493	static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm)	493	static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm)
494	{	494	{
		495	unsigned long flags;
		496	spinlock_t *lock;
		497
		498	/*
		499	* Workaround to stop racing between the fence signaling and handling
		500	* the cb. The lock is static after initially setting it up, just make
		501	* sure that the dma_fence structure isn't freed up.
		502	*/
		503	rcu_read_lock();
		504	lock = vm->last_tlb_flush->lock;
		505	rcu_read_unlock();
		506
		507	spin_lock_irqsave(lock, flags);
		508	spin_unlock_irqrestore(lock, flags);
		509
495	return atomic64_read(&vm->tlb_seq);	510	return atomic64_read(&vm->tlb_seq);
496	}	511	}
497		512
		513	/*
		514	* vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
		515	* happens while holding this lock anywhere to prevent deadlocks when
		516	* an MMU notifier runs in reclaim-FS context.
		517	*/
		518	static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
		519	{
		520	mutex_lock(&vm->eviction_lock);
		521	vm->saved_flags = memalloc_noreclaim_save();
		522	}
		523
		524	static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
		525	{
		526	if (mutex_trylock(&vm->eviction_lock)) {
		527	vm->saved_flags = memalloc_noreclaim_save();
		528	return true;
		529	}
		530	return false;
		531	}
		532
		533	static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
		534	{
		535	memalloc_noreclaim_restore(vm->saved_flags);
		536	mutex_unlock(&vm->eviction_lock);
		537	}
		538
498	#endif	539	#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c+2−0

@@ -597,7 +597,9 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev, · 596 unmodified lines
597	if (entry->bo)	597	if (entry->bo)
598	return 0;	598	return 0;
599		599
		600	amdgpu_vm_eviction_unlock(vm);
600	r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);	601	r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
		602	amdgpu_vm_eviction_lock(vm);
601	if (r)	603	if (r)
602	return r;	604	return r;
603		605

drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c+1−1

@@ -435,7 +435,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, · 434 unmodified lines
435	if (place->flags & TTM_PL_FLAG_TOPDOWN)	435	if (place->flags & TTM_PL_FLAG_TOPDOWN)
436	vres->flags \|= DRM_BUDDY_TOPDOWN_ALLOCATION;	436	vres->flags \|= DRM_BUDDY_TOPDOWN_ALLOCATION;
437		437
438	if (fpfn \|\| lpfn != man->size)	438	if (fpfn \|\| lpfn != mgr->mm.size)
439	/* Allocate blocks in desired range */	439	/* Allocate blocks in desired range */
440	vres->flags \|= DRM_BUDDY_RANGE_ALLOCATION;	440	vres->flags \|= DRM_BUDDY_RANGE_ALLOCATION;
441		441

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c+15−19

 {
 	int ret;
 	uint32_t num_devices, num_bos, num_objects;
-	uint64_t priv_size, priv_offset = 0;
+	uint64_t priv_size, priv_offset = 0, bo_priv_offset;
 	if (!args->devices || !args->bos || !args->priv_data)
 		return -EINVAL;
 	if (ret)
 		goto exit_unlock;
-	ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
+	/* Leave room for BOs in the private data. They need to be restored
-			    (uint8_t __user *)args->priv_data, &priv_offset);
+	 * before events, but we checkpoint them last to simplify the error
-	if (ret)
+	 * handling.
-		goto exit_unlock;
+	 */
+	bo_priv_offset = priv_offset;
+	priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data);
 	if (num_objects) {
 		ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,
 						 &priv_offset);
 		if (ret)
-			goto close_bo_fds;
+			goto exit_unlock;
 		ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,
 						 &priv_offset);
 		if (ret)
-			goto close_bo_fds;
+			goto exit_unlock;
 		ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);
 		if (ret)
-			goto close_bo_fds;
+			goto exit_unlock;
 	}
-close_bo_fds:
+	/* This must be the last thing in this function that can fail.
-	if (ret) {
+	 * Otherwise we leak dmabuf file descriptors.
-		/* If IOCTL returns err, user assumes all FDs opened in criu_dump_bos are closed */
+	 */
-		uint32_t i;
+	ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
-		struct kfd_criu_bo_bucket *bo_buckets = (struct kfd_criu_bo_bucket *) args->bos;
+			   (uint8_t __user *)args->priv_data, &bo_priv_offset);
-		for (i = 0; i < num_bos; i++) {
-			if (bo_buckets[i].alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)
-				close_fd(bo_buckets[i].dmabuf_fd);
-		}
-	}
 exit_unlock:
 	mutex_unlock(&p->mutex);

drivers/gpu/drm/amd/amdkfd/kfd_events.c+1−2

 		ret = create_other_event(p, ev, &ev_priv->event_id);
 		break;
 	}
+	mutex_unlock(&p->event_mutex);
 exit:
 	if (ret)
 	kfree(ev_priv);
-	mutex_unlock(&p->event_mutex);
 	return ret;
 }

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+4−3

 		bundle->surface_updates[planes_count].plane_info =
 			&bundle->plane_infos[planes_count];
-		fill_dc_dirty_rects(plane, old_plane_state, new_plane_state,
+		if (acrtc_state->stream->link->psr_settings.psr_feature_enabled)
-				    new_crtc_state,
+			fill_dc_dirty_rects(plane, old_plane_state,
-				    &bundle->flip_addrs[planes_count]);
+					    new_plane_state, new_crtc_state,
+					    &bundle->flip_addrs[planes_count]);
 		/*
 		 * Only allow immediate flips for fast updates that don't

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c+16−16

@@ -363,32 +363,32 @@ static struct wm_table ddr5_wm_table = { · 362 unmodified lines
363	.wm_inst = WM_A,	363	.wm_inst = WM_A,
364	.wm_type = WM_TYPE_PSTATE_CHG,	364	.wm_type = WM_TYPE_PSTATE_CHG,
365	.pstate_latency_us = 11.72,	365	.pstate_latency_us = 11.72,
366	.sr_exit_time_us = 9,	366	.sr_exit_time_us = 12.5,
367	.sr_enter_plus_exit_time_us = 11,	367	.sr_enter_plus_exit_time_us = 14.5,
368	.valid = true,	368	.valid = true,
369	},	369	},
370	{	370	{
371	.wm_inst = WM_B,	371	.wm_inst = WM_B,
372	.wm_type = WM_TYPE_PSTATE_CHG,	372	.wm_type = WM_TYPE_PSTATE_CHG,
373	.pstate_latency_us = 11.72,	373	.pstate_latency_us = 11.72,
374	.sr_exit_time_us = 9,	374	.sr_exit_time_us = 12.5,
375	.sr_enter_plus_exit_time_us = 11,	375	.sr_enter_plus_exit_time_us = 14.5,
376	.valid = true,	376	.valid = true,
377	},	377	},
378	{	378	{
379	.wm_inst = WM_C,	379	.wm_inst = WM_C,
380	.wm_type = WM_TYPE_PSTATE_CHG,	380	.wm_type = WM_TYPE_PSTATE_CHG,
381	.pstate_latency_us = 11.72,	381	.pstate_latency_us = 11.72,
382	.sr_exit_time_us = 9,	382	.sr_exit_time_us = 12.5,
383	.sr_enter_plus_exit_time_us = 11,	383	.sr_enter_plus_exit_time_us = 14.5,
384	.valid = true,	384	.valid = true,
385	},	385	},
386	{	386	{
387	.wm_inst = WM_D,	387	.wm_inst = WM_D,
388	.wm_type = WM_TYPE_PSTATE_CHG,	388	.wm_type = WM_TYPE_PSTATE_CHG,
389	.pstate_latency_us = 11.72,	389	.pstate_latency_us = 11.72,
390	.sr_exit_time_us = 9,	390	.sr_exit_time_us = 12.5,
391	.sr_enter_plus_exit_time_us = 11,	391	.sr_enter_plus_exit_time_us = 14.5,
392	.valid = true,	392	.valid = true,
393	},	393	},
394	}	394	}
@@ -400,32 +400,32 @@ static struct wm_table lpddr5_wm_table = { · 5 unmodified lines
400	.wm_inst = WM_A,	400	.wm_inst = WM_A,
401	.wm_type = WM_TYPE_PSTATE_CHG,	401	.wm_type = WM_TYPE_PSTATE_CHG,
402	.pstate_latency_us = 11.65333,	402	.pstate_latency_us = 11.65333,
403	.sr_exit_time_us = 11.5,	403	.sr_exit_time_us = 16.5,
404	.sr_enter_plus_exit_time_us = 14.5,	404	.sr_enter_plus_exit_time_us = 18.5,
405	.valid = true,	405	.valid = true,
406	},	406	},
407	{	407	{
408	.wm_inst = WM_B,	408	.wm_inst = WM_B,
409	.wm_type = WM_TYPE_PSTATE_CHG,	409	.wm_type = WM_TYPE_PSTATE_CHG,
410	.pstate_latency_us = 11.65333,	410	.pstate_latency_us = 11.65333,
411	.sr_exit_time_us = 11.5,	411	.sr_exit_time_us = 16.5,
412	.sr_enter_plus_exit_time_us = 14.5,	412	.sr_enter_plus_exit_time_us = 18.5,
413	.valid = true,	413	.valid = true,
414	},	414	},
415	{	415	{
416	.wm_inst = WM_C,	416	.wm_inst = WM_C,
417	.wm_type = WM_TYPE_PSTATE_CHG,	417	.wm_type = WM_TYPE_PSTATE_CHG,
418	.pstate_latency_us = 11.65333,	418	.pstate_latency_us = 11.65333,
419	.sr_exit_time_us = 11.5,	419	.sr_exit_time_us = 16.5,
420	.sr_enter_plus_exit_time_us = 14.5,	420	.sr_enter_plus_exit_time_us = 18.5,
421	.valid = true,	421	.valid = true,
422	},	422	},
423	{	423	{
424	.wm_inst = WM_D,	424	.wm_inst = WM_D,
425	.wm_type = WM_TYPE_PSTATE_CHG,	425	.wm_type = WM_TYPE_PSTATE_CHG,
426	.pstate_latency_us = 11.65333,	426	.pstate_latency_us = 11.65333,
427	.sr_exit_time_us = 11.5,	427	.sr_exit_time_us = 16.5,
428	.sr_enter_plus_exit_time_us = 14.5,	428	.sr_enter_plus_exit_time_us = 18.5,
429	.valid = true,	429	.valid = true,
430	},	430	},
431	}	431	}

drivers/gpu/drm/amd/display/dc/dc.h+1−0

@@ -853,6 +853,7 @@ struct dc_debug_options { · 852 unmodified lines
853	bool enable_dp_dig_pixel_rate_div_policy;	853	bool enable_dp_dig_pixel_rate_div_policy;
854	enum lttpr_mode lttpr_mode_override;	854	enum lttpr_mode lttpr_mode_override;
855	unsigned int dsc_delay_factor_wa_x1000;	855	unsigned int dsc_delay_factor_wa_x1000;
		856	unsigned int min_prefetch_in_strobe_ns;
856	};	857	};
857		858
858	struct gpu_info_soc_bounding_box_v1_0;	859	struct gpu_info_soc_bounding_box_v1_0;

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c+18−6

@@ -49,18 +49,30 @@ · 48 unmodified lines
49	#define CTX \	49	#define CTX \
50	enc1->base.ctx	50	enc1->base.ctx
51		51
		52	static void enc314_reset_fifo(struct stream_encoder *enc, bool reset)
		53	{
		54	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
		55	uint32_t reset_val = reset ? 1 : 0;
		56	uint32_t is_symclk_on;
		57
		58	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);
		59	REG_GET(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, &is_symclk_on);
		60
		61	if (is_symclk_on)
		62	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);
		63	else
		64	udelay(10);
		65	}
52		66
53	static void enc314_enable_fifo(struct stream_encoder *enc)	67	static void enc314_enable_fifo(struct stream_encoder *enc)
54	{	68	{
55	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);	69	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
56		70
57	/* TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON */
58	REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
59	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);	71	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
60	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);	72
61	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);	73	enc314_reset_fifo(enc, true);
62	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);	74	enc314_reset_fifo(enc, false);
63	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);	75
64	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);	76	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
65	}	77	}
66		78

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c+1−0

@@ -724,6 +724,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 723 unmodified lines
724	.enable_dp_dig_pixel_rate_div_policy = 1,	724	.enable_dp_dig_pixel_rate_div_policy = 1,
725	.allow_sw_cursor_fallback = false,	725	.allow_sw_cursor_fallback = false,
726	.alloc_extra_way_for_cursor = true,	726	.alloc_extra_way_for_cursor = true,
		727	.min_prefetch_in_strobe_ns = 60000, // 60us
727	};	728	};
728		729
729	static const struct dc_debug_options debug_defaults_diags = {	730	static const struct dc_debug_options debug_defaults_diags = {

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c+1−0

@@ -722,6 +722,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 721 unmodified lines
722	.enable_dp_dig_pixel_rate_div_policy = 1,	722	.enable_dp_dig_pixel_rate_div_policy = 1,
723	.allow_sw_cursor_fallback = false,	723	.allow_sw_cursor_fallback = false,
724	.alloc_extra_way_for_cursor = true,	724	.alloc_extra_way_for_cursor = true,
		725	.min_prefetch_in_strobe_ns = 60000, // 60us
725	};	726	};
726		727
727	static const struct dc_debug_options debug_defaults_diags = {	728	static const struct dc_debug_options debug_defaults_diags = {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c+2−2

@@ -146,8 +146,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = { · 145 unmodified lines
146	},	146	},
147	},	147	},
148	.num_states = 5,	148	.num_states = 5,
149	.sr_exit_time_us = 9.0,	149	.sr_exit_time_us = 16.5,
150	.sr_enter_plus_exit_time_us = 11.0,	150	.sr_enter_plus_exit_time_us = 18.5,
151	.sr_exit_z8_time_us = 442.0,	151	.sr_exit_z8_time_us = 442.0,
152	.sr_enter_plus_exit_z8_time_us = 560.0,	152	.sr_enter_plus_exit_z8_time_us = 560.0,
153	.writeback_latency_us = 12.0,	153	.writeback_latency_us = 12.0,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c+2−0

@@ -2364,6 +2364,8 @@ void dcn32_update_bw_bounding_box_fpu(struct dc dc, struct clk_bw_params bw_pa · 2363 unmodified lines
2364	/* DML DSC delay factor workaround */	2364	/* DML DSC delay factor workaround */
2365	dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;	2365	dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
2366		2366
		2367	dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
		2368
2367	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */	2369	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
2368	dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;	2370	dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2369	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;	2371	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c+5−0

 					v->SwathHeightY[k],
 					v->SwathHeightC[k],
 					TWait,
+					v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ?
+							mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
 					/* Output */
 					&v->DSTXAfterScaler[k],
 					&v->DSTYAfterScaler[k],
 							mode_lib->vba.FCLKChangeLatency, mode_lib->vba.UrgLatency[i],
 							mode_lib->vba.SREnterPlusExitTime);
+					memset(&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull, 0, sizeof(DmlPipe));
 					v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.Dppclk = mode_lib->vba.RequiredDPPCLK[i][j][k];
 					v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.Dispclk = mode_lib->vba.RequiredDISPCLK[i][j];
 					v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.PixelClock = mode_lib->vba.PixelClock[k];
 							v->swath_width_chroma_ub_this_state[k],
 							v->SwathHeightYThisState[k],
 							v->SwathHeightCThisState[k], v->TWait,
+							v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ ?
+									mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
 							/* Output */
 							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h+3−0

@@ -49,6 +49,9 @@ · 48 unmodified lines
49	#define BPP_INVALID 0	49	#define BPP_INVALID 0
50	#define BPP_BLENDED_PIPE 0xffffffff	50	#define BPP_BLENDED_PIPE 0xffffffff
51		51
		52	#define MEM_STROBE_FREQ_MHZ 1600
		53	#define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0
		54
52	struct display_mode_lib;	55	struct display_mode_lib;
53		56
54	void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);	57	void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c+11−3

 		unsigned int SwathHeightY,
 		unsigned int SwathHeightC,
 		double TWait,
+		double TPreReq,
 		/* Output */
 		double   *DSTXAfterScaler,
 		double   *DSTYAfterScaler,
 	double  min_Lsw;
 	double  Tsw_est1 = 0;
 	double  Tsw_est3 = 0;
+	double  TPreMargin = 0;
 	if (v->GPUVMEnable == true && v->HostVMEnable == true)
 		HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
 	dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;
 	Tpre_rounded = dst_y_prefetch_equ * LineTime;
+	TPreMargin = Tpre_rounded - TPreReq;
 #ifdef __DML_VBA_DEBUG__
 	dml_print("DML::%s: dst_y_prefetch_equ: %f (after round)\n", __func__, dst_y_prefetch_equ);
 	dml_print("DML::%s: LineTime: %f\n", __func__, LineTime);
 	*VRatioPrefetchY = 0;
 	*VRatioPrefetchC = 0;
 	*RequiredPrefetchPixDataBWLuma = 0;
-	if (dst_y_prefetch_equ > 1) {
+	if (dst_y_prefetch_equ > 1 && TPreMargin > 0.0) {
 		double PrefetchBandwidth1;
 		double PrefetchBandwidth2;
 		double PrefetchBandwidth3;
 		}
 		if (dst_y_prefetch_oto < dst_y_prefetch_equ) {
-			*DestinationLinesForPrefetch = dst_y_prefetch_oto;
+			if (dst_y_prefetch_oto * LineTime < TPreReq) {
+				*DestinationLinesForPrefetch = dst_y_prefetch_equ;
+			} else {
+				*DestinationLinesForPrefetch = dst_y_prefetch_oto;
+			}
 			TimeForFetchingMetaPTE = Tvm_oto;
 			TimeForFetchingRowInVBlank = Tr0_oto;
 			*PrefetchBandwidth = prefetch_bw_oto;
 		if (v->NumberOfActiveSurfaces > 1) {
 			ActiveClockChangeLatencyHidingY = ActiveClockChangeLatencyHidingY
-					- (1 - 1 / v->NumberOfActiveSurfaces) * SwathHeightY[k] * v->HTotal[k]
+					- (1.0 - 1.0 / v->NumberOfActiveSurfaces) * SwathHeightY[k] * v->HTotal[k]
 							/ v->PixelClock[k] / v->VRatio[k];
 		}

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h+2−1

 #include "os_types.h"
 #include "../dc_features.h"
 #include "../display_mode_structs.h"
-#include "dml/display_mode_vba.h"
+#include "../display_mode_vba.h"
 unsigned int dml32_dscceComputeDelay(
 		unsigned int bpc,
 		unsigned int SwathHeightY,
 		unsigned int SwathHeightC,
 		double TWait,
+		double TPreReq,
 		/* Output */
 		double   *DSTXAfterScaler,
 		double   *DSTYAfterScaler,

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c+2−0

@@ -544,6 +544,8 @@ void dcn321_update_bw_bounding_box_fpu(struct dc dc, struct clk_bw_params bw_p · 543 unmodified lines
544	/* DML DSC delay factor workaround */	544	/* DML DSC delay factor workaround */
545	dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;	545	dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
546		546
		547	dcn3_21_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
		548
547	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */	549	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
548	dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;	550	dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
549	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;	551	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h+1−0

@@ -367,6 +367,7 @@ struct _vcs_dpi_ip_params_st { · 366 unmodified lines
367		367
368	/* DM workarounds */	368	/* DM workarounds */
369	double dsc_delay_factor_wa; // TODO: Remove after implementing root cause fix	369	double dsc_delay_factor_wa; // TODO: Remove after implementing root cause fix
		370	double min_prefetch_in_strobe_us;
370	};	371	};
371		372
372	struct _vcs_dpi_display_xfc_params_st {	373	struct _vcs_dpi_display_xfc_params_st {

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c+14−0

@@ -107,6 +107,13 @@ static const struct ddc_registers ddc_data_regs_dcn[] = { · 106 unmodified lines
107	ddc_data_regs_dcn2(3),	107	ddc_data_regs_dcn2(3),
108	ddc_data_regs_dcn2(4),	108	ddc_data_regs_dcn2(4),
109	ddc_data_regs_dcn2(5),	109	ddc_data_regs_dcn2(5),
		110	{
		111	// add a dummy entry for cases no such port
		112	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
		113	.ddc_setup = 0,
		114	.phy_aux_cntl = 0,
		115	.dc_gpio_aux_ctrl_5 = 0
		116	},
110	{	117	{
111	DDC_GPIO_VGA_REG_LIST(DATA),	118	DDC_GPIO_VGA_REG_LIST(DATA),
112	.ddc_setup = 0,	119	.ddc_setup = 0,
@@ -121,6 +128,13 @@ static const struct ddc_registers ddc_clk_regs_dcn[] = { · 8 unmodified lines
121	ddc_clk_regs_dcn2(3),	128	ddc_clk_regs_dcn2(3),
122	ddc_clk_regs_dcn2(4),	129	ddc_clk_regs_dcn2(4),
123	ddc_clk_regs_dcn2(5),	130	ddc_clk_regs_dcn2(5),
		131	{
		132	// add a dummy entry for cases no such port
		133	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
		134	.ddc_setup = 0,
		135	.phy_aux_cntl = 0,
		136	.dc_gpio_aux_ctrl_5 = 0
		137	},
124	{	138	{
125	DDC_GPIO_VGA_REG_LIST(CLK),	139	DDC_GPIO_VGA_REG_LIST(CLK),
126	.ddc_setup = 0,	140	.ddc_setup = 0,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c+6−3

@@ -94,11 +94,14 @@ static enum gpio_result set_config( · 93 unmodified lines
94	* is required for detection of AUX mode */	94	* is required for detection of AUX mode */
95	if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) {	95	if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) {
96	if (!ddc_data_pd_en \|\| !ddc_clk_pd_en) {	96	if (!ddc_data_pd_en \|\| !ddc_clk_pd_en) {
97		97	if (hw_gpio->base.en == GPIO_DDC_LINE_DDC_VGA) {
98	REG_SET_2(gpio.MASK_reg, regval,	98	// bit 4 of mask has different usage in some cases
		99	REG_SET(gpio.MASK_reg, regval, DC_GPIO_DDC1DATA_PD_EN, 1);
		100	} else {
		101	REG_SET_2(gpio.MASK_reg, regval,
99	DC_GPIO_DDC1DATA_PD_EN, 1,	102	DC_GPIO_DDC1DATA_PD_EN, 1,
100	DC_GPIO_DDC1CLK_PD_EN, 1);	103	DC_GPIO_DDC1CLK_PD_EN, 1);
101		104	}
102	if (config_data->type ==	105	if (config_data->type ==
103	GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)	106	GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
104	msleep(3);	107	msleep(3);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c+12−13

@@ -67,22 +67,21 @@ int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, · 66 unmodified lines
67	int vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,	67	int vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
68	uint32_t *speed)	68	uint32_t *speed)
69	{	69	{
70	uint32_t current_rpm;	70	struct amdgpu_device *adev = hwmgr->adev;
71	uint32_t percent = 0;	71	uint32_t duty100, duty;
72		72	uint64_t tmp64;
73	if (hwmgr->thermal_controller.fanInfo.bNoFan)
74	return 0;
75		73
76	if (vega10_get_current_rpm(hwmgr, &current_rpm))	74	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
77	return -1;	75	CG_FDO_CTRL1, FMAX_DUTY100);
		76	duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
		77	CG_THERMAL_STATUS, FDO_PWM_DUTY);
78		78
79	if (hwmgr->thermal_controller.	79	if (!duty100)
80	advanceFanControlParameters.usMaxFanRPM != 0)	80	return -EINVAL;
81	percent = current_rpm * 255 /
82	hwmgr->thermal_controller.
83	advanceFanControlParameters.usMaxFanRPM;
84		81
85	*speed = MIN(percent, 255);	82	tmp64 = (uint64_t)duty * 255;
		83	do_div(tmp64, duty100);
		84	*speed = MIN((uint32_t)tmp64, 255);
86		85
87	return 0;	86	return 0;
88	}	87	}

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_ppsmc.h+7−8

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c+3−1

 		if (((adev->pdev->device == 0x73A1) &&
 		    (adev->pdev->revision == 0x00)) ||
 		    ((adev->pdev->device == 0x73BF) &&
-		    (adev->pdev->revision == 0xCF)))
+		    (adev->pdev->revision == 0xCF)) ||
+		    ((adev->pdev->device == 0x7422) &&
+		    (adev->pdev->revision == 0x00)))
 			smu_baco->platform_support = false;
 	}

drivers/gpu/drm/drm_panel_orientation_quirks.c+12−0

 		  DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "One S1003"),
 		},
 		.driver_data = (void *)&lcd800x1280_rightside_up,
+	}, {	/* Acer Switch V 10 (SW5-017) */
+		.matches = {
+		  DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer"),
+		  DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "SW5-017"),
+		},
+		.driver_data = (void *)&lcd800x1280_rightside_up,
 	}, {	/* Anbernic Win600 */
 		.matches = {
 		  DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Anbernic"),
 		 DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"),
 		},
 		.driver_data = (void *)&lcd1200x1920_rightside_up,
+	}, {	/* Nanote UMPC-01 */
+		.matches = {
+		 DMI_MATCH(DMI_SYS_VENDOR, "RWC CO.,LTD"),
+		 DMI_MATCH(DMI_PRODUCT_NAME, "UMPC-01"),
+		},
+		.driver_data = (void *)&lcd1200x1920_rightside_up,
 	}, {	/* OneGX1 Pro */
 		.matches = {
 		  DMI_EXACT_MATCH(DMI_SYS_VENDOR, "SYSTEM_MANUFACTURER"),

drivers/gpu/drm/i915/display/intel_psr.c+4−1

 	if (intel_dp->psr.psr2_sel_fetch_enabled) {
 		u32 val;
-		if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
+		if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
+			/* Send one update otherwise lag is observed in screen */
+			intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
 			return;
+		}
 		val = man_trk_ctl_enable_bit_get(dev_priv) |
 		      man_trk_ctl_partial_frame_bit_get(dev_priv) |

drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c+2−2

@@ -40,13 +40,13 @@ static struct sg_table i915_gem_map_dma_buf(struct dma_buf_attachment attachme · 39 unmodified lines
40	goto err;	40	goto err;
41	}	41	}
42		42
43	ret = sg_alloc_table(st, obj->mm.pages->nents, GFP_KERNEL);	43	ret = sg_alloc_table(st, obj->mm.pages->orig_nents, GFP_KERNEL);
44	if (ret)	44	if (ret)
45	goto err_free;	45	goto err_free;
46		46
47	src = obj->mm.pages->sgl;	47	src = obj->mm.pages->sgl;
48	dst = st->sgl;	48	dst = st->sgl;
49	for (i = 0; i < obj->mm.pages->nents; i++) {	49	for (i = 0; i < obj->mm.pages->orig_nents; i++) {
50	sg_set_page(dst, sg_page(src), src->length, 0);	50	sg_set_page(dst, sg_page(src), src->length, 0);
51	dst = sg_next(dst);	51	dst = sg_next(dst);
52	src = sg_next(src);	52	src = sg_next(src);

drivers/gpu/drm/i915/gem/i915_gem_shmem.c+2−2

@@ -369,14 +369,14 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, · 368 unmodified lines
369		369
370	__start_cpu_write(obj);	370	__start_cpu_write(obj);
371	/*	371	/*
372	* On non-LLC platforms, force the flush-on-acquire if this is ever	372	* On non-LLC igfx platforms, force the flush-on-acquire if this is ever
373	* swapped-in. Our async flush path is not trust worthy enough yet(and	373	* swapped-in. Our async flush path is not trust worthy enough yet(and
374	* happens in the wrong order), and with some tricks it's conceivable	374	* happens in the wrong order), and with some tricks it's conceivable
375	* for userspace to change the cache-level to I915_CACHE_NONE after the	375	* for userspace to change the cache-level to I915_CACHE_NONE after the
376	* pages are swapped-in, and since execbuf binds the object before doing	376	* pages are swapped-in, and since execbuf binds the object before doing
377	* the async flush, we have a race window.	377	* the async flush, we have a race window.
378	*/	378	*/
379	if (!HAS_LLC(i915))	379	if (!HAS_LLC(i915) && !IS_DGFX(i915))
380	obj->cache_dirty = true;	380	obj->cache_dirty = true;
381	}	381	}
382		382

drivers/gpu/drm/i915/gem/i915_gem_userptr.c+3−2

 {
 	VMA_ITERATOR(vmi, mm, addr);
 	struct vm_area_struct *vma;
+	unsigned long end = addr + len;
 	mmap_read_lock(mm);
-	for_each_vma_range(vmi, vma, addr + len) {
+	for_each_vma_range(vmi, vma, end) {
 		/* Check for holes, note that we also update the addr below */
 		if (vma->vm_start > addr)
 			break;
 	}
 	mmap_read_unlock(mm);
-	if (vma)
+	if (vma || addr < end)
 		return -EFAULT;
 	return 0;
 }

drivers/gpu/drm/panfrost/panfrost_mmu.c+10−1

 static size_t get_pgsize(u64 addr, size_t size, size_t *count)
 {
+	/*
+	 * io-pgtable only operates on multiple pages within a single table
+	 * entry, so we need to split at boundaries of the table size, i.e.
+	 * the next block size up. The distance from address A to the next
+	 * boundary of block size B is logically B - A % B, but in unsigned
+	 * two's complement where B is a power of two we get the equivalence
+	 * B - A % B == (B - A) % B == (n * B - A) % B, and choose n = 0 :)
+	 */
 	size_t blk_offset = -addr % SZ_2M;
 	if (blk_offset || size < SZ_2M) {
 		*count = min_not_zero(blk_offset, size) / SZ_4K;
 		return SZ_4K;
 	}
-	*count = size / SZ_2M;
+	blk_offset = -addr % SZ_1G ?: SZ_1G;
+	*count = min(blk_offset, size) / SZ_2M;
 	return SZ_2M;
 }

drivers/gpu/drm/rcar-du/Kconfig+9−4

 	select OF_FLATTREE
 	select OF_OVERLAY
-config DRM_RCAR_MIPI_DSI
+config DRM_RCAR_USE_MIPI_DSI
-	tristate "R-Car DU MIPI DSI Encoder Support"
+	bool "R-Car DU MIPI DSI Encoder Support"
-	depends on DRM && DRM_BRIDGE && OF
+	depends on DRM_BRIDGE && OF
-	select DRM_MIPI_DSI
+	default DRM_RCAR_DU
 	help
 	  Enable support for the R-Car Display Unit embedded MIPI DSI encoders.
+config DRM_RCAR_MIPI_DSI
+	def_tristate DRM_RCAR_DU
+	depends on DRM_RCAR_USE_MIPI_DSI
+	select DRM_MIPI_DSI
 config DRM_RCAR_VSP
 	bool "R-Car DU VSP Compositor Support" if ARM
 	default y if ARM64

drivers/gpu/drm/vc4/vc4_drv.c+6−1

 	if (ret)
 		return ret;
-	return platform_driver_register(&vc4_platform_driver);
+	ret = platform_driver_register(&vc4_platform_driver);
+	if (ret)
+		platform_unregister_drivers(component_drivers,
+					    ARRAY_SIZE(component_drivers));
+	return ret;
 }
 static void __exit vc4_drm_unregister(void)

drivers/gpu/drm/vc4/vc4_hdmi.c+36−11

 	if (!crtc_state->active)
 		return 0;
-	if (!vc4_hdmi_supports_scrambling(encoder))
+	mutex_lock(&vc4_hdmi->mutex);
+	if (!vc4_hdmi_supports_scrambling(encoder)) {
+		mutex_unlock(&vc4_hdmi->mutex);
 		return 0;
+	}
 	scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
 							   vc4_hdmi->output_bpc,
 							   vc4_hdmi->output_format);
-	if (!scrambling_needed)
+	if (!scrambling_needed) {
+		mutex_unlock(&vc4_hdmi->mutex);
 		return 0;
+	}
 	if (conn_state->commit &&
-	    !try_wait_for_completion(&conn_state->commit->hw_done))
+	    !try_wait_for_completion(&conn_state->commit->hw_done)) {
+		mutex_unlock(&vc4_hdmi->mutex);
 		return 0;
+	}
 	ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
 	if (ret < 0) {
 		drm_err(drm, "Failed to read TMDS config: %d\n", ret);
+		mutex_unlock(&vc4_hdmi->mutex);
 		return 0;
 	}
-	if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed)
+	if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
+		mutex_unlock(&vc4_hdmi->mutex);
 		return 0;
+	}
+	mutex_unlock(&vc4_hdmi->mutex);
 	/*
 	 * HDMI 2.0 says that one should not send scrambled data
 	 * .adap_enable, which leads to that funtion being called with
 	 * our mutex held.
 	 *
-	 * A similar situation occurs with
+	 * A similar situation occurs with vc4_hdmi_reset_link() that
-	 * drm_atomic_helper_connector_hdmi_reset_link() that will call
+	 * will call into our KMS hooks if the scrambling was enabled.
-	 * into our KMS hooks if the scrambling was enabled.
 	 *
 	 * Concurrency isn't an issue at the moment since we don't share
 	 * any state with any of the other frameworks so we can ignore
 		DRM_ERROR("Failed to get HDMI state machine clock\n");
 		return PTR_ERR(vc4_hdmi->hsm_clock);
 	}
 	vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
 	vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
+	vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi");
+	if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) {
+		DRM_ERROR("Failed to get HDMI state machine clock\n");
+		return PTR_ERR(vc4_hdmi->hsm_rpm_clock);
+	}
 	return 0;
 }
 		return PTR_ERR(vc4_hdmi->hsm_clock);
 	}
+	vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi");
+	if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) {
+		DRM_ERROR("Failed to get HDMI state machine clock\n");
+		return PTR_ERR(vc4_hdmi->hsm_rpm_clock);
+	}
 	vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
 	if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
 		DRM_ERROR("Failed to get pixel bvb clock\n");
 {
 	struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
-	clk_disable_unprepare(vc4_hdmi->hsm_clock);
+	clk_disable_unprepare(vc4_hdmi->hsm_rpm_clock);
 	return 0;
 }
 	 * its frequency while the power domain is active so that it
 	 * keeps its rate.
 	 */
-	ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
+	ret = clk_set_min_rate(vc4_hdmi->hsm_rpm_clock, HSM_MIN_CLOCK_FREQ);
 	if (ret)
 		return ret;
-	ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
+	ret = clk_prepare_enable(vc4_hdmi->hsm_rpm_clock);
 	if (ret)
 		return ret;
 	 * case, it will lead to a silent CPU stall. Let's make sure we
 	 * prevent such a case.
 	 */
-	rate = clk_get_rate(vc4_hdmi->hsm_clock);
+	rate = clk_get_rate(vc4_hdmi->hsm_rpm_clock);
 	if (!rate) {
 		ret = -EINVAL;
 		goto err_disable_clk;

drivers/gpu/drm/vc4/vc4_hdmi.h+1−0

@@ -172,6 +172,7 @@ struct vc4_hdmi { · 171 unmodified lines
172	struct clk *cec_clock;	172	struct clk *cec_clock;
173	struct clk *pixel_clock;	173	struct clk *pixel_clock;
174	struct clk *hsm_clock;	174	struct clk *hsm_clock;
		175	struct clk *hsm_rpm_clock;
175	struct clk *audio_clock;	176	struct clk *audio_clock;
176	struct clk *pixel_bvb_clock;	177	struct clk *pixel_bvb_clock;
177		178

drivers/hid/hid-asus.c+1−3

 {
 	struct input_mt *mt = drvdat->input->mt;
 	struct input_mt_slot *oldest;
-	int oldid, count, i;
+	int oldid, i;
 	if (drvdat->tp->contact_size < 5)
 		return;
 	oldest = NULL;
 	oldid = mt->trkid;
-	count = 0;
 	for (i = 0; i < mt->num_slots; ++i) {
 		struct input_mt_slot *ps = &mt->slots[i];
 			oldest = ps;
 			oldid = id;
 		}
-		count++;
 	}
 	if (oldest) {

drivers/hid/hid-hyperv.c+1−1

@@ -499,7 +499,7 @@ static int mousevsc_probe(struct hv_device *device, · 498 unmodified lines
499		499
500	ret = hid_add_device(hid_dev);	500	ret = hid_add_device(hid_dev);
501	if (ret)	501	if (ret)
502	goto probe_err1;	502	goto probe_err2;
503		503
504		504
505	ret = hid_parse(hid_dev);	505	ret = hid_parse(hid_dev);

drivers/hid/wacom_wac.c+6−5

@@ -2520,11 +2520,12 @@ static void wacom_wac_pen_report(struct hid_device *hdev, · 2519 unmodified lines
2520		2520
2521	if (!delay_pen_events(wacom_wac) && wacom_wac->tool[0]) {	2521	if (!delay_pen_events(wacom_wac) && wacom_wac->tool[0]) {
2522	int id = wacom_wac->id[0];	2522	int id = wacom_wac->id[0];
2523	if (wacom_wac->features.quirks & WACOM_QUIRK_PEN_BUTTON3 &&	2523	if (wacom_wac->features.quirks & WACOM_QUIRK_PEN_BUTTON3) {
2524	wacom_wac->hid_data.barrelswitch & wacom_wac->hid_data.barrelswitch2) {	2524	int sw_state = wacom_wac->hid_data.barrelswitch \|
2525	wacom_wac->hid_data.barrelswitch = 0;	2525	(wacom_wac->hid_data.barrelswitch2 << 1);
2526	wacom_wac->hid_data.barrelswitch2 = 0;	2526	wacom_wac->hid_data.barrelswitch = sw_state == 1;
2527	wacom_wac->hid_data.barrelswitch3 = 1;	2527	wacom_wac->hid_data.barrelswitch2 = sw_state == 2;
		2528	wacom_wac->hid_data.barrelswitch3 = sw_state == 3;
2528	}	2529	}
2529	input_report_key(input, BTN_STYLUS, wacom_wac->hid_data.barrelswitch);	2530	input_report_key(input, BTN_STYLUS, wacom_wac->hid_data.barrelswitch);
2530	input_report_key(input, BTN_STYLUS2, wacom_wac->hid_data.barrelswitch2);	2531	input_report_key(input, BTN_STYLUS2, wacom_wac->hid_data.barrelswitch2);

drivers/hv/hv_balloon.c+1−1

@@ -905,7 +905,7 @@ static unsigned long handle_pg_range(unsigned long pg_start, · 904 unmodified lines
905	* We have some residual hot add range	905	* We have some residual hot add range
906	* that needs to be hot added; hot add	906	* that needs to be hot added; hot add
907	* it now. Hot add a multiple of	907	* it now. Hot add a multiple of
908	* of HA_CHUNK that fully covers the pages	908	* HA_CHUNK that fully covers the pages
909	* we have.	909	* we have.
910	*/	910	*/
911	size = (has->end_pfn - has->ha_end_pfn);	911	size = (has->end_pfn - has->ha_end_pfn);

drivers/hwspinlock/qcom_hwspinlock.c+32−10

 struct qcom_hwspinlock_of_data {
 	u32 offset;
 	u32 stride;
+	const struct regmap_config *regmap_config;
 };
 static int qcom_hwspinlock_trylock(struct hwspinlock *lock)
 	.stride = 0x4,
 };
-/* All modern platform has offset 0 and stride of 4k */
+static const struct regmap_config tcsr_msm8226_mutex_config = {
+	.reg_bits		= 32,
+	.reg_stride		= 4,
+	.val_bits		= 32,
+	.max_register		= 0x1000,
+	.fast_io		= true,
+};
+static const struct qcom_hwspinlock_of_data of_msm8226_tcsr_mutex = {
+	.offset = 0,
+	.stride = 0x80,
+	.regmap_config = &tcsr_msm8226_mutex_config,
+};
+static const struct regmap_config tcsr_mutex_config = {
+	.reg_bits		= 32,
+	.reg_stride		= 4,
+	.val_bits		= 32,
+	.max_register		= 0x20000,
+	.fast_io		= true,
+};
 static const struct qcom_hwspinlock_of_data of_tcsr_mutex = {
 	.offset = 0,
 	.stride = 0x1000,
+	.regmap_config = &tcsr_mutex_config,
 };
 static const struct of_device_id qcom_hwspinlock_of_match[] = {
 	{ .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex },
 	{ .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
+	{ .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+	{ .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+	{ .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+	{ .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+	{ .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
 	return regmap;
 }
-static const struct regmap_config tcsr_mutex_config = {
-	.reg_bits		= 32,
-	.reg_stride		= 4,
-	.val_bits		= 32,
-	.max_register		= 0x40000,
-	.fast_io		= true,
-};
 static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev,
 						 u32 *offset, u32 *stride)
 {
 	void __iomem *base;
 	data = of_device_get_match_data(dev);
+	if (!data->regmap_config)
+		return ERR_PTR(-EINVAL);
 	*offset = data->offset;
 	*stride = data->stride;
 	if (IS_ERR(base))
 		return ERR_CAST(base);
-	return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config);
+	return devm_regmap_init_mmio(dev, base, data->regmap_config);
 }
 static int qcom_hwspinlock_probe(struct platform_device *pdev)

drivers/mmc/host/sdhci-brcmstb.c+2−1

 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include "sdhci-cqhci.h"
 #include "sdhci-pltfm.h"
 #include "cqhci.h"
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
-	sdhci_reset(host, mask);
+	sdhci_and_cqhci_reset(host, mask);
 	/* Reset will clear this, so re-enable it */
 	if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK)

drivers/mmc/host/sdhci-cqhci.h+24−0

@@ -0,0 +1,24 @@
	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* Copyright 2022 The Chromium OS Authors
	4	*
	5	* Support that applies to the combination of SDHCI and CQHCI, while not
	6	* expressing a dependency between the two modules.
	7	*/
	8
	9	#ifndef __MMC_HOST_SDHCI_CQHCI_H__
	10	#define __MMC_HOST_SDHCI_CQHCI_H__
	11
	12	#include "cqhci.h"
	13	#include "sdhci.h"
	14
	15	static inline void sdhci_and_cqhci_reset(struct sdhci_host *host, u8 mask)
	16	{
	17	if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
	18	host->mmc->cqe_private)
	19	cqhci_deactivate(host->mmc);
	20
	21	sdhci_reset(host, mask);
	22	}
	23
	24	#endif /* __MMC_HOST_SDHCI_CQHCI_H__ */

drivers/mmc/host/sdhci-esdhc-imx.c+4−3

 #include <linux/of_device.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pm_runtime.h>
+#include "sdhci-cqhci.h"
 #include "sdhci-pltfm.h"
 #include "sdhci-esdhc.h"
 #include "cqhci.h"
 static void esdhc_reset(struct sdhci_host *host, u8 mask)
 {
-	sdhci_reset(host, mask);
+	sdhci_and_cqhci_reset(host, mask);
 	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 	if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
 		host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
-	if (host->caps & MMC_CAP_8_BIT_DATA &&
+	if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
 	    imx_data->socdata->flags & ESDHC_FLAG_HS400)
 		host->mmc->caps2 |= MMC_CAP2_HS400;
 	if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
 		host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
-	if (host->caps & MMC_CAP_8_BIT_DATA &&
+	if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
 	    imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
 		host->mmc->caps2 |= MMC_CAP2_HS400_ES;
 		host->mmc_host_ops.hs400_enhanced_strobe =

drivers/mmc/host/sdhci-of-arasan.c+2−1

 #include <linux/firmware/xlnx-zynqmp.h>
 #include "cqhci.h"
+#include "sdhci-cqhci.h"
 #include "sdhci-pltfm.h"
 #define SDHCI_ARASAN_VENDOR_REGISTER	0x78
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
-	sdhci_reset(host, mask);
+	sdhci_and_cqhci_reset(host, mask);
 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
 		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);

drivers/mmc/host/sdhci-tegra.c+2−1

 #include <soc/tegra/common.h>
+#include "sdhci-cqhci.h"
 #include "sdhci-pltfm.h"
 #include "cqhci.h"
 	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 	u32 misc_ctrl, clk_ctrl, pad_ctrl;
-	sdhci_reset(host, mask);
+	sdhci_and_cqhci_reset(host, mask);
 	if (!(mask & SDHCI_RESET_ALL))
 		return;

drivers/mmc/host/sdhci_am654.c+4−3

 #include <linux/sys_soc.h>
 #include "cqhci.h"
+#include "sdhci-cqhci.h"
 #include "sdhci-pltfm.h"
 /* CTL_CFG Registers */
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
-	sdhci_reset(host, mask);
+	sdhci_and_cqhci_reset(host, mask);
 	if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
 		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 	.set_clock = sdhci_am654_set_clock,
 	.write_b = sdhci_am654_write_b,
 	.irq = sdhci_am654_cqhci_irq,
-	.reset = sdhci_reset,
+	.reset = sdhci_and_cqhci_reset,
 };
 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
 	.set_clock = sdhci_am654_set_clock,
 	.write_b = sdhci_am654_write_b,
 	.irq = sdhci_am654_cqhci_irq,
-	.reset = sdhci_reset,
+	.reset = sdhci_and_cqhci_reset,
 };
 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {

drivers/net/can/at91_can.c+1−1

@@ -452,7 +452,7 @@ static netdev_tx_t at91_start_xmit(struct sk_buff skb, struct net_device dev) · 451 unmodified lines
452	unsigned int mb, prio;	452	unsigned int mb, prio;
453	u32 reg_mid, reg_mcr;	453	u32 reg_mid, reg_mcr;
454		454
455	if (can_dropped_invalid_skb(dev, skb))	455	if (can_dev_dropped_skb(dev, skb))
456	return NETDEV_TX_OK;	456	return NETDEV_TX_OK;
457		457
458	mb = get_tx_next_mb(priv);	458	mb = get_tx_next_mb(priv);

drivers/net/can/c_can/c_can_main.c+1−1

@@ -457,7 +457,7 @@ static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, · 456 unmodified lines
457	struct c_can_tx_ring *tx_ring = &priv->tx;	457	struct c_can_tx_ring *tx_ring = &priv->tx;
458	u32 idx, obj, cmd = IF_COMM_TX;	458	u32 idx, obj, cmd = IF_COMM_TX;
459		459
460	if (can_dropped_invalid_skb(dev, skb))	460	if (can_dev_dropped_skb(dev, skb))
461	return NETDEV_TX_OK;	461	return NETDEV_TX_OK;
462		462
463	if (c_can_tx_busy(priv, tx_ring))	463	if (c_can_tx_busy(priv, tx_ring))

drivers/net/can/can327.c+1−1

@@ -813,7 +813,7 @@ static netdev_tx_t can327_netdev_start_xmit(struct sk_buff *skb, · 812 unmodified lines
813	struct can327 *elm = netdev_priv(dev);	813	struct can327 *elm = netdev_priv(dev);
814	struct can_frame frame = (struct can_frame )skb->data;	814	struct can_frame frame = (struct can_frame )skb->data;
815		815
816	if (can_dropped_invalid_skb(dev, skb))	816	if (can_dev_dropped_skb(dev, skb))
817	return NETDEV_TX_OK;	817	return NETDEV_TX_OK;
818		818
819	/* We shouldn't get here after a hardware fault:	819	/* We shouldn't get here after a hardware fault:

drivers/net/can/cc770/cc770.c+1−1

@@ -429,7 +429,7 @@ static netdev_tx_t cc770_start_xmit(struct sk_buff skb, struct net_device dev) · 428 unmodified lines
429	struct cc770_priv *priv = netdev_priv(dev);	429	struct cc770_priv *priv = netdev_priv(dev);
430	unsigned int mo = obj2msgobj(CC770_OBJ_TX);	430	unsigned int mo = obj2msgobj(CC770_OBJ_TX);
431		431
432	if (can_dropped_invalid_skb(dev, skb))	432	if (can_dev_dropped_skb(dev, skb))
433	return NETDEV_TX_OK;	433	return NETDEV_TX_OK;
434		434
435	netif_stop_queue(dev);	435	netif_stop_queue(dev);

drivers/net/can/ctucanfd/ctucanfd_base.c+1−1

@@ -600,7 +600,7 @@ static netdev_tx_t ctucan_start_xmit(struct sk_buff skb, struct net_device nde · 599 unmodified lines
600	bool ok;	600	bool ok;
601	unsigned long flags;	601	unsigned long flags;
602		602
603	if (can_dropped_invalid_skb(ndev, skb))	603	if (can_dev_dropped_skb(ndev, skb))
604	return NETDEV_TX_OK;	604	return NETDEV_TX_OK;
605		605
606	if (unlikely(!CTU_CAN_FD_TXTNF(priv))) {	606	if (unlikely(!CTU_CAN_FD_TXTNF(priv))) {

drivers/net/can/dev/skb.c+1−9

  */
 #include <linux/can/dev.h>
-#include <linux/can/netlink.h>
 #include <linux/module.h>
 #define MOD_DESC "CAN device driver interface"
 /* Drop a given socketbuffer if it does not contain a valid CAN frame. */
 bool can_dropped_invalid_skb(struct net_device *dev, struct sk_buff *skb)
 {
-	struct can_priv *priv = netdev_priv(dev);
 	switch (ntohs(skb->protocol)) {
 	case ETH_P_CAN:
 		if (!can_is_can_skb(skb))
 		goto inval_skb;
 	}
-	if (!can_skb_headroom_valid(dev, skb)) {
+	if (!can_skb_headroom_valid(dev, skb))
 		goto inval_skb;
-	} else if (priv->ctrlmode & CAN_CTRLMODE_LISTENONLY) {
-		netdev_info_once(dev,
-				 "interface in listen only mode, dropping skb\n");
-		goto inval_skb;
-	}
 	return false;

drivers/net/can/flexcan/flexcan-core.c+1−1

@@ -742,7 +742,7 @@ static netdev_tx_t flexcan_start_xmit(struct sk_buff skb, struct net_device de · 741 unmodified lines
742	u32 ctrl = FLEXCAN_MB_CODE_TX_DATA \| ((can_fd_len2dlc(cfd->len)) << 16);	742	u32 ctrl = FLEXCAN_MB_CODE_TX_DATA \| ((can_fd_len2dlc(cfd->len)) << 16);
743	int i;	743	int i;
744		744
745	if (can_dropped_invalid_skb(dev, skb))	745	if (can_dev_dropped_skb(dev, skb))
746	return NETDEV_TX_OK;	746	return NETDEV_TX_OK;
747		747
748	netif_stop_queue(dev);	748	netif_stop_queue(dev);

drivers/net/can/grcan.c+1−1

@@ -1345,7 +1345,7 @@ static netdev_tx_t grcan_start_xmit(struct sk_buff *skb, · 1344 unmodified lines
1345	unsigned long flags;	1345	unsigned long flags;
1346	u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;	1346	u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
1347		1347
1348	if (can_dropped_invalid_skb(dev, skb))	1348	if (can_dev_dropped_skb(dev, skb))
1349	return NETDEV_TX_OK;	1349	return NETDEV_TX_OK;
1350		1350
1351	/* Trying to transmit in silent mode will generate error interrupts, but	1351	/* Trying to transmit in silent mode will generate error interrupts, but

drivers/net/can/ifi_canfd/ifi_canfd.c+1−1

@@ -860,7 +860,7 @@ static netdev_tx_t ifi_canfd_start_xmit(struct sk_buff *skb, · 859 unmodified lines
860	u32 txst, txid, txdlc;	860	u32 txst, txid, txdlc;
861	int i;	861	int i;
862		862
863	if (can_dropped_invalid_skb(ndev, skb))	863	if (can_dev_dropped_skb(ndev, skb))
864	return NETDEV_TX_OK;	864	return NETDEV_TX_OK;
865		865
866	/* Check if the TX buffer is full */	866	/* Check if the TX buffer is full */

drivers/net/can/janz-ican3.c+1−1

@@ -1693,7 +1693,7 @@ static netdev_tx_t ican3_xmit(struct sk_buff skb, struct net_device ndev) · 1692 unmodified lines
1693	void __iomem *desc_addr;	1693	void __iomem *desc_addr;
1694	unsigned long flags;	1694	unsigned long flags;
1695		1695
1696	if (can_dropped_invalid_skb(ndev, skb))	1696	if (can_dev_dropped_skb(ndev, skb))
1697	return NETDEV_TX_OK;	1697	return NETDEV_TX_OK;
1698		1698
1699	spin_lock_irqsave(&mod->lock, flags);	1699	spin_lock_irqsave(&mod->lock, flags);

drivers/net/can/kvaser_pciefd.c+1−1

@@ -772,7 +772,7 @@ static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, · 771 unmodified lines
772	int nwords;	772	int nwords;
773	u8 count;	773	u8 count;
774		774
775	if (can_dropped_invalid_skb(netdev, skb))	775	if (can_dev_dropped_skb(netdev, skb))
776	return NETDEV_TX_OK;	776	return NETDEV_TX_OK;
777		777
778	nwords = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);	778	nwords = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);

drivers/net/can/m_can/m_can.c+1−1

@@ -1721,7 +1721,7 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, · 1720 unmodified lines
1721	{	1721	{
1722	struct m_can_classdev *cdev = netdev_priv(dev);	1722	struct m_can_classdev *cdev = netdev_priv(dev);
1723		1723
1724	if (can_dropped_invalid_skb(dev, skb))	1724	if (can_dev_dropped_skb(dev, skb))
1725	return NETDEV_TX_OK;	1725	return NETDEV_TX_OK;
1726		1726
1727	if (cdev->is_peripheral) {	1727	if (cdev->is_peripheral) {

drivers/net/can/mscan/mscan.c+1−1

@@ -191,7 +191,7 @@ static netdev_tx_t mscan_start_xmit(struct sk_buff skb, struct net_device dev) · 190 unmodified lines
191	int i, rtr, buf_id;	191	int i, rtr, buf_id;
192	u32 can_id;	192	u32 can_id;
193		193
194	if (can_dropped_invalid_skb(dev, skb))	194	if (can_dev_dropped_skb(dev, skb))
195	return NETDEV_TX_OK;	195	return NETDEV_TX_OK;
196		196
197	out_8(&regs->cantier, 0);	197	out_8(&regs->cantier, 0);

drivers/net/can/pch_can.c+1−1

@@ -882,7 +882,7 @@ static netdev_tx_t pch_xmit(struct sk_buff skb, struct net_device ndev) · 881 unmodified lines
882	int i;	882	int i;
883	u32 id2;	883	u32 id2;
884		884
885	if (can_dropped_invalid_skb(ndev, skb))	885	if (can_dev_dropped_skb(ndev, skb))
886	return NETDEV_TX_OK;	886	return NETDEV_TX_OK;
887		887
888	tx_obj_no = priv->tx_obj;	888	tx_obj_no = priv->tx_obj;

drivers/net/can/peak_canfd/peak_canfd.c+1−1

@@ -651,7 +651,7 @@ static netdev_tx_t peak_canfd_start_xmit(struct sk_buff *skb, · 650 unmodified lines
651	int room_left;	651	int room_left;
652	u8 len;	652	u8 len;
653		653
654	if (can_dropped_invalid_skb(ndev, skb))	654	if (can_dev_dropped_skb(ndev, skb))
655	return NETDEV_TX_OK;	655	return NETDEV_TX_OK;
656		656
657	msg_size = ALIGN(sizeof(*msg) + cf->len, 4);	657	msg_size = ALIGN(sizeof(*msg) + cf->len, 4);

drivers/net/can/rcar/rcar_can.c+1−1

@@ -590,7 +590,7 @@ static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, · 589 unmodified lines
590	struct can_frame cf = (struct can_frame )skb->data;	590	struct can_frame cf = (struct can_frame )skb->data;
591	u32 data, i;	591	u32 data, i;
592		592
593	if (can_dropped_invalid_skb(ndev, skb))	593	if (can_dev_dropped_skb(ndev, skb))
594	return NETDEV_TX_OK;	594	return NETDEV_TX_OK;
595		595
596	if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */	596	if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */

drivers/net/can/rcar/rcar_canfd.c+5−10

 /* RSCFDnCFDGERFL / RSCFDnGERFL */
 #define RCANFD_GERFL_EEF0_7		GENMASK(23, 16)
-#define RCANFD_GERFL_EEF1		BIT(17)
+#define RCANFD_GERFL_EEF(ch)		BIT(16 + (ch))
-#define RCANFD_GERFL_EEF0		BIT(16)
 #define RCANFD_GERFL_CMPOF		BIT(3)	/* CAN FD only */
 #define RCANFD_GERFL_THLES		BIT(2)
 #define RCANFD_GERFL_MES		BIT(1)
 #define RCANFD_GERFL_ERR(gpriv, x) \
 	((x) & (reg_v3u(gpriv, RCANFD_GERFL_EEF0_7, \
-			RCANFD_GERFL_EEF0 | RCANFD_GERFL_EEF1) | \
+			RCANFD_GERFL_EEF(0) | RCANFD_GERFL_EEF(1)) | \
 		RCANFD_GERFL_MES | \
 		((gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0)))
 	u32 ridx = ch + RCANFD_RFFIFO_IDX;
 	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
-	if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
+	if (gerfl & RCANFD_GERFL_EEF(ch)) {
-		netdev_dbg(ndev, "Ch0: ECC Error flag\n");
+		netdev_dbg(ndev, "Ch%u: ECC Error flag\n", ch);
-		stats->tx_dropped++;
-	}
-	if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
-		netdev_dbg(ndev, "Ch1: ECC Error flag\n");
 		stats->tx_dropped++;
 	}
 	if (gerfl & RCANFD_GERFL_MES) {
 	unsigned long flags;
 	u32 ch = priv->channel;
-	if (can_dropped_invalid_skb(ndev, skb))
+	if (can_dev_dropped_skb(ndev, skb))
 		return NETDEV_TX_OK;
 	if (cf->can_id & CAN_EFF_FLAG) {

drivers/net/can/sja1000/sja1000.c+1−1

@@ -291,7 +291,7 @@ static netdev_tx_t sja1000_start_xmit(struct sk_buff *skb, · 290 unmodified lines
291	u8 cmd_reg_val = 0x00;	291	u8 cmd_reg_val = 0x00;
292	int i;	292	int i;
293		293
294	if (can_dropped_invalid_skb(dev, skb))	294	if (can_dev_dropped_skb(dev, skb))
295	return NETDEV_TX_OK;	295	return NETDEV_TX_OK;
296		296
297	netif_stop_queue(dev);	297	netif_stop_queue(dev);

drivers/net/can/slcan/slcan-core.c+1−1

@@ -594,7 +594,7 @@ static netdev_tx_t slcan_netdev_xmit(struct sk_buff *skb, · 593 unmodified lines
594	{	594	{
595	struct slcan *sl = netdev_priv(dev);	595	struct slcan *sl = netdev_priv(dev);
596		596
597	if (can_dropped_invalid_skb(dev, skb))	597	if (can_dev_dropped_skb(dev, skb))
598	return NETDEV_TX_OK;	598	return NETDEV_TX_OK;
599		599
600	spin_lock(&sl->lock);	600	spin_lock(&sl->lock);

drivers/net/can/softing/softing_main.c+1−1

@@ -60,7 +60,7 @@ static netdev_tx_t softing_netdev_start_xmit(struct sk_buff *skb, · 59 unmodified lines
60	struct can_frame cf = (struct can_frame )skb->data;	60	struct can_frame cf = (struct can_frame )skb->data;
61	uint8_t buf[DPRAM_TX_SIZE];	61	uint8_t buf[DPRAM_TX_SIZE];
62		62
63	if (can_dropped_invalid_skb(dev, skb))	63	if (can_dev_dropped_skb(dev, skb))
64	return NETDEV_TX_OK;	64	return NETDEV_TX_OK;
65		65
66	spin_lock(&card->spin);	66	spin_lock(&card->spin);

drivers/net/can/spi/hi311x.c+1−1

@@ -373,7 +373,7 @@ static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb, · 372 unmodified lines
373	return NETDEV_TX_BUSY;	373	return NETDEV_TX_BUSY;
374	}	374	}
375		375
376	if (can_dropped_invalid_skb(net, skb))	376	if (can_dev_dropped_skb(net, skb))
377	return NETDEV_TX_OK;	377	return NETDEV_TX_OK;
378		378
379	netif_stop_queue(net);	379	netif_stop_queue(net);

drivers/net/can/spi/mcp251x.c+1−1

@@ -789,7 +789,7 @@ static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb, · 788 unmodified lines
789	return NETDEV_TX_BUSY;	789	return NETDEV_TX_BUSY;
790	}	790	}
791		791
792	if (can_dropped_invalid_skb(net, skb))	792	if (can_dev_dropped_skb(net, skb))
793	return NETDEV_TX_OK;	793	return NETDEV_TX_OK;
794		794
795	netif_stop_queue(net);	795	netif_stop_queue(net);

drivers/net/can/spi/mcp251xfd/mcp251xfd-tx.c+1−1

@@ -172,7 +172,7 @@ netdev_tx_t mcp251xfd_start_xmit(struct sk_buff *skb, · 171 unmodified lines
172	u8 tx_head;	172	u8 tx_head;
173	int err;	173	int err;
174		174
175	if (can_dropped_invalid_skb(ndev, skb))	175	if (can_dev_dropped_skb(ndev, skb))
176	return NETDEV_TX_OK;	176	return NETDEV_TX_OK;
177		177
178	if (mcp251xfd_tx_busy(priv, tx_ring))	178	if (mcp251xfd_tx_busy(priv, tx_ring))

drivers/net/can/sun4i_can.c+1−1

@@ -429,7 +429,7 @@ static netdev_tx_t sun4ican_start_xmit(struct sk_buff skb, struct net_device d · 428 unmodified lines
429	canid_t id;	429	canid_t id;
430	int i;	430	int i;
431		431
432	if (can_dropped_invalid_skb(dev, skb))	432	if (can_dev_dropped_skb(dev, skb))
433	return NETDEV_TX_OK;	433	return NETDEV_TX_OK;
434		434
435	netif_stop_queue(dev);	435	netif_stop_queue(dev);

drivers/net/can/ti_hecc.c+1−1

@@ -470,7 +470,7 @@ static netdev_tx_t ti_hecc_xmit(struct sk_buff skb, struct net_device ndev) · 469 unmodified lines
470	u32 mbxno, mbx_mask, data;	470	u32 mbxno, mbx_mask, data;
471	unsigned long flags;	471	unsigned long flags;
472		472
473	if (can_dropped_invalid_skb(ndev, skb))	473	if (can_dev_dropped_skb(ndev, skb))
474	return NETDEV_TX_OK;	474	return NETDEV_TX_OK;
475		475
476	mbxno = get_tx_head_mb(priv);	476	mbxno = get_tx_head_mb(priv);

drivers/net/can/usb/ems_usb.c+1−1

@@ -747,7 +747,7 @@ static netdev_tx_t ems_usb_start_xmit(struct sk_buff skb, struct net_device ne · 746 unmodified lines
747	size_t size = CPC_HEADER_SIZE + CPC_MSG_HEADER_LEN	747	size_t size = CPC_HEADER_SIZE + CPC_MSG_HEADER_LEN
748	+ sizeof(struct cpc_can_msg);	748	+ sizeof(struct cpc_can_msg);
749		749
750	if (can_dropped_invalid_skb(netdev, skb))	750	if (can_dev_dropped_skb(netdev, skb))
751	return NETDEV_TX_OK;	751	return NETDEV_TX_OK;
752		752
753	/* create a URB, and a buffer for it, and copy the data to the URB */	753	/* create a URB, and a buffer for it, and copy the data to the URB */

drivers/net/can/usb/esd_usb.c+1−1

@@ -725,7 +725,7 @@ static netdev_tx_t esd_usb_start_xmit(struct sk_buff *skb, · 724 unmodified lines
725	int ret = NETDEV_TX_OK;	725	int ret = NETDEV_TX_OK;
726	size_t size = sizeof(struct esd_usb_msg);	726	size_t size = sizeof(struct esd_usb_msg);
727		727
728	if (can_dropped_invalid_skb(netdev, skb))	728	if (can_dev_dropped_skb(netdev, skb))
729	return NETDEV_TX_OK;	729	return NETDEV_TX_OK;
730		730
731	/* create a URB, and a buffer for it, and copy the data to the URB */	731	/* create a URB, and a buffer for it, and copy the data to the URB */

drivers/net/can/usb/etas_es58x/es58x_core.c+1−1

@@ -1913,7 +1913,7 @@ static netdev_tx_t es58x_start_xmit(struct sk_buff *skb, · 1912 unmodified lines
1913	unsigned int frame_len;	1913	unsigned int frame_len;
1914	int ret;	1914	int ret;
1915		1915
1916	if (can_dropped_invalid_skb(netdev, skb)) {	1916	if (can_dev_dropped_skb(netdev, skb)) {
1917	if (priv->tx_urb)	1917	if (priv->tx_urb)
1918	goto xmit_commit;	1918	goto xmit_commit;
1919	return NETDEV_TX_OK;	1919	return NETDEV_TX_OK;

drivers/net/can/usb/gs_usb.c+1−1

@@ -723,7 +723,7 @@ static netdev_tx_t gs_can_start_xmit(struct sk_buff *skb, · 722 unmodified lines
723	unsigned int idx;	723	unsigned int idx;
724	struct gs_tx_context *txc;	724	struct gs_tx_context *txc;
725		725
726	if (can_dropped_invalid_skb(netdev, skb))	726	if (can_dev_dropped_skb(netdev, skb))
727	return NETDEV_TX_OK;	727	return NETDEV_TX_OK;
728		728
729	/* find an empty context to keep track of transmission */	729	/* find an empty context to keep track of transmission */

drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c+1−1

@@ -570,7 +570,7 @@ static netdev_tx_t kvaser_usb_start_xmit(struct sk_buff *skb, · 569 unmodified lines
570	unsigned int i;	570	unsigned int i;
571	unsigned long flags;	571	unsigned long flags;
572		572
573	if (can_dropped_invalid_skb(netdev, skb))	573	if (can_dev_dropped_skb(netdev, skb))
574	return NETDEV_TX_OK;	574	return NETDEV_TX_OK;
575		575
576	urb = usb_alloc_urb(0, GFP_ATOMIC);	576	urb = usb_alloc_urb(0, GFP_ATOMIC);

drivers/net/can/usb/mcba_usb.c+1−1

@@ -311,7 +311,7 @@ static netdev_tx_t mcba_usb_start_xmit(struct sk_buff *skb, · 310 unmodified lines
311	.cmd_id = MBCA_CMD_TRANSMIT_MESSAGE_EV	311	.cmd_id = MBCA_CMD_TRANSMIT_MESSAGE_EV
312	};	312	};
313		313
314	if (can_dropped_invalid_skb(netdev, skb))	314	if (can_dev_dropped_skb(netdev, skb))
315	return NETDEV_TX_OK;	315	return NETDEV_TX_OK;
316		316
317	ctx = mcba_usb_get_free_ctx(priv, cf);	317	ctx = mcba_usb_get_free_ctx(priv, cf);

drivers/net/can/usb/peak_usb/pcan_usb_core.c+1−1

@@ -351,7 +351,7 @@ static netdev_tx_t peak_usb_ndo_start_xmit(struct sk_buff *skb, · 350 unmodified lines
351	int i, err;	351	int i, err;
352	size_t size = dev->adapter->tx_buffer_size;	352	size_t size = dev->adapter->tx_buffer_size;
353		353
354	if (can_dropped_invalid_skb(netdev, skb))	354	if (can_dev_dropped_skb(netdev, skb))
355	return NETDEV_TX_OK;	355	return NETDEV_TX_OK;
356		356
357	for (i = 0; i < PCAN_USB_MAX_TX_URBS; i++)	357	for (i = 0; i < PCAN_USB_MAX_TX_URBS; i++)

drivers/net/can/usb/ucan.c+1−1

@@ -1120,7 +1120,7 @@ static netdev_tx_t ucan_start_xmit(struct sk_buff *skb, · 1119 unmodified lines
1120	struct can_frame cf = (struct can_frame )skb->data;	1120	struct can_frame cf = (struct can_frame )skb->data;
1121		1121
1122	/* check skb */	1122	/* check skb */
1123	if (can_dropped_invalid_skb(netdev, skb))	1123	if (can_dev_dropped_skb(netdev, skb))
1124	return NETDEV_TX_OK;	1124	return NETDEV_TX_OK;
1125		1125
1126	/* allocate a context and slow down tx path, if fifo state is low */	1126	/* allocate a context and slow down tx path, if fifo state is low */

drivers/net/can/usb/usb_8dev.c+1−1

@@ -602,7 +602,7 @@ static netdev_tx_t usb_8dev_start_xmit(struct sk_buff *skb, · 601 unmodified lines
602	int i, err;	602	int i, err;
603	size_t size = sizeof(struct usb_8dev_tx_msg);	603	size_t size = sizeof(struct usb_8dev_tx_msg);
604		604
605	if (can_dropped_invalid_skb(netdev, skb))	605	if (can_dev_dropped_skb(netdev, skb))
606	return NETDEV_TX_OK;	606	return NETDEV_TX_OK;
607		607
608	/* create a URB, and a buffer for it, and copy the data to the URB */	608	/* create a URB, and a buffer for it, and copy the data to the URB */

drivers/net/can/xilinx_can.c+1−1

@@ -743,7 +743,7 @@ static netdev_tx_t xcan_start_xmit(struct sk_buff skb, struct net_device ndev) · 742 unmodified lines
743	struct xcan_priv *priv = netdev_priv(ndev);	743	struct xcan_priv *priv = netdev_priv(ndev);
744	int ret;	744	int ret;
745		745
746	if (can_dropped_invalid_skb(ndev, skb))	746	if (can_dev_dropped_skb(ndev, skb))
747	return NETDEV_TX_OK;	747	return NETDEV_TX_OK;
748		748
749	if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES)	749	if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES)

drivers/net/ethernet/apm/xgene/xgene_enet_main.c+3−1

 	xgene_enet_napi_enable(pdata);
 	ret = xgene_enet_register_irq(ndev);
-	if (ret)
+	if (ret) {
+		xgene_enet_napi_disable(pdata);
 		return ret;
+	}
 	if (ndev->phydev) {
 		phy_start(ndev->phydev);

drivers/net/ethernet/aquantia/atlantic/aq_macsec.c+2−0

 	ret = aq_mss_set_egress_sakey_record(hw, &key_rec, sa_idx);
+	memzero_explicit(&key_rec, sizeof(key_rec));
 	return ret;
 }
 	ret = aq_mss_set_ingress_sakey_record(hw, &sa_key_record, sa_idx);
+	memzero_explicit(&sa_key_record, sizeof(sa_key_record));
 	return ret;
 }

drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c+11−7

 			 u16 table_index)
 {
 	u16 packed_record[18];
+	int ret;
 	if (table_index >= NUMROWS_INGRESSSAKEYRECORD)
 		return -EINVAL;
 	packed_record[16] = rec->key_len & 0x3;
-	return set_raw_ingress_record(hw, packed_record, 18, 2,
+	ret = set_raw_ingress_record(hw, packed_record, 18, 2,
-				      ROWOFFSET_INGRESSSAKEYRECORD +
+				     ROWOFFSET_INGRESSSAKEYRECORD +
-					      table_index);
+				     table_index);
+	memzero_explicit(packed_record, sizeof(packed_record));
+	return ret;
 }
 int aq_mss_set_ingress_sakey_record(struct aq_hw_s *hw,
 	ret = set_raw_egress_record(hw, packed_record, 8, 2,
 				    ROWOFFSET_EGRESSSAKEYRECORD + table_index);
 	if (unlikely(ret))
-		return ret;
+		goto clear_key;
 	ret = set_raw_egress_record(hw, packed_record + 8, 8, 2,
 				    ROWOFFSET_EGRESSSAKEYRECORD + table_index -
 					    32);
-	if (unlikely(ret))
-		return ret;
-	return 0;
+clear_key:
+	memzero_explicit(packed_record, sizeof(packed_record));
+	return ret;
 }
 int aq_mss_set_egress_sakey_record(struct aq_hw_s *hw,

drivers/net/ethernet/broadcom/Kconfig+1−1

@@ -77,7 +77,7 @@ config BCMGENET · 76 unmodified lines
77	select BCM7XXX_PHY	77	select BCM7XXX_PHY
78	select MDIO_BCM_UNIMAC	78	select MDIO_BCM_UNIMAC
79	select DIMLIB	79	select DIMLIB
80	select BROADCOM_PHY if ARCH_BCM2835	80	select BROADCOM_PHY if (ARCH_BCM2835 && PTP_1588_CLOCK_OPTIONAL)
81	help	81	help
82	This driver supports the built-in Ethernet MACs found in the	82	This driver supports the built-in Ethernet MACs found in the
83	Broadcom BCM7xxx Set Top Box family chipset.	83	Broadcom BCM7xxx Set Top Box family chipset.

drivers/net/ethernet/broadcom/bnxt/bnxt.c+45−9

 	return -ENODEV;
 }
-int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset)
+static void bnxt_clear_reservations(struct bnxt *bp, bool fw_reset)
 {
 	struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
-	int rc;
 	if (!BNXT_NEW_RM(bp))
-		return 0; /* no resource reservations required */
+		return; /* no resource reservations required */
-	rc = bnxt_hwrm_func_resc_qcaps(bp, true);
-	if (rc)
-		netdev_err(bp->dev, "resc_qcaps failed\n");
 	hw_resc->resv_cp_rings = 0;
 	hw_resc->resv_stat_ctxs = 0;
 		bp->tx_nr_rings = 0;
 		bp->rx_nr_rings = 0;
 	}
+}
+int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset)
+{
+	int rc;
+	if (!BNXT_NEW_RM(bp))
+		return 0; /* no resource reservations required */
+	rc = bnxt_hwrm_func_resc_qcaps(bp, true);
+	if (rc)
+		netdev_err(bp->dev, "resc_qcaps failed\n");
+	bnxt_clear_reservations(bp, fw_reset);
 	return rc;
 }
 	rcu_read_lock();
 	hlist_for_each_entry_rcu(fltr, head, hash) {
 		if (bnxt_fltr_match(fltr, new_fltr)) {
+			rc = fltr->sw_id;
 			rcu_read_unlock();
-			rc = 0;
 			goto err_free;
 		}
 	}
 	pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
 	struct net_device *netdev = pci_get_drvdata(pdev);
 	struct bnxt *bp = netdev_priv(netdev);
-	int err = 0, off;
+	int retry = 0;
+	int err = 0;
+	int off;
 	netdev_info(bp->dev, "PCI Slot Reset\n");
 		pci_restore_state(pdev);
 		pci_save_state(pdev);
+		bnxt_inv_fw_health_reg(bp);
+		bnxt_try_map_fw_health_reg(bp);
+		/* In some PCIe AER scenarios, firmware may take up to
+		 * 10 seconds to become ready in the worst case.
+		 */
+		do {
+			err = bnxt_try_recover_fw(bp);
+			if (!err)
+				break;
+			retry++;
+		} while (retry < BNXT_FW_SLOT_RESET_RETRY);
+		if (err) {
+			dev_err(&pdev->dev, "Firmware not ready\n");
+			goto reset_exit;
+		}
 		err = bnxt_hwrm_func_reset(bp);
 		if (!err)
 			result = PCI_ERS_RESULT_RECOVERED;
+		bnxt_ulp_irq_stop(bp);
+		bnxt_clear_int_mode(bp);
+		err = bnxt_init_int_mode(bp);
+		bnxt_ulp_irq_restart(bp, err);
 	}
+reset_exit:
+	bnxt_clear_reservations(bp, true);
 	rtnl_unlock();
 	return result;

drivers/net/ethernet/broadcom/bnxt/bnxt.h+1−0

@@ -1621,6 +1621,7 @@ struct bnxt_fw_health { · 1620 unmodified lines
1621		1621
1622	#define BNXT_FW_RETRY 5	1622	#define BNXT_FW_RETRY 5
1623	#define BNXT_FW_IF_RETRY 10	1623	#define BNXT_FW_IF_RETRY 10
		1624	#define BNXT_FW_SLOT_RESET_RETRY 4
1624		1625
1625	enum board_idx {	1626	enum board_idx {
1626	BCM57301,	1627	BCM57301,

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c+1−1

@@ -162,7 +162,7 @@ static int bnxt_set_coalesce(struct net_device *dev, · 161 unmodified lines
162	}	162	}
163		163
164	reset_coalesce:	164	reset_coalesce:
165	if (netif_running(dev)) {	165	if (test_bit(BNXT_STATE_OPEN, &bp->state)) {
166	if (update_stats) {	166	if (update_stats) {
167	rc = bnxt_close_nic(bp, true, false);	167	rc = bnxt_close_nic(bp, true, false);
168	if (!rc)	168	if (!rc)

drivers/net/ethernet/broadcom/bnxt/bnxt_hwrm.c+2−1

@@ -476,7 +476,8 @@ static int __hwrm_send(struct bnxt bp, struct bnxt_hwrm_ctx ctx) · 475 unmodified lines
476	memset(ctx->resp, 0, PAGE_SIZE);	476	memset(ctx->resp, 0, PAGE_SIZE);
477		477
478	req_type = le16_to_cpu(ctx->req->req_type);	478	req_type = le16_to_cpu(ctx->req->req_type);
479	if (BNXT_NO_FW_ACCESS(bp) && req_type != HWRM_FUNC_RESET) {	479	if (BNXT_NO_FW_ACCESS(bp) &&
		480	(req_type != HWRM_FUNC_RESET && req_type != HWRM_VER_GET)) {
480	netdev_dbg(bp->dev, "hwrm req_type 0x%x skipped, FW channel down\n",	481	netdev_dbg(bp->dev, "hwrm req_type 0x%x skipped, FW channel down\n",
481	req_type);	482	req_type);
482	goto exit;	483	goto exit;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c+1−0

@@ -1301,6 +1301,7 @@ static int cxgb_up(struct adapter *adap) · 1300 unmodified lines
1301	if (ret < 0) {	1301	if (ret < 0) {
1302	CH_ERR(adap, "failed to bind qsets, err %d\n", ret);	1302	CH_ERR(adap, "failed to bind qsets, err %d\n", ret);
1303	t3_intr_disable(adap);	1303	t3_intr_disable(adap);
		1304	quiesce_rx(adap);
1304	free_irq_resources(adap);	1305	free_irq_resources(adap);
1305	err = ret;	1306	err = ret;
1306	goto out;	1307	goto out;

drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c+1−1

@@ -858,7 +858,7 @@ static int cxgb4vf_open(struct net_device *dev) · 857 unmodified lines
858	*/	858	*/
859	err = t4vf_update_port_info(pi);	859	err = t4vf_update_port_info(pi);
860	if (err < 0)	860	if (err < 0)
861	return err;	861	goto err_unwind;
862		862
863	/*	863	/*
864	* Note that this interface is up and start everything up ...	864	* Note that this interface is up and start everything up ...

drivers/net/ethernet/freescale/fman/mac.c+9−0

 	return err;
 }
+static int mac_remove(struct platform_device *pdev)
+{
+	struct mac_device *mac_dev = platform_get_drvdata(pdev);
+	platform_device_unregister(mac_dev->priv->eth_dev);
+	return 0;
+}
 static struct platform_driver mac_driver = {
 	.driver = {
 		.name		= KBUILD_MODNAME,
 		.of_match_table	= mac_match,
 	},
 	.probe		= mac_probe,
+	.remove		= mac_remove,
 };
 builtin_platform_driver(mac_driver);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+5−3

 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode,
 			       u8 *priority)
 {
+	struct hclge_vport *vport = hclge_get_vport(h);
 	if (dscp >= HNAE3_MAX_DSCP)
 		return -EINVAL;
 	if (tc_mode)
-		*tc_mode = h->kinfo.tc_map_mode;
+		*tc_mode = vport->nic.kinfo.tc_map_mode;
 	if (priority)
-		*priority = h->kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 :
+		*priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 :
-			    h->kinfo.dscp_prio[dscp];
+			    vport->nic.kinfo.dscp_prio[dscp];
 	return 0;
 }

drivers/net/ethernet/ibm/ibmveth.c+2−1

@@ -1757,7 +1757,8 @@ static int ibmveth_probe(struct vio_dev dev, const struct vio_device_id id) · 1756 unmodified lines
1757	kobject_uevent(kobj, KOBJ_ADD);	1757	kobject_uevent(kobj, KOBJ_ADD);
1758	}	1758	}
1759		1759
1760	rc = netif_set_real_num_tx_queues(netdev, ibmveth_real_max_tx_queues());	1760	rc = netif_set_real_num_tx_queues(netdev, min(num_online_cpus(),
		1761	IBMVETH_DEFAULT_QUEUES));
1761	if (rc) {	1762	if (rc) {
1762	netdev_dbg(netdev, "failed to set number of tx queues rc=%d\n",	1763	netdev_dbg(netdev, "failed to set number of tx queues rc=%d\n",
1763	rc);	1764	rc);

drivers/net/ethernet/ibm/ibmveth.h+1−0

@@ -100,6 +100,7 @@ static inline long h_illan_attributes(unsigned long unit_address, · 99 unmodified lines
100	#define IBMVETH_MAX_BUF_SIZE (1024 * 128)	100	#define IBMVETH_MAX_BUF_SIZE (1024 * 128)
101	#define IBMVETH_MAX_TX_BUF_SIZE (1024 * 64)	101	#define IBMVETH_MAX_TX_BUF_SIZE (1024 * 64)
102	#define IBMVETH_MAX_QUEUES 16U	102	#define IBMVETH_MAX_QUEUES 16U
		103	#define IBMVETH_DEFAULT_QUEUES 8U
103		104
104	static int pool_size[] = { 512, 1024 * 2, 1024 * 16, 1024 * 32, 1024 * 64 };	105	static int pool_size[] = { 512, 1024 * 2, 1024 * 16, 1024 * 32, 1024 * 64 };
105	static int pool_count[] = { 256, 512, 256, 256, 256 };	106	static int pool_count[] = { 256, 512, 256, 256, 256 };

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c+2−0

 		list_for_each_entry(f, &adapter->vlan_filter_list, list) {
 			if (f->is_new_vlan) {
 				f->is_new_vlan = false;
+				if (!f->vlan.vid)
+					continue;
 				if (f->vlan.tpid == ETH_P_8021Q)
 					set_bit(f->vlan.vid,
 						adapter->vsi.active_cvlans);

drivers/net/ethernet/intel/ice/ice_base.c+1−1

@@ -958,7 +958,7 @@ ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src, · 957 unmodified lines
958	* associated to the queue to schedule NAPI handler	958	* associated to the queue to schedule NAPI handler
959	*/	959	*/
960	q_vector = ring->q_vector;	960	q_vector = ring->q_vector;
961	if (q_vector)	961	if (q_vector && !(vsi->vf && ice_is_vf_disabled(vsi->vf)))
962	ice_trigger_sw_intr(hw, q_vector);	962	ice_trigger_sw_intr(hw, q_vector);
963		963
964	status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx,	964	status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx,

drivers/net/ethernet/intel/ice/ice_lib.c+25−0

@@ -2239,6 +2239,31 @@ int ice_vsi_stop_xdp_tx_rings(struct ice_vsi *vsi) · 2238 unmodified lines
2239	return ice_vsi_stop_tx_rings(vsi, ICE_NO_RESET, 0, vsi->xdp_rings, vsi->num_xdp_txq);	2239	return ice_vsi_stop_tx_rings(vsi, ICE_NO_RESET, 0, vsi->xdp_rings, vsi->num_xdp_txq);
2240	}	2240	}
2241		2241
		2242	/**
		2243	* ice_vsi_is_rx_queue_active
		2244	* @vsi: the VSI being configured
		2245	*
		2246	* Return true if at least one queue is active.
		2247	*/
		2248	bool ice_vsi_is_rx_queue_active(struct ice_vsi *vsi)
		2249	{
		2250	struct ice_pf *pf = vsi->back;
		2251	struct ice_hw *hw = &pf->hw;
		2252	int i;
		2253
		2254	ice_for_each_rxq(vsi, i) {
		2255	u32 rx_reg;
		2256	int pf_q;
		2257
		2258	pf_q = vsi->rxq_map[i];
		2259	rx_reg = rd32(hw, QRX_CTRL(pf_q));
		2260	if (rx_reg & QRX_CTRL_QENA_STAT_M)
		2261	return true;
		2262	}
		2263
		2264	return false;
		2265	}
		2266
2242	/**	2267	/**
2243	* ice_vsi_is_vlan_pruning_ena - check if VLAN pruning is enabled or not	2268	* ice_vsi_is_vlan_pruning_ena - check if VLAN pruning is enabled or not
2244	* @vsi: VSI to check whether or not VLAN pruning is enabled.	2269	* @vsi: VSI to check whether or not VLAN pruning is enabled.

drivers/net/ethernet/intel/ice/ice_lib.h+1−0

@@ -129,4 +129,5 @@ u16 ice_vsi_num_non_zero_vlans(struct ice_vsi *vsi); · 128 unmodified lines
129	bool ice_is_feature_supported(struct ice_pf *pf, enum ice_feature f);	129	bool ice_is_feature_supported(struct ice_pf *pf, enum ice_feature f);
130	void ice_clear_feature_support(struct ice_pf *pf, enum ice_feature f);	130	void ice_clear_feature_support(struct ice_pf *pf, enum ice_feature f);
131	void ice_init_feature_support(struct ice_pf *pf);	131	void ice_init_feature_support(struct ice_pf *pf);
		132	bool ice_vsi_is_rx_queue_active(struct ice_vsi *vsi);
132	#endif /* !_ICE_LIB_H_ */	133	#endif /* !_ICE_LIB_H_ */

drivers/net/ethernet/intel/ice/ice_vf_lib.c+4−1

@@ -576,7 +576,10 @@ int ice_reset_vf(struct ice_vf *vf, u32 flags) · 575 unmodified lines
576	return -EINVAL;	576	return -EINVAL;
577	}	577	}
578	ice_vsi_stop_lan_tx_rings(vsi, ICE_NO_RESET, vf->vf_id);	578	ice_vsi_stop_lan_tx_rings(vsi, ICE_NO_RESET, vf->vf_id);
579	ice_vsi_stop_all_rx_rings(vsi);	579
		580	if (ice_vsi_is_rx_queue_active(vsi))
		581	ice_vsi_stop_all_rx_rings(vsi);
		582
580	dev_dbg(dev, "VF is already disabled, there is no need for resetting it, telling VM, all is fine %d\n",	583	dev_dbg(dev, "VF is already disabled, there is no need for resetting it, telling VM, all is fine %d\n",
581	vf->vf_id);	584	vf->vf_id);
582	return 0;	585	return 0;

drivers/net/ethernet/marvell/mv643xx_eth.c+1−0

@@ -2481,6 +2481,7 @@ out_free: · 2480 unmodified lines
2481	for (i = 0; i < mp->rxq_count; i++)	2481	for (i = 0; i < mp->rxq_count; i++)
2482	rxq_deinit(mp->rxq + i);	2482	rxq_deinit(mp->rxq + i);
2483	out:	2483	out:
		2484	napi_disable(&mp->napi);
2484	free_irq(dev->irq, dev);	2485	free_irq(dev->irq, dev);
2485		2486
2486	return err;	2487	return err;

drivers/net/ethernet/marvell/octeontx2/Kconfig+2−0

 	tristate "Marvell OcteonTX2 NIC Physical Function driver"
 	select OCTEONTX2_MBOX
 	select NET_DEVLINK
+	depends on MACSEC || !MACSEC
 	depends on (64BIT && COMPILE_TEST) || ARM64
 	select DIMLIB
 	depends on PCI
 	depends on PTP_1588_CLOCK_OPTIONAL
+	depends on MACSEC || !MACSEC
 	help
 	  This driver supports Marvell's OcteonTX2 NIC physical function.

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c+1−0

@@ -898,6 +898,7 @@ static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) · 897 unmodified lines
898	}	898	}
899		899
900	sq->head = 0;	900	sq->head = 0;
		901	sq->cons_head = 0;
901	sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;	902	sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;
902	sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb;	903	sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb;
903	/* Set SQE threshold to 10% of total SQEs */	904	/* Set SQE threshold to 10% of total SQEs */

drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c+105−30

@@ -15,6 +15,7 @@ · 14 unmodified lines
15	#include <net/ip.h>	15	#include <net/ip.h>
16	#include <linux/bpf.h>	16	#include <linux/bpf.h>
17	#include <linux/bpf_trace.h>	17	#include <linux/bpf_trace.h>
		18	#include <linux/bitfield.h>
18		19
19	#include "otx2_reg.h"	20	#include "otx2_reg.h"
20	#include "otx2_common.h"	21	#include "otx2_common.h"
@@ -1171,6 +1172,59 @@ int otx2_set_real_num_queues(struct net_device *netdev, · 1150 unmodified lines
1171	}	1172	}
1172	EXPORT_SYMBOL(otx2_set_real_num_queues);	1173	EXPORT_SYMBOL(otx2_set_real_num_queues);
1173		1174
		1175	static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = {
		1176	"NIX_SQOPERR_OOR",
		1177	"NIX_SQOPERR_CTX_FAULT",
		1178	"NIX_SQOPERR_CTX_POISON",
		1179	"NIX_SQOPERR_DISABLED",
		1180	"NIX_SQOPERR_SIZE_ERR",
		1181	"NIX_SQOPERR_OFLOW",
		1182	"NIX_SQOPERR_SQB_NULL",
		1183	"NIX_SQOPERR_SQB_FAULT",
		1184	"NIX_SQOPERR_SQE_SZ_ZERO",
		1185	};
		1186
		1187	static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = {
		1188	"NIX_MNQERR_SQ_CTX_FAULT",
		1189	"NIX_MNQERR_SQ_CTX_POISON",
		1190	"NIX_MNQERR_SQB_FAULT",
		1191	"NIX_MNQERR_SQB_POISON",
		1192	"NIX_MNQERR_TOTAL_ERR",
		1193	"NIX_MNQERR_LSO_ERR",
		1194	"NIX_MNQERR_CQ_QUERY_ERR",
		1195	"NIX_MNQERR_MAX_SQE_SIZE_ERR",
		1196	"NIX_MNQERR_MAXLEN_ERR",
		1197	"NIX_MNQERR_SQE_SIZEM1_ZERO",
		1198	};
		1199
		1200	static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = {
		1201	"NIX_SND_STATUS_GOOD",
		1202	"NIX_SND_STATUS_SQ_CTX_FAULT",
		1203	"NIX_SND_STATUS_SQ_CTX_POISON",
		1204	"NIX_SND_STATUS_SQB_FAULT",
		1205	"NIX_SND_STATUS_SQB_POISON",
		1206	"NIX_SND_STATUS_HDR_ERR",
		1207	"NIX_SND_STATUS_EXT_ERR",
		1208	"NIX_SND_STATUS_JUMP_FAULT",
		1209	"NIX_SND_STATUS_JUMP_POISON",
		1210	"NIX_SND_STATUS_CRC_ERR",
		1211	"NIX_SND_STATUS_IMM_ERR",
		1212	"NIX_SND_STATUS_SG_ERR",
		1213	"NIX_SND_STATUS_MEM_ERR",
		1214	"NIX_SND_STATUS_INVALID_SUBDC",
		1215	"NIX_SND_STATUS_SUBDC_ORDER_ERR",
		1216	"NIX_SND_STATUS_DATA_FAULT",
		1217	"NIX_SND_STATUS_DATA_POISON",
		1218	"NIX_SND_STATUS_NPC_DROP_ACTION",
		1219	"NIX_SND_STATUS_LOCK_VIOL",
		1220	"NIX_SND_STATUS_NPC_UCAST_CHAN_ERR",
		1221	"NIX_SND_STATUS_NPC_MCAST_CHAN_ERR",
		1222	"NIX_SND_STATUS_NPC_MCAST_ABORT",
		1223	"NIX_SND_STATUS_NPC_VTAG_PTR_ERR",
		1224	"NIX_SND_STATUS_NPC_VTAG_SIZE_ERR",
		1225	"NIX_SND_STATUS_SEND_STATS_ERR",
		1226	};
		1227
1174	static irqreturn_t otx2_q_intr_handler(int irq, void *data)	1228	static irqreturn_t otx2_q_intr_handler(int irq, void *data)
1175	{	1229	{
1176	struct otx2_nic *pf = data;	1230	struct otx2_nic *pf = data;
@@ -1204,46 +1258,67 @@ static irqreturn_t otx2_q_intr_handler(int irq, void *data) · 27 unmodified lines
1204		1258
1205	/* SQ */	1259	/* SQ */
1206	for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) {	1260	for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) {
		1261	u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg;
		1262	u8 sq_op_err_code, mnq_err_code, snd_err_code;
		1263
		1264	/* Below debug registers captures first errors corresponding to
		1265	* those registers. We don't have to check against SQ qid as
		1266	* these are fatal errors.
		1267	*/
		1268
1207	ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);	1269	ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);
1208	val = otx2_atomic64_add((qidx << 44), ptr);	1270	val = otx2_atomic64_add((qidx << 44), ptr);
1209	otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) \|	1271	otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) \|
1210	(val & NIX_SQINT_BITS));	1272	(val & NIX_SQINT_BITS));
1211		1273
1212	if (!(val & (NIX_SQINT_BITS \| BIT_ULL(42))))
1213	continue;
1214
1215	if (val & BIT_ULL(42)) {	1274	if (val & BIT_ULL(42)) {
1216	netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",	1275	netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1217	qidx, otx2_read64(pf, NIX_LF_ERR_INT));	1276	qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1218	} else {	1277	goto done;
1219	if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) {
1220	netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx",
1221	qidx,
1222	otx2_read64(pf,
1223	NIX_LF_SQ_OP_ERR_DBG));
1224	otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG,
1225	BIT_ULL(44));
1226	}
1227	if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
1228	netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n",
1229	qidx,
1230	otx2_read64(pf, NIX_LF_MNQ_ERR_DBG));
1231	otx2_write64(pf, NIX_LF_MNQ_ERR_DBG,
1232	BIT_ULL(44));
1233	}
1234	if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) {
1235	netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx",
1236	qidx,
1237	otx2_read64(pf,
1238	NIX_LF_SEND_ERR_DBG));
1239	otx2_write64(pf, NIX_LF_SEND_ERR_DBG,
1240	BIT_ULL(44));
1241	}
1242	if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
1243	netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
1244	qidx);
1245	}	1278	}
1246		1279
		1280	sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG);
		1281	if (!(sq_op_err_dbg & BIT(44)))
		1282	goto chk_mnq_err_dbg;
		1283
		1284	sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg);
		1285	netdev_err(pf->netdev, "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(%llx) err=%s\n",
		1286	qidx, sq_op_err_dbg, nix_sqoperr_e_str[sq_op_err_code]);
		1287
		1288	otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44));
		1289
		1290	if (sq_op_err_code == NIX_SQOPERR_SQB_NULL)
		1291	goto chk_mnq_err_dbg;
		1292
		1293	/* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure.
		1294	* TODO: But we are in irq context. How to call mbox functions which does sleep
		1295	*/
		1296
		1297	chk_mnq_err_dbg:
		1298	mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG);
		1299	if (!(mnq_err_dbg & BIT(44)))
		1300	goto chk_snd_err_dbg;
		1301
		1302	mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg);
		1303	netdev_err(pf->netdev, "SQ%lld: NIX_LF_MNQ_ERR_DBG(%llx) err=%s\n",
		1304	qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code]);
		1305	otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44));
		1306
		1307	chk_snd_err_dbg:
		1308	snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG);
		1309	if (snd_err_dbg & BIT(44)) {
		1310	snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg);
		1311	netdev_err(pf->netdev, "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s\n",
		1312	qidx, snd_err_dbg, nix_snd_status_e_str[snd_err_code]);
		1313	otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44));
		1314	}
		1315
		1316	done:
		1317	/* Print values and reset */
		1318	if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
		1319	netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
		1320	qidx);
		1321
1247	schedule_work(&pf->reset_task);	1322	schedule_work(&pf->reset_task);
1248	}	1323	}
1249		1324

drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h+57−0

@@ -281,4 +281,61 @@ enum nix_sqint_e { · 280 unmodified lines
281	BIT_ULL(NIX_SQINT_SEND_ERR) \| \	281	BIT_ULL(NIX_SQINT_SEND_ERR) \| \
282	BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))	282	BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
283		283
		284	enum nix_sqoperr_e {
		285	NIX_SQOPERR_OOR = 0,
		286	NIX_SQOPERR_CTX_FAULT = 1,
		287	NIX_SQOPERR_CTX_POISON = 2,
		288	NIX_SQOPERR_DISABLED = 3,
		289	NIX_SQOPERR_SIZE_ERR = 4,
		290	NIX_SQOPERR_OFLOW = 5,
		291	NIX_SQOPERR_SQB_NULL = 6,
		292	NIX_SQOPERR_SQB_FAULT = 7,
		293	NIX_SQOPERR_SQE_SZ_ZERO = 8,
		294	NIX_SQOPERR_MAX,
		295	};
		296
		297	enum nix_mnqerr_e {
		298	NIX_MNQERR_SQ_CTX_FAULT = 0,
		299	NIX_MNQERR_SQ_CTX_POISON = 1,
		300	NIX_MNQERR_SQB_FAULT = 2,
		301	NIX_MNQERR_SQB_POISON = 3,
		302	NIX_MNQERR_TOTAL_ERR = 4,
		303	NIX_MNQERR_LSO_ERR = 5,
		304	NIX_MNQERR_CQ_QUERY_ERR = 6,
		305	NIX_MNQERR_MAX_SQE_SIZE_ERR = 7,
		306	NIX_MNQERR_MAXLEN_ERR = 8,
		307	NIX_MNQERR_SQE_SIZEM1_ZERO = 9,
		308	NIX_MNQERR_MAX,
		309	};
		310
		311	enum nix_snd_status_e {
		312	NIX_SND_STATUS_GOOD = 0x0,
		313	NIX_SND_STATUS_SQ_CTX_FAULT = 0x1,
		314	NIX_SND_STATUS_SQ_CTX_POISON = 0x2,
		315	NIX_SND_STATUS_SQB_FAULT = 0x3,
		316	NIX_SND_STATUS_SQB_POISON = 0x4,
		317	NIX_SND_STATUS_HDR_ERR = 0x5,
		318	NIX_SND_STATUS_EXT_ERR = 0x6,
		319	NIX_SND_STATUS_JUMP_FAULT = 0x7,
		320	NIX_SND_STATUS_JUMP_POISON = 0x8,
		321	NIX_SND_STATUS_CRC_ERR = 0x9,
		322	NIX_SND_STATUS_IMM_ERR = 0x10,
		323	NIX_SND_STATUS_SG_ERR = 0x11,
		324	NIX_SND_STATUS_MEM_ERR = 0x12,
		325	NIX_SND_STATUS_INVALID_SUBDC = 0x13,
		326	NIX_SND_STATUS_SUBDC_ORDER_ERR = 0x14,
		327	NIX_SND_STATUS_DATA_FAULT = 0x15,
		328	NIX_SND_STATUS_DATA_POISON = 0x16,
		329	NIX_SND_STATUS_NPC_DROP_ACTION = 0x17,
		330	NIX_SND_STATUS_LOCK_VIOL = 0x18,
		331	NIX_SND_STATUS_NPC_UCAST_CHAN_ERR = 0x19,
		332	NIX_SND_STATUS_NPC_MCAST_CHAN_ERR = 0x20,
		333	NIX_SND_STATUS_NPC_MCAST_ABORT = 0x21,
		334	NIX_SND_STATUS_NPC_VTAG_PTR_ERR = 0x22,
		335	NIX_SND_STATUS_NPC_VTAG_SIZE_ERR = 0x23,
		336	NIX_SND_STATUS_SEND_MEM_FAULT = 0x24,
		337	NIX_SND_STATUS_SEND_STATS_ERR = 0x25,
		338	NIX_SND_STATUS_MAX,
		339	};
		340
284	#endif /* OTX2_STRUCT_H */	341	#endif /* OTX2_STRUCT_H */

drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c+19−13

 				struct otx2_cq_queue *cq, int budget)
 {
 	int tx_pkts = 0, tx_bytes = 0, qidx;
+	struct otx2_snd_queue *sq;
 	struct nix_cqe_tx_s *cqe;
 	int processed_cqe = 0;
 		return 0;
 process_cqe:
+	qidx = cq->cq_idx - pfvf->hw.rx_queues;
+	sq = &pfvf->qset.sq[qidx];
 	while (likely(processed_cqe < budget) && cq->pend_cqe) {
 		cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
 		if (unlikely(!cqe)) {
 				return 0;
 			break;
 		}
 		if (cq->cq_type == CQ_XDP) {
-			qidx = cq->cq_idx - pfvf->hw.rx_queues;
+			otx2_xdp_snd_pkt_handler(pfvf, sq, cqe);
-			otx2_xdp_snd_pkt_handler(pfvf, &pfvf->qset.sq[qidx],
-						 cqe);
 		} else {
-			otx2_snd_pkt_handler(pfvf, cq,
+			otx2_snd_pkt_handler(pfvf, cq, sq, cqe, budget,
-					     &pfvf->qset.sq[cq->cint_idx],
+					     &tx_pkts, &tx_bytes);
-					     cqe, budget, &tx_pkts, &tx_bytes);
 		}
 		cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
 		processed_cqe++;
 		cq->pend_cqe--;
+		sq->cons_head++;
+		sq->cons_head &= (sq->sqe_cnt - 1);
 	}
 	/* Free CQEs to HW */
 {
 	struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx);
 	struct otx2_nic *pfvf = netdev_priv(netdev);
-	int offset, num_segs, free_sqe;
+	int offset, num_segs, free_desc;
 	struct nix_sqe_hdr_s *sqe_hdr;
-	/* Check if there is room for new SQE.
+	/* Check if there is enough room between producer
-	 * 'Num of SQBs freed to SQ's pool - SQ's Aura count'
+	 * and consumer index.
-	 * will give free SQE count.
 	 */
-	free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb;
+	free_desc = (sq->cons_head - sq->head - 1 + sq->sqe_cnt) & (sq->sqe_cnt - 1);
+	if (free_desc < sq->sqe_thresh)
+		return false;
-	if (free_sqe < sq->sqe_thresh ||
+	if (free_desc < otx2_get_sqe_count(pfvf, skb))
-	    free_sqe < otx2_get_sqe_count(pfvf, skb))
 		return false;
 	num_segs = skb_shinfo(skb)->nr_frags + 1;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h+1−0

@@ -79,6 +79,7 @@ struct sg_list { · 78 unmodified lines
79	struct otx2_snd_queue {	79	struct otx2_snd_queue {
80	u8 aura_id;	80	u8 aura_id;
81	u16 head;	81	u16 head;
		82	u16 cons_head;
82	u16 sqe_size;	83	u16 sqe_size;
83	u32 sqe_cnt;	84	u32 sqe_cnt;
84	u16 num_sqbs;	85	u16 num_sqbs;

drivers/net/ethernet/marvell/prestera/prestera_rxtx.c+6−1

 int prestera_rxtx_switch_init(struct prestera_switch *sw)
 {
 	struct prestera_rxtx *rxtx;
+	int err;
 	rxtx = kzalloc(sizeof(*rxtx), GFP_KERNEL);
 	if (!rxtx)
 	sw->rxtx = rxtx;
-	return prestera_sdma_switch_init(sw);
+	err = prestera_sdma_switch_init(sw);
+	if (err)
+		kfree(rxtx);
+	return err;
 }
 void prestera_rxtx_switch_fini(struct prestera_switch *sw)

drivers/net/ethernet/mediatek/mtk_star_emac.c+2−0

@@ -1026,6 +1026,8 @@ static int mtk_star_enable(struct net_device *ndev) · 1025 unmodified lines
1026	return 0;	1026	return 0;
1027		1027
1028	err_free_irq:	1028	err_free_irq:
		1029	napi_disable(&priv->rx_napi);
		1030	napi_disable(&priv->tx_napi);
1029	free_irq(ndev->irq, ndev);	1031	free_irq(ndev->irq, ndev);
1030	err_free_skbs:	1032	err_free_skbs:
1031	mtk_star_free_rx_skbs(priv);	1033	mtk_star_free_rx_skbs(priv);

drivers/net/ethernet/mellanox/mlx5/core/cmd.c+8−3

 	struct mlx5_cmd *cmd = &dev->cmd;
 	int i;
-	for (i = 0; i < cmd->max_reg_cmds; i++)
+	for (i = 0; i < cmd->max_reg_cmds; i++) {
-		while (down_trylock(&cmd->sem))
+		while (down_trylock(&cmd->sem)) {
 			mlx5_cmd_trigger_completions(dev);
+			cond_resched();
+		}
+	}
-	while (down_trylock(&cmd->pages_sem))
+	while (down_trylock(&cmd->pages_sem)) {
 		mlx5_cmd_trigger_completions(dev);
+		cond_resched();
+	}
 	/* Unlock cmdif */
 	up(&cmd->pages_sem);

drivers/net/ethernet/mellanox/mlx5/core/en/rep/bridge.c+31−0

@@ -164,6 +164,36 @@ static int mlx5_esw_bridge_port_changeupper(struct notifier_block nb, void ptr · 163 unmodified lines
164	return err;	164	return err;
165	}	165	}
166		166
		167	static int
		168	mlx5_esw_bridge_changeupper_validate_netdev(void *ptr)
		169	{
		170	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
		171	struct netdev_notifier_changeupper_info *info = ptr;
		172	struct net_device *upper = info->upper_dev;
		173	struct net_device *lower;
		174	struct list_head *iter;
		175
		176	if (!netif_is_bridge_master(upper) \|\| !netif_is_lag_master(dev))
		177	return 0;
		178
		179	netdev_for_each_lower_dev(dev, lower, iter) {
		180	struct mlx5_core_dev *mdev;
		181	struct mlx5e_priv *priv;
		182
		183	if (!mlx5e_eswitch_rep(lower))
		184	continue;
		185
		186	priv = netdev_priv(lower);
		187	mdev = priv->mdev;
		188	if (!mlx5_lag_is_active(mdev))
		189	return -EAGAIN;
		190	if (!mlx5_lag_is_shared_fdb(mdev))
		191	return -EOPNOTSUPP;
		192	}
		193
		194	return 0;
		195	}
		196
167	static int mlx5_esw_bridge_switchdev_port_event(struct notifier_block *nb,	197	static int mlx5_esw_bridge_switchdev_port_event(struct notifier_block *nb,
168	unsigned long event, void *ptr)	198	unsigned long event, void *ptr)
169	{	199	{
@@ -171,6 +201,7 @@ static int mlx5_esw_bridge_switchdev_port_event(struct notifier_block *nb, · 1 unmodified line
171		201
172	switch (event) {	202	switch (event) {
173	case NETDEV_PRECHANGEUPPER:	203	case NETDEV_PRECHANGEUPPER:
		204	err = mlx5_esw_bridge_changeupper_validate_netdev(ptr);
174	break;	205	break;
175		206
176	case NETDEV_CHANGEUPPER:	207	case NETDEV_CHANGEUPPER:

drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.c+32−60

@@ -6,70 +6,42 @@ · 5 unmodified lines
6	#include "en/tc_priv.h"	6	#include "en/tc_priv.h"
7	#include "mlx5_core.h"	7	#include "mlx5_core.h"
8		8
9	/* Must be aligned with enum flow_action_id. */
10	static struct mlx5e_tc_act *tc_acts_fdb[NUM_FLOW_ACTIONS] = {	9	static struct mlx5e_tc_act *tc_acts_fdb[NUM_FLOW_ACTIONS] = {
11	&mlx5e_tc_act_accept,	10	[FLOW_ACTION_ACCEPT] = &mlx5e_tc_act_accept,
12	&mlx5e_tc_act_drop,	11	[FLOW_ACTION_DROP] = &mlx5e_tc_act_drop,
13	&mlx5e_tc_act_trap,	12	[FLOW_ACTION_TRAP] = &mlx5e_tc_act_trap,
14	&mlx5e_tc_act_goto,	13	[FLOW_ACTION_GOTO] = &mlx5e_tc_act_goto,
15	&mlx5e_tc_act_mirred,	14	[FLOW_ACTION_REDIRECT] = &mlx5e_tc_act_mirred,
16	&mlx5e_tc_act_mirred,	15	[FLOW_ACTION_MIRRED] = &mlx5e_tc_act_mirred,
17	&mlx5e_tc_act_redirect_ingress,	16	[FLOW_ACTION_REDIRECT_INGRESS] = &mlx5e_tc_act_redirect_ingress,
18	NULL, /* FLOW_ACTION_MIRRED_INGRESS, */	17	[FLOW_ACTION_VLAN_PUSH] = &mlx5e_tc_act_vlan,
19	&mlx5e_tc_act_vlan,	18	[FLOW_ACTION_VLAN_POP] = &mlx5e_tc_act_vlan,
20	&mlx5e_tc_act_vlan,	19	[FLOW_ACTION_VLAN_MANGLE] = &mlx5e_tc_act_vlan_mangle,
21	&mlx5e_tc_act_vlan_mangle,	20	[FLOW_ACTION_TUNNEL_ENCAP] = &mlx5e_tc_act_tun_encap,
22	&mlx5e_tc_act_tun_encap,	21	[FLOW_ACTION_TUNNEL_DECAP] = &mlx5e_tc_act_tun_decap,
23	&mlx5e_tc_act_tun_decap,	22	[FLOW_ACTION_MANGLE] = &mlx5e_tc_act_pedit,
24	&mlx5e_tc_act_pedit,	23	[FLOW_ACTION_ADD] = &mlx5e_tc_act_pedit,
25	&mlx5e_tc_act_pedit,	24	[FLOW_ACTION_CSUM] = &mlx5e_tc_act_csum,
26	&mlx5e_tc_act_csum,	25	[FLOW_ACTION_PTYPE] = &mlx5e_tc_act_ptype,
27	NULL, /* FLOW_ACTION_MARK, */	26	[FLOW_ACTION_SAMPLE] = &mlx5e_tc_act_sample,
28	&mlx5e_tc_act_ptype,	27	[FLOW_ACTION_POLICE] = &mlx5e_tc_act_police,
29	NULL, /* FLOW_ACTION_PRIORITY, */	28	[FLOW_ACTION_CT] = &mlx5e_tc_act_ct,
30	NULL, /* FLOW_ACTION_WAKE, */	29	[FLOW_ACTION_MPLS_PUSH] = &mlx5e_tc_act_mpls_push,
31	NULL, /* FLOW_ACTION_QUEUE, */	30	[FLOW_ACTION_MPLS_POP] = &mlx5e_tc_act_mpls_pop,
32	&mlx5e_tc_act_sample,	31	[FLOW_ACTION_VLAN_PUSH_ETH] = &mlx5e_tc_act_vlan,
33	&mlx5e_tc_act_police,	32	[FLOW_ACTION_VLAN_POP_ETH] = &mlx5e_tc_act_vlan,
34	&mlx5e_tc_act_ct,
35	NULL, /* FLOW_ACTION_CT_METADATA, */
36	&mlx5e_tc_act_mpls_push,
37	&mlx5e_tc_act_mpls_pop,
38	NULL, /* FLOW_ACTION_MPLS_MANGLE, */
39	NULL, /* FLOW_ACTION_GATE, */
40	NULL, /* FLOW_ACTION_PPPOE_PUSH, */
41	NULL, /* FLOW_ACTION_JUMP, */
42	NULL, /* FLOW_ACTION_PIPE, */
43	&mlx5e_tc_act_vlan,
44	&mlx5e_tc_act_vlan,
45	};	33	};
46		34
47	/* Must be aligned with enum flow_action_id. */
48	static struct mlx5e_tc_act *tc_acts_nic[NUM_FLOW_ACTIONS] = {	35	static struct mlx5e_tc_act *tc_acts_nic[NUM_FLOW_ACTIONS] = {
49	&mlx5e_tc_act_accept,	36	[FLOW_ACTION_ACCEPT] = &mlx5e_tc_act_accept,
50	&mlx5e_tc_act_drop,	37	[FLOW_ACTION_DROP] = &mlx5e_tc_act_drop,
51	NULL, /* FLOW_ACTION_TRAP, */	38	[FLOW_ACTION_GOTO] = &mlx5e_tc_act_goto,
52	&mlx5e_tc_act_goto,	39	[FLOW_ACTION_REDIRECT] = &mlx5e_tc_act_mirred_nic,
53	&mlx5e_tc_act_mirred_nic,	40	[FLOW_ACTION_MANGLE] = &mlx5e_tc_act_pedit,
54	NULL, /* FLOW_ACTION_MIRRED, */	41	[FLOW_ACTION_ADD] = &mlx5e_tc_act_pedit,
55	NULL, /* FLOW_ACTION_REDIRECT_INGRESS, */	42	[FLOW_ACTION_CSUM] = &mlx5e_tc_act_csum,
56	NULL, /* FLOW_ACTION_MIRRED_INGRESS, */	43	[FLOW_ACTION_MARK] = &mlx5e_tc_act_mark,
57	NULL, /* FLOW_ACTION_VLAN_PUSH, */	44	[FLOW_ACTION_CT] = &mlx5e_tc_act_ct,
58	NULL, /* FLOW_ACTION_VLAN_POP, */
59	NULL, /* FLOW_ACTION_VLAN_MANGLE, */
60	NULL, /* FLOW_ACTION_TUNNEL_ENCAP, */
61	NULL, /* FLOW_ACTION_TUNNEL_DECAP, */
62	&mlx5e_tc_act_pedit,
63	&mlx5e_tc_act_pedit,
64	&mlx5e_tc_act_csum,
65	&mlx5e_tc_act_mark,
66	NULL, /* FLOW_ACTION_PTYPE, */
67	NULL, /* FLOW_ACTION_PRIORITY, */
68	NULL, /* FLOW_ACTION_WAKE, */
69	NULL, /* FLOW_ACTION_QUEUE, */
70	NULL, /* FLOW_ACTION_SAMPLE, */
71	NULL, /* FLOW_ACTION_POLICE, */
72	&mlx5e_tc_act_ct,
73	};	45	};
74		46
75	/**	47	/**

drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h+23−1

@@ -11,6 +11,27 @@ · 10 unmodified lines
11		11
12	#define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start))	12	#define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start))
13		13
		14	/* IPSEC inline data includes:
		15	* 1. ESP trailer: up to 255 bytes of padding, 1 byte for pad length, 1 byte for
		16	* next header.
		17	* 2. ESP authentication data: 16 bytes for ICV.
		18	*/
		19	#define MLX5E_MAX_TX_IPSEC_DS DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + \
		20	255 + 1 + 1 + 16, MLX5_SEND_WQE_DS)
		21
		22	/* 366 should be big enough to cover all L2, L3 and L4 headers with possible
		23	* encapsulations.
		24	*/
		25	#define MLX5E_MAX_TX_INLINE_DS DIV_ROUND_UP(366 - INL_HDR_START_SZ + VLAN_HLEN, \
		26	MLX5_SEND_WQE_DS)
		27
		28	/* Sync the calculation with mlx5e_sq_calc_wqe_attr. */
		29	#define MLX5E_MAX_TX_WQEBBS DIV_ROUND_UP(MLX5E_TX_WQE_EMPTY_DS_COUNT + \
		30	MLX5E_MAX_TX_INLINE_DS + \
		31	MLX5E_MAX_TX_IPSEC_DS + \
		32	MAX_SKB_FRAGS + 1, \
		33	MLX5_SEND_WQEBB_NUM_DS)
		34
14	#define MLX5E_RX_ERR_CQE(cqe) (get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND)	35	#define MLX5E_RX_ERR_CQE(cqe) (get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND)
15		36
16	static inline	37	static inline
@@ -424,6 +445,8 @@ mlx5e_set_eseg_swp(struct sk_buff skb, struct mlx5_wqe_eth_seg eseg, · 407 unmodified lines
424		445
425	static inline u16 mlx5e_stop_room_for_wqe(struct mlx5_core_dev *mdev, u16 wqe_size)	446	static inline u16 mlx5e_stop_room_for_wqe(struct mlx5_core_dev *mdev, u16 wqe_size)
426	{	447	{
		448	WARN_ON_ONCE(PAGE_SIZE / MLX5_SEND_WQE_BB < mlx5e_get_max_sq_wqebbs(mdev));
		449
427	/* A WQE must not cross the page boundary, hence two conditions:	450	/* A WQE must not cross the page boundary, hence two conditions:
428	* 1. Its size must not exceed the page size.	451	* 1. Its size must not exceed the page size.
429	* 2. If the WQE size is X, and the space remaining in a page is less	452	* 2. If the WQE size is X, and the space remaining in a page is less
@@ -436,7 +459,6 @@ static inline u16 mlx5e_stop_room_for_wqe(struct mlx5_core_dev *mdev, u16 wqe_si · 6 unmodified lines
436	"wqe_size %u is greater than max SQ WQEBBs %u",	459	"wqe_size %u is greater than max SQ WQEBBs %u",
437	wqe_size, mlx5e_get_max_sq_wqebbs(mdev));	460	wqe_size, mlx5e_get_max_sq_wqebbs(mdev));
438		461
439
440	return MLX5E_STOP_ROOM(wqe_size);	462	return MLX5E_STOP_ROOM(wqe_size);
441	}	463	}
442		464

drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c+2−2

@@ -117,7 +117,7 @@ mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq sq, struct mlx5e_rq rq, · 116 unmodified lines
117	xdpi.page.rq = rq;	117	xdpi.page.rq = rq;
118		118
119	dma_addr = page_pool_get_dma_addr(page) + (xdpf->data - (void *)xdpf);	119	dma_addr = page_pool_get_dma_addr(page) + (xdpf->data - (void *)xdpf);
120	dma_sync_single_for_device(sq->pdev, dma_addr, xdptxd.len, DMA_TO_DEVICE);	120	dma_sync_single_for_device(sq->pdev, dma_addr, xdptxd.len, DMA_BIDIRECTIONAL);
121		121
122	if (unlikely(xdp_frame_has_frags(xdpf))) {	122	if (unlikely(xdp_frame_has_frags(xdpf))) {
123	sinfo = xdp_get_shared_info_from_frame(xdpf);	123	sinfo = xdp_get_shared_info_from_frame(xdpf);
@@ -131,7 +131,7 @@ mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq sq, struct mlx5e_rq rq, · 7 unmodified lines
131	skb_frag_off(frag);	131	skb_frag_off(frag);
132	len = skb_frag_size(frag);	132	len = skb_frag_size(frag);
133	dma_sync_single_for_device(sq->pdev, addr, len,	133	dma_sync_single_for_device(sq->pdev, addr, len,
134	DMA_TO_DEVICE);	134	DMA_BIDIRECTIONAL);
135	}	135	}
136	}	136	}
137		137

drivers/net/ethernet/mellanox/mlx5/core/en_main.c+7−0

@@ -5694,6 +5694,13 @@ int mlx5e_attach_netdev(struct mlx5e_priv *priv) · 5693 unmodified lines
5694	mlx5e_fs_set_state_destroy(priv->fs,	5694	mlx5e_fs_set_state_destroy(priv->fs,
5695	!test_bit(MLX5E_STATE_DESTROYING, &priv->state));	5695	!test_bit(MLX5E_STATE_DESTROYING, &priv->state));
5696		5696
		5697	/* Validate the max_wqe_size_sq capability. */
		5698	if (WARN_ON_ONCE(mlx5e_get_max_sq_wqebbs(priv->mdev) < MLX5E_MAX_TX_WQEBBS)) {
		5699	mlx5_core_warn(priv->mdev, "MLX5E: Max SQ WQEBBs firmware capability: %u, needed %lu\n",
		5700	mlx5e_get_max_sq_wqebbs(priv->mdev), MLX5E_MAX_TX_WQEBBS);
		5701	return -EIO;
		5702	}
		5703
5697	/* max number of channels may have changed */	5704	/* max number of channels may have changed */
5698	max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);	5705	max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5699	if (priv->channels.params.num_channels > max_nch) {	5706	if (priv->channels.params.num_channels > max_nch) {

drivers/net/ethernet/mellanox/mlx5/core/en_rx.c+14−13

 	addr = page_pool_get_dma_addr(au->page);
 	/* Non-XSK always uses PAGE_SIZE. */
-	dma_sync_single_for_device(rq->pdev, addr, PAGE_SIZE, DMA_FROM_DEVICE);
+	dma_sync_single_for_device(rq->pdev, addr, PAGE_SIZE, rq->buff.map_dir);
 	return true;
 }
 		return -ENOMEM;
 	/* Non-XSK always uses PAGE_SIZE. */
-	addr = dma_map_page_attrs(rq->pdev, au->page, 0, PAGE_SIZE,
+	addr = dma_map_page(rq->pdev, au->page, 0, PAGE_SIZE, rq->buff.map_dir);
-				  rq->buff.map_dir, DMA_ATTR_SKIP_CPU_SYNC);
 	if (unlikely(dma_mapping_error(rq->pdev, addr))) {
 		page_pool_recycle_direct(rq->page_pool, au->page);
 		au->page = NULL;
 {
 	dma_addr_t addr = page_pool_get_dma_addr(au->page);
-	dma_sync_single_for_cpu(rq->pdev, addr + frag_offset, len, DMA_FROM_DEVICE);
+	dma_sync_single_for_cpu(rq->pdev, addr + frag_offset, len,
+				rq->buff.map_dir);
 	page_ref_inc(au->page);
 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 			au->page, frag_offset, len, truesize);
 }
 static inline void
-mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
+mlx5e_copy_skb_header(struct mlx5e_rq *rq, struct sk_buff *skb,
 		      struct page *page, dma_addr_t addr,
 		      int offset_from, int dma_offset, u32 headlen)
 {
 	/* Aligning len to sizeof(long) optimizes memcpy performance */
 	unsigned int len = ALIGN(headlen, sizeof(long));
-	dma_sync_single_for_cpu(pdev, addr + dma_offset, len, DMA_FROM_DEVICE);
+	dma_sync_single_for_cpu(rq->pdev, addr + dma_offset, len,
+				rq->buff.map_dir);
 	skb_copy_to_linear_data(skb, from, len);
 }
 	addr = page_pool_get_dma_addr(au->page);
 	dma_sync_single_range_for_cpu(rq->pdev, addr, wi->offset,
-				      frag_size, DMA_FROM_DEVICE);
+				      frag_size, rq->buff.map_dir);
 	net_prefetch(data);
 	prog = rcu_dereference(rq->xdp_prog);
 	addr = page_pool_get_dma_addr(au->page);
 	dma_sync_single_range_for_cpu(rq->pdev, addr, wi->offset,
-				      rq->buff.frame0_sz, DMA_FROM_DEVICE);
+				      rq->buff.frame0_sz, rq->buff.map_dir);
 	net_prefetchw(va); /* xdp_frame data area */
 	net_prefetch(va + rx_headroom);
 		addr = page_pool_get_dma_addr(au->page);
 		dma_sync_single_for_cpu(rq->pdev, addr + wi->offset,
-					frag_consumed_bytes, DMA_FROM_DEVICE);
+					frag_consumed_bytes, rq->buff.map_dir);
 		if (!xdp_buff_has_frags(&xdp)) {
 			/* Init on the first fragment to avoid cold cache access
 	mlx5e_fill_skb_data(skb, rq, au, byte_cnt, frag_offset);
 	/* copy header */
 	addr = page_pool_get_dma_addr(head_au->page);
-	mlx5e_copy_skb_header(rq->pdev, skb, head_au->page, addr,
+	mlx5e_copy_skb_header(rq, skb, head_au->page, addr,
 			      head_offset, head_offset, headlen);
 	/* skb linear part was allocated with headlen and aligned to long */
 	skb->tail += headlen;
 	addr = page_pool_get_dma_addr(au->page);
 	dma_sync_single_range_for_cpu(rq->pdev, addr, head_offset,
-				      frag_size, DMA_FROM_DEVICE);
+				      frag_size, rq->buff.map_dir);
 	net_prefetch(data);
 	prog = rcu_dereference(rq->xdp_prog);
 	if (likely(frag_size <= BIT(MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE))) {
 		/* build SKB around header */
-		dma_sync_single_range_for_cpu(rq->pdev, head->addr, 0, frag_size, DMA_FROM_DEVICE);
+		dma_sync_single_range_for_cpu(rq->pdev, head->addr, 0, frag_size, rq->buff.map_dir);
 		prefetchw(hdr);
 		prefetch(data);
 		skb = mlx5e_build_linear_skb(rq, hdr, frag_size, rx_headroom, head_size, 0);
 		}
 		prefetchw(skb->data);
-		mlx5e_copy_skb_header(rq->pdev, skb, head->page, head->addr,
+		mlx5e_copy_skb_header(rq, skb, head->page, head->addr,
 				      head_offset + rx_headroom,
 				      rx_headroom, head_size);
 		/* skb linear part was allocated with headlen and aligned to long */

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c+6−8

 	attr2->action = 0;
 	attr2->flags = 0;
 	attr2->parse_attr = parse_attr;
-	attr2->esw_attr->out_count = 0;
-	attr2->esw_attr->split_count = 0;
 	attr2->dest_chain = 0;
 	attr2->dest_ft = NULL;
+	if (ns_type == MLX5_FLOW_NAMESPACE_FDB) {
+		attr2->esw_attr->out_count = 0;
+		attr2->esw_attr->split_count = 0;
+	}
 	return attr2;
 }
 		return -EOPNOTSUPP;
 	}
-	if (act->police.rate_pkt_ps) {
-		NL_SET_ERR_MSG_MOD(extack,
-				   "QoS offload not support packets per second");
-		return -EOPNOTSUPP;
-	}
 	return 0;
 }

drivers/net/ethernet/mellanox/mlx5/core/en_tx.c+5−0

 	u16 ds_cnt_inl = 0;
 	u16 ds_cnt_ids = 0;
+	/* Sync the calculation with MLX5E_MAX_TX_WQEBBS. */
 	if (attr->insz)
 		ds_cnt_ids = DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + attr->insz,
 					  MLX5_SEND_WQE_DS);
 			inl += VLAN_HLEN;
 		ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
+		if (WARN_ON_ONCE(ds_cnt_inl > MLX5E_MAX_TX_INLINE_DS))
+			netdev_warn(skb->dev, "ds_cnt_inl = %u > max %u\n", ds_cnt_inl,
+				    (u16)MLX5E_MAX_TX_INLINE_DS);
 		ds_cnt += ds_cnt_inl;
 	}

drivers/net/ethernet/mellanox/mlx5/core/eswitch.c+8−6

@@ -1387,12 +1387,14 @@ void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw) · 1386 unmodified lines
1387	esw->mode == MLX5_ESWITCH_LEGACY ? "LEGACY" : "OFFLOADS",	1387	esw->mode == MLX5_ESWITCH_LEGACY ? "LEGACY" : "OFFLOADS",
1388	esw->esw_funcs.num_vfs, esw->enabled_vports);	1388	esw->esw_funcs.num_vfs, esw->enabled_vports);
1389		1389
1390	esw->fdb_table.flags &= ~MLX5_ESW_FDB_CREATED;	1390	if (esw->fdb_table.flags & MLX5_ESW_FDB_CREATED) {
1391	if (esw->mode == MLX5_ESWITCH_OFFLOADS)	1391	esw->fdb_table.flags &= ~MLX5_ESW_FDB_CREATED;
1392	esw_offloads_disable(esw);	1392	if (esw->mode == MLX5_ESWITCH_OFFLOADS)
1393	else if (esw->mode == MLX5_ESWITCH_LEGACY)	1393	esw_offloads_disable(esw);
1394	esw_legacy_disable(esw);	1394	else if (esw->mode == MLX5_ESWITCH_LEGACY)
1395	mlx5_esw_acls_ns_cleanup(esw);	1395	esw_legacy_disable(esw);
		1396	mlx5_esw_acls_ns_cleanup(esw);
		1397	}
1396		1398
1397	if (esw->mode == MLX5_ESWITCH_OFFLOADS)	1399	if (esw->mode == MLX5_ESWITCH_OFFLOADS)
1398	devl_rate_nodes_destroy(devlink);	1400	devl_rate_nodes_destroy(devlink);

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c+3−15

 static int esw_offloads_start(struct mlx5_eswitch *esw,
 			      struct netlink_ext_ack *extack)
 {
-	int err, err1;
+	int err;
 	esw->mode = MLX5_ESWITCH_OFFLOADS;
 	err = mlx5_eswitch_enable_locked(esw, esw->dev->priv.sriov.num_vfs);
 		NL_SET_ERR_MSG_MOD(extack,
 				   "Failed setting eswitch to offloads");
 		esw->mode = MLX5_ESWITCH_LEGACY;
-		err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
-		if (err1) {
-			NL_SET_ERR_MSG_MOD(extack,
-					   "Failed setting eswitch back to legacy");
-		}
 		mlx5_rescan_drivers(esw->dev);
 	}
 	if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
 static int esw_offloads_stop(struct mlx5_eswitch *esw,
 			     struct netlink_ext_ack *extack)
 {
-	int err, err1;
+	int err;
 	esw->mode = MLX5_ESWITCH_LEGACY;
 	err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
-	if (err) {
+	if (err)
 		NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
-		esw->mode = MLX5_ESWITCH_OFFLOADS;
-		err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
-		if (err1) {
-			NL_SET_ERR_MSG_MOD(extack,
-					   "Failed setting eswitch back to offloads");
-		}
-	}
 	return err;
 }

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c+8−6

 		     sizeof(dest->vport.num), hash);
 	hash = jhash((const void *)&dest->vport.vhca_id,
 		     sizeof(dest->vport.num), hash);
-	if (dest->vport.pkt_reformat)
+	if (flow_act->pkt_reformat)
-		hash = jhash(dest->vport.pkt_reformat,
+		hash = jhash(flow_act->pkt_reformat,
-			     sizeof(*dest->vport.pkt_reformat),
+			     sizeof(*flow_act->pkt_reformat),
 			     hash);
 	return hash;
 }
 	if (ret)
 		return ret;
-	return dest1->vport.pkt_reformat && dest2->vport.pkt_reformat ?
+	if (flow_act1->pkt_reformat && flow_act2->pkt_reformat)
-	       memcmp(dest1->vport.pkt_reformat, dest2->vport.pkt_reformat,
+		return memcmp(flow_act1->pkt_reformat, flow_act2->pkt_reformat,
-		      sizeof(*dest1->vport.pkt_reformat)) : 0;
+			      sizeof(*flow_act1->pkt_reformat));
+	return !(flow_act1->pkt_reformat == flow_act2->pkt_reformat);
 }
 static int

drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c+2−1

 		mlx5_unload_one(dev);
 		if (mlx5_health_wait_pci_up(dev))
 			mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
-		mlx5_load_one(dev, false);
+		else
+			mlx5_load_one(dev, false);
 		devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0,
 							BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
 							BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));

drivers/net/ethernet/neterion/s2io.c+20−9

 		if (ret) {
 			DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
 				  dev->name);
-			s2io_reset(sp);
+			ret = -ENOMEM;
-			free_rx_buffers(sp);
+			goto err_fill_buff;
-			return -ENOMEM;
 		}
 		DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
 			  ring->rx_bufs_left);
 	/* Enable Rx Traffic and interrupts on the NIC */
 	if (start_nic(sp)) {
 		DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
-		s2io_reset(sp);
+		ret = -ENODEV;
-		free_rx_buffers(sp);
+		goto err_out;
-		return -ENODEV;
 	}
 	/* Add interrupt service routine */
 	if (s2io_add_isr(sp) != 0) {
 		if (sp->config.intr_type == MSI_X)
 			s2io_rem_isr(sp);
-		s2io_reset(sp);
+		ret = -ENODEV;
-		free_rx_buffers(sp);
+		goto err_out;
-		return -ENODEV;
 	}
 	timer_setup(&sp->alarm_timer, s2io_alarm_handle, 0);
 	}
 	return 0;
+err_out:
+	if (config->napi) {
+		if (config->intr_type == MSI_X) {
+			for (i = 0; i < sp->config.rx_ring_num; i++)
+				napi_disable(&sp->mac_control.rings[i].napi);
+		} else {
+			napi_disable(&sp->napi);
+		}
+	}
+err_fill_buff:
+	s2io_reset(sp);
+	free_rx_buffers(sp);
+	return ret;
 }
 /**

drivers/net/ethernet/ni/nixge.c+1−0

@@ -900,6 +900,7 @@ static int nixge_open(struct net_device *ndev) · 899 unmodified lines
900	err_rx_irq:	900	err_rx_irq:
901	free_irq(priv->tx_irq, ndev);	901	free_irq(priv->tx_irq, ndev);
902	err_tx_irq:	902	err_tx_irq:
		903	napi_disable(&priv->napi);
903	phy_stop(phy);	904	phy_stop(phy);
904	phy_disconnect(phy);	905	phy_disconnect(phy);
905	tasklet_kill(&priv->dma_err_tasklet);	906	tasklet_kill(&priv->dma_err_tasklet);

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c+9−2

 {
 	plat->rx_queues_to_use = 8;
 	plat->tx_queues_to_use = 8;
-	plat->clk_ptp_rate = 200000000;
 	plat->use_phy_wol = 1;
 	plat->safety_feat_cfg->tsoee = 1;
 	plat->serdes_powerup = intel_serdes_powerup;
 	plat->serdes_powerdown = intel_serdes_powerdown;
+	plat->clk_ptp_rate = 204800000;
 	return ehl_common_data(pdev, plat);
 }
 	plat->bus_id = 1;
 	plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
+	plat->clk_ptp_rate = 204800000;
 	return ehl_common_data(pdev, plat);
 }
 	plat->bus_id = 2;
 	plat->addr64 = 32;
+	plat->clk_ptp_rate = 200000000;
 	intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
 	return ehl_common_data(pdev, plat);
 	plat->bus_id = 3;
 	plat->addr64 = 32;
+	plat->clk_ptp_rate = 200000000;
 	intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
 	return ehl_common_data(pdev, plat);
 {
 	plat->rx_queues_to_use = 6;
 	plat->tx_queues_to_use = 4;
-	plat->clk_ptp_rate = 200000000;
+	plat->clk_ptp_rate = 204800000;
 	plat->speed_mode_2500 = intel_speed_mode_2500;
 	plat->safety_feat_cfg->tsoee = 1;

drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c+31−8

 		plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
 						   sizeof(*plat->mdio_bus_data),
 						   GFP_KERNEL);
-		if (!plat->mdio_bus_data)
+		if (!plat->mdio_bus_data) {
-			return -ENOMEM;
+			ret = -ENOMEM;
+			goto err_put_node;
+		}
 		plat->mdio_bus_data->needs_reset = true;
 	}
 	plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
-	if (!plat->dma_cfg)
+	if (!plat->dma_cfg) {
-		return -ENOMEM;
+		ret = -ENOMEM;
+		goto err_put_node;
+	}
 	/* Enable pci device */
 	ret = pci_enable_device(pdev);
 	if (ret) {
 		dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", __func__);
-		return ret;
+		goto err_put_node;
 	}
 	/* Get the base address of device */
 			continue;
 		ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
 		if (ret)
-			return ret;
+			goto err_disable_device;
 		break;
 	}
 	phy_mode = device_get_phy_mode(&pdev->dev);
 	if (phy_mode < 0) {
 		dev_err(&pdev->dev, "phy_mode not found\n");
-		return phy_mode;
+		ret = phy_mode;
+		goto err_disable_device;
 	}
 	plat->phy_interface = phy_mode;
 	if (res.irq < 0) {
 		dev_err(&pdev->dev, "IRQ macirq not found\n");
 		ret = -ENODEV;
+		goto err_disable_msi;
 	}
 	res.wol_irq = of_irq_get_byname(np, "eth_wake_irq");
 	if (res.lpi_irq < 0) {
 		dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
 		ret = -ENODEV;
+		goto err_disable_msi;
 	}
-	return stmmac_dvr_probe(&pdev->dev, plat, &res);
+	ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
+	if (ret)
+		goto err_disable_msi;
+	return ret;
+err_disable_msi:
+	pci_disable_msi(pdev);
+err_disable_device:
+	pci_disable_device(pdev);
+err_put_node:
+	of_node_put(plat->mdio_node);
+	return ret;
 }
 static void loongson_dwmac_remove(struct pci_dev *pdev)
 {
+	struct net_device *ndev = dev_get_drvdata(&pdev->dev);
+	struct stmmac_priv *priv = netdev_priv(ndev);
 	int i;
+	of_node_put(priv->plat->mdio_node);
 	stmmac_dvr_remove(&pdev->dev);
 	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
 		break;
 	}
+	pci_disable_msi(pdev);
 	pci_disable_device(pdev);
 }

drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c+3−5

 	if (ret)
 		return ret;
-	devm_add_action_or_reset(dwmac->dev,
+	return devm_add_action_or_reset(dwmac->dev,
-				 (void(*)(void *))clk_disable_unprepare,
+					(void(*)(void *))clk_disable_unprepare,
-				 dwmac->rgmii_tx_clk);
+					clk);
-	return 0;
 }
 static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac)

drivers/net/ethernet/sunplus/spl2sw_driver.c+0−1

@@ -287,7 +287,6 @@ static u32 spl2sw_init_netdev(struct platform_device pdev, u8 mac_addr, · 286 unmodified lines
287	if (ret) {	287	if (ret) {
288	dev_err(&pdev->dev, "Failed to register net device \"%s\"!\n",	288	dev_err(&pdev->dev, "Failed to register net device \"%s\"!\n",
289	ndev->name);	289	ndev->name);
290	free_netdev(ndev);
291	*r_ndev = NULL;	290	*r_ndev = NULL;
292	return ret;	291	return ret;
293	}	292	}

drivers/net/ethernet/ti/am65-cpsw-nuss.c+1−1

 	if (ret < 0)
 		return ret;
-	am65_cpsw_nuss_phylink_cleanup(common);
 	am65_cpsw_unregister_devlink(common);
 	am65_cpsw_unregister_notifiers(common);
 	 * dma_deconfigure(dev) before devres_release_all(dev)
 	 */
 	am65_cpsw_nuss_cleanup_ndev(common);
+	am65_cpsw_nuss_phylink_cleanup(common);
 	of_platform_device_destroy(common->mdio_dev, NULL);

drivers/net/ethernet/ti/cpsw.c+2−0

@@ -854,6 +854,8 @@ static int cpsw_ndo_open(struct net_device *ndev) · 853 unmodified lines
854		854
855	err_cleanup:	855	err_cleanup:
856	if (!cpsw->usage_count) {	856	if (!cpsw->usage_count) {
		857	napi_disable(&cpsw->napi_rx);
		858	napi_disable(&cpsw->napi_tx);
857	cpdma_ctlr_stop(cpsw->dma);	859	cpdma_ctlr_stop(cpsw->dma);
858	cpsw_destroy_xdp_rxqs(cpsw);	860	cpsw_destroy_xdp_rxqs(cpsw);
859	}	861	}

drivers/net/ethernet/tundra/tsi108_eth.c+4−1

 	data->rxring = dma_alloc_coherent(&data->pdev->dev, rxring_size,
 					  &data->rxdma, GFP_KERNEL);
-	if (!data->rxring)
+	if (!data->rxring) {
+		free_irq(data->irq_num, dev);
 		return -ENOMEM;
+	}
 	data->txring = dma_alloc_coherent(&data->pdev->dev, txring_size,
 					  &data->txdma, GFP_KERNEL);
 	if (!data->txring) {
+		free_irq(data->irq_num, dev);
 		dma_free_coherent(&data->pdev->dev, rxring_size, data->rxring,
 				    data->rxdma);
 		return -ENOMEM;

drivers/net/hamradio/bpqether.c+1−1

@@ -533,7 +533,7 @@ static int bpq_device_event(struct notifier_block *this, · 532 unmodified lines
533	if (!net_eq(dev_net(dev), &init_net))	533	if (!net_eq(dev_net(dev), &init_net))
534	return NOTIFY_DONE;	534	return NOTIFY_DONE;
535		535
536	if (!dev_is_ethdev(dev))	536	if (!dev_is_ethdev(dev) && !bpq_get_ax25_dev(dev))
537	return NOTIFY_DONE;	537	return NOTIFY_DONE;
538		538
539	switch (event) {	539	switch (event) {

drivers/net/macsec.c+17−33

 	return NULL;
 }
-static struct macsec_rx_sc *create_rx_sc(struct net_device *dev, sci_t sci)
+static struct macsec_rx_sc *create_rx_sc(struct net_device *dev, sci_t sci,
+					 bool active)
 {
 	struct macsec_rx_sc *rx_sc;
 	struct macsec_dev *macsec;
 	}
 	rx_sc->sci = sci;
-	rx_sc->active = true;
+	rx_sc->active = active;
 	refcount_set(&rx_sc->refcnt, 1);
 	secy = &macsec_priv(dev)->secy;
 		       secy->key_len);
 		err = macsec_offload(ops->mdo_add_rxsa, &ctx);
+		memzero_explicit(ctx.sa.key, secy->key_len);
 		if (err)
 			goto cleanup;
 	}
 	struct macsec_rx_sc *rx_sc;
 	struct nlattr *tb_rxsc[MACSEC_RXSC_ATTR_MAX + 1];
 	struct macsec_secy *secy;
-	bool was_active;
+	bool active = true;
 	int ret;
 	if (!attrs[MACSEC_ATTR_IFINDEX])
 	secy = &macsec_priv(dev)->secy;
 	sci = nla_get_sci(tb_rxsc[MACSEC_RXSC_ATTR_SCI]);
-	rx_sc = create_rx_sc(dev, sci);
+	if (tb_rxsc[MACSEC_RXSC_ATTR_ACTIVE])
+		active = nla_get_u8(tb_rxsc[MACSEC_RXSC_ATTR_ACTIVE]);
+	rx_sc = create_rx_sc(dev, sci, active);
 	if (IS_ERR(rx_sc)) {
 		rtnl_unlock();
 		return PTR_ERR(rx_sc);
 	}
-	was_active = rx_sc->active;
-	if (tb_rxsc[MACSEC_RXSC_ATTR_ACTIVE])
-		rx_sc->active = !!nla_get_u8(tb_rxsc[MACSEC_RXSC_ATTR_ACTIVE]);
 	if (macsec_is_offloaded(netdev_priv(dev))) {
 		const struct macsec_ops *ops;
 		struct macsec_context ctx;
 	return 0;
 cleanup:
-	rx_sc->active = was_active;
+	del_rx_sc(secy, sci);
+	free_rx_sc(rx_sc);
 	rtnl_unlock();
 	return ret;
 }
 		       secy->key_len);
 		err = macsec_offload(ops->mdo_add_txsa, &ctx);
+		memzero_explicit(ctx.sa.key, secy->key_len);
 		if (err)
 			goto cleanup;
 	}
 	struct macsec_tx_sc *tx_sc = &secy->tx_sc;
 	int i;
-	if (secy->n_rx_sc > 0)
+	if (secy->rx_sc)
 		return true;
 	for (i = 0; i < MACSEC_NUM_AN; i++)
 	if (ret)
 		goto rollback;
-	/* Force features update, since they are different for SW MACSec and
-	 * HW offloading cases.
-	 */
-	netdev_update_features(dev);
 	rtnl_unlock();
 	return 0;
 	return ret;
 }
-#define SW_MACSEC_FEATURES \
+#define MACSEC_FEATURES \
 	(NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST)
-/* If h/w offloading is enabled, use real device features save for
- *   VLAN_FEATURES - they require additional ops
- *   HW_MACSEC - no reason to report it
- */
-#define REAL_DEV_FEATURES(dev) \
-	((dev)->features & ~(NETIF_F_VLAN_FEATURES | NETIF_F_HW_MACSEC))
 static int macsec_dev_init(struct net_device *dev)
 {
 	struct macsec_dev *macsec = macsec_priv(dev);
 		return err;
 	}
-	if (macsec_is_offloaded(macsec)) {
+	dev->features = real_dev->features & MACSEC_FEATURES;
-		dev->features = REAL_DEV_FEATURES(real_dev);
+	dev->features |= NETIF_F_LLTX | NETIF_F_GSO_SOFTWARE;
-	} else {
-		dev->features = real_dev->features & SW_MACSEC_FEATURES;
-		dev->features |= NETIF_F_LLTX | NETIF_F_GSO_SOFTWARE;
-	}
 	dev->needed_headroom = real_dev->needed_headroom +
 			       MACSEC_NEEDED_HEADROOM;
 	struct macsec_dev *macsec = macsec_priv(dev);
 	struct net_device *real_dev = macsec->real_dev;
-	if (macsec_is_offloaded(macsec))
+	features &= (real_dev->features & MACSEC_FEATURES) |
-		return REAL_DEV_FEATURES(real_dev);
-	features &= (real_dev->features & SW_MACSEC_FEATURES) |
 		    NETIF_F_GSO_SOFTWARE | NETIF_F_SOFT_FEATURES;
 	features |= NETIF_F_LLTX;

drivers/net/macvlan.c+3−1

 	/* the macvlan port may be freed by macvlan_uninit when fail to register.
 	 * so we destroy the macvlan port only when it's valid.
 	 */
-	if (create && macvlan_port_get_rtnl(lowerdev))
+	if (create && macvlan_port_get_rtnl(lowerdev)) {
+		macvlan_flush_sources(port, vlan);
 		macvlan_port_destroy(port->dev);
+	}
 	return err;
 }
 EXPORT_SYMBOL_GPL(macvlan_common_newlink);

drivers/net/phy/mscc/mscc_macsec.c+1−0

@@ -632,6 +632,7 @@ static void vsc8584_macsec_free_flow(struct vsc8531_private *priv, · 631 unmodified lines
632		632
633	list_del(&flow->list);	633	list_del(&flow->list);
634	clear_bit(flow->index, bitmap);	634	clear_bit(flow->index, bitmap);
		635	memzero_explicit(flow->key, sizeof(flow->key));
635	kfree(flow);	636	kfree(flow);
636	}	637	}
637		638

drivers/net/tun.c+13−5

 					  skb_headlen(skb));
 		if (unlikely(headlen > skb_headlen(skb))) {
+			WARN_ON_ONCE(1);
+			err = -ENOMEM;
 			dev_core_stats_rx_dropped_inc(tun->dev);
+napi_busy:
 			napi_free_frags(&tfile->napi);
 			rcu_read_unlock();
 			mutex_unlock(&tfile->napi_mutex);
-			WARN_ON(1);
+			return err;
-			return -ENOMEM;
 		}
-		local_bh_disable();
+		if (likely(napi_schedule_prep(&tfile->napi))) {
-		napi_gro_frags(&tfile->napi);
+			local_bh_disable();
-		local_bh_enable();
+			napi_gro_frags(&tfile->napi);
+			napi_complete(&tfile->napi);
+			local_bh_enable();
+		} else {
+			err = -EBUSY;
+			goto napi_busy;
+		}
 		mutex_unlock(&tfile->napi_mutex);
 	} else if (tfile->napi_enabled) {
 		struct sk_buff_head *queue = &tfile->sk.sk_write_queue;

drivers/net/wan/lapbether.c+2−1

 	err = lapb_register(dev, &lapbeth_callbacks);
 	if (err != LAPB_OK) {
+		napi_disable(&lapbeth->napi);
 		pr_err("lapb_register error: %d\n", err);
 		return -ENODEV;
 	}
 	if (dev_net(dev) != &init_net)
 		return NOTIFY_DONE;
-	if (!dev_is_ethdev(dev))
+	if (!dev_is_ethdev(dev) && !lapbeth_get_x25_dev(dev))
 		return NOTIFY_DONE;
 	switch (event) {

drivers/net/wireless/ath/ath11k/qmi.h+1−1

@@ -27,7 +27,7 @@ · 26 unmodified lines
27	#define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52	27	#define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52
28	#define ATH11K_QMI_CALDB_SIZE 0x480000	28	#define ATH11K_QMI_CALDB_SIZE 0x480000
29	#define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20	29	#define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20
30	#define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 3	30	#define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 5
31		31
32	#define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035	32	#define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035
33	#define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037	33	#define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037

drivers/net/wireless/ath/ath11k/reg.c+1−5

 		goto err;
 	}
-	rtnl_lock();
+	ret = regulatory_set_wiphy_regd(ar->hw->wiphy, regd_copy);
-	wiphy_lock(ar->hw->wiphy);
-	ret = regulatory_set_wiphy_regd_sync(ar->hw->wiphy, regd_copy);
-	wiphy_unlock(ar->hw->wiphy);
-	rtnl_unlock();
 	kfree(regd_copy);

drivers/net/wireless/broadcom/brcm80211/brcmfmac/fweh.c+4−0

 			  brcmf_fweh_event_name(event->code), event->code,
 			  event->emsg.ifidx, event->emsg.bsscfgidx,
 			  event->emsg.addr);
+		if (event->emsg.bsscfgidx >= BRCMF_MAX_IFS) {
+			bphy_err(drvr, "invalid bsscfg index: %u\n", event->emsg.bsscfgidx);
+			goto event_free;
+		}
 		/* convert event message */
 		emsg_be = &event->emsg;

drivers/net/wireless/cisco/airo.c+14−4

 	return -1;
 }
-static int set_wep_key(struct airo_info *ai, u16 index, const char *key,
+static int set_wep_key(struct airo_info *ai, u16 index, const u8 *key,
 		       u16 keylen, int perm, int lock)
 {
 	static const unsigned char macaddr[ETH_ALEN] = { 0x01, 0, 0, 0, 0, 0 };
 	struct net_device *dev = pde_data(inode);
 	struct airo_info *ai = dev->ml_priv;
 	int i, rc;
-	char key[16];
+	u8 key[16];
 	u16 index = 0;
 	int j = 0;
 	}
 	for (i = 0; i < 16*3 && data->wbuffer[i+j]; i++) {
+		int val;
+		if (i % 3 == 2)
+			continue;
+		val = hex_to_bin(data->wbuffer[i+j]);
+		if (val < 0) {
+			airo_print_err(ai->dev->name, "WebKey passed invalid key hex");
+			return;
+		}
 		switch(i%3) {
 		case 0:
-			key[i/3] = hex_to_bin(data->wbuffer[i+j])<<4;
+			key[i/3] = (u8)val << 4;
 			break;
 		case 1:
-			key[i/3] |= hex_to_bin(data->wbuffer[i+j]);
+			key[i/3] |= (u8)val;
 			break;
 		}
 	}

drivers/net/wireless/mac80211_hwsim.c+5−0

 	struct hwsim_vif_priv *vp = (void *)vif->drv_priv;
 	struct sk_buff *skb;
 	struct ieee80211_hdr *hdr;
+	struct ieee80211_tx_info *cb;
 	if (!vp->assoc)
 		return;
 	memcpy(hdr->addr2, mac, ETH_ALEN);
 	memcpy(hdr->addr3, vp->bssid, ETH_ALEN);
+	cb = IEEE80211_SKB_CB(skb);
+	cb->control.rates[0].count = 1;
+	cb->control.rates[1].idx = -1;
 	rcu_read_lock();
 	mac80211_hwsim_tx_frame(data->hw, skb,
 				rcu_dereference(vif->bss_conf.chanctx_conf)->def.chan);

drivers/net/wireless/ralink/rt2x00/rt2400pci.c+4−4

@@ -1023,9 +1023,9 @@ static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, · 1022 unmodified lines
1023	{	1023	{
1024	u32 reg, reg2;	1024	u32 reg, reg2;
1025	unsigned int i;	1025	unsigned int i;
1026	char put_to_sleep;	1026	bool put_to_sleep;
1027	char bbp_state;	1027	u8 bbp_state;
1028	char rf_state;	1028	u8 rf_state;
1029		1029
1030	put_to_sleep = (state != STATE_AWAKE);	1030	put_to_sleep = (state != STATE_AWAKE);
1031		1031
@@ -1561,7 +1561,7 @@ static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 529 unmodified lines
1561	{	1561	{
1562	struct hw_mode_spec *spec = &rt2x00dev->spec;	1562	struct hw_mode_spec *spec = &rt2x00dev->spec;
1563	struct channel_info *info;	1563	struct channel_info *info;
1564	char *tx_power;	1564	u8 *tx_power;
1565	unsigned int i;	1565	unsigned int i;
1566		1566
1567	/*	1567	/*

drivers/net/wireless/ralink/rt2x00/rt2400pci.h+1−1

@@ -939,7 +939,7 @@ · 938 unmodified lines
939	#define DEFAULT_TXPOWER 39	939	#define DEFAULT_TXPOWER 39
940		940
941	#define __CLAMP_TX(__txpower) \	941	#define __CLAMP_TX(__txpower) \
942	clamp_t(char, (__txpower), MIN_TXPOWER, MAX_TXPOWER)	942	clamp_t(u8, (__txpower), MIN_TXPOWER, MAX_TXPOWER)
943		943
944	#define TXPOWER_FROM_DEV(__txpower) \	944	#define TXPOWER_FROM_DEV(__txpower) \
945	((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER)	945	((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER)

drivers/net/wireless/ralink/rt2x00/rt2500pci.c+4−4

@@ -1176,9 +1176,9 @@ static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev, · 1175 unmodified lines
1176	{	1176	{
1177	u32 reg, reg2;	1177	u32 reg, reg2;
1178	unsigned int i;	1178	unsigned int i;
1179	char put_to_sleep;	1179	bool put_to_sleep;
1180	char bbp_state;	1180	u8 bbp_state;
1181	char rf_state;	1181	u8 rf_state;
1182		1182
1183	put_to_sleep = (state != STATE_AWAKE);	1183	put_to_sleep = (state != STATE_AWAKE);
1184		1184
@@ -1856,7 +1856,7 @@ static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 671 unmodified lines
1856	{	1856	{
1857	struct hw_mode_spec *spec = &rt2x00dev->spec;	1857	struct hw_mode_spec *spec = &rt2x00dev->spec;
1858	struct channel_info *info;	1858	struct channel_info *info;
1859	char *tx_power;	1859	u8 *tx_power;
1860	unsigned int i;	1860	unsigned int i;
1861		1861
1862	/*	1862	/*

drivers/net/wireless/ralink/rt2x00/rt2500pci.h+1−1

@@ -1219,6 +1219,6 @@ · 1218 unmodified lines
1219	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)	1219	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1220		1220
1221	#define TXPOWER_TO_DEV(__txpower) \	1221	#define TXPOWER_TO_DEV(__txpower) \
1222	clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)	1222	clamp_t(u8, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1223		1223
1224	#endif /* RT2500PCI_H */	1224	#endif /* RT2500PCI_H */

drivers/net/wireless/ralink/rt2x00/rt2500usb.c+4−4

@@ -984,9 +984,9 @@ static int rt2500usb_set_state(struct rt2x00_dev *rt2x00dev, · 983 unmodified lines
984	u16 reg;	984	u16 reg;
985	u16 reg2;	985	u16 reg2;
986	unsigned int i;	986	unsigned int i;
987	char put_to_sleep;	987	bool put_to_sleep;
988	char bbp_state;	988	u8 bbp_state;
989	char rf_state;	989	u8 rf_state;
990		990
991	put_to_sleep = (state != STATE_AWAKE);	991	put_to_sleep = (state != STATE_AWAKE);
992		992
@@ -1663,7 +1663,7 @@ static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 670 unmodified lines
1663	{	1663	{
1664	struct hw_mode_spec *spec = &rt2x00dev->spec;	1664	struct hw_mode_spec *spec = &rt2x00dev->spec;
1665	struct channel_info *info;	1665	struct channel_info *info;
1666	char *tx_power;	1666	u8 *tx_power;
1667	unsigned int i;	1667	unsigned int i;
1668		1668
1669	/*	1669	/*

drivers/net/wireless/ralink/rt2x00/rt2500usb.h+1−1

@@ -839,6 +839,6 @@ · 838 unmodified lines
839	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)	839	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
840		840
841	#define TXPOWER_TO_DEV(__txpower) \	841	#define TXPOWER_TO_DEV(__txpower) \
842	clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)	842	clamp_t(u8, __txpower, MIN_TXPOWER, MAX_TXPOWER)
843		843
844	#endif /* RT2500USB_H */	844	#endif /* RT2500USB_H */

drivers/net/wireless/ralink/rt2x00/rt2800lib.c+30−30

@@ -3372,10 +3372,10 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, · 3371 unmodified lines
3372	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {	3372	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3373	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {	3373	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3374	/* r55/r59 value array of channel 1~14 */	3374	/* r55/r59 value array of channel 1~14 */
3375	static const char r55_bt_rev[] = {0x83, 0x83,	3375	static const u8 r55_bt_rev[] = {0x83, 0x83,
3376	0x83, 0x73, 0x73, 0x63, 0x53, 0x53,	3376	0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
3377	0x53, 0x43, 0x43, 0x43, 0x43, 0x43};	3377	0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
3378	static const char r59_bt_rev[] = {0x0e, 0x0e,	3378	static const u8 r59_bt_rev[] = {0x0e, 0x0e,
3379	0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,	3379	0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
3380	0x07, 0x07, 0x07, 0x07, 0x07, 0x07};	3380	0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
3381		3381
@@ -3384,7 +3384,7 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, · 2 unmodified lines
3384	rt2800_rfcsr_write(rt2x00dev, 59,	3384	rt2800_rfcsr_write(rt2x00dev, 59,
3385	r59_bt_rev[idx]);	3385	r59_bt_rev[idx]);
3386	} else {	3386	} else {
3387	static const char r59_bt[] = {0x8b, 0x8b, 0x8b,	3387	static const u8 r59_bt[] = {0x8b, 0x8b, 0x8b,
3388	0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,	3388	0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
3389	0x88, 0x88, 0x86, 0x85, 0x84};	3389	0x88, 0x88, 0x86, 0x85, 0x84};
3390		3390
@@ -3392,10 +3392,10 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, · 1 unmodified line
3392	}	3392	}
3393	} else {	3393	} else {
3394	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {	3394	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3395	static const char r55_nonbt_rev[] = {0x23, 0x23,	3395	static const u8 r55_nonbt_rev[] = {0x23, 0x23,
3396	0x23, 0x23, 0x13, 0x13, 0x03, 0x03,	3396	0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
3397	0x03, 0x03, 0x03, 0x03, 0x03, 0x03};	3397	0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
3398	static const char r59_nonbt_rev[] = {0x07, 0x07,	3398	static const u8 r59_nonbt_rev[] = {0x07, 0x07,
3399	0x07, 0x07, 0x07, 0x07, 0x07, 0x07,	3399	0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
3400	0x07, 0x07, 0x06, 0x05, 0x04, 0x04};	3400	0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
3401		3401
@@ -3406,14 +3406,14 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, · 4 unmodified lines
3406	} else if (rt2x00_rt(rt2x00dev, RT5390) \|\|	3406	} else if (rt2x00_rt(rt2x00dev, RT5390) \|\|
3407	rt2x00_rt(rt2x00dev, RT5392) \|\|	3407	rt2x00_rt(rt2x00dev, RT5392) \|\|
3408	rt2x00_rt(rt2x00dev, RT6352)) {	3408	rt2x00_rt(rt2x00dev, RT6352)) {
3409	static const char r59_non_bt[] = {0x8f, 0x8f,	3409	static const u8 r59_non_bt[] = {0x8f, 0x8f,
3410	0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,	3410	0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
3411	0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};	3411	0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
3412		3412
3413	rt2800_rfcsr_write(rt2x00dev, 59,	3413	rt2800_rfcsr_write(rt2x00dev, 59,
3414	r59_non_bt[idx]);	3414	r59_non_bt[idx]);
3415	} else if (rt2x00_rt(rt2x00dev, RT5350)) {	3415	} else if (rt2x00_rt(rt2x00dev, RT5350)) {
3416	static const char r59_non_bt[] = {0x0b, 0x0b,	3416	static const u8 r59_non_bt[] = {0x0b, 0x0b,
3417	0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,	3417	0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
3418	0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};	3418	0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
3419		3419
@@ -4035,23 +4035,23 @@ static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) · 615 unmodified lines
4035	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);	4035	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
4036	}	4036	}
4037		4037
4038	static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,	4038	static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
4039	unsigned int channel,	4039	unsigned int channel,
4040	char txpower)	4040	s8 txpower)
4041	{	4041	{
4042	if (rt2x00_rt(rt2x00dev, RT3593) \|\|	4042	if (rt2x00_rt(rt2x00dev, RT3593) \|\|
4043	rt2x00_rt(rt2x00dev, RT3883))	4043	rt2x00_rt(rt2x00dev, RT3883))
4044	txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);	4044	txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
4045		4045
4046	if (channel <= 14)	4046	if (channel <= 14)
4047	return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);	4047	return clamp_t(s8, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
4048		4048
4049	if (rt2x00_rt(rt2x00dev, RT3593) \|\|	4049	if (rt2x00_rt(rt2x00dev, RT3593) \|\|
4050	rt2x00_rt(rt2x00dev, RT3883))	4050	rt2x00_rt(rt2x00dev, RT3883))
4051	return clamp_t(char, txpower, MIN_A_TXPOWER_3593,	4051	return clamp_t(s8, txpower, MIN_A_TXPOWER_3593,
4052	MAX_A_TXPOWER_3593);	4052	MAX_A_TXPOWER_3593);
4053	else	4053	else
4054	return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);	4054	return clamp_t(s8, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
4055	}	4055	}
4056		4056
4057	static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,	4057	static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
@@ -8530,7 +8530,7 @@ static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) · 4472 unmodified lines
8530	u8 bytevalue = 0;	8530	u8 bytevalue = 0;
8531	int rcalcode;	8531	int rcalcode;
8532	u8 r_cal_code = 0;	8532	u8 r_cal_code = 0;
8533	char d1 = 0, d2 = 0;	8533	s8 d1 = 0, d2 = 0;
8534	u8 rfvalue;	8534	u8 rfvalue;
8535	u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG;	8535	u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG;
8536	u32 maccfg;	8536	u32 maccfg;
@@ -8591,7 +8591,7 @@ static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) · 54 unmodified lines
8591	if (bytevalue > 128)	8591	if (bytevalue > 128)
8592	d1 = bytevalue - 256;	8592	d1 = bytevalue - 256;
8593	else	8593	else
8594	d1 = (char)bytevalue;	8594	d1 = (s8)bytevalue;
8595	rt2800_bbp_write(rt2x00dev, 22, 0x0);	8595	rt2800_bbp_write(rt2x00dev, 22, 0x0);
8596	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);	8596	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);
8597		8597
@@ -8601,7 +8601,7 @@ static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) · 3 unmodified lines
8601	if (bytevalue > 128)	8601	if (bytevalue > 128)
8602	d2 = bytevalue - 256;	8602	d2 = bytevalue - 256;
8603	else	8603	else
8604	d2 = (char)bytevalue;	8604	d2 = (s8)bytevalue;
8605	rt2800_bbp_write(rt2x00dev, 22, 0x0);	8605	rt2800_bbp_write(rt2x00dev, 22, 0x0);
8606		8606
8607	rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);	8607	rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);
@@ -8703,7 +8703,7 @@ static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev) · 95 unmodified lines
8703	static u32 rt2800_do_sqrt_accumulation(u32 si)	8703	static u32 rt2800_do_sqrt_accumulation(u32 si)
8704	{	8704	{
8705	u32 root, root_pre, bit;	8705	u32 root, root_pre, bit;
8706	char i;	8706	s8 i;
8707		8707
8708	bit = 1 << 15;	8708	bit = 1 << 15;
8709	root = 0;	8709	root = 0;
@@ -9330,11 +9330,11 @@ static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, · 620 unmodified lines
9330	u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])	9330	u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
9331	{	9331	{
9332	u32 p0 = 0, p1 = 0, pf = 0;	9332	u32 p0 = 0, p1 = 0, pf = 0;
9333	char idx0 = 0, idx1 = 0;	9333	s8 idx0 = 0, idx1 = 0;
9334	u8 idxf[] = {0x00, 0x00};	9334	u8 idxf[] = {0x00, 0x00};
9335	u8 ibit = 0x20;	9335	u8 ibit = 0x20;
9336	u8 iorq;	9336	u8 iorq;
9337	char bidx;	9337	s8 bidx;
9338		9338
9339	rt2800_bbp_write(rt2x00dev, 158, 0xb0);	9339	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
9340	rt2800_bbp_write(rt2x00dev, 159, 0x80);	9340	rt2800_bbp_write(rt2x00dev, 159, 0x80);
@@ -9384,17 +9384,17 @@ static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, · 43 unmodified lines
9384	static void rt2800_iq_search(struct rt2x00_dev rt2x00dev, u8 ch_idx, u8 ges, u8 *pes)	9384	static void rt2800_iq_search(struct rt2x00_dev rt2x00dev, u8 ch_idx, u8 ges, u8 *pes)
9385	{	9385	{
9386	u32 p0 = 0, p1 = 0, pf = 0;	9386	u32 p0 = 0, p1 = 0, pf = 0;
9387	char perr = 0, gerr = 0, iq_err = 0;	9387	s8 perr = 0, gerr = 0, iq_err = 0;
9388	char pef = 0, gef = 0;	9388	s8 pef = 0, gef = 0;
9389	char psta, pend;	9389	s8 psta, pend;
9390	char gsta, gend;	9390	s8 gsta, gend;
9391		9391
9392	u8 ibit = 0x20;	9392	u8 ibit = 0x20;
9393	u8 first_search = 0x00, touch_neg_max = 0x00;	9393	u8 first_search = 0x00, touch_neg_max = 0x00;
9394	char idx0 = 0, idx1 = 0;	9394	s8 idx0 = 0, idx1 = 0;
9395	u8 gop;	9395	u8 gop;
9396	u8 bbp = 0;	9396	u8 bbp = 0;
9397	char bidx;	9397	s8 bidx;
9398		9398
9399	for (bidx = 5; bidx >= 1; bidx--) {	9399	for (bidx = 5; bidx >= 1; bidx--) {
9400	for (gop = 0; gop < 2; gop++) {	9400	for (gop = 0; gop < 2; gop++) {
@@ -10043,11 +10043,11 @@ static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) · 642 unmodified lines
10043	return 0;	10043	return 0;
10044	}	10044	}
10045		10045
10046	static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)	10046	static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
10047	{	10047	{
10048	unsigned int cnt;	10048	unsigned int cnt;
10049	u8 bbp_val;	10049	u8 bbp_val;
10050	char cal_val;	10050	s8 cal_val;
10051		10051
10052	rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);	10052	rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
10053		10053
@@ -10079,7 +10079,7 @@ static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, · 25 unmodified lines
10079	u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;	10079	u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
10080	int loop = 0, is_ht40, cnt;	10080	int loop = 0, is_ht40, cnt;
10081	u8 bbp_val, rf_val;	10081	u8 bbp_val, rf_val;
10082	char cal_r32_init, cal_r32_val, cal_diff;	10082	s8 cal_r32_init, cal_r32_val, cal_diff;
10083	u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;	10083	u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
10084	u8 saverfb5r06, saverfb5r07;	10084	u8 saverfb5r06, saverfb5r07;
10085	u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;	10085	u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
@@ -11550,9 +11550,9 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 1464 unmodified lines
11550	{	11550	{
11551	struct hw_mode_spec *spec = &rt2x00dev->spec;	11551	struct hw_mode_spec *spec = &rt2x00dev->spec;
11552	struct channel_info *info;	11552	struct channel_info *info;
11553	char *default_power1;	11553	s8 *default_power1;
11554	char *default_power2;	11554	s8 *default_power2;
11555	char *default_power3;	11555	s8 *default_power3;
11556	unsigned int i, tx_chains, rx_chains;	11556	unsigned int i, tx_chains, rx_chains;
11557	u32 reg;	11557	u32 reg;
11558		11558

drivers/net/wireless/ralink/rt2x00/rt2800lib.h+4−4

@@ -32,10 +32,10 @@ struct rf_reg_pair { · 31 unmodified lines
32	struct rt2800_drv_data {	32	struct rt2800_drv_data {
33	u8 calibration_bw20;	33	u8 calibration_bw20;
34	u8 calibration_bw40;	34	u8 calibration_bw40;
35	char rx_calibration_bw20;	35	s8 rx_calibration_bw20;
36	char rx_calibration_bw40;	36	s8 rx_calibration_bw40;
37	char tx_calibration_bw20;	37	s8 tx_calibration_bw20;
38	char tx_calibration_bw40;	38	s8 tx_calibration_bw40;
39	u8 bbp25;	39	u8 bbp25;
40	u8 bbp26;	40	u8 bbp26;
41	u8 txmixer_gain_24g;	41	u8 txmixer_gain_24g;

drivers/net/wireless/ralink/rt2x00/rt2x00usb.c+3−3

@@ -117,12 +117,12 @@ int rt2x00usb_vendor_request_buff(struct rt2x00_dev *rt2x00dev, · 116 unmodified lines
117	const u16 buffer_length)	117	const u16 buffer_length)
118	{	118	{
119	int status = 0;	119	int status = 0;
120	unsigned char *tb;	120	u8 *tb;
121	u16 off, len, bsize;	121	u16 off, len, bsize;
122		122
123	mutex_lock(&rt2x00dev->csr_mutex);	123	mutex_lock(&rt2x00dev->csr_mutex);
124		124
125	tb = (char *)buffer;	125	tb = (u8 *)buffer;
126	off = offset;	126	off = offset;
127	len = buffer_length;	127	len = buffer_length;
128	while (len && !status) {	128	while (len && !status) {
@@ -215,7 +215,7 @@ void rt2x00usb_register_read_async(struct rt2x00_dev *rt2x00dev, · 86 unmodified lines
215	rd->cr.wLength = cpu_to_le16(sizeof(u32));	215	rd->cr.wLength = cpu_to_le16(sizeof(u32));
216		216
217	usb_fill_control_urb(urb, usb_dev, usb_rcvctrlpipe(usb_dev, 0),	217	usb_fill_control_urb(urb, usb_dev, usb_rcvctrlpipe(usb_dev, 0),
218	(unsigned char *)(&rd->cr), &rd->reg, sizeof(rd->reg),	218	(u8 *)(&rd->cr), &rd->reg, sizeof(rd->reg),
219	rt2x00usb_register_read_async_cb, rd);	219	rt2x00usb_register_read_async_cb, rd);
220	usb_anchor_urb(urb, rt2x00dev->anchor);	220	usb_anchor_urb(urb, rt2x00dev->anchor);
221	if (usb_submit_urb(urb, GFP_ATOMIC) < 0) {	221	if (usb_submit_urb(urb, GFP_ATOMIC) < 0) {

drivers/net/wireless/ralink/rt2x00/rt61pci.c+2−2

@@ -1709,7 +1709,7 @@ static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) · 1708 unmodified lines
1709	{	1709	{
1710	u32 reg, reg2;	1710	u32 reg, reg2;
1711	unsigned int i;	1711	unsigned int i;
1712	char put_to_sleep;	1712	bool put_to_sleep;
1713		1713
1714	put_to_sleep = (state != STATE_AWAKE);	1714	put_to_sleep = (state != STATE_AWAKE);
1715		1715
@@ -2656,7 +2656,7 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 940 unmodified lines
2656	{	2656	{
2657	struct hw_mode_spec *spec = &rt2x00dev->spec;	2657	struct hw_mode_spec *spec = &rt2x00dev->spec;
2658	struct channel_info *info;	2658	struct channel_info *info;
2659	char *tx_power;	2659	u8 *tx_power;
2660	unsigned int i;	2660	unsigned int i;
2661		2661
2662	/*	2662	/*

drivers/net/wireless/ralink/rt2x00/rt61pci.h+1−1

@@ -1484,6 +1484,6 @@ struct hw_pairwise_ta_entry { · 1483 unmodified lines
1484	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)	1484	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1485		1485
1486	#define TXPOWER_TO_DEV(__txpower) \	1486	#define TXPOWER_TO_DEV(__txpower) \
1487	clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)	1487	clamp_t(u8, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1488		1488
1489	#endif /* RT61PCI_H */	1489	#endif /* RT61PCI_H */

drivers/net/wireless/ralink/rt2x00/rt73usb.c+2−2

@@ -1378,7 +1378,7 @@ static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) · 1377 unmodified lines
1378	{	1378	{
1379	u32 reg, reg2;	1379	u32 reg, reg2;
1380	unsigned int i;	1380	unsigned int i;
1381	char put_to_sleep;	1381	bool put_to_sleep;
1382		1382
1383	put_to_sleep = (state != STATE_AWAKE);	1383	put_to_sleep = (state != STATE_AWAKE);
1384		1384
@@ -2090,7 +2090,7 @@ static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev) · 705 unmodified lines
2090	{	2090	{
2091	struct hw_mode_spec *spec = &rt2x00dev->spec;	2091	struct hw_mode_spec *spec = &rt2x00dev->spec;
2092	struct channel_info *info;	2092	struct channel_info *info;
2093	char *tx_power;	2093	u8 *tx_power;
2094	unsigned int i;	2094	unsigned int i;
2095		2095
2096	/*	2096	/*

drivers/net/wireless/ralink/rt2x00/rt73usb.h+1−1

@@ -1063,6 +1063,6 @@ struct hw_pairwise_ta_entry { · 1062 unmodified lines
1063	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)	1063	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1064		1064
1065	#define TXPOWER_TO_DEV(__txpower) \	1065	#define TXPOWER_TO_DEV(__txpower) \
1066	clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)	1066	clamp_t(u8, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1067		1067
1068	#endif /* RT73USB_H */	1068	#endif /* RT73USB_H */

drivers/net/wwan/Kconfig+1−1

@@ -94,7 +94,7 @@ config RPMSG_WWAN_CTRL · 93 unmodified lines
94		94
95	config IOSM	95	config IOSM
96	tristate "IOSM Driver for Intel M.2 WWAN Device"	96	tristate "IOSM Driver for Intel M.2 WWAN Device"
97	depends on INTEL_IOMMU	97	depends on PCI
98	select NET_DEVLINK	98	select NET_DEVLINK
99	select RELAY if WWAN_DEBUGFS	99	select RELAY if WWAN_DEBUGFS
100	help	100	help

drivers/net/wwan/iosm/iosm_ipc_coredump.c+1−0

@@ -2,6 +2,7 @@ · 1 unmodified line
2	/*	2	/*
3	* Copyright (C) 2020-2021 Intel Corporation.	3	* Copyright (C) 2020-2021 Intel Corporation.
4	*/	4	*/
		5	#include <linux/vmalloc.h>
5		6
6	#include "iosm_ipc_coredump.h"	7	#include "iosm_ipc_coredump.h"
7		8

drivers/net/wwan/iosm/iosm_ipc_devlink.c+1−0

@@ -2,6 +2,7 @@ · 1 unmodified line
2	/*	2	/*
3	* Copyright (C) 2020-2021 Intel Corporation.	3	* Copyright (C) 2020-2021 Intel Corporation.
4	*/	4	*/
		5	#include <linux/vmalloc.h>
5		6
6	#include "iosm_ipc_chnl_cfg.h"	7	#include "iosm_ipc_chnl_cfg.h"
7	#include "iosm_ipc_coredump.h"	8	#include "iosm_ipc_coredump.h"

drivers/net/wwan/iosm/iosm_ipc_imem_ops.c+8−0

@@ -91,6 +91,14 @@ void ipc_imem_wwan_channel_init(struct iosm_imem *ipc_imem, · 90 unmodified lines
91	}	91	}
92		92
93	ipc_chnl_cfg_get(&chnl_cfg, ipc_imem->nr_of_channels);	93	ipc_chnl_cfg_get(&chnl_cfg, ipc_imem->nr_of_channels);
		94
		95	if (ipc_imem->mmio->mux_protocol == MUX_AGGREGATION &&
		96	ipc_imem->nr_of_channels == IPC_MEM_IP_CHL_ID_0) {
		97	chnl_cfg.ul_nr_of_entries = IPC_MEM_MAX_TDS_MUX_AGGR_UL;
		98	chnl_cfg.dl_nr_of_entries = IPC_MEM_MAX_TDS_MUX_AGGR_DL;
		99	chnl_cfg.dl_buf_size = IPC_MEM_MAX_ADB_BUF_SIZE;
		100	}
		101
94	ipc_imem_channel_init(ipc_imem, IPC_CTYPE_WWAN, chnl_cfg,	102	ipc_imem_channel_init(ipc_imem, IPC_CTYPE_WWAN, chnl_cfg,
95	IRQ_MOD_OFF);	103	IRQ_MOD_OFF);
96		104

drivers/net/wwan/iosm/iosm_ipc_mux.h+1−0

@@ -10,6 +10,7 @@ · 9 unmodified lines
10		10
11	#define IPC_MEM_MAX_UL_DG_ENTRIES 100	11	#define IPC_MEM_MAX_UL_DG_ENTRIES 100
12	#define IPC_MEM_MAX_TDS_MUX_AGGR_UL 60	12	#define IPC_MEM_MAX_TDS_MUX_AGGR_UL 60
		13	#define IPC_MEM_MAX_TDS_MUX_AGGR_DL 60
13		14
14	#define IPC_MEM_MAX_ADB_BUF_SIZE (16 * 1024)	15	#define IPC_MEM_MAX_ADB_BUF_SIZE (16 * 1024)
15	#define IPC_MEM_MAX_UL_ADB_BUF_SIZE IPC_MEM_MAX_ADB_BUF_SIZE	16	#define IPC_MEM_MAX_UL_ADB_BUF_SIZE IPC_MEM_MAX_ADB_BUF_SIZE

drivers/net/wwan/iosm/iosm_ipc_pcie.c+15−3

  */
 static enum ipc_pcie_sleep_state ipc_pcie_read_bios_cfg(struct device *dev)
 {
+	enum ipc_pcie_sleep_state sleep_state = IPC_PCIE_D0L12;
 	union acpi_object *object;
 	acpi_handle handle_acpi;
 	}
 	object = acpi_evaluate_dsm(handle_acpi, &wwan_acpi_guid, 0, 3, NULL);
+	if (!object)
+		goto default_ret;
+	if (object->integer.value == 3)
+		sleep_state = IPC_PCIE_D3L2;
-	if (object && object->integer.value == 3)
+	kfree(object);
-		return IPC_PCIE_D3L2;
 default_ret:
-	return IPC_PCIE_D0L12;
+	return sleep_state;
 }
 static int ipc_pcie_probe(struct pci_dev *pci,
 			  const struct pci_device_id *pci_id)
 {
 	struct iosm_pcie *ipc_pcie = kzalloc(sizeof(*ipc_pcie), GFP_KERNEL);
+	int ret;
 	pr_debug("Probing device 0x%X from the vendor 0x%X", pci_id->device,
 		 pci_id->vendor);
 		goto pci_enable_fail;
 	}
+	ret = dma_set_mask(ipc_pcie->dev, DMA_BIT_MASK(64));
+	if (ret) {
+		dev_err(ipc_pcie->dev, "Could not set PCI DMA mask: %d", ret);
+		return ret;
+	}
 	ipc_pcie_config_aspm(ipc_pcie);
 	dev_dbg(ipc_pcie->dev, "PCIe device enabled.");

drivers/net/wwan/iosm/iosm_ipc_wwan.c+7−36

  * @ipc_imem:		Pointer to imem data-struct
  * @sub_netlist:	List of active netdevs
  * @dev:		Pointer device structure
- * @if_mutex:		Mutex used for add and remove interface id
  */
 struct iosm_wwan {
 	struct iosm_imem *ipc_imem;
 	struct iosm_netdev_priv __rcu *sub_netlist[IP_MUX_SESSION_END + 1];
 	struct device *dev;
-	struct mutex if_mutex; /* Mutex used for add and remove interface id */
 };
 /* Bring-up the wwan net link */
 	struct iosm_netdev_priv *priv = wwan_netdev_drvpriv(netdev);
 	struct iosm_wwan *ipc_wwan = priv->ipc_wwan;
 	int if_id = priv->if_id;
-	int ret;
 	if (if_id < IP_MUX_SESSION_START ||
 	    if_id >= ARRAY_SIZE(ipc_wwan->sub_netlist))
 		return -EINVAL;
-	mutex_lock(&ipc_wwan->if_mutex);
 	/* get channel id */
 	priv->ch_id = ipc_imem_sys_wwan_open(ipc_wwan->ipc_imem, if_id);
 		dev_err(ipc_wwan->dev,
 			"cannot connect wwan0 & id %d to the IPC mem layer",
 			if_id);
-		ret = -ENODEV;
+		return -ENODEV;
-		goto out;
 	}
 	/* enable tx path, DL data may follow */
 	dev_dbg(ipc_wwan->dev, "Channel id %d allocated to if_id %d",
 		priv->ch_id, priv->if_id);
-	ret = 0;
+	return 0;
-out:
-	mutex_unlock(&ipc_wwan->if_mutex);
-	return ret;
 }
 /* Bring-down the wwan net link */
 	netif_stop_queue(netdev);
-	mutex_lock(&priv->ipc_wwan->if_mutex);
 	ipc_imem_sys_wwan_close(priv->ipc_wwan->ipc_imem, priv->if_id,
 				priv->ch_id);
 	priv->ch_id = -1;
-	mutex_unlock(&priv->ipc_wwan->if_mutex);
 	return 0;
 }
 	iosm_dev->max_mtu = ETH_MAX_MTU;
 	iosm_dev->flags = IFF_POINTOPOINT | IFF_NOARP;
+	iosm_dev->needs_free_netdev = true;
 	iosm_dev->netdev_ops = &ipc_inm_ops;
 }
 	priv->netdev = dev;
 	priv->ipc_wwan = ipc_wwan;
-	mutex_lock(&ipc_wwan->if_mutex);
+	if (rcu_access_pointer(ipc_wwan->sub_netlist[if_id]))
-	if (rcu_access_pointer(ipc_wwan->sub_netlist[if_id])) {
+		return -EBUSY;
-		err = -EBUSY;
-		goto out_unlock;
-	}
 	err = register_netdevice(dev);
 	if (err)
-		goto out_unlock;
+		return err;
 	rcu_assign_pointer(ipc_wwan->sub_netlist[if_id], priv);
-	mutex_unlock(&ipc_wwan->if_mutex);
 	netif_device_attach(dev);
 	return 0;
-out_unlock:
-	mutex_unlock(&ipc_wwan->if_mutex);
-	return err;
 }
 static void ipc_wwan_dellink(void *ctxt, struct net_device *dev,
 		    if_id >= ARRAY_SIZE(ipc_wwan->sub_netlist)))
 		return;
-	mutex_lock(&ipc_wwan->if_mutex);
 	if (WARN_ON(rcu_access_pointer(ipc_wwan->sub_netlist[if_id]) != priv))
-		goto unlock;
+		return;
 	RCU_INIT_POINTER(ipc_wwan->sub_netlist[if_id], NULL);
 	/* unregistering includes synchronize_net() */
 	unregister_netdevice_queue(dev, head);
-unlock:
-	mutex_unlock(&ipc_wwan->if_mutex);
 }
 static const struct wwan_ops iosm_wwan_ops = {
 	ipc_wwan->dev = dev;
 	ipc_wwan->ipc_imem = ipc_imem;
-	mutex_init(&ipc_wwan->if_mutex);
 	/* WWAN core will create a netdev for the default IP MUX channel */
 	if (wwan_register_ops(ipc_wwan->dev, &iosm_wwan_ops, ipc_wwan,
 			      IP_MUX_SESSION_DEFAULT)) {
-		mutex_destroy(&ipc_wwan->if_mutex);
 		kfree(ipc_wwan);
 		return NULL;
 	}
 	/* This call will remove all child netdev(s) */
 	wwan_unregister_ops(ipc_wwan->dev);
-	mutex_destroy(&ipc_wwan->if_mutex);
 	kfree(ipc_wwan);
 }

drivers/net/wwan/mhi_wwan_mbim.c+1−0

@@ -582,6 +582,7 @@ static void mhi_mbim_setup(struct net_device *ndev) · 581 unmodified lines
582	ndev->min_mtu = ETH_MIN_MTU;	582	ndev->min_mtu = ETH_MIN_MTU;
583	ndev->max_mtu = MHI_MAX_BUF_SZ - ndev->needed_headroom;	583	ndev->max_mtu = MHI_MAX_BUF_SZ - ndev->needed_headroom;
584	ndev->tx_queue_len = 1000;	584	ndev->tx_queue_len = 1000;
		585	ndev->needs_free_netdev = true;
585	}	586	}
586		587
587	static const struct wwan_ops mhi_mbim_wwan_ops = {	588	static const struct wwan_ops mhi_mbim_wwan_ops = {

drivers/nvme/host/core.c+1−2

 	if (req->mq_hctx->type == HCTX_TYPE_POLL)
 		req->cmd_flags |= REQ_POLLED;
 	nvme_clear_nvme_request(req);
+	req->rq_flags |= RQF_QUIET;
 	memcpy(nvme_req(req)->cmd, cmd, sizeof(*cmd));
 }
 EXPORT_SYMBOL_GPL(nvme_init_request);
 			goto out;
 	}
-	req->rq_flags |= RQF_QUIET;
 	ret = nvme_execute_rq(req, at_head);
 	if (result && ret >= 0)
 		*result = nvme_req(req)->result;
 	rq->timeout = ctrl->kato * HZ;
 	rq->end_io = nvme_keep_alive_end_io;
 	rq->end_io_data = ctrl;
-	rq->rq_flags |= RQF_QUIET;
 	blk_execute_rq_nowait(rq, false);
 }

drivers/nvme/host/pci.c+0−2

 	abort_req->end_io = abort_endio;
 	abort_req->end_io_data = NULL;
-	abort_req->rq_flags |= RQF_QUIET;
 	blk_execute_rq_nowait(abort_req, false);
 	/*
 	req->end_io_data = nvmeq;
 	init_completion(&nvmeq->delete_done);
-	req->rq_flags |= RQF_QUIET;
 	blk_execute_rq_nowait(req, false);
 	return 0;
 }

drivers/nvme/target/configfs.c+6−2

 		const char *page, size_t count)
 {
 	int pos = 0, len;
+	char *val;
 	if (subsys->subsys_discovered) {
 		pr_err("Can't set model number. %s is already assigned\n",
 			return -EINVAL;
 	}
-	subsys->model_number = kmemdup_nul(page, len, GFP_KERNEL);
+	val = kmemdup_nul(page, len, GFP_KERNEL);
-	if (!subsys->model_number)
+	if (!val)
 		return -ENOMEM;
+	kfree(subsys->model_number);
+	subsys->model_number = val;
 	return count;
 }
 #ifdef CONFIG_NVME_TARGET_AUTH
 	kfree(host->dhchap_secret);
+	kfree(host->dhchap_ctrl_secret);
 #endif
 	kfree(host);
 }

drivers/pci/controller/pci-hyperv.c+16−6

 static u32 hv_compose_msi_req_v1(
 	struct pci_create_interrupt *int_pkt, const struct cpumask *affinity,
-	u32 slot, u8 vector, u8 vector_count)
+	u32 slot, u8 vector, u16 vector_count)
 {
 	int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE;
 	int_pkt->wslot.slot = slot;
 static u32 hv_compose_msi_req_v2(
 	struct pci_create_interrupt2 *int_pkt, const struct cpumask *affinity,
-	u32 slot, u8 vector, u8 vector_count)
+	u32 slot, u8 vector, u16 vector_count)
 {
 	int cpu;
 static u32 hv_compose_msi_req_v3(
 	struct pci_create_interrupt3 *int_pkt, const struct cpumask *affinity,
-	u32 slot, u32 vector, u8 vector_count)
+	u32 slot, u32 vector, u16 vector_count)
 {
 	int cpu;
 	struct compose_comp_ctxt comp;
 	struct tran_int_desc *int_desc;
 	struct msi_desc *msi_desc;
-	u8 vector, vector_count;
+	/*
+	 * vector_count should be u16: see hv_msi_desc, hv_msi_desc2
+	 * and hv_msi_desc3. vector must be u32: see hv_msi_desc3.
+	 */
+	u16 vector_count;
+	u32 vector;
 	struct {
 		struct pci_packet pci_pkt;
 		union {
 		vector_count = 1;
 	}
+	/*
+	 * hv_compose_msi_req_v1 and v2 are for x86 only, meaning 'vector'
+	 * can't exceed u8. Cast 'vector' down to u8 for v1/v2 explicitly
+	 * for better readability.
+	 */
 	memset(&ctxt, 0, sizeof(ctxt));
 	init_completion(&comp.comp_pkt.host_event);
 	ctxt.pci_pkt.completion_func = hv_pci_compose_compl;
 		size = hv_compose_msi_req_v1(&ctxt.int_pkts.v1,
 					dest,
 					hpdev->desc.win_slot.slot,
-					vector,
+					(u8)vector,
 					vector_count);
 		break;
 		size = hv_compose_msi_req_v2(&ctxt.int_pkts.v2,
 					dest,
 					hpdev->desc.win_slot.slot,
-					vector,
+					(u8)vector,
 					vector_count);
 		break;

drivers/phy/qualcomm/phy-qcom-qmp-combo.c+1−1

@@ -2240,7 +2240,7 @@ static void qmp_combo_enable_autonomous_mode(struct qmp_phy *qphy) · 2239 unmodified lines
2240	static void qmp_combo_disable_autonomous_mode(struct qmp_phy *qphy)	2240	static void qmp_combo_disable_autonomous_mode(struct qmp_phy *qphy)
2241	{	2241	{
2242	const struct qmp_phy_cfg *cfg = qphy->cfg;	2242	const struct qmp_phy_cfg *cfg = qphy->cfg;
2243	void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs_usb;	2243	void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
2244	void __iomem *pcs_misc = qphy->pcs_misc;	2244	void __iomem *pcs_misc = qphy->pcs_misc;
2245		2245
2246	/* Disable i/o clamp_n on resume for normal mode */	2246	/* Disable i/o clamp_n on resume for normal mode */

drivers/phy/ralink/phy-mt7621-pci.c+2−1

@@ -280,7 +280,8 @@ static struct phy mt7621_pcie_phy_of_xlate(struct device dev, · 279 unmodified lines
280	}	280	}
281		281
282	static const struct soc_device_attribute mt7621_pci_quirks_match[] = {	282	static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
283	{ .soc_id = "mt7621", .revision = "E2" }	283	{ .soc_id = "mt7621", .revision = "E2" },
		284	{ /* sentinel */ }
284	};	285	};
285		286
286	static const struct regmap_config mt7621_pci_phy_regmap_config = {	287	static const struct regmap_config mt7621_pci_phy_regmap_config = {

drivers/phy/st/phy-stm32-usbphyc.c+2−0

@@ -710,6 +710,8 @@ static int stm32_usbphyc_probe(struct platform_device *pdev) · 709 unmodified lines
710	ret = of_property_read_u32(child, "reg", &index);	710	ret = of_property_read_u32(child, "reg", &index);
711	if (ret \|\| index > usbphyc->nphys) {	711	if (ret \|\| index > usbphyc->nphys) {
712	dev_err(&phy->dev, "invalid reg property: %d\n", ret);	712	dev_err(&phy->dev, "invalid reg property: %d\n", ret);
		713	if (!ret)
		714	ret = -EINVAL;
713	goto put_child;	715	goto put_child;
714	}	716	}
715		717

drivers/phy/sunplus/phy-sunplus-usb2.c+2−2

@@ -256,8 +256,8 @@ static int sp_usb_phy_probe(struct platform_device *pdev) · 255 unmodified lines
256	usbphy->moon4_res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "moon4");	256	usbphy->moon4_res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "moon4");
257	usbphy->moon4_regs = devm_ioremap(&pdev->dev, usbphy->moon4_res_mem->start,	257	usbphy->moon4_regs = devm_ioremap(&pdev->dev, usbphy->moon4_res_mem->start,
258	resource_size(usbphy->moon4_res_mem));	258	resource_size(usbphy->moon4_res_mem));
259	if (IS_ERR(usbphy->moon4_regs))	259	if (!usbphy->moon4_regs)
260	return PTR_ERR(usbphy->moon4_regs);	260	return -ENOMEM;
261		261
262	usbphy->phy_clk = devm_clk_get(&pdev->dev, NULL);	262	usbphy->phy_clk = devm_clk_get(&pdev->dev, NULL);
263	if (IS_ERR(usbphy->phy_clk))	263	if (IS_ERR(usbphy->phy_clk))

drivers/phy/tegra/xusb.c+16−4

 void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
 {
-	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+	struct tegra_xusb_lane *lane;
-	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+	struct tegra_xusb_padctl *padctl;
+	if (!phy)
+		return;
+	lane = phy_get_drvdata(phy);
+	padctl = lane->pad->padctl;
 	if (padctl->soc->ops->utmi_pad_power_on)
 		padctl->soc->ops->utmi_pad_power_on(phy);
 void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
 {
-	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+	struct tegra_xusb_lane *lane;
-	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+	struct tegra_xusb_padctl *padctl;
+	if (!phy)
+		return;
+	lane = phy_get_drvdata(phy);
+	padctl = lane->pad->padctl;
 	if (padctl->soc->ops->utmi_pad_power_down)
 		padctl->soc->ops->utmi_pad_power_down(phy);

drivers/platform/x86/hp-wmi.c+10−2

 	wwan_rfkill = NULL;
 	rfkill2_count = 0;
-	if (hp_wmi_rfkill_setup(device))
+	/*
-		hp_wmi_rfkill2_setup(device);
+	 * In pre-2009 BIOS, command 1Bh return 0x4 to indicate that
+	 * BIOS no longer controls the power for the wireless
+	 * devices. All features supported by this command will no
+	 * longer be supported.
+	 */
+	if (!hp_wmi_bios_2009_later()) {
+		if (hp_wmi_rfkill_setup(device))
+			hp_wmi_rfkill2_setup(device);
+	}
 	err = hp_wmi_hwmon_init();

drivers/platform/x86/ideapad-laptop.c+24−1

@@ -1533,6 +1533,24 @@ static const struct dmi_system_id hw_rfkill_list[] = { · 1532 unmodified lines
1533	{}	1533	{}
1534	};	1534	};
1535		1535
		1536	static const struct dmi_system_id no_touchpad_switch_list[] = {
		1537	{
		1538	.ident = "Lenovo Yoga 3 Pro 1370",
		1539	.matches = {
		1540	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
		1541	DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo YOGA 3"),
		1542	},
		1543	},
		1544	{
		1545	.ident = "ZhaoYang K4e-IML",
		1546	.matches = {
		1547	DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
		1548	DMI_MATCH(DMI_PRODUCT_VERSION, "ZhaoYang K4e-IML"),
		1549	},
		1550	},
		1551	{}
		1552	};
		1553
1536	static void ideapad_check_features(struct ideapad_private *priv)	1554	static void ideapad_check_features(struct ideapad_private *priv)
1537	{	1555	{
1538	acpi_handle handle = priv->adev->handle;	1556	acpi_handle handle = priv->adev->handle;
@@ -1541,7 +1559,12 @@ static void ideapad_check_features(struct ideapad_private *priv) · 2 unmodified lines
1541	priv->features.hw_rfkill_switch = dmi_check_system(hw_rfkill_list);	1559	priv->features.hw_rfkill_switch = dmi_check_system(hw_rfkill_list);
1542		1560
1543	/* Most ideapads with ELAN0634 touchpad don't use EC touchpad switch */	1561	/* Most ideapads with ELAN0634 touchpad don't use EC touchpad switch */
1544	priv->features.touchpad_ctrl_via_ec = !acpi_dev_present("ELAN0634", NULL, -1);	1562	if (acpi_dev_present("ELAN0634", NULL, -1))
		1563	priv->features.touchpad_ctrl_via_ec = 0;
		1564	else if (dmi_check_system(no_touchpad_switch_list))
		1565	priv->features.touchpad_ctrl_via_ec = 0;
		1566	else
		1567	priv->features.touchpad_ctrl_via_ec = 1;
1545		1568
1546	if (!read_ec_data(handle, VPCCMD_R_FAN, &val))	1569	if (!read_ec_data(handle, VPCCMD_R_FAN, &val))
1547	priv->features.fan_mode = true;	1570	priv->features.fan_mode = true;

drivers/platform/x86/intel/hid.c+3−0

 	{"INTC1051", 0},
 	{"INTC1054", 0},
 	{"INTC1070", 0},
+	{"INTC1076", 0},
+	{"INTC1077", 0},
+	{"INTC1078", 0},
 	{"", 0},
 };
 MODULE_DEVICE_TABLE(acpi, intel_hid_ids);

drivers/platform/x86/intel/pmt/class.c+30−1

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	*/	9	*/
10		10
11	#include <linux/kernel.h>	11	#include <linux/kernel.h>
		12	#include <linux/io-64-nonatomic-lo-hi.h>
12	#include <linux/module.h>	13	#include <linux/module.h>
13	#include <linux/mm.h>	14	#include <linux/mm.h>
14	#include <linux/pci.h>	15	#include <linux/pci.h>
@@ -19,6 +20,7 @@ · 4 unmodified lines
19	#define PMT_XA_START 0	20	#define PMT_XA_START 0
20	#define PMT_XA_MAX INT_MAX	21	#define PMT_XA_MAX INT_MAX
21	#define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX)	22	#define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX)
		23	#define GUID_SPR_PUNIT 0x9956f43f
22		24
23	bool intel_pmt_is_early_client_hw(struct device *dev)	25	bool intel_pmt_is_early_client_hw(struct device *dev)
24	{	26	{
@@ -33,6 +35,29 @@ bool intel_pmt_is_early_client_hw(struct device *dev) · 8 unmodified lines
33	}	35	}
34	EXPORT_SYMBOL_GPL(intel_pmt_is_early_client_hw);	36	EXPORT_SYMBOL_GPL(intel_pmt_is_early_client_hw);
35		37
		38	static inline int
		39	pmt_memcpy64_fromio(void to, const u64 __iomem from, size_t count)
		40	{
		41	int i, remain;
		42	u64 *buf = to;
		43
		44	if (!IS_ALIGNED((unsigned long)from, 8))
		45	return -EFAULT;
		46
		47	for (i = 0; i < count/8; i++)
		48	buf[i] = readq(&from[i]);
		49
		50	/* Copy any remaining bytes */
		51	remain = count % 8;
		52	if (remain) {
		53	u64 tmp = readq(&from[i]);
		54
		55	memcpy(&buf[i], &tmp, remain);
		56	}
		57
		58	return count;
		59	}
		60
36	/*	61	/*
37	* sysfs	62	* sysfs
38	*/	63	*/
@@ -54,7 +79,11 @@ intel_pmt_read(struct file filp, struct kobject kobj, · 15 unmodified lines
54	if (count > entry->size - off)	79	if (count > entry->size - off)
55	count = entry->size - off;	80	count = entry->size - off;
56		81
57	memcpy_fromio(buf, entry->base + off, count);	82	if (entry->guid == GUID_SPR_PUNIT)
		83	/* PUNIT on SPR only supports aligned 64-bit read */
		84	count = pmt_memcpy64_fromio(buf, entry->base + off, count);
		85	else
		86	memcpy_fromio(buf, entry->base + off, count);
58		87
59	return count;	88	return count;
60	}	89	}

drivers/platform/x86/p2sb.c+6−9

 #define P2SBC			0xe0
 #define P2SBC_HIDE		BIT(8)
+#define P2SB_DEVFN_DEFAULT	PCI_DEVFN(31, 1)
 static const struct x86_cpu_id p2sb_cpu_ids[] = {
 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,	PCI_DEVFN(13, 0)),
-	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,	PCI_DEVFN(31, 1)),
-	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D,	PCI_DEVFN(31, 1)),
-	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,		PCI_DEVFN(31, 1)),
-	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,		PCI_DEVFN(31, 1)),
-	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,		PCI_DEVFN(31, 1)),
-	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,		PCI_DEVFN(31, 1)),
 	{}
 };
 static int p2sb_get_devfn(unsigned int *devfn)
 {
+	unsigned int fn = P2SB_DEVFN_DEFAULT;
 	const struct x86_cpu_id *id;
 	id = x86_match_cpu(p2sb_cpu_ids);
-	if (!id)
+	if (id)
-		return -ENODEV;
+		fn = (unsigned int)id->driver_data;
-	*devfn = (unsigned int)id->driver_data;
+	*devfn = fn;
 	return 0;
 }

drivers/platform/x86/touchscreen_dmi.c+25−0

@@ -770,6 +770,22 @@ static const struct ts_dmi_data predia_basic_data = { · 769 unmodified lines
770	.properties = predia_basic_props,	770	.properties = predia_basic_props,
771	};	771	};
772		772
		773	static const struct property_entry rca_cambio_w101_v2_props[] = {
		774	PROPERTY_ENTRY_U32("touchscreen-min-x", 4),
		775	PROPERTY_ENTRY_U32("touchscreen-min-y", 20),
		776	PROPERTY_ENTRY_U32("touchscreen-size-x", 1644),
		777	PROPERTY_ENTRY_U32("touchscreen-size-y", 874),
		778	PROPERTY_ENTRY_BOOL("touchscreen-swapped-x-y"),
		779	PROPERTY_ENTRY_STRING("firmware-name", "gsl1680-rca-cambio-w101-v2.fw"),
		780	PROPERTY_ENTRY_U32("silead,max-fingers", 10),
		781	{ }
		782	};
		783
		784	static const struct ts_dmi_data rca_cambio_w101_v2_data = {
		785	.acpi_name = "MSSL1680:00",
		786	.properties = rca_cambio_w101_v2_props,
		787	};
		788
773	static const struct property_entry rwc_nanote_p8_props[] = {	789	static const struct property_entry rwc_nanote_p8_props[] = {
774	PROPERTY_ENTRY_U32("touchscreen-min-y", 46),	790	PROPERTY_ENTRY_U32("touchscreen-min-y", 46),
775	PROPERTY_ENTRY_U32("touchscreen-size-x", 1728),	791	PROPERTY_ENTRY_U32("touchscreen-size-x", 1728),
@@ -1409,6 +1425,15 @@ const struct dmi_system_id touchscreen_dmi_table[] = { · 633 unmodified lines
1409	DMI_EXACT_MATCH(DMI_BOARD_NAME, "0E57"),	1425	DMI_EXACT_MATCH(DMI_BOARD_NAME, "0E57"),
1410	},	1426	},
1411	},	1427	},
		1428	{
		1429	/* RCA Cambio W101 v2 */
		1430	/* https://github.com/onitake/gsl-firmware/discussions/193 */
		1431	.driver_data = (void *)&rca_cambio_w101_v2_data,
		1432	.matches = {
		1433	DMI_MATCH(DMI_SYS_VENDOR, "RCA"),
		1434	DMI_MATCH(DMI_PRODUCT_NAME, "W101SA23T1"),
		1435	},
		1436	},
1412	{	1437	{
1413	/* RWC NANOTE P8 */	1438	/* RWC NANOTE P8 */
1414	.driver_data = (void *)&rwc_nanote_p8_data,	1439	.driver_data = (void *)&rwc_nanote_p8_data,

drivers/s390/crypto/zcrypt_msgtype6.c+15−6

 	};
 	struct {
 		struct type6_hdr hdr;
-		struct CPRBX cprbx;
+		union {
+			struct CPRBX cprbx;
+			DECLARE_FLEX_ARRAY(u8, userdata);
+		};
 	} __packed * msg = ap_msg->msg;
 	int rcblen = CEIL4(xcrb->request_control_blk_length);
 	msg->hdr.fromcardlen2 = xcrb->reply_data_length;
 	/* prepare CPRB */
-	if (z_copy_from_user(userspace, &msg->cprbx, xcrb->request_control_blk_addr,
+	if (z_copy_from_user(userspace, msg->userdata,
+			     xcrb->request_control_blk_addr,
 			     xcrb->request_control_blk_length))
 		return -EFAULT;
 	if (msg->cprbx.cprb_len + sizeof(msg->hdr.function_code) >
 	struct {
 		struct type6_hdr hdr;
-		struct ep11_cprb cprbx;
+		union {
-		unsigned char	pld_tag;	/* fixed value 0x30 */
+			struct {
-		unsigned char	pld_lenfmt;	/* payload length format */
+				struct ep11_cprb cprbx;
+				unsigned char pld_tag;    /* fixed value 0x30 */
+				unsigned char pld_lenfmt; /* length format */
+			} __packed;
+			DECLARE_FLEX_ARRAY(u8, userdata);
+		};
 	} __packed * msg = ap_msg->msg;
 	struct pld_hdr {
 	msg->hdr.fromcardlen1 = xcrb->resp_len;
 	/* Import CPRB data from the ioctl input parameter */
-	if (z_copy_from_user(userspace, &msg->cprbx.cprb_len,
+	if (z_copy_from_user(userspace, msg->userdata,
 			     (char __force __user *)xcrb->req, xcrb->req_len)) {
 		return -EFAULT;
 	}

drivers/scsi/ibmvscsi/ibmvfc.c+11−3

 		memset(vhost->async_crq.msgs.async, 0, PAGE_SIZE);
 		vhost->async_crq.cur = 0;
-		list_for_each_entry(tgt, &vhost->targets, queue)
+		list_for_each_entry(tgt, &vhost->targets, queue) {
-			ibmvfc_del_tgt(tgt);
+			if (vhost->client_migrated)
+				tgt->need_login = 1;
+			else
+				ibmvfc_del_tgt(tgt);
+		}
 		scsi_block_requests(vhost->host);
 		ibmvfc_set_host_action(vhost, IBMVFC_HOST_ACTION_INIT);
 		vhost->job_step = ibmvfc_npiv_login;
 			/* We need to re-setup the interpartition connection */
 			dev_info(vhost->dev, "Partition migrated, Re-enabling adapter\n");
 			vhost->client_migrated = 1;
+			scsi_block_requests(vhost->host);
 			ibmvfc_purge_requests(vhost, DID_REQUEUE);
-			ibmvfc_link_down(vhost, IBMVFC_LINK_DOWN);
+			ibmvfc_set_host_state(vhost, IBMVFC_LINK_DOWN);
 			ibmvfc_set_host_action(vhost, IBMVFC_HOST_ACTION_REENABLE);
+			wake_up(&vhost->work_wait_q);
 		} else if (crq->format == IBMVFC_PARTNER_FAILED || crq->format == IBMVFC_PARTNER_DEREGISTER) {
 			dev_err(vhost->dev, "Host partner adapter deregistered or failed (rc=%d)\n", crq->format);
 			ibmvfc_purge_requests(vhost, DID_ERROR);

drivers/scsi/scsi_debug.c+7−0

@@ -1899,6 +1899,13 @@ static int resp_readcap16(struct scsi_cmnd *scp, · 1898 unmodified lines
1899	arr[14] \|= 0x40;	1899	arr[14] \|= 0x40;
1900	}	1900	}
1901		1901
		1902	/*
		1903	* Since the scsi_debug READ CAPACITY implementation always reports the
		1904	* total disk capacity, set RC BASIS = 1 for host-managed ZBC devices.
		1905	*/
		1906	if (devip->zmodel == BLK_ZONED_HM)
		1907	arr[12] \|= 1 << 4;
		1908
1902	arr[15] = sdebug_lowest_aligned & 0xff;	1909	arr[15] = sdebug_lowest_aligned & 0xff;
1903		1910
1904	if (have_dif_prot) {	1911	if (have_dif_prot) {

drivers/scsi/scsi_transport_sas.c+9−4

@@ -722,12 +722,17 @@ int sas_phy_add(struct sas_phy *phy) · 721 unmodified lines
722	int error;	722	int error;
723		723
724	error = device_add(&phy->dev);	724	error = device_add(&phy->dev);
725	if (!error) {	725	if (error)
726	transport_add_device(&phy->dev);	726	return error;
727	transport_configure_device(&phy->dev);	727
		728	error = transport_add_device(&phy->dev);
		729	if (error) {
		730	device_del(&phy->dev);
		731	return error;
728	}	732	}
		733	transport_configure_device(&phy->dev);
729		734
730	return error;	735	return 0;
731	}	736	}
732	EXPORT_SYMBOL(sas_phy_add);	737	EXPORT_SYMBOL(sas_phy_add);
733		738

drivers/soundwire/intel.c+1−0

@@ -1513,6 +1513,7 @@ static int intel_link_probe(struct auxiliary_device *auxdev, · 1512 unmodified lines
1513		1513
1514	bus->link_id = auxdev->id;	1514	bus->link_id = auxdev->id;
1515	bus->dev_num_ida_min = INTEL_DEV_NUM_IDA_MIN;	1515	bus->dev_num_ida_min = INTEL_DEV_NUM_IDA_MIN;
		1516	bus->clk_stop_timeout = 1;
1516		1517
1517	sdw_cdns_probe(cdns);	1518	sdw_cdns_probe(cdns);
1518		1519

drivers/soundwire/qcom.c+9−0

 	if (swrm_wait_for_wr_fifo_avail(swrm))
 		return SDW_CMD_FAIL_OTHER;
+	if (cmd_id == SWR_BROADCAST_CMD_ID)
+		reinit_completion(&swrm->broadcast);
 	/* Its assumed that write is okay as we do not get any status back */
 	swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
 	val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
+	/*
+	 * Check for outstanding cmd wrt. write fifo depth to avoid
+	 * overflow as read will also increase write fifo cnt.
+	 */
+	swrm_wait_for_wr_fifo_avail(swrm);
 	/* wait for FIFO RD to complete to avoid overflow */
 	usleep_range(100, 105);
 	swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);

drivers/spi/spi-amd.c+1−1

@@ -65,7 +65,7 @@ enum amd_spi_speed { · 64 unmodified lines
65	F_16_66MHz,	65	F_16_66MHz,
66	F_100MHz,	66	F_100MHz,
67	F_800KHz,	67	F_800KHz,
68	SPI_SPD7,	68	SPI_SPD7 = 0x7,
69	F_50MHz = 0x4,	69	F_50MHz = 0x4,
70	F_4MHz = 0x32,	70	F_4MHz = 0x32,
71	F_3_17MHz = 0x3F	71	F_3_17MHz = 0x3F

drivers/spi/spi-intel.c+4−4

@@ -52,17 +52,17 @@ · 51 unmodified lines
52	#define FRACC 0x50	52	#define FRACC 0x50
53		53
54	#define FREG(n) (0x54 + ((n) * 4))	54	#define FREG(n) (0x54 + ((n) * 4))
55	#define FREG_BASE_MASK 0x3fff	55	#define FREG_BASE_MASK GENMASK(14, 0)
56	#define FREG_LIMIT_SHIFT 16	56	#define FREG_LIMIT_SHIFT 16
57	#define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)	57	#define FREG_LIMIT_MASK GENMASK(30, 16)
58		58
59	/* Offset is from @ispi->pregs */	59	/* Offset is from @ispi->pregs */
60	#define PR(n) ((n) * 4)	60	#define PR(n) ((n) * 4)
61	#define PR_WPE BIT(31)	61	#define PR_WPE BIT(31)
62	#define PR_LIMIT_SHIFT 16	62	#define PR_LIMIT_SHIFT 16
63	#define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)	63	#define PR_LIMIT_MASK GENMASK(30, 16)
64	#define PR_RPE BIT(15)	64	#define PR_RPE BIT(15)
65	#define PR_BASE_MASK 0x3fff	65	#define PR_BASE_MASK GENMASK(14, 0)
66		66
67	/* Offsets are from @ispi->sregs */	67	/* Offsets are from @ispi->sregs */
68	#define SSFSTS_CTL 0x00	68	#define SSFSTS_CTL 0x00

drivers/spi/spi-meson-spicc.c+22−2

 	struct clk			*clk;
 	struct spi_message		*message;
 	struct spi_transfer		*xfer;
+	struct completion		done;
 	const struct meson_spicc_data	*data;
 	u8				*tx_buf;
 	u8				*rx_buf;
 		/* Disable all IRQs */
 		writel(0, spicc->base + SPICC_INTREG);
-		spi_finalize_current_transfer(spicc->master);
+		complete(&spicc->done);
 		return IRQ_HANDLED;
 	}
 				    struct spi_transfer *xfer)
 {
 	struct meson_spicc_device *spicc = spi_master_get_devdata(master);
+	uint64_t timeout;
 	/* Store current transfer */
 	spicc->xfer = xfer;
 	/* Setup burst */
 	meson_spicc_setup_burst(spicc);
+	/* Setup wait for completion */
+	reinit_completion(&spicc->done);
+	/* For each byte we wait for 8 cycles of the SPI clock */
+	timeout = 8LL * MSEC_PER_SEC * xfer->len;
+	do_div(timeout, xfer->speed_hz);
+	/* Add 10us delay between each fifo bursts */
+	timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC;
+	/* Increase it twice and add 200 ms tolerance */
+	timeout += timeout + 200;
 	/* Start burst */
 	writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
 	/* Enable interrupts */
 	writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
-	return 1;
+	if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout)))
+		return -ETIMEDOUT;
+	return 0;
 }
 static int meson_spicc_prepare_message(struct spi_master *master,
 	spicc->pdev = pdev;
 	platform_set_drvdata(pdev, spicc);
+	init_completion(&spicc->done);
 	spicc->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(spicc->base)) {
 		dev_err(&pdev->dev, "io resource mapping failed\n");

drivers/spi/spi-mt65xx.c+13−10

 	writel(cmd, mdata->base + SPI_CMD_REG);
 }
-static int mtk_spi_get_mult_delta(u32 xfer_len)
+static int mtk_spi_get_mult_delta(struct mtk_spi *mdata, u32 xfer_len)
 {
-	u32 mult_delta;
+	u32 mult_delta = 0;
-	if (xfer_len > MTK_SPI_PACKET_SIZE)
+	if (mdata->dev_comp->ipm_design) {
-		mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
+		if (xfer_len > MTK_SPI_IPM_PACKET_SIZE)
-	else
+			mult_delta = xfer_len % MTK_SPI_IPM_PACKET_SIZE;
-		mult_delta = 0;
+	} else {
+		if (xfer_len > MTK_SPI_PACKET_SIZE)
+			mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
+	}
 	return mult_delta;
 }
 	if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
 		if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
-			mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
+			mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len);
 			mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
 			mdata->rx_sgl_len = mult_delta;
 			mdata->tx_sgl_len -= mdata->xfer_len;
 		} else {
-			mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
+			mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len);
 			mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
 			mdata->tx_sgl_len = mult_delta;
 			mdata->rx_sgl_len -= mdata->xfer_len;
 		}
 	} else if (mdata->tx_sgl_len) {
-		mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
+		mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len);
 		mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
 		mdata->tx_sgl_len = mult_delta;
 	} else if (mdata->rx_sgl_len) {
-		mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
+		mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len);
 		mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
 		mdata->rx_sgl_len = mult_delta;
 	}

drivers/spi/spi-stm32.c+2−1

 	u32 div, mbrdiv;
 	/* Ensure spi->clk_rate is even */
-	div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
+	div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
 	/*
 	 * SPI framework set xfer->speed_hz to master->max_speed_hz if
 		static DEFINE_RATELIMIT_STATE(rs,
 					      DEFAULT_RATELIMIT_INTERVAL * 10,
 					      1);
+		ratelimit_set_flags(&rs, RATELIMIT_MSG_ON_RELEASE);
 		if (__ratelimit(&rs))
 			dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
 		if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))

drivers/spi/spi-tegra210-quad.c+6−0

 static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi)
 {
+	if (!tqspi->soc_data->has_dma)
+		return;
 	if (tqspi->tx_dma_buf) {
 		dma_free_coherent(tqspi->dev, tqspi->dma_buf_size,
 				  tqspi->tx_dma_buf, tqspi->tx_dma_phys);
 	u32 *dma_buf;
 	int err;
+	if (!tqspi->soc_data->has_dma)
+		return 0;
 	dma_chan = dma_request_chan(tqspi->dev, "rx");
 	if (IS_ERR(dma_chan)) {
 		err = PTR_ERR(dma_chan);

fs/btrfs/compression.c+8−6

 static noinline int add_ra_bio_pages(struct inode *inode,
 				     u64 compressed_end,
 				     struct compressed_bio *cb,
-				     unsigned long *pflags)
+				     int *memstall, unsigned long *pflags)
 {
 	struct btrfs_fs_info *fs_info = btrfs_sb(inode->i_sb);
 	unsigned long end_index;
 			continue;
 		}
-		if (PageWorkingset(page))
+		if (!*memstall && PageWorkingset(page)) {
 			psi_memstall_enter(pflags);
+			*memstall = 1;
+		}
 		ret = set_page_extent_mapped(page);
 		if (ret < 0) {
 	u64 em_len;
 	u64 em_start;
 	struct extent_map *em;
-	/* Initialize to 1 to make skip psi_memstall_leave unless needed */
+	unsigned long pflags;
-	unsigned long pflags = 1;
+	int memstall = 0;
 	blk_status_t ret;
 	int ret2;
 	int i;
 		goto fail;
 	}
-	add_ra_bio_pages(inode, em_start + em_len, cb, &pflags);
+	add_ra_bio_pages(inode, em_start + em_len, cb, &memstall, &pflags);
 	/* include any pages we added in add_ra-bio_pages */
 	cb->len = bio->bi_iter.bi_size;
 		}
 	}
-	if (!pflags)
+	if (memstall)
 		psi_memstall_leave(&pflags);
 	if (refcount_dec_and_test(&cb->pending_ios))

fs/btrfs/ctree.c+16−0

@@ -113,6 +113,22 @@ noinline void btrfs_release_path(struct btrfs_path *p) · 112 unmodified lines
113	}	113	}
114	}	114	}
115		115
		116	/*
		117	* We want the transaction abort to print stack trace only for errors where the
		118	* cause could be a bug, eg. due to ENOSPC, and not for common errors that are
		119	* caused by external factors.
		120	*/
		121	bool __cold abort_should_print_stack(int errno)
		122	{
		123	switch (errno) {
		124	case -EIO:
		125	case -EROFS:
		126	case -ENOMEM:
		127	return false;
		128	}
		129	return true;
		130	}
		131
116	/*	132	/*
117	* safely gets a reference on the root node of a tree. A lock	133	* safely gets a reference on the root node of a tree. A lock
118	* is not taken, so a concurrent writer may put a different node	134	* is not taken, so a concurrent writer may put a different node

fs/btrfs/ctree.h+7−4

 			       const char *function,
 			       unsigned int line, int errno, bool first_hit);
+bool __cold abort_should_print_stack(int errno);
 /*
  * Call btrfs_abort_transaction as early as possible when an error condition is
- * detected, that way the exact line number is reported.
+ * detected, that way the exact stack trace is reported for some errors.
  */
 #define btrfs_abort_transaction(trans, errno)		\
 do {								\
 	if (!test_and_set_bit(BTRFS_FS_STATE_TRANS_ABORTED,	\
 			&((trans)->fs_info->fs_state))) {	\
 		first = true;					\
-		if ((errno) != -EIO && (errno) != -EROFS) {		\
+		if (WARN(abort_should_print_stack(errno), 	\
-			WARN(1, KERN_DEBUG				\
+			KERN_DEBUG				\
 			"BTRFS: Transaction aborted (error %d)\n",	\
-			(errno));					\
+			(errno))) {					\
+			/* Stack trace printed. */			\
 		} else {						\
 			btrfs_debug((trans)->fs_info,			\
 				    "Transaction aborted (error %d)", \

fs/btrfs/disk-io.c+3−1

 		fs_info->dev_root = root;
 	}
 	/* Initialize fs_info for all devices in any case */
-	btrfs_init_devices_late(fs_info);
+	ret = btrfs_init_devices_late(fs_info);
+	if (ret)
+		goto out;
 	/*
 	 * This tree can share blocks with some other fs tree during relocation

fs/btrfs/scrub.c+1−8

 	u8 csum[BTRFS_CSUM_SIZE];
 	u32 blocksize;
-	/*
-	 * Block size determines how many scrub_block will be allocated.  Here
-	 * we use BTRFS_STRIPE_LEN (64KiB) as default limit, so we won't
-	 * allocate too many scrub_block, while still won't cause too large
-	 * bios for large extents.
-	 */
 	if (flags & BTRFS_EXTENT_FLAG_DATA) {
 		if (map->type & BTRFS_BLOCK_GROUP_RAID56_MASK)
 			blocksize = map->stripe_len;
 		else
-			blocksize = BTRFS_STRIPE_LEN;
+			blocksize = sctx->fs_info->sectorsize;
 		spin_lock(&sctx->stat_lock);
 		sctx->stat.data_extents_scrubbed++;
 		sctx->stat.data_bytes_scrubbed += len;
 		if (sctx->is_dev_replace && btrfs_is_zoned(fs_info)) {
 			if (!test_bit(BLOCK_GROUP_FLAG_TO_COPY, &cache->runtime_flags)) {
-				spin_unlock(&cache->lock);
 				btrfs_put_block_group(cache);
 				goto skip;
 			}

fs/btrfs/tests/btrfs-tests.c+1−1

@@ -200,7 +200,7 @@ void btrfs_free_dummy_fs_info(struct btrfs_fs_info *fs_info) · 199 unmodified lines
200		200
201	void btrfs_free_dummy_root(struct btrfs_root *root)	201	void btrfs_free_dummy_root(struct btrfs_root *root)
202	{	202	{
203	if (!root)	203	if (IS_ERR_OR_NULL(root))
204	return;	204	return;
205	/* Will be freed by btrfs_free_fs_roots */	205	/* Will be freed by btrfs_free_fs_roots */
206	if (WARN_ON(test_bit(BTRFS_ROOT_IN_RADIX, &root->state)))	206	if (WARN_ON(test_bit(BTRFS_ROOT_IN_RADIX, &root->state)))

fs/btrfs/volumes.c+29−10

 			rcu_assign_pointer(device->name, name);
 		}
+		if (orig_dev->zone_info) {
+			struct btrfs_zoned_device_info *zone_info;
+			zone_info = btrfs_clone_dev_zone_info(orig_dev);
+			if (!zone_info) {
+				btrfs_free_device(device);
+				ret = -ENOMEM;
+				goto error;
+			}
+			device->zone_info = zone_info;
+		}
 		list_add(&device->dev_list, &fs_devices->devices);
 		device->fs_devices = fs_devices;
 		fs_devices->num_devices++;
 static bool dev_args_match_device(const struct btrfs_dev_lookup_args *args,
 				  const struct btrfs_device *device)
 {
-	ASSERT((args->devid != (u64)-1) || args->missing);
+	if (args->missing) {
+		if (test_bit(BTRFS_DEV_STATE_IN_FS_METADATA, &device->dev_state) &&
+		    !device->bdev)
+			return true;
+		return false;
+	}
-	if ((args->devid != (u64)-1) && device->devid != args->devid)
+	if (device->devid != args->devid)
 		return false;
 	if (args->uuid && memcmp(device->uuid, args->uuid, BTRFS_UUID_SIZE) != 0)
 		return false;
-	if (!args->missing)
+	return true;
-		return true;
-	if (test_bit(BTRFS_DEV_STATE_IN_FS_METADATA, &device->dev_state) &&
-	    !device->bdev)
-		return true;
-	return false;
 }
 /*
 	return ret;
 }
-void btrfs_init_devices_late(struct btrfs_fs_info *fs_info)
+int btrfs_init_devices_late(struct btrfs_fs_info *fs_info)
 {
 	struct btrfs_fs_devices *fs_devices = fs_info->fs_devices, *seed_devs;
 	struct btrfs_device *device;
+	int ret = 0;
 	fs_devices->fs_info = fs_info;
 		device->fs_info = fs_info;
 	list_for_each_entry(seed_devs, &fs_devices->seed_list, seed_list) {
-		list_for_each_entry(device, &seed_devs->devices, dev_list)
+		list_for_each_entry(device, &seed_devs->devices, dev_list) {
 			device->fs_info = fs_info;
+			ret = btrfs_get_dev_zone_info(device, false);
+			if (ret)
+				break;
+		}
 		seed_devs->fs_info = fs_info;
 	}
 	mutex_unlock(&fs_devices->device_list_mutex);
+	return ret;
 }
 static u64 btrfs_dev_stats_value(const struct extent_buffer *eb,

fs/btrfs/volumes.h+1−1

@@ -671,7 +671,7 @@ int find_free_dev_extent(struct btrfs_device *device, u64 num_bytes, · 670 unmodified lines
671	void btrfs_dev_stat_inc_and_print(struct btrfs_device *dev, int index);	671	void btrfs_dev_stat_inc_and_print(struct btrfs_device *dev, int index);
672	int btrfs_get_dev_stats(struct btrfs_fs_info *fs_info,	672	int btrfs_get_dev_stats(struct btrfs_fs_info *fs_info,
673	struct btrfs_ioctl_get_dev_stats *stats);	673	struct btrfs_ioctl_get_dev_stats *stats);
674	void btrfs_init_devices_late(struct btrfs_fs_info *fs_info);	674	int btrfs_init_devices_late(struct btrfs_fs_info *fs_info);
675	int btrfs_init_dev_stats(struct btrfs_fs_info *fs_info);	675	int btrfs_init_dev_stats(struct btrfs_fs_info *fs_info);
676	int btrfs_run_dev_stats(struct btrfs_trans_handle *trans);	676	int btrfs_run_dev_stats(struct btrfs_trans_handle *trans);
677	void btrfs_rm_dev_replace_remove_srcdev(struct btrfs_device *srcdev);	677	void btrfs_rm_dev_replace_remove_srcdev(struct btrfs_device *srcdev);

fs/btrfs/zoned.c+40−0

@@ -639,6 +639,46 @@ void btrfs_destroy_dev_zone_info(struct btrfs_device *device) · 638 unmodified lines
639	device->zone_info = NULL;	639	device->zone_info = NULL;
640	}	640	}
641		641
		642	struct btrfs_zoned_device_info btrfs_clone_dev_zone_info(struct btrfs_device orig_dev)
		643	{
		644	struct btrfs_zoned_device_info *zone_info;
		645
		646	zone_info = kmemdup(orig_dev->zone_info, sizeof(*zone_info), GFP_KERNEL);
		647	if (!zone_info)
		648	return NULL;
		649
		650	zone_info->seq_zones = bitmap_zalloc(zone_info->nr_zones, GFP_KERNEL);
		651	if (!zone_info->seq_zones)
		652	goto out;
		653
		654	bitmap_copy(zone_info->seq_zones, orig_dev->zone_info->seq_zones,
		655	zone_info->nr_zones);
		656
		657	zone_info->empty_zones = bitmap_zalloc(zone_info->nr_zones, GFP_KERNEL);
		658	if (!zone_info->empty_zones)
		659	goto out;
		660
		661	bitmap_copy(zone_info->empty_zones, orig_dev->zone_info->empty_zones,
		662	zone_info->nr_zones);
		663
		664	zone_info->active_zones = bitmap_zalloc(zone_info->nr_zones, GFP_KERNEL);
		665	if (!zone_info->active_zones)
		666	goto out;
		667
		668	bitmap_copy(zone_info->active_zones, orig_dev->zone_info->active_zones,
		669	zone_info->nr_zones);
		670	zone_info->zone_cache = NULL;
		671
		672	return zone_info;
		673
		674	out:
		675	bitmap_free(zone_info->seq_zones);
		676	bitmap_free(zone_info->empty_zones);
		677	bitmap_free(zone_info->active_zones);
		678	kfree(zone_info);
		679	return NULL;
		680	}
		681
642	int btrfs_get_dev_zone(struct btrfs_device *device, u64 pos,	682	int btrfs_get_dev_zone(struct btrfs_device *device, u64 pos,
643	struct blk_zone *zone)	683	struct blk_zone *zone)
644	{	684	{

fs/btrfs/zoned.h+11−0

 int btrfs_get_dev_zone_info_all_devices(struct btrfs_fs_info *fs_info);
 int btrfs_get_dev_zone_info(struct btrfs_device *device, bool populate_cache);
 void btrfs_destroy_dev_zone_info(struct btrfs_device *device);
+struct btrfs_zoned_device_info *btrfs_clone_dev_zone_info(struct btrfs_device *orig_dev);
 int btrfs_check_zoned_mode(struct btrfs_fs_info *fs_info);
 int btrfs_check_mountopts_zoned(struct btrfs_fs_info *info);
 int btrfs_sb_log_location_bdev(struct block_device *bdev, int mirror, int rw,
 static inline void btrfs_destroy_dev_zone_info(struct btrfs_device *device) { }
+/*
+ * In case the kernel is compiled without CONFIG_BLK_DEV_ZONED we'll never call
+ * into btrfs_clone_dev_zone_info() so it's safe to return NULL here.
+ */
+static inline struct btrfs_zoned_device_info *btrfs_clone_dev_zone_info(
+						 struct btrfs_device *orig_dev)
+{
+	return NULL;
+}
 static inline int btrfs_check_zoned_mode(const struct btrfs_fs_info *fs_info)
 {
 	if (!btrfs_is_zoned(fs_info))

fs/erofs/zdata.c+11−7

 	struct block_device *last_bdev;
 	unsigned int nr_bios = 0;
 	struct bio *bio = NULL;
-	/* initialize to 1 to make skip psi_memstall_leave unless needed */
+	unsigned long pflags;
-	unsigned long pflags = 1;
+	int memstall = 0;
 	bi_private = jobqueueset_init(sb, q, fgq, force_fg);
 	qtail[JQ_BYPASS] = &q[JQ_BYPASS]->head;
 			if (bio && (cur != last_index + 1 ||
 				    last_bdev != mdev.m_bdev)) {
 submit_bio_retry:
-				if (!pflags)
-					psi_memstall_leave(&pflags);
 				submit_bio(bio);
+				if (memstall) {
+					psi_memstall_leave(&pflags);
+					memstall = 0;
+				}
 				bio = NULL;
 			}
-			if (unlikely(PageWorkingset(page)))
+			if (unlikely(PageWorkingset(page)) && !memstall) {
 				psi_memstall_enter(&pflags);
+				memstall = 1;
+			}
 			if (!bio) {
 				bio = bio_alloc(mdev.m_bdev, BIO_MAX_VECS,
 	} while (owned_head != Z_EROFS_PCLUSTER_TAIL);
 	if (bio) {
-		if (!pflags)
-			psi_memstall_leave(&pflags);
 		submit_bio(bio);
+		if (memstall)
+			psi_memstall_leave(&pflags);
 	}
 	/*

fs/hugetlbfs/inode.c+6−7

 		} else {
 			unlock_page(page);
+			if (PageHWPoison(page)) {
+				put_page(page);
+				retval = -EIO;
+				break;
+			}
 			/*
 			 * We have the page, copy it to user space buffer.
 			 */
 static int hugetlbfs_error_remove_page(struct address_space *mapping,
 				struct page *page)
 {
-	struct inode *inode = mapping->host;
-	pgoff_t index = page->index;
-	hugetlb_delete_from_page_cache(page);
-	if (unlikely(hugetlb_unreserve_pages(inode, index, index + 1, 1)))
-		hugetlb_fix_reserve_counts(inode);
 	return 0;
 }

fs/nfsd/filecache.c+1−0

@@ -1076,6 +1076,7 @@ retry: · 1075 unmodified lines
1076	goto open_file;	1076	goto open_file;
1077		1077
1078	nfsd_file_slab_free(&nf->nf_rcu);	1078	nfsd_file_slab_free(&nf->nf_rcu);
		1079	nf = NULL;
1079	if (ret == -EEXIST)	1080	if (ret == -EEXIST)
1080	goto retry;	1081	goto retry;
1081	trace_nfsd_file_insert_err(rqstp, key.inode, may_flags, ret);	1082	trace_nfsd_file_insert_err(rqstp, key.inode, may_flags, ret);

fs/nfsd/nfs4state.c+1−0

@@ -5382,6 +5382,7 @@ nfsd4_verify_deleg_dentry(struct nfsd4_open open, struct nfs4_file fp, · 5381 unmodified lines
5382	if (err)	5382	if (err)
5383	return -EAGAIN;	5383	return -EAGAIN;
5384		5384
		5385	exp_put(exp);
5385	dput(child);	5386	dput(child);
5386	if (child != file_dentry(fp->fi_deleg_file->nf_file))	5387	if (child != file_dentry(fp->fi_deleg_file->nf_file))
5387	return -EAGAIN;	5388	return -EAGAIN;

fs/nilfs2/segment.c+8−7

 	struct the_nilfs *nilfs = sb->s_fs_info;
 	struct nilfs_sc_info *sci = nilfs->ns_writer;
-	if (!sci || !sci->sc_flush_request)
+	if (sb_rdonly(sb) || unlikely(!sci) || !sci->sc_flush_request)
 		return;
 	set_bit(NILFS_SC_PRIOR_FLUSH, &sci->sc_flags);
 	struct nilfs_sc_info *sci = nilfs->ns_writer;
 	struct nilfs_transaction_info *ti;
-	if (!sci)
+	if (sb_rdonly(sb) || unlikely(!sci))
 		return -EROFS;
 	/* A call inside transactions causes a deadlock. */
 	struct nilfs_transaction_info ti;
 	int err = 0;
-	if (!sci)
+	if (sb_rdonly(sb) || unlikely(!sci))
 		return -EROFS;
 	nilfs_transaction_lock(sb, &ti, 0);
 	if (nilfs->ns_writer) {
 		/*
-		 * This happens if the filesystem was remounted
+		 * This happens if the filesystem is made read-only by
-		 * read/write after nilfs_error degenerated it into a
+		 * __nilfs_error or nilfs_remount and then remounted
-		 * read-only mount.
+		 * read/write.  In these cases, reuse the existing
+		 * writer.
 		 */
-		nilfs_detach_log_writer(sb);
+		return 0;
 	}
 	nilfs->ns_writer = nilfs_segctor_new(sb, root);

fs/nilfs2/super.c+0−2

@@ -1133,8 +1133,6 @@ static int nilfs_remount(struct super_block sb, int flags, char *data) · 1132 unmodified lines
1133	if ((bool)(*flags & SB_RDONLY) == sb_rdonly(sb))	1133	if ((bool)(*flags & SB_RDONLY) == sb_rdonly(sb))
1134	goto out;	1134	goto out;
1135	if (*flags & SB_RDONLY) {	1135	if (*flags & SB_RDONLY) {
1136	/* Shutting down log writer */
1137	nilfs_detach_log_writer(sb);
1138	sb->s_flags \|= SB_RDONLY;	1136	sb->s_flags \|= SB_RDONLY;
1139		1137
1140	/*	1138	/*

fs/nilfs2/the_nilfs.c+0−2

 {
 	unsigned long ncleansegs;
-	down_read(&NILFS_MDT(nilfs->ns_dat)->mi_sem);
 	ncleansegs = nilfs_sufile_get_ncleansegs(nilfs->ns_sufile);
-	up_read(&NILFS_MDT(nilfs->ns_dat)->mi_sem);
 	*nblocks = (sector_t)ncleansegs * nilfs->ns_blocks_per_segment;
 	return 0;
 }

fs/udf/namei.c+1−1

@@ -240,7 +240,7 @@ static struct fileIdentDesc udf_find_entry(struct inode dir, · 239 unmodified lines
240	poffset - lfi);	240	poffset - lfi);
241	else {	241	else {
242	if (!copy_name) {	242	if (!copy_name) {
243	copy_name = kmalloc(UDF_NAME_LEN,	243	copy_name = kmalloc(UDF_NAME_LEN_CS0,
244	GFP_NOFS);	244	GFP_NOFS);
245	if (!copy_name) {	245	if (!copy_name) {
246	fi = ERR_PTR(-ENOMEM);	246	fi = ERR_PTR(-ENOMEM);

fs/userfaultfd.c+3−0

 				 NULL_VM_UFFD_CTX, anon_vma_name(vma));
 		if (prev) {
 			vma = prev;
+			mas_pause(&mas);
 			goto next;
 		}
 		if (vma->vm_start < start) {
 			ret = split_vma(mm, vma, start, 1);
 			if (ret)
 				break;
+			mas_pause(&mas);
 		}
 		if (vma->vm_end > end) {
 			ret = split_vma(mm, vma, end, 0);
 			if (ret)
 				break;
+			mas_pause(&mas);
 		}
 	next:
 		/*

include/asm-generic/hyperv-tlfs.h+9−0

@@ -102,6 +102,15 @@ struct ms_hyperv_tsc_page { · 101 unmodified lines
102	volatile s64 tsc_offset;	102	volatile s64 tsc_offset;
103	} __packed;	103	} __packed;
104		104
		105	union hv_reference_tsc_msr {
		106	u64 as_uint64;
		107	struct {
		108	u64 enable:1;
		109	u64 reserved:11;
		110	u64 pfn:52;
		111	} __packed;
		112	};
		113
105	/*	114	/*
106	* The guest OS needs to register the guest ID with the hypervisor.	115	* The guest OS needs to register the guest ID with the hypervisor.
107	* The guest ID is a 64 bit entity and the structure of this ID is	116	* The guest ID is a 64 bit entity and the structure of this ID is

include/asm-generic/vmlinux.lds.h+1−1

 #define DATA_DATA							\
 	*(.xiptext)							\
 	*(DATA_MAIN)							\
+	*(.data..decrypted)						\
 	*(.ref.data)							\
 	*(.data..shared_aligned) /* percpu related */			\
 	MEM_KEEP(init.data*)						\
 #ifdef CONFIG_AMD_MEM_ENCRYPT
 #define PERCPU_DECRYPTED_SECTION					\
 	. = ALIGN(PAGE_SIZE);						\
-	*(.data..decrypted)						\
 	*(.data..percpu..decrypted)					\
 	. = ALIGN(PAGE_SIZE);
 #else

include/linux/can/dev.h+16−0

@@ -152,6 +152,22 @@ static inline bool can_is_canxl_dev_mtu(unsigned int mtu) · 151 unmodified lines
152	return (mtu >= CANXL_MIN_MTU && mtu <= CANXL_MAX_MTU);	152	return (mtu >= CANXL_MIN_MTU && mtu <= CANXL_MAX_MTU);
153	}	153	}
154		154
		155	/* drop skb if it does not contain a valid CAN frame for sending */
		156	static inline bool can_dev_dropped_skb(struct net_device dev, struct sk_buff skb)
		157	{
		158	struct can_priv *priv = netdev_priv(dev);
		159
		160	if (priv->ctrlmode & CAN_CTRLMODE_LISTENONLY) {
		161	netdev_info_once(dev,
		162	"interface in listen only mode, dropping skb\n");
		163	kfree_skb(skb);
		164	dev->stats.tx_dropped++;
		165	return true;
		166	}
		167
		168	return can_dropped_invalid_skb(dev, skb);
		169	}
		170
155	void can_setup(struct net_device *dev);	171	void can_setup(struct net_device *dev);
156		172
157	struct net_device *alloc_candev_mqs(int sizeof_priv, unsigned int echo_skb_max,	173	struct net_device *alloc_candev_mqs(int sizeof_priv, unsigned int echo_skb_max,

include/linux/efi.h+1−0

@@ -389,6 +389,7 @@ void efi_native_runtime_setup(void); · 388 unmodified lines
389	#define EFI_LOAD_FILE2_PROTOCOL_GUID EFI_GUID(0x4006c0c1, 0xfcb3, 0x403e, 0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d)	389	#define EFI_LOAD_FILE2_PROTOCOL_GUID EFI_GUID(0x4006c0c1, 0xfcb3, 0x403e, 0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d)
390	#define EFI_RT_PROPERTIES_TABLE_GUID EFI_GUID(0xeb66918a, 0x7eef, 0x402a, 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9)	390	#define EFI_RT_PROPERTIES_TABLE_GUID EFI_GUID(0xeb66918a, 0x7eef, 0x402a, 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9)
391	#define EFI_DXE_SERVICES_TABLE_GUID EFI_GUID(0x05ad34ba, 0x6f02, 0x4214, 0x95, 0x2e, 0x4d, 0xa0, 0x39, 0x8e, 0x2b, 0xb9)	391	#define EFI_DXE_SERVICES_TABLE_GUID EFI_GUID(0x05ad34ba, 0x6f02, 0x4214, 0x95, 0x2e, 0x4d, 0xa0, 0x39, 0x8e, 0x2b, 0xb9)
		392	#define EFI_SMBIOS_PROTOCOL_GUID EFI_GUID(0x03583ff6, 0xcb36, 0x4940, 0x94, 0x7e, 0xb9, 0xb3, 0x9f, 0x4a, 0xfa, 0xf7)
392		393
393	#define EFI_IMAGE_SECURITY_DATABASE_GUID EFI_GUID(0xd719b2cb, 0x3d3a, 0x4596, 0xa3, 0xbc, 0xda, 0xd0, 0x0e, 0x67, 0x65, 0x6f)	394	#define EFI_IMAGE_SECURITY_DATABASE_GUID EFI_GUID(0xd719b2cb, 0x3d3a, 0x4596, 0xa3, 0xbc, 0xda, 0xd0, 0x0e, 0x67, 0x65, 0x6f)
394	#define EFI_SHIM_LOCK_GUID EFI_GUID(0x605dab50, 0xe046, 0x4300, 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23)	395	#define EFI_SHIM_LOCK_GUID EFI_GUID(0x605dab50, 0xe046, 0x4300, 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23)

include/linux/maple_tree.h+7−0

 	}
 }
+static inline unsigned int mt_height(const struct maple_tree *mt)
+{
+	return (mt->ma_flags & MT_FLAGS_HEIGHT_MASK) >> MT_FLAGS_HEIGHT_OFFSET;
+}
 void *mt_find(struct maple_tree *mt, unsigned long *index, unsigned long max);
 void *mt_find_after(struct maple_tree *mt, unsigned long *index,
 		    unsigned long max);
 void mt_dump(const struct maple_tree *mt);
 void mt_validate(struct maple_tree *mt);
+void mt_cache_shrink(void);
 #define MT_BUG_ON(__tree, __x) do {					\
 	atomic_inc(&maple_tree_tests_run);				\
 	if (__x) {							\

include/linux/skmsg.h+1−1

@@ -376,7 +376,7 @@ static inline void sk_psock_report_error(struct sk_psock *psock, int err) · 375 unmodified lines
376	}	376	}
377		377
378	struct sk_psock sk_psock_init(struct sock sk, int node);	378	struct sk_psock sk_psock_init(struct sock sk, int node);
379	void sk_psock_stop(struct sk_psock *psock, bool wait);	379	void sk_psock_stop(struct sk_psock *psock);
380		380
381	#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER)	381	#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER)
382	int sk_psock_init_strp(struct sock sk, struct sk_psock psock);	382	int sk_psock_init_strp(struct sock sk, struct sk_psock psock);

include/linux/slab.h+0−23

@@ -470,35 +470,12 @@ void *__kmalloc_node(size_t size, gfp_t flags, int node) __assume_kmalloc_alignm · 469 unmodified lines
470	void kmem_cache_alloc_node(struct kmem_cache s, gfp_t flags, int node) __assume_slab_alignment	470	void kmem_cache_alloc_node(struct kmem_cache s, gfp_t flags, int node) __assume_slab_alignment
471	__malloc;	471	__malloc;
472		472
473	#ifdef CONFIG_TRACING
474	void kmalloc_trace(struct kmem_cache s, gfp_t flags, size_t size)	473	void kmalloc_trace(struct kmem_cache s, gfp_t flags, size_t size)
475	__assume_kmalloc_alignment __alloc_size(3);	474	__assume_kmalloc_alignment __alloc_size(3);
476		475
477	void kmalloc_node_trace(struct kmem_cache s, gfp_t gfpflags,	476	void kmalloc_node_trace(struct kmem_cache s, gfp_t gfpflags,
478	int node, size_t size) __assume_kmalloc_alignment	477	int node, size_t size) __assume_kmalloc_alignment
479	__alloc_size(4);	478	__alloc_size(4);
480	#else /* CONFIG_TRACING */
481	/* Save a function call when CONFIG_TRACING=n */
482	static __always_inline __alloc_size(3)
483	void kmalloc_trace(struct kmem_cache s, gfp_t flags, size_t size)
484	{
485	void *ret = kmem_cache_alloc(s, flags);
486
487	ret = kasan_kmalloc(s, ret, size, flags);
488	return ret;
489	}
490
491	static __always_inline __alloc_size(4)
492	void kmalloc_node_trace(struct kmem_cache s, gfp_t gfpflags,
493	int node, size_t size)
494	{
495	void *ret = kmem_cache_alloc_node(s, gfpflags, node);
496
497	ret = kasan_kmalloc(s, ret, size, gfpflags);
498	return ret;
499	}
500	#endif /* CONFIG_TRACING */
501
502	void *kmalloc_large(size_t size, gfp_t flags) __assume_page_alignment	479	void *kmalloc_large(size_t size, gfp_t flags) __assume_page_alignment
503	__alloc_size(1);	480	__alloc_size(1);
504		481

include/uapi/drm/panfrost_drm.h+1−1

@@ -254,7 +254,7 @@ struct panfrost_dump_object_header { · 253 unmodified lines
254	__u64 nbos;	254	__u64 nbos;
255	} reghdr;	255	} reghdr;
256		256
257	struct pan_bomap_hdr {	257	struct {
258	__u32 valid;	258	__u32 valid;
259	__u64 iova;	259	__u64 iova;
260	__u32 data[2];	260	__u32 data[2];

include/uapi/linux/audit.h+1−1

@@ -187,7 +187,7 @@ · 186 unmodified lines
187	#define AUDIT_MAX_KEY_LEN 256	187	#define AUDIT_MAX_KEY_LEN 256
188	#define AUDIT_BITMASK_SIZE 64	188	#define AUDIT_BITMASK_SIZE 64
189	#define AUDIT_WORD(nr) ((__u32)((nr)/32))	189	#define AUDIT_WORD(nr) ((__u32)((nr)/32))
190	#define AUDIT_BIT(nr) (1 << ((nr) - AUDIT_WORD(nr)*32))	190	#define AUDIT_BIT(nr) (1U << ((nr) - AUDIT_WORD(nr)*32))
191		191
192	#define AUDIT_SYSCALL_CLASSES 16	192	#define AUDIT_SYSCALL_CLASSES 16
193	#define AUDIT_CLASS_DIR_WRITE 0	193	#define AUDIT_CLASS_DIR_WRITE 0

include/uapi/linux/capability.h+1−1

@@ -426,7 +426,7 @@ struct vfs_ns_cap_data { · 425 unmodified lines
426	*/	426	*/
427		427
428	#define CAP_TO_INDEX(x) ((x) >> 5) /* 1 << 5 == bits in __u32 */	428	#define CAP_TO_INDEX(x) ((x) >> 5) /* 1 << 5 == bits in __u32 */
429	#define CAP_TO_MASK(x) (1 << ((x) & 31)) /* mask for indexed __u32 */	429	#define CAP_TO_MASK(x) (1U << ((x) & 31)) /* mask for indexed __u32 */
430		430
431		431
432	#endif /* _UAPI_LINUX_CAPABILITY_H */	432	#endif /* _UAPI_LINUX_CAPABILITY_H */

include/uapi/linux/idxd.h+1−0

@@ -29,6 +29,7 @@ enum idxd_scmd_stat { · 28 unmodified lines
29	IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,	29	IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
30	IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,	30	IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
31	IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,	31	IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,
		32	IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000,
32	};	33	};
33		34
34	#define IDXD_SCMD_SOFTERR_MASK 0x80000000	35	#define IDXD_SCMD_SOFTERR_MASK 0x80000000

include/uapi/linux/in.h+1−0

@@ -20,6 +20,7 @@ · 19 unmodified lines
20	#define _UAPI_LINUX_IN_H	20	#define _UAPI_LINUX_IN_H
21		21
22	#include <linux/types.h>	22	#include <linux/types.h>
		23	#include <linux/stddef.h>
23	#include <linux/libc-compat.h>	24	#include <linux/libc-compat.h>
24	#include <linux/socket.h>	25	#include <linux/socket.h>
25		26

include/uapi/linux/io_uring.h+1−1

@@ -222,7 +222,7 @@ enum io_uring_op { · 221 unmodified lines
222		222
223	/*	223	/*
224	* sqe->uring_cmd_flags	224	* sqe->uring_cmd_flags
225	* IORING_URING_CMD_FIXED use registered buffer; pass thig flag	225	* IORING_URING_CMD_FIXED use registered buffer; pass this flag
226	* along with setting sqe->buf_index.	226	* along with setting sqe->buf_index.
227	*/	227	*/
228	#define IORING_URING_CMD_FIXED (1U << 0)	228	#define IORING_URING_CMD_FIXED (1U << 0)

io_uring/io_uring.c+8−2

 	return ctx->cached_cq_tail - READ_ONCE(ctx->rings->cq.head);
 }
+static inline unsigned int __io_cqring_events_user(struct io_ring_ctx *ctx)
+{
+	return READ_ONCE(ctx->rings->cq.tail) - READ_ONCE(ctx->rings->cq.head);
+}
 static bool io_match_linked(struct io_kiocb *head)
 {
 	struct io_kiocb *req;
 static inline bool io_should_wake(struct io_wait_queue *iowq)
 {
 	struct io_ring_ctx *ctx = iowq->ctx;
-	int dist = ctx->cached_cq_tail - (int) iowq->cq_tail;
+	int dist = READ_ONCE(ctx->rings->cq.tail) - (int) iowq->cq_tail;
 	/*
 	 * Wake up if we have enough events, or if a timeout occurred since we
 			return ret;
 		io_cqring_overflow_flush(ctx);
-		if (io_cqring_events(ctx) >= min_events)
+		/* if user messes with these they will just get an early return */
+		if (__io_cqring_events_user(ctx) >= min_events)
 			return 0;
 	} while (ret > 0);

io_uring/kbuf.c+2−0

 	tmp = READ_ONCE(sqe->off);
 	if (tmp > USHRT_MAX)
 		return -E2BIG;
+	if (tmp + p->nbufs >= USHRT_MAX)
+		return -EINVAL;
 	p->bid = tmp;
 	return 0;
 }

io_uring/poll.c+19−12

@@ -116,6 +116,8 @@ static void io_poll_req_insert_locked(struct io_kiocb *req) · 115 unmodified lines
116	struct io_hash_table *table = &req->ctx->cancel_table_locked;	116	struct io_hash_table *table = &req->ctx->cancel_table_locked;
117	u32 index = hash_long(req->cqe.user_data, table->hash_bits);	117	u32 index = hash_long(req->cqe.user_data, table->hash_bits);
118		118
		119	lockdep_assert_held(&req->ctx->uring_lock);
		120
119	hlist_add_head(&req->hash_node, &table->hbs[index].list);	121	hlist_add_head(&req->hash_node, &table->hbs[index].list);
120	}	122	}
121		123
@@ -394,7 +396,8 @@ static int io_poll_wake(struct wait_queue_entry *wait, unsigned mode, int sync, · 272 unmodified lines
394	return 1;	396	return 1;
395	}	397	}
396		398
397	static void io_poll_double_prepare(struct io_kiocb *req)	399	/* fails only when polling is already completing by the first entry */
		400	static bool io_poll_double_prepare(struct io_kiocb *req)
398	{	401	{
399	struct wait_queue_head *head;	402	struct wait_queue_head *head;
400	struct io_poll *poll = io_poll_get_single(req);	403	struct io_poll *poll = io_poll_get_single(req);
@@ -403,20 +406,20 @@ static void io_poll_double_prepare(struct io_kiocb *req) · 2 unmodified lines
403	rcu_read_lock();	406	rcu_read_lock();
404	head = smp_load_acquire(&poll->head);	407	head = smp_load_acquire(&poll->head);
405	/*	408	/*
406	* poll arm may not hold ownership and so race with	409	* poll arm might not hold ownership and so race for req->flags with
407	* io_poll_wake() by modifying req->flags. There is only one	410	* io_poll_wake(). There is only one poll entry queued, serialise with
408	* poll entry queued, serialise with it by taking its head lock.	411	* it by taking its head lock. As we're still arming the tw hanlder
		412	* is not going to be run, so there are no races with it.
409	*/	413	*/
410	if (head)	414	if (head) {
411	spin_lock_irq(&head->lock);	415	spin_lock_irq(&head->lock);
412		416	req->flags \|= REQ_F_DOUBLE_POLL;
413	req->flags \|= REQ_F_DOUBLE_POLL;	417	if (req->opcode == IORING_OP_POLL_ADD)
414	if (req->opcode == IORING_OP_POLL_ADD)	418	req->flags \|= REQ_F_ASYNC_DATA;
415	req->flags \|= REQ_F_ASYNC_DATA;
416
417	if (head)
418	spin_unlock_irq(&head->lock);	419	spin_unlock_irq(&head->lock);
		420	}
419	rcu_read_unlock();	421	rcu_read_unlock();
		422	return !!head;
420	}	423	}
421		424
422	static void __io_queue_proc(struct io_poll poll, struct io_poll_table pt,	425	static void __io_queue_proc(struct io_poll poll, struct io_poll_table pt,
@@ -454,7 +457,11 @@ static void __io_queue_proc(struct io_poll poll, struct io_poll_table pt, · 31 unmodified lines
454	/* mark as double wq entry */	457	/* mark as double wq entry */
455	wqe_private \|= IO_WQE_F_DOUBLE;	458	wqe_private \|= IO_WQE_F_DOUBLE;
456	io_init_poll_iocb(poll, first->events, first->wait.func);	459	io_init_poll_iocb(poll, first->events, first->wait.func);
457	io_poll_double_prepare(req);	460	if (!io_poll_double_prepare(req)) {
		461	/* the request is completing, just back off */
		462	kfree(poll);
		463	return;
		464	}
458	*poll_ptr = poll;	465	*poll_ptr = poll;
459	} else {	466	} else {
460	/* fine to modify, there is no poll queued to race with us */	467	/* fine to modify, there is no poll queued to race with us */

kernel/bpf/verifier.c+13−4

  */
 static void *realloc_array(void *arr, size_t old_n, size_t new_n, size_t size)
 {
+	void *new_arr;
 	if (!new_n || old_n == new_n)
 		goto out;
-	arr = krealloc_array(arr, new_n, size, GFP_KERNEL);
+	new_arr = krealloc_array(arr, new_n, size, GFP_KERNEL);
-	if (!arr)
+	if (!new_arr) {
+		kfree(arr);
 		return NULL;
+	}
+	arr = new_arr;
 	if (new_n > old_n)
 		memset(arr + old_n * size, 0, (new_n - old_n) * size);
 		return err;
 	bpf_for_each_reg_in_vstate(env->cur_state, state, reg, ({
-		if (reg->ref_obj_id == ref_obj_id)
+		if (reg->ref_obj_id == ref_obj_id) {
-			__mark_reg_unknown(env, reg);
+			if (!env->allow_ptr_leaks)
+				__mark_reg_not_init(env, reg);
+			else
+				__mark_reg_unknown(env, reg);
+		}
 	}));
 	return 0;

lib/Kconfig.debug+5−1

 config FRAME_WARN
 	int "Warn for stack frames larger than"
 	range 0 8192
+	default 0 if KMSAN
 	default 2048 if GCC_PLUGIN_LATENT_ENTROPY
 	default 2048 if PARISC
 	default 1536 if (!64BIT && XTENSA)
 	default 1024 if !64BIT
 	default 2048 if 64BIT
-	default 0 if KMSAN
 	help
 	  Tell the compiler to warn at build time for stack frames larger than this.
 	  Setting this too low will cause a lot of warnings.
 config TEST_XARRAY
 	tristate "Test the XArray code at runtime"
+config TEST_MAPLE_TREE
+	select DEBUG_MAPLE_TREE
+	tristate "Test the Maple Tree code at runtime"
 config TEST_RHASHTABLE
 	tristate "Perform selftest on resizable hash table"
 	help

lib/Kconfig.kmsan+1−0

@@ -12,6 +12,7 @@ config KMSAN · 11 unmodified lines
12	bool "KMSAN: detector of uninitialized values use"	12	bool "KMSAN: detector of uninitialized values use"
13	depends on HAVE_ARCH_KMSAN && HAVE_KMSAN_COMPILER	13	depends on HAVE_ARCH_KMSAN && HAVE_KMSAN_COMPILER
14	depends on SLUB && DEBUG_KERNEL && !KASAN && !KCSAN	14	depends on SLUB && DEBUG_KERNEL && !KASAN && !KCSAN
		15	depends on !PREEMPT_RT
15	select STACKDEPOT	16	select STACKDEPOT
16	select STACKDEPOT_ALWAYS_INIT	17	select STACKDEPOT_ALWAYS_INIT
17	help	18	help

lib/Makefile+1−0

@@ -85,6 +85,7 @@ obj-$(CONFIG_TEST_BITMAP) += test_bitmap.o · 84 unmodified lines
85	obj-$(CONFIG_TEST_STRSCPY) += test_strscpy.o	85	obj-$(CONFIG_TEST_STRSCPY) += test_strscpy.o
86	obj-$(CONFIG_TEST_UUID) += test_uuid.o	86	obj-$(CONFIG_TEST_UUID) += test_uuid.o
87	obj-$(CONFIG_TEST_XARRAY) += test_xarray.o	87	obj-$(CONFIG_TEST_XARRAY) += test_xarray.o
		88	obj-$(CONFIG_TEST_MAPLE_TREE) += test_maple_tree.o
88	obj-$(CONFIG_TEST_PARMAN) += test_parman.o	89	obj-$(CONFIG_TEST_PARMAN) += test_parman.o
89	obj-$(CONFIG_TEST_KMOD) += test_kmod.o	90	obj-$(CONFIG_TEST_KMOD) += test_kmod.o
90	obj-$(CONFIG_TEST_DEBUG_VIRTUAL) += test_debug_virtual.o	91	obj-$(CONFIG_TEST_DEBUG_VIRTUAL) += test_debug_virtual.o

lib/maple_tree.c+40−18

 	call_rcu(&node->rcu, mt_free_rcu);
 }
-static unsigned int mt_height(const struct maple_tree *mt)
-{
-	return (mt->ma_flags & MT_FLAGS_HEIGHT_MASK) >> MT_FLAGS_HEIGHT_OFFSET;
-}
 static void mas_set_height(struct ma_state *mas)
 {
 static inline void mas_alloc_nodes(struct ma_state *mas, gfp_t gfp)
 {
 	struct maple_alloc *node;
-	struct maple_alloc **nodep = &mas->alloc;
 	unsigned long allocated = mas_allocated(mas);
 	unsigned long success = allocated;
 	unsigned int requested = mas_alloc_req(mas);
 			node->node_count--;
 		success += count;
-		nodep = &node->slot[0];
+		node = node->slot[0];
-		node = *nodep;
 		requested -= count;
 	}
 	mas->alloc->total = success;
 		root = mas_root(mas);
 		/* Tree with nodes */
 		if (likely(xa_is_node(root))) {
+			mas->depth = 1;
 			mas->node = mte_safe_root(root);
 			return NULL;
 		}
 	node = mas_pop_node(wr_mas->mas);
 	node->parent = mas_mn(wr_mas->mas)->parent;
 	wr_mas->mas->node = mt_mk_node(node, b_type);
-	mab_mas_cp(b_node, 0, b_end, wr_mas->mas, true);
+	mab_mas_cp(b_node, 0, b_end, wr_mas->mas, false);
 	mas_replace(wr_mas->mas, false);
 reuse_node:
 	mas_update_gap(wr_mas->mas);
 static inline void mas_wr_walk_descend(struct ma_wr_state *wr_mas)
 {
-	wr_mas->mas->depth++;
 	wr_mas->type = mte_node_type(wr_mas->mas->node);
 	mas_wr_node_walk(wr_mas);
 	wr_mas->slots = ma_slots(wr_mas->node, wr_mas->type);
 	wr_mas->mas->min = wr_mas->r_min;
 	wr_mas->mas->node = wr_mas->content;
 	wr_mas->mas->offset = 0;
+	wr_mas->mas->depth++;
 }
 /*
  * mas_wr_walk() - Walk the tree for a write.
 {
 	enum maple_type type = mte_node_type(mas->node);
 	unsigned long pivot, min, gap = 0;
-	unsigned char count, offset;
+	unsigned char offset;
-	unsigned long *gaps = NULL, *pivots = ma_pivots(mas_mn(mas), type);
+	unsigned long *gaps;
+	unsigned long *pivots = ma_pivots(mas_mn(mas), type);
 	void __rcu **slots = ma_slots(mas_mn(mas), type);
 	bool found = false;
 	gaps = ma_gaps(mte_to_node(mas->node), type);
 	offset = mas->offset;
-	count = mt_slots[type];
 	min = mas_safe_min(mas, pivots, offset);
-	for (; offset < count; offset++) {
+	for (; offset < mt_slots[type]; offset++) {
 		pivot = mas_safe_pivot(mas, pivots, offset, type);
 		if (offset && !pivot)
 			break;
 				mas->min = min;
 				mas->max = pivot;
 				offset = 0;
-				type = mte_node_type(mas->node);
-				count = mt_slots[type];
 				break;
 			}
 		}
 	return entry;
 }
+EXPORT_SYMBOL_GPL(mas_walk);
 static inline bool mas_rewind_node(struct ma_state *mas)
 {
 	mas->last = mas->index + size - 1;
 	return 0;
 }
+EXPORT_SYMBOL_GPL(mas_empty_area);
 /*
  * mas_empty_area_rev() - Get the highest address within the range that is
 	mas->index = mas->last - size + 1;
 	return 0;
 }
+EXPORT_SYMBOL_GPL(mas_empty_area_rev);
 static inline int mas_alloc(struct ma_state *mas, void *entry,
 		unsigned long size, unsigned long *index)
 	mas_wr_store_entry(&wr_mas);
 	return wr_mas.content;
 }
+EXPORT_SYMBOL_GPL(mas_store);
 /**
  * mas_store_gfp() - Store a value into the tree.
 	return 0;
 }
+EXPORT_SYMBOL_GPL(mas_store_gfp);
 /**
  * mas_store_prealloc() - Store a value into the tree using memory
 	BUG_ON(mas_is_err(mas));
 	mas_destroy(mas);
 }
+EXPORT_SYMBOL_GPL(mas_store_prealloc);
 /**
  * mas_preallocate() - Preallocate enough nodes for a store operation
 	}
 	mas->alloc = NULL;
 }
+EXPORT_SYMBOL_GPL(mas_destroy);
 /*
  * mas_expected_entries() - Set the expected number of entries that will be inserted.
 	return ret;
 }
+EXPORT_SYMBOL_GPL(mas_expected_entries);
 /**
  * mas_next() - Get the next entry.
 	/* Retries on dead nodes handled by mas_next_entry */
 	return mas_next_entry(mas, max);
 }
+EXPORT_SYMBOL_GPL(mas_find);
 /**
  * mas_find_rev: On the first call, find the first non-null entry at or below
 	/* Retries on dead nodes handled by mas_next_entry */
 	return mas_prev_entry(mas, min);
 }
-EXPORT_SYMBOL_GPL(mas_find);
+EXPORT_SYMBOL_GPL(mas_find_rev);
 /**
  * mas_erase() - Find the range in which index resides and erase the entire
 	mas_rewalk(mas, index);
 	return 1;
 }
-#endif /* not defined __KERNEL__ */
+void mt_cache_shrink(void)
+{
+}
+#else
+/*
+ * mt_cache_shrink() - For testing, don't use this.
+ *
+ * Certain testcases can trigger an OOM when combined with other memory
+ * debugging configuration options.  This function is used to reduce the
+ * possibility of an out of memory even due to kmem_cache objects remaining
+ * around for longer than usual.
+ */
+void mt_cache_shrink(void)
+{
+	kmem_cache_shrink(maple_node_cache);
+}
+EXPORT_SYMBOL_GPL(mt_cache_shrink);
+#endif /* not defined __KERNEL__ */
 /*
  * mas_get_slot() - Get the entry in the maple state node stored at @offset.
  * @mas: The maple state
 	else if (entry)
 		mt_dump_node(mt, entry, 0, mt_max[mte_node_type(entry)], 0);
 }
+EXPORT_SYMBOL_GPL(mt_dump);
 /*
  * Calculate the maximum gap in a node and check if that's what is reported in
 	rcu_read_unlock();
 }
+EXPORT_SYMBOL_GPL(mt_validate);
 #endif /* CONFIG_DEBUG_MAPLE_TREE */

lib/test_maple_tree.c+1193−36733

@@ -1,24 +1,35 @@
1	// SPDX-License-Identifier: GPL-2.0+	1	// SPDX-License-Identifier: GPL-2.0+
2	/*	2	/*
3	* test_maple_tree.c: Test the maple tree API	3	* test_maple_tree.c: Test the maple tree API
4	* Copyright (c) 2018 Liam R. Howlett	4	* Copyright (c) 2018-2022 Oracle Corporation
5	* Author: Liam R. Howlett <Liam.Howlett@Oracle.com>	5	* Author: Liam R. Howlett <Liam.Howlett@Oracle.com>
		6	*
		7	* Any tests that only require the interface of the tree.
6	*/	8	*/
7		9
8	#include <linux/maple_tree.h>	10	#include <linux/maple_tree.h>
9	#include <linux/module.h>	11	#include <linux/module.h>
10	#include <stdlib.h>
11	#include <time.h>
12		12
13	#define MTREE_ALLOC_MAX 0x2000000000000Ul	13	#define MTREE_ALLOC_MAX 0x2000000000000Ul
		14	#ifndef CONFIG_DEBUG_MAPLE_TREE
14	#define CONFIG_DEBUG_MAPLE_TREE	15	#define CONFIG_DEBUG_MAPLE_TREE
		16	#endif
15	#define CONFIG_MAPLE_SEARCH	17	#define CONFIG_MAPLE_SEARCH
		18	#define MAPLE_32BIT (MAPLE_NODE_SLOTS > 31)
		19
16	/* #define BENCH_SLOT_STORE */	20	/* #define BENCH_SLOT_STORE */
17	/* #define BENCH_NODE_STORE */	21	/* #define BENCH_NODE_STORE */
18	/* #define BENCH_AWALK */	22	/* #define BENCH_AWALK */
19	/* #define BENCH_WALK */	23	/* #define BENCH_WALK */
20	/* #define BENCH_MT_FOR_EACH */	24	/* #define BENCH_MT_FOR_EACH */
21	/* #define BENCH_FORK */	25	/* #define BENCH_FORK */
		26
		27	#ifdef __KERNEL__
		28	#define mt_set_non_kernel(x) do {} while (0)
		29	#define mt_zero_nr_tallocated(x) do {} while (0)
		30	#else
		31	#define cond_resched() do {} while (0)
		32	#endif
22	static	33	static
23	int mtree_insert_index(struct maple_tree *mt, unsigned long index, gfp_t gfp)	34	int mtree_insert_index(struct maple_tree *mt, unsigned long index, gfp_t gfp)
24	{	35	{
@@ -65,6 +76,7 @@ static void mtree_test_erase(struct maple_tree mt, unsigned long index) · 40 unmodified lines
65	return mtree_erase(mt, index);	76	return mtree_erase(mt, index);
66	}	77	}
67		78
		79	#if defined(CONFIG_64BIT)
68	static noinline void check_mtree_alloc_range(struct maple_tree *mt,	80	static noinline void check_mtree_alloc_range(struct maple_tree *mt,
69	unsigned long start, unsigned long end, unsigned long size,	81	unsigned long start, unsigned long end, unsigned long size,
70	unsigned long expected, int eret, void *ptr)	82	unsigned long expected, int eret, void *ptr)
@@ -98,6 +110,7 @@ static noinline void check_mtree_alloc_rrange(struct maple_tree *mt, · 27 unmodified lines
98		110
99	MT_BUG_ON(mt, result != expected);	111	MT_BUG_ON(mt, result != expected);
100	}	112	}
		113	#endif
101		114
102	static noinline void check_load(struct maple_tree *mt, unsigned long index,	115	static noinline void check_load(struct maple_tree *mt, unsigned long index,
103	void *ptr)	116	void *ptr)
@@ -150,12 +163,6 @@ static noinline void check_insert(struct maple_tree *mt, unsigned long index, · 46 unmodified lines
150	MT_BUG_ON(mt, ret != 0);	163	MT_BUG_ON(mt, ret != 0);
151	}	164	}
152		165
153	static noinline void check_erase(struct maple_tree *mt, unsigned long index,
154	void *ptr)
155	{
156	MT_BUG_ON(mt, mtree_test_erase(mt, index) != ptr);
157	}
158
159	static noinline void check_dup_insert(struct maple_tree *mt,	166	static noinline void check_dup_insert(struct maple_tree *mt,
160	unsigned long index, void *ptr)	167	unsigned long index, void *ptr)
161	{	168	{
@@ -172,41 +179,6 @@ void check_index_load(struct maple_tree *mt, unsigned long index) · 10 unmodified lines
172	return check_load(mt, index, xa_mk_value(index & LONG_MAX));	179	return check_load(mt, index, xa_mk_value(index & LONG_MAX));
173	}	180	}
174		181
175	static noinline void check_nomem(struct maple_tree *mt)
176	{
177	MA_STATE(ms, mt, 1, 1);
178
179	MT_BUG_ON(mt, !mtree_empty(mt));
180	/* Ensure no bypassing of allocation failures */
181	mt_set_non_kernel(0);
182
183	/* Storing something at 1 requires memory allocation */
184	MT_BUG_ON(mt, mtree_insert(mt, 1, &ms, GFP_ATOMIC) != -ENOMEM);
185	/* Storing something at 0 does not */
186	MT_BUG_ON(mt, mtree_insert(mt, 0, &ms, GFP_ATOMIC) != 0);
187
188	/*
189	* Simulate two threads racing; the first one fails to allocate
190	* memory to insert an entry at 1, then the second one succeeds
191	* in allocating memory to insert an entry at 2. The first one
192	* then needs to free the node it allocated. LeakSanitizer will
193	* notice this, as will the 'nr_allocated' debugging aid in the
194	* userspace test suite.
195	*/
196	mtree_lock(mt);
197	mas_store(&ms, &ms); /* insert 1 -> &ms, fails. */
198	MT_BUG_ON(mt, ms.node != MA_ERROR(-ENOMEM));
199	mas_nomem(&ms, GFP_KERNEL); /* Node allocated in here. */
200	MT_BUG_ON(mt, ms.node != MAS_START);
201	mtree_unlock(mt);
202	MT_BUG_ON(mt, mtree_insert(mt, 2, mt, GFP_KERNEL) != 0);
203	mtree_lock(mt);
204	mas_store(&ms, &ms); /* insert 1 -> &ms */
205	mas_nomem(&ms, GFP_KERNEL); /* Node allocated in here. */
206	mtree_unlock(mt);
207	mtree_destroy(mt);
208	}
209
210	static inline int not_empty(struct maple_node *node)	182	static inline int not_empty(struct maple_node *node)
211	{	183	{
212	int i;	184	int i;
@@ -221,350 +193,6 @@ static inline int not_empty(struct maple_node *node) · 8 unmodified lines
221	return 0;	193	return 0;
222	}	194	}
223		195
224	static noinline void check_new_node(struct maple_tree *mt)
225	{
226
227	struct maple_node mn, mn2, *mn3;
228	struct maple_alloc *smn;
229	struct maple_node *nodes[100];
230	int i, j, total;
231
232	MA_STATE(mas, mt, 0, 0);
233
234	/* Try allocating 3 nodes */
235	mtree_lock(mt);
236	/* request 3 nodes to be allocated. */
237	mas_node_count(&mas, 3);
238	/* Allocation request of 3. */
239	MT_BUG_ON(mt, mas_alloc_req(&mas) != 3);
240	/* Allocate failed. */
241	MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
242	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
243
244	MT_BUG_ON(mt, mas_allocated(&mas) != 3);
245	mn = mas_pop_node(&mas);
246	MT_BUG_ON(mt, not_empty(mn));
247	MT_BUG_ON(mt, mn == NULL);
248	MT_BUG_ON(mt, mas.alloc == NULL);
249	MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
250	mas_push_node(&mas, mn);
251	mas_nomem(&mas, GFP_KERNEL); /* free */
252	mtree_unlock(mt);
253
254
255	/* Try allocating 1 node, then 2 more */
256	mtree_lock(mt);
257	/* Set allocation request to 1. */
258	mas_set_alloc_req(&mas, 1);
259	/* Check Allocation request of 1. */
260	MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
261	mas_set_err(&mas, -ENOMEM);
262	/* Validate allocation request. */
263	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
264	/* Eat the requested node. */
265	mn = mas_pop_node(&mas);
266	MT_BUG_ON(mt, not_empty(mn));
267	MT_BUG_ON(mt, mn == NULL);
268	MT_BUG_ON(mt, mn->slot[0] != NULL);
269	MT_BUG_ON(mt, mn->slot[1] != NULL);
270	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
271
272	ma_free_rcu(mn);
273	mas.node = MAS_START;
274	mas_nomem(&mas, GFP_KERNEL);
275	/* Allocate 3 nodes, will fail. */
276	mas_node_count(&mas, 3);
277	/* Drop the lock and allocate 3 nodes. */
278	mas_nomem(&mas, GFP_KERNEL);
279	/* Ensure 3 are allocated. */
280	MT_BUG_ON(mt, mas_allocated(&mas) != 3);
281	/* Allocation request of 0. */
282	MT_BUG_ON(mt, mas_alloc_req(&mas) != 0);
283
284	MT_BUG_ON(mt, mas.alloc == NULL);
285	MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
286	MT_BUG_ON(mt, mas.alloc->slot[1] == NULL);
287	/* Ensure we counted 3. */
288	MT_BUG_ON(mt, mas_allocated(&mas) != 3);
289	/* Free. */
290	mas_nomem(&mas, GFP_KERNEL);
291
292	/* Set allocation request to 1. */
293	mas_set_alloc_req(&mas, 1);
294	MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
295	mas_set_err(&mas, -ENOMEM);
296	/* Validate allocation request. */
297	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
298	MT_BUG_ON(mt, mas_allocated(&mas) != 1);
299	/* Check the node is only one node. */
300	mn = mas_pop_node(&mas);
301	MT_BUG_ON(mt, not_empty(mn));
302	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
303	MT_BUG_ON(mt, mn == NULL);
304	MT_BUG_ON(mt, mn->slot[0] != NULL);
305	MT_BUG_ON(mt, mn->slot[1] != NULL);
306	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
307	mas_push_node(&mas, mn);
308	MT_BUG_ON(mt, mas_allocated(&mas) != 1);
309	MT_BUG_ON(mt, mas.alloc->node_count);
310
311	mas_set_alloc_req(&mas, 2); /* request 2 more. */
312	MT_BUG_ON(mt, mas_alloc_req(&mas) != 2);
313	mas_set_err(&mas, -ENOMEM);
314	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
315	MT_BUG_ON(mt, mas_allocated(&mas) != 3);
316	MT_BUG_ON(mt, mas.alloc == NULL);
317	MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
318	MT_BUG_ON(mt, mas.alloc->slot[1] == NULL);
319	for (i = 2; i >= 0; i--) {
320	mn = mas_pop_node(&mas);
321	MT_BUG_ON(mt, mas_allocated(&mas) != i);
322	MT_BUG_ON(mt, !mn);
323	MT_BUG_ON(mt, not_empty(mn));
324	ma_free_rcu(mn);
325	}
326
327	total = 64;
328	mas_set_alloc_req(&mas, total); /* request 2 more. */
329	MT_BUG_ON(mt, mas_alloc_req(&mas) != total);
330	mas_set_err(&mas, -ENOMEM);
331	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
332	for (i = total; i > 0; i--) {
333	unsigned int e = 0; /* expected node_count */
334
335	if (i >= 35)
336	e = i - 35;
337	else if (i >= 5)
338	e = i - 5;
339	else if (i >= 2)
340	e = i - 2;
341	MT_BUG_ON(mt, mas.alloc->node_count != e);
342	mn = mas_pop_node(&mas);
343	MT_BUG_ON(mt, not_empty(mn));
344	MT_BUG_ON(mt, mas_allocated(&mas) != i - 1);
345	MT_BUG_ON(mt, !mn);
346	ma_free_rcu(mn);
347	}
348
349	total = 100;
350	for (i = 1; i < total; i++) {
351	mas_set_alloc_req(&mas, i);
352	mas_set_err(&mas, -ENOMEM);
353	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
354	for (j = i; j > 0; j--) {
355	mn = mas_pop_node(&mas);
356	MT_BUG_ON(mt, mas_allocated(&mas) != j - 1);
357	MT_BUG_ON(mt, !mn);
358	MT_BUG_ON(mt, not_empty(mn));
359	mas_push_node(&mas, mn);
360	MT_BUG_ON(mt, mas_allocated(&mas) != j);
361	mn = mas_pop_node(&mas);
362	MT_BUG_ON(mt, not_empty(mn));
363	MT_BUG_ON(mt, mas_allocated(&mas) != j - 1);
364	ma_free_rcu(mn);
365	}
366	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
367
368	mas_set_alloc_req(&mas, i);
369	mas_set_err(&mas, -ENOMEM);
370	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
371	for (j = 0; j <= i/2; j++) {
372	MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
373	nodes[j] = mas_pop_node(&mas);
374	MT_BUG_ON(mt, mas_allocated(&mas) != i - j - 1);
375	}
376
377	while (j) {
378	j--;
379	mas_push_node(&mas, nodes[j]);
380	MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
381	}
382	MT_BUG_ON(mt, mas_allocated(&mas) != i);
383	for (j = 0; j <= i/2; j++) {
384	MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
385	mn = mas_pop_node(&mas);
386	MT_BUG_ON(mt, not_empty(mn));
387	ma_free_rcu(mn);
388	MT_BUG_ON(mt, mas_allocated(&mas) != i - j - 1);
389	}
390	MT_BUG_ON(mt, mas_nomem(&mas, GFP_KERNEL));
391
392	}
393
394	/* Set allocation request. */
395	total = 500;
396	mas_node_count(&mas, total);
397	/* Drop the lock and allocate the nodes. */
398	mas_nomem(&mas, GFP_KERNEL);
399	MT_BUG_ON(mt, !mas.alloc);
400	i = 1;
401	smn = mas.alloc;
402	while (i < total) {
403	for (j = 0; j < MAPLE_ALLOC_SLOTS; j++) {
404	i++;
405	MT_BUG_ON(mt, !smn->slot[j]);
406	if (i == total)
407	break;
408	}
409	smn = smn->slot[0]; /* next. */
410	}
411	MT_BUG_ON(mt, mas_allocated(&mas) != total);
412	mas_nomem(&mas, GFP_KERNEL); /* Free. */
413
414	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
415	for (i = 1; i < 128; i++) {
416	mas_node_count(&mas, i); /* Request */
417	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
418	MT_BUG_ON(mt, mas_allocated(&mas) != i); /* check request filled */
419	for (j = i; j > 0; j--) { /Free the requests /
420	mn = mas_pop_node(&mas); /* get the next node. */
421	MT_BUG_ON(mt, mn == NULL);
422	MT_BUG_ON(mt, not_empty(mn));
423	ma_free_rcu(mn);
424	}
425	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
426	}
427
428	for (i = 1; i < MAPLE_NODE_MASK + 1; i++) {
429	MA_STATE(mas2, mt, 0, 0);
430	mas_node_count(&mas, i); /* Request */
431	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
432	MT_BUG_ON(mt, mas_allocated(&mas) != i); /* check request filled */
433	for (j = 1; j <= i; j++) { /* Move the allocations to mas2 */
434	mn = mas_pop_node(&mas); /* get the next node. */
435	MT_BUG_ON(mt, mn == NULL);
436	MT_BUG_ON(mt, not_empty(mn));
437	mas_push_node(&mas2, mn);
438	MT_BUG_ON(mt, mas_allocated(&mas2) != j);
439	}
440	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
441	MT_BUG_ON(mt, mas_allocated(&mas2) != i);
442
443	for (j = i; j > 0; j--) { /Free the requests /
444	MT_BUG_ON(mt, mas_allocated(&mas2) != j);
445	mn = mas_pop_node(&mas2); /* get the next node. */
446	MT_BUG_ON(mt, mn == NULL);
447	MT_BUG_ON(mt, not_empty(mn));
448	ma_free_rcu(mn);
449	}
450	MT_BUG_ON(mt, mas_allocated(&mas2) != 0);
451	}
452
453
454	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
455	mas_node_count(&mas, MAPLE_ALLOC_SLOTS + 1); /* Request */
456	MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
457	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
458	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
459	MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
460
461	mn = mas_pop_node(&mas); /* get the next node. */
462	MT_BUG_ON(mt, mn == NULL);
463	MT_BUG_ON(mt, not_empty(mn));
464	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS);
465	MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 2);
466
467	mas_push_node(&mas, mn);
468	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
469	MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
470
471	/* Check the limit of pop/push/pop */
472	mas_node_count(&mas, MAPLE_ALLOC_SLOTS + 2); /* Request */
473	MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
474	MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
475	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
476	MT_BUG_ON(mt, mas_alloc_req(&mas));
477	MT_BUG_ON(mt, mas.alloc->node_count);
478	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 2);
479	mn = mas_pop_node(&mas);
480	MT_BUG_ON(mt, not_empty(mn));
481	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
482	MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
483	mas_push_node(&mas, mn);
484	MT_BUG_ON(mt, mas.alloc->node_count);
485	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 2);
486	mn = mas_pop_node(&mas);
487	MT_BUG_ON(mt, not_empty(mn));
488	ma_free_rcu(mn);
489	for (i = 1; i <= MAPLE_ALLOC_SLOTS + 1; i++) {
490	mn = mas_pop_node(&mas);
491	MT_BUG_ON(mt, not_empty(mn));
492	ma_free_rcu(mn);
493	}
494	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
495
496
497	for (i = 3; i < MAPLE_NODE_MASK * 3; i++) {
498	mas.node = MA_ERROR(-ENOMEM);
499	mas_node_count(&mas, i); /* Request */
500	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
501	mn = mas_pop_node(&mas); /* get the next node. */
502	mas_push_node(&mas, mn); /* put it back */
503	mas_destroy(&mas);
504
505	mas.node = MA_ERROR(-ENOMEM);
506	mas_node_count(&mas, i); /* Request */
507	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
508	mn = mas_pop_node(&mas); /* get the next node. */
509	mn2 = mas_pop_node(&mas); /* get the next node. */
510	mas_push_node(&mas, mn); /* put them back */
511	mas_push_node(&mas, mn2);
512	mas_destroy(&mas);
513
514	mas.node = MA_ERROR(-ENOMEM);
515	mas_node_count(&mas, i); /* Request */
516	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
517	mn = mas_pop_node(&mas); /* get the next node. */
518	mn2 = mas_pop_node(&mas); /* get the next node. */
519	mn3 = mas_pop_node(&mas); /* get the next node. */
520	mas_push_node(&mas, mn); /* put them back */
521	mas_push_node(&mas, mn2);
522	mas_push_node(&mas, mn3);
523	mas_destroy(&mas);
524
525	mas.node = MA_ERROR(-ENOMEM);
526	mas_node_count(&mas, i); /* Request */
527	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
528	mn = mas_pop_node(&mas); /* get the next node. */
529	ma_free_rcu(mn);
530	mas_destroy(&mas);
531
532	mas.node = MA_ERROR(-ENOMEM);
533	mas_node_count(&mas, i); /* Request */
534	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
535	mn = mas_pop_node(&mas); /* get the next node. */
536	ma_free_rcu(mn);
537	mn = mas_pop_node(&mas); /* get the next node. */
538	ma_free_rcu(mn);
539	mn = mas_pop_node(&mas); /* get the next node. */
540	ma_free_rcu(mn);
541	mas_destroy(&mas);
542	}
543
544	mas.node = MA_ERROR(-ENOMEM);
545	mas_node_count(&mas, 5); /* Request */
546	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
547	MT_BUG_ON(mt, mas_allocated(&mas) != 5);
548	mas.node = MA_ERROR(-ENOMEM);
549	mas_node_count(&mas, 10); /* Request */
550	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
551	mas.node = MAS_START;
552	MT_BUG_ON(mt, mas_allocated(&mas) != 10);
553	mas_destroy(&mas);
554
555	mas.node = MA_ERROR(-ENOMEM);
556	mas_node_count(&mas, MAPLE_ALLOC_SLOTS - 1); /* Request */
557	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
558	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS - 1);
559	mas.node = MA_ERROR(-ENOMEM);
560	mas_node_count(&mas, 10 + MAPLE_ALLOC_SLOTS - 1); /* Request */
561	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
562	mas.node = MAS_START;
563	MT_BUG_ON(mt, mas_allocated(&mas) != 10 + MAPLE_ALLOC_SLOTS - 1);
564	mas_destroy(&mas);
565
566	mtree_unlock(mt);
567	}
568		196
569	static noinline void check_rev_seq(struct maple_tree *mt, unsigned long max,	197	static noinline void check_rev_seq(struct maple_tree *mt, unsigned long max,
570	bool verbose)	198	bool verbose)
@@ -588,6 +216,7 @@ static noinline void check_rev_seq(struct maple_tree *mt, unsigned long max, · 17 unmodified lines
588	}	216	}
589	check_load(mt, max + 1, NULL);	217	check_load(mt, max + 1, NULL);
590		218
		219	#ifndef __KERNEL__
591	if (verbose) {	220	if (verbose) {
592	rcu_barrier();	221	rcu_barrier();
593	mt_dump(mt);	222	mt_dump(mt);
@@ -595,6 +224,7 @@ static noinline void check_rev_seq(struct maple_tree *mt, unsigned long max, · 1 unmodified line
595	__func__, max, mt_get_alloc_size()/1024, mt_nr_allocated(),	224	__func__, max, mt_get_alloc_size()/1024, mt_nr_allocated(),
596	mt_nr_tallocated());	225	mt_nr_tallocated());
597	}	226	}
		227	#endif
598	}	228	}
599		229
600	static noinline void check_seq(struct maple_tree *mt, unsigned long max,	230	static noinline void check_seq(struct maple_tree *mt, unsigned long max,
@@ -614,6 +244,8 @@ static noinline void check_seq(struct maple_tree *mt, unsigned long max, · 13 unmodified lines
614	MT_BUG_ON(mt, !mt_height(mt));	244	MT_BUG_ON(mt, !mt_height(mt));
615	check_load(mt, i + 1, NULL);	245	check_load(mt, i + 1, NULL);
616	}	246	}
		247
		248	#ifndef __KERNEL__
617	if (verbose) {	249	if (verbose) {
618	rcu_barrier();	250	rcu_barrier();
619	mt_dump(mt);	251	mt_dump(mt);
@@ -621,6 +253,7 @@ static noinline void check_seq(struct maple_tree *mt, unsigned long max, · 1 unmodified line
621	max, mt_get_alloc_size()/1024, mt_nr_allocated(),	253	max, mt_get_alloc_size()/1024, mt_nr_allocated(),
622	mt_nr_tallocated());	254	mt_nr_tallocated());
623	}	255	}
		256	#endif
624	}	257	}
625		258
626	static noinline void check_lb_not_empty(struct maple_tree *mt)	259	static noinline void check_lb_not_empty(struct maple_tree *mt)
@@ -651,10 +284,15 @@ static noinline void check_lower_bound_split(struct maple_tree *mt) · 24 unmodified lines
651	static noinline void check_upper_bound_split(struct maple_tree *mt)	284	static noinline void check_upper_bound_split(struct maple_tree *mt)
652	{	285	{
653	unsigned long i, j;	286	unsigned long i, j;
654	unsigned long huge = 4000UL * 1000 * 1000;	287	unsigned long huge;
655		288
656	MT_BUG_ON(mt, !mtree_empty(mt));	289	MT_BUG_ON(mt, !mtree_empty(mt));
657		290
		291	if (MAPLE_32BIT)
		292	huge = 2147483647UL;
		293	else
		294	huge = 4000UL * 1000 * 1000;
		295
658	i = 4096;	296	i = 4096;
659	while (i < huge) {	297	while (i < huge) {
660	check_insert(mt, i, (void *) i);	298	check_insert(mt, i, (void *) i);
@@ -687,6 +325,7 @@ static noinline void check_rev_find(struct maple_tree *mt) · 26 unmodified lines
687	mtree_store_range(mt, i10, i10 + 5,	325	mtree_store_range(mt, i10, i10 + 5,
688	xa_mk_value(i), GFP_KERNEL);	326	xa_mk_value(i), GFP_KERNEL);
689		327
		328	rcu_read_lock();
690	mas_set(&mas, 1000);	329	mas_set(&mas, 1000);
691	val = mas_find_rev(&mas, 1000);	330	val = mas_find_rev(&mas, 1000);
692	MT_BUG_ON(mt, val != xa_mk_value(100));	331	MT_BUG_ON(mt, val != xa_mk_value(100));
@@ -712,13 +351,15 @@ static noinline void check_rev_find(struct maple_tree *mt) · 19 unmodified lines
712	MT_BUG_ON(mt, val != xa_mk_value(0));	351	MT_BUG_ON(mt, val != xa_mk_value(0));
713	val = mas_find_rev(&mas, 0);	352	val = mas_find_rev(&mas, 0);
714	MT_BUG_ON(mt, val != NULL);	353	MT_BUG_ON(mt, val != NULL);
		354	rcu_read_unlock();
715	}	355	}
716		356
717	static noinline void check_find(struct maple_tree *mt)	357	static noinline void check_find(struct maple_tree *mt)
718	{	358	{
719	unsigned long val = 0;	359	unsigned long val = 0;
720	unsigned long count = 20;	360	unsigned long count;
721	unsigned long max;	361	unsigned long max;
		362	unsigned long top;
722	unsigned long last = 0, index = 0;	363	unsigned long last = 0, index = 0;
723	void entry, entry2;	364	void entry, entry2;
724		365
@@ -727,6 +368,18 @@ static noinline void check_find(struct maple_tree *mt) · 2 unmodified lines
727	/* Insert 0. */	368	/* Insert 0. */
728	MT_BUG_ON(mt, mtree_insert_index(mt, val++, GFP_KERNEL));	369	MT_BUG_ON(mt, mtree_insert_index(mt, val++, GFP_KERNEL));
729		370
		371	#if defined(CONFIG_64BIT)
		372	top = 4398046511104UL;
		373	#else
		374	top = ULONG_MAX;
		375	#endif
		376
		377	if (MAPLE_32BIT) {
		378	count = 15;
		379	} else {
		380	count = 20;
		381	}
		382
730	for (int i = 0; i <= count; i++) {	383	for (int i = 0; i <= count; i++) {
731	if (val != 64)	384	if (val != 64)
732	MT_BUG_ON(mt, mtree_insert_index(mt, val, GFP_KERNEL));	385	MT_BUG_ON(mt, mtree_insert_index(mt, val, GFP_KERNEL));
@@ -805,12 +458,17 @@ static noinline void check_find(struct maple_tree *mt) · 72 unmodified lines
805	index = 0;	458	index = 0;
806	MT_BUG_ON(mt, mtree_insert_index(mt, ULONG_MAX, GFP_KERNEL));	459	MT_BUG_ON(mt, mtree_insert_index(mt, ULONG_MAX, GFP_KERNEL));
807	mt_for_each(mt, entry, index, ULONG_MAX) {	460	mt_for_each(mt, entry, index, ULONG_MAX) {
808	if (val == 4398046511104)	461	if (val == top)
809	MT_BUG_ON(mt, entry !=	462	MT_BUG_ON(mt, entry != xa_mk_value(LONG_MAX));
810	xa_mk_value(ULONG_MAX & LONG_MAX));
811	else	463	else
812	MT_BUG_ON(mt, xa_mk_value(val) != entry);	464	MT_BUG_ON(mt, xa_mk_value(val) != entry);
813	val <<= 2;	465
		466	/* Workaround for 32bit */
		467	if ((val << 2) < val)
		468	val = ULONG_MAX;
		469	else
		470	val <<= 2;
		471
814	if (val == 64) /* Skip zero entry. */	472	if (val == 64) /* Skip zero entry. */
815	val <<= 2;	473	val <<= 2;
816	/* For zero check. */	474	/* For zero check. */
@@ -842,11 +500,16 @@ static noinline void check_find(struct maple_tree *mt) · 25 unmodified lines
842	mas_for_each(&mas, entry, ULONG_MAX) {	500	mas_for_each(&mas, entry, ULONG_MAX) {
843	if (val == 64)	501	if (val == 64)
844	MT_BUG_ON(mt, entry != XA_ZERO_ENTRY);	502	MT_BUG_ON(mt, entry != XA_ZERO_ENTRY);
845	else if (val == 4398046511104)	503	else if (val == top)
846	MT_BUG_ON(mt, entry != xa_mk_value(ULONG_MAX & LONG_MAX));	504	MT_BUG_ON(mt, entry != xa_mk_value(LONG_MAX));
847	else	505	else
848	MT_BUG_ON(mt, xa_mk_value(val) != entry);	506	MT_BUG_ON(mt, xa_mk_value(val) != entry);
849	val <<= 2;	507
		508	/* Workaround for 32bit */
		509	if ((val << 2) < val)
		510	val = ULONG_MAX;
		511	else
		512	val <<= 2;
850		513
851	/* For zero check. */	514	/* For zero check. */
852	if (!val)	515	if (!val)
@@ -951,36548 +614,1350 @@ static noinline void check_find_2(struct maple_tree *mt) · 98 unmodified lines
951	/MT_BUG_ON(mt, !mtree_empty(mt)); /	614	/MT_BUG_ON(mt, !mtree_empty(mt)); /
952	}	615	}
953		616
954	#define erase_ptr(i) entry[i%2]
955	#define erase_check_load(mt, i) check_load(mt, set[i], entry[i%2])
956	#define erase_check_insert(mt, i) check_insert(mt, set[i], entry[i%2])
957	#define erase_check_erase(mt, i) check_erase(mt, set[i], entry[i%2])
958		617
959	static noinline void check_erase_testset(struct maple_tree *mt)	618	#if defined(CONFIG_64BIT)
		619	static noinline void check_alloc_rev_range(struct maple_tree *mt)
960	{	620	{
961	unsigned long set[] = { 5015, 5014, 5017, 25, 1000,
962	1001, 1002, 1003, 1005, 0,
963	6003, 6002, 6008, 6012, 6015,
964	7003, 7002, 7008, 7012, 7015,
965	8003, 8002, 8008, 8012, 8015,
966	9003, 9002, 9008, 9012, 9015,
967	10003, 10002, 10008, 10012, 10015,
968	11003, 11002, 11008, 11012, 11015,
969	12003, 12002, 12008, 12012, 12015,
970	13003, 13002, 13008, 13012, 13015,
971	14003, 14002, 14008, 14012, 14015,
972	15003, 15002, 15008, 15012, 15015,
973	};
974
975
976	void *ptr = &set;
977	void *entry[2] = { ptr, mt };
978	void *root_node;
979
980
981	rcu_register_thread();
982	mt_set_in_rcu(mt);
983	for (int i = 0; i < 4; i++)
984	erase_check_insert(mt, i);
985	for (int i = 0; i < 4; i++)
986	erase_check_load(mt, i);
987
988	mt_set_non_kernel(2);
989	erase_check_erase(mt, 1);
990	erase_check_load(mt, 0);
991	check_load(mt, set[1], NULL);
992	for (int i = 2; i < 4; i++)
993	erase_check_load(mt, i);
994
995
996	erase_check_erase(mt, 2);
997	erase_check_load(mt, 0);
998	check_load(mt, set[1], NULL);
999	check_load(mt, set[2], NULL);
1000
1001	erase_check_insert(mt, 1);
1002	erase_check_insert(mt, 2);
1003
1004	for (int i = 0; i < 4; i++)
1005	erase_check_load(mt, i);
1006
1007	/* Check erase and load without an allocation. */
1008	erase_check_load(mt, 3);
1009	erase_check_erase(mt, 1);
1010	erase_check_load(mt, 0);
1011	check_load(mt, set[1], NULL);
1012	for (int i = 2; i < 4; i++)
1013	erase_check_load(mt, i);
1014
1015	/*	621	/*
1016	* Set the newly erased node. This will produce a different allocated	622	* Generated by:
1017	* node to avoid busy slots.	623	* cat /proc/self/maps \| awk '{print $1}'\|
		624	* awk -F "-" '{printf "0x%s, 0x%s, ", $1, $2}'
1018	*/	625	*/
1019	root_node = mt->ma_root;
1020	erase_check_insert(mt, 1);
1021
1022	erase_check_load(mt, 0);
1023	check_load(mt, 5016, NULL);
1024	erase_check_load(mt, 1);
1025	check_load(mt, 5013, NULL);
1026	erase_check_load(mt, 2);
1027	check_load(mt, 5018, NULL);
1028	erase_check_load(mt, 3);
1029
1030	erase_check_erase(mt, 2); /* erase 5017 to check append */
1031	erase_check_load(mt, 0);
1032	check_load(mt, 5016, NULL);
1033	erase_check_load(mt, 1);
1034	check_load(mt, 5013, NULL);
1035	check_load(mt, set[2], NULL);
1036	check_load(mt, 5018, NULL);
1037
1038	erase_check_load(mt, 3);
1039
1040	root_node = mt->ma_root;
1041	erase_check_insert(mt, 2);
1042
1043	erase_check_load(mt, 0);
1044	check_load(mt, 5016, NULL);
1045	erase_check_load(mt, 1);
1046	check_load(mt, 5013, NULL);
1047	erase_check_load(mt, 2);
1048	check_load(mt, 5018, NULL);
1049	erase_check_load(mt, 3);
1050		626
1051	mt_set_non_kernel(1);	627	unsigned long range[] = {
1052	erase_check_erase(mt, 2); /* erase 5017 to check append */	628	/* Inclusive , Exclusive. */
1053	erase_check_load(mt, 0);	629	0x565234af2000, 0x565234af4000,
1054	check_load(mt, 5016, NULL);	630	0x565234af4000, 0x565234af9000,
1055	check_load(mt, set[2], NULL);	631	0x565234af9000, 0x565234afb000,
1056	erase_check_erase(mt, 0); /* erase 5015 to check append */	632	0x565234afc000, 0x565234afd000,
1057	check_load(mt, set[0], NULL);	633	0x565234afd000, 0x565234afe000,
1058	check_load(mt, 5016, NULL);	634	0x565235def000, 0x565235e10000,
1059	erase_check_insert(mt, 4); /* 1000 < Should not split. */	635	0x7f36d4bfd000, 0x7f36d4ee2000,
1060	check_load(mt, set[0], NULL);	636	0x7f36d4ee2000, 0x7f36d4f04000,
1061	check_load(mt, 5016, NULL);	637	0x7f36d4f04000, 0x7f36d504c000,
1062	erase_check_load(mt, 1);	638	0x7f36d504c000, 0x7f36d5098000,
1063	check_load(mt, 5013, NULL);	639	0x7f36d5098000, 0x7f36d5099000,
1064	check_load(mt, set[2], NULL);	640	0x7f36d5099000, 0x7f36d509d000,
1065	check_load(mt, 5018, NULL);	641	0x7f36d509d000, 0x7f36d509f000,
1066	erase_check_load(mt, 4);	642	0x7f36d509f000, 0x7f36d50a5000,
1067	check_load(mt, 999, NULL);	643	0x7f36d50b9000, 0x7f36d50db000,
1068	check_load(mt, 1001, NULL);	644	0x7f36d50db000, 0x7f36d50dc000,
1069	erase_check_load(mt, 4);	645	0x7f36d50dc000, 0x7f36d50fa000,
1070	if (mt_in_rcu(mt))	646	0x7f36d50fa000, 0x7f36d5102000,
1071	MT_BUG_ON(mt, root_node == mt->ma_root);	647	0x7f36d5102000, 0x7f36d5103000,
1072	else	648	0x7f36d5103000, 0x7f36d5104000,
1073	MT_BUG_ON(mt, root_node != mt->ma_root);	649	0x7f36d5104000, 0x7f36d5105000,
		650	0x7fff5876b000, 0x7fff5878d000,
		651	0x7fff5878e000, 0x7fff58791000,
		652	0x7fff58791000, 0x7fff58793000,
		653	};
1074		654
1075	/* Should not have split. */	655	unsigned long holes[] = {
1076	MT_BUG_ON(mt, !mte_is_leaf(mt->ma_root));	656	/*
		657	* Note: start of hole is INCLUSIVE
		658	* end of hole is EXCLUSIVE
		659	* (opposite of the above table.)
		660	* Start of hole, end of hole, size of hole (+1)
		661	*/
		662	0x565234afb000, 0x565234afc000, 0x1000,
		663	0x565234afe000, 0x565235def000, 0x12F1000,
		664	0x565235e10000, 0x7f36d4bfd000, 0x28E49EDED000,
		665	};
1077		666
		667	/*
		668	* req_range consists of 4 values.
		669	* 1. min index
		670	* 2. max index
		671	* 3. size
		672	* 4. number that should be returned.
		673	* 5. return value
		674	*/
		675	unsigned long req_range[] = {
		676	0x565234af9000, /* Min */
		677	0x7fff58791000, /* Max */
		678	0x1000, /* Size */
		679	0x7fff5878d << 12, /* First rev hole of size 0x1000 */
		680	0, /* Return value success. */
1078		681
1079	/* Coalesce testing */	682	0x0, /* Min */
1080	erase_check_insert(mt, 0);	683	0x565234AF1 << 12, /* Max */
1081	erase_check_insert(mt, 2);	684	0x3000, /* Size */
		685	0x565234AEE << 12, /* max - 3. */
		686	0, /* Return value success. */
1082		687
1083	for (int i = 5; i < 25; i++) {	688	0x0, /* Min */
1084	erase_check_insert(mt, i);	689	-1, /* Max */
1085	for (int j = i; j >= 0; j--)	690	0x1000, /* Size */
1086	erase_check_load(mt, j);	691	562949953421311 << 12,/* First rev hole of size 0x1000 */
1087	}	692	0, /* Return value success. */
1088		693
1089	erase_check_erase(mt, 14); /6015 /	694	0x0, /* Min */
1090	for (int i = 0; i < 25; i++) {	695	0x7F36D510A << 12, /* Max */
1091	if (i == 14)	696	0x4000, /* Size */
1092	check_load(mt, set[i], NULL);	697	0x7F36D5106 << 12, /* First rev hole of size 0x4000 */
1093	else	698	0, /* Return value success. */
1094	erase_check_load(mt, i);
1095	}
1096	erase_check_erase(mt, 16); /7002 /
1097	for (int i = 0; i < 25; i++) {
1098	if (i == 16 \|\| i == 14)
1099	check_load(mt, set[i], NULL);
1100	else
1101	erase_check_load(mt, i);
1102	}
1103		699
		700	/* Ascend test. */
		701	0x0,
		702	34148798629 << 12,
		703	19 << 12,
		704	34148797418 << 12,
		705	0x0,
1104		706
1105	mt_set_non_kernel(1);	707	/* Too big test. */
1106	erase_check_erase(mt, 13); /6012 /	708	0x0,
1107	for (int i = 0; i < 25; i++) {	709	18446744073709551615UL,
1108	if (i == 16 \|\| i == 14 \|\| i == 13)	710	562915594369134UL << 12,
1109	check_load(mt, set[i], NULL);	711	0x0,
1110	else	712	-EBUSY,
1111	erase_check_load(mt, i);
1112	}
1113		713
1114	erase_check_erase(mt, 15); /7003 /	714	};
1115	for (int i = 0; i < 25; i++) {
1116	if (i <= 16 && i >= 13)
1117	check_load(mt, set[i], NULL);
1118	else
1119	erase_check_load(mt, i);
1120	}
1121		715
1122	mt_set_non_kernel(2);	716	int i, range_count = ARRAY_SIZE(range);
1123	erase_check_erase(mt, 17); /7008 should* cause coalesce. */	717	int req_range_count = ARRAY_SIZE(req_range);
1124	for (int i = 0; i < 25; i++) {	718	unsigned long min = 0;
1125	if (i <= 17 && i >= 13)
1126	check_load(mt, set[i], NULL);
1127	else
1128	erase_check_load(mt, i);
1129	}
1130		719
1131	erase_check_erase(mt, 18); /7012 /	720	MA_STATE(mas, mt, 0, 0);
1132	for (int i = 0; i < 25; i++) {
1133	if (i <= 18 && i >= 13)
1134	check_load(mt, set[i], NULL);
1135	else
1136	erase_check_load(mt, i);
1137	}
1138		721
1139	mt_set_non_kernel(2);	722	mtree_store_range(mt, MTREE_ALLOC_MAX, ULONG_MAX, XA_ZERO_ENTRY,
1140	erase_check_erase(mt, 19); /7015 /	723	GFP_KERNEL);
1141	for (int i = 0; i < 25; i++) {	724	#define DEBUG_REV_RANGE 0
1142	if (i <= 19 && i >= 13)	725	for (i = 0; i < range_count; i += 2) {
1143	check_load(mt, set[i], NULL);	726	/* Inclusive, Inclusive (with the -1) */
1144	else
1145	erase_check_load(mt, i);
1146	}
1147		727
1148	erase_check_erase(mt, 20); /8003 /	728	#if DEBUG_REV_RANGE
1149	for (int i = 0; i < 25; i++) {	729	pr_debug("\t%s: Insert %lu-%lu\n", __func__, range[i] >> 12,
1150	if (i <= 20 && i >= 13)	730	(range[i + 1] >> 12) - 1);
1151	check_load(mt, set[i], NULL);	731	#endif
1152	else	732	check_insert_range(mt, range[i] >> 12, (range[i + 1] >> 12) - 1,
1153	erase_check_load(mt, i);	733	xa_mk_value(range[i] >> 12), 0);
		734	mt_validate(mt);
1154	}	735	}
1155		736
1156	erase_check_erase(mt, 21); /8002 /
1157	for (int i = 0; i < 25; i++) {
1158	if (i <= 21 && i >= 13)
1159	check_load(mt, set[i], NULL);
1160	else
1161	erase_check_load(mt, i);
1162	}
1163		737
1164	mt_set_non_kernel(2);	738	mas_lock(&mas);
1165	erase_check_erase(mt, 22); /8008 /	739	for (i = 0; i < ARRAY_SIZE(holes); i += 3) {
1166	for (int i = 0; i < 25; i++) {	740	#if DEBUG_REV_RANGE
1167	if (i <= 22 && i >= 13)	741	pr_debug("Search from %lu-%lu for gap %lu should be at %lu\n",
1168	check_load(mt, set[i], NULL);	742	min, holes[i+1]>>12, holes[i+2]>>12,
1169	else	743	holes[i] >> 12);
1170	erase_check_load(mt, i);	744	#endif
		745	MT_BUG_ON(mt, mas_empty_area_rev(&mas, min,
		746	holes[i+1] >> 12,
		747	holes[i+2] >> 12));
		748	#if DEBUG_REV_RANGE
		749	pr_debug("Found %lu %lu\n", mas.index, mas.last);
		750	pr_debug("gap %lu %lu\n", (holes[i] >> 12),
		751	(holes[i+1] >> 12));
		752	#endif
		753	MT_BUG_ON(mt, mas.last + 1 != (holes[i+1] >> 12));
		754	MT_BUG_ON(mt, mas.index != (holes[i+1] >> 12) - (holes[i+2] >> 12));
		755	min = holes[i+1] >> 12;
		756	mas_reset(&mas);
1171	}	757	}
1172	for (int i = 23; i < 25; i++)
1173	erase_check_erase(mt, i);
1174		758
1175	for (int i = 0; i < 25; i++) {	759	mas_unlock(&mas);
1176	if (i <= 25 && i >= 13)	760	for (i = 0; i < req_range_count; i += 5) {
1177	check_load(mt, set[i], NULL);	761	#if DEBUG_REV_RANGE
1178	else	762	pr_debug("\tReverse request between %lu-%lu size %lu, should get %lu\n",
1179	erase_check_load(mt, i);	763	req_range[i] >> 12,
		764	(req_range[i + 1] >> 12) - 1,
		765	req_range[i+2] >> 12,
		766	req_range[i+3] >> 12);
		767	#endif
		768	check_mtree_alloc_rrange(mt,
		769	req_range[i] >> 12, /* start */
		770	req_range[i+1] >> 12, /* end */
		771	req_range[i+2] >> 12, /* size */
		772	req_range[i+3] >> 12, /* expected address */
		773	req_range[i+4], /* expected return */
		774	xa_mk_value(req_range[i] >> 12)); /* pointer */
		775	mt_validate(mt);
1180	}	776	}
1181		777
1182	/* Shrinking tree test. */	778	mt_set_non_kernel(1);
		779	mtree_erase(mt, 34148798727); /* create a deleted range. */
		780	check_mtree_alloc_rrange(mt, 0, 34359052173, 210253414,
		781	34148798725, 0, mt);
1183		782
1184	for (int i = 13; i < ARRAY_SIZE(set); i++)	783	mtree_destroy(mt);
1185	erase_check_insert(mt, i);	784	}
1186		785
1187	mt_set_non_kernel(99);	786	static noinline void check_alloc_range(struct maple_tree *mt)
1188	for (int i = 18; i < ARRAY_SIZE(set); i++) {
1189	erase_check_erase(mt, i);
1190	for (int j = 0; j < ARRAY_SIZE(set); j++) {
1191	if (j < 18 \|\| j > i)
1192	erase_check_load(mt, j);
1193	else
1194	check_load(mt, set[j], NULL);
1195	}
1196	}
1197	mt_set_non_kernel(35);
1198	for (int i = 0; i < 18; i++) {
1199	erase_check_erase(mt, i);
1200	for (int j = 0; j < ARRAY_SIZE(set); j++) {
1201	if (j < 18 && j > i)
1202	erase_check_load(mt, j);
1203	else
1204	check_load(mt, set[j], NULL);
1205	}
1206	}
1207	erase_check_insert(mt, 8);
1208	erase_check_insert(mt, 9);
1209	erase_check_erase(mt, 8);
1210	rcu_unregister_thread();
1211	}
1212
1213	#define erase_check_store_range(mt, a, i, ptr) mtree_test_store_range(mt, \
1214	a[(i)], a[(i + 1)], ptr)
1215	#define STORE 1
1216	#define SNULL 2
1217	#define ERASE 3
1218	#define ec_type_str(x) \
1219	(((x) == STORE) ? \
1220	"STORE" : \
1221	(((x) == SNULL) ? \
1222	"SNULL" : "ERASE") \
1223	)
1224	#define check_erase2_debug 0
1225	void mas_next(struct ma_state mas, unsigned long max);
1226
1227	/* Calculate the overwritten entries. */
1228	int mas_ce2_over_count(struct ma_state mas_start, struct ma_state mas_end,
1229	void *s_entry, unsigned long s_min,
1230	void *e_entry, unsigned long e_max,
1231	unsigned long *set, int i, bool null_entry)
1232	{
1233	int count = 0, span = 0;
1234	unsigned long retry = 0;
1235	void *entry;
1236	struct ma_state tmp;
1237
1238
1239	/* count slots */
1240	memcpy(&tmp, mas_start, sizeof(tmp));
1241	entry = mas_next(&tmp, mas_end->last);
1242	while (entry) {
1243	BUG_ON(retry > 50); /* stop infinite retry on testing. */
1244	if (xa_is_zero(s_entry)) {
1245	retry++;
1246	continue;
1247	}
1248	count++;
1249	span++;
1250	entry = mas_next(&tmp, mas_end->last);
1251	}
1252
1253	if (null_entry) {
1254	/* Check splitting end. */
1255	if (e_entry && (e_max > mas_end->last))
1256	count--;
1257
1258	/* check overwrite of entire start */
1259	if (s_entry && (s_min == mas_start->index))
1260	count++;
1261	} else { /* !null_entry (store) */
1262	bool esplit = e_max > mas_end->last;
1263	bool ssplit = s_min != mas_start->index;
1264
1265	if (s_entry && e_entry) {
1266	if (esplit && ssplit)
1267	count--;
1268	else if (ssplit)
1269	count--;
1270	else if (esplit) {
1271	if (span)
1272	count--;
1273	}
1274	} else if (s_entry && !e_entry) {
1275	if (ssplit)
1276	count--;
1277	} else if (!s_entry && e_entry) {
1278	if (esplit)
1279	count--;
1280	count--;
1281	} else {
1282	count--;
1283	}
1284	}
1285	return count;
1286	}
1287
1288	/*
1289	* mas_node_walk() - Walk a maple node to offset of the index.
1290	* @mas: The maple state
1291	* @type: The maple node type
1292	* @*range_min: Pointer to store the minimum range of the offset
1293	* @*range_max: Pointer to store the maximum range of the offset
1294	*
1295	* The offset will be stored in the maple state.
1296	*
1297	*/
1298	static inline void mas_node_walk(struct ma_state mas, struct maple_node node,
1299	enum maple_type type, unsigned long *range_min,
1300	unsigned long *range_max)
1301
1302	{
1303	unsigned long *pivots;
1304	unsigned char count;
1305	unsigned long prev, max;
1306	unsigned char offset;
1307	unsigned long index;
1308
1309	if (unlikely(ma_is_dense(type))) {
1310	(range_max) = (range_min) = mas->index;
1311	if (unlikely(ma_dead_node(node)))
1312	return;
1313
1314	mas->offset = mas->index = mas->min;
1315	return;
1316	}
1317
1318	pivots = ma_pivots(node, type);
1319	max = pivots[0];
1320	if (unlikely(ma_dead_node(node)))
1321	return;
1322
1323	offset = 0;
1324	prev = mas->min;
1325	index = mas->index;
1326	if (unlikely(index <= max))
1327	goto offset_zero;
1328
1329	count = mt_pivots[type];
1330	while (++offset < count) {
1331	prev = max;
1332	max = pivots[offset];
1333	if (unlikely(ma_dead_node(node)))
1334	return;
1335
1336	if (index <= max)
1337	goto offset_found;
1338	else if (unlikely(!max))
1339	goto mas_max;
1340	}
1341
1342	prev = max;
1343	mas_max:
1344	max = mas->max;
1345	offset_found:
1346	prev++;
1347	offset_zero:
1348	mas->offset = offset;
1349	if (ma_is_leaf(type)) {
1350	*range_max = max;
1351	*range_min = prev;
1352	} else {
1353	mas->max = max;
1354	mas->min = prev;
1355	}
1356	}
1357
1358	/*
1359	* mas_descend_walk(): Locates a value and sets the mas->node and slot
1360	* accordingly. range_min and range_max are set to the range which the entry is
1361	* valid.
1362	* @mas: The maple state
1363	* @*range_min: A pointer to store the minimum of the range
1364	* @*range_max: A pointer to store the maximum of the range
1365	*
1366	* Check mas->node is still valid on return of any value.
1367	*
1368	* Return: true if pointing to a valid node and offset. False otherwise.
1369	*/
1370	static inline bool mas_descend_walk(struct ma_state *mas,
1371	unsigned long range_min, unsigned long range_max)
1372	{
1373	struct maple_enode *next;
1374	struct maple_node *node;
1375	enum maple_type type;
1376
1377	next = mas->node;
1378	while (true) {
1379	node = mte_to_node(next);
1380	type = mte_node_type(next);
1381	mas_node_walk(mas, node, type, range_min, range_max);
1382	next = mas_slot(mas, ma_slots(node, type), mas->offset);
1383	if (unlikely(ma_dead_node(node)))
1384	return false;
1385
1386	if (unlikely(ma_is_leaf(type)))
1387	return true;
1388
1389	/* Descend. */
1390	mas->node = next;
1391	}
1392	return false;
1393	}
1394
1395	/*
1396	* mas_tree_walk() - Walk to @mas->index and set the range values.
1397	* @mas: The maple state.
1398	* @*range_min: The minimum range to be set.
1399	* @*range_max: The maximum range to be set.
1400	*
1401	* Ranges are only valid if there is a valid entry at @mas->index.
1402	*
1403	* Return: True if a value exists, false otherwise.
1404	*/
1405	static inline bool mas_tree_walk(struct ma_state mas, unsigned long range_min,
1406	unsigned long *range_max)
1407	{	787	{
1408	bool ret;	788	/*
1409		789	* Generated by:
1410	retry:	790	* cat /proc/self/maps\|awk '{print $1}'\|
1411	ret = false;	791	* awk -F "-" '{printf "0x%s, 0x%s, ", $1, $2}'
1412	mas_start(mas);	792	*/
1413	if (mas_is_none(mas))
1414	goto not_found;
1415
1416	if (mas_is_ptr(mas)) {
1417	range_min = range_max = 0;
1418	if (!mas->index)
1419	return true;
1420
1421	goto not_found;
1422	}
1423
1424	ret = mas_descend_walk(mas, range_min, range_max);
1425	if (unlikely(mte_dead_node(mas->node))) {
1426	mas->node = MAS_START;
1427	goto retry;
1428	}
1429
1430	return ret;
1431		793
1432	not_found:	794	unsigned long range[] = {
1433	mas->offset = MAPLE_NODE_SLOTS;	795	/* Inclusive , Exclusive. */
1434	return false;	796	0x565234af2000, 0x565234af4000,
1435	}	797	0x565234af4000, 0x565234af9000,
		798	0x565234af9000, 0x565234afb000,
		799	0x565234afc000, 0x565234afd000,
		800	0x565234afd000, 0x565234afe000,
		801	0x565235def000, 0x565235e10000,
		802	0x7f36d4bfd000, 0x7f36d4ee2000,
		803	0x7f36d4ee2000, 0x7f36d4f04000,
		804	0x7f36d4f04000, 0x7f36d504c000,
		805	0x7f36d504c000, 0x7f36d5098000,
		806	0x7f36d5098000, 0x7f36d5099000,
		807	0x7f36d5099000, 0x7f36d509d000,
		808	0x7f36d509d000, 0x7f36d509f000,
		809	0x7f36d509f000, 0x7f36d50a5000,
		810	0x7f36d50b9000, 0x7f36d50db000,
		811	0x7f36d50db000, 0x7f36d50dc000,
		812	0x7f36d50dc000, 0x7f36d50fa000,
		813	0x7f36d50fa000, 0x7f36d5102000,
		814	0x7f36d5102000, 0x7f36d5103000,
		815	0x7f36d5103000, 0x7f36d5104000,
		816	0x7f36d5104000, 0x7f36d5105000,
		817	0x7fff5876b000, 0x7fff5878d000,
		818	0x7fff5878e000, 0x7fff58791000,
		819	0x7fff58791000, 0x7fff58793000,
		820	};
		821	unsigned long holes[] = {
		822	/* Start of hole, end of hole, size of hole (+1) */
		823	0x565234afb000, 0x565234afc000, 0x1000,
		824	0x565234afe000, 0x565235def000, 0x12F1000,
		825	0x565235e10000, 0x7f36d4bfd000, 0x28E49EDED000,
		826	};
1436		827
1437	static inline void mas_range_load(struct ma_state mas,	828	/*
1438	unsigned long range_min, unsigned long range_max)	829	* req_range consists of 4 values.
		830	* 1. min index
		831	* 2. max index
		832	* 3. size
		833	* 4. number that should be returned.
		834	* 5. return value
		835	*/
		836	unsigned long req_range[] = {
		837	0x565234af9000, /* Min */
		838	0x7fff58791000, /* Max */
		839	0x1000, /* Size */
		840	0x565234afb000, /* First hole in our data of size 1000. */
		841	0, /* Return value success. */
1439		842
1440	{	843	0x0, /* Min */
1441	void *entry = NULL;	844	0x7fff58791000, /* Max */
1442	unsigned long index = mas->index;	845	0x1F00, /* Size */
		846	0x0, /* First hole in our data of size 2000. */
		847	0, /* Return value success. */
1443		848
1444	if (mas_is_none(mas) \|\| mas_is_paused(mas))	849	/* Test ascend. */
1445	mas->node = MAS_START;	850	34148797436 << 12, /* Min */
1446	retry:	851	0x7fff587AF000, /* Max */
1447	if (mas_tree_walk(mas, range_min, range_max))	852	0x3000, /* Size */
1448	if (unlikely(mas->node == MAS_ROOT))	853	34148798629 << 12, /* Expected location */
1449	return mas_root(mas);	854	0, /* Return value success. */
1450		855
1451	if (likely(mas->offset != MAPLE_NODE_SLOTS))	856	/* Test failing. */
1452	entry = mas_get_slot(mas, mas->offset);	857	34148798623 << 12, /* Min */
		858	34148798683 << 12, /* Max */
		859	0x15000, /* Size */
		860	0, /* Expected location */
		861	-EBUSY, /* Return value failed. */
1453		862
1454	if (mas_dead_node(mas, index))	863	/* Test filling entire gap. */
1455	goto retry;	864	34148798623 << 12, /* Min */
		865	0x7fff587AF000, /* Max */
		866	0x10000, /* Size */
		867	34148798632 << 12, /* Expected location */
		868	0, /* Return value success. */
1456		869
1457	return entry;	870	/* Test walking off the end of root. */
1458	}	871	0, /* Min */
1459	static noinline void check_erase2_testset(struct maple_tree *mt,	872	-1, /* Max */
1460	unsigned long *set, unsigned long size)	873	-1, /* Size */
1461	{	874	0, /* Expected location */
1462	int entry_count = 0;	875	-EBUSY, /* Return value failure. */
1463	int check = 0;
1464	void *foo;
1465	unsigned long addr = 0;
1466	void s_entry = NULL, e_entry = NULL;
1467		876
		877	/* Test looking for too large a hole across entire range. */
		878	0, /* Min */
		879	-1, /* Max */
		880	4503599618982063UL << 12, /* Size */
		881	34359052178 << 12, /* Expected location */
		882	-EBUSY, /* Return failure. */
		883	};
		884	int i, range_count = ARRAY_SIZE(range);
		885	int req_range_count = ARRAY_SIZE(req_range);
		886	unsigned long min = 0x565234af2000;
1468	MA_STATE(mas, mt, 0, 0);	887	MA_STATE(mas, mt, 0, 0);
1469		888
1470	for (int i = 0; i < size; i += 3) {	889	mtree_store_range(mt, MTREE_ALLOC_MAX, ULONG_MAX, XA_ZERO_ENTRY,
1471	unsigned long s_min, s_max;	890	GFP_KERNEL);
1472	unsigned long e_min, e_max;	891	for (i = 0; i < range_count; i += 2) {
1473	void *value = NULL;	892	#define DEBUG_ALLOC_RANGE 0
1474		893	#if DEBUG_ALLOC_RANGE
1475	MA_STATE(mas_start, mt, set[i+1], set[i+1]);	894	pr_debug("\tInsert %lu-%lu\n", range[i] >> 12,
1476	MA_STATE(mas_end, mt, set[i+2], set[i+2]);	895	(range[i + 1] >> 12) - 1);
1477	mt_set_non_kernel(127);
1478	#if check_erase2_debug
1479	pr_err("%s: %d %s %lu - %lu\n", __func__, i,
1480	ec_type_str(set[i]),
1481	set[i+1], set[i+2]);
1482	#endif
1483	s_entry = mas_range_load(&mas_start, &s_min, &s_max);
1484	e_entry = mas_range_load(&mas_end, &e_min, &e_max);
1485
1486	switch (set[i]) {
1487	case SNULL:
1488	if ((s_min == set[i+1]) && (s_max == set[i+2])) {
1489	if (s_entry)
1490	entry_count--;
1491	} else if ((s_min != set[i+1]) && (s_max != set[i+2])) {
1492	entry_count++;
1493	} else if ((mas_start.node != mas_end.node) \|\|
1494	(mas_start.offset != mas_end.offset)) {
1495	entry_count -=
1496	mas_ce2_over_count(&mas_start, &mas_end,
1497	s_entry, s_min,
1498	e_entry, e_max, set, i,
1499	true);
1500	}
1501
1502
1503	erase_check_store_range(mt, set, i + 1, value);
1504	break;
1505	case STORE:
1506	value = xa_mk_value(set[i + 1]);
1507	if (mas_start.offset > mt_slot_count(mas_start.node)) {
1508	entry_count++; /* appending an entry. */
1509	} else if ((s_min == e_min) && (s_max == e_max)) {
1510	if (!entry_count)
1511	entry_count++;
1512
1513	else if (s_entry) {
1514	if (e_max > mas_end.last)
1515	entry_count++;
1516
1517	if (s_min < mas_start.index)
1518	entry_count++;
1519
1520	} else {
1521	entry_count++;
1522	}
1523	} else {
1524	entry_count -=
1525	mas_ce2_over_count(&mas_start, &mas_end,
1526	s_entry, s_min,
1527	e_entry, e_max, set, i,
1528	false);
1529	}
1530
1531	erase_check_store_range(mt, set, i + 1, value);
1532	break;
1533	case ERASE:
1534	if (!s_entry)
1535	break;
1536	check_erase(mt, set[i+1], xa_mk_value(set[i+1]));
1537	entry_count--;
1538	break;
1539	}
1540	mt_validate(mt);
1541	if (entry_count)
1542	MT_BUG_ON(mt, !mt_height(mt));
1543	#if check_erase2_debug > 1
1544	mt_dump(mt);	896	mt_dump(mt);
1545	#endif	897	#endif
1546	#if check_erase2_debug	898	check_insert_range(mt, range[i] >> 12, (range[i + 1] >> 12) - 1,
1547	pr_err("Done\n");	899	xa_mk_value(range[i] >> 12), 0);
1548	#endif	900	mt_validate(mt);
		901	}
1549		902
1550	check = 0;
1551	addr = 0;
1552	mt_for_each(mt, foo, addr, ULONG_MAX) {
1553	check++;
1554	#if check_erase2_debug > 2
1555	pr_err("mt: %lu -> %p (%d)\n", addr+1, foo, check);
1556	#endif
1557	if (check > entry_count)
1558	break;
1559	}
1560		903
1561	#if check_erase2_debug > 2
1562	pr_err("mt_for_each %d and count %d\n", check, entry_count);
1563	#endif
1564		904
1565	MT_BUG_ON(mt, check != entry_count);	905	mas_lock(&mas);
		906	for (i = 0; i < ARRAY_SIZE(holes); i += 3) {
1566		907
1567	check = 0;	908	#if DEBUG_ALLOC_RANGE
1568	addr = 0;	909	pr_debug("\tGet empty %lu-%lu size %lu (%lx-%lx)\n", min >> 12,
		910	holes[i+1] >> 12, holes[i+2] >> 12,
		911	min, holes[i+1]);
		912	#endif
		913	MT_BUG_ON(mt, mas_empty_area(&mas, min >> 12,
		914	holes[i+1] >> 12,
		915	holes[i+2] >> 12));
		916	MT_BUG_ON(mt, mas.index != holes[i] >> 12);
		917	min = holes[i+1];
1569	mas_reset(&mas);	918	mas_reset(&mas);
1570	mas.index = 0;	919	}
1571	rcu_read_lock();	920	mas_unlock(&mas);
1572	mas_for_each(&mas, foo, ULONG_MAX) {	921	for (i = 0; i < req_range_count; i += 5) {
1573	if (xa_is_zero(foo)) {	922	#if DEBUG_ALLOC_RANGE
1574	if (addr == mas.index) {	923	pr_debug("\tTest %d: %lu-%lu size %lu expected %lu (%lu-%lu)\n",
1575	mt_dump(mas.tree);	924	i/5, req_range[i] >> 12, req_range[i + 1] >> 12,
1576	pr_err("retry failed %lu - %lu\n",	925	req_range[i + 2] >> 12, req_range[i + 3] >> 12,
1577	mas.index, mas.last);	926	req_range[i], req_range[i+1]);
1578	MT_BUG_ON(mt, 1);
1579	}
1580	addr = mas.index;
1581	continue;
1582	}
1583	#if check_erase2_debug > 2
1584	pr_err("mas: %lu -> %p\n", mas.index, foo);
1585	#endif	927	#endif
1586	check++;	928	check_mtree_alloc_range(mt,
1587	if (check > entry_count)	929	req_range[i] >> 12, /* start */
1588	break;	930	req_range[i+1] >> 12, /* end */
1589	}	931	req_range[i+2] >> 12, /* size */
1590	rcu_read_unlock();	932	req_range[i+3] >> 12, /* expected address */
1591	#if check_erase2_debug > 2	933	req_range[i+4], /* expected return */
1592	pr_err("mas_for_each %d and count %d\n", check, entry_count);	934	xa_mk_value(req_range[i] >> 12)); /* pointer */
1593	mt_validate(mt);	935	mt_validate(mt);
		936	#if DEBUG_ALLOC_RANGE
		937	mt_dump(mt);
1594	#endif	938	#endif
1595
1596	MT_BUG_ON(mt, check != entry_count);
1597
1598	MT_BUG_ON(mt, mtree_load(mas.tree, 0) != NULL);
1599	}	939	}
1600	}
1601		940
		941	mtree_destroy(mt);
		942	}
		943	#endif
1602		944
1603	/* These tests were pulled from kvm tests. */	945	static noinline void check_ranges(struct maple_tree *mt)
1604	static noinline void check_erase2_sets(struct maple_tree *mt)
1605	{	946	{
1606	void *entry;	947	int i, val, val2;
1607	unsigned long start = 0;	948	unsigned long r[] = {
1608	unsigned long set[] = {	949	10, 15,
1609	STORE, 140737488347136, 140737488351231,	950	20, 25,
1610	STORE, 140721266458624, 140737488351231,	951	17, 22, /* Overlaps previous range. */
1611	ERASE, 140721266458624, 140737488351231,	952	9, 1000, /* Huge. */
1612	STORE, 140721266458624, 140721266462719,	953	100, 200,
1613	STORE, 94735788949504, 94735789121535,	954	45, 168,
1614	ERASE, 94735788949504, 94735789121535,	955	118, 128,
1615	STORE, 94735788949504, 94735788965887,	956	};
1616	STORE, 94735788965888, 94735789121535,
1617	ERASE, 94735788965888, 94735789121535,
1618	STORE, 94735788965888, 94735789068287,
1619	STORE, 94735789068288, 94735789109247,
1620	STORE, 94735789109248, 94735789121535,
1621	STORE, 140253902692352, 140253902864383,
1622	ERASE, 140253902692352, 140253902864383,
1623	STORE, 140253902692352, 140253902696447,
1624	STORE, 140253902696448, 140253902864383,
1625	};
1626	unsigned long set2[] = {
1627	STORE, 140737488347136, 140737488351231,
1628	STORE, 140735933583360, 140737488351231,
1629	ERASE, 140735933583360, 140737488351231,
1630	STORE, 140735933583360, 140735933587455,
1631	STORE, 94811003260928, 94811003432959,
1632	ERASE, 94811003260928, 94811003432959,
1633	STORE, 94811003260928, 94811003277311,
1634	STORE, 94811003277312, 94811003432959,
1635	ERASE, 94811003277312, 94811003432959,
1636	STORE, 94811003277312, 94811003379711,
1637	STORE, 94811003379712, 94811003420671,
1638	STORE, 94811003420672, 94811003432959,
1639	STORE, 140277094653952, 140277094825983,
1640	ERASE, 140277094653952, 140277094825983,
1641	STORE, 140277094653952, 140277094658047,
1642	STORE, 140277094658048, 140277094825983,
1643	ERASE, 140277094658048, 140277094825983,
1644	STORE, 140277094658048, 140277094780927,
1645	STORE, 140277094780928, 140277094813695,
1646	STORE, 140277094813696, 140277094821887,
1647	STORE, 140277094821888, 140277094825983,
1648	STORE, 140735933906944, 140735933911039,
1649	};
1650	unsigned long set3[] = {
1651	STORE, 140737488347136, 140737488351231,
1652	STORE, 140735790264320, 140737488351231,
1653	ERASE, 140735790264320, 140737488351231,
1654	STORE, 140735790264320, 140735790268415,
1655	STORE, 94016597282816, 94016597454847,
1656	ERASE, 94016597282816, 94016597454847,
1657	STORE, 94016597282816, 94016597299199,
1658	STORE, 94016597299200, 94016597454847,
1659	ERASE, 94016597299200, 94016597454847,
1660	STORE, 94016597299200, 94016597401599,
1661	STORE, 94016597401600, 94016597442559,
1662	STORE, 94016597442560, 94016597454847,
1663	STORE, 140496959283200, 140496959455231,
1664	ERASE, 140496959283200, 140496959455231,
1665	STORE, 140496959283200, 140496959287295,
1666	STORE, 140496959287296, 140496959455231,
1667	ERASE, 140496959287296, 140496959455231,
1668	STORE, 140496959287296, 140496959410175,
1669	STORE, 140496959410176, 140496959442943,
1670	STORE, 140496959442944, 140496959451135,
1671	STORE, 140496959451136, 140496959455231,
1672	STORE, 140735791718400, 140735791722495,
1673	STORE, 140735791706112, 140735791718399,
1674	STORE, 47135835713536, 47135835721727,
1675	STORE, 47135835721728, 47135835729919,
1676	STORE, 47135835729920, 47135835893759,
1677	ERASE, 47135835729920, 47135835893759,
1678	STORE, 47135835729920, 47135835742207,
1679	STORE, 47135835742208, 47135835893759,
1680	STORE, 47135835840512, 47135835893759,
1681	STORE, 47135835742208, 47135835840511,
1682	ERASE, 47135835742208, 47135835840511,
1683	STORE, 47135835742208, 47135835840511,
1684	STORE, 47135835885568, 47135835893759,
1685	STORE, 47135835840512, 47135835885567,
1686	ERASE, 47135835840512, 47135835885567,
1687	STORE, 47135835840512, 47135835893759,
1688	ERASE, 47135835840512, 47135835893759,
1689	STORE, 47135835840512, 47135835885567,
1690	STORE, 47135835885568, 47135835893759,
1691	};
1692
1693	unsigned long set4[] = {
1694	STORE, 140737488347136, 140737488351231,
1695	STORE, 140728251703296, 140737488351231,
1696	ERASE, 140728251703296, 140737488351231,
1697	STORE, 140728251703296, 140728251707391,
1698	STORE, 94668429205504, 94668429377535,
1699	ERASE, 94668429205504, 94668429377535,
1700	STORE, 94668429205504, 94668429221887,
1701	STORE, 94668429221888, 94668429377535,
1702	ERASE, 94668429221888, 94668429377535,
1703	STORE, 94668429221888, 94668429324287,
1704	STORE, 94668429324288, 94668429365247,
1705	STORE, 94668429365248, 94668429377535,
1706	STORE, 47646523273216, 47646523445247,
1707	ERASE, 47646523273216, 47646523445247,
1708	STORE, 47646523273216, 47646523277311,
1709	STORE, 47646523277312, 47646523445247,
1710	ERASE, 47646523277312, 47646523445247,
1711	STORE, 47646523277312, 47646523400191,
1712	};
1713
1714	unsigned long set5[] = {
1715	STORE, 140737488347136, 140737488351231,
1716	STORE, 140726874062848, 140737488351231,
1717	ERASE, 140726874062848, 140737488351231,
1718	STORE, 140726874062848, 140726874066943,
1719	STORE, 94248892870656, 94248893042687,
1720	ERASE, 94248892870656, 94248893042687,
1721	STORE, 94248892870656, 94248892887039,
1722	STORE, 94248892887040, 94248893042687,
1723	ERASE, 94248892887040, 94248893042687,
1724	STORE, 94248892887040, 94248892989439,
1725	STORE, 94248892989440, 94248893030399,
1726	STORE, 94248893030400, 94248893042687,
1727	STORE, 47884786266112, 47884786438143,
1728	ERASE, 47884786266112, 47884786438143,
1729	STORE, 47884786266112, 47884786270207,
1730	STORE, 47884786270208, 47884786438143,
1731	ERASE, 47884786270208, 47884786438143,
1732	STORE, 47884786270208, 47884786393087,
1733	STORE, 47884786393088, 47884786425855,
1734	STORE, 47884786425856, 47884786434047,
1735	STORE, 47884786434048, 47884786438143,
1736	STORE, 140726874513408, 140726874517503,
1737	STORE, 140726874501120, 140726874513407,
1738	STORE, 47884786438144, 47884786446335,
1739	STORE, 47884786446336, 47884786454527,
1740	STORE, 47884786454528, 47884786618367,
1741	ERASE, 47884786454528, 47884786618367,
1742	STORE, 47884786454528, 47884786466815,
1743	STORE, 47884786466816, 47884786618367,
1744	STORE, 47884786565120, 47884786618367,
1745	STORE, 47884786466816, 47884786565119,
1746	ERASE, 47884786466816, 47884786565119,
1747	STORE, 47884786466816, 47884786565119,
1748	STORE, 47884786610176, 47884786618367,
1749	STORE, 47884786565120, 47884786610175,
1750	ERASE, 47884786565120, 47884786610175,
1751	STORE, 47884786565120, 47884786618367,
1752	ERASE, 47884786565120, 47884786618367,
1753	STORE, 47884786565120, 47884786610175,
1754	STORE, 47884786610176, 47884786618367,
1755	ERASE, 47884786610176, 47884786618367,
1756	STORE, 47884786610176, 47884786618367,
1757	STORE, 47884786618368, 47884789669887,
1758	STORE, 47884787163136, 47884789669887,
1759	STORE, 47884786618368, 47884787163135,
1760	ERASE, 47884787163136, 47884789669887,
1761	STORE, 47884787163136, 47884789448703,
1762	STORE, 47884789448704, 47884789669887,
1763	STORE, 47884788858880, 47884789448703,
1764	STORE, 47884787163136, 47884788858879,
1765	ERASE, 47884787163136, 47884788858879,
1766	STORE, 47884787163136, 47884788858879,
1767	STORE, 47884789444608, 47884789448703,
1768	STORE, 47884788858880, 47884789444607,
1769	ERASE, 47884788858880, 47884789444607,
1770	STORE, 47884788858880, 47884789444607,
1771	STORE, 47884789653504, 47884789669887,
1772	STORE, 47884789448704, 47884789653503,
1773	ERASE, 47884789448704, 47884789653503,
1774	STORE, 47884789448704, 47884789653503,
1775	ERASE, 47884789653504, 47884789669887,
1776	STORE, 47884789653504, 47884789669887,
1777	STORE, 47884789669888, 47884791508991,
1778	STORE, 47884789809152, 47884791508991,
1779	STORE, 47884789669888, 47884789809151,
1780	ERASE, 47884789809152, 47884791508991,
1781	STORE, 47884789809152, 47884791468031,
1782	STORE, 47884791468032, 47884791508991,
1783	STORE, 47884791152640, 47884791468031,
1784	STORE, 47884789809152, 47884791152639,
1785	ERASE, 47884789809152, 47884791152639,
1786	STORE, 47884789809152, 47884791152639,
1787	STORE, 47884791463936, 47884791468031,
1788	STORE, 47884791152640, 47884791463935,
1789	ERASE, 47884791152640, 47884791463935,
1790	STORE, 47884791152640, 47884791463935,
1791	STORE, 47884791492608, 47884791508991,
1792	STORE, 47884791468032, 47884791492607,
1793	ERASE, 47884791468032, 47884791492607,
1794	STORE, 47884791468032, 47884791492607,
1795	ERASE, 47884791492608, 47884791508991,
1796	STORE, 47884791492608, 47884791508991,
1797	STORE, 47884791508992, 47884791644159,
1798	ERASE, 47884791508992, 47884791644159,
1799	STORE, 47884791508992, 47884791533567,
1800	STORE, 47884791533568, 47884791644159,
1801	STORE, 47884791595008, 47884791644159,
1802	STORE, 47884791533568, 47884791595007,
1803	ERASE, 47884791533568, 47884791595007,
1804	STORE, 47884791533568, 47884791595007,
1805	STORE, 47884791619584, 47884791644159,
1806	STORE, 47884791595008, 47884791619583,
1807	ERASE, 47884791595008, 47884791619583,
1808	STORE, 47884791595008, 47884791644159,
1809	ERASE, 47884791595008, 47884791644159,
1810	STORE, 47884791595008, 47884791619583,
1811	STORE, 47884791619584, 47884791644159,
1812	STORE, 47884791627776, 47884791644159,
1813	STORE, 47884791619584, 47884791627775,
1814	ERASE, 47884791619584, 47884791627775,
1815	STORE, 47884791619584, 47884791627775,
1816	ERASE, 47884791627776, 47884791644159,
1817	STORE, 47884791627776, 47884791644159,
1818	STORE, 47884791644160, 47884791664639,
1819	ERASE, 47884791644160, 47884791664639,
1820	STORE, 47884791644160, 47884791648255,
1821	STORE, 47884791648256, 47884791664639,
1822	STORE, 47884791652352, 47884791664639,
1823	STORE, 47884791648256, 47884791652351,
1824	ERASE, 47884791648256, 47884791652351,
1825	STORE, 47884791648256, 47884791652351,
1826	STORE, 47884791656448, 47884791664639,
1827	STORE, 47884791652352, 47884791656447,
1828	ERASE, 47884791652352, 47884791656447,
1829	STORE, 47884791652352, 47884791664639,
1830	ERASE, 47884791652352, 47884791664639,
1831	STORE, 47884791652352, 47884791656447,
1832	STORE, 47884791656448, 47884791664639,
1833	ERASE, 47884791656448, 47884791664639,
1834	STORE, 47884791656448, 47884791664639,
1835	STORE, 47884791664640, 47884791672831,
1836	ERASE, 47884791468032, 47884791492607,
1837	STORE, 47884791468032, 47884791484415,
1838	STORE, 47884791484416, 47884791492607,
1839	ERASE, 47884791656448, 47884791664639,
1840	STORE, 47884791656448, 47884791660543,
1841	STORE, 47884791660544, 47884791664639,
1842	ERASE, 47884791619584, 47884791627775,
1843	STORE, 47884791619584, 47884791623679,
1844	STORE, 47884791623680, 47884791627775,
1845	};
1846		957
1847	unsigned long set6[] = {	958	MT_BUG_ON(mt, !mtree_empty(mt));
1848	STORE, 140737488347136, 140737488351231,	959	check_insert_range(mt, r[0], r[1], xa_mk_value(r[0]), 0);
1849	STORE, 140722999021568, 140737488351231,	960	check_insert_range(mt, r[2], r[3], xa_mk_value(r[2]), 0);
1850	ERASE, 140722999021568, 140737488351231,	961	check_insert_range(mt, r[4], r[5], xa_mk_value(r[4]), -EEXIST);
1851	STORE, 140722999021568, 140722999025663,	962	MT_BUG_ON(mt, !mt_height(mt));
1852	STORE, 94901500268544, 94901500440575,	963	/* Store */
1853	ERASE, 94901500268544, 94901500440575,	964	check_store_range(mt, r[4], r[5], xa_mk_value(r[4]), 0);
1854	STORE, 94901500268544, 94901500284927,	965	check_store_range(mt, r[6], r[7], xa_mk_value(r[6]), 0);
1855	STORE, 94901500284928, 94901500440575,	966	check_store_range(mt, r[8], r[9], xa_mk_value(r[8]), 0);
1856	ERASE, 94901500284928, 94901500440575,	967	MT_BUG_ON(mt, !mt_height(mt));
1857	STORE, 94901500284928, 94901500387327,	968	mtree_destroy(mt);
1858	STORE, 94901500387328, 94901500428287,	969	MT_BUG_ON(mt, mt_height(mt));
1859	STORE, 94901500428288, 94901500440575,
1860	STORE, 47430426660864, 47430426832895,
1861	ERASE, 47430426660864, 47430426832895,
1862	STORE, 47430426660864, 47430426664959,
1863	STORE, 47430426664960, 47430426832895,
1864	ERASE, 47430426664960, 47430426832895,
1865	STORE, 47430426664960, 47430426787839,
1866	STORE, 47430426787840, 47430426820607,
1867	STORE, 47430426820608, 47430426828799,
1868	STORE, 47430426828800, 47430426832895,
1869	STORE, 140722999115776, 140722999119871,
1870	STORE, 140722999103488, 140722999115775,
1871	STORE, 47430426832896, 47430426841087,
1872	STORE, 47430426841088, 47430426849279,
1873	STORE, 47430426849280, 47430427013119,
1874	ERASE, 47430426849280, 47430427013119,
1875	STORE, 47430426849280, 47430426861567,
1876	STORE, 47430426861568, 47430427013119,
1877	STORE, 47430426959872, 47430427013119,
1878	STORE, 47430426861568, 47430426959871,
1879	ERASE, 47430426861568, 47430426959871,
1880	STORE, 47430426861568, 47430426959871,
1881	STORE, 47430427004928, 47430427013119,
1882	STORE, 47430426959872, 47430427004927,
1883	ERASE, 47430426959872, 47430427004927,
1884	STORE, 47430426959872, 47430427013119,
1885	ERASE, 47430426959872, 47430427013119,
1886	STORE, 47430426959872, 47430427004927,
1887	STORE, 47430427004928, 47430427013119,
1888	ERASE, 47430427004928, 47430427013119,
1889	STORE, 47430427004928, 47430427013119,
1890	STORE, 47430427013120, 47430430064639,
1891	STORE, 47430427557888, 47430430064639,
1892	STORE, 47430427013120, 47430427557887,
1893	ERASE, 47430427557888, 47430430064639,
1894	STORE, 47430427557888, 47430429843455,
1895	STORE, 47430429843456, 47430430064639,
1896	STORE, 47430429253632, 47430429843455,
1897	STORE, 47430427557888, 47430429253631,
1898	ERASE, 47430427557888, 47430429253631,
1899	STORE, 47430427557888, 47430429253631,
1900	STORE, 47430429839360, 47430429843455,
1901	STORE, 47430429253632, 47430429839359,
1902	ERASE, 47430429253632, 47430429839359,
1903	STORE, 47430429253632, 47430429839359,
1904	STORE, 47430430048256, 47430430064639,
1905	STORE, 47430429843456, 47430430048255,
1906	ERASE, 47430429843456, 47430430048255,
1907	STORE, 47430429843456, 47430430048255,
1908	ERASE, 47430430048256, 47430430064639,
1909	STORE, 47430430048256, 47430430064639,
1910	STORE, 47430430064640, 47430431903743,
1911	STORE, 47430430203904, 47430431903743,
1912	STORE, 47430430064640, 47430430203903,
1913	ERASE, 47430430203904, 47430431903743,
1914	STORE, 47430430203904, 47430431862783,
1915	STORE, 47430431862784, 47430431903743,
1916	STORE, 47430431547392, 47430431862783,
1917	STORE, 47430430203904, 47430431547391,
1918	ERASE, 47430430203904, 47430431547391,
1919	STORE, 47430430203904, 47430431547391,
1920	STORE, 47430431858688, 47430431862783,
1921	STORE, 47430431547392, 47430431858687,
1922	ERASE, 47430431547392, 47430431858687,
1923	STORE, 47430431547392, 47430431858687,
1924	STORE, 47430431887360, 47430431903743,
1925	STORE, 47430431862784, 47430431887359,
1926	ERASE, 47430431862784, 47430431887359,
1927	STORE, 47430431862784, 47430431887359,
1928	ERASE, 47430431887360, 47430431903743,
1929	STORE, 47430431887360, 47430431903743,
1930	STORE, 47430431903744, 47430432038911,
1931	ERASE, 47430431903744, 47430432038911,
1932	STORE, 47430431903744, 47430431928319,
1933	STORE, 47430431928320, 47430432038911,
1934	STORE, 47430431989760, 47430432038911,
1935	STORE, 47430431928320, 47430431989759,
1936	ERASE, 47430431928320, 47430431989759,
1937	STORE, 47430431928320, 47430431989759,
1938	STORE, 47430432014336, 47430432038911,
1939	STORE, 47430431989760, 47430432014335,
1940	ERASE, 47430431989760, 47430432014335,
1941	STORE, 47430431989760, 47430432038911,
1942	ERASE, 47430431989760, 47430432038911,
1943	STORE, 47430431989760, 47430432014335,
1944	STORE, 47430432014336, 47430432038911,
1945	STORE, 47430432022528, 47430432038911,
1946	STORE, 47430432014336, 47430432022527,
1947	ERASE, 47430432014336, 47430432022527,
1948	STORE, 47430432014336, 47430432022527,
1949	ERASE, 47430432022528, 47430432038911,
1950	STORE, 47430432022528, 47430432038911,
1951	STORE, 47430432038912, 47430432059391,
1952	ERASE, 47430432038912, 47430432059391,
1953	STORE, 47430432038912, 47430432043007,
1954	STORE, 47430432043008, 47430432059391,
1955	STORE, 47430432047104, 47430432059391,
1956	STORE, 47430432043008, 47430432047103,
1957	ERASE, 47430432043008, 47430432047103,
1958	STORE, 47430432043008, 47430432047103,
1959	STORE, 47430432051200, 47430432059391,
1960	STORE, 47430432047104, 47430432051199,
1961	ERASE, 47430432047104, 47430432051199,
1962	STORE, 47430432047104, 47430432059391,
1963	ERASE, 47430432047104, 47430432059391,
1964	STORE, 47430432047104, 47430432051199,
1965	STORE, 47430432051200, 47430432059391,
1966	ERASE, 47430432051200, 47430432059391,
1967	STORE, 47430432051200, 47430432059391,
1968	STORE, 47430432059392, 47430432067583,
1969	ERASE, 47430431862784, 47430431887359,
1970	STORE, 47430431862784, 47430431879167,
1971	STORE, 47430431879168, 47430431887359,
1972	ERASE, 47430432051200, 47430432059391,
1973	STORE, 47430432051200, 47430432055295,
1974	STORE, 47430432055296, 47430432059391,
1975	ERASE, 47430432014336, 47430432022527,
1976	STORE, 47430432014336, 47430432018431,
1977	STORE, 47430432018432, 47430432022527,
1978	};
1979	unsigned long set7[] = {
1980	STORE, 140737488347136, 140737488351231,
1981	STORE, 140729808330752, 140737488351231,
1982	ERASE, 140729808330752, 140737488351231,
1983	STORE, 140729808330752, 140729808334847,
1984	STORE, 94629632020480, 94629632192511,
1985	ERASE, 94629632020480, 94629632192511,
1986	STORE, 94629632020480, 94629632036863,
1987	STORE, 94629632036864, 94629632192511,
1988	ERASE, 94629632036864, 94629632192511,
1989	STORE, 94629632036864, 94629632139263,
1990	STORE, 94629632139264, 94629632180223,
1991	STORE, 94629632180224, 94629632192511,
1992	STORE, 47439981776896, 47439981948927,
1993	ERASE, 47439981776896, 47439981948927,
1994	STORE, 47439981776896, 47439981780991,
1995	STORE, 47439981780992, 47439981948927,
1996	ERASE, 47439981780992, 47439981948927,
1997	STORE, 47439981780992, 47439981903871,
1998	STORE, 47439981903872, 47439981936639,
1999	STORE, 47439981936640, 47439981944831,
2000	STORE, 47439981944832, 47439981948927,
2001	STORE, 140729808474112, 140729808478207,
2002	STORE, 140729808461824, 140729808474111,
2003	STORE, 47439981948928, 47439981957119,
2004	STORE, 47439981957120, 47439981965311,
2005	STORE, 47439981965312, 47439982129151,
2006	ERASE, 47439981965312, 47439982129151,
2007	STORE, 47439981965312, 47439981977599,
2008	STORE, 47439981977600, 47439982129151,
2009	STORE, 47439982075904, 47439982129151,
2010	STORE, 47439981977600, 47439982075903,
2011	ERASE, 47439981977600, 47439982075903,
2012	STORE, 47439981977600, 47439982075903,
2013	STORE, 47439982120960, 47439982129151,
2014	STORE, 47439982075904, 47439982120959,
2015	ERASE, 47439982075904, 47439982120959,
2016	STORE, 47439982075904, 47439982129151,
2017	ERASE, 47439982075904, 47439982129151,
2018	STORE, 47439982075904, 47439982120959,
2019	STORE, 47439982120960, 47439982129151,
2020	ERASE, 47439982120960, 47439982129151,
2021	STORE, 47439982120960, 47439982129151,
2022	STORE, 47439982129152, 47439985180671,
2023	STORE, 47439982673920, 47439985180671,
2024	STORE, 47439982129152, 47439982673919,
2025	ERASE, 47439982673920, 47439985180671,
2026	STORE, 47439982673920, 47439984959487,
2027	STORE, 47439984959488, 47439985180671,
2028	STORE, 47439984369664, 47439984959487,
2029	STORE, 47439982673920, 47439984369663,
2030	ERASE, 47439982673920, 47439984369663,
2031	STORE, 47439982673920, 47439984369663,
2032	STORE, 47439984955392, 47439984959487,
2033	STORE, 47439984369664, 47439984955391,
2034	ERASE, 47439984369664, 47439984955391,
2035	STORE, 47439984369664, 47439984955391,
2036	STORE, 47439985164288, 47439985180671,
2037	STORE, 47439984959488, 47439985164287,
2038	ERASE, 47439984959488, 47439985164287,
2039	STORE, 47439984959488, 47439985164287,
2040	ERASE, 47439985164288, 47439985180671,
2041	STORE, 47439985164288, 47439985180671,
2042	STORE, 47439985180672, 47439987019775,
2043	STORE, 47439985319936, 47439987019775,
2044	STORE, 47439985180672, 47439985319935,
2045	ERASE, 47439985319936, 47439987019775,
2046	STORE, 47439985319936, 47439986978815,
2047	STORE, 47439986978816, 47439987019775,
2048	STORE, 47439986663424, 47439986978815,
2049	STORE, 47439985319936, 47439986663423,
2050	ERASE, 47439985319936, 47439986663423,
2051	STORE, 47439985319936, 47439986663423,
2052	STORE, 47439986974720, 47439986978815,
2053	STORE, 47439986663424, 47439986974719,
2054	ERASE, 47439986663424, 47439986974719,
2055	STORE, 47439986663424, 47439986974719,
2056	STORE, 47439987003392, 47439987019775,
2057	STORE, 47439986978816, 47439987003391,
2058	ERASE, 47439986978816, 47439987003391,
2059	STORE, 47439986978816, 47439987003391,
2060	ERASE, 47439987003392, 47439987019775,
2061	STORE, 47439987003392, 47439987019775,
2062	STORE, 47439987019776, 47439987154943,
2063	ERASE, 47439987019776, 47439987154943,
2064	STORE, 47439987019776, 47439987044351,
2065	STORE, 47439987044352, 47439987154943,
2066	STORE, 47439987105792, 47439987154943,
2067	STORE, 47439987044352, 47439987105791,
2068	ERASE, 47439987044352, 47439987105791,
2069	STORE, 47439987044352, 47439987105791,
2070	STORE, 47439987130368, 47439987154943,
2071	STORE, 47439987105792, 47439987130367,
2072	ERASE, 47439987105792, 47439987130367,
2073	STORE, 47439987105792, 47439987154943,
2074	ERASE, 47439987105792, 47439987154943,
2075	STORE, 47439987105792, 47439987130367,
2076	STORE, 47439987130368, 47439987154943,
2077	STORE, 47439987138560, 47439987154943,
2078	STORE, 47439987130368, 47439987138559,
2079	ERASE, 47439987130368, 47439987138559,
2080	STORE, 47439987130368, 47439987138559,
2081	ERASE, 47439987138560, 47439987154943,
2082	STORE, 47439987138560, 47439987154943,
2083	STORE, 47439987154944, 47439987175423,
2084	ERASE, 47439987154944, 47439987175423,
2085	STORE, 47439987154944, 47439987159039,
2086	STORE, 47439987159040, 47439987175423,
2087	STORE, 47439987163136, 47439987175423,
2088	STORE, 47439987159040, 47439987163135,
2089	ERASE, 47439987159040, 47439987163135,
2090	STORE, 47439987159040, 47439987163135,
2091	STORE, 47439987167232, 47439987175423,
2092	STORE, 47439987163136, 47439987167231,
2093	ERASE, 47439987163136, 47439987167231,
2094	STORE, 47439987163136, 47439987175423,
2095	ERASE, 47439987163136, 47439987175423,
2096	STORE, 47439987163136, 47439987167231,
2097	STORE, 47439987167232, 47439987175423,
2098	ERASE, 47439987167232, 47439987175423,
2099	STORE, 47439987167232, 47439987175423,
2100	STORE, 47439987175424, 47439987183615,
2101	ERASE, 47439986978816, 47439987003391,
2102	STORE, 47439986978816, 47439986995199,
2103	STORE, 47439986995200, 47439987003391,
2104	ERASE, 47439987167232, 47439987175423,
2105	STORE, 47439987167232, 47439987171327,
2106	STORE, 47439987171328, 47439987175423,
2107	ERASE, 47439987130368, 47439987138559,
2108	STORE, 47439987130368, 47439987134463,
2109	STORE, 47439987134464, 47439987138559,
2110	};
2111	unsigned long set8[] = {
2112	STORE, 140737488347136, 140737488351231,
2113	STORE, 140722482974720, 140737488351231,
2114	ERASE, 140722482974720, 140737488351231,
2115	STORE, 140722482974720, 140722482978815,
2116	STORE, 94121505034240, 94121505206271,
2117	ERASE, 94121505034240, 94121505206271,
2118	STORE, 94121505034240, 94121505050623,
2119	STORE, 94121505050624, 94121505206271,
2120	ERASE, 94121505050624, 94121505206271,
2121	STORE, 94121505050624, 94121505153023,
2122	STORE, 94121505153024, 94121505193983,
2123	STORE, 94121505193984, 94121505206271,
2124	STORE, 47708483284992, 47708483457023,
2125	ERASE, 47708483284992, 47708483457023,
2126	STORE, 47708483284992, 47708483289087,
2127	STORE, 47708483289088, 47708483457023,
2128	ERASE, 47708483289088, 47708483457023,
2129	STORE, 47708483289088, 47708483411967,
2130	STORE, 47708483411968, 47708483444735,
2131	STORE, 47708483444736, 47708483452927,
2132	STORE, 47708483452928, 47708483457023,
2133	STORE, 140722483142656, 140722483146751,
2134	STORE, 140722483130368, 140722483142655,
2135	STORE, 47708483457024, 47708483465215,
2136	STORE, 47708483465216, 47708483473407,
2137	STORE, 47708483473408, 47708483637247,
2138	ERASE, 47708483473408, 47708483637247,
2139	STORE, 47708483473408, 47708483485695,
2140	STORE, 47708483485696, 47708483637247,
2141	STORE, 47708483584000, 47708483637247,
2142	STORE, 47708483485696, 47708483583999,
2143	ERASE, 47708483485696, 47708483583999,
2144	STORE, 47708483485696, 47708483583999,
2145	STORE, 47708483629056, 47708483637247,
2146	STORE, 47708483584000, 47708483629055,
2147	ERASE, 47708483584000, 47708483629055,
2148	STORE, 47708483584000, 47708483637247,
2149	ERASE, 47708483584000, 47708483637247,
2150	STORE, 47708483584000, 47708483629055,
2151	STORE, 47708483629056, 47708483637247,
2152	ERASE, 47708483629056, 47708483637247,
2153	STORE, 47708483629056, 47708483637247,
2154	STORE, 47708483637248, 47708486688767,
2155	STORE, 47708484182016, 47708486688767,
2156	STORE, 47708483637248, 47708484182015,
2157	ERASE, 47708484182016, 47708486688767,
2158	STORE, 47708484182016, 47708486467583,
2159	STORE, 47708486467584, 47708486688767,
2160	STORE, 47708485877760, 47708486467583,
2161	STORE, 47708484182016, 47708485877759,
2162	ERASE, 47708484182016, 47708485877759,
2163	STORE, 47708484182016, 47708485877759,
2164	STORE, 47708486463488, 47708486467583,
2165	STORE, 47708485877760, 47708486463487,
2166	ERASE, 47708485877760, 47708486463487,
2167	STORE, 47708485877760, 47708486463487,
2168	STORE, 47708486672384, 47708486688767,
2169	STORE, 47708486467584, 47708486672383,
2170	ERASE, 47708486467584, 47708486672383,
2171	STORE, 47708486467584, 47708486672383,
2172	ERASE, 47708486672384, 47708486688767,
2173	STORE, 47708486672384, 47708486688767,
2174	STORE, 47708486688768, 47708488527871,
2175	STORE, 47708486828032, 47708488527871,
2176	STORE, 47708486688768, 47708486828031,
2177	ERASE, 47708486828032, 47708488527871,
2178	STORE, 47708486828032, 47708488486911,
2179	STORE, 47708488486912, 47708488527871,
2180	STORE, 47708488171520, 47708488486911,
2181	STORE, 47708486828032, 47708488171519,
2182	ERASE, 47708486828032, 47708488171519,
2183	STORE, 47708486828032, 47708488171519,
2184	STORE, 47708488482816, 47708488486911,
2185	STORE, 47708488171520, 47708488482815,
2186	ERASE, 47708488171520, 47708488482815,
2187	STORE, 47708488171520, 47708488482815,
2188	STORE, 47708488511488, 47708488527871,
2189	STORE, 47708488486912, 47708488511487,
2190	ERASE, 47708488486912, 47708488511487,
2191	STORE, 47708488486912, 47708488511487,
2192	ERASE, 47708488511488, 47708488527871,
2193	STORE, 47708488511488, 47708488527871,
2194	STORE, 47708488527872, 47708488663039,
2195	ERASE, 47708488527872, 47708488663039,
2196	STORE, 47708488527872, 47708488552447,
2197	STORE, 47708488552448, 47708488663039,
2198	STORE, 47708488613888, 47708488663039,
2199	STORE, 47708488552448, 47708488613887,
2200	ERASE, 47708488552448, 47708488613887,
2201	STORE, 47708488552448, 47708488613887,
2202	STORE, 47708488638464, 47708488663039,
2203	STORE, 47708488613888, 47708488638463,
2204	ERASE, 47708488613888, 47708488638463,
2205	STORE, 47708488613888, 47708488663039,
2206	ERASE, 47708488613888, 47708488663039,
2207	STORE, 47708488613888, 47708488638463,
2208	STORE, 47708488638464, 47708488663039,
2209	STORE, 47708488646656, 47708488663039,
2210	STORE, 47708488638464, 47708488646655,
2211	ERASE, 47708488638464, 47708488646655,
2212	STORE, 47708488638464, 47708488646655,
2213	ERASE, 47708488646656, 47708488663039,
2214	STORE, 47708488646656, 47708488663039,
2215	STORE, 47708488663040, 47708488683519,
2216	ERASE, 47708488663040, 47708488683519,
2217	STORE, 47708488663040, 47708488667135,
2218	STORE, 47708488667136, 47708488683519,
2219	STORE, 47708488671232, 47708488683519,
2220	STORE, 47708488667136, 47708488671231,
2221	ERASE, 47708488667136, 47708488671231,
2222	STORE, 47708488667136, 47708488671231,
2223	STORE, 47708488675328, 47708488683519,
2224	STORE, 47708488671232, 47708488675327,
2225	ERASE, 47708488671232, 47708488675327,
2226	STORE, 47708488671232, 47708488683519,
2227	ERASE, 47708488671232, 47708488683519,
2228	STORE, 47708488671232, 47708488675327,
2229	STORE, 47708488675328, 47708488683519,
2230	ERASE, 47708488675328, 47708488683519,
2231	STORE, 47708488675328, 47708488683519,
2232	STORE, 47708488683520, 47708488691711,
2233	ERASE, 47708488486912, 47708488511487,
2234	STORE, 47708488486912, 47708488503295,
2235	STORE, 47708488503296, 47708488511487,
2236	ERASE, 47708488675328, 47708488683519,
2237	STORE, 47708488675328, 47708488679423,
2238	STORE, 47708488679424, 47708488683519,
2239	ERASE, 47708488638464, 47708488646655,
2240	STORE, 47708488638464, 47708488642559,
2241	STORE, 47708488642560, 47708488646655,
2242	};
2243		970
2244	unsigned long set9[] = {
2245	STORE, 140737488347136, 140737488351231,
2246	STORE, 140736427839488, 140737488351231,
2247	ERASE, 140736427839488, 140736427839488,
2248	STORE, 140736427839488, 140736427843583,
2249	STORE, 94071213395968, 94071213567999,
2250	ERASE, 94071213395968, 94071213395968,
2251	STORE, 94071213395968, 94071213412351,
2252	STORE, 94071213412352, 94071213567999,
2253	ERASE, 94071213412352, 94071213412352,
2254	STORE, 94071213412352, 94071213514751,
2255	STORE, 94071213514752, 94071213555711,
2256	STORE, 94071213555712, 94071213567999,
2257	STORE, 139968410644480, 139968410816511,
2258	ERASE, 139968410644480, 139968410644480,
2259	STORE, 139968410644480, 139968410648575,
2260	STORE, 139968410648576, 139968410816511,
2261	ERASE, 139968410648576, 139968410648576,
2262	STORE, 139968410648576, 139968410771455,
2263	STORE, 139968410771456, 139968410804223,
2264	STORE, 139968410804224, 139968410812415,
2265	STORE, 139968410812416, 139968410816511,
2266	STORE, 140736429277184, 140736429281279,
2267	STORE, 140736429264896, 140736429277183,
2268	STORE, 47664384352256, 47664384360447,
2269	STORE, 47664384360448, 47664384368639,
2270	STORE, 47664384368640, 47664384532479,
2271	ERASE, 47664384368640, 47664384368640,
2272	STORE, 47664384368640, 47664384380927,
2273	STORE, 47664384380928, 47664384532479,
2274	STORE, 47664384479232, 47664384532479,
2275	STORE, 47664384380928, 47664384479231,
2276	ERASE, 47664384380928, 47664384380928,
2277	STORE, 47664384380928, 47664384479231,
2278	STORE, 47664384524288, 47664384532479,
2279	STORE, 47664384479232, 47664384524287,
2280	ERASE, 47664384479232, 47664384479232,
2281	STORE, 47664384479232, 47664384532479,
2282	ERASE, 47664384479232, 47664384479232,
2283	STORE, 47664384479232, 47664384524287,
2284	STORE, 47664384524288, 47664384532479,
2285	ERASE, 47664384524288, 47664384524288,
2286	STORE, 47664384524288, 47664384532479,
2287	STORE, 47664384532480, 47664387583999,
2288	STORE, 47664385077248, 47664387583999,
2289	STORE, 47664384532480, 47664385077247,
2290	ERASE, 47664385077248, 47664385077248,
2291	STORE, 47664385077248, 47664387362815,
2292	STORE, 47664387362816, 47664387583999,
2293	STORE, 47664386772992, 47664387362815,
2294	STORE, 47664385077248, 47664386772991,
2295	ERASE, 47664385077248, 47664385077248,
2296	STORE, 47664385077248, 47664386772991,
2297	STORE, 47664387358720, 47664387362815,
2298	STORE, 47664386772992, 47664387358719,
2299	ERASE, 47664386772992, 47664386772992,
2300	STORE, 47664386772992, 47664387358719,
2301	STORE, 47664387567616, 47664387583999,
2302	STORE, 47664387362816, 47664387567615,
2303	ERASE, 47664387362816, 47664387362816,
2304	STORE, 47664387362816, 47664387567615,
2305	ERASE, 47664387567616, 47664387567616,
2306	STORE, 47664387567616, 47664387583999,
2307	STORE, 47664387584000, 47664389423103,
2308	STORE, 47664387723264, 47664389423103,
2309	STORE, 47664387584000, 47664387723263,
2310	ERASE, 47664387723264, 47664387723264,
2311	STORE, 47664387723264, 47664389382143,
2312	STORE, 47664389382144, 47664389423103,
2313	STORE, 47664389066752, 47664389382143,
2314	STORE, 47664387723264, 47664389066751,
2315	ERASE, 47664387723264, 47664387723264,
2316	STORE, 47664387723264, 47664389066751,
2317	STORE, 47664389378048, 47664389382143,
2318	STORE, 47664389066752, 47664389378047,
2319	ERASE, 47664389066752, 47664389066752,
2320	STORE, 47664389066752, 47664389378047,
2321	STORE, 47664389406720, 47664389423103,
2322	STORE, 47664389382144, 47664389406719,
2323	ERASE, 47664389382144, 47664389382144,
2324	STORE, 47664389382144, 47664389406719,
2325	ERASE, 47664389406720, 47664389406720,
2326	STORE, 47664389406720, 47664389423103,
2327	STORE, 47664389423104, 47664389558271,
2328	ERASE, 47664389423104, 47664389423104,
2329	STORE, 47664389423104, 47664389447679,
2330	STORE, 47664389447680, 47664389558271,
2331	STORE, 47664389509120, 47664389558271,
2332	STORE, 47664389447680, 47664389509119,
2333	ERASE, 47664389447680, 47664389447680,
2334	STORE, 47664389447680, 47664389509119,
2335	STORE, 47664389533696, 47664389558271,
2336	STORE, 47664389509120, 47664389533695,
2337	ERASE, 47664389509120, 47664389509120,
2338	STORE, 47664389509120, 47664389558271,
2339	ERASE, 47664389509120, 47664389509120,
2340	STORE, 47664389509120, 47664389533695,
2341	STORE, 47664389533696, 47664389558271,
2342	STORE, 47664389541888, 47664389558271,
2343	STORE, 47664389533696, 47664389541887,
2344	ERASE, 47664389533696, 47664389533696,
2345	STORE, 47664389533696, 47664389541887,
2346	ERASE, 47664389541888, 47664389541888,
2347	STORE, 47664389541888, 47664389558271,
2348	STORE, 47664389558272, 47664389578751,
2349	ERASE, 47664389558272, 47664389558272,
2350	STORE, 47664389558272, 47664389562367,
2351	STORE, 47664389562368, 47664389578751,
2352	STORE, 47664389566464, 47664389578751,
2353	STORE, 47664389562368, 47664389566463,
2354	ERASE, 47664389562368, 47664389562368,
2355	STORE, 47664389562368, 47664389566463,
2356	STORE, 47664389570560, 47664389578751,
2357	STORE, 47664389566464, 47664389570559,
2358	ERASE, 47664389566464, 47664389566464,
2359	STORE, 47664389566464, 47664389578751,
2360	ERASE, 47664389566464, 47664389566464,
2361	STORE, 47664389566464, 47664389570559,
2362	STORE, 47664389570560, 47664389578751,
2363	ERASE, 47664389570560, 47664389570560,
2364	STORE, 47664389570560, 47664389578751,
2365	STORE, 47664389578752, 47664389586943,
2366	ERASE, 47664389382144, 47664389382144,
2367	STORE, 47664389382144, 47664389398527,
2368	STORE, 47664389398528, 47664389406719,
2369	ERASE, 47664389570560, 47664389570560,
2370	STORE, 47664389570560, 47664389574655,
2371	STORE, 47664389574656, 47664389578751,
2372	ERASE, 47664389533696, 47664389533696,
2373	STORE, 47664389533696, 47664389537791,
2374	STORE, 47664389537792, 47664389541887,
2375	ERASE, 47664387362816, 47664387362816,
2376	STORE, 47664387362816, 47664387559423,
2377	STORE, 47664387559424, 47664387567615,
2378	ERASE, 47664384524288, 47664384524288,
2379	STORE, 47664384524288, 47664384528383,
2380	STORE, 47664384528384, 47664384532479,
2381	ERASE, 94071213555712, 94071213555712,
2382	STORE, 94071213555712, 94071213563903,
2383	STORE, 94071213563904, 94071213567999,
2384	ERASE, 139968410804224, 139968410804224,
2385	STORE, 139968410804224, 139968410808319,
2386	STORE, 139968410808320, 139968410812415,
2387	ERASE, 47664384352256, 47664384352256,
2388	STORE, 94071244402688, 94071244537855,
2389	STORE, 140737488347136, 140737488351231,
2390	STORE, 140728271503360, 140737488351231,
2391	ERASE, 140728271503360, 140728271503360,
2392	STORE, 140728271503360, 140728271507455,
2393	STORE, 94410361982976, 94410362155007,
2394	ERASE, 94410361982976, 94410361982976,
2395	STORE, 94410361982976, 94410361999359,
2396	STORE, 94410361999360, 94410362155007,
2397	ERASE, 94410361999360, 94410361999360,
2398	STORE, 94410361999360, 94410362101759,
2399	STORE, 94410362101760, 94410362142719,
2400	STORE, 94410362142720, 94410362155007,
2401	STORE, 140351953997824, 140351954169855,
2402	ERASE, 140351953997824, 140351953997824,
2403	STORE, 140351953997824, 140351954001919,
2404	STORE, 140351954001920, 140351954169855,
2405	ERASE, 140351954001920, 140351954001920,
2406	STORE, 140351954001920, 140351954124799,
2407	STORE, 140351954124800, 140351954157567,
2408	STORE, 140351954157568, 140351954165759,
2409	STORE, 140351954165760, 140351954169855,
2410	STORE, 140728272429056, 140728272433151,
2411	STORE, 140728272416768, 140728272429055,
2412	STORE, 47280840998912, 47280841007103,
2413	STORE, 47280841007104, 47280841015295,
2414	STORE, 47280841015296, 47280841179135,
2415	ERASE, 47280841015296, 47280841015296,
2416	STORE, 47280841015296, 47280841027583,
2417	STORE, 47280841027584, 47280841179135,
2418	STORE, 47280841125888, 47280841179135,
2419	STORE, 47280841027584, 47280841125887,
2420	ERASE, 47280841027584, 47280841027584,
2421	STORE, 47280841027584, 47280841125887,
2422	STORE, 47280841170944, 47280841179135,
2423	STORE, 47280841125888, 47280841170943,
2424	ERASE, 47280841125888, 47280841125888,
2425	STORE, 47280841125888, 47280841179135,
2426	ERASE, 47280841125888, 47280841125888,
2427	STORE, 47280841125888, 47280841170943,
2428	STORE, 47280841170944, 47280841179135,
2429	ERASE, 47280841170944, 47280841170944,
2430	STORE, 47280841170944, 47280841179135,
2431	STORE, 47280841179136, 47280844230655,
2432	STORE, 47280841723904, 47280844230655,
2433	STORE, 47280841179136, 47280841723903,
2434	ERASE, 47280841723904, 47280841723904,
2435	STORE, 47280841723904, 47280844009471,
2436	STORE, 47280844009472, 47280844230655,
2437	STORE, 47280843419648, 47280844009471,
2438	STORE, 47280841723904, 47280843419647,
2439	ERASE, 47280841723904, 47280841723904,
2440	STORE, 47280841723904, 47280843419647,
2441	STORE, 47280844005376, 47280844009471,
2442	STORE, 47280843419648, 47280844005375,
2443	ERASE, 47280843419648, 47280843419648,
2444	STORE, 47280843419648, 47280844005375,
2445	STORE, 47280844214272, 47280844230655,
2446	STORE, 47280844009472, 47280844214271,
2447	ERASE, 47280844009472, 47280844009472,
2448	STORE, 47280844009472, 47280844214271,
2449	ERASE, 47280844214272, 47280844214272,
2450	STORE, 47280844214272, 47280844230655,
2451	STORE, 47280844230656, 47280846069759,
2452	STORE, 47280844369920, 47280846069759,
2453	STORE, 47280844230656, 47280844369919,
2454	ERASE, 47280844369920, 47280844369920,
2455	STORE, 47280844369920, 47280846028799,
2456	STORE, 47280846028800, 47280846069759,
2457	STORE, 47280845713408, 47280846028799,
2458	STORE, 47280844369920, 47280845713407,
2459	ERASE, 47280844369920, 47280844369920,
2460	STORE, 47280844369920, 47280845713407,
2461	STORE, 47280846024704, 47280846028799,
2462	STORE, 47280845713408, 47280846024703,
2463	ERASE, 47280845713408, 47280845713408,
2464	STORE, 47280845713408, 47280846024703,
2465	STORE, 47280846053376, 47280846069759,
2466	STORE, 47280846028800, 47280846053375,
2467	ERASE, 47280846028800, 47280846028800,
2468	STORE, 47280846028800, 47280846053375,
2469	ERASE, 47280846053376, 47280846053376,
2470	STORE, 47280846053376, 47280846069759,
2471	STORE, 47280846069760, 47280846204927,
2472	ERASE, 47280846069760, 47280846069760,
2473	STORE, 47280846069760, 47280846094335,
2474	STORE, 47280846094336, 47280846204927,
2475	STORE, 47280846155776, 47280846204927,
2476	STORE, 47280846094336, 47280846155775,
2477	ERASE, 47280846094336, 47280846094336,
2478	STORE, 47280846094336, 47280846155775,
2479	STORE, 47280846180352, 47280846204927,
2480	STORE, 47280846155776, 47280846180351,
2481	ERASE, 47280846155776, 47280846155776,
2482	STORE, 47280846155776, 47280846204927,
2483	ERASE, 47280846155776, 47280846155776,
2484	STORE, 47280846155776, 47280846180351,
2485	STORE, 47280846180352, 47280846204927,
2486	STORE, 47280846188544, 47280846204927,
2487	STORE, 47280846180352, 47280846188543,
2488	ERASE, 47280846180352, 47280846180352,
2489	STORE, 47280846180352, 47280846188543,
2490	ERASE, 47280846188544, 47280846188544,
2491	STORE, 47280846188544, 47280846204927,
2492	STORE, 47280846204928, 47280846225407,
2493	ERASE, 47280846204928, 47280846204928,
2494	STORE, 47280846204928, 47280846209023,
2495	STORE, 47280846209024, 47280846225407,
2496	STORE, 47280846213120, 47280846225407,
2497	STORE, 47280846209024, 47280846213119,
2498	ERASE, 47280846209024, 47280846209024,
2499	STORE, 47280846209024, 47280846213119,
2500	STORE, 47280846217216, 47280846225407,
2501	STORE, 47280846213120, 47280846217215,
2502	ERASE, 47280846213120, 47280846213120,
2503	STORE, 47280846213120, 47280846225407,
2504	ERASE, 47280846213120, 47280846213120,
2505	STORE, 47280846213120, 47280846217215,
2506	STORE, 47280846217216, 47280846225407,
2507	ERASE, 47280846217216, 47280846217216,
2508	STORE, 47280846217216, 47280846225407,
2509	STORE, 47280846225408, 47280846233599,
2510	ERASE, 47280846028800, 47280846028800,
2511	STORE, 47280846028800, 47280846045183,
2512	STORE, 47280846045184, 47280846053375,
2513	ERASE, 47280846217216, 47280846217216,
2514	STORE, 47280846217216, 47280846221311,
2515	STORE, 47280846221312, 47280846225407,
2516	ERASE, 47280846180352, 47280846180352,
2517	STORE, 47280846180352, 47280846184447,
2518	STORE, 47280846184448, 47280846188543,
2519	ERASE, 47280844009472, 47280844009472,
2520	STORE, 47280844009472, 47280844206079,
2521	STORE, 47280844206080, 47280844214271,
2522	ERASE, 47280841170944, 47280841170944,
2523	STORE, 47280841170944, 47280841175039,
2524	STORE, 47280841175040, 47280841179135,
2525	ERASE, 94410362142720, 94410362142720,
2526	STORE, 94410362142720, 94410362150911,
2527	STORE, 94410362150912, 94410362155007,
2528	ERASE, 140351954157568, 140351954157568,
2529	STORE, 140351954157568, 140351954161663,
2530	STORE, 140351954161664, 140351954165759,
2531	ERASE, 47280840998912, 47280840998912,
2532	STORE, 94410379456512, 94410379591679,
2533	STORE, 140737488347136, 140737488351231,
2534	STORE, 140732946362368, 140737488351231,
2535	ERASE, 140732946362368, 140732946362368,
2536	STORE, 140732946362368, 140732946366463,
2537	STORE, 94352937934848, 94352938106879,
2538	ERASE, 94352937934848, 94352937934848,
2539	STORE, 94352937934848, 94352937951231,
2540	STORE, 94352937951232, 94352938106879,
2541	ERASE, 94352937951232, 94352937951232,
2542	STORE, 94352937951232, 94352938053631,
2543	STORE, 94352938053632, 94352938094591,
2544	STORE, 94352938094592, 94352938106879,
2545	STORE, 140595518742528, 140595518914559,
2546	ERASE, 140595518742528, 140595518742528,
2547	STORE, 140595518742528, 140595518746623,
2548	STORE, 140595518746624, 140595518914559,
2549	ERASE, 140595518746624, 140595518746624,
2550	STORE, 140595518746624, 140595518869503,
2551	STORE, 140595518869504, 140595518902271,
2552	STORE, 140595518902272, 140595518910463,
2553	STORE, 140595518910464, 140595518914559,
2554	STORE, 140732947468288, 140732947472383,
2555	STORE, 140732947456000, 140732947468287,
2556	STORE, 47037276254208, 47037276262399,
2557	STORE, 47037276262400, 47037276270591,
2558	STORE, 47037276270592, 47037276434431,
2559	ERASE, 47037276270592, 47037276270592,
2560	STORE, 47037276270592, 47037276282879,
2561	STORE, 47037276282880, 47037276434431,
2562	STORE, 47037276381184, 47037276434431,
2563	STORE, 47037276282880, 47037276381183,
2564	ERASE, 47037276282880, 47037276282880,
2565	STORE, 47037276282880, 47037276381183,
2566	STORE, 47037276426240, 47037276434431,
2567	STORE, 47037276381184, 47037276426239,
2568	ERASE, 47037276381184, 47037276381184,
2569	STORE, 47037276381184, 47037276434431,
2570	ERASE, 47037276381184, 47037276381184,
2571	STORE, 47037276381184, 47037276426239,
2572	STORE, 47037276426240, 47037276434431,
2573	ERASE, 47037276426240, 47037276426240,
2574	STORE, 47037276426240, 47037276434431,
2575	STORE, 47037276434432, 47037279485951,
2576	STORE, 47037276979200, 47037279485951,
2577	STORE, 47037276434432, 47037276979199,
2578	ERASE, 47037276979200, 47037276979200,
2579	STORE, 47037276979200, 47037279264767,
2580	STORE, 47037279264768, 47037279485951,
2581	STORE, 47037278674944, 47037279264767,
2582	STORE, 47037276979200, 47037278674943,
2583	ERASE, 47037276979200, 47037276979200,
2584	STORE, 47037276979200, 47037278674943,
2585	STORE, 47037279260672, 47037279264767,
2586	STORE, 47037278674944, 47037279260671,
2587	ERASE, 47037278674944, 47037278674944,
2588	STORE, 47037278674944, 47037279260671,
2589	STORE, 47037279469568, 47037279485951,
2590	STORE, 47037279264768, 47037279469567,
2591	ERASE, 47037279264768, 47037279264768,
2592	STORE, 47037279264768, 47037279469567,
2593	ERASE, 47037279469568, 47037279469568,
2594	STORE, 47037279469568, 47037279485951,
2595	STORE, 47037279485952, 47037281325055,
2596	STORE, 47037279625216, 47037281325055,
2597	STORE, 47037279485952, 47037279625215,
2598	ERASE, 47037279625216, 47037279625216,
2599	STORE, 47037279625216, 47037281284095,
2600	STORE, 47037281284096, 47037281325055,
2601	STORE, 47037280968704, 47037281284095,
2602	STORE, 47037279625216, 47037280968703,
2603	ERASE, 47037279625216, 47037279625216,
2604	STORE, 47037279625216, 47037280968703,
2605	STORE, 47037281280000, 47037281284095,
2606	STORE, 47037280968704, 47037281279999,
2607	ERASE, 47037280968704, 47037280968704,
2608	STORE, 47037280968704, 47037281279999,
2609	STORE, 47037281308672, 47037281325055,
2610	STORE, 47037281284096, 47037281308671,
2611	ERASE, 47037281284096, 47037281284096,
2612	STORE, 47037281284096, 47037281308671,
2613	ERASE, 47037281308672, 47037281308672,
2614	STORE, 47037281308672, 47037281325055,
2615	STORE, 47037281325056, 47037281460223,
2616	ERASE, 47037281325056, 47037281325056,
2617	STORE, 47037281325056, 47037281349631,
2618	STORE, 47037281349632, 47037281460223,
2619	STORE, 47037281411072, 47037281460223,
2620	STORE, 47037281349632, 47037281411071,
2621	ERASE, 47037281349632, 47037281349632,
2622	STORE, 47037281349632, 47037281411071,
2623	STORE, 47037281435648, 47037281460223,
2624	STORE, 47037281411072, 47037281435647,
2625	ERASE, 47037281411072, 47037281411072,
2626	STORE, 47037281411072, 47037281460223,
2627	ERASE, 47037281411072, 47037281411072,
2628	STORE, 47037281411072, 47037281435647,
2629	STORE, 47037281435648, 47037281460223,
2630	STORE, 47037281443840, 47037281460223,
2631	STORE, 47037281435648, 47037281443839,
2632	ERASE, 47037281435648, 47037281435648,
2633	STORE, 47037281435648, 47037281443839,
2634	ERASE, 47037281443840, 47037281443840,
2635	STORE, 47037281443840, 47037281460223,
2636	STORE, 47037281460224, 47037281480703,
2637	ERASE, 47037281460224, 47037281460224,
2638	STORE, 47037281460224, 47037281464319,
2639	STORE, 47037281464320, 47037281480703,
2640	STORE, 47037281468416, 47037281480703,
2641	STORE, 47037281464320, 47037281468415,
2642	ERASE, 47037281464320, 47037281464320,
2643	STORE, 47037281464320, 47037281468415,
2644	STORE, 47037281472512, 47037281480703,
2645	STORE, 47037281468416, 47037281472511,
2646	ERASE, 47037281468416, 47037281468416,
2647	STORE, 47037281468416, 47037281480703,
2648	ERASE, 47037281468416, 47037281468416,
2649	STORE, 47037281468416, 47037281472511,
2650	STORE, 47037281472512, 47037281480703,
2651	ERASE, 47037281472512, 47037281472512,
2652	STORE, 47037281472512, 47037281480703,
2653	STORE, 47037281480704, 47037281488895,
2654	ERASE, 47037281284096, 47037281284096,
2655	STORE, 47037281284096, 47037281300479,
2656	STORE, 47037281300480, 47037281308671,
2657	ERASE, 47037281472512, 47037281472512,
2658	STORE, 47037281472512, 47037281476607,
2659	STORE, 47037281476608, 47037281480703,
2660	ERASE, 47037281435648, 47037281435648,
2661	STORE, 47037281435648, 47037281439743,
2662	STORE, 47037281439744, 47037281443839,
2663	ERASE, 47037279264768, 47037279264768,
2664	STORE, 47037279264768, 47037279461375,
2665	STORE, 47037279461376, 47037279469567,
2666	ERASE, 47037276426240, 47037276426240,
2667	STORE, 47037276426240, 47037276430335,
2668	STORE, 47037276430336, 47037276434431,
2669	ERASE, 94352938094592, 94352938094592,
2670	STORE, 94352938094592, 94352938102783,
2671	STORE, 94352938102784, 94352938106879,
2672	ERASE, 140595518902272, 140595518902272,
2673	STORE, 140595518902272, 140595518906367,
2674	STORE, 140595518906368, 140595518910463,
2675	ERASE, 47037276254208, 47037276254208,
2676	STORE, 94352938438656, 94352938573823,
2677	STORE, 140737488347136, 140737488351231,
2678	STORE, 140733506027520, 140737488351231,
2679	ERASE, 140733506027520, 140733506027520,
2680	STORE, 140733506027520, 140733506031615,
2681	STORE, 94150123073536, 94150123245567,
2682	ERASE, 94150123073536, 94150123073536,
2683	STORE, 94150123073536, 94150123089919,
2684	STORE, 94150123089920, 94150123245567,
2685	ERASE, 94150123089920, 94150123089920,
2686	STORE, 94150123089920, 94150123192319,
2687	STORE, 94150123192320, 94150123233279,
2688	STORE, 94150123233280, 94150123245567,
2689	STORE, 140081290375168, 140081290547199,
2690	ERASE, 140081290375168, 140081290375168,
2691	STORE, 140081290375168, 140081290379263,
2692	STORE, 140081290379264, 140081290547199,
2693	ERASE, 140081290379264, 140081290379264,
2694	STORE, 140081290379264, 140081290502143,
2695	STORE, 140081290502144, 140081290534911,
2696	STORE, 140081290534912, 140081290543103,
2697	STORE, 140081290543104, 140081290547199,
2698	STORE, 140733506707456, 140733506711551,
2699	STORE, 140733506695168, 140733506707455,
2700	STORE, 47551504621568, 47551504629759,
2701	STORE, 47551504629760, 47551504637951,
2702	STORE, 47551504637952, 47551504801791,
2703	ERASE, 47551504637952, 47551504637952,
2704	STORE, 47551504637952, 47551504650239,
2705	STORE, 47551504650240, 47551504801791,
2706	STORE, 47551504748544, 47551504801791,
2707	STORE, 47551504650240, 47551504748543,
2708	ERASE, 47551504650240, 47551504650240,
2709	STORE, 47551504650240, 47551504748543,
2710	STORE, 47551504793600, 47551504801791,
2711	STORE, 47551504748544, 47551504793599,
2712	ERASE, 47551504748544, 47551504748544,
2713	STORE, 47551504748544, 47551504801791,
2714	ERASE, 47551504748544, 47551504748544,
2715	STORE, 47551504748544, 47551504793599,
2716	STORE, 47551504793600, 47551504801791,
2717	ERASE, 47551504793600, 47551504793600,
2718	STORE, 47551504793600, 47551504801791,
2719	STORE, 47551504801792, 47551507853311,
2720	STORE, 47551505346560, 47551507853311,
2721	STORE, 47551504801792, 47551505346559,
2722	ERASE, 47551505346560, 47551505346560,
2723	STORE, 47551505346560, 47551507632127,
2724	STORE, 47551507632128, 47551507853311,
2725	STORE, 47551507042304, 47551507632127,
2726	STORE, 47551505346560, 47551507042303,
2727	ERASE, 47551505346560, 47551505346560,
2728	STORE, 47551505346560, 47551507042303,
2729	STORE, 47551507628032, 47551507632127,
2730	STORE, 47551507042304, 47551507628031,
2731	ERASE, 47551507042304, 47551507042304,
2732	STORE, 47551507042304, 47551507628031,
2733	STORE, 47551507836928, 47551507853311,
2734	STORE, 47551507632128, 47551507836927,
2735	ERASE, 47551507632128, 47551507632128,
2736	STORE, 47551507632128, 47551507836927,
2737	ERASE, 47551507836928, 47551507836928,
2738	STORE, 47551507836928, 47551507853311,
2739	STORE, 47551507853312, 47551509692415,
2740	STORE, 47551507992576, 47551509692415,
2741	STORE, 47551507853312, 47551507992575,
2742	ERASE, 47551507992576, 47551507992576,
2743	STORE, 47551507992576, 47551509651455,
2744	STORE, 47551509651456, 47551509692415,
2745	STORE, 47551509336064, 47551509651455,
2746	STORE, 47551507992576, 47551509336063,
2747	ERASE, 47551507992576, 47551507992576,
2748	STORE, 47551507992576, 47551509336063,
2749	STORE, 47551509647360, 47551509651455,
2750	STORE, 47551509336064, 47551509647359,
2751	ERASE, 47551509336064, 47551509336064,
2752	STORE, 47551509336064, 47551509647359,
2753	STORE, 47551509676032, 47551509692415,
2754	STORE, 47551509651456, 47551509676031,
2755	ERASE, 47551509651456, 47551509651456,
2756	STORE, 47551509651456, 47551509676031,
2757	ERASE, 47551509676032, 47551509676032,
2758	STORE, 47551509676032, 47551509692415,
2759	STORE, 47551509692416, 47551509827583,
2760	ERASE, 47551509692416, 47551509692416,
2761	STORE, 47551509692416, 47551509716991,
2762	STORE, 47551509716992, 47551509827583,
2763	STORE, 47551509778432, 47551509827583,
2764	STORE, 47551509716992, 47551509778431,
2765	ERASE, 47551509716992, 47551509716992,
2766	STORE, 47551509716992, 47551509778431,
2767	STORE, 47551509803008, 47551509827583,
2768	STORE, 47551509778432, 47551509803007,
2769	ERASE, 47551509778432, 47551509778432,
2770	STORE, 47551509778432, 47551509827583,
2771	ERASE, 47551509778432, 47551509778432,
2772	STORE, 47551509778432, 47551509803007,
2773	STORE, 47551509803008, 47551509827583,
2774	STORE, 47551509811200, 47551509827583,
2775	STORE, 47551509803008, 47551509811199,
2776	ERASE, 47551509803008, 47551509803008,
2777	STORE, 47551509803008, 47551509811199,
2778	ERASE, 47551509811200, 47551509811200,
2779	STORE, 47551509811200, 47551509827583,
2780	STORE, 47551509827584, 47551509848063,
2781	ERASE, 47551509827584, 47551509827584,
2782	STORE, 47551509827584, 47551509831679,
2783	STORE, 47551509831680, 47551509848063,
2784	STORE, 47551509835776, 47551509848063,
2785	STORE, 47551509831680, 47551509835775,
2786	ERASE, 47551509831680, 47551509831680,
2787	STORE, 47551509831680, 47551509835775,
2788	STORE, 47551509839872, 47551509848063,
2789	STORE, 47551509835776, 47551509839871,
2790	ERASE, 47551509835776, 47551509835776,
2791	STORE, 47551509835776, 47551509848063,
2792	ERASE, 47551509835776, 47551509835776,
2793	STORE, 47551509835776, 47551509839871,
2794	STORE, 47551509839872, 47551509848063,
2795	ERASE, 47551509839872, 47551509839872,
2796	STORE, 47551509839872, 47551509848063,
2797	STORE, 47551509848064, 47551509856255,
2798	ERASE, 47551509651456, 47551509651456,
2799	STORE, 47551509651456, 47551509667839,
2800	STORE, 47551509667840, 47551509676031,
2801	ERASE, 47551509839872, 47551509839872,
2802	STORE, 47551509839872, 47551509843967,
2803	STORE, 47551509843968, 47551509848063,
2804	ERASE, 47551509803008, 47551509803008,
2805	STORE, 47551509803008, 47551509807103,
2806	STORE, 47551509807104, 47551509811199,
2807	ERASE, 47551507632128, 47551507632128,
2808	STORE, 47551507632128, 47551507828735,
2809	STORE, 47551507828736, 47551507836927,
2810	ERASE, 47551504793600, 47551504793600,
2811	STORE, 47551504793600, 47551504797695,
2812	STORE, 47551504797696, 47551504801791,
2813	ERASE, 94150123233280, 94150123233280,
2814	STORE, 94150123233280, 94150123241471,
2815	STORE, 94150123241472, 94150123245567,
2816	ERASE, 140081290534912, 140081290534912,
2817	STORE, 140081290534912, 140081290539007,
2818	STORE, 140081290539008, 140081290543103,
2819	ERASE, 47551504621568, 47551504621568,
2820	STORE, 94150148112384, 94150148247551,
2821	STORE, 140737488347136, 140737488351231,
2822	STORE, 140734389334016, 140737488351231,
2823	ERASE, 140734389334016, 140734389334016,
2824	STORE, 140734389334016, 140734389338111,
2825	STORE, 94844636606464, 94844636778495,
2826	ERASE, 94844636606464, 94844636606464,
2827	STORE, 94844636606464, 94844636622847,
2828	STORE, 94844636622848, 94844636778495,
2829	ERASE, 94844636622848, 94844636622848,
2830	STORE, 94844636622848, 94844636725247,
2831	STORE, 94844636725248, 94844636766207,
2832	STORE, 94844636766208, 94844636778495,
2833	STORE, 139922765217792, 139922765389823,
2834	ERASE, 139922765217792, 139922765217792,
2835	STORE, 139922765217792, 139922765221887,
2836	STORE, 139922765221888, 139922765389823,
2837	ERASE, 139922765221888, 139922765221888,
2838	STORE, 139922765221888, 139922765344767,
2839	STORE, 139922765344768, 139922765377535,
2840	STORE, 139922765377536, 139922765385727,
2841	STORE, 139922765385728, 139922765389823,
2842	STORE, 140734389678080, 140734389682175,
2843	STORE, 140734389665792, 140734389678079,
2844	STORE, 47710029778944, 47710029787135,
2845	STORE, 47710029787136, 47710029795327,
2846	STORE, 47710029795328, 47710029959167,
2847	ERASE, 47710029795328, 47710029795328,
2848	STORE, 47710029795328, 47710029807615,
2849	STORE, 47710029807616, 47710029959167,
2850	STORE, 47710029905920, 47710029959167,
2851	STORE, 47710029807616, 47710029905919,
2852	ERASE, 47710029807616, 47710029807616,
2853	STORE, 47710029807616, 47710029905919,
2854	STORE, 47710029950976, 47710029959167,
2855	STORE, 47710029905920, 47710029950975,
2856	ERASE, 47710029905920, 47710029905920,
2857	STORE, 47710029905920, 47710029959167,
2858	ERASE, 47710029905920, 47710029905920,
2859	STORE, 47710029905920, 47710029950975,
2860	STORE, 47710029950976, 47710029959167,
2861	ERASE, 47710029950976, 47710029950976,
2862	STORE, 47710029950976, 47710029959167,
2863	STORE, 47710029959168, 47710033010687,
2864	STORE, 47710030503936, 47710033010687,
2865	STORE, 47710029959168, 47710030503935,
2866	ERASE, 47710030503936, 47710030503936,
2867	STORE, 47710030503936, 47710032789503,
2868	STORE, 47710032789504, 47710033010687,
2869	STORE, 47710032199680, 47710032789503,
2870	STORE, 47710030503936, 47710032199679,
2871	ERASE, 47710030503936, 47710030503936,
2872	STORE, 47710030503936, 47710032199679,
2873	STORE, 47710032785408, 47710032789503,
2874	STORE, 47710032199680, 47710032785407,
2875	ERASE, 47710032199680, 47710032199680,
2876	STORE, 47710032199680, 47710032785407,
2877	STORE, 47710032994304, 47710033010687,
2878	STORE, 47710032789504, 47710032994303,
2879	ERASE, 47710032789504, 47710032789504,
2880	STORE, 47710032789504, 47710032994303,
2881	ERASE, 47710032994304, 47710032994304,
2882	STORE, 47710032994304, 47710033010687,
2883	STORE, 47710033010688, 47710034849791,
2884	STORE, 47710033149952, 47710034849791,
2885	STORE, 47710033010688, 47710033149951,
2886	ERASE, 47710033149952, 47710033149952,
2887	STORE, 47710033149952, 47710034808831,
2888	STORE, 47710034808832, 47710034849791,
2889	STORE, 47710034493440, 47710034808831,
2890	STORE, 47710033149952, 47710034493439,
2891	ERASE, 47710033149952, 47710033149952,
2892	STORE, 47710033149952, 47710034493439,
2893	STORE, 47710034804736, 47710034808831,
2894	STORE, 47710034493440, 47710034804735,
2895	ERASE, 47710034493440, 47710034493440,
2896	STORE, 47710034493440, 47710034804735,
2897	STORE, 47710034833408, 47710034849791,
2898	STORE, 47710034808832, 47710034833407,
2899	ERASE, 47710034808832, 47710034808832,
2900	STORE, 47710034808832, 47710034833407,
2901	ERASE, 47710034833408, 47710034833408,
2902	STORE, 47710034833408, 47710034849791,
2903	STORE, 47710034849792, 47710034984959,
2904	ERASE, 47710034849792, 47710034849792,
2905	STORE, 47710034849792, 47710034874367,
2906	STORE, 47710034874368, 47710034984959,
2907	STORE, 47710034935808, 47710034984959,
2908	STORE, 47710034874368, 47710034935807,
2909	ERASE, 47710034874368, 47710034874368,
2910	STORE, 47710034874368, 47710034935807,
2911	STORE, 47710034960384, 47710034984959,
2912	STORE, 47710034935808, 47710034960383,
2913	ERASE, 47710034935808, 47710034935808,
2914	STORE, 47710034935808, 47710034984959,
2915	ERASE, 47710034935808, 47710034935808,
2916	STORE, 47710034935808, 47710034960383,
2917	STORE, 47710034960384, 47710034984959,
2918	STORE, 47710034968576, 47710034984959,
2919	STORE, 47710034960384, 47710034968575,
2920	ERASE, 47710034960384, 47710034960384,
2921	STORE, 47710034960384, 47710034968575,
2922	ERASE, 47710034968576, 47710034968576,
2923	STORE, 47710034968576, 47710034984959,
2924	STORE, 47710034984960, 47710035005439,
2925	ERASE, 47710034984960, 47710034984960,
2926	STORE, 47710034984960, 47710034989055,
2927	STORE, 47710034989056, 47710035005439,
2928	STORE, 47710034993152, 47710035005439,
2929	STORE, 47710034989056, 47710034993151,
2930	ERASE, 47710034989056, 47710034989056,
2931	STORE, 47710034989056, 47710034993151,
2932	STORE, 47710034997248, 47710035005439,
2933	STORE, 47710034993152, 47710034997247,
2934	ERASE, 47710034993152, 47710034993152,
2935	STORE, 47710034993152, 47710035005439,
2936	ERASE, 47710034993152, 47710034993152,
2937	STORE, 47710034993152, 47710034997247,
2938	STORE, 47710034997248, 47710035005439,
2939	ERASE, 47710034997248, 47710034997248,
2940	STORE, 47710034997248, 47710035005439,
2941	STORE, 47710035005440, 47710035013631,
2942	ERASE, 47710034808832, 47710034808832,
2943	STORE, 47710034808832, 47710034825215,
2944	STORE, 47710034825216, 47710034833407,
2945	ERASE, 47710034997248, 47710034997248,
2946	STORE, 47710034997248, 47710035001343,
2947	STORE, 47710035001344, 47710035005439,
2948	ERASE, 47710034960384, 47710034960384,
2949	STORE, 47710034960384, 47710034964479,
2950	STORE, 47710034964480, 47710034968575,
2951	ERASE, 47710032789504, 47710032789504,
2952	STORE, 47710032789504, 47710032986111,
2953	STORE, 47710032986112, 47710032994303,
2954	ERASE, 47710029950976, 47710029950976,
2955	STORE, 47710029950976, 47710029955071,
2956	STORE, 47710029955072, 47710029959167,
2957	ERASE, 94844636766208, 94844636766208,
2958	STORE, 94844636766208, 94844636774399,
2959	STORE, 94844636774400, 94844636778495,
2960	ERASE, 139922765377536, 139922765377536,
2961	STORE, 139922765377536, 139922765381631,
2962	STORE, 139922765381632, 139922765385727,
2963	ERASE, 47710029778944, 47710029778944,
2964	STORE, 94844641775616, 94844641910783,
2965	STORE, 140737488347136, 140737488351231,
2966	STORE, 140732213886976, 140737488351231,
2967	ERASE, 140732213886976, 140732213886976,
2968	STORE, 140732213886976, 140732213891071,
2969	STORE, 94240508887040, 94240509059071,
2970	ERASE, 94240508887040, 94240508887040,
2971	STORE, 94240508887040, 94240508903423,
2972	STORE, 94240508903424, 94240509059071,
2973	ERASE, 94240508903424, 94240508903424,
2974	STORE, 94240508903424, 94240509005823,
2975	STORE, 94240509005824, 94240509046783,
2976	STORE, 94240509046784, 94240509059071,
2977	STORE, 140275106516992, 140275106689023,
2978	ERASE, 140275106516992, 140275106516992,
2979	STORE, 140275106516992, 140275106521087,
2980	STORE, 140275106521088, 140275106689023,
2981	ERASE, 140275106521088, 140275106521088,
2982	STORE, 140275106521088, 140275106643967,
2983	STORE, 140275106643968, 140275106676735,
2984	STORE, 140275106676736, 140275106684927,
2985	STORE, 140275106684928, 140275106689023,
2986	STORE, 140732213977088, 140732213981183,
2987	STORE, 140732213964800, 140732213977087,
2988	STORE, 47357688479744, 47357688487935,
2989	STORE, 47357688487936, 47357688496127,
2990	STORE, 47357688496128, 47357688659967,
2991	ERASE, 47357688496128, 47357688496128,
2992	STORE, 47357688496128, 47357688508415,
2993	STORE, 47357688508416, 47357688659967,
2994	STORE, 47357688606720, 47357688659967,
2995	STORE, 47357688508416, 47357688606719,
2996	ERASE, 47357688508416, 47357688508416,
2997	STORE, 47357688508416, 47357688606719,
2998	STORE, 47357688651776, 47357688659967,
2999	STORE, 47357688606720, 47357688651775,
3000	ERASE, 47357688606720, 47357688606720,
3001	STORE, 47357688606720, 47357688659967,
3002	ERASE, 47357688606720, 47357688606720,
3003	STORE, 47357688606720, 47357688651775,
3004	STORE, 47357688651776, 47357688659967,
3005	ERASE, 47357688651776, 47357688651776,
3006	STORE, 47357688651776, 47357688659967,
3007	STORE, 47357688659968, 47357691711487,
3008	STORE, 47357689204736, 47357691711487,
3009	STORE, 47357688659968, 47357689204735,
3010	ERASE, 47357689204736, 47357689204736,
3011	STORE, 47357689204736, 47357691490303,
3012	STORE, 47357691490304, 47357691711487,
3013	STORE, 47357690900480, 47357691490303,
3014	STORE, 47357689204736, 47357690900479,
3015	ERASE, 47357689204736, 47357689204736,
3016	STORE, 47357689204736, 47357690900479,
3017	STORE, 47357691486208, 47357691490303,
3018	STORE, 47357690900480, 47357691486207,
3019	ERASE, 47357690900480, 47357690900480,
3020	STORE, 47357690900480, 47357691486207,
3021	STORE, 47357691695104, 47357691711487,
3022	STORE, 47357691490304, 47357691695103,
3023	ERASE, 47357691490304, 47357691490304,
3024	STORE, 47357691490304, 47357691695103,
3025	ERASE, 47357691695104, 47357691695104,
3026	STORE, 47357691695104, 47357691711487,
3027	STORE, 47357691711488, 47357693550591,
3028	STORE, 47357691850752, 47357693550591,
3029	STORE, 47357691711488, 47357691850751,
3030	ERASE, 47357691850752, 47357691850752,
3031	STORE, 47357691850752, 47357693509631,
3032	STORE, 47357693509632, 47357693550591,
3033	STORE, 47357693194240, 47357693509631,
3034	STORE, 47357691850752, 47357693194239,
3035	ERASE, 47357691850752, 47357691850752,
3036	STORE, 47357691850752, 47357693194239,
3037	STORE, 47357693505536, 47357693509631,
3038	STORE, 47357693194240, 47357693505535,
3039	ERASE, 47357693194240, 47357693194240,
3040	STORE, 47357693194240, 47357693505535,
3041	STORE, 47357693534208, 47357693550591,
3042	STORE, 47357693509632, 47357693534207,
3043	ERASE, 47357693509632, 47357693509632,
3044	STORE, 47357693509632, 47357693534207,
3045	ERASE, 47357693534208, 47357693534208,
3046	STORE, 47357693534208, 47357693550591,
3047	STORE, 47357693550592, 47357693685759,
3048	ERASE, 47357693550592, 47357693550592,
3049	STORE, 47357693550592, 47357693575167,
3050	STORE, 47357693575168, 47357693685759,
3051	STORE, 47357693636608, 47357693685759,
3052	STORE, 47357693575168, 47357693636607,
3053	ERASE, 47357693575168, 47357693575168,
3054	STORE, 47357693575168, 47357693636607,
3055	STORE, 47357693661184, 47357693685759,
3056	STORE, 47357693636608, 47357693661183,
3057	ERASE, 47357693636608, 47357693636608,
3058	STORE, 47357693636608, 47357693685759,
3059	ERASE, 47357693636608, 47357693636608,
3060	STORE, 47357693636608, 47357693661183,
3061	STORE, 47357693661184, 47357693685759,
3062	STORE, 47357693669376, 47357693685759,
3063	STORE, 47357693661184, 47357693669375,
3064	ERASE, 47357693661184, 47357693661184,
3065	STORE, 47357693661184, 47357693669375,
3066	ERASE, 47357693669376, 47357693669376,
3067	STORE, 47357693669376, 47357693685759,
3068	STORE, 47357693685760, 47357693706239,
3069	ERASE, 47357693685760, 47357693685760,
3070	STORE, 47357693685760, 47357693689855,
3071	STORE, 47357693689856, 47357693706239,
3072	STORE, 47357693693952, 47357693706239,
3073	STORE, 47357693689856, 47357693693951,
3074	ERASE, 47357693689856, 47357693689856,
3075	STORE, 47357693689856, 47357693693951,
3076	STORE, 47357693698048, 47357693706239,
3077	STORE, 47357693693952, 47357693698047,
3078	ERASE, 47357693693952, 47357693693952,
3079	STORE, 47357693693952, 47357693706239,
3080	ERASE, 47357693693952, 47357693693952,
3081	STORE, 47357693693952, 47357693698047,
3082	STORE, 47357693698048, 47357693706239,
3083	ERASE, 47357693698048, 47357693698048,
3084	STORE, 47357693698048, 47357693706239,
3085	STORE, 47357693706240, 47357693714431,
3086	ERASE, 47357693509632, 47357693509632,
3087	STORE, 47357693509632, 47357693526015,
3088	STORE, 47357693526016, 47357693534207,
3089	ERASE, 47357693698048, 47357693698048,
3090	STORE, 47357693698048, 47357693702143,
3091	STORE, 47357693702144, 47357693706239,
3092	ERASE, 47357693661184, 47357693661184,
3093	STORE, 47357693661184, 47357693665279,
3094	STORE, 47357693665280, 47357693669375,
3095	ERASE, 47357691490304, 47357691490304,
3096	STORE, 47357691490304, 47357691686911,
3097	STORE, 47357691686912, 47357691695103,
3098	ERASE, 47357688651776, 47357688651776,
3099	STORE, 47357688651776, 47357688655871,
3100	STORE, 47357688655872, 47357688659967,
3101	ERASE, 94240509046784, 94240509046784,
3102	STORE, 94240509046784, 94240509054975,
3103	STORE, 94240509054976, 94240509059071,
3104	ERASE, 140275106676736, 140275106676736,
3105	STORE, 140275106676736, 140275106680831,
3106	STORE, 140275106680832, 140275106684927,
3107	ERASE, 47357688479744, 47357688479744,
3108	STORE, 94240518361088, 94240518496255,
3109	STORE, 140737488347136, 140737488351231,
3110	STORE, 140732688277504, 140737488351231,
3111	ERASE, 140732688277504, 140732688277504,
3112	STORE, 140732688277504, 140732688281599,
3113	STORE, 94629171351552, 94629172064255,
3114	ERASE, 94629171351552, 94629171351552,
3115	STORE, 94629171351552, 94629171400703,
3116	STORE, 94629171400704, 94629172064255,
3117	ERASE, 94629171400704, 94629171400704,
3118	STORE, 94629171400704, 94629171945471,
3119	STORE, 94629171945472, 94629172043775,
3120	STORE, 94629172043776, 94629172064255,
3121	STORE, 139770707644416, 139770707816447,
3122	ERASE, 139770707644416, 139770707644416,
3123	STORE, 139770707644416, 139770707648511,
3124	STORE, 139770707648512, 139770707816447,
3125	ERASE, 139770707648512, 139770707648512,
3126	STORE, 139770707648512, 139770707771391,
3127	STORE, 139770707771392, 139770707804159,
3128	STORE, 139770707804160, 139770707812351,
3129	STORE, 139770707812352, 139770707816447,
3130	STORE, 140732689121280, 140732689125375,
3131	STORE, 140732689108992, 140732689121279,
3132	STORE, 47862087352320, 47862087360511,
3133	STORE, 47862087360512, 47862087368703,
3134	STORE, 47862087368704, 47862087475199,
3135	STORE, 47862087385088, 47862087475199,
3136	STORE, 47862087368704, 47862087385087,
3137	ERASE, 47862087385088, 47862087385088,
3138	STORE, 47862087385088, 47862087458815,
3139	STORE, 47862087458816, 47862087475199,
3140	STORE, 47862087438336, 47862087458815,
3141	STORE, 47862087385088, 47862087438335,
3142	ERASE, 47862087385088, 47862087385088,
3143	STORE, 47862087385088, 47862087438335,
3144	STORE, 47862087454720, 47862087458815,
3145	STORE, 47862087438336, 47862087454719,
3146	ERASE, 47862087438336, 47862087438336,
3147	STORE, 47862087438336, 47862087454719,
3148	STORE, 47862087467008, 47862087475199,
3149	STORE, 47862087458816, 47862087467007,
3150	ERASE, 47862087458816, 47862087458816,
3151	STORE, 47862087458816, 47862087467007,
3152	ERASE, 47862087467008, 47862087467008,
3153	STORE, 47862087467008, 47862087475199,
3154	STORE, 47862087475200, 47862089314303,
3155	STORE, 47862087614464, 47862089314303,
3156	STORE, 47862087475200, 47862087614463,
3157	ERASE, 47862087614464, 47862087614464,
3158	STORE, 47862087614464, 47862089273343,
3159	STORE, 47862089273344, 47862089314303,
3160	STORE, 47862088957952, 47862089273343,
3161	STORE, 47862087614464, 47862088957951,
3162	ERASE, 47862087614464, 47862087614464,
3163	STORE, 47862087614464, 47862088957951,
3164	STORE, 47862089269248, 47862089273343,
3165	STORE, 47862088957952, 47862089269247,
3166	ERASE, 47862088957952, 47862088957952,
3167	STORE, 47862088957952, 47862089269247,
3168	STORE, 47862089297920, 47862089314303,
3169	STORE, 47862089273344, 47862089297919,
3170	ERASE, 47862089273344, 47862089273344,
3171	STORE, 47862089273344, 47862089297919,
3172	ERASE, 47862089297920, 47862089297920,
3173	STORE, 47862089297920, 47862089314303,
3174	STORE, 47862089297920, 47862089326591,
3175	ERASE, 47862089273344, 47862089273344,
3176	STORE, 47862089273344, 47862089289727,
3177	STORE, 47862089289728, 47862089297919,
3178	ERASE, 47862087458816, 47862087458816,
3179	STORE, 47862087458816, 47862087462911,
3180	STORE, 47862087462912, 47862087467007,
3181	ERASE, 94629172043776, 94629172043776,
3182	STORE, 94629172043776, 94629172060159,
3183	STORE, 94629172060160, 94629172064255,
3184	ERASE, 139770707804160, 139770707804160,
3185	STORE, 139770707804160, 139770707808255,
3186	STORE, 139770707808256, 139770707812351,
3187	ERASE, 47862087352320, 47862087352320,
3188	STORE, 94629197533184, 94629197668351,
3189	STORE, 140737488347136, 140737488351231,
3190	STORE, 140727540711424, 140737488351231,
3191	ERASE, 140727540711424, 140727540711424,
3192	STORE, 140727540711424, 140727540715519,
3193	STORE, 94299865313280, 94299866025983,
3194	ERASE, 94299865313280, 94299865313280,
3195	STORE, 94299865313280, 94299865362431,
3196	STORE, 94299865362432, 94299866025983,
3197	ERASE, 94299865362432, 94299865362432,
3198	STORE, 94299865362432, 94299865907199,
3199	STORE, 94299865907200, 94299866005503,
3200	STORE, 94299866005504, 94299866025983,
3201	STORE, 140680268763136, 140680268935167,
3202	ERASE, 140680268763136, 140680268763136,
3203	STORE, 140680268763136, 140680268767231,
3204	STORE, 140680268767232, 140680268935167,
3205	ERASE, 140680268767232, 140680268767232,
3206	STORE, 140680268767232, 140680268890111,
3207	STORE, 140680268890112, 140680268922879,
3208	STORE, 140680268922880, 140680268931071,
3209	STORE, 140680268931072, 140680268935167,
3210	STORE, 140727541424128, 140727541428223,
3211	STORE, 140727541411840, 140727541424127,
3212	STORE, 46952526233600, 46952526241791,
3213	STORE, 46952526241792, 46952526249983,
3214	STORE, 46952526249984, 46952526356479,
3215	STORE, 46952526266368, 46952526356479,
3216	STORE, 46952526249984, 46952526266367,
3217	ERASE, 46952526266368, 46952526266368,
3218	STORE, 46952526266368, 46952526340095,
3219	STORE, 46952526340096, 46952526356479,
3220	STORE, 46952526319616, 46952526340095,
3221	STORE, 46952526266368, 46952526319615,
3222	ERASE, 46952526266368, 46952526266368,
3223	STORE, 46952526266368, 46952526319615,
3224	STORE, 46952526336000, 46952526340095,
3225	STORE, 46952526319616, 46952526335999,
3226	ERASE, 46952526319616, 46952526319616,
3227	STORE, 46952526319616, 46952526335999,
3228	STORE, 46952526348288, 46952526356479,
3229	STORE, 46952526340096, 46952526348287,
3230	ERASE, 46952526340096, 46952526340096,
3231	STORE, 46952526340096, 46952526348287,
3232	ERASE, 46952526348288, 46952526348288,
3233	STORE, 46952526348288, 46952526356479,
3234	STORE, 46952526356480, 46952528195583,
3235	STORE, 46952526495744, 46952528195583,
3236	STORE, 46952526356480, 46952526495743,
3237	ERASE, 46952526495744, 46952526495744,
3238	STORE, 46952526495744, 46952528154623,
3239	STORE, 46952528154624, 46952528195583,
3240	STORE, 46952527839232, 46952528154623,
3241	STORE, 46952526495744, 46952527839231,
3242	ERASE, 46952526495744, 46952526495744,
3243	STORE, 46952526495744, 46952527839231,
3244	STORE, 46952528150528, 46952528154623,
3245	STORE, 46952527839232, 46952528150527,
3246	ERASE, 46952527839232, 46952527839232,
3247	STORE, 46952527839232, 46952528150527,
3248	STORE, 46952528179200, 46952528195583,
3249	STORE, 46952528154624, 46952528179199,
3250	ERASE, 46952528154624, 46952528154624,
3251	STORE, 46952528154624, 46952528179199,
3252	ERASE, 46952528179200, 46952528179200,
3253	STORE, 46952528179200, 46952528195583,
3254	STORE, 46952528179200, 46952528207871,
3255	ERASE, 46952528154624, 46952528154624,
3256	STORE, 46952528154624, 46952528171007,
3257	STORE, 46952528171008, 46952528179199,
3258	ERASE, 46952526340096, 46952526340096,
3259	STORE, 46952526340096, 46952526344191,
3260	STORE, 46952526344192, 46952526348287,
3261	ERASE, 94299866005504, 94299866005504,
3262	STORE, 94299866005504, 94299866021887,
3263	STORE, 94299866021888, 94299866025983,
3264	ERASE, 140680268922880, 140680268922880,
3265	STORE, 140680268922880, 140680268926975,
3266	STORE, 140680268926976, 140680268931071,
3267	ERASE, 46952526233600, 46952526233600,
3268	STORE, 140737488347136, 140737488351231,
3269	STORE, 140722874793984, 140737488351231,
3270	ERASE, 140722874793984, 140722874793984,
3271	STORE, 140722874793984, 140722874798079,
3272	STORE, 94448916213760, 94448916926463,
3273	ERASE, 94448916213760, 94448916213760,
3274	STORE, 94448916213760, 94448916262911,
3275	STORE, 94448916262912, 94448916926463,
3276	ERASE, 94448916262912, 94448916262912,
3277	STORE, 94448916262912, 94448916807679,
3278	STORE, 94448916807680, 94448916905983,
3279	STORE, 94448916905984, 94448916926463,
3280	STORE, 140389117046784, 140389117218815,
3281	ERASE, 140389117046784, 140389117046784,
3282	STORE, 140389117046784, 140389117050879,
3283	STORE, 140389117050880, 140389117218815,
3284	ERASE, 140389117050880, 140389117050880,
3285	STORE, 140389117050880, 140389117173759,
3286	STORE, 140389117173760, 140389117206527,
3287	STORE, 140389117206528, 140389117214719,
3288	STORE, 140389117214720, 140389117218815,
3289	STORE, 140722875297792, 140722875301887,
3290	STORE, 140722875285504, 140722875297791,
3291	STORE, 47243677949952, 47243677958143,
3292	STORE, 47243677958144, 47243677966335,
3293	STORE, 47243677966336, 47243678072831,
3294	STORE, 47243677982720, 47243678072831,
3295	STORE, 47243677966336, 47243677982719,
3296	ERASE, 47243677982720, 47243677982720,
3297	STORE, 47243677982720, 47243678056447,
3298	STORE, 47243678056448, 47243678072831,
3299	STORE, 47243678035968, 47243678056447,
3300	STORE, 47243677982720, 47243678035967,
3301	ERASE, 47243677982720, 47243677982720,
3302	STORE, 47243677982720, 47243678035967,
3303	STORE, 47243678052352, 47243678056447,
3304	STORE, 47243678035968, 47243678052351,
3305	ERASE, 47243678035968, 47243678035968,
3306	STORE, 47243678035968, 47243678052351,
3307	STORE, 47243678064640, 47243678072831,
3308	STORE, 47243678056448, 47243678064639,
3309	ERASE, 47243678056448, 47243678056448,
3310	STORE, 47243678056448, 47243678064639,
3311	ERASE, 47243678064640, 47243678064640,
3312	STORE, 47243678064640, 47243678072831,
3313	STORE, 47243678072832, 47243679911935,
3314	STORE, 47243678212096, 47243679911935,
3315	STORE, 47243678072832, 47243678212095,
3316	ERASE, 47243678212096, 47243678212096,
3317	STORE, 47243678212096, 47243679870975,
3318	STORE, 47243679870976, 47243679911935,
3319	STORE, 47243679555584, 47243679870975,
3320	STORE, 47243678212096, 47243679555583,
3321	ERASE, 47243678212096, 47243678212096,
3322	STORE, 47243678212096, 47243679555583,
3323	STORE, 47243679866880, 47243679870975,
3324	STORE, 47243679555584, 47243679866879,
3325	ERASE, 47243679555584, 47243679555584,
3326	STORE, 47243679555584, 47243679866879,
3327	STORE, 47243679895552, 47243679911935,
3328	STORE, 47243679870976, 47243679895551,
3329	ERASE, 47243679870976, 47243679870976,
3330	STORE, 47243679870976, 47243679895551,
3331	ERASE, 47243679895552, 47243679895552,
3332	STORE, 47243679895552, 47243679911935,
3333	STORE, 47243679895552, 47243679924223,
3334	ERASE, 47243679870976, 47243679870976,
3335	STORE, 47243679870976, 47243679887359,
3336	STORE, 47243679887360, 47243679895551,
3337	ERASE, 47243678056448, 47243678056448,
3338	STORE, 47243678056448, 47243678060543,
3339	STORE, 47243678060544, 47243678064639,
3340	ERASE, 94448916905984, 94448916905984,
3341	STORE, 94448916905984, 94448916922367,
3342	STORE, 94448916922368, 94448916926463,
3343	ERASE, 140389117206528, 140389117206528,
3344	STORE, 140389117206528, 140389117210623,
3345	STORE, 140389117210624, 140389117214719,
3346	ERASE, 47243677949952, 47243677949952,
3347	STORE, 140737488347136, 140737488351231,
3348	STORE, 140733068505088, 140737488351231,
3349	ERASE, 140733068505088, 140733068505088,
3350	STORE, 140733068505088, 140733068509183,
3351	STORE, 94207145750528, 94207146463231,
3352	ERASE, 94207145750528, 94207145750528,
3353	STORE, 94207145750528, 94207145799679,
3354	STORE, 94207145799680, 94207146463231,
3355	ERASE, 94207145799680, 94207145799680,
3356	STORE, 94207145799680, 94207146344447,
3357	STORE, 94207146344448, 94207146442751,
3358	STORE, 94207146442752, 94207146463231,
3359	STORE, 140684504911872, 140684505083903,
3360	ERASE, 140684504911872, 140684504911872,
3361	STORE, 140684504911872, 140684504915967,
3362	STORE, 140684504915968, 140684505083903,
3363	ERASE, 140684504915968, 140684504915968,
3364	STORE, 140684504915968, 140684505038847,
3365	STORE, 140684505038848, 140684505071615,
3366	STORE, 140684505071616, 140684505079807,
3367	STORE, 140684505079808, 140684505083903,
3368	STORE, 140733068607488, 140733068611583,
3369	STORE, 140733068595200, 140733068607487,
3370	STORE, 46948290084864, 46948290093055,
3371	STORE, 46948290093056, 46948290101247,
3372	STORE, 46948290101248, 46948290207743,
3373	STORE, 46948290117632, 46948290207743,
3374	STORE, 46948290101248, 46948290117631,
3375	ERASE, 46948290117632, 46948290117632,
3376	STORE, 46948290117632, 46948290191359,
3377	STORE, 46948290191360, 46948290207743,
3378	STORE, 46948290170880, 46948290191359,
3379	STORE, 46948290117632, 46948290170879,
3380	ERASE, 46948290117632, 46948290117632,
3381	STORE, 46948290117632, 46948290170879,
3382	STORE, 46948290187264, 46948290191359,
3383	STORE, 46948290170880, 46948290187263,
3384	ERASE, 46948290170880, 46948290170880,
3385	STORE, 46948290170880, 46948290187263,
3386	STORE, 46948290199552, 46948290207743,
3387	STORE, 46948290191360, 46948290199551,
3388	ERASE, 46948290191360, 46948290191360,
3389	STORE, 46948290191360, 46948290199551,
3390	ERASE, 46948290199552, 46948290199552,
3391	STORE, 46948290199552, 46948290207743,
3392	STORE, 46948290207744, 46948292046847,
3393	STORE, 46948290347008, 46948292046847,
3394	STORE, 46948290207744, 46948290347007,
3395	ERASE, 46948290347008, 46948290347008,
3396	STORE, 46948290347008, 46948292005887,
3397	STORE, 46948292005888, 46948292046847,
3398	STORE, 46948291690496, 46948292005887,
3399	STORE, 46948290347008, 46948291690495,
3400	ERASE, 46948290347008, 46948290347008,
3401	STORE, 46948290347008, 46948291690495,
3402	STORE, 46948292001792, 46948292005887,
3403	STORE, 46948291690496, 46948292001791,
3404	ERASE, 46948291690496, 46948291690496,
3405	STORE, 46948291690496, 46948292001791,
3406	STORE, 46948292030464, 46948292046847,
3407	STORE, 46948292005888, 46948292030463,
3408	ERASE, 46948292005888, 46948292005888,
3409	STORE, 46948292005888, 46948292030463,
3410	ERASE, 46948292030464, 46948292030464,
3411	STORE, 46948292030464, 46948292046847,
3412	STORE, 46948292030464, 46948292059135,
3413	ERASE, 46948292005888, 46948292005888,
3414	STORE, 46948292005888, 46948292022271,
3415	STORE, 46948292022272, 46948292030463,
3416	ERASE, 46948290191360, 46948290191360,
3417	STORE, 46948290191360, 46948290195455,
3418	STORE, 46948290195456, 46948290199551,
3419	ERASE, 94207146442752, 94207146442752,
3420	STORE, 94207146442752, 94207146459135,
3421	STORE, 94207146459136, 94207146463231,
3422	ERASE, 140684505071616, 140684505071616,
3423	STORE, 140684505071616, 140684505075711,
3424	STORE, 140684505075712, 140684505079807,
3425	ERASE, 46948290084864, 46948290084864,
3426	STORE, 140737488347136, 140737488351231,
3427	STORE, 140726367158272, 140737488351231,
3428	ERASE, 140726367158272, 140726367158272,
3429	STORE, 140726367158272, 140726367162367,
3430	STORE, 94436124106752, 94436124819455,
3431	ERASE, 94436124106752, 94436124106752,
3432	STORE, 94436124106752, 94436124155903,
3433	STORE, 94436124155904, 94436124819455,
3434	ERASE, 94436124155904, 94436124155904,
3435	STORE, 94436124155904, 94436124700671,
3436	STORE, 94436124700672, 94436124798975,
3437	STORE, 94436124798976, 94436124819455,
3438	STORE, 140049025044480, 140049025216511,
3439	ERASE, 140049025044480, 140049025044480,
3440	STORE, 140049025044480, 140049025048575,
3441	STORE, 140049025048576, 140049025216511,
3442	ERASE, 140049025048576, 140049025048576,
3443	STORE, 140049025048576, 140049025171455,
3444	STORE, 140049025171456, 140049025204223,
3445	STORE, 140049025204224, 140049025212415,
3446	STORE, 140049025212416, 140049025216511,
3447	STORE, 140726367256576, 140726367260671,
3448	STORE, 140726367244288, 140726367256575,
3449	STORE, 47583769952256, 47583769960447,
3450	STORE, 47583769960448, 47583769968639,
3451	STORE, 47583769968640, 47583770075135,
3452	STORE, 47583769985024, 47583770075135,
3453	STORE, 47583769968640, 47583769985023,
3454	ERASE, 47583769985024, 47583769985024,
3455	STORE, 47583769985024, 47583770058751,
3456	STORE, 47583770058752, 47583770075135,
3457	STORE, 47583770038272, 47583770058751,
3458	STORE, 47583769985024, 47583770038271,
3459	ERASE, 47583769985024, 47583769985024,
3460	STORE, 47583769985024, 47583770038271,
3461	STORE, 47583770054656, 47583770058751,
3462	STORE, 47583770038272, 47583770054655,
3463	ERASE, 47583770038272, 47583770038272,
3464	STORE, 47583770038272, 47583770054655,
3465	STORE, 47583770066944, 47583770075135,
3466	STORE, 47583770058752, 47583770066943,
3467	ERASE, 47583770058752, 47583770058752,
3468	STORE, 47583770058752, 47583770066943,
3469	ERASE, 47583770066944, 47583770066944,
3470	STORE, 47583770066944, 47583770075135,
3471	STORE, 47583770075136, 47583771914239,
3472	STORE, 47583770214400, 47583771914239,
3473	STORE, 47583770075136, 47583770214399,
3474	ERASE, 47583770214400, 47583770214400,
3475	STORE, 47583770214400, 47583771873279,
3476	STORE, 47583771873280, 47583771914239,
3477	STORE, 47583771557888, 47583771873279,
3478	STORE, 47583770214400, 47583771557887,
3479	ERASE, 47583770214400, 47583770214400,
3480	STORE, 47583770214400, 47583771557887,
3481	STORE, 47583771869184, 47583771873279,
3482	STORE, 47583771557888, 47583771869183,
3483	ERASE, 47583771557888, 47583771557888,
3484	STORE, 47583771557888, 47583771869183,
3485	STORE, 47583771897856, 47583771914239,
3486	STORE, 47583771873280, 47583771897855,
3487	ERASE, 47583771873280, 47583771873280,
3488	STORE, 47583771873280, 47583771897855,
3489	ERASE, 47583771897856, 47583771897856,
3490	STORE, 47583771897856, 47583771914239,
3491	STORE, 47583771897856, 47583771926527,
3492	ERASE, 47583771873280, 47583771873280,
3493	STORE, 47583771873280, 47583771889663,
3494	STORE, 47583771889664, 47583771897855,
3495	ERASE, 47583770058752, 47583770058752,
3496	STORE, 47583770058752, 47583770062847,
3497	STORE, 47583770062848, 47583770066943,
3498	ERASE, 94436124798976, 94436124798976,
3499	STORE, 94436124798976, 94436124815359,
3500	STORE, 94436124815360, 94436124819455,
3501	ERASE, 140049025204224, 140049025204224,
3502	STORE, 140049025204224, 140049025208319,
3503	STORE, 140049025208320, 140049025212415,
3504	ERASE, 47583769952256, 47583769952256,
3505	STORE, 140737488347136, 140737488351231,
3506	STORE, 140727116099584, 140737488351231,
3507	ERASE, 140727116099584, 140727116099584,
3508	STORE, 140727116099584, 140727116103679,
3509	STORE, 94166319734784, 94166320447487,
3510	ERASE, 94166319734784, 94166319734784,
3511	STORE, 94166319734784, 94166319783935,
3512	STORE, 94166319783936, 94166320447487,
3513	ERASE, 94166319783936, 94166319783936,
3514	STORE, 94166319783936, 94166320328703,
3515	STORE, 94166320328704, 94166320427007,
3516	STORE, 94166320427008, 94166320447487,
3517	STORE, 139976559542272, 139976559714303,
3518	ERASE, 139976559542272, 139976559542272,
3519	STORE, 139976559542272, 139976559546367,
3520	STORE, 139976559546368, 139976559714303,
3521	ERASE, 139976559546368, 139976559546368,
3522	STORE, 139976559546368, 139976559669247,
3523	STORE, 139976559669248, 139976559702015,
3524	STORE, 139976559702016, 139976559710207,
3525	STORE, 139976559710208, 139976559714303,
3526	STORE, 140727116222464, 140727116226559,
3527	STORE, 140727116210176, 140727116222463,
3528	STORE, 47656235454464, 47656235462655,
3529	STORE, 47656235462656, 47656235470847,
3530	STORE, 47656235470848, 47656235577343,
3531	STORE, 47656235487232, 47656235577343,
3532	STORE, 47656235470848, 47656235487231,
3533	ERASE, 47656235487232, 47656235487232,
3534	STORE, 47656235487232, 47656235560959,
3535	STORE, 47656235560960, 47656235577343,
3536	STORE, 47656235540480, 47656235560959,
3537	STORE, 47656235487232, 47656235540479,
3538	ERASE, 47656235487232, 47656235487232,
3539	STORE, 47656235487232, 47656235540479,
3540	STORE, 47656235556864, 47656235560959,
3541	STORE, 47656235540480, 47656235556863,
3542	ERASE, 47656235540480, 47656235540480,
3543	STORE, 47656235540480, 47656235556863,
3544	STORE, 47656235569152, 47656235577343,
3545	STORE, 47656235560960, 47656235569151,
3546	ERASE, 47656235560960, 47656235560960,
3547	STORE, 47656235560960, 47656235569151,
3548	ERASE, 47656235569152, 47656235569152,
3549	STORE, 47656235569152, 47656235577343,
3550	STORE, 47656235577344, 47656237416447,
3551	STORE, 47656235716608, 47656237416447,
3552	STORE, 47656235577344, 47656235716607,
3553	ERASE, 47656235716608, 47656235716608,
3554	STORE, 47656235716608, 47656237375487,
3555	STORE, 47656237375488, 47656237416447,
3556	STORE, 47656237060096, 47656237375487,
3557	STORE, 47656235716608, 47656237060095,
3558	ERASE, 47656235716608, 47656235716608,
3559	STORE, 47656235716608, 47656237060095,
3560	STORE, 47656237371392, 47656237375487,
3561	STORE, 47656237060096, 47656237371391,
3562	ERASE, 47656237060096, 47656237060096,
3563	STORE, 47656237060096, 47656237371391,
3564	STORE, 47656237400064, 47656237416447,
3565	STORE, 47656237375488, 47656237400063,
3566	ERASE, 47656237375488, 47656237375488,
3567	STORE, 47656237375488, 47656237400063,
3568	ERASE, 47656237400064, 47656237400064,
3569	STORE, 47656237400064, 47656237416447,
3570	STORE, 47656237400064, 47656237428735,
3571	ERASE, 47656237375488, 47656237375488,
3572	STORE, 47656237375488, 47656237391871,
3573	STORE, 47656237391872, 47656237400063,
3574	ERASE, 47656235560960, 47656235560960,
3575	STORE, 47656235560960, 47656235565055,
3576	STORE, 47656235565056, 47656235569151,
3577	ERASE, 94166320427008, 94166320427008,
3578	STORE, 94166320427008, 94166320443391,
3579	STORE, 94166320443392, 94166320447487,
3580	ERASE, 139976559702016, 139976559702016,
3581	STORE, 139976559702016, 139976559706111,
3582	STORE, 139976559706112, 139976559710207,
3583	ERASE, 47656235454464, 47656235454464,
3584	STORE, 94166332153856, 94166332289023,
3585	STORE, 140737488347136, 140737488351231,
3586	STORE, 140726412816384, 140737488351231,
3587	ERASE, 140726412816384, 140726412816384,
3588	STORE, 140726412816384, 140726412820479,
3589	STORE, 94094884507648, 94094885220351,
3590	ERASE, 94094884507648, 94094884507648,
3591	STORE, 94094884507648, 94094884556799,
3592	STORE, 94094884556800, 94094885220351,
3593	ERASE, 94094884556800, 94094884556800,
3594	STORE, 94094884556800, 94094885101567,
3595	STORE, 94094885101568, 94094885199871,
3596	STORE, 94094885199872, 94094885220351,
3597	STORE, 139773773938688, 139773774110719,
3598	ERASE, 139773773938688, 139773773938688,
3599	STORE, 139773773938688, 139773773942783,
3600	STORE, 139773773942784, 139773774110719,
3601	ERASE, 139773773942784, 139773773942784,
3602	STORE, 139773773942784, 139773774065663,
3603	STORE, 139773774065664, 139773774098431,
3604	STORE, 139773774098432, 139773774106623,
3605	STORE, 139773774106624, 139773774110719,
3606	STORE, 140726412963840, 140726412967935,
3607	STORE, 140726412951552, 140726412963839,
3608	STORE, 47859021058048, 47859021066239,
3609	STORE, 47859021066240, 47859021074431,
3610	STORE, 47859021074432, 47859021180927,
3611	STORE, 47859021090816, 47859021180927,
3612	STORE, 47859021074432, 47859021090815,
3613	ERASE, 47859021090816, 47859021090816,
3614	STORE, 47859021090816, 47859021164543,
3615	STORE, 47859021164544, 47859021180927,
3616	STORE, 47859021144064, 47859021164543,
3617	STORE, 47859021090816, 47859021144063,
3618	ERASE, 47859021090816, 47859021090816,
3619	STORE, 47859021090816, 47859021144063,
3620	STORE, 47859021160448, 47859021164543,
3621	STORE, 47859021144064, 47859021160447,
3622	ERASE, 47859021144064, 47859021144064,
3623	STORE, 47859021144064, 47859021160447,
3624	STORE, 47859021172736, 47859021180927,
3625	STORE, 47859021164544, 47859021172735,
3626	ERASE, 47859021164544, 47859021164544,
3627	STORE, 47859021164544, 47859021172735,
3628	ERASE, 47859021172736, 47859021172736,
3629	STORE, 47859021172736, 47859021180927,
3630	STORE, 47859021180928, 47859023020031,
3631	STORE, 47859021320192, 47859023020031,
3632	STORE, 47859021180928, 47859021320191,
3633	ERASE, 47859021320192, 47859021320192,
3634	STORE, 47859021320192, 47859022979071,
3635	STORE, 47859022979072, 47859023020031,
3636	STORE, 47859022663680, 47859022979071,
3637	STORE, 47859021320192, 47859022663679,
3638	ERASE, 47859021320192, 47859021320192,
3639	STORE, 47859021320192, 47859022663679,
3640	STORE, 47859022974976, 47859022979071,
3641	STORE, 47859022663680, 47859022974975,
3642	ERASE, 47859022663680, 47859022663680,
3643	STORE, 47859022663680, 47859022974975,
3644	STORE, 47859023003648, 47859023020031,
3645	STORE, 47859022979072, 47859023003647,
3646	ERASE, 47859022979072, 47859022979072,
3647	STORE, 47859022979072, 47859023003647,
3648	ERASE, 47859023003648, 47859023003648,
3649	STORE, 47859023003648, 47859023020031,
3650	STORE, 47859023003648, 47859023032319,
3651	ERASE, 47859022979072, 47859022979072,
3652	STORE, 47859022979072, 47859022995455,
3653	STORE, 47859022995456, 47859023003647,
3654	ERASE, 47859021164544, 47859021164544,
3655	STORE, 47859021164544, 47859021168639,
3656	STORE, 47859021168640, 47859021172735,
3657	ERASE, 94094885199872, 94094885199872,
3658	STORE, 94094885199872, 94094885216255,
3659	STORE, 94094885216256, 94094885220351,
3660	ERASE, 139773774098432, 139773774098432,
3661	STORE, 139773774098432, 139773774102527,
3662	STORE, 139773774102528, 139773774106623,
3663	ERASE, 47859021058048, 47859021058048,
3664	STORE, 94094901108736, 94094901243903,
3665	STORE, 140737488347136, 140737488351231,
3666	STORE, 140736567963648, 140737488351231,
3667	ERASE, 140736567963648, 140736567963648,
3668	STORE, 140736567963648, 140736567967743,
3669	STORE, 94924425748480, 94924426461183,
3670	ERASE, 94924425748480, 94924425748480,
3671	STORE, 94924425748480, 94924425797631,
3672	STORE, 94924425797632, 94924426461183,
3673	ERASE, 94924425797632, 94924425797632,
3674	STORE, 94924425797632, 94924426342399,
3675	STORE, 94924426342400, 94924426440703,
3676	STORE, 94924426440704, 94924426461183,
3677	STORE, 140042126319616, 140042126491647,
3678	ERASE, 140042126319616, 140042126319616,
3679	STORE, 140042126319616, 140042126323711,
3680	STORE, 140042126323712, 140042126491647,
3681	ERASE, 140042126323712, 140042126323712,
3682	STORE, 140042126323712, 140042126446591,
3683	STORE, 140042126446592, 140042126479359,
3684	STORE, 140042126479360, 140042126487551,
3685	STORE, 140042126487552, 140042126491647,
3686	STORE, 140736568672256, 140736568676351,
3687	STORE, 140736568659968, 140736568672255,
3688	STORE, 47590668677120, 47590668685311,
3689	STORE, 47590668685312, 47590668693503,
3690	STORE, 47590668693504, 47590668799999,
3691	STORE, 47590668709888, 47590668799999,
3692	STORE, 47590668693504, 47590668709887,
3693	ERASE, 47590668709888, 47590668709888,
3694	STORE, 47590668709888, 47590668783615,
3695	STORE, 47590668783616, 47590668799999,
3696	STORE, 47590668763136, 47590668783615,
3697	STORE, 47590668709888, 47590668763135,
3698	ERASE, 47590668709888, 47590668709888,
3699	STORE, 47590668709888, 47590668763135,
3700	STORE, 47590668779520, 47590668783615,
3701	STORE, 47590668763136, 47590668779519,
3702	ERASE, 47590668763136, 47590668763136,
3703	STORE, 47590668763136, 47590668779519,
3704	STORE, 47590668791808, 47590668799999,
3705	STORE, 47590668783616, 47590668791807,
3706	ERASE, 47590668783616, 47590668783616,
3707	STORE, 47590668783616, 47590668791807,
3708	ERASE, 47590668791808, 47590668791808,
3709	STORE, 47590668791808, 47590668799999,
3710	STORE, 47590668800000, 47590670639103,
3711	STORE, 47590668939264, 47590670639103,
3712	STORE, 47590668800000, 47590668939263,
3713	ERASE, 47590668939264, 47590668939264,
3714	STORE, 47590668939264, 47590670598143,
3715	STORE, 47590670598144, 47590670639103,
3716	STORE, 47590670282752, 47590670598143,
3717	STORE, 47590668939264, 47590670282751,
3718	ERASE, 47590668939264, 47590668939264,
3719	STORE, 47590668939264, 47590670282751,
3720	STORE, 47590670594048, 47590670598143,
3721	STORE, 47590670282752, 47590670594047,
3722	ERASE, 47590670282752, 47590670282752,
3723	STORE, 47590670282752, 47590670594047,
3724	STORE, 47590670622720, 47590670639103,
3725	STORE, 47590670598144, 47590670622719,
3726	ERASE, 47590670598144, 47590670598144,
3727	STORE, 47590670598144, 47590670622719,
3728	ERASE, 47590670622720, 47590670622720,
3729	STORE, 47590670622720, 47590670639103,
3730	STORE, 47590670622720, 47590670651391,
3731	ERASE, 47590670598144, 47590670598144,
3732	STORE, 47590670598144, 47590670614527,
3733	STORE, 47590670614528, 47590670622719,
3734	ERASE, 47590668783616, 47590668783616,
3735	STORE, 47590668783616, 47590668787711,
3736	STORE, 47590668787712, 47590668791807,
3737	ERASE, 94924426440704, 94924426440704,
3738	STORE, 94924426440704, 94924426457087,
3739	STORE, 94924426457088, 94924426461183,
3740	ERASE, 140042126479360, 140042126479360,
3741	STORE, 140042126479360, 140042126483455,
3742	STORE, 140042126483456, 140042126487551,
3743	ERASE, 47590668677120, 47590668677120,
3744	STORE, 140737488347136, 140737488351231,
3745	STORE, 140733281439744, 140737488351231,
3746	ERASE, 140733281439744, 140733281439744,
3747	STORE, 140733281439744, 140733281443839,
3748	STORE, 94490667069440, 94490667782143,
3749	ERASE, 94490667069440, 94490667069440,
3750	STORE, 94490667069440, 94490667118591,
3751	STORE, 94490667118592, 94490667782143,
3752	ERASE, 94490667118592, 94490667118592,
3753	STORE, 94490667118592, 94490667663359,
3754	STORE, 94490667663360, 94490667761663,
3755	STORE, 94490667761664, 94490667782143,
3756	STORE, 139878215118848, 139878215290879,
3757	ERASE, 139878215118848, 139878215118848,
3758	STORE, 139878215118848, 139878215122943,
3759	STORE, 139878215122944, 139878215290879,
3760	ERASE, 139878215122944, 139878215122944,
3761	STORE, 139878215122944, 139878215245823,
3762	STORE, 139878215245824, 139878215278591,
3763	STORE, 139878215278592, 139878215286783,
3764	STORE, 139878215286784, 139878215290879,
3765	STORE, 140733281464320, 140733281468415,
3766	STORE, 140733281452032, 140733281464319,
3767	STORE, 47754579877888, 47754579886079,
3768	STORE, 47754579886080, 47754579894271,
3769	STORE, 47754579894272, 47754580000767,
3770	STORE, 47754579910656, 47754580000767,
3771	STORE, 47754579894272, 47754579910655,
3772	ERASE, 47754579910656, 47754579910656,
3773	STORE, 47754579910656, 47754579984383,
3774	STORE, 47754579984384, 47754580000767,
3775	STORE, 47754579963904, 47754579984383,
3776	STORE, 47754579910656, 47754579963903,
3777	ERASE, 47754579910656, 47754579910656,
3778	STORE, 47754579910656, 47754579963903,
3779	STORE, 47754579980288, 47754579984383,
3780	STORE, 47754579963904, 47754579980287,
3781	ERASE, 47754579963904, 47754579963904,
3782	STORE, 47754579963904, 47754579980287,
3783	STORE, 47754579992576, 47754580000767,
3784	STORE, 47754579984384, 47754579992575,
3785	ERASE, 47754579984384, 47754579984384,
3786	STORE, 47754579984384, 47754579992575,
3787	ERASE, 47754579992576, 47754579992576,
3788	STORE, 47754579992576, 47754580000767,
3789	STORE, 47754580000768, 47754581839871,
3790	STORE, 47754580140032, 47754581839871,
3791	STORE, 47754580000768, 47754580140031,
3792	ERASE, 47754580140032, 47754580140032,
3793	STORE, 47754580140032, 47754581798911,
3794	STORE, 47754581798912, 47754581839871,
3795	STORE, 47754581483520, 47754581798911,
3796	STORE, 47754580140032, 47754581483519,
3797	ERASE, 47754580140032, 47754580140032,
3798	STORE, 47754580140032, 47754581483519,
3799	STORE, 47754581794816, 47754581798911,
3800	STORE, 47754581483520, 47754581794815,
3801	ERASE, 47754581483520, 47754581483520,
3802	STORE, 47754581483520, 47754581794815,
3803	STORE, 47754581823488, 47754581839871,
3804	STORE, 47754581798912, 47754581823487,
3805	ERASE, 47754581798912, 47754581798912,
3806	STORE, 47754581798912, 47754581823487,
3807	ERASE, 47754581823488, 47754581823488,
3808	STORE, 47754581823488, 47754581839871,
3809	STORE, 47754581823488, 47754581852159,
3810	ERASE, 47754581798912, 47754581798912,
3811	STORE, 47754581798912, 47754581815295,
3812	STORE, 47754581815296, 47754581823487,
3813	ERASE, 47754579984384, 47754579984384,
3814	STORE, 47754579984384, 47754579988479,
3815	STORE, 47754579988480, 47754579992575,
3816	ERASE, 94490667761664, 94490667761664,
3817	STORE, 94490667761664, 94490667778047,
3818	STORE, 94490667778048, 94490667782143,
3819	ERASE, 139878215278592, 139878215278592,
3820	STORE, 139878215278592, 139878215282687,
3821	STORE, 139878215282688, 139878215286783,
3822	ERASE, 47754579877888, 47754579877888,
3823	STORE, 94490669649920, 94490669785087,
3824	STORE, 140737488347136, 140737488351231,
3825	STORE, 140735382188032, 140737488351231,
3826	ERASE, 140735382188032, 140735382188032,
3827	STORE, 140735382188032, 140735382192127,
3828	STORE, 94150181302272, 94150182014975,
3829	ERASE, 94150181302272, 94150181302272,
3830	STORE, 94150181302272, 94150181351423,
3831	STORE, 94150181351424, 94150182014975,
3832	ERASE, 94150181351424, 94150181351424,
3833	STORE, 94150181351424, 94150181896191,
3834	STORE, 94150181896192, 94150181994495,
3835	STORE, 94150181994496, 94150182014975,
3836	STORE, 139679752458240, 139679752630271,
3837	ERASE, 139679752458240, 139679752458240,
3838	STORE, 139679752458240, 139679752462335,
3839	STORE, 139679752462336, 139679752630271,
3840	ERASE, 139679752462336, 139679752462336,
3841	STORE, 139679752462336, 139679752585215,
3842	STORE, 139679752585216, 139679752617983,
3843	STORE, 139679752617984, 139679752626175,
3844	STORE, 139679752626176, 139679752630271,
3845	STORE, 140735382536192, 140735382540287,
3846	STORE, 140735382523904, 140735382536191,
3847	STORE, 47953042538496, 47953042546687,
3848	STORE, 47953042546688, 47953042554879,
3849	STORE, 47953042554880, 47953042661375,
3850	STORE, 47953042571264, 47953042661375,
3851	STORE, 47953042554880, 47953042571263,
3852	ERASE, 47953042571264, 47953042571264,
3853	STORE, 47953042571264, 47953042644991,
3854	STORE, 47953042644992, 47953042661375,
3855	STORE, 47953042624512, 47953042644991,
3856	STORE, 47953042571264, 47953042624511,
3857	ERASE, 47953042571264, 47953042571264,
3858	STORE, 47953042571264, 47953042624511,
3859	STORE, 47953042640896, 47953042644991,
3860	STORE, 47953042624512, 47953042640895,
3861	ERASE, 47953042624512, 47953042624512,
3862	STORE, 47953042624512, 47953042640895,
3863	STORE, 47953042653184, 47953042661375,
3864	STORE, 47953042644992, 47953042653183,
3865	ERASE, 47953042644992, 47953042644992,
3866	STORE, 47953042644992, 47953042653183,
3867	ERASE, 47953042653184, 47953042653184,
3868	STORE, 47953042653184, 47953042661375,
3869	STORE, 47953042661376, 47953044500479,
3870	STORE, 47953042800640, 47953044500479,
3871	STORE, 47953042661376, 47953042800639,
3872	ERASE, 47953042800640, 47953042800640,
3873	STORE, 47953042800640, 47953044459519,
3874	STORE, 47953044459520, 47953044500479,
3875	STORE, 47953044144128, 47953044459519,
3876	STORE, 47953042800640, 47953044144127,
3877	ERASE, 47953042800640, 47953042800640,
3878	STORE, 47953042800640, 47953044144127,
3879	STORE, 47953044455424, 47953044459519,
3880	STORE, 47953044144128, 47953044455423,
3881	ERASE, 47953044144128, 47953044144128,
3882	STORE, 47953044144128, 47953044455423,
3883	STORE, 47953044484096, 47953044500479,
3884	STORE, 47953044459520, 47953044484095,
3885	ERASE, 47953044459520, 47953044459520,
3886	STORE, 47953044459520, 47953044484095,
3887	ERASE, 47953044484096, 47953044484096,
3888	STORE, 47953044484096, 47953044500479,
3889	STORE, 47953044484096, 47953044512767,
3890	ERASE, 47953044459520, 47953044459520,
3891	STORE, 47953044459520, 47953044475903,
3892	STORE, 47953044475904, 47953044484095,
3893	ERASE, 47953042644992, 47953042644992,
3894	STORE, 47953042644992, 47953042649087,
3895	STORE, 47953042649088, 47953042653183,
3896	ERASE, 94150181994496, 94150181994496,
3897	STORE, 94150181994496, 94150182010879,
3898	STORE, 94150182010880, 94150182014975,
3899	ERASE, 139679752617984, 139679752617984,
3900	STORE, 139679752617984, 139679752622079,
3901	STORE, 139679752622080, 139679752626175,
3902	ERASE, 47953042538496, 47953042538496,
3903	STORE, 140737488347136, 140737488351231,
3904	STORE, 140737044123648, 140737488351231,
3905	ERASE, 140737044123648, 140737044123648,
3906	STORE, 140737044123648, 140737044127743,
3907	STORE, 94425324294144, 94425325006847,
3908	ERASE, 94425324294144, 94425324294144,
3909	STORE, 94425324294144, 94425324343295,
3910	STORE, 94425324343296, 94425325006847,
3911	ERASE, 94425324343296, 94425324343296,
3912	STORE, 94425324343296, 94425324888063,
3913	STORE, 94425324888064, 94425324986367,
3914	STORE, 94425324986368, 94425325006847,
3915	STORE, 140382015016960, 140382015188991,
3916	ERASE, 140382015016960, 140382015016960,
3917	STORE, 140382015016960, 140382015021055,
3918	STORE, 140382015021056, 140382015188991,
3919	ERASE, 140382015021056, 140382015021056,
3920	STORE, 140382015021056, 140382015143935,
3921	STORE, 140382015143936, 140382015176703,
3922	STORE, 140382015176704, 140382015184895,
3923	STORE, 140382015184896, 140382015188991,
3924	STORE, 140737045585920, 140737045590015,
3925	STORE, 140737045573632, 140737045585919,
3926	STORE, 47250779979776, 47250779987967,
3927	STORE, 47250779987968, 47250779996159,
3928	STORE, 47250779996160, 47250780102655,
3929	STORE, 47250780012544, 47250780102655,
3930	STORE, 47250779996160, 47250780012543,
3931	ERASE, 47250780012544, 47250780012544,
3932	STORE, 47250780012544, 47250780086271,
3933	STORE, 47250780086272, 47250780102655,
3934	STORE, 47250780065792, 47250780086271,
3935	STORE, 47250780012544, 47250780065791,
3936	ERASE, 47250780012544, 47250780012544,
3937	STORE, 47250780012544, 47250780065791,
3938	STORE, 47250780082176, 47250780086271,
3939	STORE, 47250780065792, 47250780082175,
3940	ERASE, 47250780065792, 47250780065792,
3941	STORE, 47250780065792, 47250780082175,
3942	STORE, 47250780094464, 47250780102655,
3943	STORE, 47250780086272, 47250780094463,
3944	ERASE, 47250780086272, 47250780086272,
3945	STORE, 47250780086272, 47250780094463,
3946	ERASE, 47250780094464, 47250780094464,
3947	STORE, 47250780094464, 47250780102655,
3948	STORE, 47250780102656, 47250781941759,
3949	STORE, 47250780241920, 47250781941759,
3950	STORE, 47250780102656, 47250780241919,
3951	ERASE, 47250780241920, 47250780241920,
3952	STORE, 47250780241920, 47250781900799,
3953	STORE, 47250781900800, 47250781941759,
3954	STORE, 47250781585408, 47250781900799,
3955	STORE, 47250780241920, 47250781585407,
3956	ERASE, 47250780241920, 47250780241920,
3957	STORE, 47250780241920, 47250781585407,
3958	STORE, 47250781896704, 47250781900799,
3959	STORE, 47250781585408, 47250781896703,
3960	ERASE, 47250781585408, 47250781585408,
3961	STORE, 47250781585408, 47250781896703,
3962	STORE, 47250781925376, 47250781941759,
3963	STORE, 47250781900800, 47250781925375,
3964	ERASE, 47250781900800, 47250781900800,
3965	STORE, 47250781900800, 47250781925375,
3966	ERASE, 47250781925376, 47250781925376,
3967	STORE, 47250781925376, 47250781941759,
3968	STORE, 47250781925376, 47250781954047,
3969	ERASE, 47250781900800, 47250781900800,
3970	STORE, 47250781900800, 47250781917183,
3971	STORE, 47250781917184, 47250781925375,
3972	ERASE, 47250780086272, 47250780086272,
3973	STORE, 47250780086272, 47250780090367,
3974	STORE, 47250780090368, 47250780094463,
3975	ERASE, 94425324986368, 94425324986368,
3976	STORE, 94425324986368, 94425325002751,
3977	STORE, 94425325002752, 94425325006847,
3978	ERASE, 140382015176704, 140382015176704,
3979	STORE, 140382015176704, 140382015180799,
3980	STORE, 140382015180800, 140382015184895,
3981	ERASE, 47250779979776, 47250779979776,
3982	STORE, 94425351438336, 94425351573503,
3983	STORE, 140737488347136, 140737488351231,
3984	STORE, 140736801144832, 140737488351231,
3985	ERASE, 140736801144832, 140736801144832,
3986	STORE, 140736801144832, 140736801148927,
3987	STORE, 94629429358592, 94629430071295,
3988	ERASE, 94629429358592, 94629429358592,
3989	STORE, 94629429358592, 94629429407743,
3990	STORE, 94629429407744, 94629430071295,
3991	ERASE, 94629429407744, 94629429407744,
3992	STORE, 94629429407744, 94629429952511,
3993	STORE, 94629429952512, 94629430050815,
3994	STORE, 94629430050816, 94629430071295,
3995	STORE, 139801685483520, 139801685655551,
3996	ERASE, 139801685483520, 139801685483520,
3997	STORE, 139801685483520, 139801685487615,
3998	STORE, 139801685487616, 139801685655551,
3999	ERASE, 139801685487616, 139801685487616,
4000	STORE, 139801685487616, 139801685610495,
4001	STORE, 139801685610496, 139801685643263,
4002	STORE, 139801685643264, 139801685651455,
4003	STORE, 139801685651456, 139801685655551,
4004	STORE, 140736801198080, 140736801202175,
4005	STORE, 140736801185792, 140736801198079,
4006	STORE, 47831109513216, 47831109521407,
4007	STORE, 47831109521408, 47831109529599,
4008	STORE, 47831109529600, 47831109636095,
4009	STORE, 47831109545984, 47831109636095,
4010	STORE, 47831109529600, 47831109545983,
4011	ERASE, 47831109545984, 47831109545984,
4012	STORE, 47831109545984, 47831109619711,
4013	STORE, 47831109619712, 47831109636095,
4014	STORE, 47831109599232, 47831109619711,
4015	STORE, 47831109545984, 47831109599231,
4016	ERASE, 47831109545984, 47831109545984,
4017	STORE, 47831109545984, 47831109599231,
4018	STORE, 47831109615616, 47831109619711,
4019	STORE, 47831109599232, 47831109615615,
4020	ERASE, 47831109599232, 47831109599232,
4021	STORE, 47831109599232, 47831109615615,
4022	STORE, 47831109627904, 47831109636095,
4023	STORE, 47831109619712, 47831109627903,
4024	ERASE, 47831109619712, 47831109619712,
4025	STORE, 47831109619712, 47831109627903,
4026	ERASE, 47831109627904, 47831109627904,
4027	STORE, 47831109627904, 47831109636095,
4028	STORE, 47831109636096, 47831111475199,
4029	STORE, 47831109775360, 47831111475199,
4030	STORE, 47831109636096, 47831109775359,
4031	ERASE, 47831109775360, 47831109775360,
4032	STORE, 47831109775360, 47831111434239,
4033	STORE, 47831111434240, 47831111475199,
4034	STORE, 47831111118848, 47831111434239,
4035	STORE, 47831109775360, 47831111118847,
4036	ERASE, 47831109775360, 47831109775360,
4037	STORE, 47831109775360, 47831111118847,
4038	STORE, 47831111430144, 47831111434239,
4039	STORE, 47831111118848, 47831111430143,
4040	ERASE, 47831111118848, 47831111118848,
4041	STORE, 47831111118848, 47831111430143,
4042	STORE, 47831111458816, 47831111475199,
4043	STORE, 47831111434240, 47831111458815,
4044	ERASE, 47831111434240, 47831111434240,
4045	STORE, 47831111434240, 47831111458815,
4046	ERASE, 47831111458816, 47831111458816,
4047	STORE, 47831111458816, 47831111475199,
4048	STORE, 47831111458816, 47831111487487,
4049	ERASE, 47831111434240, 47831111434240,
4050	STORE, 47831111434240, 47831111450623,
4051	STORE, 47831111450624, 47831111458815,
4052	ERASE, 47831109619712, 47831109619712,
4053	STORE, 47831109619712, 47831109623807,
4054	STORE, 47831109623808, 47831109627903,
4055	ERASE, 94629430050816, 94629430050816,
4056	STORE, 94629430050816, 94629430067199,
4057	STORE, 94629430067200, 94629430071295,
4058	ERASE, 139801685643264, 139801685643264,
4059	STORE, 139801685643264, 139801685647359,
4060	STORE, 139801685647360, 139801685651455,
4061	ERASE, 47831109513216, 47831109513216,
4062	STORE, 140737488347136, 140737488351231,
4063	STORE, 140729419612160, 140737488351231,
4064	ERASE, 140729419612160, 140729419612160,
4065	STORE, 140729419612160, 140729419616255,
4066	STORE, 94443354148864, 94443354861567,
4067	ERASE, 94443354148864, 94443354148864,
4068	STORE, 94443354148864, 94443354198015,
4069	STORE, 94443354198016, 94443354861567,
4070	ERASE, 94443354198016, 94443354198016,
4071	STORE, 94443354198016, 94443354742783,
4072	STORE, 94443354742784, 94443354841087,
4073	STORE, 94443354841088, 94443354861567,
4074	STORE, 139741700038656, 139741700210687,
4075	ERASE, 139741700038656, 139741700038656,
4076	STORE, 139741700038656, 139741700042751,
4077	STORE, 139741700042752, 139741700210687,
4078	ERASE, 139741700042752, 139741700042752,
4079	STORE, 139741700042752, 139741700165631,
4080	STORE, 139741700165632, 139741700198399,
4081	STORE, 139741700198400, 139741700206591,
4082	STORE, 139741700206592, 139741700210687,
4083	STORE, 140729420574720, 140729420578815,
4084	STORE, 140729420562432, 140729420574719,
4085	STORE, 47891094958080, 47891094966271,
4086	STORE, 47891094966272, 47891094974463,
4087	STORE, 47891094974464, 47891095080959,
4088	STORE, 47891094990848, 47891095080959,
4089	STORE, 47891094974464, 47891094990847,
4090	ERASE, 47891094990848, 47891094990848,
4091	STORE, 47891094990848, 47891095064575,
4092	STORE, 47891095064576, 47891095080959,
4093	STORE, 47891095044096, 47891095064575,
4094	STORE, 47891094990848, 47891095044095,
4095	ERASE, 47891094990848, 47891094990848,
4096	STORE, 47891094990848, 47891095044095,
4097	STORE, 47891095060480, 47891095064575,
4098	STORE, 47891095044096, 47891095060479,
4099	ERASE, 47891095044096, 47891095044096,
4100	STORE, 47891095044096, 47891095060479,
4101	STORE, 47891095072768, 47891095080959,
4102	STORE, 47891095064576, 47891095072767,
4103	ERASE, 47891095064576, 47891095064576,
4104	STORE, 47891095064576, 47891095072767,
4105	ERASE, 47891095072768, 47891095072768,
4106	STORE, 47891095072768, 47891095080959,
4107	STORE, 47891095080960, 47891096920063,
4108	STORE, 47891095220224, 47891096920063,
4109	STORE, 47891095080960, 47891095220223,
4110	ERASE, 47891095220224, 47891095220224,
4111	STORE, 47891095220224, 47891096879103,
4112	STORE, 47891096879104, 47891096920063,
4113	STORE, 47891096563712, 47891096879103,
4114	STORE, 47891095220224, 47891096563711,
4115	ERASE, 47891095220224, 47891095220224,
4116	STORE, 47891095220224, 47891096563711,
4117	STORE, 47891096875008, 47891096879103,
4118	STORE, 47891096563712, 47891096875007,
4119	ERASE, 47891096563712, 47891096563712,
4120	STORE, 47891096563712, 47891096875007,
4121	STORE, 47891096903680, 47891096920063,
4122	STORE, 47891096879104, 47891096903679,
4123	ERASE, 47891096879104, 47891096879104,
4124	STORE, 47891096879104, 47891096903679,
4125	ERASE, 47891096903680, 47891096903680,
4126	STORE, 47891096903680, 47891096920063,
4127	STORE, 47891096903680, 47891096932351,
4128	ERASE, 47891096879104, 47891096879104,
4129	STORE, 47891096879104, 47891096895487,
4130	STORE, 47891096895488, 47891096903679,
4131	ERASE, 47891095064576, 47891095064576,
4132	STORE, 47891095064576, 47891095068671,
4133	STORE, 47891095068672, 47891095072767,
4134	ERASE, 94443354841088, 94443354841088,
4135	STORE, 94443354841088, 94443354857471,
4136	STORE, 94443354857472, 94443354861567,
4137	ERASE, 139741700198400, 139741700198400,
4138	STORE, 139741700198400, 139741700202495,
4139	STORE, 139741700202496, 139741700206591,
4140	ERASE, 47891094958080, 47891094958080,
4141	STORE, 94443360825344, 94443360960511,
4142	STORE, 140737488347136, 140737488351231,
4143	STORE, 140722961661952, 140737488351231,
4144	ERASE, 140722961661952, 140722961661952,
4145	STORE, 140722961661952, 140722961666047,
4146	STORE, 94878388944896, 94878389657599,
4147	ERASE, 94878388944896, 94878388944896,
4148	STORE, 94878388944896, 94878388994047,
4149	STORE, 94878388994048, 94878389657599,
4150	ERASE, 94878388994048, 94878388994048,
4151	STORE, 94878388994048, 94878389538815,
4152	STORE, 94878389538816, 94878389637119,
4153	STORE, 94878389637120, 94878389657599,
4154	STORE, 140210690056192, 140210690228223,
4155	ERASE, 140210690056192, 140210690056192,
4156	STORE, 140210690056192, 140210690060287,
4157	STORE, 140210690060288, 140210690228223,
4158	ERASE, 140210690060288, 140210690060288,
4159	STORE, 140210690060288, 140210690183167,
4160	STORE, 140210690183168, 140210690215935,
4161	STORE, 140210690215936, 140210690224127,
4162	STORE, 140210690224128, 140210690228223,
4163	STORE, 140722963148800, 140722963152895,
4164	STORE, 140722963136512, 140722963148799,
4165	STORE, 47422104940544, 47422104948735,
4166	STORE, 47422104948736, 47422104956927,
4167	STORE, 47422104956928, 47422105063423,
4168	STORE, 47422104973312, 47422105063423,
4169	STORE, 47422104956928, 47422104973311,
4170	ERASE, 47422104973312, 47422104973312,
4171	STORE, 47422104973312, 47422105047039,
4172	STORE, 47422105047040, 47422105063423,
4173	STORE, 47422105026560, 47422105047039,
4174	STORE, 47422104973312, 47422105026559,
4175	ERASE, 47422104973312, 47422104973312,
4176	STORE, 47422104973312, 47422105026559,
4177	STORE, 47422105042944, 47422105047039,
4178	STORE, 47422105026560, 47422105042943,
4179	ERASE, 47422105026560, 47422105026560,
4180	STORE, 47422105026560, 47422105042943,
4181	STORE, 47422105055232, 47422105063423,
4182	STORE, 47422105047040, 47422105055231,
4183	ERASE, 47422105047040, 47422105047040,
4184	STORE, 47422105047040, 47422105055231,
4185	ERASE, 47422105055232, 47422105055232,
4186	STORE, 47422105055232, 47422105063423,
4187	STORE, 47422105063424, 47422106902527,
4188	STORE, 47422105202688, 47422106902527,
4189	STORE, 47422105063424, 47422105202687,
4190	ERASE, 47422105202688, 47422105202688,
4191	STORE, 47422105202688, 47422106861567,
4192	STORE, 47422106861568, 47422106902527,
4193	STORE, 47422106546176, 47422106861567,
4194	STORE, 47422105202688, 47422106546175,
4195	ERASE, 47422105202688, 47422105202688,
4196	STORE, 47422105202688, 47422106546175,
4197	STORE, 47422106857472, 47422106861567,
4198	STORE, 47422106546176, 47422106857471,
4199	ERASE, 47422106546176, 47422106546176,
4200	STORE, 47422106546176, 47422106857471,
4201	STORE, 47422106886144, 47422106902527,
4202	STORE, 47422106861568, 47422106886143,
4203	ERASE, 47422106861568, 47422106861568,
4204	STORE, 47422106861568, 47422106886143,
4205	ERASE, 47422106886144, 47422106886144,
4206	STORE, 47422106886144, 47422106902527,
4207	STORE, 47422106886144, 47422106914815,
4208	ERASE, 47422106861568, 47422106861568,
4209	STORE, 47422106861568, 47422106877951,
4210	STORE, 47422106877952, 47422106886143,
4211	ERASE, 47422105047040, 47422105047040,
4212	STORE, 47422105047040, 47422105051135,
4213	STORE, 47422105051136, 47422105055231,
4214	ERASE, 94878389637120, 94878389637120,
4215	STORE, 94878389637120, 94878389653503,
4216	STORE, 94878389653504, 94878389657599,
4217	ERASE, 140210690215936, 140210690215936,
4218	STORE, 140210690215936, 140210690220031,
4219	STORE, 140210690220032, 140210690224127,
4220	ERASE, 47422104940544, 47422104940544,
4221	STORE, 140737488347136, 140737488351231,
4222	STORE, 140727690309632, 140737488351231,
4223	ERASE, 140727690309632, 140727690309632,
4224	STORE, 140727690309632, 140727690313727,
4225	STORE, 94121892208640, 94121892921343,
4226	ERASE, 94121892208640, 94121892208640,
4227	STORE, 94121892208640, 94121892257791,
4228	STORE, 94121892257792, 94121892921343,
4229	ERASE, 94121892257792, 94121892257792,
4230	STORE, 94121892257792, 94121892802559,
4231	STORE, 94121892802560, 94121892900863,
4232	STORE, 94121892900864, 94121892921343,
4233	STORE, 140662438326272, 140662438498303,
4234	ERASE, 140662438326272, 140662438326272,
4235	STORE, 140662438326272, 140662438330367,
4236	STORE, 140662438330368, 140662438498303,
4237	ERASE, 140662438330368, 140662438330368,
4238	STORE, 140662438330368, 140662438453247,
4239	STORE, 140662438453248, 140662438486015,
4240	STORE, 140662438486016, 140662438494207,
4241	STORE, 140662438494208, 140662438498303,
4242	STORE, 140727690379264, 140727690383359,
4243	STORE, 140727690366976, 140727690379263,
4244	STORE, 46970356670464, 46970356678655,
4245	STORE, 46970356678656, 46970356686847,
4246	STORE, 46970356686848, 46970356793343,
4247	STORE, 46970356703232, 46970356793343,
4248	STORE, 46970356686848, 46970356703231,
4249	ERASE, 46970356703232, 46970356703232,
4250	STORE, 46970356703232, 46970356776959,
4251	STORE, 46970356776960, 46970356793343,
4252	STORE, 46970356756480, 46970356776959,
4253	STORE, 46970356703232, 46970356756479,
4254	ERASE, 46970356703232, 46970356703232,
4255	STORE, 46970356703232, 46970356756479,
4256	STORE, 46970356772864, 46970356776959,
4257	STORE, 46970356756480, 46970356772863,
4258	ERASE, 46970356756480, 46970356756480,
4259	STORE, 46970356756480, 46970356772863,
4260	STORE, 46970356785152, 46970356793343,
4261	STORE, 46970356776960, 46970356785151,
4262	ERASE, 46970356776960, 46970356776960,
4263	STORE, 46970356776960, 46970356785151,
4264	ERASE, 46970356785152, 46970356785152,
4265	STORE, 46970356785152, 46970356793343,
4266	STORE, 46970356793344, 46970358632447,
4267	STORE, 46970356932608, 46970358632447,
4268	STORE, 46970356793344, 46970356932607,
4269	ERASE, 46970356932608, 46970356932608,
4270	STORE, 46970356932608, 46970358591487,
4271	STORE, 46970358591488, 46970358632447,
4272	STORE, 46970358276096, 46970358591487,
4273	STORE, 46970356932608, 46970358276095,
4274	ERASE, 46970356932608, 46970356932608,
4275	STORE, 46970356932608, 46970358276095,
4276	STORE, 46970358587392, 46970358591487,
4277	STORE, 46970358276096, 46970358587391,
4278	ERASE, 46970358276096, 46970358276096,
4279	STORE, 46970358276096, 46970358587391,
4280	STORE, 46970358616064, 46970358632447,
4281	STORE, 46970358591488, 46970358616063,
4282	ERASE, 46970358591488, 46970358591488,
4283	STORE, 46970358591488, 46970358616063,
4284	ERASE, 46970358616064, 46970358616064,
4285	STORE, 46970358616064, 46970358632447,
4286	STORE, 46970358616064, 46970358644735,
4287	ERASE, 46970358591488, 46970358591488,
4288	STORE, 46970358591488, 46970358607871,
4289	STORE, 46970358607872, 46970358616063,
4290	ERASE, 46970356776960, 46970356776960,
4291	STORE, 46970356776960, 46970356781055,
4292	STORE, 46970356781056, 46970356785151,
4293	ERASE, 94121892900864, 94121892900864,
4294	STORE, 94121892900864, 94121892917247,
4295	STORE, 94121892917248, 94121892921343,
4296	ERASE, 140662438486016, 140662438486016,
4297	STORE, 140662438486016, 140662438490111,
4298	STORE, 140662438490112, 140662438494207,
4299	ERASE, 46970356670464, 46970356670464,
4300	STORE, 94121898610688, 94121898745855,
4301	STORE, 140737488347136, 140737488351231,
4302	STORE, 140737189351424, 140737488351231,
4303	ERASE, 140737189351424, 140737189351424,
4304	STORE, 140737189351424, 140737189355519,
4305	STORE, 93847948832768, 93847949545471,
4306	ERASE, 93847948832768, 93847948832768,
4307	STORE, 93847948832768, 93847948881919,
4308	STORE, 93847948881920, 93847949545471,
4309	ERASE, 93847948881920, 93847948881920,
4310	STORE, 93847948881920, 93847949426687,
4311	STORE, 93847949426688, 93847949524991,
4312	STORE, 93847949524992, 93847949545471,
4313	STORE, 139698989985792, 139698990157823,
4314	ERASE, 139698989985792, 139698989985792,
4315	STORE, 139698989985792, 139698989989887,
4316	STORE, 139698989989888, 139698990157823,
4317	ERASE, 139698989989888, 139698989989888,
4318	STORE, 139698989989888, 139698990112767,
4319	STORE, 139698990112768, 139698990145535,
4320	STORE, 139698990145536, 139698990153727,
4321	STORE, 139698990153728, 139698990157823,
4322	STORE, 140737189744640, 140737189748735,
4323	STORE, 140737189732352, 140737189744639,
4324	STORE, 47933805010944, 47933805019135,
4325	STORE, 47933805019136, 47933805027327,
4326	STORE, 47933805027328, 47933805133823,
4327	STORE, 47933805043712, 47933805133823,
4328	STORE, 47933805027328, 47933805043711,
4329	ERASE, 47933805043712, 47933805043712,
4330	STORE, 47933805043712, 47933805117439,
4331	STORE, 47933805117440, 47933805133823,
4332	STORE, 47933805096960, 47933805117439,
4333	STORE, 47933805043712, 47933805096959,
4334	ERASE, 47933805043712, 47933805043712,
4335	STORE, 47933805043712, 47933805096959,
4336	STORE, 47933805113344, 47933805117439,
4337	STORE, 47933805096960, 47933805113343,
4338	ERASE, 47933805096960, 47933805096960,
4339	STORE, 47933805096960, 47933805113343,
4340	STORE, 47933805125632, 47933805133823,
4341	STORE, 47933805117440, 47933805125631,
4342	ERASE, 47933805117440, 47933805117440,
4343	STORE, 47933805117440, 47933805125631,
4344	ERASE, 47933805125632, 47933805125632,
4345	STORE, 47933805125632, 47933805133823,
4346	STORE, 47933805133824, 47933806972927,
4347	STORE, 47933805273088, 47933806972927,
4348	STORE, 47933805133824, 47933805273087,
4349	ERASE, 47933805273088, 47933805273088,
4350	STORE, 47933805273088, 47933806931967,
4351	STORE, 47933806931968, 47933806972927,
4352	STORE, 47933806616576, 47933806931967,
4353	STORE, 47933805273088, 47933806616575,
4354	ERASE, 47933805273088, 47933805273088,
4355	STORE, 47933805273088, 47933806616575,
4356	STORE, 47933806927872, 47933806931967,
4357	STORE, 47933806616576, 47933806927871,
4358	ERASE, 47933806616576, 47933806616576,
4359	STORE, 47933806616576, 47933806927871,
4360	STORE, 47933806956544, 47933806972927,
4361	STORE, 47933806931968, 47933806956543,
4362	ERASE, 47933806931968, 47933806931968,
4363	STORE, 47933806931968, 47933806956543,
4364	ERASE, 47933806956544, 47933806956544,
4365	STORE, 47933806956544, 47933806972927,
4366	STORE, 47933806956544, 47933806985215,
4367	ERASE, 47933806931968, 47933806931968,
4368	STORE, 47933806931968, 47933806948351,
4369	STORE, 47933806948352, 47933806956543,
4370	ERASE, 47933805117440, 47933805117440,
4371	STORE, 47933805117440, 47933805121535,
4372	STORE, 47933805121536, 47933805125631,
4373	ERASE, 93847949524992, 93847949524992,
4374	STORE, 93847949524992, 93847949541375,
4375	STORE, 93847949541376, 93847949545471,
4376	ERASE, 139698990145536, 139698990145536,
4377	STORE, 139698990145536, 139698990149631,
4378	STORE, 139698990149632, 139698990153727,
4379	ERASE, 47933805010944, 47933805010944,
4380	STORE, 140737488347136, 140737488351231,
4381	STORE, 140725553991680, 140737488351231,
4382	ERASE, 140725553991680, 140725553991680,
4383	STORE, 140725553991680, 140725553995775,
4384	STORE, 93980056248320, 93980056961023,
4385	ERASE, 93980056248320, 93980056248320,
4386	STORE, 93980056248320, 93980056297471,
4387	STORE, 93980056297472, 93980056961023,
4388	ERASE, 93980056297472, 93980056297472,
4389	STORE, 93980056297472, 93980056842239,
4390	STORE, 93980056842240, 93980056940543,
4391	STORE, 93980056940544, 93980056961023,
4392	STORE, 140146588971008, 140146589143039,
4393	ERASE, 140146588971008, 140146588971008,
4394	STORE, 140146588971008, 140146588975103,
4395	STORE, 140146588975104, 140146589143039,
4396	ERASE, 140146588975104, 140146588975104,
4397	STORE, 140146588975104, 140146589097983,
4398	STORE, 140146589097984, 140146589130751,
4399	STORE, 140146589130752, 140146589138943,
4400	STORE, 140146589138944, 140146589143039,
4401	STORE, 140725554860032, 140725554864127,
4402	STORE, 140725554847744, 140725554860031,
4403	STORE, 47486206025728, 47486206033919,
4404	STORE, 47486206033920, 47486206042111,
4405	STORE, 47486206042112, 47486206148607,
4406	STORE, 47486206058496, 47486206148607,
4407	STORE, 47486206042112, 47486206058495,
4408	ERASE, 47486206058496, 47486206058496,
4409	STORE, 47486206058496, 47486206132223,
4410	STORE, 47486206132224, 47486206148607,
4411	STORE, 47486206111744, 47486206132223,
4412	STORE, 47486206058496, 47486206111743,
4413	ERASE, 47486206058496, 47486206058496,
4414	STORE, 47486206058496, 47486206111743,
4415	STORE, 47486206128128, 47486206132223,
4416	STORE, 47486206111744, 47486206128127,
4417	ERASE, 47486206111744, 47486206111744,
4418	STORE, 47486206111744, 47486206128127,
4419	STORE, 47486206140416, 47486206148607,
4420	STORE, 47486206132224, 47486206140415,
4421	ERASE, 47486206132224, 47486206132224,
4422	STORE, 47486206132224, 47486206140415,
4423	ERASE, 47486206140416, 47486206140416,
4424	STORE, 47486206140416, 47486206148607,
4425	STORE, 47486206148608, 47486207987711,
4426	STORE, 47486206287872, 47486207987711,
4427	STORE, 47486206148608, 47486206287871,
4428	ERASE, 47486206287872, 47486206287872,
4429	STORE, 47486206287872, 47486207946751,
4430	STORE, 47486207946752, 47486207987711,
4431	STORE, 47486207631360, 47486207946751,
4432	STORE, 47486206287872, 47486207631359,
4433	ERASE, 47486206287872, 47486206287872,
4434	STORE, 47486206287872, 47486207631359,
4435	STORE, 47486207942656, 47486207946751,
4436	STORE, 47486207631360, 47486207942655,
4437	ERASE, 47486207631360, 47486207631360,
4438	STORE, 47486207631360, 47486207942655,
4439	STORE, 47486207971328, 47486207987711,
4440	STORE, 47486207946752, 47486207971327,
4441	ERASE, 47486207946752, 47486207946752,
4442	STORE, 47486207946752, 47486207971327,
4443	ERASE, 47486207971328, 47486207971328,
4444	STORE, 47486207971328, 47486207987711,
4445	STORE, 47486207971328, 47486207999999,
4446	ERASE, 47486207946752, 47486207946752,
4447	STORE, 47486207946752, 47486207963135,
4448	STORE, 47486207963136, 47486207971327,
4449	ERASE, 47486206132224, 47486206132224,
4450	STORE, 47486206132224, 47486206136319,
4451	STORE, 47486206136320, 47486206140415,
4452	ERASE, 93980056940544, 93980056940544,
4453	STORE, 93980056940544, 93980056956927,
4454	STORE, 93980056956928, 93980056961023,
4455	ERASE, 140146589130752, 140146589130752,
4456	STORE, 140146589130752, 140146589134847,
4457	STORE, 140146589134848, 140146589138943,
4458	ERASE, 47486206025728, 47486206025728,
4459	STORE, 93980070006784, 93980070141951,
4460	STORE, 140737488347136, 140737488351231,
4461	STORE, 140727334776832, 140737488351231,
4462	ERASE, 140727334776832, 140727334776832,
4463	STORE, 140727334776832, 140727334780927,
4464	STORE, 94049747247104, 94049747959807,
4465	ERASE, 94049747247104, 94049747247104,
4466	STORE, 94049747247104, 94049747296255,
4467	STORE, 94049747296256, 94049747959807,
4468	ERASE, 94049747296256, 94049747296256,
4469	STORE, 94049747296256, 94049747841023,
4470	STORE, 94049747841024, 94049747939327,
4471	STORE, 94049747939328, 94049747959807,
4472	STORE, 140227307216896, 140227307388927,
4473	ERASE, 140227307216896, 140227307216896,
4474	STORE, 140227307216896, 140227307220991,
4475	STORE, 140227307220992, 140227307388927,
4476	ERASE, 140227307220992, 140227307220992,
4477	STORE, 140227307220992, 140227307343871,
4478	STORE, 140227307343872, 140227307376639,
4479	STORE, 140227307376640, 140227307384831,
4480	STORE, 140227307384832, 140227307388927,
4481	STORE, 140727335337984, 140727335342079,
4482	STORE, 140727335325696, 140727335337983,
4483	STORE, 47405487779840, 47405487788031,
4484	STORE, 47405487788032, 47405487796223,
4485	STORE, 47405487796224, 47405487902719,
4486	STORE, 47405487812608, 47405487902719,
4487	STORE, 47405487796224, 47405487812607,
4488	ERASE, 47405487812608, 47405487812608,
4489	STORE, 47405487812608, 47405487886335,
4490	STORE, 47405487886336, 47405487902719,
4491	STORE, 47405487865856, 47405487886335,
4492	STORE, 47405487812608, 47405487865855,
4493	ERASE, 47405487812608, 47405487812608,
4494	STORE, 47405487812608, 47405487865855,
4495	STORE, 47405487882240, 47405487886335,
4496	STORE, 47405487865856, 47405487882239,
4497	ERASE, 47405487865856, 47405487865856,
4498	STORE, 47405487865856, 47405487882239,
4499	STORE, 47405487894528, 47405487902719,
4500	STORE, 47405487886336, 47405487894527,
4501	ERASE, 47405487886336, 47405487886336,
4502	STORE, 47405487886336, 47405487894527,
4503	ERASE, 47405487894528, 47405487894528,
4504	STORE, 47405487894528, 47405487902719,
4505	STORE, 47405487902720, 47405489741823,
4506	STORE, 47405488041984, 47405489741823,
4507	STORE, 47405487902720, 47405488041983,
4508	ERASE, 47405488041984, 47405488041984,
4509	STORE, 47405488041984, 47405489700863,
4510	STORE, 47405489700864, 47405489741823,
4511	STORE, 47405489385472, 47405489700863,
4512	STORE, 47405488041984, 47405489385471,
4513	ERASE, 47405488041984, 47405488041984,
4514	STORE, 47405488041984, 47405489385471,
4515	STORE, 47405489696768, 47405489700863,
4516	STORE, 47405489385472, 47405489696767,
4517	ERASE, 47405489385472, 47405489385472,
4518	STORE, 47405489385472, 47405489696767,
4519	STORE, 47405489725440, 47405489741823,
4520	STORE, 47405489700864, 47405489725439,
4521	ERASE, 47405489700864, 47405489700864,
4522	STORE, 47405489700864, 47405489725439,
4523	ERASE, 47405489725440, 47405489725440,
4524	STORE, 47405489725440, 47405489741823,
4525	STORE, 47405489725440, 47405489754111,
4526	ERASE, 47405489700864, 47405489700864,
4527	STORE, 47405489700864, 47405489717247,
4528	STORE, 47405489717248, 47405489725439,
4529	ERASE, 47405487886336, 47405487886336,
4530	STORE, 47405487886336, 47405487890431,
4531	STORE, 47405487890432, 47405487894527,
4532	ERASE, 94049747939328, 94049747939328,
4533	STORE, 94049747939328, 94049747955711,
4534	STORE, 94049747955712, 94049747959807,
4535	ERASE, 140227307376640, 140227307376640,
4536	STORE, 140227307376640, 140227307380735,
4537	STORE, 140227307380736, 140227307384831,
4538	ERASE, 47405487779840, 47405487779840,
4539	STORE, 94049758810112, 94049758945279,
4540	STORE, 140737488347136, 140737488351231,
4541	STORE, 140727079718912, 140737488351231,
4542	ERASE, 140727079718912, 140727079718912,
4543	STORE, 140727079718912, 140727079723007,
4544	STORE, 94250996527104, 94250997239807,
4545	ERASE, 94250996527104, 94250996527104,
4546	STORE, 94250996527104, 94250996576255,
4547	STORE, 94250996576256, 94250997239807,
4548	ERASE, 94250996576256, 94250996576256,
4549	STORE, 94250996576256, 94250997121023,
4550	STORE, 94250997121024, 94250997219327,
4551	STORE, 94250997219328, 94250997239807,
4552	STORE, 140060022587392, 140060022759423,
4553	ERASE, 140060022587392, 140060022587392,
4554	STORE, 140060022587392, 140060022591487,
4555	STORE, 140060022591488, 140060022759423,
4556	ERASE, 140060022591488, 140060022591488,
4557	STORE, 140060022591488, 140060022714367,
4558	STORE, 140060022714368, 140060022747135,
4559	STORE, 140060022747136, 140060022755327,
4560	STORE, 140060022755328, 140060022759423,
4561	STORE, 140727079788544, 140727079792639,
4562	STORE, 140727079776256, 140727079788543,
4563	/* this next one caused issues when lowering the efficiency */
4564	STORE, 47572772409344, 47572772417535,
4565	STORE, 47572772417536, 47572772425727,
4566	STORE, 47572772425728, 47572772532223,
4567	STORE, 47572772442112, 47572772532223,
4568	STORE, 47572772425728, 47572772442111,
4569	ERASE, 47572772442112, 47572772442112,
4570	STORE, 47572772442112, 47572772515839,
4571	STORE, 47572772515840, 47572772532223,
4572	STORE, 47572772495360, 47572772515839,
4573	STORE, 47572772442112, 47572772495359,
4574	ERASE, 47572772442112, 47572772442112,
4575	STORE, 47572772442112, 47572772495359,
4576	STORE, 47572772511744, 47572772515839,
4577	STORE, 47572772495360, 47572772511743,
4578	ERASE, 47572772495360, 47572772495360,
4579	STORE, 47572772495360, 47572772511743,
4580	STORE, 47572772524032, 47572772532223,
4581	STORE, 47572772515840, 47572772524031,
4582	ERASE, 47572772515840, 47572772515840,
4583	STORE, 47572772515840, 47572772524031,
4584	ERASE, 47572772524032, 47572772524032,
4585	STORE, 47572772524032, 47572772532223,
4586	STORE, 47572772532224, 47572774371327,
4587	STORE, 47572772671488, 47572774371327,
4588	STORE, 47572772532224, 47572772671487,
4589	ERASE, 47572772671488, 47572772671488,
4590	STORE, 47572772671488, 47572774330367,
4591	STORE, 47572774330368, 47572774371327,
4592	STORE, 47572774014976, 47572774330367,
4593	STORE, 47572772671488, 47572774014975,
4594	ERASE, 47572772671488, 47572772671488,
4595	STORE, 47572772671488, 47572774014975,
4596	STORE, 47572774326272, 47572774330367,
4597	STORE, 47572774014976, 47572774326271,
4598	ERASE, 47572774014976, 47572774014976,
4599	STORE, 47572774014976, 47572774326271,
4600	STORE, 47572774354944, 47572774371327,
4601	STORE, 47572774330368, 47572774354943,
4602	ERASE, 47572774330368, 47572774330368,
4603	STORE, 47572774330368, 47572774354943,
4604	ERASE, 47572774354944, 47572774354944,
4605	STORE, 47572774354944, 47572774371327,
4606	STORE, 47572774354944, 47572774383615,
4607	ERASE, 47572774330368, 47572774330368,
4608	STORE, 47572774330368, 47572774346751,
4609	STORE, 47572774346752, 47572774354943,
4610	ERASE, 47572772515840, 47572772515840,
4611	STORE, 47572772515840, 47572772519935,
4612	STORE, 47572772519936, 47572772524031,
4613	ERASE, 94250997219328, 94250997219328,
4614	STORE, 94250997219328, 94250997235711,
4615	STORE, 94250997235712, 94250997239807,
4616	ERASE, 140060022747136, 140060022747136,
4617	STORE, 140060022747136, 140060022751231,
4618	STORE, 140060022751232, 140060022755327,
4619	ERASE, 47572772409344, 47572772409344,
4620	STORE, 94251018305536, 94251018440703,
4621	STORE, 140737488347136, 140737488351231,
4622	STORE, 140730012389376, 140737488351231,
4623	ERASE, 140730012389376, 140730012389376,
4624	STORE, 140730012389376, 140730012393471,
4625	STORE, 94382607675392, 94382607695871,
4626	ERASE, 94382607675392, 94382607675392,
4627	STORE, 94382607675392, 94382607679487,
4628	STORE, 94382607679488, 94382607695871,
4629	ERASE, 94382607679488, 94382607679488,
4630	STORE, 94382607679488, 94382607683583,
4631	STORE, 94382607683584, 94382607687679,
4632	STORE, 94382607687680, 94382607695871,
4633	STORE, 140252451454976, 140252451627007,
4634	ERASE, 140252451454976, 140252451454976,
4635	STORE, 140252451454976, 140252451459071,
4636	STORE, 140252451459072, 140252451627007,
4637	ERASE, 140252451459072, 140252451459072,
4638	STORE, 140252451459072, 140252451581951,
4639	STORE, 140252451581952, 140252451614719,
4640	STORE, 140252451614720, 140252451622911,
4641	STORE, 140252451622912, 140252451627007,
4642	STORE, 140730013548544, 140730013552639,
4643	STORE, 140730013536256, 140730013548543,
4644	STORE, 47380343541760, 47380343549951,
4645	STORE, 47380343549952, 47380343558143,
4646	STORE, 47380343558144, 47380345397247,
4647	STORE, 47380343697408, 47380345397247,
4648	STORE, 47380343558144, 47380343697407,
4649	ERASE, 47380343697408, 47380343697408,
4650	STORE, 47380343697408, 47380345356287,
4651	STORE, 47380345356288, 47380345397247,
4652	STORE, 47380345040896, 47380345356287,
4653	STORE, 47380343697408, 47380345040895,
4654	ERASE, 47380343697408, 47380343697408,
4655	STORE, 47380343697408, 47380345040895,
4656	STORE, 47380345352192, 47380345356287,
4657	STORE, 47380345040896, 47380345352191,
4658	ERASE, 47380345040896, 47380345040896,
4659	STORE, 47380345040896, 47380345352191,
4660	STORE, 47380345380864, 47380345397247,
4661	STORE, 47380345356288, 47380345380863,
4662	ERASE, 47380345356288, 47380345356288,
4663	STORE, 47380345356288, 47380345380863,
4664	ERASE, 47380345380864, 47380345380864,
4665	STORE, 47380345380864, 47380345397247,
4666	ERASE, 47380345356288, 47380345356288,
4667	STORE, 47380345356288, 47380345372671,
4668	STORE, 47380345372672, 47380345380863,
4669	ERASE, 94382607687680, 94382607687680,
4670	STORE, 94382607687680, 94382607691775,
4671	STORE, 94382607691776, 94382607695871,
4672	ERASE, 140252451614720, 140252451614720,
4673	STORE, 140252451614720, 140252451618815,
4674	STORE, 140252451618816, 140252451622911,
4675	ERASE, 47380343541760, 47380343541760,
4676	STORE, 94382626803712, 94382626938879,
4677	STORE, 140737488347136, 140737488351231,
4678	STORE, 140730900271104, 140737488351231,
4679	ERASE, 140730900271104, 140730900271104,
4680	STORE, 140730900271104, 140730900275199,
4681	STORE, 93855478120448, 93855478337535,
4682	ERASE, 93855478120448, 93855478120448,
4683	STORE, 93855478120448, 93855478198271,
4684	STORE, 93855478198272, 93855478337535,
4685	ERASE, 93855478198272, 93855478198272,
4686	STORE, 93855478198272, 93855478243327,
4687	STORE, 93855478243328, 93855478288383,
4688	STORE, 93855478288384, 93855478337535,
4689	STORE, 140092686573568, 140092686745599,
4690	ERASE, 140092686573568, 140092686573568,
4691	STORE, 140092686573568, 140092686577663,
4692	STORE, 140092686577664, 140092686745599,
4693	ERASE, 140092686577664, 140092686577664,
4694	STORE, 140092686577664, 140092686700543,
4695	STORE, 140092686700544, 140092686733311,
4696	STORE, 140092686733312, 140092686741503,
4697	STORE, 140092686741504, 140092686745599,
4698	STORE, 140730900537344, 140730900541439,
4699	STORE, 140730900525056, 140730900537343,
4700	STORE, 47540108423168, 47540108431359,
4701	STORE, 47540108431360, 47540108439551,
4702	STORE, 47540108439552, 47540110278655,
4703	STORE, 47540108578816, 47540110278655,
4704	STORE, 47540108439552, 47540108578815,
4705	ERASE, 47540108578816, 47540108578816,
4706	STORE, 47540108578816, 47540110237695,
4707	STORE, 47540110237696, 47540110278655,
4708	STORE, 47540109922304, 47540110237695,
4709	STORE, 47540108578816, 47540109922303,
4710	ERASE, 47540108578816, 47540108578816,
4711	STORE, 47540108578816, 47540109922303,
4712	STORE, 47540110233600, 47540110237695,
4713	STORE, 47540109922304, 47540110233599,
4714	ERASE, 47540109922304, 47540109922304,
4715	STORE, 47540109922304, 47540110233599,
4716	STORE, 47540110262272, 47540110278655,
4717	STORE, 47540110237696, 47540110262271,
4718	ERASE, 47540110237696, 47540110237696,
4719	STORE, 47540110237696, 47540110262271,
4720	ERASE, 47540110262272, 47540110262272,
4721	STORE, 47540110262272, 47540110278655,
4722	ERASE, 47540110237696, 47540110237696,
4723	STORE, 47540110237696, 47540110254079,
4724	STORE, 47540110254080, 47540110262271,
4725	ERASE, 93855478288384, 93855478288384,
4726	STORE, 93855478288384, 93855478333439,
4727	STORE, 93855478333440, 93855478337535,
4728	ERASE, 140092686733312, 140092686733312,
4729	STORE, 140092686733312, 140092686737407,
4730	STORE, 140092686737408, 140092686741503,
4731	ERASE, 47540108423168, 47540108423168,
4732	STORE, 93855492222976, 93855492358143,
4733	STORE, 93855492222976, 93855492493311,
4734	STORE, 140737488347136, 140737488351231,
4735	STORE, 140733498146816, 140737488351231,
4736	ERASE, 140733498146816, 140733498146816,
4737	STORE, 140733498146816, 140733498150911,
4738	STORE, 94170739654656, 94170740367359,
4739	ERASE, 94170739654656, 94170739654656,
4740	STORE, 94170739654656, 94170739703807,
4741	STORE, 94170739703808, 94170740367359,
4742	ERASE, 94170739703808, 94170739703808,
4743	STORE, 94170739703808, 94170740248575,
4744	STORE, 94170740248576, 94170740346879,
4745	STORE, 94170740346880, 94170740367359,
4746	STORE, 140024788877312, 140024789049343,
4747	ERASE, 140024788877312, 140024788877312,
4748	STORE, 140024788877312, 140024788881407,
4749	STORE, 140024788881408, 140024789049343,
4750	ERASE, 140024788881408, 140024788881408,
4751	STORE, 140024788881408, 140024789004287,
4752	STORE, 140024789004288, 140024789037055,
4753	STORE, 140024789037056, 140024789045247,
4754	STORE, 140024789045248, 140024789049343,
4755	STORE, 140733499023360, 140733499027455,
4756	STORE, 140733499011072, 140733499023359,
4757	STORE, 47608006119424, 47608006127615,
4758	STORE, 47608006127616, 47608006135807,
4759	STORE, 47608006135808, 47608006242303,
4760	STORE, 47608006152192, 47608006242303,
4761	STORE, 47608006135808, 47608006152191,
4762	ERASE, 47608006152192, 47608006152192,
4763	STORE, 47608006152192, 47608006225919,
4764	STORE, 47608006225920, 47608006242303,
4765	STORE, 47608006205440, 47608006225919,
4766	STORE, 47608006152192, 47608006205439,
4767	ERASE, 47608006152192, 47608006152192,
4768	STORE, 47608006152192, 47608006205439,
4769	STORE, 47608006221824, 47608006225919,
4770	STORE, 47608006205440, 47608006221823,
4771	ERASE, 47608006205440, 47608006205440,
4772	STORE, 47608006205440, 47608006221823,
4773	STORE, 47608006234112, 47608006242303,
4774	STORE, 47608006225920, 47608006234111,
4775	ERASE, 47608006225920, 47608006225920,
4776	STORE, 47608006225920, 47608006234111,
4777	ERASE, 47608006234112, 47608006234112,
4778	STORE, 47608006234112, 47608006242303,
4779	STORE, 47608006242304, 47608008081407,
4780	STORE, 47608006381568, 47608008081407,
4781	STORE, 47608006242304, 47608006381567,
4782	ERASE, 47608006381568, 47608006381568,
4783	STORE, 47608006381568, 47608008040447,
4784	STORE, 47608008040448, 47608008081407,
4785	STORE, 47608007725056, 47608008040447,
4786	STORE, 47608006381568, 47608007725055,
4787	ERASE, 47608006381568, 47608006381568,
4788	STORE, 47608006381568, 47608007725055,
4789	STORE, 47608008036352, 47608008040447,
4790	STORE, 47608007725056, 47608008036351,
4791	ERASE, 47608007725056, 47608007725056,
4792	STORE, 47608007725056, 47608008036351,
4793	STORE, 47608008065024, 47608008081407,
4794	STORE, 47608008040448, 47608008065023,
4795	ERASE, 47608008040448, 47608008040448,
4796	STORE, 47608008040448, 47608008065023,
4797	ERASE, 47608008065024, 47608008065024,
4798	STORE, 47608008065024, 47608008081407,
4799	STORE, 47608008065024, 47608008093695,
4800	ERASE, 47608008040448, 47608008040448,
4801	STORE, 47608008040448, 47608008056831,
4802	STORE, 47608008056832, 47608008065023,
4803	ERASE, 47608006225920, 47608006225920,
4804	STORE, 47608006225920, 47608006230015,
4805	STORE, 47608006230016, 47608006234111,
4806	ERASE, 94170740346880, 94170740346880,
4807	STORE, 94170740346880, 94170740363263,
4808	STORE, 94170740363264, 94170740367359,
4809	ERASE, 140024789037056, 140024789037056,
4810	STORE, 140024789037056, 140024789041151,
4811	STORE, 140024789041152, 140024789045247,
4812	ERASE, 47608006119424, 47608006119424,
4813	STORE, 140737488347136, 140737488351231,
4814	STORE, 140730264326144, 140737488351231,
4815	ERASE, 140730264326144, 140730264326144,
4816	STORE, 140730264326144, 140730264330239,
4817	STORE, 94653216407552, 94653217120255,
4818	ERASE, 94653216407552, 94653216407552,
4819	STORE, 94653216407552, 94653216456703,
4820	STORE, 94653216456704, 94653217120255,
4821	ERASE, 94653216456704, 94653216456704,
4822	STORE, 94653216456704, 94653217001471,
4823	STORE, 94653217001472, 94653217099775,
4824	STORE, 94653217099776, 94653217120255,
4825	STORE, 140103617011712, 140103617183743,
4826	ERASE, 140103617011712, 140103617011712,
4827	STORE, 140103617011712, 140103617015807,
4828	STORE, 140103617015808, 140103617183743,
4829	ERASE, 140103617015808, 140103617015808,
4830	STORE, 140103617015808, 140103617138687,
4831	STORE, 140103617138688, 140103617171455,
4832	STORE, 140103617171456, 140103617179647,
4833	STORE, 140103617179648, 140103617183743,
4834	STORE, 140730265427968, 140730265432063,
4835	STORE, 140730265415680, 140730265427967,
4836	STORE, 47529177985024, 47529177993215,
4837	STORE, 47529177993216, 47529178001407,
4838	STORE, 47529178001408, 47529178107903,
4839	STORE, 47529178017792, 47529178107903,
4840	STORE, 47529178001408, 47529178017791,
4841	ERASE, 47529178017792, 47529178017792,
4842	STORE, 47529178017792, 47529178091519,
4843	STORE, 47529178091520, 47529178107903,
4844	STORE, 47529178071040, 47529178091519,
4845	STORE, 47529178017792, 47529178071039,
4846	ERASE, 47529178017792, 47529178017792,
4847	STORE, 47529178017792, 47529178071039,
4848	STORE, 47529178087424, 47529178091519,
4849	STORE, 47529178071040, 47529178087423,
4850	ERASE, 47529178071040, 47529178071040,
4851	STORE, 47529178071040, 47529178087423,
4852	STORE, 47529178099712, 47529178107903,
4853	STORE, 47529178091520, 47529178099711,
4854	ERASE, 47529178091520, 47529178091520,
4855	STORE, 47529178091520, 47529178099711,
4856	ERASE, 47529178099712, 47529178099712,
4857	STORE, 47529178099712, 47529178107903,
4858	STORE, 47529178107904, 47529179947007,
4859	STORE, 47529178247168, 47529179947007,
4860	STORE, 47529178107904, 47529178247167,
4861	ERASE, 47529178247168, 47529178247168,
4862	STORE, 47529178247168, 47529179906047,
4863	STORE, 47529179906048, 47529179947007,
4864	STORE, 47529179590656, 47529179906047,
4865	STORE, 47529178247168, 47529179590655,
4866	ERASE, 47529178247168, 47529178247168,
4867	STORE, 47529178247168, 47529179590655,
4868	STORE, 47529179901952, 47529179906047,
4869	STORE, 47529179590656, 47529179901951,
4870	ERASE, 47529179590656, 47529179590656,
4871	STORE, 47529179590656, 47529179901951,
4872	STORE, 47529179930624, 47529179947007,
4873	STORE, 47529179906048, 47529179930623,
4874	ERASE, 47529179906048, 47529179906048,
4875	STORE, 47529179906048, 47529179930623,
4876	ERASE, 47529179930624, 47529179930624,
4877	STORE, 47529179930624, 47529179947007,
4878	STORE, 47529179930624, 47529179959295,
4879	ERASE, 47529179906048, 47529179906048,
4880	STORE, 47529179906048, 47529179922431,
4881	STORE, 47529179922432, 47529179930623,
4882	ERASE, 47529178091520, 47529178091520,
4883	STORE, 47529178091520, 47529178095615,
4884	STORE, 47529178095616, 47529178099711,
4885	ERASE, 94653217099776, 94653217099776,
4886	STORE, 94653217099776, 94653217116159,
4887	STORE, 94653217116160, 94653217120255,
4888	ERASE, 140103617171456, 140103617171456,
4889	STORE, 140103617171456, 140103617175551,
4890	STORE, 140103617175552, 140103617179647,
4891	ERASE, 47529177985024, 47529177985024,
4892	STORE, 94653241135104, 94653241270271,
4893	STORE, 140737488347136, 140737488351231,
4894	STORE, 140736284549120, 140737488351231,
4895	ERASE, 140736284549120, 140736284549120,
4896	STORE, 140736284549120, 140736284553215,
4897	STORE, 93963663822848, 93963664506879,
4898	ERASE, 93963663822848, 93963663822848,
4899	STORE, 93963663822848, 93963663884287,
4900	STORE, 93963663884288, 93963664506879,
4901	ERASE, 93963663884288, 93963663884288,
4902	STORE, 93963663884288, 93963664240639,
4903	STORE, 93963664240640, 93963664379903,
4904	STORE, 93963664379904, 93963664506879,
4905	STORE, 140450188439552, 140450188611583,
4906	ERASE, 140450188439552, 140450188439552,
4907	STORE, 140450188439552, 140450188443647,
4908	STORE, 140450188443648, 140450188611583,
4909	ERASE, 140450188443648, 140450188443648,
4910	STORE, 140450188443648, 140450188566527,
4911	STORE, 140450188566528, 140450188599295,
4912	STORE, 140450188599296, 140450188607487,
4913	STORE, 140450188607488, 140450188611583,
4914	STORE, 140736284577792, 140736284581887,
4915	STORE, 140736284565504, 140736284577791,
4916	STORE, 47182606557184, 47182606565375,
4917	STORE, 47182606565376, 47182606573567,
4918	STORE, 47182606573568, 47182608412671,
4919	STORE, 47182606712832, 47182608412671,
4920	STORE, 47182606573568, 47182606712831,
4921	ERASE, 47182606712832, 47182606712832,
4922	STORE, 47182606712832, 47182608371711,
4923	STORE, 47182608371712, 47182608412671,
4924	STORE, 47182608056320, 47182608371711,
4925	STORE, 47182606712832, 47182608056319,
4926	ERASE, 47182606712832, 47182606712832,
4927	STORE, 47182606712832, 47182608056319,
4928	STORE, 47182608367616, 47182608371711,
4929	STORE, 47182608056320, 47182608367615,
4930	ERASE, 47182608056320, 47182608056320,
4931	STORE, 47182608056320, 47182608367615,
4932	STORE, 47182608396288, 47182608412671,
4933	STORE, 47182608371712, 47182608396287,
4934	ERASE, 47182608371712, 47182608371712,
4935	STORE, 47182608371712, 47182608396287,
4936	ERASE, 47182608396288, 47182608396288,
4937	STORE, 47182608396288, 47182608412671,
4938	STORE, 47182608412672, 47182608523263,
4939	STORE, 47182608429056, 47182608523263,
4940	STORE, 47182608412672, 47182608429055,
4941	ERASE, 47182608429056, 47182608429056,
4942	STORE, 47182608429056, 47182608515071,
4943	STORE, 47182608515072, 47182608523263,
4944	STORE, 47182608490496, 47182608515071,
4945	STORE, 47182608429056, 47182608490495,
4946	ERASE, 47182608429056, 47182608429056,
4947	STORE, 47182608429056, 47182608490495,
4948	STORE, 47182608510976, 47182608515071,
4949	STORE, 47182608490496, 47182608510975,
4950	ERASE, 47182608490496, 47182608490496,
4951	STORE, 47182608490496, 47182608510975,
4952	ERASE, 47182608515072, 47182608515072,
4953	STORE, 47182608515072, 47182608523263,
4954	STORE, 47182608523264, 47182608568319,
4955	ERASE, 47182608523264, 47182608523264,
4956	STORE, 47182608523264, 47182608531455,
4957	STORE, 47182608531456, 47182608568319,
4958	STORE, 47182608551936, 47182608568319,
4959	STORE, 47182608531456, 47182608551935,
4960	ERASE, 47182608531456, 47182608531456,
4961	STORE, 47182608531456, 47182608551935,
4962	STORE, 47182608560128, 47182608568319,
4963	STORE, 47182608551936, 47182608560127,
4964	ERASE, 47182608551936, 47182608551936,
4965	STORE, 47182608551936, 47182608568319,
4966	ERASE, 47182608551936, 47182608551936,
4967	STORE, 47182608551936, 47182608560127,
4968	STORE, 47182608560128, 47182608568319,
4969	ERASE, 47182608560128, 47182608560128,
4970	STORE, 47182608560128, 47182608568319,
4971	STORE, 47182608568320, 47182608916479,
4972	STORE, 47182608609280, 47182608916479,
4973	STORE, 47182608568320, 47182608609279,
4974	ERASE, 47182608609280, 47182608609280,
4975	STORE, 47182608609280, 47182608891903,
4976	STORE, 47182608891904, 47182608916479,
4977	STORE, 47182608822272, 47182608891903,
4978	STORE, 47182608609280, 47182608822271,
4979	ERASE, 47182608609280, 47182608609280,
4980	STORE, 47182608609280, 47182608822271,
4981	STORE, 47182608887808, 47182608891903,
4982	STORE, 47182608822272, 47182608887807,
4983	ERASE, 47182608822272, 47182608822272,
4984	STORE, 47182608822272, 47182608887807,
4985	ERASE, 47182608891904, 47182608891904,
4986	STORE, 47182608891904, 47182608916479,
4987	STORE, 47182608916480, 47182611177471,
4988	STORE, 47182609068032, 47182611177471,
4989	STORE, 47182608916480, 47182609068031,
4990	ERASE, 47182609068032, 47182609068032,
4991	STORE, 47182609068032, 47182611161087,
4992	STORE, 47182611161088, 47182611177471,
4993	STORE, 47182611169280, 47182611177471,
4994	STORE, 47182611161088, 47182611169279,
4995	ERASE, 47182611161088, 47182611161088,
4996	STORE, 47182611161088, 47182611169279,
4997	ERASE, 47182611169280, 47182611169280,
4998	STORE, 47182611169280, 47182611177471,
4999	STORE, 47182611177472, 47182611312639,
5000	ERASE, 47182611177472, 47182611177472,
5001	STORE, 47182611177472, 47182611202047,
5002	STORE, 47182611202048, 47182611312639,
5003	STORE, 47182611263488, 47182611312639,
5004	STORE, 47182611202048, 47182611263487,
5005	ERASE, 47182611202048, 47182611202048,
5006	STORE, 47182611202048, 47182611263487,
5007	STORE, 47182611288064, 47182611312639,
5008	STORE, 47182611263488, 47182611288063,
5009	ERASE, 47182611263488, 47182611263488,
5010	STORE, 47182611263488, 47182611312639,
5011	ERASE, 47182611263488, 47182611263488,
5012	STORE, 47182611263488, 47182611288063,
5013	STORE, 47182611288064, 47182611312639,
5014	STORE, 47182611296256, 47182611312639,
5015	STORE, 47182611288064, 47182611296255,
5016	ERASE, 47182611288064, 47182611288064,
5017	STORE, 47182611288064, 47182611296255,
5018	ERASE, 47182611296256, 47182611296256,
5019	STORE, 47182611296256, 47182611312639,
5020	STORE, 47182611296256, 47182611320831,
5021	STORE, 47182611320832, 47182611484671,
5022	ERASE, 47182611320832, 47182611320832,
5023	STORE, 47182611320832, 47182611333119,
5024	STORE, 47182611333120, 47182611484671,
5025	STORE, 47182611431424, 47182611484671,
5026	STORE, 47182611333120, 47182611431423,
5027	ERASE, 47182611333120, 47182611333120,
5028	STORE, 47182611333120, 47182611431423,
5029	STORE, 47182611476480, 47182611484671,
5030	STORE, 47182611431424, 47182611476479,
5031	ERASE, 47182611431424, 47182611431424,
5032	STORE, 47182611431424, 47182611484671,
5033	ERASE, 47182611431424, 47182611431424,
5034	STORE, 47182611431424, 47182611476479,
5035	STORE, 47182611476480, 47182611484671,
5036	ERASE, 47182611476480, 47182611476480,
5037	STORE, 47182611476480, 47182611484671,
5038	STORE, 47182611484672, 47182612082687,
5039	STORE, 47182611603456, 47182612082687,
5040	STORE, 47182611484672, 47182611603455,
5041	ERASE, 47182611603456, 47182611603456,
5042	STORE, 47182611603456, 47182612029439,
5043	STORE, 47182612029440, 47182612082687,
5044	STORE, 47182611918848, 47182612029439,
5045	STORE, 47182611603456, 47182611918847,
5046	ERASE, 47182611603456, 47182611603456,
5047	STORE, 47182611603456, 47182611918847,
5048	STORE, 47182612025344, 47182612029439,
5049	STORE, 47182611918848, 47182612025343,
5050	ERASE, 47182611918848, 47182611918848,
5051	STORE, 47182611918848, 47182612025343,

33494 more lines aren’t shown here.

mm/damon/dbgfs.c+7−0

 static int dbgfs_rm_context(char *name)
 {
 	struct dentry *root, *dir, **new_dirs;
+	struct inode *inode;
 	struct damon_ctx **new_ctxs;
 	int i, j;
 	int ret = 0;
 	if (!dir)
 		return -ENOENT;
+	inode = d_inode(dir);
+	if (!S_ISDIR(inode->i_mode)) {
+		ret = -EINVAL;
+		goto out_dput;
+	}
 	new_dirs = kmalloc_array(dbgfs_nr_ctxs - 1, sizeof(*dbgfs_dirs),
 			GFP_KERNEL);
 	if (!new_dirs) {

mm/huge_memory.c+6−3

 				entry = pte_wrprotect(entry);
 			if (!young)
 				entry = pte_mkold(entry);
-			/* NOTE: this may set soft-dirty too on some archs */
+			/*
-			if (dirty)
+			 * NOTE: we don't do pte_mkdirty when dirty==true
-				entry = pte_mkdirty(entry);
+			 * because it breaks sparc64 which can sigsegv
+			 * random process.  Need to revisit when we figure
+			 * out what is special with sparc64.
+			 */
 			if (soft_dirty)
 				entry = pte_mksoft_dirty(entry);
 			if (uffd_wp)

mm/hugetlb.c+4−0

@@ -6111,6 +6111,10 @@ int hugetlb_mcopy_atomic_pte(struct mm_struct *dst_mm, · 6110 unmodified lines
6111		6111
6112	ptl = huge_pte_lock(h, dst_mm, dst_pte);	6112	ptl = huge_pte_lock(h, dst_mm, dst_pte);
6113		6113
		6114	ret = -EIO;
		6115	if (PageHWPoison(page))
		6116	goto out_release_unlock;
		6117
6114	/*	6118	/*
6115	* We allow to overwrite a pte marker: consider when both MISSING\|WP	6119	* We allow to overwrite a pte marker: consider when both MISSING\|WP
6116	* registered, we firstly wr-protect a none pte which has no page cache	6120	* registered, we firstly wr-protect a none pte which has no page cache

mm/hugetlb_vmemmap.c+1−0

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	#define pr_fmt(fmt) "HugeTLB: " fmt	11	#define pr_fmt(fmt) "HugeTLB: " fmt
12		12
13	#include <linux/pgtable.h>	13	#include <linux/pgtable.h>
		14	#include <linux/moduleparam.h>
14	#include <linux/bootmem_info.h>	15	#include <linux/bootmem_info.h>
15	#include <asm/pgalloc.h>	16	#include <asm/pgalloc.h>
16	#include <asm/tlbflush.h>	17	#include <asm/tlbflush.h>

mm/kmsan/kmsan.h+2−0

@@ -124,6 +124,8 @@ static __always_inline bool kmsan_in_runtime(void) · 123 unmodified lines
124	{	124	{
125	if ((hardirq_count() >> HARDIRQ_SHIFT) > 1)	125	if ((hardirq_count() >> HARDIRQ_SHIFT) > 1)
126	return true;	126	return true;
		127	if (in_nmi())
		128	return true;
127	return kmsan_get_context()->kmsan_in_runtime;	129	return kmsan_get_context()->kmsan_in_runtime;
128	}	130	}
129		131

mm/memory-failure.c+4−1

 	int res;
 	struct page *hpage = compound_head(p);
 	struct address_space *mapping;
+	bool extra_pins = false;
 	if (!PageHuge(hpage))
 		return MF_DELAYED;
 	mapping = page_mapping(hpage);
 	if (mapping) {
 		res = truncate_error_page(hpage, page_to_pfn(p), mapping);
+		/* The page is kept in page cache. */
+		extra_pins = true;
 		unlock_page(hpage);
 	} else {
 		unlock_page(hpage);
 		}
 	}
-	if (has_extra_refcount(ps, p, false))
+	if (has_extra_refcount(ps, p, extra_pins))
 		res = MF_FAILED;
 	return res;

mm/memremap.c+1−0

@@ -335,6 +335,7 @@ void memremap_pages(struct dev_pagemap pgmap, int nid) · 334 unmodified lines
335	WARN(1, "File system DAX not supported\n");	335	WARN(1, "File system DAX not supported\n");
336	return ERR_PTR(-EINVAL);	336	return ERR_PTR(-EINVAL);
337	}	337	}
		338	params.pgprot = pgprot_decrypted(params.pgprot);
338	break;	339	break;
339	case MEMORY_DEVICE_GENERIC:	340	case MEMORY_DEVICE_GENERIC:
340	break;	341	break;

mm/mmap.c+5−1

 		error = -EINVAL;
 		if (file)
 			goto close_and_free_vma;
+		else if (vma->vm_file)
+			goto unmap_and_free_vma;
 		else
 			goto free_vma;
 	}
 		error = -ENOMEM;
 		if (file)
 			goto close_and_free_vma;
+		else if (vma->vm_file)
+			goto unmap_and_free_vma;
 		else
 			goto free_vma;
 	}
 	/* Undo any partial mapping done by a device driver. */
 	unmap_region(mm, mas.tree, vma, prev, next, vma->vm_start, vma->vm_end);
-	if (vm_flags & VM_SHARED)
+	if (file && (vm_flags & VM_SHARED))
 		mapping_unmap_writable(file->f_mapping);
 free_vma:
 	vm_area_free(vma);

mm/slab_common.c+4−20

 	if (unlikely(size > KMALLOC_MAX_CACHE_SIZE)) {
 		ret = __kmalloc_large_node(size, flags, node);
-		trace_kmalloc(_RET_IP_, ret, size,
+		trace_kmalloc(caller, ret, size,
 			      PAGE_SIZE << get_order(size), flags, node);
 		return ret;
 	}
 	ret = __kmem_cache_alloc_node(s, flags, node, size, caller);
 	ret = kasan_kmalloc(s, ret, size, flags);
-	trace_kmalloc(_RET_IP_, ret, size, s->size, flags, node);
+	trace_kmalloc(caller, ret, size, s->size, flags, node);
 	return ret;
 }
 /**
  * __ksize -- Report full size of underlying allocation
- * @objp: pointer to the object
+ * @object: pointer to the object
  *
  * This should only be used internally to query the true size of allocations.
  * It is not meant to be a way to discover the usable size of an allocation
  * the originally requested allocation size may trigger KASAN, UBSAN_BOUNDS,
  * and/or FORTIFY_SOURCE.
  *
- * Return: size of the actual memory used by @objp in bytes
+ * Return: size of the actual memory used by @object in bytes
  */
 size_t __ksize(const void *object)
 {
 	return slab_ksize(folio_slab(folio)->slab_cache);
 }
-#ifdef CONFIG_TRACING
 void *kmalloc_trace(struct kmem_cache *s, gfp_t gfpflags, size_t size)
 {
 	void *ret = __kmem_cache_alloc_node(s, gfpflags, NUMA_NO_NODE,
 	return ret;
 }
 EXPORT_SYMBOL(kmalloc_node_trace);
-#endif /* !CONFIG_TRACING */
 #endif /* !CONFIG_SLOB */
 gfp_t kmalloc_fix_flags(gfp_t flags)
 }
 EXPORT_SYMBOL(kfree_sensitive);
-/**
- * ksize - get the actual amount of memory allocated for a given object
- * @objp: Pointer to the object
- *
- * kmalloc may internally round up allocations and return more memory
- * than requested. ksize() can be used to determine the actual amount of
- * memory allocated. The caller may use this additional memory, even though
- * a smaller amount of memory was initially specified with the kmalloc call.
- * The caller must guarantee that objp points to a valid object previously
- * allocated with either kmalloc() or kmem_cache_alloc(). The object
- * must not be freed during the duration of the call.
- *
- * Return: size of the actual memory used by @objp in bytes
- */
 size_t ksize(const void *objp)
 {
 	size_t size;

mm/userfaultfd.c+1−1

@@ -64,7 +64,7 @@ int mfill_atomic_install_pte(struct mm_struct dst_mm, pmd_t dst_pmd, · 63 unmodified lines
64	pte_t _dst_pte, *dst_pte;	64	pte_t _dst_pte, *dst_pte;
65	bool writable = dst_vma->vm_flags & VM_WRITE;	65	bool writable = dst_vma->vm_flags & VM_WRITE;
66	bool vm_shared = dst_vma->vm_flags & VM_SHARED;	66	bool vm_shared = dst_vma->vm_flags & VM_SHARED;
67	bool page_in_cache = page->mapping;	67	bool page_in_cache = page_mapping(page);
68	spinlock_t *ptl;	68	spinlock_t *ptl;
69	struct inode *inode;	69	struct inode *inode;
70	pgoff_t offset, max_off;	70	pgoff_t offset, max_off;

net/can/af_can.c+2−1

 	/* insert new receiver  (dev,canid,mask) -> (func,data) */
-	if (dev && dev->type != ARPHRD_CAN)
+	if (dev && (dev->type != ARPHRD_CAN || !can_get_ml_priv(dev)))
 		return -ENODEV;
 	if (dev && !net_eq(net, dev_net(dev)))
 static __exit void can_exit(void)
 {
 	/* protocol unregister */
+	dev_remove_pack(&canxl_packet);
 	dev_remove_pack(&canfd_packet);
 	dev_remove_pack(&can_packet);
 	sock_unregister(PF_CAN);

net/can/isotp.c+38−33

 #define ISOTP_FC_WT 1		/* wait */
 #define ISOTP_FC_OVFLW 2	/* overflow */
+#define ISOTP_FC_TIMEOUT 1	/* 1 sec */
+#define ISOTP_ECHO_TIMEOUT 2	/* 2 secs */
 enum {
 	ISOTP_IDLE = 0,
 	ISOTP_WAIT_FIRST_FC,
 	so->lastrxcf_tstamp = ktime_set(0, 0);
 	/* start rx timeout watchdog */
-	hrtimer_start(&so->rxtimer, ktime_set(1, 0), HRTIMER_MODE_REL_SOFT);
+	hrtimer_start(&so->rxtimer, ktime_set(ISOTP_FC_TIMEOUT, 0),
+		      HRTIMER_MODE_REL_SOFT);
 	return 0;
 }
 	return 0;
 }
+static void isotp_send_cframe(struct isotp_sock *so);
 static int isotp_rcv_fc(struct isotp_sock *so, struct canfd_frame *cf, int ae)
 {
 	struct sock *sk = &so->sk;
 	case ISOTP_FC_CTS:
 		so->tx.bs = 0;
 		so->tx.state = ISOTP_SENDING;
-		/* start cyclic timer for sending CF frame */
+		/* send CF frame and enable echo timeout handling */
-		hrtimer_start(&so->txtimer, so->tx_gap,
+		hrtimer_start(&so->txtimer, ktime_set(ISOTP_ECHO_TIMEOUT, 0),
 			      HRTIMER_MODE_REL_SOFT);
+		isotp_send_cframe(so);
 		break;
 	case ISOTP_FC_WT:
 		/* start timer to wait for next FC frame */
-		hrtimer_start(&so->txtimer, ktime_set(1, 0),
+		hrtimer_start(&so->txtimer, ktime_set(ISOTP_FC_TIMEOUT, 0),
 			      HRTIMER_MODE_REL_SOFT);
 		break;
 	/* perform blocksize handling, if enabled */
 	if (!so->rxfc.bs || ++so->rx.bs < so->rxfc.bs) {
 		/* start rx timeout watchdog */
-		hrtimer_start(&so->rxtimer, ktime_set(1, 0),
+		hrtimer_start(&so->rxtimer, ktime_set(ISOTP_FC_TIMEOUT, 0),
 			      HRTIMER_MODE_REL_SOFT);
 		return 0;
 	}
 	struct isotp_sock *so = isotp_sk(sk);
 	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
-	/* only handle my own local echo skb's */
+	/* only handle my own local echo CF/SF skb's (no FF!) */
 	if (skb->sk != sk || so->cfecho != *(u32 *)cf->data)
 		return;
 	if (so->txfc.bs && so->tx.bs >= so->txfc.bs) {
 		/* stop and wait for FC with timeout */
 		so->tx.state = ISOTP_WAIT_FC;
-		hrtimer_start(&so->txtimer, ktime_set(1, 0),
+		hrtimer_start(&so->txtimer, ktime_set(ISOTP_FC_TIMEOUT, 0),
 			      HRTIMER_MODE_REL_SOFT);
 		return;
 	}
 	/* no gap between data frames needed => use burst mode */
 	if (!so->tx_gap) {
+		/* enable echo timeout handling */
+		hrtimer_start(&so->txtimer, ktime_set(ISOTP_ECHO_TIMEOUT, 0),
+			      HRTIMER_MODE_REL_SOFT);
 		isotp_send_cframe(so);
 		return;
 	}
 			/* start timeout for unlikely lost echo skb */
 			hrtimer_set_expires(&so->txtimer,
 					    ktime_add(ktime_get(),
-						      ktime_set(2, 0)));
+						      ktime_set(ISOTP_ECHO_TIMEOUT, 0)));
 			restart = HRTIMER_RESTART;
 			/* push out the next consecutive frame */
 		break;
 	default:
-		WARN_ON_ONCE(1);
+		WARN_ONCE(1, "can-isotp: tx timer state %08X cfecho %08X\n",
+			  so->tx.state, so->cfecho);
 	}
 	return restart;
 	struct canfd_frame *cf;
 	int ae = (so->opt.flags & CAN_ISOTP_EXTEND_ADDR) ? 1 : 0;
 	int wait_tx_done = (so->opt.flags & CAN_ISOTP_WAIT_TX_DONE) ? 1 : 0;
-	s64 hrtimer_sec = 0;
+	s64 hrtimer_sec = ISOTP_ECHO_TIMEOUT;
 	int off;
 	int err;
 		err = wait_event_interruptible(so->wait, so->tx.state == ISOTP_IDLE);
 		if (err)
 			goto err_out;
+		so->tx.state = ISOTP_SENDING;
 	}
 	if (!size || size > MAX_MSG_LENGTH) {
 	cf = (struct canfd_frame *)skb->data;
 	skb_put_zero(skb, so->ll.mtu);
+	/* cfecho should have been zero'ed by init / former isotp_rcv_echo() */
+	if (so->cfecho)
+		pr_notice_once("can-isotp: uninit cfecho %08X\n", so->cfecho);
 	/* check for single frame transmission depending on TX_DL */
 	if (size <= so->tx.ll_dl - SF_PCI_SZ4 - ae - off) {
 		/* The message size generally fits into a SingleFrame - good.
 		else
 			cf->data[ae] |= size;
-		so->tx.state = ISOTP_IDLE;
+		/* set CF echo tag for isotp_rcv_echo() (SF-mode) */
-		wake_up_interruptible(&so->wait);
+		so->cfecho = *(u32 *)cf->data;
-		/* don't enable wait queue for a single frame transmission */
-		wait_tx_done = 0;
 	} else {
 		/* send first frame */
 			/* disable wait for FCs due to activated block size */
 			so->txfc.bs = 0;
-			/* cfecho should have been zero'ed by init */
+			/* set CF echo tag for isotp_rcv_echo() (CF-mode) */
-			if (so->cfecho)
-				pr_notice_once("can-isotp: no fc cfecho %08X\n",
-					       so->cfecho);
-			/* set consecutive frame echo tag */
 			so->cfecho = *(u32 *)cf->data;
-			/* switch directly to ISOTP_SENDING state */
-			so->tx.state = ISOTP_SENDING;
-			/* start timeout for unlikely lost echo skb */
-			hrtimer_sec = 2;
 		} else {
 			/* standard flow control check */
 			so->tx.state = ISOTP_WAIT_FIRST_FC;
 			/* start timeout for FC */
-			hrtimer_sec = 1;
+			hrtimer_sec = ISOTP_FC_TIMEOUT;
-		}
-		hrtimer_start(&so->txtimer, ktime_set(hrtimer_sec, 0),
+			/* no CF echo tag for isotp_rcv_echo() (FF-mode) */
-			      HRTIMER_MODE_REL_SOFT);
+			so->cfecho = 0;
+		}
 	}
+	hrtimer_start(&so->txtimer, ktime_set(hrtimer_sec, 0),
+		      HRTIMER_MODE_REL_SOFT);
 	/* send the first or only CAN frame */
 	cf->flags = so->ll.tx_flags;
 			       __func__, ERR_PTR(err));
 		/* no transmission -> no timeout monitoring */
-		if (hrtimer_sec)
+		hrtimer_cancel(&so->txtimer);
-			hrtimer_cancel(&so->txtimer);
 		/* reset consecutive frame echo tag */
 		so->cfecho = 0;

net/can/j1939/main.c+3−0

@@ -336,6 +336,9 @@ int j1939_send_one(struct j1939_priv priv, struct sk_buff skb) · 335 unmodified lines
336	/* re-claim the CAN_HDR from the SKB */	336	/* re-claim the CAN_HDR from the SKB */
337	cf = skb_push(skb, J1939_CAN_HDR);	337	cf = skb_push(skb, J1939_CAN_HDR);
338		338
		339	/* initialize header structure */
		340	memset(cf, 0, J1939_CAN_HDR);
		341
339	/* make it a full can frame again */	342	/* make it a full can frame again */
340	skb_put(skb, J1939_CAN_FTR + (8 - dlc));	343	skb_put(skb, J1939_CAN_FTR + (8 - dlc));
341		344

net/core/skbuff.c+19−17

@@ -4134,23 +4134,25 @@ struct sk_buff skb_segment(struct sk_buff head_skb, · 4133 unmodified lines
4134	int i = 0;	4134	int i = 0;
4135	int pos;	4135	int pos;
4136		4136
4137	if (list_skb && !list_skb->head_frag && skb_headlen(list_skb) &&	4137	if ((skb_shinfo(head_skb)->gso_type & SKB_GSO_DODGY) &&
4138	(skb_shinfo(head_skb)->gso_type & SKB_GSO_DODGY)) {	4138	mss != GSO_BY_FRAGS && mss != skb_headlen(head_skb)) {
4139	/* gso_size is untrusted, and we have a frag_list with a linear	4139	struct sk_buff *check_skb;
4140	* non head_frag head.	4140
4141	*	4141	for (check_skb = list_skb; check_skb; check_skb = check_skb->next) {
4142	* (we assume checking the first list_skb member suffices;	4142	if (skb_headlen(check_skb) && !check_skb->head_frag) {
4143	* i.e if either of the list_skb members have non head_frag	4143	/* gso_size is untrusted, and we have a frag_list with
4144	* head, then the first one has too).	4144	* a linear non head_frag item.
4145	*	4145	*
4146	* If head_skb's headlen does not fit requested gso_size, it	4146	* If head_skb's headlen does not fit requested gso_size,
4147	* means that the frag_list members do NOT terminate on exact	4147	* it means that the frag_list members do NOT terminate
4148	* gso_size boundaries. Hence we cannot perform skb_frag_t page	4148	* on exact gso_size boundaries. Hence we cannot perform
4149	* sharing. Therefore we must fallback to copying the frag_list	4149	* skb_frag_t page sharing. Therefore we must fallback to
4150	* skbs; we do so by disabling SG.	4150	* copying the frag_list skbs; we do so by disabling SG.
4151	*/	4151	*/
4152	if (mss != GSO_BY_FRAGS && mss != skb_headlen(head_skb))	4152	features &= ~NETIF_F_SG;
4153	features &= ~NETIF_F_SG;	4153	break;
		4154	}
		4155	}
4154	}	4156	}
4155		4157
4156	__skb_push(head_skb, doffset);	4158	__skb_push(head_skb, doffset);

net/core/skmsg.c+2−5

 	}
 }
-void sk_psock_stop(struct sk_psock *psock, bool wait)
+void sk_psock_stop(struct sk_psock *psock)
 {
 	spin_lock_bh(&psock->ingress_lock);
 	sk_psock_clear_state(psock, SK_PSOCK_TX_ENABLED);
 	sk_psock_cork_free(psock);
 	__sk_psock_zap_ingress(psock);
 	spin_unlock_bh(&psock->ingress_lock);
-	if (wait)
-		cancel_work_sync(&psock->work);
 }
 static void sk_psock_done_strp(struct sk_psock *psock);
 		sk_psock_stop_verdict(sk, psock);
 	write_unlock_bh(&sk->sk_callback_lock);
-	sk_psock_stop(psock, false);
+	sk_psock_stop(psock);
 	INIT_RCU_WORK(&psock->rwork, sk_psock_destroy);
 	queue_rcu_work(system_wq, &psock->rwork);

net/core/sock_map.c+4−3

 	saved_destroy = psock->saved_destroy;
 	sock_map_remove_links(sk, psock);
 	rcu_read_unlock();
-	sk_psock_stop(psock, false);
+	sk_psock_stop(psock);
 	sk_psock_put(sk, psock);
 	saved_destroy(sk);
 }
 	saved_close = psock->saved_close;
 	sock_map_remove_links(sk, psock);
 	rcu_read_unlock();
-	sk_psock_stop(psock, true);
+	sk_psock_stop(psock);
-	sk_psock_put(sk, psock);
 	release_sock(sk);
+	cancel_work_sync(&psock->work);
+	sk_psock_put(sk, psock);
 	saved_close(sk, timeout);
 }
 EXPORT_SYMBOL_GPL(sock_map_close);

net/ipv4/tcp.c+1−1

@@ -3647,7 +3647,7 @@ int do_tcp_setsockopt(struct sock *sk, int level, int optname, · 3646 unmodified lines
3647	case TCP_REPAIR_OPTIONS:	3647	case TCP_REPAIR_OPTIONS:
3648	if (!tp->repair)	3648	if (!tp->repair)
3649	err = -EINVAL;	3649	err = -EINVAL;
3650	else if (sk->sk_state == TCP_ESTABLISHED)	3650	else if (sk->sk_state == TCP_ESTABLISHED && !tp->bytes_sent)
3651	err = tcp_repair_options_est(sk, optval, optlen);	3651	err = tcp_repair_options_est(sk, optval, optlen);
3652	else	3652	else
3653	err = -EPERM;	3653	err = -EPERM;

net/ipv4/tcp_bpf.c+5−3

 {
 	bool cork = false, enospc = sk_msg_full(msg);
 	struct sock *sk_redir;
-	u32 tosend, delta = 0;
+	u32 tosend, origsize, sent, delta = 0;
 	u32 eval = __SK_NONE;
 	int ret;
 			cork = true;
 			psock->cork = NULL;
 		}
-		sk_msg_return(sk, msg, msg->sg.size);
+		sk_msg_return(sk, msg, tosend);
 		release_sock(sk);
+		origsize = msg->sg.size;
 		ret = tcp_bpf_sendmsg_redir(sk_redir, msg, tosend, flags);
+		sent = origsize - msg->sg.size;
 		if (eval == __SK_REDIRECT)
 			sock_put(sk_redir);
 		    msg->sg.data[msg->sg.start].page_link &&
 		    msg->sg.data[msg->sg.start].length) {
 			if (eval == __SK_REDIRECT)
-				sk_mem_charge(sk, msg->sg.size);
+				sk_mem_charge(sk, tosend - sent);
 			goto more_data;
 		}
 	}

net/ipv6/addrlabel.c+1−0

@@ -437,6 +437,7 @@ static void ip6addrlbl_putmsg(struct nlmsghdr *nlh, · 436 unmodified lines
437	{	437	{
438	struct ifaddrlblmsg *ifal = nlmsg_data(nlh);	438	struct ifaddrlblmsg *ifal = nlmsg_data(nlh);
439	ifal->ifal_family = AF_INET6;	439	ifal->ifal_family = AF_INET6;
		440	ifal->__ifal_reserved = 0;
440	ifal->ifal_prefixlen = prefixlen;	441	ifal->ifal_prefixlen = prefixlen;
441	ifal->ifal_flags = 0;	442	ifal->ifal_flags = 0;
442	ifal->ifal_index = ifindex;	443	ifal->ifal_index = ifindex;

net/mac80211/main.c+6−2

 	ieee80211_led_exit(local);
 	destroy_workqueue(local->workqueue);
  fail_workqueue:
-	if (local->wiphy_ciphers_allocated)
+	if (local->wiphy_ciphers_allocated) {
 		kfree(local->hw.wiphy->cipher_suites);
+		local->wiphy_ciphers_allocated = false;
+	}
 	kfree(local->int_scan_req);
 	return result;
 }
 	mutex_destroy(&local->iflist_mtx);
 	mutex_destroy(&local->mtx);
-	if (local->wiphy_ciphers_allocated)
+	if (local->wiphy_ciphers_allocated) {
 		kfree(local->hw.wiphy->cipher_suites);
+		local->wiphy_ciphers_allocated = false;
+	}
 	idr_for_each(&local->ack_status_frames,
 		     ieee80211_free_ack_frame, NULL);

net/mac80211/mesh_pathtbl.c+1−1

@@ -710,7 +710,7 @@ int mesh_path_send_to_gates(struct mesh_path *mpath) · 709 unmodified lines
710	void mesh_path_discard_frame(struct ieee80211_sub_if_data *sdata,	710	void mesh_path_discard_frame(struct ieee80211_sub_if_data *sdata,
711	struct sk_buff *skb)	711	struct sk_buff *skb)
712	{	712	{
713	kfree_skb(skb);	713	ieee80211_free_txskb(&sdata->local->hw, skb);
714	sdata->u.mesh.mshstats.dropped_frames_no_route++;	714	sdata->u.mesh.mshstats.dropped_frames_no_route++;
715	}	715	}
716		716

net/mac80211/s1g.c+3−0

@@ -112,6 +112,9 @@ ieee80211_s1g_rx_twt_setup(struct ieee80211_sub_if_data *sdata, · 111 unmodified lines
112	goto out;	112	goto out;
113	}	113	}
114		114
		115	/* TWT Information not supported yet */
		116	twt->control \|= IEEE80211_TWT_CONTROL_RX_DISABLED;
		117
115	drv_add_twt_setup(sdata->local, sdata, &sta->sta, twt);	118	drv_add_twt_setup(sdata->local, sdata, &sta->sta, twt);
116	out:	119	out:
117	ieee80211_s1g_send_twt_setup(sdata, mgmt->sa, sdata->vif.addr, twt);	120	ieee80211_s1g_send_twt_setup(sdata, mgmt->sa, sdata->vif.addr, twt);

net/mac80211/tx.c+5−0

 	if (likely(!is_multicast_ether_addr(eth->h_dest)))
 		goto normal;
+	if (unlikely(!ieee80211_sdata_running(sdata))) {
+		kfree_skb(skb);
+		return NETDEV_TX_OK;
+	}
 	if (unlikely(ieee80211_multicast_to_unicast(skb, dev))) {
 		struct sk_buff_head queue;

net/mctp/af_mctp.c+3−1

 	rc = mctp_neigh_init();
 	if (rc)
-		goto err_unreg_proto;
+		goto err_unreg_routes;
 	mctp_device_init();
 	return 0;
+err_unreg_routes:
+	mctp_routes_exit();
 err_unreg_proto:
 	proto_unregister(&mctp_proto);
 err_unreg_sock:

net/mctp/route.c+1−1

@@ -1400,7 +1400,7 @@ int __init mctp_routes_init(void) · 1399 unmodified lines
1400	return register_pernet_subsys(&mctp_net_ops);	1400	return register_pernet_subsys(&mctp_net_ops);
1401	}	1401	}
1402		1402
1403	void __exit mctp_routes_exit(void)	1403	void mctp_routes_exit(void)
1404	{	1404	{
1405	unregister_pernet_subsys(&mctp_net_ops);	1405	unregister_pernet_subsys(&mctp_net_ops);
1406	rtnl_unregister(PF_MCTP, RTM_DELROUTE);	1406	rtnl_unregister(PF_MCTP, RTM_DELROUTE);

net/netfilter/nf_tables_api.c+2−1

@@ -10090,7 +10090,8 @@ static void __net_exit nf_tables_exit_net(struct net *net) · 10089 unmodified lines
10090	struct nftables_pernet *nft_net = nft_pernet(net);	10090	struct nftables_pernet *nft_net = nft_pernet(net);
10091		10091
10092	mutex_lock(&nft_net->commit_mutex);	10092	mutex_lock(&nft_net->commit_mutex);
10093	if (!list_empty(&nft_net->commit_list))	10093	if (!list_empty(&nft_net->commit_list) \|\|
		10094	!list_empty(&nft_net->module_list))
10094	__nf_tables_abort(net, NFNL_ABORT_NONE);	10095	__nf_tables_abort(net, NFNL_ABORT_NONE);
10095	__nft_release_tables(net);	10096	__nft_release_tables(net);
10096	mutex_unlock(&nft_net->commit_mutex);	10097	mutex_unlock(&nft_net->commit_mutex);

net/netfilter/nfnetlink.c+1−0

@@ -294,6 +294,7 @@ replay: · 293 unmodified lines
294	nfnl_lock(subsys_id);	294	nfnl_lock(subsys_id);
295	if (nfnl_dereference_protected(subsys_id) != ss \|\|	295	if (nfnl_dereference_protected(subsys_id) != ss \|\|
296	nfnetlink_find_client(type, ss) != nc) {	296	nfnetlink_find_client(type, ss) != nc) {
		297	nfnl_unlock(subsys_id);
297	err = -EAGAIN;	298	err = -EAGAIN;
298	break;	299	break;
299	}	300	}

net/sctp/outqueue.c+8−5

 {
 	struct sctp_outq *q = &asoc->outqueue;
 	struct sctp_chunk *chk, *temp;
+	struct sctp_stream_out *sout;
 	q->sched->unsched_all(&asoc->stream);
 		sctp_sched_dequeue_common(q, chk);
 		asoc->sent_cnt_removable--;
 		asoc->abandoned_unsent[SCTP_PR_INDEX(PRIO)]++;
-		if (chk->sinfo.sinfo_stream < asoc->stream.outcnt) {
-			struct sctp_stream_out *streamout =
-				SCTP_SO(&asoc->stream, chk->sinfo.sinfo_stream);
-			streamout->ext->abandoned_unsent[SCTP_PR_INDEX(PRIO)]++;
+		sout = SCTP_SO(&asoc->stream, chk->sinfo.sinfo_stream);
-		}
+		sout->ext->abandoned_unsent[SCTP_PR_INDEX(PRIO)]++;
+		/* clear out_curr if all frag chunks are pruned */
+		if (asoc->stream.out_curr == sout &&
+		    list_is_last(&chk->frag_list, &chk->msg->chunks))
+			asoc->stream.out_curr = NULL;
 		msg_len -= chk->skb->truesize + sizeof(struct sctp_chunk);
 		sctp_chunk_free(chk);

net/tipc/netlink_compat.c+1−1

@@ -880,7 +880,7 @@ static int tipc_nl_compat_name_table_dump_header(struct tipc_nl_compat_msg *msg) · 879 unmodified lines
880	};	880	};
881		881
882	ntq = (struct tipc_name_table_query *)TLV_DATA(msg->req);	882	ntq = (struct tipc_name_table_query *)TLV_DATA(msg->req);
883	if (TLV_GET_DATA_LEN(msg->req) < sizeof(struct tipc_name_table_query))	883	if (TLV_GET_DATA_LEN(msg->req) < (int)sizeof(struct tipc_name_table_query))
884	return -EINVAL;	884	return -EINVAL;
885		885
886	depth = ntohl(ntq->depth);	886	depth = ntohl(ntq->depth);

net/wireless/reg.c+9−3

 static int query_regdb_file(const char *alpha2)
 {
+	int err;
 	ASSERT_RTNL();
 	if (regdb)
 	if (!alpha2)
 		return -ENOMEM;
-	return request_firmware_nowait(THIS_MODULE, true, "regulatory.db",
+	err = request_firmware_nowait(THIS_MODULE, true, "regulatory.db",
-				       &reg_pdev->dev, GFP_KERNEL,
+				      &reg_pdev->dev, GFP_KERNEL,
-				       (void *)alpha2, regdb_fw_cb);
+				      (void *)alpha2, regdb_fw_cb);
+	if (err)
+		kfree(alpha2);
+	return err;
 }
 int reg_reload_regdb(void)

net/wireless/scan.c+3−1

@@ -1674,7 +1674,9 @@ cfg80211_update_known_bss(struct cfg80211_registered_device *rdev, · 1673 unmodified lines
1674	if (old == rcu_access_pointer(known->pub.ies))	1674	if (old == rcu_access_pointer(known->pub.ies))
1675	rcu_assign_pointer(known->pub.ies, new->pub.beacon_ies);	1675	rcu_assign_pointer(known->pub.ies, new->pub.beacon_ies);
1676		1676
1677	cfg80211_update_hidden_bsses(known, new->pub.beacon_ies, old);	1677	cfg80211_update_hidden_bsses(known,
		1678	rcu_access_pointer(new->pub.beacon_ies),
		1679	old);
1678		1680
1679	if (old)	1681	if (old)
1680	kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head);	1682	kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head);

net/wireless/util.c+4−2

 	tmp = result;
 	tmp *= SCALE;
 	do_div(tmp, mcs_divisors[rate->mcs]);
-	result = tmp;
 	/* and take NSS */
-	result = (result * rate->nss) / 8;
+	tmp *= rate->nss;
+	do_div(tmp, 8);
+	result = tmp;
 	return result / 10000;
 }

scripts/min-tool-version.sh+1−1

@@ -25,7 +25,7 @@ icc) · 24 unmodified lines
25	;;	25	;;
26	llvm)	26	llvm)
27	if [ "$SRCARCH" = s390 ]; then	27	if [ "$SRCARCH" = s390 ]; then
28	echo 14.0.0	28	echo 15.0.0
29	else	29	else
30	echo 11.0.0	30	echo 11.0.0
31	fi	31	fi

sound/arm/pxa2xx-ac97-lib.c+3−1

 		goto err_clk2;
 	irq = platform_get_irq(dev, 0);
-	if (!irq)
+	if (irq < 0) {
+		ret = irq;
 		goto err_irq;
+	}
 	ret = request_irq(irq, pxa2xx_ac97_irq, 0, "AC97", NULL);
 	if (ret < 0)

sound/core/memalloc.c+8−7

 #include <linux/slab.h>
 #include <linux/mm.h>
 #include <linux/dma-mapping.h>
+#include <linux/dma-map-ops.h>
 #include <linux/genalloc.h>
 #include <linux/highmem.h>
 #include <linux/vmalloc.h>
 	sgt = dma_alloc_noncontiguous(dmab->dev.dev, size, dmab->dev.dir,
 				      DEFAULT_GFP, 0);
-	if (!sgt) {
 #ifdef CONFIG_SND_DMA_SGBUF
+	if (!sgt && !get_dma_ops(dmab->dev.dev)) {
 		if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_WC_SG)
 			dmab->dev.type = SNDRV_DMA_TYPE_DEV_WC_SG_FALLBACK;
 		else
 			dmab->dev.type = SNDRV_DMA_TYPE_DEV_SG_FALLBACK;
 		return snd_dma_sg_fallback_alloc(dmab, size);
-#else
-		return NULL;
-#endif
 	}
+#endif
+	if (!sgt)
+		return NULL;
 	dmab->dev.need_sync = dma_need_sync(dmab->dev.dev,
 					    sg_dma_address(sgt->sgl));
 /*
  * Entry points
  */
-static const struct snd_malloc_ops *dma_ops[] = {
+static const struct snd_malloc_ops *snd_dma_ops[] = {
 	[SNDRV_DMA_TYPE_CONTINUOUS] = &snd_dma_continuous_ops,
 	[SNDRV_DMA_TYPE_VMALLOC] = &snd_dma_vmalloc_ops,
 #ifdef CONFIG_HAS_DMA
 	if (WARN_ON_ONCE(!dmab))
 		return NULL;
 	if (WARN_ON_ONCE(dmab->dev.type <= SNDRV_DMA_TYPE_UNKNOWN ||
-			 dmab->dev.type >= ARRAY_SIZE(dma_ops)))
+			 dmab->dev.type >= ARRAY_SIZE(snd_dma_ops)))
 		return NULL;
-	return dma_ops[dmab->dev.type];
+	return snd_dma_ops[dmab->dev.type];
 }

sound/hda/hdac_sysfs.c+3−1

 		return -ENOMEM;
 	kobject_init(kobj, &widget_ktype);
 	err = kobject_add(kobj, parent, "%02x", nid);
-	if (err < 0)
+	if (err < 0) {
+		kobject_put(kobj);
 		return err;
+	}
 	err = sysfs_create_group(kobj, group);
 	if (err < 0) {
 		kobject_put(kobj);

sound/pci/hda/hda_intel.c+7−4

 	int timeout;
 	/*
-	 * the codecs are sharing the first link setting by default
+	 * Changes to LCTL.SCF are only needed for the first multi-link dealing
-	 * If other links are enabled for stream, they need similar fix
+	 * with external codecs
 	 */
 	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 	val &= ~AZX_ML_LCTL_SPA;
 	/* 0. check lctl register value is correct or not */
 	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
-	/* if SCF is already set, let's use it */
+	/* only perform additional configurations if the SCF is initially based on 6MHz */
 	if ((val & AZX_ML_LCTL_SCF) != 0)
 		return;
 	if (ret)
 		goto set_spa;
-	/* 2. update SCF to select a properly audio clock*/
+	/* 2. update SCF to select an audio clock different from 6MHz */
 	val &= ~AZX_ML_LCTL_SCF;
 	val |= intel_get_lctl_scf(chip);
 	writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 	{ PCI_DEVICE(0x1002, 0xab28),
 	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
 	  AZX_DCAPS_PM_RUNTIME },
+	{ PCI_DEVICE(0x1002, 0xab30),
+	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
+	  AZX_DCAPS_PM_RUNTIME },
 	{ PCI_DEVICE(0x1002, 0xab38),
 	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
 	  AZX_DCAPS_PM_RUNTIME },

sound/pci/hda/patch_ca0132.c+1−0

@@ -1306,6 +1306,7 @@ static const struct snd_pci_quirk ca0132_quirks[] = { · 1305 unmodified lines
1306	SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),	1306	SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1307	SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),	1307	SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1308	SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),	1308	SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
		1309	SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1309	SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),	1310	SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1310	SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),	1311	SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1311	SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),	1312	SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),

sound/pci/hda/patch_realtek.c+2−0

 	SND_PCI_QUIRK(0x1043, 0x1e8e, "ASUS Zephyrus G15", ALC289_FIXUP_ASUS_GA401),
 	SND_PCI_QUIRK(0x1043, 0x1c52, "ASUS Zephyrus G15 2022", ALC289_FIXUP_ASUS_GA401),
 	SND_PCI_QUIRK(0x1043, 0x1f11, "ASUS Zephyrus G14", ALC289_FIXUP_ASUS_GA401),
+	SND_PCI_QUIRK(0x1043, 0x1f12, "ASUS UM5302", ALC287_FIXUP_CS35L41_I2C_2),
 	SND_PCI_QUIRK(0x1043, 0x1f92, "ASUS ROG Flow X16", ALC289_FIXUP_ASUS_GA401),
 	SND_PCI_QUIRK(0x1043, 0x3030, "ASUS ZN270IE", ALC256_FIXUP_ASUS_AIO_GPIO2),
 	SND_PCI_QUIRK(0x1043, 0x831a, "ASUS P901", ALC269_FIXUP_STEREO_DMIC),
 	SND_PCI_QUIRK(0x17aa, 0x511f, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
 	SND_PCI_QUIRK(0x17aa, 0x9e54, "LENOVO NB", ALC269_FIXUP_LENOVO_EAPD),
 	SND_PCI_QUIRK(0x1849, 0x1233, "ASRock NUC Box 1100", ALC233_FIXUP_NO_AUDIO_JACK),
+	SND_PCI_QUIRK(0x1849, 0xa233, "Positivo Master C6300", ALC269_FIXUP_HEADSET_MIC),
 	SND_PCI_QUIRK(0x19e5, 0x3204, "Huawei MACH-WX9", ALC256_FIXUP_HUAWEI_MACH_WX9_PINS),
 	SND_PCI_QUIRK(0x19e5, 0x320f, "Huawei WRT-WX9 ", ALC256_FIXUP_ASUS_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1b35, 0x1235, "CZC B20", ALC269_FIXUP_CZC_B20),

sound/soc/codecs/adau1372.c+17−14

 #include "adau-utils.h"
 struct adau1372 {
-	struct clk *clk;
 	struct regmap *regmap;
 	void (*switch_mode)(struct device *dev);
 	bool use_pll;
 		       2, 1, 0, adau1372_pga_boost_tlv),
 	SOC_SINGLE_TLV("PGA 3 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
 		       3, 1, 0, adau1372_pga_boost_tlv),
-	SOC_SINGLE("PGA 0 Capture Switch", ADAU1372_REG_PGA_CTRL(0), 7, 1, 1),
+	SOC_SINGLE("PGA 0 Capture Switch", ADAU1372_REG_PGA_CTRL(0), 7, 1, 0),
-	SOC_SINGLE("PGA 1 Capture Switch", ADAU1372_REG_PGA_CTRL(1), 7, 1, 1),
+	SOC_SINGLE("PGA 1 Capture Switch", ADAU1372_REG_PGA_CTRL(1), 7, 1, 0),
-	SOC_SINGLE("PGA 2 Capture Switch", ADAU1372_REG_PGA_CTRL(2), 7, 1, 1),
+	SOC_SINGLE("PGA 2 Capture Switch", ADAU1372_REG_PGA_CTRL(2), 7, 1, 0),
-	SOC_SINGLE("PGA 3 Capture Switch", ADAU1372_REG_PGA_CTRL(3), 7, 1, 1),
+	SOC_SINGLE("PGA 3 Capture Switch", ADAU1372_REG_PGA_CTRL(3), 7, 1, 0),
 	SOC_SINGLE_TLV("DAC 0 Playback Volume", ADAU1372_REG_DAC_VOL(0),
 		       0, 0xff, 1, adau1372_digital_tlv),
 	SND_SOC_DAPM_SUPPLY("MICBIAS0", ADAU1372_REG_MICBIAS, 4, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1372_REG_MICBIAS, 5, 0, NULL, 0),
-	SND_SOC_DAPM_PGA("PGA0", ADAU1372_REG_PGA_CTRL(0), 6, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("PGA0", ADAU1372_REG_PGA_CTRL(0), 6, 1, NULL, 0),
-	SND_SOC_DAPM_PGA("PGA1", ADAU1372_REG_PGA_CTRL(1), 6, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("PGA1", ADAU1372_REG_PGA_CTRL(1), 6, 1, NULL, 0),
-	SND_SOC_DAPM_PGA("PGA2", ADAU1372_REG_PGA_CTRL(2), 6, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("PGA2", ADAU1372_REG_PGA_CTRL(2), 6, 1, NULL, 0),
-	SND_SOC_DAPM_PGA("PGA3", ADAU1372_REG_PGA_CTRL(3), 6, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("PGA3", ADAU1372_REG_PGA_CTRL(3), 6, 1, NULL, 0),
 	SND_SOC_DAPM_ADC("ADC0", NULL, ADAU1372_REG_ADC_CTRL2, 0, 0),
 	SND_SOC_DAPM_ADC("ADC1", NULL, ADAU1372_REG_ADC_CTRL2, 1, 0),
 	SND_SOC_DAPM_ADC("ADC2", NULL, ADAU1372_REG_ADC_CTRL3, 0, 0),
 	case 16:
 		sai1 = ADAU1372_SAI1_BCLKRATE;
 		break;
+	case 24:
 	case 32:
 		sai1 = 0;
 		break;
 	case 16:
 		sai1 = ADAU1372_SAI1_BCLK_TDMC;
 		break;
+	case 24:
 	case 32:
 		sai1 = 0;
 		break;
 	.startup = adau1372_startup,
 };
-#define ADAU1372_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |	SNDRV_PCM_FMTBIT_S32_LE)
+#define ADAU1372_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+			  SNDRV_PCM_FMTBIT_S24_LE | \
+			  SNDRV_PCM_FMTBIT_S32_LE)
 static struct snd_soc_dai_driver adau1372_dai_driver = {
 	.name = "adau1372",
 	if (!adau1372)
 		return -ENOMEM;
-	adau1372->clk = devm_clk_get(dev, "mclk");
+	adau1372->mclk = devm_clk_get(dev, "mclk");
-	if (IS_ERR(adau1372->clk))
+	if (IS_ERR(adau1372->mclk))
-		return PTR_ERR(adau1372->clk);
+		return PTR_ERR(adau1372->mclk);
 	adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
 	if (IS_ERR(adau1372->pd_gpio))
 	 * 12.288MHz. Automatically choose a valid configuration from the
 	 * external clock.
 	 */
-	rate = clk_get_rate(adau1372->clk);
+	rate = clk_get_rate(adau1372->mclk);
 	switch (rate) {
 	case 12288000:

sound/usb/card.c+20−9

 	return NULL;
 }
+/* register card if we reach to the last interface or to the specified
+ * one given via option
+ */
+static int try_to_register_card(struct snd_usb_audio *chip, int ifnum)
+{
+	if (check_delayed_register_option(chip) == ifnum ||
+	    chip->last_iface == ifnum ||
+	    usb_interface_claimed(usb_ifnum_to_if(chip->dev, chip->last_iface)))
+		return snd_card_register(chip->card);
+	return 0;
+}
 /*
  * probe the active usb device
  *
 		chip->need_delayed_register = false; /* clear again */
 	}
-	/* register card if we reach to the last interface or to the specified
+	err = try_to_register_card(chip, ifnum);
-	 * one given via option
+	if (err < 0)
-	 */
+		goto __error_no_register;
-	if (check_delayed_register_option(chip) == ifnum ||
-	    usb_interface_claimed(usb_ifnum_to_if(dev, chip->last_iface))) {
-		err = snd_card_register(chip->card);
-		if (err < 0)
-			goto __error;
-	}
 	if (chip->quirk_flags & QUIRK_FLAG_SHARE_MEDIA_DEVICE) {
 		/* don't want to fail when snd_media_device_create() fails */
 	return 0;
  __error:
+	/* in the case of error in secondary interface, still try to register */
+	if (chip)
+		try_to_register_card(chip, ifnum);
+ __error_no_register:
 	if (chip) {
 		/* chip->active is inside the chip->card object,
 		 * decrement before memory is possibly returned.

sound/usb/endpoint.c+2−1

@@ -931,7 +931,8 @@ void snd_usb_endpoint_close(struct snd_usb_audio *chip, · 930 unmodified lines
931	usb_audio_dbg(chip, "Closing EP 0x%x (count %d)\n",	931	usb_audio_dbg(chip, "Closing EP 0x%x (count %d)\n",
932	ep->ep_num, ep->opened);	932	ep->ep_num, ep->opened);
933		933
934	if (!--ep->iface_ref->opened)	934	if (!--ep->iface_ref->opened &&
		935	!(chip->quirk_flags & QUIRK_FLAG_IFACE_SKIP_CLOSE))
935	endpoint_set_interface(chip, ep, false);	936	endpoint_set_interface(chip, ep, false);
936		937
937	if (!--ep->opened) {	938	if (!--ep->opened) {

sound/usb/quirks-table.h+4−0

 		}
 	}
 },
+{
+	/* M-Audio Micro */
+	USB_DEVICE_VENDOR_SPEC(0x0763, 0x201a),
+},
 {
 	USB_DEVICE_VENDOR_SPEC(0x0763, 0x2030),
 	.driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {

sound/usb/quirks.c+6−41

@@ -376,7 +376,8 @@ static int create_auto_midi_quirk(struct snd_usb_audio *chip, · 375 unmodified lines
376		376
377	static int create_autodetect_quirk(struct snd_usb_audio *chip,	377	static int create_autodetect_quirk(struct snd_usb_audio *chip,
378	struct usb_interface *iface,	378	struct usb_interface *iface,
379	struct usb_driver *driver)	379	struct usb_driver *driver,
		380	const struct snd_usb_audio_quirk *quirk)
380	{	381	{
381	int err;	382	int err;
382		383
@@ -386,45 +387,6 @@ static int create_autodetect_quirk(struct snd_usb_audio *chip, · 3 unmodified lines
386	return err;	387	return err;
387	}	388	}
388		389
389	static int create_autodetect_quirks(struct snd_usb_audio *chip,
390	struct usb_interface *iface,
391	struct usb_driver *driver,
392	const struct snd_usb_audio_quirk *quirk)
393	{
394	int probed_ifnum = get_iface_desc(iface->altsetting)->bInterfaceNumber;
395	int ifcount, ifnum, err;
396
397	err = create_autodetect_quirk(chip, iface, driver);
398	if (err < 0)
399	return err;
400
401	/*
402	* ALSA PCM playback/capture devices cannot be registered in two steps,
403	* so we have to claim the other corresponding interface here.
404	*/
405	ifcount = chip->dev->actconfig->desc.bNumInterfaces;
406	for (ifnum = 0; ifnum < ifcount; ifnum++) {
407	if (ifnum == probed_ifnum \|\| quirk->ifnum >= 0)
408	continue;
409	iface = usb_ifnum_to_if(chip->dev, ifnum);
410	if (!iface \|\|
411	usb_interface_claimed(iface) \|\|
412	get_iface_desc(iface->altsetting)->bInterfaceClass !=
413	USB_CLASS_VENDOR_SPEC)
414	continue;
415
416	err = create_autodetect_quirk(chip, iface, driver);
417	if (err >= 0) {
418	err = usb_driver_claim_interface(driver, iface,
419	USB_AUDIO_IFACE_UNUSED);
420	if (err < 0)
421	return err;
422	}
423	}
424
425	return 0;
426	}
427
428	/*	390	/*
429	* Create a stream for an Edirol UA-700/UA-25/UA-4FX interface.	391	* Create a stream for an Edirol UA-700/UA-25/UA-4FX interface.
430	* The only way to detect the sample rate is by looking at wMaxPacketSize.	392	* The only way to detect the sample rate is by looking at wMaxPacketSize.
@@ -554,7 +516,7 @@ int snd_usb_create_quirk(struct snd_usb_audio *chip, · 123 unmodified lines
554	static const quirk_func_t quirk_funcs[] = {	516	static const quirk_func_t quirk_funcs[] = {
555	[QUIRK_IGNORE_INTERFACE] = ignore_interface_quirk,	517	[QUIRK_IGNORE_INTERFACE] = ignore_interface_quirk,
556	[QUIRK_COMPOSITE] = create_composite_quirk,	518	[QUIRK_COMPOSITE] = create_composite_quirk,
557	[QUIRK_AUTODETECT] = create_autodetect_quirks,	519	[QUIRK_AUTODETECT] = create_autodetect_quirk,
558	[QUIRK_MIDI_STANDARD_INTERFACE] = create_any_midi_quirk,	520	[QUIRK_MIDI_STANDARD_INTERFACE] = create_any_midi_quirk,
559	[QUIRK_MIDI_FIXED_ENDPOINT] = create_any_midi_quirk,	521	[QUIRK_MIDI_FIXED_ENDPOINT] = create_any_midi_quirk,
560	[QUIRK_MIDI_YAMAHA] = create_any_midi_quirk,	522	[QUIRK_MIDI_YAMAHA] = create_any_midi_quirk,
@@ -1913,6 +1875,7 @@ u64 snd_usb_interface_dsd_format_quirks(struct snd_usb_audio *chip, · 1352 unmodified lines
1913	/* XMOS based USB DACs */	1875	/* XMOS based USB DACs */
1914	switch (chip->usb_id) {	1876	switch (chip->usb_id) {
1915	case USB_ID(0x1511, 0x0037): /* AURALiC VEGA */	1877	case USB_ID(0x1511, 0x0037): /* AURALiC VEGA */
		1878	case USB_ID(0x21ed, 0xd75a): /* Accuphase DAC-60 option card */
1916	case USB_ID(0x2522, 0x0012): /* LH Labs VI DAC Infinity */	1879	case USB_ID(0x2522, 0x0012): /* LH Labs VI DAC Infinity */
1917	case USB_ID(0x2772, 0x0230): /* Pro-Ject Pre Box S2 Digital */	1880	case USB_ID(0x2772, 0x0230): /* Pro-Ject Pre Box S2 Digital */
1918	if (fp->altsetting == 2)	1881	if (fp->altsetting == 2)
@@ -2185,6 +2148,8 @@ static const struct usb_audio_quirk_flags_table quirk_flags_table[] = { · 266 unmodified lines
2185	QUIRK_FLAG_GENERIC_IMPLICIT_FB),	2148	QUIRK_FLAG_GENERIC_IMPLICIT_FB),
2186	DEVICE_FLG(0x2b53, 0x0031, /* Fiero SC-01 (firmware v1.1.0) */	2149	DEVICE_FLG(0x2b53, 0x0031, /* Fiero SC-01 (firmware v1.1.0) */
2187	QUIRK_FLAG_GENERIC_IMPLICIT_FB),	2150	QUIRK_FLAG_GENERIC_IMPLICIT_FB),
		2151	DEVICE_FLG(0x0525, 0xa4ad, /* Hamedal C20 usb camero */
		2152	QUIRK_FLAG_IFACE_SKIP_CLOSE),
2188		2153
2189	/* Vendor matches */	2154	/* Vendor matches */
2190	VENDOR_FLG(0x045e, /* MS Lifecam */	2155	VENDOR_FLG(0x045e, /* MS Lifecam */

sound/usb/usbaudio.h+3−0

  *  Apply the generic implicit feedback sync mode (same as implicit_fb=1 option)
  * QUIRK_FLAG_SKIP_IMPLICIT_FB
  *  Don't apply implicit feedback sync mode
+ * QUIRK_FLAG_IFACE_SKIP_CLOSE
+ *  Don't closed interface during setting sample rate
  */
 #define QUIRK_FLAG_GET_SAMPLE_RATE	(1U << 0)
 #define QUIRK_FLAG_SET_IFACE_FIRST	(1U << 16)
 #define QUIRK_FLAG_GENERIC_IMPLICIT_FB	(1U << 17)
 #define QUIRK_FLAG_SKIP_IMPLICIT_FB	(1U << 18)
+#define QUIRK_FLAG_IFACE_SKIP_CLOSE	(1U << 19)
 #endif /* __USBAUDIO_H */

tools/bpf/bpftool/common.c+3−0

@@ -300,6 +300,9 @@ int do_pin_any(int argc, char *argv, int (get_fd)(int , char **)) · 299 unmodified lines
300	int err;	300	int err;
301	int fd;	301	int fd;
302		302
		303	if (!REQ_ARGS(3))
		304	return -EINVAL;
		305
303	fd = get_fd(&argc, &argv);	306	fd = get_fd(&argc, &argv);
304	if (fd < 0)	307	if (fd < 0)
305	return fd;	308	return fd;

tools/include/uapi/linux/in.h+1−0

@@ -20,6 +20,7 @@ · 19 unmodified lines
20	#define _UAPI_LINUX_IN_H	20	#define _UAPI_LINUX_IN_H
21		21
22	#include <linux/types.h>	22	#include <linux/types.h>
		23	#include <linux/stddef.h>
23	#include <linux/libc-compat.h>	24	#include <linux/libc-compat.h>
24	#include <linux/socket.h>	25	#include <linux/socket.h>
25		26

tools/include/uapi/linux/stddef.h+47−0

@@ -0,0 +1,47 @@
	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
	2	#ifndef _LINUX_STDDEF_H
	3	#define _LINUX_STDDEF_H
	4
	5
	6
	7	#ifndef __always_inline
	8	#define __always_inline __inline__
	9	#endif
	10
	11	/**
	12	* __struct_group() - Create a mirrored named and anonyomous struct
	13	*
	14	* @TAG: The tag name for the named sub-struct (usually empty)
	15	* @NAME: The identifier name of the mirrored sub-struct
	16	* @ATTRS: Any struct attributes (usually empty)
	17	* @MEMBERS: The member declarations for the mirrored structs
	18	*
	19	* Used to create an anonymous union of two structs with identical layout
	20	* and size: one anonymous and one named. The former's members can be used
	21	* normally without sub-struct naming, and the latter can be used to
	22	* reason about the start, end, and size of the group of struct members.
	23	* The named struct can also be explicitly tagged for layer reuse, as well
	24	* as both having struct attributes appended.
	25	*/
	26	#define __struct_group(TAG, NAME, ATTRS, MEMBERS...) \
	27	union { \
	28	struct { MEMBERS } ATTRS; \
	29	struct TAG { MEMBERS } ATTRS NAME; \
	30	}
	31
	32	/**
	33	* __DECLARE_FLEX_ARRAY() - Declare a flexible array usable in a union
	34	*
	35	* @TYPE: The type of each flexible array element
	36	* @NAME: The name of the flexible array member
	37	*
	38	* In order to have a flexible array member in a union or alone in a
	39	* struct, it needs to be wrapped in an anonymous struct with at least 1
	40	* named member, but that member can be empty.
	41	*/
	42	#define __DECLARE_FLEX_ARRAY(TYPE, NAME) \
	43	struct { \
	44	struct { } __empty_ ## NAME; \
	45	TYPE NAME[]; \
	46	}
	47	#endif

tools/kvm/kvm_stat/kvm_stat+83−15

     'EXCEPTION_NMI':        0,
     'EXTERNAL_INTERRUPT':   1,
     'TRIPLE_FAULT':         2,
-    'PENDING_INTERRUPT':    7,
+    'INIT_SIGNAL':          3,
+    'SIPI_SIGNAL':          4,
+    'INTERRUPT_WINDOW':     7,
     'NMI_WINDOW':           8,
     'TASK_SWITCH':          9,
     'CPUID':                10,
     'HLT':                  12,
+    'INVD':                 13,
     'INVLPG':               14,
     'RDPMC':                15,
     'RDTSC':                16,
     'MSR_READ':             31,
     'MSR_WRITE':            32,
     'INVALID_STATE':        33,
+    'MSR_LOAD_FAIL':        34,
     'MWAIT_INSTRUCTION':    36,
+    'MONITOR_TRAP_FLAG':    37,
     'MONITOR_INSTRUCTION':  39,
     'PAUSE_INSTRUCTION':    40,
     'MCE_DURING_VMENTRY':   41,
     'TPR_BELOW_THRESHOLD':  43,
     'APIC_ACCESS':          44,
+    'EOI_INDUCED':          45,
+    'GDTR_IDTR':            46,
+    'LDTR_TR':              47,
     'EPT_VIOLATION':        48,
     'EPT_MISCONFIG':        49,
+    'INVEPT':               50,
+    'RDTSCP':               51,
+    'PREEMPTION_TIMER':     52,
+    'INVVPID':              53,
     'WBINVD':               54,
     'XSETBV':               55,
     'APIC_WRITE':           56,
+    'RDRAND':               57,
     'INVPCID':              58,
+    'VMFUNC':               59,
+    'ENCLS':                60,
+    'RDSEED':               61,
+    'PML_FULL':             62,
+    'XSAVES':               63,
+    'XRSTORS':              64,
+    'UMWAIT':               67,
+    'TPAUSE':               68,
+    'BUS_LOCK':             74,
+    'NOTIFY':               75,
 }
 SVM_EXIT_REASONS = {
     'READ_CR0':       0x000,
+    'READ_CR2':       0x002,
     'READ_CR3':       0x003,
     'READ_CR4':       0x004,
     'READ_CR8':       0x008,
     'WRITE_CR0':      0x010,
+    'WRITE_CR2':      0x012,
     'WRITE_CR3':      0x013,
     'WRITE_CR4':      0x014,
     'WRITE_CR8':      0x018,
     'WRITE_DR6':      0x036,
     'WRITE_DR7':      0x037,
     'EXCP_BASE':      0x040,
+    'LAST_EXCP':      0x05f,
     'INTR':           0x060,
     'NMI':            0x061,
     'SMI':            0x062,
     'MWAIT':          0x08b,
     'MWAIT_COND':     0x08c,
     'XSETBV':         0x08d,
+    'RDPRU':          0x08e,
+    'EFER_WRITE_TRAP':           0x08f,
+    'CR0_WRITE_TRAP':            0x090,
+    'CR1_WRITE_TRAP':            0x091,
+    'CR2_WRITE_TRAP':            0x092,
+    'CR3_WRITE_TRAP':            0x093,
+    'CR4_WRITE_TRAP':            0x094,
+    'CR5_WRITE_TRAP':            0x095,
+    'CR6_WRITE_TRAP':            0x096,
+    'CR7_WRITE_TRAP':            0x097,
+    'CR8_WRITE_TRAP':            0x098,
+    'CR9_WRITE_TRAP':            0x099,
+    'CR10_WRITE_TRAP':           0x09a,
+    'CR11_WRITE_TRAP':           0x09b,
+    'CR12_WRITE_TRAP':           0x09c,
+    'CR13_WRITE_TRAP':           0x09d,
+    'CR14_WRITE_TRAP':           0x09e,
+    'CR15_WRITE_TRAP':           0x09f,
+    'INVPCID':        0x0a2,
     'NPF':            0x400,
+    'AVIC_INCOMPLETE_IPI':       0x401,
+    'AVIC_UNACCELERATED_ACCESS': 0x402,
+    'VMGEXIT':        0x403,
 }
-# EC definition of HSR (from arch/arm64/include/asm/kvm_arm.h)
+# EC definition of HSR (from arch/arm64/include/asm/esr.h)
 AARCH64_EXIT_REASONS = {
     'UNKNOWN':      0x00,
-    'WFI':          0x01,
+    'WFx':          0x01,
     'CP15_32':      0x03,
     'CP15_64':      0x04,
     'CP14_MR':      0x05,
     'CP14_LS':      0x06,
     'FP_ASIMD':     0x07,
     'CP10_ID':      0x08,
+    'PAC':          0x09,
     'CP14_64':      0x0C,
-    'ILL_ISS':      0x0E,
+    'BTI':          0x0D,
+    'ILL':          0x0E,
     'SVC32':        0x11,
     'HVC32':        0x12,
     'SMC32':        0x13,
     'HVC64':        0x16,
     'SMC64':        0x17,
     'SYS64':        0x18,
-    'IABT':         0x20,
+    'SVE':          0x19,
-    'IABT_HYP':     0x21,
+    'ERET':         0x1A,
+    'FPAC':         0x1C,
+    'SME':          0x1D,
+    'IMP_DEF':      0x1F,
+    'IABT_LOW':     0x20,
+    'IABT_CUR':     0x21,
     'PC_ALIGN':     0x22,
-    'DABT':         0x24,
+    'DABT_LOW':     0x24,
-    'DABT_HYP':     0x25,
+    'DABT_CUR':     0x25,
     'SP_ALIGN':     0x26,
     'FP_EXC32':     0x28,
     'FP_EXC64':     0x2C,
     'SERROR':       0x2F,
-    'BREAKPT':      0x30,
+    'BREAKPT_LOW':  0x30,
-    'BREAKPT_HYP':  0x31,
+    'BREAKPT_CUR':  0x31,
-    'SOFTSTP':      0x32,
+    'SOFTSTP_LOW':  0x32,
-    'SOFTSTP_HYP':  0x33,
+    'SOFTSTP_CUR':  0x33,
-    'WATCHPT':      0x34,
+    'WATCHPT_LOW':  0x34,
-    'WATCHPT_HYP':  0x35,
+    'WATCHPT_CUR':  0x35,
     'BKPT32':       0x38,
     'VECTOR32':     0x3A,
     'BRK64':        0x3C,
     'S390_TSCH':        22,
     'EPR':              23,
     'SYSTEM_EVENT':     24,
+    'S390_STSI':        25,
+    'IOAPIC_EOI':       26,
+    'HYPERV':           27,
+    'ARM_NISV':         28,
+    'X86_RDMSR':        29,
+    'X86_WRMSR':        30,
+    'DIRTY_RING_FULL':  31,
+    'AP_RESET_HOLD':    32,
+    'X86_BUS_LOCK':     33,
+    'XEN':              34,
+    'RISCV_SBI':        35,
+    'RISCV_CSR':        36,
+    'NOTIFY':           37,
 }
 IOCTL_NUMBERS = {
     debugfs = ''
     for line in open('/proc/mounts'):
-        if line.split(' ')[0] == 'debugfs':
+        if line.split(' ')[2] == 'debugfs':
             debugfs = line.split(' ')[1]
             break
     if debugfs == '':

tools/perf/.gitignore+1−0

@@ -4,6 +4,7 @@ PERF-GUI-VARS · 3 unmodified lines
4	PERF-VERSION-FILE	4	PERF-VERSION-FILE
5	FEATURE-DUMP	5	FEATURE-DUMP
6	perf	6	perf
		7	!include/perf/
7	perf-read-vdso32	8	perf-read-vdso32
8	perf-read-vdsox32	9	perf-read-vdsox32
9	perf-help	10	perf-help

tools/perf/tests/shell/test_brstack.sh+4−1

@@ -13,7 +13,10 @@ fi · 12 unmodified lines
13		13
14	# skip the test if the hardware doesn't support branch stack sampling	14	# skip the test if the hardware doesn't support branch stack sampling
15	# and if the architecture doesn't support filter types: any,save_type,u	15	# and if the architecture doesn't support filter types: any,save_type,u
16	perf record -b -o- -B --branch-filter any,save_type,u true > /dev/null 2>&1 \|\| exit 2	16	if ! perf record -o- --no-buildid --branch-filter any,save_type,u -- true > /dev/null 2>&1 ; then
		17	echo "skip: system doesn't support filter types: any,save_type,u"
		18	exit 2
		19	fi
17		20
18	TMPDIR=$(mktemp -d /tmp/__perf_test.program.XXXXX)	21	TMPDIR=$(mktemp -d /tmp/__perf_test.program.XXXXX)
19		22

tools/perf/util/parse-branch-options.c+3−1

 	/*
 	 * cannot set it twice, -b + --branch-filter for instance
 	 */
-	if (*mode)
+	if (*mode) {
+		pr_err("Error: Can't use --branch-any (-b) with --branch-filter (-j).\n");
 		return -1;
+	}
 	return parse_branch_str(str, mode);
 }

tools/perf/util/stat-display.c+4−2

 	fputc('\n', os->fh);
 	if (os->prefix)
-		fprintf(os->fh, "%s%s", os->prefix, config->csv_sep);
+		fprintf(os->fh, "%s", os->prefix);
 	aggr_printout(config, os->evsel, os->id, os->nr);
 	for (i = 0; i < os->nfields; i++)
 		fputs(config->csv_sep, os->fh);
 			[AGGR_CORE] = 2,
 			[AGGR_THREAD] = 1,
 			[AGGR_UNSET] = 0,
-			[AGGR_NODE] = 0,
+			[AGGR_NODE] = 1,
 		};
 		pm = config->metric_only ? print_metric_only_csv : print_metric_csv;
 	[AGGR_SOCKET] = 12,
 	[AGGR_NONE] = 6,
 	[AGGR_THREAD] = 24,
+	[AGGR_NODE] = 6,
 	[AGGR_GLOBAL] = 0,
 };
 	[AGGR_SOCKET] 	= 	"socket,cpus",
 	[AGGR_NONE] 	= 	"cpu,",
 	[AGGR_THREAD] 	= 	"comm-pid,",
+	[AGGR_NODE] 	= 	"node,",
 	[AGGR_GLOBAL] 	=	""
 };

tools/testing/radix-tree/.gitignore+1−0

@@ -1,4 +1,5 @@
1	# SPDX-License-Identifier: GPL-2.0-only	1	# SPDX-License-Identifier: GPL-2.0-only
		2	generated/bit-length.h
2	generated/map-shift.h	3	generated/map-shift.h
3	idr.c	4	idr.c
4	idr-test	5	idr-test

tools/testing/radix-tree/Makefile+16−3

 ifeq ($(BUILD), 32)
 	CFLAGS += -m32
 	LDFLAGS += -m32
+LONG_BIT := 32
 endif
-targets: generated/map-shift.h $(TARGETS)
+ifndef LONG_BIT
+LONG_BIT := $(shell getconf LONG_BIT)
+endif
+targets: generated/map-shift.h generated/bit-length.h $(TARGETS)
 main:	$(OFILES)
 multiorder: multiorder.o $(CORE_OFILES)
 clean:
-	$(RM) $(TARGETS) *.o radix-tree.c idr.c generated/map-shift.h
+	$(RM) $(TARGETS) *.o radix-tree.c idr.c generated/map-shift.h generated/bit-length.h
 vpath %.c ../../lib
-$(OFILES): Makefile *.h */*.h generated/map-shift.h \
+$(OFILES): Makefile *.h */*.h generated/map-shift.h generated/bit-length.h \
 	../../include/linux/*.h \
 	../../include/asm/*.h \
 	../../../include/linux/xarray.h \
 		echo "#define XA_CHUNK_SHIFT $(SHIFT)" >		\
 				generated/map-shift.h;			\
 	fi
+generated/bit-length.h: FORCE
+	@if ! grep -qws CONFIG_$(LONG_BIT)BIT generated/bit-length.h; then   \
+		echo "Generating $@";                                        \
+		echo "#define CONFIG_$(LONG_BIT)BIT 1" > $@;                 \
+	fi
+FORCE: ;

tools/testing/radix-tree/generated/autoconf.h+1−1

@@ -1,2 +1,2 @@
		1	#include "bit-length.h"
1	#define CONFIG_XARRAY_MULTI 1	2	#define CONFIG_XARRAY_MULTI 1
2	#define CONFIG_64BIT 1

tools/testing/radix-tree/linux.c+4−0

 	pthread_mutex_unlock(&cachep->lock);
 }
+void kmem_cache_shrink(struct kmem_cache *cachep)
+{
+}
 int kmem_cache_alloc_bulk(struct kmem_cache *cachep, gfp_t gfp, size_t size,
 			  void **p)
 {

tools/testing/radix-tree/maple.c+35770−0

@@ -2,11 +2,17 @@ · 1 unmodified line
2	/*	2	/*
3	* maple_tree.c: Userspace shim for maple tree test-suite	3	* maple_tree.c: Userspace shim for maple tree test-suite
4	* Copyright (c) 2018 Liam R. Howlett <Liam.Howlett@Oracle.com>	4	* Copyright (c) 2018 Liam R. Howlett <Liam.Howlett@Oracle.com>
		5	*
		6	* Any tests that require internal knowledge of the tree or threads and other
		7	* difficult to handle in kernel tests.
5	*/	8	*/
6		9
7	#define CONFIG_DEBUG_MAPLE_TREE	10	#define CONFIG_DEBUG_MAPLE_TREE
8	#define CONFIG_MAPLE_SEARCH	11	#define CONFIG_MAPLE_SEARCH
		12	#define MAPLE_32BIT (MAPLE_NODE_SLOTS > 31)
9	#include "test.h"	13	#include "test.h"
		14	#include <stdlib.h>
		15	#include <time.h>
10		16
11	#define module_init(x)	17	#define module_init(x)
12	#define module_exit(x)	18	#define module_exit(x)
@@ -18,6 +24,35717 @@ · 5 unmodified lines
18	#undef CONFIG_DEBUG_MAPLE_TREE	24	#undef CONFIG_DEBUG_MAPLE_TREE
19	#include "../../../lib/test_maple_tree.c"	25	#include "../../../lib/test_maple_tree.c"
20		26
		27	#define RCU_RANGE_COUNT 1000
		28	#define RCU_MT_BUG_ON(test, y) {if (y) { test->stop = true; } MT_BUG_ON(test->mt, y); }
		29
		30	struct rcu_test_struct2 {
		31	struct maple_tree *mt;
		32
		33	bool start;
		34	bool stop;
		35	unsigned int thread_count;
		36
		37	unsigned int seen_toggle;
		38	unsigned int seen_added;
		39	unsigned int seen_modified;
		40	unsigned int seen_deleted;
		41	int pause;
		42
		43	unsigned long index[RCU_RANGE_COUNT];
		44	unsigned long last[RCU_RANGE_COUNT];
		45	};
		46
		47	struct rcu_reader_struct {
		48	unsigned int id;
		49	int mod;
		50	int del;
		51	int flip;
		52	int add;
		53	int next;
		54	struct rcu_test_struct2 *test;
		55	};
		56
		57	/*
		58	* check_new_node() - Check the creation of new nodes and error path
		59	* verification.
		60	*/
		61	static noinline void check_new_node(struct maple_tree *mt)
		62	{
		63
		64	struct maple_node mn, mn2, *mn3;
		65	struct maple_alloc *smn;
		66	struct maple_node *nodes[100];
		67	int i, j, total;
		68
		69	MA_STATE(mas, mt, 0, 0);
		70
		71	/* Try allocating 3 nodes */
		72	mtree_lock(mt);
		73	mt_set_non_kernel(0);
		74	/* request 3 nodes to be allocated. */
		75	mas_node_count(&mas, 3);
		76	/* Allocation request of 3. */
		77	MT_BUG_ON(mt, mas_alloc_req(&mas) != 3);
		78	/* Allocate failed. */
		79	MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
		80	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
		81
		82	MT_BUG_ON(mt, mas_allocated(&mas) != 3);
		83	mn = mas_pop_node(&mas);
		84	MT_BUG_ON(mt, not_empty(mn));
		85	MT_BUG_ON(mt, mn == NULL);
		86	MT_BUG_ON(mt, mas.alloc == NULL);
		87	MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
		88	mas_push_node(&mas, mn);
		89	mas_nomem(&mas, GFP_KERNEL); /* free */
		90	mtree_unlock(mt);
		91
		92
		93	/* Try allocating 1 node, then 2 more */
		94	mtree_lock(mt);
		95	/* Set allocation request to 1. */
		96	mas_set_alloc_req(&mas, 1);
		97	/* Check Allocation request of 1. */
		98	MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
		99	mas_set_err(&mas, -ENOMEM);
		100	/* Validate allocation request. */
		101	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
		102	/* Eat the requested node. */
		103	mn = mas_pop_node(&mas);
		104	MT_BUG_ON(mt, not_empty(mn));
		105	MT_BUG_ON(mt, mn == NULL);
		106	MT_BUG_ON(mt, mn->slot[0] != NULL);
		107	MT_BUG_ON(mt, mn->slot[1] != NULL);
		108	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
		109
		110	ma_free_rcu(mn);
		111	mas.node = MAS_START;
		112	mas_nomem(&mas, GFP_KERNEL);
		113	/* Allocate 3 nodes, will fail. */
		114	mas_node_count(&mas, 3);
		115	/* Drop the lock and allocate 3 nodes. */
		116	mas_nomem(&mas, GFP_KERNEL);
		117	/* Ensure 3 are allocated. */
		118	MT_BUG_ON(mt, mas_allocated(&mas) != 3);
		119	/* Allocation request of 0. */
		120	MT_BUG_ON(mt, mas_alloc_req(&mas) != 0);
		121
		122	MT_BUG_ON(mt, mas.alloc == NULL);
		123	MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
		124	MT_BUG_ON(mt, mas.alloc->slot[1] == NULL);
		125	/* Ensure we counted 3. */
		126	MT_BUG_ON(mt, mas_allocated(&mas) != 3);
		127	/* Free. */
		128	mas_nomem(&mas, GFP_KERNEL);
		129
		130	/* Set allocation request to 1. */
		131	mas_set_alloc_req(&mas, 1);
		132	MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
		133	mas_set_err(&mas, -ENOMEM);
		134	/* Validate allocation request. */
		135	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
		136	MT_BUG_ON(mt, mas_allocated(&mas) != 1);
		137	/* Check the node is only one node. */
		138	mn = mas_pop_node(&mas);
		139	MT_BUG_ON(mt, not_empty(mn));
		140	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
		141	MT_BUG_ON(mt, mn == NULL);
		142	MT_BUG_ON(mt, mn->slot[0] != NULL);
		143	MT_BUG_ON(mt, mn->slot[1] != NULL);
		144	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
		145	mas_push_node(&mas, mn);
		146	MT_BUG_ON(mt, mas_allocated(&mas) != 1);
		147	MT_BUG_ON(mt, mas.alloc->node_count);
		148
		149	mas_set_alloc_req(&mas, 2); /* request 2 more. */
		150	MT_BUG_ON(mt, mas_alloc_req(&mas) != 2);
		151	mas_set_err(&mas, -ENOMEM);
		152	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
		153	MT_BUG_ON(mt, mas_allocated(&mas) != 3);
		154	MT_BUG_ON(mt, mas.alloc == NULL);
		155	MT_BUG_ON(mt, mas.alloc->slot[0] == NULL);
		156	MT_BUG_ON(mt, mas.alloc->slot[1] == NULL);
		157	for (i = 2; i >= 0; i--) {
		158	mn = mas_pop_node(&mas);
		159	MT_BUG_ON(mt, mas_allocated(&mas) != i);
		160	MT_BUG_ON(mt, !mn);
		161	MT_BUG_ON(mt, not_empty(mn));
		162	ma_free_rcu(mn);
		163	}
		164
		165	total = 64;
		166	mas_set_alloc_req(&mas, total); /* request 2 more. */
		167	MT_BUG_ON(mt, mas_alloc_req(&mas) != total);
		168	mas_set_err(&mas, -ENOMEM);
		169	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
		170	for (i = total; i > 0; i--) {
		171	unsigned int e = 0; /* expected node_count */
		172
		173	if (!MAPLE_32BIT) {
		174	if (i >= 35)
		175	e = i - 35;
		176	else if (i >= 5)
		177	e = i - 5;
		178	else if (i >= 2)
		179	e = i - 2;
		180	} else {
		181	if (i >= 4)
		182	e = i - 4;
		183	else if (i == 3)
		184	e = i - 2;
		185	else
		186	e = 0;
		187	}
		188
		189	MT_BUG_ON(mt, mas.alloc->node_count != e);
		190	mn = mas_pop_node(&mas);
		191	MT_BUG_ON(mt, not_empty(mn));
		192	MT_BUG_ON(mt, mas_allocated(&mas) != i - 1);
		193	MT_BUG_ON(mt, !mn);
		194	ma_free_rcu(mn);
		195	}
		196
		197	total = 100;
		198	for (i = 1; i < total; i++) {
		199	mas_set_alloc_req(&mas, i);
		200	mas_set_err(&mas, -ENOMEM);
		201	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
		202	for (j = i; j > 0; j--) {
		203	mn = mas_pop_node(&mas);
		204	MT_BUG_ON(mt, mas_allocated(&mas) != j - 1);
		205	MT_BUG_ON(mt, !mn);
		206	MT_BUG_ON(mt, not_empty(mn));
		207	mas_push_node(&mas, mn);
		208	MT_BUG_ON(mt, mas_allocated(&mas) != j);
		209	mn = mas_pop_node(&mas);
		210	MT_BUG_ON(mt, not_empty(mn));
		211	MT_BUG_ON(mt, mas_allocated(&mas) != j - 1);
		212	ma_free_rcu(mn);
		213	}
		214	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
		215
		216	mas_set_alloc_req(&mas, i);
		217	mas_set_err(&mas, -ENOMEM);
		218	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
		219	for (j = 0; j <= i/2; j++) {
		220	MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
		221	nodes[j] = mas_pop_node(&mas);
		222	MT_BUG_ON(mt, mas_allocated(&mas) != i - j - 1);
		223	}
		224
		225	while (j) {
		226	j--;
		227	mas_push_node(&mas, nodes[j]);
		228	MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
		229	}
		230	MT_BUG_ON(mt, mas_allocated(&mas) != i);
		231	for (j = 0; j <= i/2; j++) {
		232	MT_BUG_ON(mt, mas_allocated(&mas) != i - j);
		233	mn = mas_pop_node(&mas);
		234	MT_BUG_ON(mt, not_empty(mn));
		235	ma_free_rcu(mn);
		236	MT_BUG_ON(mt, mas_allocated(&mas) != i - j - 1);
		237	}
		238	MT_BUG_ON(mt, mas_nomem(&mas, GFP_KERNEL));
		239
		240	}
		241
		242	/* Set allocation request. */
		243	total = 500;
		244	mas_node_count(&mas, total);
		245	/* Drop the lock and allocate the nodes. */
		246	mas_nomem(&mas, GFP_KERNEL);
		247	MT_BUG_ON(mt, !mas.alloc);
		248	i = 1;
		249	smn = mas.alloc;
		250	while (i < total) {
		251	for (j = 0; j < MAPLE_ALLOC_SLOTS; j++) {
		252	i++;
		253	MT_BUG_ON(mt, !smn->slot[j]);
		254	if (i == total)
		255	break;
		256	}
		257	smn = smn->slot[0]; /* next. */
		258	}
		259	MT_BUG_ON(mt, mas_allocated(&mas) != total);
		260	mas_nomem(&mas, GFP_KERNEL); /* Free. */
		261
		262	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
		263	for (i = 1; i < 128; i++) {
		264	mas_node_count(&mas, i); /* Request */
		265	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		266	MT_BUG_ON(mt, mas_allocated(&mas) != i); /* check request filled */
		267	for (j = i; j > 0; j--) { /Free the requests /
		268	mn = mas_pop_node(&mas); /* get the next node. */
		269	MT_BUG_ON(mt, mn == NULL);
		270	MT_BUG_ON(mt, not_empty(mn));
		271	ma_free_rcu(mn);
		272	}
		273	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
		274	}
		275
		276	for (i = 1; i < MAPLE_NODE_MASK + 1; i++) {
		277	MA_STATE(mas2, mt, 0, 0);
		278	mas_node_count(&mas, i); /* Request */
		279	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		280	MT_BUG_ON(mt, mas_allocated(&mas) != i); /* check request filled */
		281	for (j = 1; j <= i; j++) { /* Move the allocations to mas2 */
		282	mn = mas_pop_node(&mas); /* get the next node. */
		283	MT_BUG_ON(mt, mn == NULL);
		284	MT_BUG_ON(mt, not_empty(mn));
		285	mas_push_node(&mas2, mn);
		286	MT_BUG_ON(mt, mas_allocated(&mas2) != j);
		287	}
		288	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
		289	MT_BUG_ON(mt, mas_allocated(&mas2) != i);
		290
		291	for (j = i; j > 0; j--) { /Free the requests /
		292	MT_BUG_ON(mt, mas_allocated(&mas2) != j);
		293	mn = mas_pop_node(&mas2); /* get the next node. */
		294	MT_BUG_ON(mt, mn == NULL);
		295	MT_BUG_ON(mt, not_empty(mn));
		296	ma_free_rcu(mn);
		297	}
		298	MT_BUG_ON(mt, mas_allocated(&mas2) != 0);
		299	}
		300
		301
		302	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
		303	mas_node_count(&mas, MAPLE_ALLOC_SLOTS + 1); /* Request */
		304	MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
		305	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
		306	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
		307	MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
		308
		309	mn = mas_pop_node(&mas); /* get the next node. */
		310	MT_BUG_ON(mt, mn == NULL);
		311	MT_BUG_ON(mt, not_empty(mn));
		312	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS);
		313	MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 2);
		314
		315	mas_push_node(&mas, mn);
		316	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
		317	MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
		318
		319	/* Check the limit of pop/push/pop */
		320	mas_node_count(&mas, MAPLE_ALLOC_SLOTS + 2); /* Request */
		321	MT_BUG_ON(mt, mas_alloc_req(&mas) != 1);
		322	MT_BUG_ON(mt, mas.node != MA_ERROR(-ENOMEM));
		323	MT_BUG_ON(mt, !mas_nomem(&mas, GFP_KERNEL));
		324	MT_BUG_ON(mt, mas_alloc_req(&mas));
		325	MT_BUG_ON(mt, mas.alloc->node_count);
		326	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 2);
		327	mn = mas_pop_node(&mas);
		328	MT_BUG_ON(mt, not_empty(mn));
		329	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 1);
		330	MT_BUG_ON(mt, mas.alloc->node_count != MAPLE_ALLOC_SLOTS - 1);
		331	mas_push_node(&mas, mn);
		332	MT_BUG_ON(mt, mas.alloc->node_count);
		333	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS + 2);
		334	mn = mas_pop_node(&mas);
		335	MT_BUG_ON(mt, not_empty(mn));
		336	ma_free_rcu(mn);
		337	for (i = 1; i <= MAPLE_ALLOC_SLOTS + 1; i++) {
		338	mn = mas_pop_node(&mas);
		339	MT_BUG_ON(mt, not_empty(mn));
		340	ma_free_rcu(mn);
		341	}
		342	MT_BUG_ON(mt, mas_allocated(&mas) != 0);
		343
		344
		345	for (i = 3; i < MAPLE_NODE_MASK * 3; i++) {
		346	mas.node = MA_ERROR(-ENOMEM);
		347	mas_node_count(&mas, i); /* Request */
		348	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		349	mn = mas_pop_node(&mas); /* get the next node. */
		350	mas_push_node(&mas, mn); /* put it back */
		351	mas_destroy(&mas);
		352
		353	mas.node = MA_ERROR(-ENOMEM);
		354	mas_node_count(&mas, i); /* Request */
		355	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		356	mn = mas_pop_node(&mas); /* get the next node. */
		357	mn2 = mas_pop_node(&mas); /* get the next node. */
		358	mas_push_node(&mas, mn); /* put them back */
		359	mas_push_node(&mas, mn2);
		360	mas_destroy(&mas);
		361
		362	mas.node = MA_ERROR(-ENOMEM);
		363	mas_node_count(&mas, i); /* Request */
		364	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		365	mn = mas_pop_node(&mas); /* get the next node. */
		366	mn2 = mas_pop_node(&mas); /* get the next node. */
		367	mn3 = mas_pop_node(&mas); /* get the next node. */
		368	mas_push_node(&mas, mn); /* put them back */
		369	mas_push_node(&mas, mn2);
		370	mas_push_node(&mas, mn3);
		371	mas_destroy(&mas);
		372
		373	mas.node = MA_ERROR(-ENOMEM);
		374	mas_node_count(&mas, i); /* Request */
		375	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		376	mn = mas_pop_node(&mas); /* get the next node. */
		377	ma_free_rcu(mn);
		378	mas_destroy(&mas);
		379
		380	mas.node = MA_ERROR(-ENOMEM);
		381	mas_node_count(&mas, i); /* Request */
		382	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		383	mn = mas_pop_node(&mas); /* get the next node. */
		384	ma_free_rcu(mn);
		385	mn = mas_pop_node(&mas); /* get the next node. */
		386	ma_free_rcu(mn);
		387	mn = mas_pop_node(&mas); /* get the next node. */
		388	ma_free_rcu(mn);
		389	mas_destroy(&mas);
		390	}
		391
		392	mas.node = MA_ERROR(-ENOMEM);
		393	mas_node_count(&mas, 5); /* Request */
		394	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		395	MT_BUG_ON(mt, mas_allocated(&mas) != 5);
		396	mas.node = MA_ERROR(-ENOMEM);
		397	mas_node_count(&mas, 10); /* Request */
		398	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		399	mas.node = MAS_START;
		400	MT_BUG_ON(mt, mas_allocated(&mas) != 10);
		401	mas_destroy(&mas);
		402
		403	mas.node = MA_ERROR(-ENOMEM);
		404	mas_node_count(&mas, MAPLE_ALLOC_SLOTS - 1); /* Request */
		405	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		406	MT_BUG_ON(mt, mas_allocated(&mas) != MAPLE_ALLOC_SLOTS - 1);
		407	mas.node = MA_ERROR(-ENOMEM);
		408	mas_node_count(&mas, 10 + MAPLE_ALLOC_SLOTS - 1); /* Request */
		409	mas_nomem(&mas, GFP_KERNEL); /* Fill request */
		410	mas.node = MAS_START;
		411	MT_BUG_ON(mt, mas_allocated(&mas) != 10 + MAPLE_ALLOC_SLOTS - 1);
		412	mas_destroy(&mas);
		413
		414	mtree_unlock(mt);
		415	}
		416
		417	/*
		418	* Check erasing including RCU.
		419	*/
		420	static noinline void check_erase(struct maple_tree *mt, unsigned long index,
		421	void *ptr)
		422	{
		423	MT_BUG_ON(mt, mtree_test_erase(mt, index) != ptr);
		424	}
		425
		426	#define erase_check_load(mt, i) check_load(mt, set[i], entry[i%2])
		427	#define erase_check_insert(mt, i) check_insert(mt, set[i], entry[i%2])
		428	#define erase_check_erase(mt, i) check_erase(mt, set[i], entry[i%2])
		429
		430	static noinline void check_erase_testset(struct maple_tree *mt)
		431	{
		432	unsigned long set[] = { 5015, 5014, 5017, 25, 1000,
		433	1001, 1002, 1003, 1005, 0,
		434	6003, 6002, 6008, 6012, 6015,
		435	7003, 7002, 7008, 7012, 7015,
		436	8003, 8002, 8008, 8012, 8015,
		437	9003, 9002, 9008, 9012, 9015,
		438	10003, 10002, 10008, 10012, 10015,
		439	11003, 11002, 11008, 11012, 11015,
		440	12003, 12002, 12008, 12012, 12015,
		441	13003, 13002, 13008, 13012, 13015,
		442	14003, 14002, 14008, 14012, 14015,
		443	15003, 15002, 15008, 15012, 15015,
		444	};
		445
		446
		447	void *ptr = &set;
		448	void *entry[2] = { ptr, mt };
		449	void *root_node;
		450
		451
		452	rcu_register_thread();
		453	mt_set_in_rcu(mt);
		454	for (int i = 0; i < 4; i++)
		455	erase_check_insert(mt, i);
		456	for (int i = 0; i < 4; i++)
		457	erase_check_load(mt, i);
		458
		459	mt_set_non_kernel(2);
		460	erase_check_erase(mt, 1);
		461	erase_check_load(mt, 0);
		462	check_load(mt, set[1], NULL);
		463	for (int i = 2; i < 4; i++)
		464	erase_check_load(mt, i);
		465
		466
		467	erase_check_erase(mt, 2);
		468	erase_check_load(mt, 0);
		469	check_load(mt, set[1], NULL);
		470	check_load(mt, set[2], NULL);
		471
		472	erase_check_insert(mt, 1);
		473	erase_check_insert(mt, 2);
		474
		475	for (int i = 0; i < 4; i++)
		476	erase_check_load(mt, i);
		477
		478	/* Check erase and load without an allocation. */
		479	erase_check_load(mt, 3);
		480	erase_check_erase(mt, 1);
		481	erase_check_load(mt, 0);
		482	check_load(mt, set[1], NULL);
		483	for (int i = 2; i < 4; i++)
		484	erase_check_load(mt, i);
		485
		486	/*
		487	* Set the newly erased node. This will produce a different allocated
		488	* node to avoid busy slots.
		489	*/
		490	root_node = mt->ma_root;
		491	erase_check_insert(mt, 1);
		492
		493	erase_check_load(mt, 0);
		494	check_load(mt, 5016, NULL);
		495	erase_check_load(mt, 1);
		496	check_load(mt, 5013, NULL);
		497	erase_check_load(mt, 2);
		498	check_load(mt, 5018, NULL);
		499	erase_check_load(mt, 3);
		500
		501	erase_check_erase(mt, 2); /* erase 5017 to check append */
		502	erase_check_load(mt, 0);
		503	check_load(mt, 5016, NULL);
		504	erase_check_load(mt, 1);
		505	check_load(mt, 5013, NULL);
		506	check_load(mt, set[2], NULL);
		507	check_load(mt, 5018, NULL);
		508
		509	erase_check_load(mt, 3);
		510
		511	root_node = mt->ma_root;
		512	erase_check_insert(mt, 2);
		513
		514	erase_check_load(mt, 0);
		515	check_load(mt, 5016, NULL);
		516	erase_check_load(mt, 1);
		517	check_load(mt, 5013, NULL);
		518	erase_check_load(mt, 2);
		519	check_load(mt, 5018, NULL);
		520	erase_check_load(mt, 3);
		521
		522	mt_set_non_kernel(1);
		523	erase_check_erase(mt, 2); /* erase 5017 to check append */
		524	erase_check_load(mt, 0);
		525	check_load(mt, 5016, NULL);
		526	check_load(mt, set[2], NULL);
		527	erase_check_erase(mt, 0); /* erase 5015 to check append */
		528	check_load(mt, set[0], NULL);
		529	check_load(mt, 5016, NULL);
		530	erase_check_insert(mt, 4); /* 1000 < Should not split. */
		531	check_load(mt, set[0], NULL);
		532	check_load(mt, 5016, NULL);
		533	erase_check_load(mt, 1);
		534	check_load(mt, 5013, NULL);
		535	check_load(mt, set[2], NULL);
		536	check_load(mt, 5018, NULL);
		537	erase_check_load(mt, 4);
		538	check_load(mt, 999, NULL);
		539	check_load(mt, 1001, NULL);
		540	erase_check_load(mt, 4);
		541	if (mt_in_rcu(mt))
		542	MT_BUG_ON(mt, root_node == mt->ma_root);
		543	else
		544	MT_BUG_ON(mt, root_node != mt->ma_root);
		545
		546	/* Should not have split. */
		547	MT_BUG_ON(mt, !mte_is_leaf(mt->ma_root));
		548
		549
		550	/* Coalesce testing */
		551	erase_check_insert(mt, 0);
		552	erase_check_insert(mt, 2);
		553
		554	for (int i = 5; i < 25; i++) {
		555	erase_check_insert(mt, i);
		556	for (int j = i; j >= 0; j--)
		557	erase_check_load(mt, j);
		558	}
		559
		560	erase_check_erase(mt, 14); /6015 /
		561	for (int i = 0; i < 25; i++) {
		562	if (i == 14)
		563	check_load(mt, set[i], NULL);
		564	else
		565	erase_check_load(mt, i);
		566	}
		567	erase_check_erase(mt, 16); /7002 /
		568	for (int i = 0; i < 25; i++) {
		569	if (i == 16 \|\| i == 14)
		570	check_load(mt, set[i], NULL);
		571	else
		572	erase_check_load(mt, i);
		573	}
		574
		575
		576	mt_set_non_kernel(1);
		577	erase_check_erase(mt, 13); /6012 /
		578	for (int i = 0; i < 25; i++) {
		579	if (i == 16 \|\| i == 14 \|\| i == 13)
		580	check_load(mt, set[i], NULL);
		581	else
		582	erase_check_load(mt, i);
		583	}
		584
		585	erase_check_erase(mt, 15); /7003 /
		586	for (int i = 0; i < 25; i++) {
		587	if (i <= 16 && i >= 13)
		588	check_load(mt, set[i], NULL);
		589	else
		590	erase_check_load(mt, i);
		591	}
		592
		593	mt_set_non_kernel(2);
		594	erase_check_erase(mt, 17); /7008 should* cause coalesce. */
		595	for (int i = 0; i < 25; i++) {
		596	if (i <= 17 && i >= 13)
		597	check_load(mt, set[i], NULL);
		598	else
		599	erase_check_load(mt, i);
		600	}
		601
		602	erase_check_erase(mt, 18); /7012 /
		603	for (int i = 0; i < 25; i++) {
		604	if (i <= 18 && i >= 13)
		605	check_load(mt, set[i], NULL);
		606	else
		607	erase_check_load(mt, i);
		608	}
		609
		610	mt_set_non_kernel(2);
		611	erase_check_erase(mt, 19); /7015 /
		612	for (int i = 0; i < 25; i++) {
		613	if (i <= 19 && i >= 13)
		614	check_load(mt, set[i], NULL);
		615	else
		616	erase_check_load(mt, i);
		617	}
		618
		619	erase_check_erase(mt, 20); /8003 /
		620	for (int i = 0; i < 25; i++) {
		621	if (i <= 20 && i >= 13)
		622	check_load(mt, set[i], NULL);
		623	else
		624	erase_check_load(mt, i);
		625	}
		626
		627	erase_check_erase(mt, 21); /8002 /
		628	for (int i = 0; i < 25; i++) {
		629	if (i <= 21 && i >= 13)
		630	check_load(mt, set[i], NULL);
		631	else
		632	erase_check_load(mt, i);
		633	}
		634
		635	mt_set_non_kernel(2);
		636	erase_check_erase(mt, 22); /8008 /
		637	for (int i = 0; i < 25; i++) {
		638	if (i <= 22 && i >= 13)
		639	check_load(mt, set[i], NULL);
		640	else
		641	erase_check_load(mt, i);
		642	}
		643	for (int i = 23; i < 25; i++)
		644	erase_check_erase(mt, i);
		645
		646	for (int i = 0; i < 25; i++) {
		647	if (i <= 25 && i >= 13)
		648	check_load(mt, set[i], NULL);
		649	else
		650	erase_check_load(mt, i);
		651	}
		652
		653	/* Shrinking tree test. */
		654
		655	for (int i = 13; i < ARRAY_SIZE(set); i++)
		656	erase_check_insert(mt, i);
		657
		658	mt_set_non_kernel(99);
		659	for (int i = 18; i < ARRAY_SIZE(set); i++) {
		660	erase_check_erase(mt, i);
		661	for (int j = 0; j < ARRAY_SIZE(set); j++) {
		662	if (j < 18 \|\| j > i)
		663	erase_check_load(mt, j);
		664	else
		665	check_load(mt, set[j], NULL);
		666	}
		667	}
		668	mt_set_non_kernel(35);
		669	for (int i = 0; i < 18; i++) {
		670	erase_check_erase(mt, i);
		671	for (int j = 0; j < ARRAY_SIZE(set); j++) {
		672	if (j < 18 && j > i)
		673	erase_check_load(mt, j);
		674	else
		675	check_load(mt, set[j], NULL);
		676	}
		677	}
		678	erase_check_insert(mt, 8);
		679	erase_check_insert(mt, 9);
		680	erase_check_erase(mt, 8);
		681	rcu_unregister_thread();
		682	}
		683
		684	/* End of erase testing */
		685
		686	/* VM Generated Crashes - uses its own tree walk for verification */
		687	#define erase_check_store_range(mt, a, i, ptr) mtree_test_store_range(mt, \
		688	a[(i)], a[(i + 1)], ptr)
		689	#define STORE 1
		690	#define SNULL 2
		691	#define ERASE 3
		692	#define ec_type_str(x) \
		693	(((x) == STORE) ? \
		694	"STORE" : \
		695	(((x) == SNULL) ? \
		696	"SNULL" : "ERASE") \
		697	)
		698	#define check_erase2_debug 0
		699
		700	/* Calculate the overwritten entries. */
		701	int mas_ce2_over_count(struct ma_state mas_start, struct ma_state mas_end,
		702	void *s_entry, unsigned long s_min,
		703	void *e_entry, unsigned long e_max,
		704	unsigned long *set, int i, bool null_entry)
		705	{
		706	int count = 0, span = 0;
		707	unsigned long retry = 0;
		708	void *entry;
		709	struct ma_state tmp;
		710
		711
		712	/* count slots */
		713	memcpy(&tmp, mas_start, sizeof(tmp));
		714	entry = mas_next(&tmp, mas_end->last);
		715	while (entry) {
		716	BUG_ON(retry > 50); /* stop infinite retry on testing. */
		717	if (xa_is_zero(s_entry)) {
		718	retry++;
		719	continue;
		720	}
		721	count++;
		722	span++;
		723	entry = mas_next(&tmp, mas_end->last);
		724	}
		725
		726	if (null_entry) {
		727	/* Check splitting end. */
		728	if (e_entry && (e_max > mas_end->last))
		729	count--;
		730
		731	/* check overwrite of entire start */
		732	if (s_entry && (s_min == mas_start->index))
		733	count++;
		734	} else { /* !null_entry (store) */
		735	bool esplit = e_max > mas_end->last;
		736	bool ssplit = s_min != mas_start->index;
		737
		738	if (s_entry && e_entry) {
		739	if (esplit && ssplit)
		740	count--;
		741	else if (ssplit)
		742	count--;
		743	else if (esplit) {
		744	if (span)
		745	count--;
		746	}
		747	} else if (s_entry && !e_entry) {
		748	if (ssplit)
		749	count--;
		750	} else if (!s_entry && e_entry) {
		751	if (esplit)
		752	count--;
		753	count--;
		754	} else {
		755	count--;
		756	}
		757	}
		758	return count;
		759	}
		760
		761	/*
		762	* mas_node_walk() - Walk a maple node to offset of the index.
		763	* @mas: The maple state
		764	* @type: The maple node type
		765	* @*range_min: Pointer to store the minimum range of the offset
		766	* @*range_max: Pointer to store the maximum range of the offset
		767	*
		768	* The offset will be stored in the maple state.
		769	*
		770	*/
		771	static inline void mas_node_walk(struct ma_state mas, struct maple_node node,
		772	enum maple_type type, unsigned long *range_min,
		773	unsigned long *range_max)
		774
		775	{
		776	unsigned long *pivots;
		777	unsigned char count;
		778	unsigned long prev, max;
		779	unsigned char offset;
		780	unsigned long index;
		781
		782	if (unlikely(ma_is_dense(type))) {
		783	(range_max) = (range_min) = mas->index;
		784	if (unlikely(ma_dead_node(node)))
		785	return;
		786
		787	mas->offset = mas->index = mas->min;
		788	return;
		789	}
		790
		791	pivots = ma_pivots(node, type);
		792	max = pivots[0];
		793	if (unlikely(ma_dead_node(node)))
		794	return;
		795
		796	offset = 0;
		797	prev = mas->min;
		798	index = mas->index;
		799	if (unlikely(index <= max))
		800	goto offset_zero;
		801
		802	count = mt_pivots[type];
		803	while (++offset < count) {
		804	prev = max;
		805	max = pivots[offset];
		806	if (unlikely(ma_dead_node(node)))
		807	return;
		808
		809	if (index <= max)
		810	goto offset_found;
		811	else if (unlikely(!max))
		812	goto mas_max;
		813	}
		814
		815	prev = max;
		816	mas_max:
		817	max = mas->max;
		818	offset_found:
		819	prev++;
		820	offset_zero:
		821	mas->offset = offset;
		822	if (ma_is_leaf(type)) {
		823	*range_max = max;
		824	*range_min = prev;
		825	} else {
		826	mas->max = max;
		827	mas->min = prev;
		828	}
		829	}
		830
		831	/*
		832	* mas_descend_walk(): Locates a value and sets the mas->node and slot
		833	* accordingly. range_min and range_max are set to the range which the entry is
		834	* valid.
		835	* @mas: The maple state
		836	* @*range_min: A pointer to store the minimum of the range
		837	* @*range_max: A pointer to store the maximum of the range
		838	*
		839	* Check mas->node is still valid on return of any value.
		840	*
		841	* Return: true if pointing to a valid node and offset. False otherwise.
		842	*/
		843	static inline bool mas_descend_walk(struct ma_state *mas,
		844	unsigned long range_min, unsigned long range_max)
		845	{
		846	struct maple_enode *next;
		847	struct maple_node *node;
		848	enum maple_type type;
		849
		850	next = mas->node;
		851	while (true) {
		852	node = mte_to_node(next);
		853	type = mte_node_type(next);
		854	mas_node_walk(mas, node, type, range_min, range_max);
		855	next = mas_slot(mas, ma_slots(node, type), mas->offset);
		856	if (unlikely(ma_dead_node(node)))
		857	return false;
		858
		859	if (unlikely(ma_is_leaf(type)))
		860	return true;
		861
		862	/* Descend. */
		863	mas->node = next;
		864	}
		865	return false;
		866	}
		867
		868	/*
		869	* mas_tree_walk() - Walk to @mas->index and set the range values.
		870	* @mas: The maple state.
		871	* @*range_min: The minimum range to be set.
		872	* @*range_max: The maximum range to be set.
		873	*
		874	* Ranges are only valid if there is a valid entry at @mas->index.
		875	*
		876	* Return: True if a value exists, false otherwise.
		877	*/
		878	static inline bool mas_tree_walk(struct ma_state mas, unsigned long range_min,
		879	unsigned long *range_max)
		880	{
		881	bool ret;
		882
		883	retry:
		884	ret = false;
		885	mas_start(mas);
		886	if (mas_is_none(mas))
		887	goto not_found;
		888
		889	if (mas_is_ptr(mas)) {
		890	range_min = range_max = 0;
		891	if (!mas->index)
		892	return true;
		893
		894	goto not_found;
		895	}
		896
		897	ret = mas_descend_walk(mas, range_min, range_max);
		898	if (unlikely(mte_dead_node(mas->node))) {
		899	mas->node = MAS_START;
		900	goto retry;
		901	}
		902
		903	return ret;
		904
		905	not_found:
		906	mas->offset = MAPLE_NODE_SLOTS;
		907	return false;
		908	}
		909
		910	static inline void mas_range_load(struct ma_state mas,
		911	unsigned long range_min, unsigned long range_max)
		912
		913	{
		914	void *entry = NULL;
		915	unsigned long index = mas->index;
		916
		917	if (mas_is_none(mas) \|\| mas_is_paused(mas))
		918	mas->node = MAS_START;
		919	retry:
		920	if (mas_tree_walk(mas, range_min, range_max))
		921	if (unlikely(mas->node == MAS_ROOT))
		922	return mas_root(mas);
		923
		924	if (likely(mas->offset != MAPLE_NODE_SLOTS))
		925	entry = mas_get_slot(mas, mas->offset);
		926
		927	if (mas_dead_node(mas, index))
		928	goto retry;
		929
		930	return entry;
		931	}
		932
		933	#if defined(CONFIG_64BIT)
		934	static noinline void check_erase2_testset(struct maple_tree *mt,
		935	unsigned long *set, unsigned long size)
		936	{
		937	int entry_count = 0;
		938	int check = 0;
		939	void *foo;
		940	unsigned long addr = 0;
		941	void s_entry = NULL, e_entry = NULL;
		942
		943	MA_STATE(mas, mt, 0, 0);
		944
		945	for (int i = 0; i < size; i += 3) {
		946	unsigned long s_min, s_max;
		947	unsigned long e_min, e_max;
		948	void *value = NULL;
		949
		950	MA_STATE(mas_start, mt, set[i+1], set[i+1]);
		951	MA_STATE(mas_end, mt, set[i+2], set[i+2]);
		952	mt_set_non_kernel(127);
		953	#if check_erase2_debug
		954	pr_err("%s: %d %s %lu - %lu\n", __func__, i,
		955	ec_type_str(set[i]),
		956	set[i+1], set[i+2]);
		957	#endif
		958	s_entry = mas_range_load(&mas_start, &s_min, &s_max);
		959	e_entry = mas_range_load(&mas_end, &e_min, &e_max);
		960
		961	switch (set[i]) {
		962	case SNULL:
		963	if ((s_min == set[i+1]) && (s_max == set[i+2])) {
		964	if (s_entry)
		965	entry_count--;
		966	} else if ((s_min != set[i+1]) && (s_max != set[i+2])) {
		967	entry_count++;
		968	} else if ((mas_start.node != mas_end.node) \|\|
		969	(mas_start.offset != mas_end.offset)) {
		970	entry_count -=
		971	mas_ce2_over_count(&mas_start, &mas_end,
		972	s_entry, s_min,
		973	e_entry, e_max, set, i,
		974	true);
		975	}
		976
		977
		978	erase_check_store_range(mt, set, i + 1, value);
		979	break;
		980	case STORE:
		981	value = xa_mk_value(set[i + 1]);
		982	if (mas_start.offset > mt_slot_count(mas_start.node)) {
		983	entry_count++; /* appending an entry. */
		984	} else if ((s_min == e_min) && (s_max == e_max)) {
		985	if (!entry_count)
		986	entry_count++;
		987
		988	else if (s_entry) {
		989	if (e_max > mas_end.last)
		990	entry_count++;
		991
		992	if (s_min < mas_start.index)
		993	entry_count++;
		994
		995	} else {
		996	entry_count++;
		997	}
		998	} else {
		999	entry_count -=
		1000	mas_ce2_over_count(&mas_start, &mas_end,
		1001	s_entry, s_min,
		1002	e_entry, e_max, set, i,
		1003	false);
		1004	}
		1005
		1006	erase_check_store_range(mt, set, i + 1, value);
		1007	break;
		1008	case ERASE:
		1009	if (!s_entry)
		1010	break;
		1011	check_erase(mt, set[i+1], xa_mk_value(set[i+1]));
		1012	entry_count--;
		1013	break;
		1014	}
		1015	mt_validate(mt);
		1016	if (entry_count)
		1017	MT_BUG_ON(mt, !mt_height(mt));
		1018	#if check_erase2_debug > 1
		1019	mt_dump(mt);
		1020	#endif
		1021	#if check_erase2_debug
		1022	pr_err("Done\n");
		1023	#endif
		1024
		1025	check = 0;
		1026	addr = 0;
		1027	mt_for_each(mt, foo, addr, ULONG_MAX) {
		1028	check++;
		1029	#if check_erase2_debug > 2
		1030	pr_err("mt: %lu -> %p (%d)\n", addr+1, foo, check);
		1031	#endif
		1032	if (check > entry_count)
		1033	break;
		1034	}
		1035
		1036	#if check_erase2_debug > 2
		1037	pr_err("mt_for_each %d and count %d\n", check, entry_count);
		1038	#endif
		1039
		1040	MT_BUG_ON(mt, check != entry_count);
		1041
		1042	check = 0;
		1043	addr = 0;
		1044	mas_reset(&mas);
		1045	mas.index = 0;
		1046	rcu_read_lock();
		1047	mas_for_each(&mas, foo, ULONG_MAX) {
		1048	if (xa_is_zero(foo)) {
		1049	if (addr == mas.index) {
		1050	mt_dump(mas.tree);
		1051	pr_err("retry failed %lu - %lu\n",
		1052	mas.index, mas.last);
		1053	MT_BUG_ON(mt, 1);
		1054	}
		1055	addr = mas.index;
		1056	continue;
		1057	}
		1058	#if check_erase2_debug > 2
		1059	pr_err("mas: %lu -> %p\n", mas.index, foo);
		1060	#endif
		1061	check++;
		1062	if (check > entry_count)
		1063	break;
		1064	}
		1065	rcu_read_unlock();
		1066	#if check_erase2_debug > 2
		1067	pr_err("mas_for_each %d and count %d\n", check, entry_count);
		1068	mt_validate(mt);
		1069	#endif
		1070
		1071	MT_BUG_ON(mt, check != entry_count);
		1072
		1073	MT_BUG_ON(mt, mtree_load(mas.tree, 0) != NULL);
		1074	}
		1075	}
		1076
		1077
		1078	/* These tests were pulled from KVM tree modifications which failed. */
		1079	static noinline void check_erase2_sets(struct maple_tree *mt)
		1080	{
		1081	void *entry;
		1082	unsigned long start = 0;
		1083	unsigned long set[] = {
		1084	STORE, 140737488347136, 140737488351231,
		1085	STORE, 140721266458624, 140737488351231,
		1086	ERASE, 140721266458624, 140737488351231,
		1087	STORE, 140721266458624, 140721266462719,
		1088	STORE, 94735788949504, 94735789121535,
		1089	ERASE, 94735788949504, 94735789121535,
		1090	STORE, 94735788949504, 94735788965887,
		1091	STORE, 94735788965888, 94735789121535,
		1092	ERASE, 94735788965888, 94735789121535,
		1093	STORE, 94735788965888, 94735789068287,
		1094	STORE, 94735789068288, 94735789109247,
		1095	STORE, 94735789109248, 94735789121535,
		1096	STORE, 140253902692352, 140253902864383,
		1097	ERASE, 140253902692352, 140253902864383,
		1098	STORE, 140253902692352, 140253902696447,
		1099	STORE, 140253902696448, 140253902864383,
		1100	};
		1101	unsigned long set2[] = {
		1102	STORE, 140737488347136, 140737488351231,
		1103	STORE, 140735933583360, 140737488351231,
		1104	ERASE, 140735933583360, 140737488351231,
		1105	STORE, 140735933583360, 140735933587455,
		1106	STORE, 94811003260928, 94811003432959,
		1107	ERASE, 94811003260928, 94811003432959,
		1108	STORE, 94811003260928, 94811003277311,
		1109	STORE, 94811003277312, 94811003432959,
		1110	ERASE, 94811003277312, 94811003432959,
		1111	STORE, 94811003277312, 94811003379711,
		1112	STORE, 94811003379712, 94811003420671,
		1113	STORE, 94811003420672, 94811003432959,
		1114	STORE, 140277094653952, 140277094825983,
		1115	ERASE, 140277094653952, 140277094825983,
		1116	STORE, 140277094653952, 140277094658047,
		1117	STORE, 140277094658048, 140277094825983,
		1118	ERASE, 140277094658048, 140277094825983,
		1119	STORE, 140277094658048, 140277094780927,
		1120	STORE, 140277094780928, 140277094813695,
		1121	STORE, 140277094813696, 140277094821887,
		1122	STORE, 140277094821888, 140277094825983,
		1123	STORE, 140735933906944, 140735933911039,
		1124	};
		1125	unsigned long set3[] = {
		1126	STORE, 140737488347136, 140737488351231,
		1127	STORE, 140735790264320, 140737488351231,
		1128	ERASE, 140735790264320, 140737488351231,
		1129	STORE, 140735790264320, 140735790268415,
		1130	STORE, 94016597282816, 94016597454847,
		1131	ERASE, 94016597282816, 94016597454847,
		1132	STORE, 94016597282816, 94016597299199,
		1133	STORE, 94016597299200, 94016597454847,
		1134	ERASE, 94016597299200, 94016597454847,
		1135	STORE, 94016597299200, 94016597401599,
		1136	STORE, 94016597401600, 94016597442559,
		1137	STORE, 94016597442560, 94016597454847,
		1138	STORE, 140496959283200, 140496959455231,
		1139	ERASE, 140496959283200, 140496959455231,
		1140	STORE, 140496959283200, 140496959287295,
		1141	STORE, 140496959287296, 140496959455231,
		1142	ERASE, 140496959287296, 140496959455231,
		1143	STORE, 140496959287296, 140496959410175,
		1144	STORE, 140496959410176, 140496959442943,
		1145	STORE, 140496959442944, 140496959451135,
		1146	STORE, 140496959451136, 140496959455231,
		1147	STORE, 140735791718400, 140735791722495,
		1148	STORE, 140735791706112, 140735791718399,
		1149	STORE, 47135835713536, 47135835721727,
		1150	STORE, 47135835721728, 47135835729919,
		1151	STORE, 47135835729920, 47135835893759,
		1152	ERASE, 47135835729920, 47135835893759,
		1153	STORE, 47135835729920, 47135835742207,
		1154	STORE, 47135835742208, 47135835893759,
		1155	STORE, 47135835840512, 47135835893759,
		1156	STORE, 47135835742208, 47135835840511,
		1157	ERASE, 47135835742208, 47135835840511,
		1158	STORE, 47135835742208, 47135835840511,
		1159	STORE, 47135835885568, 47135835893759,
		1160	STORE, 47135835840512, 47135835885567,
		1161	ERASE, 47135835840512, 47135835885567,
		1162	STORE, 47135835840512, 47135835893759,
		1163	ERASE, 47135835840512, 47135835893759,
		1164	STORE, 47135835840512, 47135835885567,
		1165	STORE, 47135835885568, 47135835893759,
		1166	};
		1167
		1168	unsigned long set4[] = {
		1169	STORE, 140737488347136, 140737488351231,
		1170	STORE, 140728251703296, 140737488351231,
		1171	ERASE, 140728251703296, 140737488351231,
		1172	STORE, 140728251703296, 140728251707391,
		1173	STORE, 94668429205504, 94668429377535,
		1174	ERASE, 94668429205504, 94668429377535,
		1175	STORE, 94668429205504, 94668429221887,
		1176	STORE, 94668429221888, 94668429377535,
		1177	ERASE, 94668429221888, 94668429377535,
		1178	STORE, 94668429221888, 94668429324287,
		1179	STORE, 94668429324288, 94668429365247,
		1180	STORE, 94668429365248, 94668429377535,
		1181	STORE, 47646523273216, 47646523445247,
		1182	ERASE, 47646523273216, 47646523445247,
		1183	STORE, 47646523273216, 47646523277311,
		1184	STORE, 47646523277312, 47646523445247,
		1185	ERASE, 47646523277312, 47646523445247,
		1186	STORE, 47646523277312, 47646523400191,
		1187	};
		1188
		1189	unsigned long set5[] = {
		1190	STORE, 140737488347136, 140737488351231,
		1191	STORE, 140726874062848, 140737488351231,
		1192	ERASE, 140726874062848, 140737488351231,
		1193	STORE, 140726874062848, 140726874066943,
		1194	STORE, 94248892870656, 94248893042687,
		1195	ERASE, 94248892870656, 94248893042687,
		1196	STORE, 94248892870656, 94248892887039,
		1197	STORE, 94248892887040, 94248893042687,
		1198	ERASE, 94248892887040, 94248893042687,
		1199	STORE, 94248892887040, 94248892989439,
		1200	STORE, 94248892989440, 94248893030399,
		1201	STORE, 94248893030400, 94248893042687,
		1202	STORE, 47884786266112, 47884786438143,
		1203	ERASE, 47884786266112, 47884786438143,
		1204	STORE, 47884786266112, 47884786270207,
		1205	STORE, 47884786270208, 47884786438143,
		1206	ERASE, 47884786270208, 47884786438143,
		1207	STORE, 47884786270208, 47884786393087,
		1208	STORE, 47884786393088, 47884786425855,
		1209	STORE, 47884786425856, 47884786434047,
		1210	STORE, 47884786434048, 47884786438143,
		1211	STORE, 140726874513408, 140726874517503,
		1212	STORE, 140726874501120, 140726874513407,
		1213	STORE, 47884786438144, 47884786446335,
		1214	STORE, 47884786446336, 47884786454527,
		1215	STORE, 47884786454528, 47884786618367,
		1216	ERASE, 47884786454528, 47884786618367,
		1217	STORE, 47884786454528, 47884786466815,
		1218	STORE, 47884786466816, 47884786618367,
		1219	STORE, 47884786565120, 47884786618367,
		1220	STORE, 47884786466816, 47884786565119,
		1221	ERASE, 47884786466816, 47884786565119,
		1222	STORE, 47884786466816, 47884786565119,
		1223	STORE, 47884786610176, 47884786618367,
		1224	STORE, 47884786565120, 47884786610175,
		1225	ERASE, 47884786565120, 47884786610175,
		1226	STORE, 47884786565120, 47884786618367,
		1227	ERASE, 47884786565120, 47884786618367,
		1228	STORE, 47884786565120, 47884786610175,
		1229	STORE, 47884786610176, 47884786618367,
		1230	ERASE, 47884786610176, 47884786618367,
		1231	STORE, 47884786610176, 47884786618367,
		1232	STORE, 47884786618368, 47884789669887,
		1233	STORE, 47884787163136, 47884789669887,
		1234	STORE, 47884786618368, 47884787163135,
		1235	ERASE, 47884787163136, 47884789669887,
		1236	STORE, 47884787163136, 47884789448703,
		1237	STORE, 47884789448704, 47884789669887,
		1238	STORE, 47884788858880, 47884789448703,
		1239	STORE, 47884787163136, 47884788858879,
		1240	ERASE, 47884787163136, 47884788858879,
		1241	STORE, 47884787163136, 47884788858879,
		1242	STORE, 47884789444608, 47884789448703,
		1243	STORE, 47884788858880, 47884789444607,
		1244	ERASE, 47884788858880, 47884789444607,
		1245	STORE, 47884788858880, 47884789444607,
		1246	STORE, 47884789653504, 47884789669887,
		1247	STORE, 47884789448704, 47884789653503,
		1248	ERASE, 47884789448704, 47884789653503,
		1249	STORE, 47884789448704, 47884789653503,
		1250	ERASE, 47884789653504, 47884789669887,
		1251	STORE, 47884789653504, 47884789669887,
		1252	STORE, 47884789669888, 47884791508991,
		1253	STORE, 47884789809152, 47884791508991,
		1254	STORE, 47884789669888, 47884789809151,
		1255	ERASE, 47884789809152, 47884791508991,
		1256	STORE, 47884789809152, 47884791468031,
		1257	STORE, 47884791468032, 47884791508991,
		1258	STORE, 47884791152640, 47884791468031,
		1259	STORE, 47884789809152, 47884791152639,
		1260	ERASE, 47884789809152, 47884791152639,
		1261	STORE, 47884789809152, 47884791152639,
		1262	STORE, 47884791463936, 47884791468031,
		1263	STORE, 47884791152640, 47884791463935,
		1264	ERASE, 47884791152640, 47884791463935,
		1265	STORE, 47884791152640, 47884791463935,
		1266	STORE, 47884791492608, 47884791508991,
		1267	STORE, 47884791468032, 47884791492607,
		1268	ERASE, 47884791468032, 47884791492607,
		1269	STORE, 47884791468032, 47884791492607,
		1270	ERASE, 47884791492608, 47884791508991,
		1271	STORE, 47884791492608, 47884791508991,
		1272	STORE, 47884791508992, 47884791644159,
		1273	ERASE, 47884791508992, 47884791644159,
		1274	STORE, 47884791508992, 47884791533567,
		1275	STORE, 47884791533568, 47884791644159,
		1276	STORE, 47884791595008, 47884791644159,
		1277	STORE, 47884791533568, 47884791595007,
		1278	ERASE, 47884791533568, 47884791595007,
		1279	STORE, 47884791533568, 47884791595007,
		1280	STORE, 47884791619584, 47884791644159,
		1281	STORE, 47884791595008, 47884791619583,
		1282	ERASE, 47884791595008, 47884791619583,
		1283	STORE, 47884791595008, 47884791644159,
		1284	ERASE, 47884791595008, 47884791644159,
		1285	STORE, 47884791595008, 47884791619583,
		1286	STORE, 47884791619584, 47884791644159,
		1287	STORE, 47884791627776, 47884791644159,
		1288	STORE, 47884791619584, 47884791627775,
		1289	ERASE, 47884791619584, 47884791627775,
		1290	STORE, 47884791619584, 47884791627775,
		1291	ERASE, 47884791627776, 47884791644159,
		1292	STORE, 47884791627776, 47884791644159,
		1293	STORE, 47884791644160, 47884791664639,
		1294	ERASE, 47884791644160, 47884791664639,
		1295	STORE, 47884791644160, 47884791648255,
		1296	STORE, 47884791648256, 47884791664639,
		1297	STORE, 47884791652352, 47884791664639,
		1298	STORE, 47884791648256, 47884791652351,
		1299	ERASE, 47884791648256, 47884791652351,
		1300	STORE, 47884791648256, 47884791652351,
		1301	STORE, 47884791656448, 47884791664639,
		1302	STORE, 47884791652352, 47884791656447,
		1303	ERASE, 47884791652352, 47884791656447,
		1304	STORE, 47884791652352, 47884791664639,
		1305	ERASE, 47884791652352, 47884791664639,
		1306	STORE, 47884791652352, 47884791656447,
		1307	STORE, 47884791656448, 47884791664639,
		1308	ERASE, 47884791656448, 47884791664639,
		1309	STORE, 47884791656448, 47884791664639,
		1310	STORE, 47884791664640, 47884791672831,
		1311	ERASE, 47884791468032, 47884791492607,
		1312	STORE, 47884791468032, 47884791484415,
		1313	STORE, 47884791484416, 47884791492607,
		1314	ERASE, 47884791656448, 47884791664639,
		1315	STORE, 47884791656448, 47884791660543,
		1316	STORE, 47884791660544, 47884791664639,
		1317	ERASE, 47884791619584, 47884791627775,
		1318	STORE, 47884791619584, 47884791623679,
		1319	STORE, 47884791623680, 47884791627775,
		1320	};
		1321
		1322	unsigned long set6[] = {
		1323	STORE, 140737488347136, 140737488351231,
		1324	STORE, 140722999021568, 140737488351231,
		1325	ERASE, 140722999021568, 140737488351231,
		1326	STORE, 140722999021568, 140722999025663,
		1327	STORE, 94901500268544, 94901500440575,
		1328	ERASE, 94901500268544, 94901500440575,
		1329	STORE, 94901500268544, 94901500284927,
		1330	STORE, 94901500284928, 94901500440575,
		1331	ERASE, 94901500284928, 94901500440575,
		1332	STORE, 94901500284928, 94901500387327,
		1333	STORE, 94901500387328, 94901500428287,
		1334	STORE, 94901500428288, 94901500440575,
		1335	STORE, 47430426660864, 47430426832895,
		1336	ERASE, 47430426660864, 47430426832895,
		1337	STORE, 47430426660864, 47430426664959,
		1338	STORE, 47430426664960, 47430426832895,
		1339	ERASE, 47430426664960, 47430426832895,
		1340	STORE, 47430426664960, 47430426787839,
		1341	STORE, 47430426787840, 47430426820607,
		1342	STORE, 47430426820608, 47430426828799,
		1343	STORE, 47430426828800, 47430426832895,
		1344	STORE, 140722999115776, 140722999119871,
		1345	STORE, 140722999103488, 140722999115775,
		1346	STORE, 47430426832896, 47430426841087,
		1347	STORE, 47430426841088, 47430426849279,
		1348	STORE, 47430426849280, 47430427013119,
		1349	ERASE, 47430426849280, 47430427013119,
		1350	STORE, 47430426849280, 47430426861567,
		1351	STORE, 47430426861568, 47430427013119,
		1352	STORE, 47430426959872, 47430427013119,
		1353	STORE, 47430426861568, 47430426959871,
		1354	ERASE, 47430426861568, 47430426959871,
		1355	STORE, 47430426861568, 47430426959871,
		1356	STORE, 47430427004928, 47430427013119,
		1357	STORE, 47430426959872, 47430427004927,
		1358	ERASE, 47430426959872, 47430427004927,
		1359	STORE, 47430426959872, 47430427013119,
		1360	ERASE, 47430426959872, 47430427013119,
		1361	STORE, 47430426959872, 47430427004927,
		1362	STORE, 47430427004928, 47430427013119,
		1363	ERASE, 47430427004928, 47430427013119,
		1364	STORE, 47430427004928, 47430427013119,
		1365	STORE, 47430427013120, 47430430064639,
		1366	STORE, 47430427557888, 47430430064639,
		1367	STORE, 47430427013120, 47430427557887,
		1368	ERASE, 47430427557888, 47430430064639,
		1369	STORE, 47430427557888, 47430429843455,
		1370	STORE, 47430429843456, 47430430064639,
		1371	STORE, 47430429253632, 47430429843455,
		1372	STORE, 47430427557888, 47430429253631,
		1373	ERASE, 47430427557888, 47430429253631,
		1374	STORE, 47430427557888, 47430429253631,
		1375	STORE, 47430429839360, 47430429843455,
		1376	STORE, 47430429253632, 47430429839359,
		1377	ERASE, 47430429253632, 47430429839359,
		1378	STORE, 47430429253632, 47430429839359,
		1379	STORE, 47430430048256, 47430430064639,
		1380	STORE, 47430429843456, 47430430048255,
		1381	ERASE, 47430429843456, 47430430048255,
		1382	STORE, 47430429843456, 47430430048255,
		1383	ERASE, 47430430048256, 47430430064639,
		1384	STORE, 47430430048256, 47430430064639,
		1385	STORE, 47430430064640, 47430431903743,
		1386	STORE, 47430430203904, 47430431903743,
		1387	STORE, 47430430064640, 47430430203903,
		1388	ERASE, 47430430203904, 47430431903743,
		1389	STORE, 47430430203904, 47430431862783,
		1390	STORE, 47430431862784, 47430431903743,
		1391	STORE, 47430431547392, 47430431862783,
		1392	STORE, 47430430203904, 47430431547391,
		1393	ERASE, 47430430203904, 47430431547391,
		1394	STORE, 47430430203904, 47430431547391,
		1395	STORE, 47430431858688, 47430431862783,
		1396	STORE, 47430431547392, 47430431858687,
		1397	ERASE, 47430431547392, 47430431858687,
		1398	STORE, 47430431547392, 47430431858687,
		1399	STORE, 47430431887360, 47430431903743,
		1400	STORE, 47430431862784, 47430431887359,
		1401	ERASE, 47430431862784, 47430431887359,
		1402	STORE, 47430431862784, 47430431887359,
		1403	ERASE, 47430431887360, 47430431903743,
		1404	STORE, 47430431887360, 47430431903743,
		1405	STORE, 47430431903744, 47430432038911,
		1406	ERASE, 47430431903744, 47430432038911,
		1407	STORE, 47430431903744, 47430431928319,
		1408	STORE, 47430431928320, 47430432038911,
		1409	STORE, 47430431989760, 47430432038911,
		1410	STORE, 47430431928320, 47430431989759,
		1411	ERASE, 47430431928320, 47430431989759,
		1412	STORE, 47430431928320, 47430431989759,
		1413	STORE, 47430432014336, 47430432038911,
		1414	STORE, 47430431989760, 47430432014335,
		1415	ERASE, 47430431989760, 47430432014335,
		1416	STORE, 47430431989760, 47430432038911,
		1417	ERASE, 47430431989760, 47430432038911,
		1418	STORE, 47430431989760, 47430432014335,
		1419	STORE, 47430432014336, 47430432038911,
		1420	STORE, 47430432022528, 47430432038911,
		1421	STORE, 47430432014336, 47430432022527,
		1422	ERASE, 47430432014336, 47430432022527,
		1423	STORE, 47430432014336, 47430432022527,
		1424	ERASE, 47430432022528, 47430432038911,
		1425	STORE, 47430432022528, 47430432038911,
		1426	STORE, 47430432038912, 47430432059391,
		1427	ERASE, 47430432038912, 47430432059391,
		1428	STORE, 47430432038912, 47430432043007,
		1429	STORE, 47430432043008, 47430432059391,
		1430	STORE, 47430432047104, 47430432059391,
		1431	STORE, 47430432043008, 47430432047103,
		1432	ERASE, 47430432043008, 47430432047103,
		1433	STORE, 47430432043008, 47430432047103,
		1434	STORE, 47430432051200, 47430432059391,
		1435	STORE, 47430432047104, 47430432051199,
		1436	ERASE, 47430432047104, 47430432051199,
		1437	STORE, 47430432047104, 47430432059391,
		1438	ERASE, 47430432047104, 47430432059391,
		1439	STORE, 47430432047104, 47430432051199,
		1440	STORE, 47430432051200, 47430432059391,
		1441	ERASE, 47430432051200, 47430432059391,
		1442	STORE, 47430432051200, 47430432059391,
		1443	STORE, 47430432059392, 47430432067583,
		1444	ERASE, 47430431862784, 47430431887359,
		1445	STORE, 47430431862784, 47430431879167,
		1446	STORE, 47430431879168, 47430431887359,
		1447	ERASE, 47430432051200, 47430432059391,
		1448	STORE, 47430432051200, 47430432055295,
		1449	STORE, 47430432055296, 47430432059391,
		1450	ERASE, 47430432014336, 47430432022527,
		1451	STORE, 47430432014336, 47430432018431,
		1452	STORE, 47430432018432, 47430432022527,
		1453	};
		1454	unsigned long set7[] = {
		1455	STORE, 140737488347136, 140737488351231,
		1456	STORE, 140729808330752, 140737488351231,
		1457	ERASE, 140729808330752, 140737488351231,
		1458	STORE, 140729808330752, 140729808334847,
		1459	STORE, 94629632020480, 94629632192511,
		1460	ERASE, 94629632020480, 94629632192511,
		1461	STORE, 94629632020480, 94629632036863,
		1462	STORE, 94629632036864, 94629632192511,
		1463	ERASE, 94629632036864, 94629632192511,
		1464	STORE, 94629632036864, 94629632139263,
		1465	STORE, 94629632139264, 94629632180223,
		1466	STORE, 94629632180224, 94629632192511,
		1467	STORE, 47439981776896, 47439981948927,
		1468	ERASE, 47439981776896, 47439981948927,
		1469	STORE, 47439981776896, 47439981780991,
		1470	STORE, 47439981780992, 47439981948927,
		1471	ERASE, 47439981780992, 47439981948927,
		1472	STORE, 47439981780992, 47439981903871,
		1473	STORE, 47439981903872, 47439981936639,
		1474	STORE, 47439981936640, 47439981944831,
		1475	STORE, 47439981944832, 47439981948927,
		1476	STORE, 140729808474112, 140729808478207,
		1477	STORE, 140729808461824, 140729808474111,
		1478	STORE, 47439981948928, 47439981957119,
		1479	STORE, 47439981957120, 47439981965311,
		1480	STORE, 47439981965312, 47439982129151,
		1481	ERASE, 47439981965312, 47439982129151,
		1482	STORE, 47439981965312, 47439981977599,
		1483	STORE, 47439981977600, 47439982129151,
		1484	STORE, 47439982075904, 47439982129151,
		1485	STORE, 47439981977600, 47439982075903,
		1486	ERASE, 47439981977600, 47439982075903,
		1487	STORE, 47439981977600, 47439982075903,
		1488	STORE, 47439982120960, 47439982129151,
		1489	STORE, 47439982075904, 47439982120959,
		1490	ERASE, 47439982075904, 47439982120959,
		1491	STORE, 47439982075904, 47439982129151,
		1492	ERASE, 47439982075904, 47439982129151,
		1493	STORE, 47439982075904, 47439982120959,
		1494	STORE, 47439982120960, 47439982129151,
		1495	ERASE, 47439982120960, 47439982129151,
		1496	STORE, 47439982120960, 47439982129151,
		1497	STORE, 47439982129152, 47439985180671,
		1498	STORE, 47439982673920, 47439985180671,
		1499	STORE, 47439982129152, 47439982673919,
		1500	ERASE, 47439982673920, 47439985180671,
		1501	STORE, 47439982673920, 47439984959487,
		1502	STORE, 47439984959488, 47439985180671,
		1503	STORE, 47439984369664, 47439984959487,
		1504	STORE, 47439982673920, 47439984369663,
		1505	ERASE, 47439982673920, 47439984369663,
		1506	STORE, 47439982673920, 47439984369663,
		1507	STORE, 47439984955392, 47439984959487,
		1508	STORE, 47439984369664, 47439984955391,
		1509	ERASE, 47439984369664, 47439984955391,
		1510	STORE, 47439984369664, 47439984955391,
		1511	STORE, 47439985164288, 47439985180671,
		1512	STORE, 47439984959488, 47439985164287,
		1513	ERASE, 47439984959488, 47439985164287,
		1514	STORE, 47439984959488, 47439985164287,
		1515	ERASE, 47439985164288, 47439985180671,
		1516	STORE, 47439985164288, 47439985180671,
		1517	STORE, 47439985180672, 47439987019775,
		1518	STORE, 47439985319936, 47439987019775,
		1519	STORE, 47439985180672, 47439985319935,
		1520	ERASE, 47439985319936, 47439987019775,
		1521	STORE, 47439985319936, 47439986978815,
		1522	STORE, 47439986978816, 47439987019775,
		1523	STORE, 47439986663424, 47439986978815,
		1524	STORE, 47439985319936, 47439986663423,
		1525	ERASE, 47439985319936, 47439986663423,
		1526	STORE, 47439985319936, 47439986663423,
		1527	STORE, 47439986974720, 47439986978815,
		1528	STORE, 47439986663424, 47439986974719,
		1529	ERASE, 47439986663424, 47439986974719,
		1530	STORE, 47439986663424, 47439986974719,
		1531	STORE, 47439987003392, 47439987019775,
		1532	STORE, 47439986978816, 47439987003391,
		1533	ERASE, 47439986978816, 47439987003391,
		1534	STORE, 47439986978816, 47439987003391,
		1535	ERASE, 47439987003392, 47439987019775,
		1536	STORE, 47439987003392, 47439987019775,
		1537	STORE, 47439987019776, 47439987154943,
		1538	ERASE, 47439987019776, 47439987154943,
		1539	STORE, 47439987019776, 47439987044351,
		1540	STORE, 47439987044352, 47439987154943,
		1541	STORE, 47439987105792, 47439987154943,
		1542	STORE, 47439987044352, 47439987105791,
		1543	ERASE, 47439987044352, 47439987105791,
		1544	STORE, 47439987044352, 47439987105791,
		1545	STORE, 47439987130368, 47439987154943,
		1546	STORE, 47439987105792, 47439987130367,
		1547	ERASE, 47439987105792, 47439987130367,
		1548	STORE, 47439987105792, 47439987154943,
		1549	ERASE, 47439987105792, 47439987154943,
		1550	STORE, 47439987105792, 47439987130367,
		1551	STORE, 47439987130368, 47439987154943,
		1552	STORE, 47439987138560, 47439987154943,
		1553	STORE, 47439987130368, 47439987138559,
		1554	ERASE, 47439987130368, 47439987138559,
		1555	STORE, 47439987130368, 47439987138559,
		1556	ERASE, 47439987138560, 47439987154943,
		1557	STORE, 47439987138560, 47439987154943,
		1558	STORE, 47439987154944, 47439987175423,
		1559	ERASE, 47439987154944, 47439987175423,
		1560	STORE, 47439987154944, 47439987159039,
		1561	STORE, 47439987159040, 47439987175423,
		1562	STORE, 47439987163136, 47439987175423,
		1563	STORE, 47439987159040, 47439987163135,
		1564	ERASE, 47439987159040, 47439987163135,
		1565	STORE, 47439987159040, 47439987163135,
		1566	STORE, 47439987167232, 47439987175423,
		1567	STORE, 47439987163136, 47439987167231,
		1568	ERASE, 47439987163136, 47439987167231,
		1569	STORE, 47439987163136, 47439987175423,
		1570	ERASE, 47439987163136, 47439987175423,
		1571	STORE, 47439987163136, 47439987167231,
		1572	STORE, 47439987167232, 47439987175423,
		1573	ERASE, 47439987167232, 47439987175423,
		1574	STORE, 47439987167232, 47439987175423,
		1575	STORE, 47439987175424, 47439987183615,
		1576	ERASE, 47439986978816, 47439987003391,
		1577	STORE, 47439986978816, 47439986995199,
		1578	STORE, 47439986995200, 47439987003391,
		1579	ERASE, 47439987167232, 47439987175423,
		1580	STORE, 47439987167232, 47439987171327,
		1581	STORE, 47439987171328, 47439987175423,
		1582	ERASE, 47439987130368, 47439987138559,
		1583	STORE, 47439987130368, 47439987134463,
		1584	STORE, 47439987134464, 47439987138559,
		1585	};
		1586	unsigned long set8[] = {
		1587	STORE, 140737488347136, 140737488351231,
		1588	STORE, 140722482974720, 140737488351231,
		1589	ERASE, 140722482974720, 140737488351231,
		1590	STORE, 140722482974720, 140722482978815,
		1591	STORE, 94121505034240, 94121505206271,
		1592	ERASE, 94121505034240, 94121505206271,
		1593	STORE, 94121505034240, 94121505050623,
		1594	STORE, 94121505050624, 94121505206271,
		1595	ERASE, 94121505050624, 94121505206271,
		1596	STORE, 94121505050624, 94121505153023,
		1597	STORE, 94121505153024, 94121505193983,
		1598	STORE, 94121505193984, 94121505206271,
		1599	STORE, 47708483284992, 47708483457023,
		1600	ERASE, 47708483284992, 47708483457023,
		1601	STORE, 47708483284992, 47708483289087,
		1602	STORE, 47708483289088, 47708483457023,
		1603	ERASE, 47708483289088, 47708483457023,
		1604	STORE, 47708483289088, 47708483411967,
		1605	STORE, 47708483411968, 47708483444735,
		1606	STORE, 47708483444736, 47708483452927,
		1607	STORE, 47708483452928, 47708483457023,
		1608	STORE, 140722483142656, 140722483146751,
		1609	STORE, 140722483130368, 140722483142655,
		1610	STORE, 47708483457024, 47708483465215,
		1611	STORE, 47708483465216, 47708483473407,
		1612	STORE, 47708483473408, 47708483637247,
		1613	ERASE, 47708483473408, 47708483637247,
		1614	STORE, 47708483473408, 47708483485695,
		1615	STORE, 47708483485696, 47708483637247,
		1616	STORE, 47708483584000, 47708483637247,
		1617	STORE, 47708483485696, 47708483583999,
		1618	ERASE, 47708483485696, 47708483583999,
		1619	STORE, 47708483485696, 47708483583999,
		1620	STORE, 47708483629056, 47708483637247,
		1621	STORE, 47708483584000, 47708483629055,
		1622	ERASE, 47708483584000, 47708483629055,
		1623	STORE, 47708483584000, 47708483637247,
		1624	ERASE, 47708483584000, 47708483637247,
		1625	STORE, 47708483584000, 47708483629055,
		1626	STORE, 47708483629056, 47708483637247,
		1627	ERASE, 47708483629056, 47708483637247,
		1628	STORE, 47708483629056, 47708483637247,
		1629	STORE, 47708483637248, 47708486688767,
		1630	STORE, 47708484182016, 47708486688767,
		1631	STORE, 47708483637248, 47708484182015,
		1632	ERASE, 47708484182016, 47708486688767,
		1633	STORE, 47708484182016, 47708486467583,
		1634	STORE, 47708486467584, 47708486688767,
		1635	STORE, 47708485877760, 47708486467583,
		1636	STORE, 47708484182016, 47708485877759,
		1637	ERASE, 47708484182016, 47708485877759,
		1638	STORE, 47708484182016, 47708485877759,
		1639	STORE, 47708486463488, 47708486467583,
		1640	STORE, 47708485877760, 47708486463487,
		1641	ERASE, 47708485877760, 47708486463487,
		1642	STORE, 47708485877760, 47708486463487,
		1643	STORE, 47708486672384, 47708486688767,
		1644	STORE, 47708486467584, 47708486672383,
		1645	ERASE, 47708486467584, 47708486672383,
		1646	STORE, 47708486467584, 47708486672383,
		1647	ERASE, 47708486672384, 47708486688767,
		1648	STORE, 47708486672384, 47708486688767,
		1649	STORE, 47708486688768, 47708488527871,
		1650	STORE, 47708486828032, 47708488527871,
		1651	STORE, 47708486688768, 47708486828031,
		1652	ERASE, 47708486828032, 47708488527871,
		1653	STORE, 47708486828032, 47708488486911,
		1654	STORE, 47708488486912, 47708488527871,
		1655	STORE, 47708488171520, 47708488486911,
		1656	STORE, 47708486828032, 47708488171519,
		1657	ERASE, 47708486828032, 47708488171519,
		1658	STORE, 47708486828032, 47708488171519,
		1659	STORE, 47708488482816, 47708488486911,
		1660	STORE, 47708488171520, 47708488482815,
		1661	ERASE, 47708488171520, 47708488482815,
		1662	STORE, 47708488171520, 47708488482815,
		1663	STORE, 47708488511488, 47708488527871,
		1664	STORE, 47708488486912, 47708488511487,
		1665	ERASE, 47708488486912, 47708488511487,
		1666	STORE, 47708488486912, 47708488511487,
		1667	ERASE, 47708488511488, 47708488527871,
		1668	STORE, 47708488511488, 47708488527871,
		1669	STORE, 47708488527872, 47708488663039,
		1670	ERASE, 47708488527872, 47708488663039,
		1671	STORE, 47708488527872, 47708488552447,
		1672	STORE, 47708488552448, 47708488663039,
		1673	STORE, 47708488613888, 47708488663039,
		1674	STORE, 47708488552448, 47708488613887,
		1675	ERASE, 47708488552448, 47708488613887,
		1676	STORE, 47708488552448, 47708488613887,
		1677	STORE, 47708488638464, 47708488663039,
		1678	STORE, 47708488613888, 47708488638463,
		1679	ERASE, 47708488613888, 47708488638463,
		1680	STORE, 47708488613888, 47708488663039,
		1681	ERASE, 47708488613888, 47708488663039,
		1682	STORE, 47708488613888, 47708488638463,
		1683	STORE, 47708488638464, 47708488663039,
		1684	STORE, 47708488646656, 47708488663039,
		1685	STORE, 47708488638464, 47708488646655,
		1686	ERASE, 47708488638464, 47708488646655,
		1687	STORE, 47708488638464, 47708488646655,
		1688	ERASE, 47708488646656, 47708488663039,
		1689	STORE, 47708488646656, 47708488663039,
		1690	STORE, 47708488663040, 47708488683519,
		1691	ERASE, 47708488663040, 47708488683519,
		1692	STORE, 47708488663040, 47708488667135,
		1693	STORE, 47708488667136, 47708488683519,
		1694	STORE, 47708488671232, 47708488683519,
		1695	STORE, 47708488667136, 47708488671231,
		1696	ERASE, 47708488667136, 47708488671231,
		1697	STORE, 47708488667136, 47708488671231,
		1698	STORE, 47708488675328, 47708488683519,
		1699	STORE, 47708488671232, 47708488675327,
		1700	ERASE, 47708488671232, 47708488675327,
		1701	STORE, 47708488671232, 47708488683519,
		1702	ERASE, 47708488671232, 47708488683519,
		1703	STORE, 47708488671232, 47708488675327,
		1704	STORE, 47708488675328, 47708488683519,
		1705	ERASE, 47708488675328, 47708488683519,
		1706	STORE, 47708488675328, 47708488683519,
		1707	STORE, 47708488683520, 47708488691711,
		1708	ERASE, 47708488486912, 47708488511487,
		1709	STORE, 47708488486912, 47708488503295,
		1710	STORE, 47708488503296, 47708488511487,
		1711	ERASE, 47708488675328, 47708488683519,
		1712	STORE, 47708488675328, 47708488679423,
		1713	STORE, 47708488679424, 47708488683519,
		1714	ERASE, 47708488638464, 47708488646655,
		1715	STORE, 47708488638464, 47708488642559,
		1716	STORE, 47708488642560, 47708488646655,
		1717	};
		1718
		1719	unsigned long set9[] = {
		1720	STORE, 140737488347136, 140737488351231,
		1721	STORE, 140736427839488, 140737488351231,
		1722	ERASE, 140736427839488, 140736427839488,
		1723	STORE, 140736427839488, 140736427843583,
		1724	STORE, 94071213395968, 94071213567999,
		1725	ERASE, 94071213395968, 94071213395968,
		1726	STORE, 94071213395968, 94071213412351,
		1727	STORE, 94071213412352, 94071213567999,
		1728	ERASE, 94071213412352, 94071213412352,
		1729	STORE, 94071213412352, 94071213514751,
		1730	STORE, 94071213514752, 94071213555711,
		1731	STORE, 94071213555712, 94071213567999,
		1732	STORE, 139968410644480, 139968410816511,
		1733	ERASE, 139968410644480, 139968410644480,
		1734	STORE, 139968410644480, 139968410648575,
		1735	STORE, 139968410648576, 139968410816511,
		1736	ERASE, 139968410648576, 139968410648576,
		1737	STORE, 139968410648576, 139968410771455,
		1738	STORE, 139968410771456, 139968410804223,
		1739	STORE, 139968410804224, 139968410812415,
		1740	STORE, 139968410812416, 139968410816511,
		1741	STORE, 140736429277184, 140736429281279,
		1742	STORE, 140736429264896, 140736429277183,
		1743	STORE, 47664384352256, 47664384360447,
		1744	STORE, 47664384360448, 47664384368639,
		1745	STORE, 47664384368640, 47664384532479,
		1746	ERASE, 47664384368640, 47664384368640,
		1747	STORE, 47664384368640, 47664384380927,
		1748	STORE, 47664384380928, 47664384532479,
		1749	STORE, 47664384479232, 47664384532479,
		1750	STORE, 47664384380928, 47664384479231,
		1751	ERASE, 47664384380928, 47664384380928,
		1752	STORE, 47664384380928, 47664384479231,
		1753	STORE, 47664384524288, 47664384532479,
		1754	STORE, 47664384479232, 47664384524287,
		1755	ERASE, 47664384479232, 47664384479232,
		1756	STORE, 47664384479232, 47664384532479,
		1757	ERASE, 47664384479232, 47664384479232,
		1758	STORE, 47664384479232, 47664384524287,
		1759	STORE, 47664384524288, 47664384532479,
		1760	ERASE, 47664384524288, 47664384524288,
		1761	STORE, 47664384524288, 47664384532479,
		1762	STORE, 47664384532480, 47664387583999,
		1763	STORE, 47664385077248, 47664387583999,
		1764	STORE, 47664384532480, 47664385077247,
		1765	ERASE, 47664385077248, 47664385077248,
		1766	STORE, 47664385077248, 47664387362815,
		1767	STORE, 47664387362816, 47664387583999,
		1768	STORE, 47664386772992, 47664387362815,
		1769	STORE, 47664385077248, 47664386772991,
		1770	ERASE, 47664385077248, 47664385077248,
		1771	STORE, 47664385077248, 47664386772991,
		1772	STORE, 47664387358720, 47664387362815,
		1773	STORE, 47664386772992, 47664387358719,
		1774	ERASE, 47664386772992, 47664386772992,
		1775	STORE, 47664386772992, 47664387358719,
		1776	STORE, 47664387567616, 47664387583999,
		1777	STORE, 47664387362816, 47664387567615,
		1778	ERASE, 47664387362816, 47664387362816,
		1779	STORE, 47664387362816, 47664387567615,
		1780	ERASE, 47664387567616, 47664387567616,
		1781	STORE, 47664387567616, 47664387583999,
		1782	STORE, 47664387584000, 47664389423103,
		1783	STORE, 47664387723264, 47664389423103,
		1784	STORE, 47664387584000, 47664387723263,
		1785	ERASE, 47664387723264, 47664387723264,
		1786	STORE, 47664387723264, 47664389382143,
		1787	STORE, 47664389382144, 47664389423103,
		1788	STORE, 47664389066752, 47664389382143,
		1789	STORE, 47664387723264, 47664389066751,
		1790	ERASE, 47664387723264, 47664387723264,
		1791	STORE, 47664387723264, 47664389066751,
		1792	STORE, 47664389378048, 47664389382143,
		1793	STORE, 47664389066752, 47664389378047,
		1794	ERASE, 47664389066752, 47664389066752,
		1795	STORE, 47664389066752, 47664389378047,
		1796	STORE, 47664389406720, 47664389423103,
		1797	STORE, 47664389382144, 47664389406719,
		1798	ERASE, 47664389382144, 47664389382144,
		1799	STORE, 47664389382144, 47664389406719,
		1800	ERASE, 47664389406720, 47664389406720,
		1801	STORE, 47664389406720, 47664389423103,
		1802	STORE, 47664389423104, 47664389558271,
		1803	ERASE, 47664389423104, 47664389423104,
		1804	STORE, 47664389423104, 47664389447679,
		1805	STORE, 47664389447680, 47664389558271,
		1806	STORE, 47664389509120, 47664389558271,
		1807	STORE, 47664389447680, 47664389509119,
		1808	ERASE, 47664389447680, 47664389447680,
		1809	STORE, 47664389447680, 47664389509119,
		1810	STORE, 47664389533696, 47664389558271,
		1811	STORE, 47664389509120, 47664389533695,
		1812	ERASE, 47664389509120, 47664389509120,
		1813	STORE, 47664389509120, 47664389558271,
		1814	ERASE, 47664389509120, 47664389509120,
		1815	STORE, 47664389509120, 47664389533695,
		1816	STORE, 47664389533696, 47664389558271,
		1817	STORE, 47664389541888, 47664389558271,
		1818	STORE, 47664389533696, 47664389541887,
		1819	ERASE, 47664389533696, 47664389533696,
		1820	STORE, 47664389533696, 47664389541887,
		1821	ERASE, 47664389541888, 47664389541888,
		1822	STORE, 47664389541888, 47664389558271,
		1823	STORE, 47664389558272, 47664389578751,
		1824	ERASE, 47664389558272, 47664389558272,
		1825	STORE, 47664389558272, 47664389562367,
		1826	STORE, 47664389562368, 47664389578751,
		1827	STORE, 47664389566464, 47664389578751,
		1828	STORE, 47664389562368, 47664389566463,
		1829	ERASE, 47664389562368, 47664389562368,
		1830	STORE, 47664389562368, 47664389566463,
		1831	STORE, 47664389570560, 47664389578751,
		1832	STORE, 47664389566464, 47664389570559,
		1833	ERASE, 47664389566464, 47664389566464,
		1834	STORE, 47664389566464, 47664389578751,
		1835	ERASE, 47664389566464, 47664389566464,
		1836	STORE, 47664389566464, 47664389570559,
		1837	STORE, 47664389570560, 47664389578751,
		1838	ERASE, 47664389570560, 47664389570560,
		1839	STORE, 47664389570560, 47664389578751,
		1840	STORE, 47664389578752, 47664389586943,
		1841	ERASE, 47664389382144, 47664389382144,
		1842	STORE, 47664389382144, 47664389398527,
		1843	STORE, 47664389398528, 47664389406719,
		1844	ERASE, 47664389570560, 47664389570560,
		1845	STORE, 47664389570560, 47664389574655,
		1846	STORE, 47664389574656, 47664389578751,
		1847	ERASE, 47664389533696, 47664389533696,
		1848	STORE, 47664389533696, 47664389537791,
		1849	STORE, 47664389537792, 47664389541887,
		1850	ERASE, 47664387362816, 47664387362816,
		1851	STORE, 47664387362816, 47664387559423,
		1852	STORE, 47664387559424, 47664387567615,
		1853	ERASE, 47664384524288, 47664384524288,
		1854	STORE, 47664384524288, 47664384528383,
		1855	STORE, 47664384528384, 47664384532479,
		1856	ERASE, 94071213555712, 94071213555712,
		1857	STORE, 94071213555712, 94071213563903,
		1858	STORE, 94071213563904, 94071213567999,
		1859	ERASE, 139968410804224, 139968410804224,
		1860	STORE, 139968410804224, 139968410808319,
		1861	STORE, 139968410808320, 139968410812415,
		1862	ERASE, 47664384352256, 47664384352256,
		1863	STORE, 94071244402688, 94071244537855,
		1864	STORE, 140737488347136, 140737488351231,
		1865	STORE, 140728271503360, 140737488351231,
		1866	ERASE, 140728271503360, 140728271503360,
		1867	STORE, 140728271503360, 140728271507455,
		1868	STORE, 94410361982976, 94410362155007,
		1869	ERASE, 94410361982976, 94410361982976,
		1870	STORE, 94410361982976, 94410361999359,
		1871	STORE, 94410361999360, 94410362155007,
		1872	ERASE, 94410361999360, 94410361999360,
		1873	STORE, 94410361999360, 94410362101759,
		1874	STORE, 94410362101760, 94410362142719,
		1875	STORE, 94410362142720, 94410362155007,
		1876	STORE, 140351953997824, 140351954169855,
		1877	ERASE, 140351953997824, 140351953997824,
		1878	STORE, 140351953997824, 140351954001919,
		1879	STORE, 140351954001920, 140351954169855,
		1880	ERASE, 140351954001920, 140351954001920,
		1881	STORE, 140351954001920, 140351954124799,
		1882	STORE, 140351954124800, 140351954157567,
		1883	STORE, 140351954157568, 140351954165759,
		1884	STORE, 140351954165760, 140351954169855,
		1885	STORE, 140728272429056, 140728272433151,
		1886	STORE, 140728272416768, 140728272429055,
		1887	STORE, 47280840998912, 47280841007103,
		1888	STORE, 47280841007104, 47280841015295,
		1889	STORE, 47280841015296, 47280841179135,
		1890	ERASE, 47280841015296, 47280841015296,
		1891	STORE, 47280841015296, 47280841027583,
		1892	STORE, 47280841027584, 47280841179135,
		1893	STORE, 47280841125888, 47280841179135,
		1894	STORE, 47280841027584, 47280841125887,
		1895	ERASE, 47280841027584, 47280841027584,
		1896	STORE, 47280841027584, 47280841125887,
		1897	STORE, 47280841170944, 47280841179135,
		1898	STORE, 47280841125888, 47280841170943,
		1899	ERASE, 47280841125888, 47280841125888,
		1900	STORE, 47280841125888, 47280841179135,
		1901	ERASE, 47280841125888, 47280841125888,
		1902	STORE, 47280841125888, 47280841170943,
		1903	STORE, 47280841170944, 47280841179135,
		1904	ERASE, 47280841170944, 47280841170944,
		1905	STORE, 47280841170944, 47280841179135,
		1906	STORE, 47280841179136, 47280844230655,
		1907	STORE, 47280841723904, 47280844230655,
		1908	STORE, 47280841179136, 47280841723903,
		1909	ERASE, 47280841723904, 47280841723904,
		1910	STORE, 47280841723904, 47280844009471,
		1911	STORE, 47280844009472, 47280844230655,
		1912	STORE, 47280843419648, 47280844009471,
		1913	STORE, 47280841723904, 47280843419647,
		1914	ERASE, 47280841723904, 47280841723904,
		1915	STORE, 47280841723904, 47280843419647,
		1916	STORE, 47280844005376, 47280844009471,
		1917	STORE, 47280843419648, 47280844005375,
		1918	ERASE, 47280843419648, 47280843419648,
		1919	STORE, 47280843419648, 47280844005375,
		1920	STORE, 47280844214272, 47280844230655,
		1921	STORE, 47280844009472, 47280844214271,
		1922	ERASE, 47280844009472, 47280844009472,
		1923	STORE, 47280844009472, 47280844214271,
		1924	ERASE, 47280844214272, 47280844214272,
		1925	STORE, 47280844214272, 47280844230655,
		1926	STORE, 47280844230656, 47280846069759,
		1927	STORE, 47280844369920, 47280846069759,
		1928	STORE, 47280844230656, 47280844369919,
		1929	ERASE, 47280844369920, 47280844369920,
		1930	STORE, 47280844369920, 47280846028799,
		1931	STORE, 47280846028800, 47280846069759,
		1932	STORE, 47280845713408, 47280846028799,
		1933	STORE, 47280844369920, 47280845713407,
		1934	ERASE, 47280844369920, 47280844369920,
		1935	STORE, 47280844369920, 47280845713407,
		1936	STORE, 47280846024704, 47280846028799,
		1937	STORE, 47280845713408, 47280846024703,
		1938	ERASE, 47280845713408, 47280845713408,
		1939	STORE, 47280845713408, 47280846024703,
		1940	STORE, 47280846053376, 47280846069759,
		1941	STORE, 47280846028800, 47280846053375,
		1942	ERASE, 47280846028800, 47280846028800,
		1943	STORE, 47280846028800, 47280846053375,
		1944	ERASE, 47280846053376, 47280846053376,
		1945	STORE, 47280846053376, 47280846069759,
		1946	STORE, 47280846069760, 47280846204927,
		1947	ERASE, 47280846069760, 47280846069760,
		1948	STORE, 47280846069760, 47280846094335,
		1949	STORE, 47280846094336, 47280846204927,
		1950	STORE, 47280846155776, 47280846204927,
		1951	STORE, 47280846094336, 47280846155775,
		1952	ERASE, 47280846094336, 47280846094336,
		1953	STORE, 47280846094336, 47280846155775,
		1954	STORE, 47280846180352, 47280846204927,
		1955	STORE, 47280846155776, 47280846180351,
		1956	ERASE, 47280846155776, 47280846155776,
		1957	STORE, 47280846155776, 47280846204927,
		1958	ERASE, 47280846155776, 47280846155776,
		1959	STORE, 47280846155776, 47280846180351,
		1960	STORE, 47280846180352, 47280846204927,
		1961	STORE, 47280846188544, 47280846204927,
		1962	STORE, 47280846180352, 47280846188543,
		1963	ERASE, 47280846180352, 47280846180352,
		1964	STORE, 47280846180352, 47280846188543,
		1965	ERASE, 47280846188544, 47280846188544,
		1966	STORE, 47280846188544, 47280846204927,
		1967	STORE, 47280846204928, 47280846225407,
		1968	ERASE, 47280846204928, 47280846204928,
		1969	STORE, 47280846204928, 47280846209023,
		1970	STORE, 47280846209024, 47280846225407,
		1971	STORE, 47280846213120, 47280846225407,
		1972	STORE, 47280846209024, 47280846213119,
		1973	ERASE, 47280846209024, 47280846209024,
		1974	STORE, 47280846209024, 47280846213119,
		1975	STORE, 47280846217216, 47280846225407,
		1976	STORE, 47280846213120, 47280846217215,
		1977	ERASE, 47280846213120, 47280846213120,
		1978	STORE, 47280846213120, 47280846225407,
		1979	ERASE, 47280846213120, 47280846213120,
		1980	STORE, 47280846213120, 47280846217215,
		1981	STORE, 47280846217216, 47280846225407,
		1982	ERASE, 47280846217216, 47280846217216,
		1983	STORE, 47280846217216, 47280846225407,
		1984	STORE, 47280846225408, 47280846233599,
		1985	ERASE, 47280846028800, 47280846028800,
		1986	STORE, 47280846028800, 47280846045183,
		1987	STORE, 47280846045184, 47280846053375,
		1988	ERASE, 47280846217216, 47280846217216,
		1989	STORE, 47280846217216, 47280846221311,
		1990	STORE, 47280846221312, 47280846225407,
		1991	ERASE, 47280846180352, 47280846180352,
		1992	STORE, 47280846180352, 47280846184447,
		1993	STORE, 47280846184448, 47280846188543,
		1994	ERASE, 47280844009472, 47280844009472,
		1995	STORE, 47280844009472, 47280844206079,
		1996	STORE, 47280844206080, 47280844214271,
		1997	ERASE, 47280841170944, 47280841170944,
		1998	STORE, 47280841170944, 47280841175039,
		1999	STORE, 47280841175040, 47280841179135,
		2000	ERASE, 94410362142720, 94410362142720,
		2001	STORE, 94410362142720, 94410362150911,
		2002	STORE, 94410362150912, 94410362155007,
		2003	ERASE, 140351954157568, 140351954157568,
		2004	STORE, 140351954157568, 140351954161663,
		2005	STORE, 140351954161664, 140351954165759,
		2006	ERASE, 47280840998912, 47280840998912,
		2007	STORE, 94410379456512, 94410379591679,
		2008	STORE, 140737488347136, 140737488351231,
		2009	STORE, 140732946362368, 140737488351231,
		2010	ERASE, 140732946362368, 140732946362368,
		2011	STORE, 140732946362368, 140732946366463,
		2012	STORE, 94352937934848, 94352938106879,
		2013	ERASE, 94352937934848, 94352937934848,
		2014	STORE, 94352937934848, 94352937951231,
		2015	STORE, 94352937951232, 94352938106879,
		2016	ERASE, 94352937951232, 94352937951232,
		2017	STORE, 94352937951232, 94352938053631,
		2018	STORE, 94352938053632, 94352938094591,
		2019	STORE, 94352938094592, 94352938106879,
		2020	STORE, 140595518742528, 140595518914559,
		2021	ERASE, 140595518742528, 140595518742528,
		2022	STORE, 140595518742528, 140595518746623,
		2023	STORE, 140595518746624, 140595518914559,
		2024	ERASE, 140595518746624, 140595518746624,
		2025	STORE, 140595518746624, 140595518869503,
		2026	STORE, 140595518869504, 140595518902271,
		2027	STORE, 140595518902272, 140595518910463,
		2028	STORE, 140595518910464, 140595518914559,
		2029	STORE, 140732947468288, 140732947472383,
		2030	STORE, 140732947456000, 140732947468287,
		2031	STORE, 47037276254208, 47037276262399,
		2032	STORE, 47037276262400, 47037276270591,
		2033	STORE, 47037276270592, 47037276434431,
		2034	ERASE, 47037276270592, 47037276270592,
		2035	STORE, 47037276270592, 47037276282879,
		2036	STORE, 47037276282880, 47037276434431,
		2037	STORE, 47037276381184, 47037276434431,
		2038	STORE, 47037276282880, 47037276381183,
		2039	ERASE, 47037276282880, 47037276282880,
		2040	STORE, 47037276282880, 47037276381183,
		2041	STORE, 47037276426240, 47037276434431,
		2042	STORE, 47037276381184, 47037276426239,
		2043	ERASE, 47037276381184, 47037276381184,
		2044	STORE, 47037276381184, 47037276434431,
		2045	ERASE, 47037276381184, 47037276381184,
		2046	STORE, 47037276381184, 47037276426239,
		2047	STORE, 47037276426240, 47037276434431,
		2048	ERASE, 47037276426240, 47037276426240,
		2049	STORE, 47037276426240, 47037276434431,
		2050	STORE, 47037276434432, 47037279485951,
		2051	STORE, 47037276979200, 47037279485951,
		2052	STORE, 47037276434432, 47037276979199,
		2053	ERASE, 47037276979200, 47037276979200,
		2054	STORE, 47037276979200, 47037279264767,
		2055	STORE, 47037279264768, 47037279485951,
		2056	STORE, 47037278674944, 47037279264767,
		2057	STORE, 47037276979200, 47037278674943,
		2058	ERASE, 47037276979200, 47037276979200,
		2059	STORE, 47037276979200, 47037278674943,
		2060	STORE, 47037279260672, 47037279264767,
		2061	STORE, 47037278674944, 47037279260671,
		2062	ERASE, 47037278674944, 47037278674944,
		2063	STORE, 47037278674944, 47037279260671,
		2064	STORE, 47037279469568, 47037279485951,
		2065	STORE, 47037279264768, 47037279469567,
		2066	ERASE, 47037279264768, 47037279264768,
		2067	STORE, 47037279264768, 47037279469567,
		2068	ERASE, 47037279469568, 47037279469568,
		2069	STORE, 47037279469568, 47037279485951,
		2070	STORE, 47037279485952, 47037281325055,
		2071	STORE, 47037279625216, 47037281325055,
		2072	STORE, 47037279485952, 47037279625215,
		2073	ERASE, 47037279625216, 47037279625216,
		2074	STORE, 47037279625216, 47037281284095,
		2075	STORE, 47037281284096, 47037281325055,
		2076	STORE, 47037280968704, 47037281284095,
		2077	STORE, 47037279625216, 47037280968703,
		2078	ERASE, 47037279625216, 47037279625216,
		2079	STORE, 47037279625216, 47037280968703,
		2080	STORE, 47037281280000, 47037281284095,
		2081	STORE, 47037280968704, 47037281279999,
		2082	ERASE, 47037280968704, 47037280968704,
		2083	STORE, 47037280968704, 47037281279999,
		2084	STORE, 47037281308672, 47037281325055,
		2085	STORE, 47037281284096, 47037281308671,
		2086	ERASE, 47037281284096, 47037281284096,
		2087	STORE, 47037281284096, 47037281308671,
		2088	ERASE, 47037281308672, 47037281308672,
		2089	STORE, 47037281308672, 47037281325055,
		2090	STORE, 47037281325056, 47037281460223,
		2091	ERASE, 47037281325056, 47037281325056,
		2092	STORE, 47037281325056, 47037281349631,
		2093	STORE, 47037281349632, 47037281460223,
		2094	STORE, 47037281411072, 47037281460223,
		2095	STORE, 47037281349632, 47037281411071,
		2096	ERASE, 47037281349632, 47037281349632,
		2097	STORE, 47037281349632, 47037281411071,
		2098	STORE, 47037281435648, 47037281460223,
		2099	STORE, 47037281411072, 47037281435647,
		2100	ERASE, 47037281411072, 47037281411072,
		2101	STORE, 47037281411072, 47037281460223,
		2102	ERASE, 47037281411072, 47037281411072,
		2103	STORE, 47037281411072, 47037281435647,
		2104	STORE, 47037281435648, 47037281460223,
		2105	STORE, 47037281443840, 47037281460223,
		2106	STORE, 47037281435648, 47037281443839,
		2107	ERASE, 47037281435648, 47037281435648,
		2108	STORE, 47037281435648, 47037281443839,
		2109	ERASE, 47037281443840, 47037281443840,
		2110	STORE, 47037281443840, 47037281460223,
		2111	STORE, 47037281460224, 47037281480703,
		2112	ERASE, 47037281460224, 47037281460224,
		2113	STORE, 47037281460224, 47037281464319,
		2114	STORE, 47037281464320, 47037281480703,
		2115	STORE, 47037281468416, 47037281480703,
		2116	STORE, 47037281464320, 47037281468415,
		2117	ERASE, 47037281464320, 47037281464320,
		2118	STORE, 47037281464320, 47037281468415,
		2119	STORE, 47037281472512, 47037281480703,
		2120	STORE, 47037281468416, 47037281472511,
		2121	ERASE, 47037281468416, 47037281468416,
		2122	STORE, 47037281468416, 47037281480703,
		2123	ERASE, 47037281468416, 47037281468416,
		2124	STORE, 47037281468416, 47037281472511,
		2125	STORE, 47037281472512, 47037281480703,
		2126	ERASE, 47037281472512, 47037281472512,
		2127	STORE, 47037281472512, 47037281480703,
		2128	STORE, 47037281480704, 47037281488895,
		2129	ERASE, 47037281284096, 47037281284096,
		2130	STORE, 47037281284096, 47037281300479,
		2131	STORE, 47037281300480, 47037281308671,
		2132	ERASE, 47037281472512, 47037281472512,
		2133	STORE, 47037281472512, 47037281476607,
		2134	STORE, 47037281476608, 47037281480703,
		2135	ERASE, 47037281435648, 47037281435648,
		2136	STORE, 47037281435648, 47037281439743,
		2137	STORE, 47037281439744, 47037281443839,
		2138	ERASE, 47037279264768, 47037279264768,
		2139	STORE, 47037279264768, 47037279461375,
		2140	STORE, 47037279461376, 47037279469567,
		2141	ERASE, 47037276426240, 47037276426240,
		2142	STORE, 47037276426240, 47037276430335,
		2143	STORE, 47037276430336, 47037276434431,
		2144	ERASE, 94352938094592, 94352938094592,
		2145	STORE, 94352938094592, 94352938102783,
		2146	STORE, 94352938102784, 94352938106879,
		2147	ERASE, 140595518902272, 140595518902272,
		2148	STORE, 140595518902272, 140595518906367,
		2149	STORE, 140595518906368, 140595518910463,
		2150	ERASE, 47037276254208, 47037276254208,
		2151	STORE, 94352938438656, 94352938573823,
		2152	STORE, 140737488347136, 140737488351231,
		2153	STORE, 140733506027520, 140737488351231,
		2154	ERASE, 140733506027520, 140733506027520,
		2155	STORE, 140733506027520, 140733506031615,
		2156	STORE, 94150123073536, 94150123245567,
		2157	ERASE, 94150123073536, 94150123073536,
		2158	STORE, 94150123073536, 94150123089919,
		2159	STORE, 94150123089920, 94150123245567,
		2160	ERASE, 94150123089920, 94150123089920,
		2161	STORE, 94150123089920, 94150123192319,
		2162	STORE, 94150123192320, 94150123233279,
		2163	STORE, 94150123233280, 94150123245567,
		2164	STORE, 140081290375168, 140081290547199,
		2165	ERASE, 140081290375168, 140081290375168,
		2166	STORE, 140081290375168, 140081290379263,
		2167	STORE, 140081290379264, 140081290547199,
		2168	ERASE, 140081290379264, 140081290379264,
		2169	STORE, 140081290379264, 140081290502143,
		2170	STORE, 140081290502144, 140081290534911,
		2171	STORE, 140081290534912, 140081290543103,
		2172	STORE, 140081290543104, 140081290547199,
		2173	STORE, 140733506707456, 140733506711551,
		2174	STORE, 140733506695168, 140733506707455,
		2175	STORE, 47551504621568, 47551504629759,
		2176	STORE, 47551504629760, 47551504637951,
		2177	STORE, 47551504637952, 47551504801791,
		2178	ERASE, 47551504637952, 47551504637952,
		2179	STORE, 47551504637952, 47551504650239,
		2180	STORE, 47551504650240, 47551504801791,
		2181	STORE, 47551504748544, 47551504801791,
		2182	STORE, 47551504650240, 47551504748543,
		2183	ERASE, 47551504650240, 47551504650240,
		2184	STORE, 47551504650240, 47551504748543,
		2185	STORE, 47551504793600, 47551504801791,
		2186	STORE, 47551504748544, 47551504793599,
		2187	ERASE, 47551504748544, 47551504748544,
		2188	STORE, 47551504748544, 47551504801791,
		2189	ERASE, 47551504748544, 47551504748544,
		2190	STORE, 47551504748544, 47551504793599,
		2191	STORE, 47551504793600, 47551504801791,
		2192	ERASE, 47551504793600, 47551504793600,
		2193	STORE, 47551504793600, 47551504801791,
		2194	STORE, 47551504801792, 47551507853311,
		2195	STORE, 47551505346560, 47551507853311,
		2196	STORE, 47551504801792, 47551505346559,
		2197	ERASE, 47551505346560, 47551505346560,
		2198	STORE, 47551505346560, 47551507632127,
		2199	STORE, 47551507632128, 47551507853311,
		2200	STORE, 47551507042304, 47551507632127,
		2201	STORE, 47551505346560, 47551507042303,
		2202	ERASE, 47551505346560, 47551505346560,
		2203	STORE, 47551505346560, 47551507042303,
		2204	STORE, 47551507628032, 47551507632127,
		2205	STORE, 47551507042304, 47551507628031,
		2206	ERASE, 47551507042304, 47551507042304,
		2207	STORE, 47551507042304, 47551507628031,
		2208	STORE, 47551507836928, 47551507853311,
		2209	STORE, 47551507632128, 47551507836927,
		2210	ERASE, 47551507632128, 47551507632128,
		2211	STORE, 47551507632128, 47551507836927,
		2212	ERASE, 47551507836928, 47551507836928,
		2213	STORE, 47551507836928, 47551507853311,
		2214	STORE, 47551507853312, 47551509692415,
		2215	STORE, 47551507992576, 47551509692415,
		2216	STORE, 47551507853312, 47551507992575,
		2217	ERASE, 47551507992576, 47551507992576,
		2218	STORE, 47551507992576, 47551509651455,
		2219	STORE, 47551509651456, 47551509692415,
		2220	STORE, 47551509336064, 47551509651455,
		2221	STORE, 47551507992576, 47551509336063,
		2222	ERASE, 47551507992576, 47551507992576,
		2223	STORE, 47551507992576, 47551509336063,
		2224	STORE, 47551509647360, 47551509651455,
		2225	STORE, 47551509336064, 47551509647359,
		2226	ERASE, 47551509336064, 47551509336064,
		2227	STORE, 47551509336064, 47551509647359,
		2228	STORE, 47551509676032, 47551509692415,
		2229	STORE, 47551509651456, 47551509676031,
		2230	ERASE, 47551509651456, 47551509651456,
		2231	STORE, 47551509651456, 47551509676031,
		2232	ERASE, 47551509676032, 47551509676032,
		2233	STORE, 47551509676032, 47551509692415,
		2234	STORE, 47551509692416, 47551509827583,
		2235	ERASE, 47551509692416, 47551509692416,
		2236	STORE, 47551509692416, 47551509716991,
		2237	STORE, 47551509716992, 47551509827583,
		2238	STORE, 47551509778432, 47551509827583,
		2239	STORE, 47551509716992, 47551509778431,
		2240	ERASE, 47551509716992, 47551509716992,
		2241	STORE, 47551509716992, 47551509778431,
		2242	STORE, 47551509803008, 47551509827583,
		2243	STORE, 47551509778432, 47551509803007,
		2244	ERASE, 47551509778432, 47551509778432,
		2245	STORE, 47551509778432, 47551509827583,
		2246	ERASE, 47551509778432, 47551509778432,
		2247	STORE, 47551509778432, 47551509803007,
		2248	STORE, 47551509803008, 47551509827583,
		2249	STORE, 47551509811200, 47551509827583,
		2250	STORE, 47551509803008, 47551509811199,
		2251	ERASE, 47551509803008, 47551509803008,
		2252	STORE, 47551509803008, 47551509811199,
		2253	ERASE, 47551509811200, 47551509811200,
		2254	STORE, 47551509811200, 47551509827583,
		2255	STORE, 47551509827584, 47551509848063,
		2256	ERASE, 47551509827584, 47551509827584,
		2257	STORE, 47551509827584, 47551509831679,
		2258	STORE, 47551509831680, 47551509848063,
		2259	STORE, 47551509835776, 47551509848063,
		2260	STORE, 47551509831680, 47551509835775,
		2261	ERASE, 47551509831680, 47551509831680,
		2262	STORE, 47551509831680, 47551509835775,
		2263	STORE, 47551509839872, 47551509848063,
		2264	STORE, 47551509835776, 47551509839871,
		2265	ERASE, 47551509835776, 47551509835776,
		2266	STORE, 47551509835776, 47551509848063,
		2267	ERASE, 47551509835776, 47551509835776,
		2268	STORE, 47551509835776, 47551509839871,
		2269	STORE, 47551509839872, 47551509848063,
		2270	ERASE, 47551509839872, 47551509839872,
		2271	STORE, 47551509839872, 47551509848063,
		2272	STORE, 47551509848064, 47551509856255,
		2273	ERASE, 47551509651456, 47551509651456,
		2274	STORE, 47551509651456, 47551509667839,
		2275	STORE, 47551509667840, 47551509676031,
		2276	ERASE, 47551509839872, 47551509839872,
		2277	STORE, 47551509839872, 47551509843967,
		2278	STORE, 47551509843968, 47551509848063,
		2279	ERASE, 47551509803008, 47551509803008,
		2280	STORE, 47551509803008, 47551509807103,
		2281	STORE, 47551509807104, 47551509811199,
		2282	ERASE, 47551507632128, 47551507632128,
		2283	STORE, 47551507632128, 47551507828735,
		2284	STORE, 47551507828736, 47551507836927,
		2285	ERASE, 47551504793600, 47551504793600,
		2286	STORE, 47551504793600, 47551504797695,
		2287	STORE, 47551504797696, 47551504801791,
		2288	ERASE, 94150123233280, 94150123233280,
		2289	STORE, 94150123233280, 94150123241471,
		2290	STORE, 94150123241472, 94150123245567,
		2291	ERASE, 140081290534912, 140081290534912,
		2292	STORE, 140081290534912, 140081290539007,
		2293	STORE, 140081290539008, 140081290543103,
		2294	ERASE, 47551504621568, 47551504621568,
		2295	STORE, 94150148112384, 94150148247551,
		2296	STORE, 140737488347136, 140737488351231,
		2297	STORE, 140734389334016, 140737488351231,
		2298	ERASE, 140734389334016, 140734389334016,
		2299	STORE, 140734389334016, 140734389338111,
		2300	STORE, 94844636606464, 94844636778495,
		2301	ERASE, 94844636606464, 94844636606464,
		2302	STORE, 94844636606464, 94844636622847,
		2303	STORE, 94844636622848, 94844636778495,
		2304	ERASE, 94844636622848, 94844636622848,
		2305	STORE, 94844636622848, 94844636725247,
		2306	STORE, 94844636725248, 94844636766207,
		2307	STORE, 94844636766208, 94844636778495,
		2308	STORE, 139922765217792, 139922765389823,
		2309	ERASE, 139922765217792, 139922765217792,
		2310	STORE, 139922765217792, 139922765221887,
		2311	STORE, 139922765221888, 139922765389823,
		2312	ERASE, 139922765221888, 139922765221888,
		2313	STORE, 139922765221888, 139922765344767,
		2314	STORE, 139922765344768, 139922765377535,
		2315	STORE, 139922765377536, 139922765385727,
		2316	STORE, 139922765385728, 139922765389823,
		2317	STORE, 140734389678080, 140734389682175,
		2318	STORE, 140734389665792, 140734389678079,
		2319	STORE, 47710029778944, 47710029787135,
		2320	STORE, 47710029787136, 47710029795327,
		2321	STORE, 47710029795328, 47710029959167,
		2322	ERASE, 47710029795328, 47710029795328,
		2323	STORE, 47710029795328, 47710029807615,
		2324	STORE, 47710029807616, 47710029959167,
		2325	STORE, 47710029905920, 47710029959167,
		2326	STORE, 47710029807616, 47710029905919,
		2327	ERASE, 47710029807616, 47710029807616,
		2328	STORE, 47710029807616, 47710029905919,
		2329	STORE, 47710029950976, 47710029959167,
		2330	STORE, 47710029905920, 47710029950975,
		2331	ERASE, 47710029905920, 47710029905920,
		2332	STORE, 47710029905920, 47710029959167,
		2333	ERASE, 47710029905920, 47710029905920,
		2334	STORE, 47710029905920, 47710029950975,
		2335	STORE, 47710029950976, 47710029959167,
		2336	ERASE, 47710029950976, 47710029950976,
		2337	STORE, 47710029950976, 47710029959167,
		2338	STORE, 47710029959168, 47710033010687,
		2339	STORE, 47710030503936, 47710033010687,
		2340	STORE, 47710029959168, 47710030503935,
		2341	ERASE, 47710030503936, 47710030503936,
		2342	STORE, 47710030503936, 47710032789503,
		2343	STORE, 47710032789504, 47710033010687,
		2344	STORE, 47710032199680, 47710032789503,
		2345	STORE, 47710030503936, 47710032199679,
		2346	ERASE, 47710030503936, 47710030503936,
		2347	STORE, 47710030503936, 47710032199679,
		2348	STORE, 47710032785408, 47710032789503,
		2349	STORE, 47710032199680, 47710032785407,
		2350	ERASE, 47710032199680, 47710032199680,
		2351	STORE, 47710032199680, 47710032785407,
		2352	STORE, 47710032994304, 47710033010687,
		2353	STORE, 47710032789504, 47710032994303,
		2354	ERASE, 47710032789504, 47710032789504,
		2355	STORE, 47710032789504, 47710032994303,
		2356	ERASE, 47710032994304, 47710032994304,
		2357	STORE, 47710032994304, 47710033010687,
		2358	STORE, 47710033010688, 47710034849791,
		2359	STORE, 47710033149952, 47710034849791,
		2360	STORE, 47710033010688, 47710033149951,
		2361	ERASE, 47710033149952, 47710033149952,
		2362	STORE, 47710033149952, 47710034808831,
		2363	STORE, 47710034808832, 47710034849791,
		2364	STORE, 47710034493440, 47710034808831,
		2365	STORE, 47710033149952, 47710034493439,
		2366	ERASE, 47710033149952, 47710033149952,
		2367	STORE, 47710033149952, 47710034493439,
		2368	STORE, 47710034804736, 47710034808831,
		2369	STORE, 47710034493440, 47710034804735,
		2370	ERASE, 47710034493440, 47710034493440,
		2371	STORE, 47710034493440, 47710034804735,
		2372	STORE, 47710034833408, 47710034849791,
		2373	STORE, 47710034808832, 47710034833407,
		2374	ERASE, 47710034808832, 47710034808832,
		2375	STORE, 47710034808832, 47710034833407,
		2376	ERASE, 47710034833408, 47710034833408,
		2377	STORE, 47710034833408, 47710034849791,
		2378	STORE, 47710034849792, 47710034984959,
		2379	ERASE, 47710034849792, 47710034849792,
		2380	STORE, 47710034849792, 47710034874367,
		2381	STORE, 47710034874368, 47710034984959,
		2382	STORE, 47710034935808, 47710034984959,
		2383	STORE, 47710034874368, 47710034935807,
		2384	ERASE, 47710034874368, 47710034874368,
		2385	STORE, 47710034874368, 47710034935807,
		2386	STORE, 47710034960384, 47710034984959,
		2387	STORE, 47710034935808, 47710034960383,
		2388	ERASE, 47710034935808, 47710034935808,
		2389	STORE, 47710034935808, 47710034984959,
		2390	ERASE, 47710034935808, 47710034935808,
		2391	STORE, 47710034935808, 47710034960383,
		2392	STORE, 47710034960384, 47710034984959,
		2393	STORE, 47710034968576, 47710034984959,
		2394	STORE, 47710034960384, 47710034968575,
		2395	ERASE, 47710034960384, 47710034960384,
		2396	STORE, 47710034960384, 47710034968575,
		2397	ERASE, 47710034968576, 47710034968576,
		2398	STORE, 47710034968576, 47710034984959,
		2399	STORE, 47710034984960, 47710035005439,
		2400	ERASE, 47710034984960, 47710034984960,
		2401	STORE, 47710034984960, 47710034989055,
		2402	STORE, 47710034989056, 47710035005439,
		2403	STORE, 47710034993152, 47710035005439,
		2404	STORE, 47710034989056, 47710034993151,
		2405	ERASE, 47710034989056, 47710034989056,
		2406	STORE, 47710034989056, 47710034993151,
		2407	STORE, 47710034997248, 47710035005439,
		2408	STORE, 47710034993152, 47710034997247,
		2409	ERASE, 47710034993152, 47710034993152,
		2410	STORE, 47710034993152, 47710035005439,
		2411	ERASE, 47710034993152, 47710034993152,
		2412	STORE, 47710034993152, 47710034997247,
		2413	STORE, 47710034997248, 47710035005439,
		2414	ERASE, 47710034997248, 47710034997248,
		2415	STORE, 47710034997248, 47710035005439,
		2416	STORE, 47710035005440, 47710035013631,
		2417	ERASE, 47710034808832, 47710034808832,
		2418	STORE, 47710034808832, 47710034825215,
		2419	STORE, 47710034825216, 47710034833407,
		2420	ERASE, 47710034997248, 47710034997248,
		2421	STORE, 47710034997248, 47710035001343,
		2422	STORE, 47710035001344, 47710035005439,
		2423	ERASE, 47710034960384, 47710034960384,
		2424	STORE, 47710034960384, 47710034964479,
		2425	STORE, 47710034964480, 47710034968575,
		2426	ERASE, 47710032789504, 47710032789504,
		2427	STORE, 47710032789504, 47710032986111,
		2428	STORE, 47710032986112, 47710032994303,
		2429	ERASE, 47710029950976, 47710029950976,
		2430	STORE, 47710029950976, 47710029955071,
		2431	STORE, 47710029955072, 47710029959167,
		2432	ERASE, 94844636766208, 94844636766208,
		2433	STORE, 94844636766208, 94844636774399,
		2434	STORE, 94844636774400, 94844636778495,
		2435	ERASE, 139922765377536, 139922765377536,
		2436	STORE, 139922765377536, 139922765381631,
		2437	STORE, 139922765381632, 139922765385727,
		2438	ERASE, 47710029778944, 47710029778944,
		2439	STORE, 94844641775616, 94844641910783,
		2440	STORE, 140737488347136, 140737488351231,
		2441	STORE, 140732213886976, 140737488351231,
		2442	ERASE, 140732213886976, 140732213886976,
		2443	STORE, 140732213886976, 140732213891071,
		2444	STORE, 94240508887040, 94240509059071,
		2445	ERASE, 94240508887040, 94240508887040,
		2446	STORE, 94240508887040, 94240508903423,
		2447	STORE, 94240508903424, 94240509059071,
		2448	ERASE, 94240508903424, 94240508903424,
		2449	STORE, 94240508903424, 94240509005823,
		2450	STORE, 94240509005824, 94240509046783,
		2451	STORE, 94240509046784, 94240509059071,
		2452	STORE, 140275106516992, 140275106689023,
		2453	ERASE, 140275106516992, 140275106516992,
		2454	STORE, 140275106516992, 140275106521087,
		2455	STORE, 140275106521088, 140275106689023,
		2456	ERASE, 140275106521088, 140275106521088,
		2457	STORE, 140275106521088, 140275106643967,
		2458	STORE, 140275106643968, 140275106676735,
		2459	STORE, 140275106676736, 140275106684927,
		2460	STORE, 140275106684928, 140275106689023,
		2461	STORE, 140732213977088, 140732213981183,
		2462	STORE, 140732213964800, 140732213977087,
		2463	STORE, 47357688479744, 47357688487935,
		2464	STORE, 47357688487936, 47357688496127,
		2465	STORE, 47357688496128, 47357688659967,
		2466	ERASE, 47357688496128, 47357688496128,
		2467	STORE, 47357688496128, 47357688508415,
		2468	STORE, 47357688508416, 47357688659967,
		2469	STORE, 47357688606720, 47357688659967,
		2470	STORE, 47357688508416, 47357688606719,
		2471	ERASE, 47357688508416, 47357688508416,
		2472	STORE, 47357688508416, 47357688606719,
		2473	STORE, 47357688651776, 47357688659967,
		2474	STORE, 47357688606720, 47357688651775,
		2475	ERASE, 47357688606720, 47357688606720,
		2476	STORE, 47357688606720, 47357688659967,
		2477	ERASE, 47357688606720, 47357688606720,
		2478	STORE, 47357688606720, 47357688651775,
		2479	STORE, 47357688651776, 47357688659967,
		2480	ERASE, 47357688651776, 47357688651776,
		2481	STORE, 47357688651776, 47357688659967,
		2482	STORE, 47357688659968, 47357691711487,
		2483	STORE, 47357689204736, 47357691711487,
		2484	STORE, 47357688659968, 47357689204735,
		2485	ERASE, 47357689204736, 47357689204736,
		2486	STORE, 47357689204736, 47357691490303,
		2487	STORE, 47357691490304, 47357691711487,
		2488	STORE, 47357690900480, 47357691490303,
		2489	STORE, 47357689204736, 47357690900479,
		2490	ERASE, 47357689204736, 47357689204736,
		2491	STORE, 47357689204736, 47357690900479,
		2492	STORE, 47357691486208, 47357691490303,
		2493	STORE, 47357690900480, 47357691486207,
		2494	ERASE, 47357690900480, 47357690900480,
		2495	STORE, 47357690900480, 47357691486207,
		2496	STORE, 47357691695104, 47357691711487,
		2497	STORE, 47357691490304, 47357691695103,
		2498	ERASE, 47357691490304, 47357691490304,
		2499	STORE, 47357691490304, 47357691695103,
		2500	ERASE, 47357691695104, 47357691695104,
		2501	STORE, 47357691695104, 47357691711487,
		2502	STORE, 47357691711488, 47357693550591,
		2503	STORE, 47357691850752, 47357693550591,
		2504	STORE, 47357691711488, 47357691850751,
		2505	ERASE, 47357691850752, 47357691850752,
		2506	STORE, 47357691850752, 47357693509631,
		2507	STORE, 47357693509632, 47357693550591,
		2508	STORE, 47357693194240, 47357693509631,
		2509	STORE, 47357691850752, 47357693194239,
		2510	ERASE, 47357691850752, 47357691850752,
		2511	STORE, 47357691850752, 47357693194239,
		2512	STORE, 47357693505536, 47357693509631,
		2513	STORE, 47357693194240, 47357693505535,
		2514	ERASE, 47357693194240, 47357693194240,
		2515	STORE, 47357693194240, 47357693505535,
		2516	STORE, 47357693534208, 47357693550591,
		2517	STORE, 47357693509632, 47357693534207,
		2518	ERASE, 47357693509632, 47357693509632,
		2519	STORE, 47357693509632, 47357693534207,
		2520	ERASE, 47357693534208, 47357693534208,
		2521	STORE, 47357693534208, 47357693550591,
		2522	STORE, 47357693550592, 47357693685759,
		2523	ERASE, 47357693550592, 47357693550592,
		2524	STORE, 47357693550592, 47357693575167,
		2525	STORE, 47357693575168, 47357693685759,
		2526	STORE, 47357693636608, 47357693685759,
		2527	STORE, 47357693575168, 47357693636607,
		2528	ERASE, 47357693575168, 47357693575168,
		2529	STORE, 47357693575168, 47357693636607,
		2530	STORE, 47357693661184, 47357693685759,
		2531	STORE, 47357693636608, 47357693661183,
		2532	ERASE, 47357693636608, 47357693636608,
		2533	STORE, 47357693636608, 47357693685759,
		2534	ERASE, 47357693636608, 47357693636608,
		2535	STORE, 47357693636608, 47357693661183,
		2536	STORE, 47357693661184, 47357693685759,
		2537	STORE, 47357693669376, 47357693685759,
		2538	STORE, 47357693661184, 47357693669375,
		2539	ERASE, 47357693661184, 47357693661184,
		2540	STORE, 47357693661184, 47357693669375,
		2541	ERASE, 47357693669376, 47357693669376,
		2542	STORE, 47357693669376, 47357693685759,
		2543	STORE, 47357693685760, 47357693706239,
		2544	ERASE, 47357693685760, 47357693685760,
		2545	STORE, 47357693685760, 47357693689855,
		2546	STORE, 47357693689856, 47357693706239,
		2547	STORE, 47357693693952, 47357693706239,
		2548	STORE, 47357693689856, 47357693693951,
		2549	ERASE, 47357693689856, 47357693689856,
		2550	STORE, 47357693689856, 47357693693951,
		2551	STORE, 47357693698048, 47357693706239,
		2552	STORE, 47357693693952, 47357693698047,
		2553	ERASE, 47357693693952, 47357693693952,
		2554	STORE, 47357693693952, 47357693706239,
		2555	ERASE, 47357693693952, 47357693693952,
		2556	STORE, 47357693693952, 47357693698047,
		2557	STORE, 47357693698048, 47357693706239,
		2558	ERASE, 47357693698048, 47357693698048,
		2559	STORE, 47357693698048, 47357693706239,
		2560	STORE, 47357693706240, 47357693714431,
		2561	ERASE, 47357693509632, 47357693509632,
		2562	STORE, 47357693509632, 47357693526015,
		2563	STORE, 47357693526016, 47357693534207,
		2564	ERASE, 47357693698048, 47357693698048,
		2565	STORE, 47357693698048, 47357693702143,
		2566	STORE, 47357693702144, 47357693706239,
		2567	ERASE, 47357693661184, 47357693661184,
		2568	STORE, 47357693661184, 47357693665279,
		2569	STORE, 47357693665280, 47357693669375,
		2570	ERASE, 47357691490304, 47357691490304,
		2571	STORE, 47357691490304, 47357691686911,
		2572	STORE, 47357691686912, 47357691695103,
		2573	ERASE, 47357688651776, 47357688651776,
		2574	STORE, 47357688651776, 47357688655871,
		2575	STORE, 47357688655872, 47357688659967,
		2576	ERASE, 94240509046784, 94240509046784,
		2577	STORE, 94240509046784, 94240509054975,
		2578	STORE, 94240509054976, 94240509059071,
		2579	ERASE, 140275106676736, 140275106676736,
		2580	STORE, 140275106676736, 140275106680831,
		2581	STORE, 140275106680832, 140275106684927,
		2582	ERASE, 47357688479744, 47357688479744,
		2583	STORE, 94240518361088, 94240518496255,
		2584	STORE, 140737488347136, 140737488351231,
		2585	STORE, 140732688277504, 140737488351231,
		2586	ERASE, 140732688277504, 140732688277504,
		2587	STORE, 140732688277504, 140732688281599,
		2588	STORE, 94629171351552, 94629172064255,
		2589	ERASE, 94629171351552, 94629171351552,
		2590	STORE, 94629171351552, 94629171400703,
		2591	STORE, 94629171400704, 94629172064255,
		2592	ERASE, 94629171400704, 94629171400704,
		2593	STORE, 94629171400704, 94629171945471,
		2594	STORE, 94629171945472, 94629172043775,
		2595	STORE, 94629172043776, 94629172064255,
		2596	STORE, 139770707644416, 139770707816447,
		2597	ERASE, 139770707644416, 139770707644416,
		2598	STORE, 139770707644416, 139770707648511,
		2599	STORE, 139770707648512, 139770707816447,
		2600	ERASE, 139770707648512, 139770707648512,
		2601	STORE, 139770707648512, 139770707771391,
		2602	STORE, 139770707771392, 139770707804159,
		2603	STORE, 139770707804160, 139770707812351,
		2604	STORE, 139770707812352, 139770707816447,
		2605	STORE, 140732689121280, 140732689125375,
		2606	STORE, 140732689108992, 140732689121279,
		2607	STORE, 47862087352320, 47862087360511,
		2608	STORE, 47862087360512, 47862087368703,
		2609	STORE, 47862087368704, 47862087475199,
		2610	STORE, 47862087385088, 47862087475199,
		2611	STORE, 47862087368704, 47862087385087,
		2612	ERASE, 47862087385088, 47862087385088,
		2613	STORE, 47862087385088, 47862087458815,
		2614	STORE, 47862087458816, 47862087475199,
		2615	STORE, 47862087438336, 47862087458815,
		2616	STORE, 47862087385088, 47862087438335,
		2617	ERASE, 47862087385088, 47862087385088,
		2618	STORE, 47862087385088, 47862087438335,
		2619	STORE, 47862087454720, 47862087458815,
		2620	STORE, 47862087438336, 47862087454719,
		2621	ERASE, 47862087438336, 47862087438336,
		2622	STORE, 47862087438336, 47862087454719,
		2623	STORE, 47862087467008, 47862087475199,
		2624	STORE, 47862087458816, 47862087467007,
		2625	ERASE, 47862087458816, 47862087458816,
		2626	STORE, 47862087458816, 47862087467007,
		2627	ERASE, 47862087467008, 47862087467008,
		2628	STORE, 47862087467008, 47862087475199,
		2629	STORE, 47862087475200, 47862089314303,
		2630	STORE, 47862087614464, 47862089314303,
		2631	STORE, 47862087475200, 47862087614463,
		2632	ERASE, 47862087614464, 47862087614464,
		2633	STORE, 47862087614464, 47862089273343,
		2634	STORE, 47862089273344, 47862089314303,
		2635	STORE, 47862088957952, 47862089273343,
		2636	STORE, 47862087614464, 47862088957951,
		2637	ERASE, 47862087614464, 47862087614464,
		2638	STORE, 47862087614464, 47862088957951,
		2639	STORE, 47862089269248, 47862089273343,
		2640	STORE, 47862088957952, 47862089269247,
		2641	ERASE, 47862088957952, 47862088957952,
		2642	STORE, 47862088957952, 47862089269247,
		2643	STORE, 47862089297920, 47862089314303,
		2644	STORE, 47862089273344, 47862089297919,
		2645	ERASE, 47862089273344, 47862089273344,
		2646	STORE, 47862089273344, 47862089297919,
		2647	ERASE, 47862089297920, 47862089297920,
		2648	STORE, 47862089297920, 47862089314303,
		2649	STORE, 47862089297920, 47862089326591,
		2650	ERASE, 47862089273344, 47862089273344,
		2651	STORE, 47862089273344, 47862089289727,
		2652	STORE, 47862089289728, 47862089297919,
		2653	ERASE, 47862087458816, 47862087458816,
		2654	STORE, 47862087458816, 47862087462911,
		2655	STORE, 47862087462912, 47862087467007,
		2656	ERASE, 94629172043776, 94629172043776,
		2657	STORE, 94629172043776, 94629172060159,
		2658	STORE, 94629172060160, 94629172064255,
		2659	ERASE, 139770707804160, 139770707804160,
		2660	STORE, 139770707804160, 139770707808255,
		2661	STORE, 139770707808256, 139770707812351,
		2662	ERASE, 47862087352320, 47862087352320,
		2663	STORE, 94629197533184, 94629197668351,
		2664	STORE, 140737488347136, 140737488351231,
		2665	STORE, 140727540711424, 140737488351231,
		2666	ERASE, 140727540711424, 140727540711424,
		2667	STORE, 140727540711424, 140727540715519,
		2668	STORE, 94299865313280, 94299866025983,
		2669	ERASE, 94299865313280, 94299865313280,
		2670	STORE, 94299865313280, 94299865362431,
		2671	STORE, 94299865362432, 94299866025983,
		2672	ERASE, 94299865362432, 94299865362432,
		2673	STORE, 94299865362432, 94299865907199,
		2674	STORE, 94299865907200, 94299866005503,
		2675	STORE, 94299866005504, 94299866025983,
		2676	STORE, 140680268763136, 140680268935167,
		2677	ERASE, 140680268763136, 140680268763136,
		2678	STORE, 140680268763136, 140680268767231,
		2679	STORE, 140680268767232, 140680268935167,
		2680	ERASE, 140680268767232, 140680268767232,
		2681	STORE, 140680268767232, 140680268890111,
		2682	STORE, 140680268890112, 140680268922879,
		2683	STORE, 140680268922880, 140680268931071,
		2684	STORE, 140680268931072, 140680268935167,
		2685	STORE, 140727541424128, 140727541428223,
		2686	STORE, 140727541411840, 140727541424127,
		2687	STORE, 46952526233600, 46952526241791,
		2688	STORE, 46952526241792, 46952526249983,
		2689	STORE, 46952526249984, 46952526356479,
		2690	STORE, 46952526266368, 46952526356479,
		2691	STORE, 46952526249984, 46952526266367,
		2692	ERASE, 46952526266368, 46952526266368,
		2693	STORE, 46952526266368, 46952526340095,
		2694	STORE, 46952526340096, 46952526356479,
		2695	STORE, 46952526319616, 46952526340095,
		2696	STORE, 46952526266368, 46952526319615,
		2697	ERASE, 46952526266368, 46952526266368,
		2698	STORE, 46952526266368, 46952526319615,
		2699	STORE, 46952526336000, 46952526340095,
		2700	STORE, 46952526319616, 46952526335999,
		2701	ERASE, 46952526319616, 46952526319616,
		2702	STORE, 46952526319616, 46952526335999,
		2703	STORE, 46952526348288, 46952526356479,
		2704	STORE, 46952526340096, 46952526348287,
		2705	ERASE, 46952526340096, 46952526340096,
		2706	STORE, 46952526340096, 46952526348287,
		2707	ERASE, 46952526348288, 46952526348288,
		2708	STORE, 46952526348288, 46952526356479,
		2709	STORE, 46952526356480, 46952528195583,
		2710	STORE, 46952526495744, 46952528195583,
		2711	STORE, 46952526356480, 46952526495743,
		2712	ERASE, 46952526495744, 46952526495744,
		2713	STORE, 46952526495744, 46952528154623,
		2714	STORE, 46952528154624, 46952528195583,
		2715	STORE, 46952527839232, 46952528154623,
		2716	STORE, 46952526495744, 46952527839231,
		2717	ERASE, 46952526495744, 46952526495744,
		2718	STORE, 46952526495744, 46952527839231,
		2719	STORE, 46952528150528, 46952528154623,
		2720	STORE, 46952527839232, 46952528150527,
		2721	ERASE, 46952527839232, 46952527839232,
		2722	STORE, 46952527839232, 46952528150527,
		2723	STORE, 46952528179200, 46952528195583,
		2724	STORE, 46952528154624, 46952528179199,
		2725	ERASE, 46952528154624, 46952528154624,
		2726	STORE, 46952528154624, 46952528179199,
		2727	ERASE, 46952528179200, 46952528179200,
		2728	STORE, 46952528179200, 46952528195583,
		2729	STORE, 46952528179200, 46952528207871,
		2730	ERASE, 46952528154624, 46952528154624,
		2731	STORE, 46952528154624, 46952528171007,
		2732	STORE, 46952528171008, 46952528179199,
		2733	ERASE, 46952526340096, 46952526340096,
		2734	STORE, 46952526340096, 46952526344191,
		2735	STORE, 46952526344192, 46952526348287,
		2736	ERASE, 94299866005504, 94299866005504,
		2737	STORE, 94299866005504, 94299866021887,
		2738	STORE, 94299866021888, 94299866025983,
		2739	ERASE, 140680268922880, 140680268922880,
		2740	STORE, 140680268922880, 140680268926975,
		2741	STORE, 140680268926976, 140680268931071,
		2742	ERASE, 46952526233600, 46952526233600,
		2743	STORE, 140737488347136, 140737488351231,
		2744	STORE, 140722874793984, 140737488351231,
		2745	ERASE, 140722874793984, 140722874793984,
		2746	STORE, 140722874793984, 140722874798079,
		2747	STORE, 94448916213760, 94448916926463,
		2748	ERASE, 94448916213760, 94448916213760,
		2749	STORE, 94448916213760, 94448916262911,
		2750	STORE, 94448916262912, 94448916926463,
		2751	ERASE, 94448916262912, 94448916262912,
		2752	STORE, 94448916262912, 94448916807679,
		2753	STORE, 94448916807680, 94448916905983,
		2754	STORE, 94448916905984, 94448916926463,
		2755	STORE, 140389117046784, 140389117218815,
		2756	ERASE, 140389117046784, 140389117046784,
		2757	STORE, 140389117046784, 140389117050879,
		2758	STORE, 140389117050880, 140389117218815,
		2759	ERASE, 140389117050880, 140389117050880,
		2760	STORE, 140389117050880, 140389117173759,
		2761	STORE, 140389117173760, 140389117206527,
		2762	STORE, 140389117206528, 140389117214719,
		2763	STORE, 140389117214720, 140389117218815,
		2764	STORE, 140722875297792, 140722875301887,
		2765	STORE, 140722875285504, 140722875297791,
		2766	STORE, 47243677949952, 47243677958143,
		2767	STORE, 47243677958144, 47243677966335,
		2768	STORE, 47243677966336, 47243678072831,
		2769	STORE, 47243677982720, 47243678072831,
		2770	STORE, 47243677966336, 47243677982719,
		2771	ERASE, 47243677982720, 47243677982720,
		2772	STORE, 47243677982720, 47243678056447,
		2773	STORE, 47243678056448, 47243678072831,
		2774	STORE, 47243678035968, 47243678056447,
		2775	STORE, 47243677982720, 47243678035967,
		2776	ERASE, 47243677982720, 47243677982720,
		2777	STORE, 47243677982720, 47243678035967,
		2778	STORE, 47243678052352, 47243678056447,
		2779	STORE, 47243678035968, 47243678052351,
		2780	ERASE, 47243678035968, 47243678035968,
		2781	STORE, 47243678035968, 47243678052351,
		2782	STORE, 47243678064640, 47243678072831,
		2783	STORE, 47243678056448, 47243678064639,
		2784	ERASE, 47243678056448, 47243678056448,
		2785	STORE, 47243678056448, 47243678064639,
		2786	ERASE, 47243678064640, 47243678064640,
		2787	STORE, 47243678064640, 47243678072831,
		2788	STORE, 47243678072832, 47243679911935,
		2789	STORE, 47243678212096, 47243679911935,
		2790	STORE, 47243678072832, 47243678212095,
		2791	ERASE, 47243678212096, 47243678212096,
		2792	STORE, 47243678212096, 47243679870975,
		2793	STORE, 47243679870976, 47243679911935,
		2794	STORE, 47243679555584, 47243679870975,
		2795	STORE, 47243678212096, 47243679555583,
		2796	ERASE, 47243678212096, 47243678212096,
		2797	STORE, 47243678212096, 47243679555583,
		2798	STORE, 47243679866880, 47243679870975,
		2799	STORE, 47243679555584, 47243679866879,
		2800	ERASE, 47243679555584, 47243679555584,
		2801	STORE, 47243679555584, 47243679866879,
		2802	STORE, 47243679895552, 47243679911935,
		2803	STORE, 47243679870976, 47243679895551,
		2804	ERASE, 47243679870976, 47243679870976,
		2805	STORE, 47243679870976, 47243679895551,
		2806	ERASE, 47243679895552, 47243679895552,
		2807	STORE, 47243679895552, 47243679911935,
		2808	STORE, 47243679895552, 47243679924223,
		2809	ERASE, 47243679870976, 47243679870976,
		2810	STORE, 47243679870976, 47243679887359,
		2811	STORE, 47243679887360, 47243679895551,
		2812	ERASE, 47243678056448, 47243678056448,
		2813	STORE, 47243678056448, 47243678060543,
		2814	STORE, 47243678060544, 47243678064639,
		2815	ERASE, 94448916905984, 94448916905984,
		2816	STORE, 94448916905984, 94448916922367,
		2817	STORE, 94448916922368, 94448916926463,
		2818	ERASE, 140389117206528, 140389117206528,
		2819	STORE, 140389117206528, 140389117210623,
		2820	STORE, 140389117210624, 140389117214719,
		2821	ERASE, 47243677949952, 47243677949952,
		2822	STORE, 140737488347136, 140737488351231,
		2823	STORE, 140733068505088, 140737488351231,
		2824	ERASE, 140733068505088, 140733068505088,
		2825	STORE, 140733068505088, 140733068509183,
		2826	STORE, 94207145750528, 94207146463231,
		2827	ERASE, 94207145750528, 94207145750528,
		2828	STORE, 94207145750528, 94207145799679,
		2829	STORE, 94207145799680, 94207146463231,
		2830	ERASE, 94207145799680, 94207145799680,
		2831	STORE, 94207145799680, 94207146344447,
		2832	STORE, 94207146344448, 94207146442751,
		2833	STORE, 94207146442752, 94207146463231,
		2834	STORE, 140684504911872, 140684505083903,
		2835	ERASE, 140684504911872, 140684504911872,
		2836	STORE, 140684504911872, 140684504915967,
		2837	STORE, 140684504915968, 140684505083903,
		2838	ERASE, 140684504915968, 140684504915968,
		2839	STORE, 140684504915968, 140684505038847,
		2840	STORE, 140684505038848, 140684505071615,
		2841	STORE, 140684505071616, 140684505079807,
		2842	STORE, 140684505079808, 140684505083903,
		2843	STORE, 140733068607488, 140733068611583,
		2844	STORE, 140733068595200, 140733068607487,
		2845	STORE, 46948290084864, 46948290093055,
		2846	STORE, 46948290093056, 46948290101247,
		2847	STORE, 46948290101248, 46948290207743,
		2848	STORE, 46948290117632, 46948290207743,
		2849	STORE, 46948290101248, 46948290117631,
		2850	ERASE, 46948290117632, 46948290117632,
		2851	STORE, 46948290117632, 46948290191359,
		2852	STORE, 46948290191360, 46948290207743,
		2853	STORE, 46948290170880, 46948290191359,
		2854	STORE, 46948290117632, 46948290170879,
		2855	ERASE, 46948290117632, 46948290117632,
		2856	STORE, 46948290117632, 46948290170879,
		2857	STORE, 46948290187264, 46948290191359,
		2858	STORE, 46948290170880, 46948290187263,
		2859	ERASE, 46948290170880, 46948290170880,
		2860	STORE, 46948290170880, 46948290187263,
		2861	STORE, 46948290199552, 46948290207743,
		2862	STORE, 46948290191360, 46948290199551,
		2863	ERASE, 46948290191360, 46948290191360,
		2864	STORE, 46948290191360, 46948290199551,
		2865	ERASE, 46948290199552, 46948290199552,
		2866	STORE, 46948290199552, 46948290207743,
		2867	STORE, 46948290207744, 46948292046847,
		2868	STORE, 46948290347008, 46948292046847,
		2869	STORE, 46948290207744, 46948290347007,
		2870	ERASE, 46948290347008, 46948290347008,
		2871	STORE, 46948290347008, 46948292005887,
		2872	STORE, 46948292005888, 46948292046847,
		2873	STORE, 46948291690496, 46948292005887,
		2874	STORE, 46948290347008, 46948291690495,
		2875	ERASE, 46948290347008, 46948290347008,
		2876	STORE, 46948290347008, 46948291690495,
		2877	STORE, 46948292001792, 46948292005887,
		2878	STORE, 46948291690496, 46948292001791,
		2879	ERASE, 46948291690496, 46948291690496,
		2880	STORE, 46948291690496, 46948292001791,
		2881	STORE, 46948292030464, 46948292046847,
		2882	STORE, 46948292005888, 46948292030463,
		2883	ERASE, 46948292005888, 46948292005888,
		2884	STORE, 46948292005888, 46948292030463,
		2885	ERASE, 46948292030464, 46948292030464,
		2886	STORE, 46948292030464, 46948292046847,
		2887	STORE, 46948292030464, 46948292059135,
		2888	ERASE, 46948292005888, 46948292005888,
		2889	STORE, 46948292005888, 46948292022271,
		2890	STORE, 46948292022272, 46948292030463,
		2891	ERASE, 46948290191360, 46948290191360,
		2892	STORE, 46948290191360, 46948290195455,
		2893	STORE, 46948290195456, 46948290199551,
		2894	ERASE, 94207146442752, 94207146442752,
		2895	STORE, 94207146442752, 94207146459135,
		2896	STORE, 94207146459136, 94207146463231,
		2897	ERASE, 140684505071616, 140684505071616,
		2898	STORE, 140684505071616, 140684505075711,
		2899	STORE, 140684505075712, 140684505079807,
		2900	ERASE, 46948290084864, 46948290084864,
		2901	STORE, 140737488347136, 140737488351231,
		2902	STORE, 140726367158272, 140737488351231,
		2903	ERASE, 140726367158272, 140726367158272,
		2904	STORE, 140726367158272, 140726367162367,
		2905	STORE, 94436124106752, 94436124819455,
		2906	ERASE, 94436124106752, 94436124106752,
		2907	STORE, 94436124106752, 94436124155903,
		2908	STORE, 94436124155904, 94436124819455,
		2909	ERASE, 94436124155904, 94436124155904,
		2910	STORE, 94436124155904, 94436124700671,
		2911	STORE, 94436124700672, 94436124798975,
		2912	STORE, 94436124798976, 94436124819455,
		2913	STORE, 140049025044480, 140049025216511,
		2914	ERASE, 140049025044480, 140049025044480,
		2915	STORE, 140049025044480, 140049025048575,
		2916	STORE, 140049025048576, 140049025216511,
		2917	ERASE, 140049025048576, 140049025048576,
		2918	STORE, 140049025048576, 140049025171455,
		2919	STORE, 140049025171456, 140049025204223,
		2920	STORE, 140049025204224, 140049025212415,
		2921	STORE, 140049025212416, 140049025216511,
		2922	STORE, 140726367256576, 140726367260671,
		2923	STORE, 140726367244288, 140726367256575,
		2924	STORE, 47583769952256, 47583769960447,
		2925	STORE, 47583769960448, 47583769968639,
		2926	STORE, 47583769968640, 47583770075135,
		2927	STORE, 47583769985024, 47583770075135,
		2928	STORE, 47583769968640, 47583769985023,
		2929	ERASE, 47583769985024, 47583769985024,
		2930	STORE, 47583769985024, 47583770058751,
		2931	STORE, 47583770058752, 47583770075135,
		2932	STORE, 47583770038272, 47583770058751,
		2933	STORE, 47583769985024, 47583770038271,
		2934	ERASE, 47583769985024, 47583769985024,
		2935	STORE, 47583769985024, 47583770038271,
		2936	STORE, 47583770054656, 47583770058751,
		2937	STORE, 47583770038272, 47583770054655,
		2938	ERASE, 47583770038272, 47583770038272,
		2939	STORE, 47583770038272, 47583770054655,
		2940	STORE, 47583770066944, 47583770075135,
		2941	STORE, 47583770058752, 47583770066943,
		2942	ERASE, 47583770058752, 47583770058752,
		2943	STORE, 47583770058752, 47583770066943,
		2944	ERASE, 47583770066944, 47583770066944,
		2945	STORE, 47583770066944, 47583770075135,
		2946	STORE, 47583770075136, 47583771914239,
		2947	STORE, 47583770214400, 47583771914239,
		2948	STORE, 47583770075136, 47583770214399,
		2949	ERASE, 47583770214400, 47583770214400,
		2950	STORE, 47583770214400, 47583771873279,
		2951	STORE, 47583771873280, 47583771914239,
		2952	STORE, 47583771557888, 47583771873279,
		2953	STORE, 47583770214400, 47583771557887,
		2954	ERASE, 47583770214400, 47583770214400,
		2955	STORE, 47583770214400, 47583771557887,
		2956	STORE, 47583771869184, 47583771873279,
		2957	STORE, 47583771557888, 47583771869183,
		2958	ERASE, 47583771557888, 47583771557888,
		2959	STORE, 47583771557888, 47583771869183,
		2960	STORE, 47583771897856, 47583771914239,
		2961	STORE, 47583771873280, 47583771897855,
		2962	ERASE, 47583771873280, 47583771873280,
		2963	STORE, 47583771873280, 47583771897855,
		2964	ERASE, 47583771897856, 47583771897856,
		2965	STORE, 47583771897856, 47583771914239,
		2966	STORE, 47583771897856, 47583771926527,
		2967	ERASE, 47583771873280, 47583771873280,
		2968	STORE, 47583771873280, 47583771889663,
		2969	STORE, 47583771889664, 47583771897855,
		2970	ERASE, 47583770058752, 47583770058752,
		2971	STORE, 47583770058752, 47583770062847,
		2972	STORE, 47583770062848, 47583770066943,
		2973	ERASE, 94436124798976, 94436124798976,
		2974	STORE, 94436124798976, 94436124815359,
		2975	STORE, 94436124815360, 94436124819455,
		2976	ERASE, 140049025204224, 140049025204224,
		2977	STORE, 140049025204224, 140049025208319,
		2978	STORE, 140049025208320, 140049025212415,
		2979	ERASE, 47583769952256, 47583769952256,
		2980	STORE, 140737488347136, 140737488351231,
		2981	STORE, 140727116099584, 140737488351231,
		2982	ERASE, 140727116099584, 140727116099584,
		2983	STORE, 140727116099584, 140727116103679,
		2984	STORE, 94166319734784, 94166320447487,
		2985	ERASE, 94166319734784, 94166319734784,
		2986	STORE, 94166319734784, 94166319783935,
		2987	STORE, 94166319783936, 94166320447487,
		2988	ERASE, 94166319783936, 94166319783936,
		2989	STORE, 94166319783936, 94166320328703,
		2990	STORE, 94166320328704, 94166320427007,
		2991	STORE, 94166320427008, 94166320447487,
		2992	STORE, 139976559542272, 139976559714303,
		2993	ERASE, 139976559542272, 139976559542272,
		2994	STORE, 139976559542272, 139976559546367,
		2995	STORE, 139976559546368, 139976559714303,
		2996	ERASE, 139976559546368, 139976559546368,
		2997	STORE, 139976559546368, 139976559669247,
		2998	STORE, 139976559669248, 139976559702015,
		2999	STORE, 139976559702016, 139976559710207,
		3000	STORE, 139976559710208, 139976559714303,
		3001	STORE, 140727116222464, 140727116226559,
		3002	STORE, 140727116210176, 140727116222463,
		3003	STORE, 47656235454464, 47656235462655,
		3004	STORE, 47656235462656, 47656235470847,
		3005	STORE, 47656235470848, 47656235577343,
		3006	STORE, 47656235487232, 47656235577343,
		3007	STORE, 47656235470848, 47656235487231,
		3008	ERASE, 47656235487232, 47656235487232,
		3009	STORE, 47656235487232, 47656235560959,
		3010	STORE, 47656235560960, 47656235577343,
		3011	STORE, 47656235540480, 47656235560959,
		3012	STORE, 47656235487232, 47656235540479,
		3013	ERASE, 47656235487232, 47656235487232,
		3014	STORE, 47656235487232, 47656235540479,
		3015	STORE, 47656235556864, 47656235560959,
		3016	STORE, 47656235540480, 47656235556863,
		3017	ERASE, 47656235540480, 47656235540480,
		3018	STORE, 47656235540480, 47656235556863,
		3019	STORE, 47656235569152, 47656235577343,
		3020	STORE, 47656235560960, 47656235569151,
		3021	ERASE, 47656235560960, 47656235560960,
		3022	STORE, 47656235560960, 47656235569151,
		3023	ERASE, 47656235569152, 47656235569152,
		3024	STORE, 47656235569152, 47656235577343,
		3025	STORE, 47656235577344, 47656237416447,
		3026	STORE, 47656235716608, 47656237416447,
		3027	STORE, 47656235577344, 47656235716607,
		3028	ERASE, 47656235716608, 47656235716608,
		3029	STORE, 47656235716608, 47656237375487,
		3030	STORE, 47656237375488, 47656237416447,
		3031	STORE, 47656237060096, 47656237375487,
		3032	STORE, 47656235716608, 47656237060095,
		3033	ERASE, 47656235716608, 47656235716608,
		3034	STORE, 47656235716608, 47656237060095,
		3035	STORE, 47656237371392, 47656237375487,
		3036	STORE, 47656237060096, 47656237371391,
		3037	ERASE, 47656237060096, 47656237060096,
		3038	STORE, 47656237060096, 47656237371391,
		3039	STORE, 47656237400064, 47656237416447,
		3040	STORE, 47656237375488, 47656237400063,
		3041	ERASE, 47656237375488, 47656237375488,
		3042	STORE, 47656237375488, 47656237400063,
		3043	ERASE, 47656237400064, 47656237400064,
		3044	STORE, 47656237400064, 47656237416447,
		3045	STORE, 47656237400064, 47656237428735,
		3046	ERASE, 47656237375488, 47656237375488,
		3047	STORE, 47656237375488, 47656237391871,
		3048	STORE, 47656237391872, 47656237400063,
		3049	ERASE, 47656235560960, 47656235560960,
		3050	STORE, 47656235560960, 47656235565055,
		3051	STORE, 47656235565056, 47656235569151,
		3052	ERASE, 94166320427008, 94166320427008,
		3053	STORE, 94166320427008, 94166320443391,
		3054	STORE, 94166320443392, 94166320447487,
		3055	ERASE, 139976559702016, 139976559702016,
		3056	STORE, 139976559702016, 139976559706111,
		3057	STORE, 139976559706112, 139976559710207,
		3058	ERASE, 47656235454464, 47656235454464,
		3059	STORE, 94166332153856, 94166332289023,
		3060	STORE, 140737488347136, 140737488351231,
		3061	STORE, 140726412816384, 140737488351231,
		3062	ERASE, 140726412816384, 140726412816384,
		3063	STORE, 140726412816384, 140726412820479,
		3064	STORE, 94094884507648, 94094885220351,
		3065	ERASE, 94094884507648, 94094884507648,
		3066	STORE, 94094884507648, 94094884556799,
		3067	STORE, 94094884556800, 94094885220351,
		3068	ERASE, 94094884556800, 94094884556800,
		3069	STORE, 94094884556800, 94094885101567,
		3070	STORE, 94094885101568, 94094885199871,
		3071	STORE, 94094885199872, 94094885220351,
		3072	STORE, 139773773938688, 139773774110719,
		3073	ERASE, 139773773938688, 139773773938688,
		3074	STORE, 139773773938688, 139773773942783,
		3075	STORE, 139773773942784, 139773774110719,
		3076	ERASE, 139773773942784, 139773773942784,
		3077	STORE, 139773773942784, 139773774065663,
		3078	STORE, 139773774065664, 139773774098431,
		3079	STORE, 139773774098432, 139773774106623,
		3080	STORE, 139773774106624, 139773774110719,
		3081	STORE, 140726412963840, 140726412967935,
		3082	STORE, 140726412951552, 140726412963839,
		3083	STORE, 47859021058048, 47859021066239,
		3084	STORE, 47859021066240, 47859021074431,
		3085	STORE, 47859021074432, 47859021180927,
		3086	STORE, 47859021090816, 47859021180927,
		3087	STORE, 47859021074432, 47859021090815,
		3088	ERASE, 47859021090816, 47859021090816,
		3089	STORE, 47859021090816, 47859021164543,
		3090	STORE, 47859021164544, 47859021180927,
		3091	STORE, 47859021144064, 47859021164543,
		3092	STORE, 47859021090816, 47859021144063,
		3093	ERASE, 47859021090816, 47859021090816,
		3094	STORE, 47859021090816, 47859021144063,
		3095	STORE, 47859021160448, 47859021164543,
		3096	STORE, 47859021144064, 47859021160447,
		3097	ERASE, 47859021144064, 47859021144064,
		3098	STORE, 47859021144064, 47859021160447,
		3099	STORE, 47859021172736, 47859021180927,
		3100	STORE, 47859021164544, 47859021172735,
		3101	ERASE, 47859021164544, 47859021164544,
		3102	STORE, 47859021164544, 47859021172735,
		3103	ERASE, 47859021172736, 47859021172736,
		3104	STORE, 47859021172736, 47859021180927,
		3105	STORE, 47859021180928, 47859023020031,
		3106	STORE, 47859021320192, 47859023020031,
		3107	STORE, 47859021180928, 47859021320191,
		3108	ERASE, 47859021320192, 47859021320192,
		3109	STORE, 47859021320192, 47859022979071,
		3110	STORE, 47859022979072, 47859023020031,
		3111	STORE, 47859022663680, 47859022979071,
		3112	STORE, 47859021320192, 47859022663679,
		3113	ERASE, 47859021320192, 47859021320192,
		3114	STORE, 47859021320192, 47859022663679,
		3115	STORE, 47859022974976, 47859022979071,
		3116	STORE, 47859022663680, 47859022974975,
		3117	ERASE, 47859022663680, 47859022663680,
		3118	STORE, 47859022663680, 47859022974975,
		3119	STORE, 47859023003648, 47859023020031,
		3120	STORE, 47859022979072, 47859023003647,
		3121	ERASE, 47859022979072, 47859022979072,
		3122	STORE, 47859022979072, 47859023003647,
		3123	ERASE, 47859023003648, 47859023003648,
		3124	STORE, 47859023003648, 47859023020031,
		3125	STORE, 47859023003648, 47859023032319,
		3126	ERASE, 47859022979072, 47859022979072,
		3127	STORE, 47859022979072, 47859022995455,
		3128	STORE, 47859022995456, 47859023003647,
		3129	ERASE, 47859021164544, 47859021164544,
		3130	STORE, 47859021164544, 47859021168639,
		3131	STORE, 47859021168640, 47859021172735,
		3132	ERASE, 94094885199872, 94094885199872,
		3133	STORE, 94094885199872, 94094885216255,
		3134	STORE, 94094885216256, 94094885220351,
		3135	ERASE, 139773774098432, 139773774098432,
		3136	STORE, 139773774098432, 139773774102527,
		3137	STORE, 139773774102528, 139773774106623,
		3138	ERASE, 47859021058048, 47859021058048,
		3139	STORE, 94094901108736, 94094901243903,
		3140	STORE, 140737488347136, 140737488351231,
		3141	STORE, 140736567963648, 140737488351231,
		3142	ERASE, 140736567963648, 140736567963648,
		3143	STORE, 140736567963648, 140736567967743,
		3144	STORE, 94924425748480, 94924426461183,
		3145	ERASE, 94924425748480, 94924425748480,
		3146	STORE, 94924425748480, 94924425797631,
		3147	STORE, 94924425797632, 94924426461183,
		3148	ERASE, 94924425797632, 94924425797632,
		3149	STORE, 94924425797632, 94924426342399,
		3150	STORE, 94924426342400, 94924426440703,
		3151	STORE, 94924426440704, 94924426461183,
		3152	STORE, 140042126319616, 140042126491647,
		3153	ERASE, 140042126319616, 140042126319616,
		3154	STORE, 140042126319616, 140042126323711,
		3155	STORE, 140042126323712, 140042126491647,
		3156	ERASE, 140042126323712, 140042126323712,
		3157	STORE, 140042126323712, 140042126446591,
		3158	STORE, 140042126446592, 140042126479359,
		3159	STORE, 140042126479360, 140042126487551,
		3160	STORE, 140042126487552, 140042126491647,
		3161	STORE, 140736568672256, 140736568676351,
		3162	STORE, 140736568659968, 140736568672255,
		3163	STORE, 47590668677120, 47590668685311,
		3164	STORE, 47590668685312, 47590668693503,
		3165	STORE, 47590668693504, 47590668799999,
		3166	STORE, 47590668709888, 47590668799999,
		3167	STORE, 47590668693504, 47590668709887,
		3168	ERASE, 47590668709888, 47590668709888,
		3169	STORE, 47590668709888, 47590668783615,
		3170	STORE, 47590668783616, 47590668799999,
		3171	STORE, 47590668763136, 47590668783615,
		3172	STORE, 47590668709888, 47590668763135,
		3173	ERASE, 47590668709888, 47590668709888,
		3174	STORE, 47590668709888, 47590668763135,
		3175	STORE, 47590668779520, 47590668783615,
		3176	STORE, 47590668763136, 47590668779519,
		3177	ERASE, 47590668763136, 47590668763136,
		3178	STORE, 47590668763136, 47590668779519,
		3179	STORE, 47590668791808, 47590668799999,
		3180	STORE, 47590668783616, 47590668791807,
		3181	ERASE, 47590668783616, 47590668783616,
		3182	STORE, 47590668783616, 47590668791807,
		3183	ERASE, 47590668791808, 47590668791808,
		3184	STORE, 47590668791808, 47590668799999,
		3185	STORE, 47590668800000, 47590670639103,
		3186	STORE, 47590668939264, 47590670639103,
		3187	STORE, 47590668800000, 47590668939263,
		3188	ERASE, 47590668939264, 47590668939264,
		3189	STORE, 47590668939264, 47590670598143,
		3190	STORE, 47590670598144, 47590670639103,
		3191	STORE, 47590670282752, 47590670598143,
		3192	STORE, 47590668939264, 47590670282751,
		3193	ERASE, 47590668939264, 47590668939264,
		3194	STORE, 47590668939264, 47590670282751,
		3195	STORE, 47590670594048, 47590670598143,
		3196	STORE, 47590670282752, 47590670594047,
		3197	ERASE, 47590670282752, 47590670282752,
		3198	STORE, 47590670282752, 47590670594047,
		3199	STORE, 47590670622720, 47590670639103,
		3200	STORE, 47590670598144, 47590670622719,
		3201	ERASE, 47590670598144, 47590670598144,
		3202	STORE, 47590670598144, 47590670622719,
		3203	ERASE, 47590670622720, 47590670622720,
		3204	STORE, 47590670622720, 47590670639103,
		3205	STORE, 47590670622720, 47590670651391,
		3206	ERASE, 47590670598144, 47590670598144,
		3207	STORE, 47590670598144, 47590670614527,
		3208	STORE, 47590670614528, 47590670622719,
		3209	ERASE, 47590668783616, 47590668783616,
		3210	STORE, 47590668783616, 47590668787711,
		3211	STORE, 47590668787712, 47590668791807,
		3212	ERASE, 94924426440704, 94924426440704,
		3213	STORE, 94924426440704, 94924426457087,
		3214	STORE, 94924426457088, 94924426461183,
		3215	ERASE, 140042126479360, 140042126479360,
		3216	STORE, 140042126479360, 140042126483455,
		3217	STORE, 140042126483456, 140042126487551,
		3218	ERASE, 47590668677120, 47590668677120,
		3219	STORE, 140737488347136, 140737488351231,
		3220	STORE, 140733281439744, 140737488351231,
		3221	ERASE, 140733281439744, 140733281439744,
		3222	STORE, 140733281439744, 140733281443839,
		3223	STORE, 94490667069440, 94490667782143,
		3224	ERASE, 94490667069440, 94490667069440,
		3225	STORE, 94490667069440, 94490667118591,
		3226	STORE, 94490667118592, 94490667782143,
		3227	ERASE, 94490667118592, 94490667118592,
		3228	STORE, 94490667118592, 94490667663359,
		3229	STORE, 94490667663360, 94490667761663,
		3230	STORE, 94490667761664, 94490667782143,
		3231	STORE, 139878215118848, 139878215290879,
		3232	ERASE, 139878215118848, 139878215118848,
		3233	STORE, 139878215118848, 139878215122943,
		3234	STORE, 139878215122944, 139878215290879,
		3235	ERASE, 139878215122944, 139878215122944,
		3236	STORE, 139878215122944, 139878215245823,
		3237	STORE, 139878215245824, 139878215278591,
		3238	STORE, 139878215278592, 139878215286783,
		3239	STORE, 139878215286784, 139878215290879,
		3240	STORE, 140733281464320, 140733281468415,
		3241	STORE, 140733281452032, 140733281464319,
		3242	STORE, 47754579877888, 47754579886079,
		3243	STORE, 47754579886080, 47754579894271,
		3244	STORE, 47754579894272, 47754580000767,
		3245	STORE, 47754579910656, 47754580000767,
		3246	STORE, 47754579894272, 47754579910655,
		3247	ERASE, 47754579910656, 47754579910656,
		3248	STORE, 47754579910656, 47754579984383,
		3249	STORE, 47754579984384, 47754580000767,
		3250	STORE, 47754579963904, 47754579984383,
		3251	STORE, 47754579910656, 47754579963903,
		3252	ERASE, 47754579910656, 47754579910656,
		3253	STORE, 47754579910656, 47754579963903,
		3254	STORE, 47754579980288, 47754579984383,
		3255	STORE, 47754579963904, 47754579980287,
		3256	ERASE, 47754579963904, 47754579963904,
		3257	STORE, 47754579963904, 47754579980287,
		3258	STORE, 47754579992576, 47754580000767,
		3259	STORE, 47754579984384, 47754579992575,
		3260	ERASE, 47754579984384, 47754579984384,
		3261	STORE, 47754579984384, 47754579992575,
		3262	ERASE, 47754579992576, 47754579992576,
		3263	STORE, 47754579992576, 47754580000767,
		3264	STORE, 47754580000768, 47754581839871,
		3265	STORE, 47754580140032, 47754581839871,
		3266	STORE, 47754580000768, 47754580140031,
		3267	ERASE, 47754580140032, 47754580140032,
		3268	STORE, 47754580140032, 47754581798911,
		3269	STORE, 47754581798912, 47754581839871,
		3270	STORE, 47754581483520, 47754581798911,
		3271	STORE, 47754580140032, 47754581483519,
		3272	ERASE, 47754580140032, 47754580140032,
		3273	STORE, 47754580140032, 47754581483519,
		3274	STORE, 47754581794816, 47754581798911,
		3275	STORE, 47754581483520, 47754581794815,
		3276	ERASE, 47754581483520, 47754581483520,
		3277	STORE, 47754581483520, 47754581794815,
		3278	STORE, 47754581823488, 47754581839871,
		3279	STORE, 47754581798912, 47754581823487,
		3280	ERASE, 47754581798912, 47754581798912,
		3281	STORE, 47754581798912, 47754581823487,
		3282	ERASE, 47754581823488, 47754581823488,
		3283	STORE, 47754581823488, 47754581839871,
		3284	STORE, 47754581823488, 47754581852159,
		3285	ERASE, 47754581798912, 47754581798912,
		3286	STORE, 47754581798912, 47754581815295,
		3287	STORE, 47754581815296, 47754581823487,
		3288	ERASE, 47754579984384, 47754579984384,
		3289	STORE, 47754579984384, 47754579988479,
		3290	STORE, 47754579988480, 47754579992575,
		3291	ERASE, 94490667761664, 94490667761664,
		3292	STORE, 94490667761664, 94490667778047,
		3293	STORE, 94490667778048, 94490667782143,
		3294	ERASE, 139878215278592, 139878215278592,
		3295	STORE, 139878215278592, 139878215282687,
		3296	STORE, 139878215282688, 139878215286783,
		3297	ERASE, 47754579877888, 47754579877888,
		3298	STORE, 94490669649920, 94490669785087,
		3299	STORE, 140737488347136, 140737488351231,
		3300	STORE, 140735382188032, 140737488351231,
		3301	ERASE, 140735382188032, 140735382188032,
		3302	STORE, 140735382188032, 140735382192127,
		3303	STORE, 94150181302272, 94150182014975,
		3304	ERASE, 94150181302272, 94150181302272,
		3305	STORE, 94150181302272, 94150181351423,
		3306	STORE, 94150181351424, 94150182014975,
		3307	ERASE, 94150181351424, 94150181351424,
		3308	STORE, 94150181351424, 94150181896191,
		3309	STORE, 94150181896192, 94150181994495,
		3310	STORE, 94150181994496, 94150182014975,
		3311	STORE, 139679752458240, 139679752630271,
		3312	ERASE, 139679752458240, 139679752458240,
		3313	STORE, 139679752458240, 139679752462335,
		3314	STORE, 139679752462336, 139679752630271,
		3315	ERASE, 139679752462336, 139679752462336,
		3316	STORE, 139679752462336, 139679752585215,
		3317	STORE, 139679752585216, 139679752617983,
		3318	STORE, 139679752617984, 139679752626175,
		3319	STORE, 139679752626176, 139679752630271,
		3320	STORE, 140735382536192, 140735382540287,
		3321	STORE, 140735382523904, 140735382536191,
		3322	STORE, 47953042538496, 47953042546687,
		3323	STORE, 47953042546688, 47953042554879,
		3324	STORE, 47953042554880, 47953042661375,
		3325	STORE, 47953042571264, 47953042661375,
		3326	STORE, 47953042554880, 47953042571263,
		3327	ERASE, 47953042571264, 47953042571264,
		3328	STORE, 47953042571264, 47953042644991,
		3329	STORE, 47953042644992, 47953042661375,
		3330	STORE, 47953042624512, 47953042644991,
		3331	STORE, 47953042571264, 47953042624511,
		3332	ERASE, 47953042571264, 47953042571264,
		3333	STORE, 47953042571264, 47953042624511,
		3334	STORE, 47953042640896, 47953042644991,
		3335	STORE, 47953042624512, 47953042640895,
		3336	ERASE, 47953042624512, 47953042624512,
		3337	STORE, 47953042624512, 47953042640895,
		3338	STORE, 47953042653184, 47953042661375,
		3339	STORE, 47953042644992, 47953042653183,
		3340	ERASE, 47953042644992, 47953042644992,
		3341	STORE, 47953042644992, 47953042653183,
		3342	ERASE, 47953042653184, 47953042653184,
		3343	STORE, 47953042653184, 47953042661375,
		3344	STORE, 47953042661376, 47953044500479,
		3345	STORE, 47953042800640, 47953044500479,
		3346	STORE, 47953042661376, 47953042800639,
		3347	ERASE, 47953042800640, 47953042800640,
		3348	STORE, 47953042800640, 47953044459519,
		3349	STORE, 47953044459520, 47953044500479,
		3350	STORE, 47953044144128, 47953044459519,
		3351	STORE, 47953042800640, 47953044144127,
		3352	ERASE, 47953042800640, 47953042800640,
		3353	STORE, 47953042800640, 47953044144127,
		3354	STORE, 47953044455424, 47953044459519,
		3355	STORE, 47953044144128, 47953044455423,
		3356	ERASE, 47953044144128, 47953044144128,
		3357	STORE, 47953044144128, 47953044455423,
		3358	STORE, 47953044484096, 47953044500479,
		3359	STORE, 47953044459520, 47953044484095,
		3360	ERASE, 47953044459520, 47953044459520,
		3361	STORE, 47953044459520, 47953044484095,
		3362	ERASE, 47953044484096, 47953044484096,
		3363	STORE, 47953044484096, 47953044500479,
		3364	STORE, 47953044484096, 47953044512767,
		3365	ERASE, 47953044459520, 47953044459520,
		3366	STORE, 47953044459520, 47953044475903,
		3367	STORE, 47953044475904, 47953044484095,
		3368	ERASE, 47953042644992, 47953042644992,
		3369	STORE, 47953042644992, 47953042649087,
		3370	STORE, 47953042649088, 47953042653183,
		3371	ERASE, 94150181994496, 94150181994496,
		3372	STORE, 94150181994496, 94150182010879,
		3373	STORE, 94150182010880, 94150182014975,
		3374	ERASE, 139679752617984, 139679752617984,
		3375	STORE, 139679752617984, 139679752622079,
		3376	STORE, 139679752622080, 139679752626175,
		3377	ERASE, 47953042538496, 47953042538496,
		3378	STORE, 140737488347136, 140737488351231,
		3379	STORE, 140737044123648, 140737488351231,
		3380	ERASE, 140737044123648, 140737044123648,
		3381	STORE, 140737044123648, 140737044127743,
		3382	STORE, 94425324294144, 94425325006847,
		3383	ERASE, 94425324294144, 94425324294144,
		3384	STORE, 94425324294144, 94425324343295,
		3385	STORE, 94425324343296, 94425325006847,
		3386	ERASE, 94425324343296, 94425324343296,
		3387	STORE, 94425324343296, 94425324888063,
		3388	STORE, 94425324888064, 94425324986367,
		3389	STORE, 94425324986368, 94425325006847,
		3390	STORE, 140382015016960, 140382015188991,
		3391	ERASE, 140382015016960, 140382015016960,
		3392	STORE, 140382015016960, 140382015021055,
		3393	STORE, 140382015021056, 140382015188991,
		3394	ERASE, 140382015021056, 140382015021056,
		3395	STORE, 140382015021056, 140382015143935,
		3396	STORE, 140382015143936, 140382015176703,
		3397	STORE, 140382015176704, 140382015184895,
		3398	STORE, 140382015184896, 140382015188991,
		3399	STORE, 140737045585920, 140737045590015,
		3400	STORE, 140737045573632, 140737045585919,
		3401	STORE, 47250779979776, 47250779987967,
		3402	STORE, 47250779987968, 47250779996159,
		3403	STORE, 47250779996160, 47250780102655,
		3404	STORE, 47250780012544, 47250780102655,
		3405	STORE, 47250779996160, 47250780012543,
		3406	ERASE, 47250780012544, 47250780012544,
		3407	STORE, 47250780012544, 47250780086271,
		3408	STORE, 47250780086272, 47250780102655,
		3409	STORE, 47250780065792, 47250780086271,
		3410	STORE, 47250780012544, 47250780065791,
		3411	ERASE, 47250780012544, 47250780012544,
		3412	STORE, 47250780012544, 47250780065791,
		3413	STORE, 47250780082176, 47250780086271,
		3414	STORE, 47250780065792, 47250780082175,
		3415	ERASE, 47250780065792, 47250780065792,
		3416	STORE, 47250780065792, 47250780082175,
		3417	STORE, 47250780094464, 47250780102655,
		3418	STORE, 47250780086272, 47250780094463,
		3419	ERASE, 47250780086272, 47250780086272,
		3420	STORE, 47250780086272, 47250780094463,
		3421	ERASE, 47250780094464, 47250780094464,
		3422	STORE, 47250780094464, 47250780102655,
		3423	STORE, 47250780102656, 47250781941759,
		3424	STORE, 47250780241920, 47250781941759,
		3425	STORE, 47250780102656, 47250780241919,
		3426	ERASE, 47250780241920, 47250780241920,
		3427	STORE, 47250780241920, 47250781900799,
		3428	STORE, 47250781900800, 47250781941759,
		3429	STORE, 47250781585408, 47250781900799,
		3430	STORE, 47250780241920, 47250781585407,
		3431	ERASE, 47250780241920, 47250780241920,
		3432	STORE, 47250780241920, 47250781585407,
		3433	STORE, 47250781896704, 47250781900799,
		3434	STORE, 47250781585408, 47250781896703,
		3435	ERASE, 47250781585408, 47250781585408,
		3436	STORE, 47250781585408, 47250781896703,
		3437	STORE, 47250781925376, 47250781941759,
		3438	STORE, 47250781900800, 47250781925375,
		3439	ERASE, 47250781900800, 47250781900800,
		3440	STORE, 47250781900800, 47250781925375,
		3441	ERASE, 47250781925376, 47250781925376,
		3442	STORE, 47250781925376, 47250781941759,
		3443	STORE, 47250781925376, 47250781954047,
		3444	ERASE, 47250781900800, 47250781900800,
		3445	STORE, 47250781900800, 47250781917183,
		3446	STORE, 47250781917184, 47250781925375,
		3447	ERASE, 47250780086272, 47250780086272,
		3448	STORE, 47250780086272, 47250780090367,
		3449	STORE, 47250780090368, 47250780094463,
		3450	ERASE, 94425324986368, 94425324986368,
		3451	STORE, 94425324986368, 94425325002751,
		3452	STORE, 94425325002752, 94425325006847,
		3453	ERASE, 140382015176704, 140382015176704,
		3454	STORE, 140382015176704, 140382015180799,
		3455	STORE, 140382015180800, 140382015184895,
		3456	ERASE, 47250779979776, 47250779979776,
		3457	STORE, 94425351438336, 94425351573503,
		3458	STORE, 140737488347136, 140737488351231,
		3459	STORE, 140736801144832, 140737488351231,
		3460	ERASE, 140736801144832, 140736801144832,
		3461	STORE, 140736801144832, 140736801148927,
		3462	STORE, 94629429358592, 94629430071295,
		3463	ERASE, 94629429358592, 94629429358592,
		3464	STORE, 94629429358592, 94629429407743,
		3465	STORE, 94629429407744, 94629430071295,
		3466	ERASE, 94629429407744, 94629429407744,
		3467	STORE, 94629429407744, 94629429952511,
		3468	STORE, 94629429952512, 94629430050815,
		3469	STORE, 94629430050816, 94629430071295,
		3470	STORE, 139801685483520, 139801685655551,
		3471	ERASE, 139801685483520, 139801685483520,
		3472	STORE, 139801685483520, 139801685487615,
		3473	STORE, 139801685487616, 139801685655551,
		3474	ERASE, 139801685487616, 139801685487616,
		3475	STORE, 139801685487616, 139801685610495,
		3476	STORE, 139801685610496, 139801685643263,
		3477	STORE, 139801685643264, 139801685651455,
		3478	STORE, 139801685651456, 139801685655551,
		3479	STORE, 140736801198080, 140736801202175,
		3480	STORE, 140736801185792, 140736801198079,
		3481	STORE, 47831109513216, 47831109521407,
		3482	STORE, 47831109521408, 47831109529599,
		3483	STORE, 47831109529600, 47831109636095,
		3484	STORE, 47831109545984, 47831109636095,
		3485	STORE, 47831109529600, 47831109545983,
		3486	ERASE, 47831109545984, 47831109545984,
		3487	STORE, 47831109545984, 47831109619711,
		3488	STORE, 47831109619712, 47831109636095,
		3489	STORE, 47831109599232, 47831109619711,
		3490	STORE, 47831109545984, 47831109599231,
		3491	ERASE, 47831109545984, 47831109545984,
		3492	STORE, 47831109545984, 47831109599231,
		3493	STORE, 47831109615616, 47831109619711,
		3494	STORE, 47831109599232, 47831109615615,
		3495	ERASE, 47831109599232, 47831109599232,
		3496	STORE, 47831109599232, 47831109615615,
		3497	STORE, 47831109627904, 47831109636095,
		3498	STORE, 47831109619712, 47831109627903,
		3499	ERASE, 47831109619712, 47831109619712,
		3500	STORE, 47831109619712, 47831109627903,
		3501	ERASE, 47831109627904, 47831109627904,
		3502	STORE, 47831109627904, 47831109636095,
		3503	STORE, 47831109636096, 47831111475199,
		3504	STORE, 47831109775360, 47831111475199,
		3505	STORE, 47831109636096, 47831109775359,
		3506	ERASE, 47831109775360, 47831109775360,
		3507	STORE, 47831109775360, 47831111434239,
		3508	STORE, 47831111434240, 47831111475199,
		3509	STORE, 47831111118848, 47831111434239,
		3510	STORE, 47831109775360, 47831111118847,
		3511	ERASE, 47831109775360, 47831109775360,
		3512	STORE, 47831109775360, 47831111118847,
		3513	STORE, 47831111430144, 47831111434239,
		3514	STORE, 47831111118848, 47831111430143,
		3515	ERASE, 47831111118848, 47831111118848,
		3516	STORE, 47831111118848, 47831111430143,
		3517	STORE, 47831111458816, 47831111475199,
		3518	STORE, 47831111434240, 47831111458815,
		3519	ERASE, 47831111434240, 47831111434240,
		3520	STORE, 47831111434240, 47831111458815,
		3521	ERASE, 47831111458816, 47831111458816,
		3522	STORE, 47831111458816, 47831111475199,
		3523	STORE, 47831111458816, 47831111487487,
		3524	ERASE, 47831111434240, 47831111434240,
		3525	STORE, 47831111434240, 47831111450623,
		3526	STORE, 47831111450624, 47831111458815,
		3527	ERASE, 47831109619712, 47831109619712,
		3528	STORE, 47831109619712, 47831109623807,
		3529	STORE, 47831109623808, 47831109627903,
		3530	ERASE, 94629430050816, 94629430050816,
		3531	STORE, 94629430050816, 94629430067199,
		3532	STORE, 94629430067200, 94629430071295,
		3533	ERASE, 139801685643264, 139801685643264,
		3534	STORE, 139801685643264, 139801685647359,
		3535	STORE, 139801685647360, 139801685651455,
		3536	ERASE, 47831109513216, 47831109513216,
		3537	STORE, 140737488347136, 140737488351231,
		3538	STORE, 140729419612160, 140737488351231,
		3539	ERASE, 140729419612160, 140729419612160,
		3540	STORE, 140729419612160, 140729419616255,
		3541	STORE, 94443354148864, 94443354861567,
		3542	ERASE, 94443354148864, 94443354148864,
		3543	STORE, 94443354148864, 94443354198015,
		3544	STORE, 94443354198016, 94443354861567,
		3545	ERASE, 94443354198016, 94443354198016,
		3546	STORE, 94443354198016, 94443354742783,
		3547	STORE, 94443354742784, 94443354841087,
		3548	STORE, 94443354841088, 94443354861567,
		3549	STORE, 139741700038656, 139741700210687,
		3550	ERASE, 139741700038656, 139741700038656,
		3551	STORE, 139741700038656, 139741700042751,
		3552	STORE, 139741700042752, 139741700210687,
		3553	ERASE, 139741700042752, 139741700042752,
		3554	STORE, 139741700042752, 139741700165631,
		3555	STORE, 139741700165632, 139741700198399,
		3556	STORE, 139741700198400, 139741700206591,
		3557	STORE, 139741700206592, 139741700210687,
		3558	STORE, 140729420574720, 140729420578815,
		3559	STORE, 140729420562432, 140729420574719,
		3560	STORE, 47891094958080, 47891094966271,
		3561	STORE, 47891094966272, 47891094974463,
		3562	STORE, 47891094974464, 47891095080959,
		3563	STORE, 47891094990848, 47891095080959,
		3564	STORE, 47891094974464, 47891094990847,
		3565	ERASE, 47891094990848, 47891094990848,
		3566	STORE, 47891094990848, 47891095064575,
		3567	STORE, 47891095064576, 47891095080959,
		3568	STORE, 47891095044096, 47891095064575,
		3569	STORE, 47891094990848, 47891095044095,
		3570	ERASE, 47891094990848, 47891094990848,
		3571	STORE, 47891094990848, 47891095044095,
		3572	STORE, 47891095060480, 47891095064575,
		3573	STORE, 47891095044096, 47891095060479,
		3574	ERASE, 47891095044096, 47891095044096,
		3575	STORE, 47891095044096, 47891095060479,
		3576	STORE, 47891095072768, 47891095080959,
		3577	STORE, 47891095064576, 47891095072767,
		3578	ERASE, 47891095064576, 47891095064576,
		3579	STORE, 47891095064576, 47891095072767,
		3580	ERASE, 47891095072768, 47891095072768,
		3581	STORE, 47891095072768, 47891095080959,
		3582	STORE, 47891095080960, 47891096920063,
		3583	STORE, 47891095220224, 47891096920063,
		3584	STORE, 47891095080960, 47891095220223,
		3585	ERASE, 47891095220224, 47891095220224,
		3586	STORE, 47891095220224, 47891096879103,
		3587	STORE, 47891096879104, 47891096920063,
		3588	STORE, 47891096563712, 47891096879103,
		3589	STORE, 47891095220224, 47891096563711,
		3590	ERASE, 47891095220224, 47891095220224,
		3591	STORE, 47891095220224, 47891096563711,
		3592	STORE, 47891096875008, 47891096879103,
		3593	STORE, 47891096563712, 47891096875007,
		3594	ERASE, 47891096563712, 47891096563712,
		3595	STORE, 47891096563712, 47891096875007,
		3596	STORE, 47891096903680, 47891096920063,
		3597	STORE, 47891096879104, 47891096903679,
		3598	ERASE, 47891096879104, 47891096879104,
		3599	STORE, 47891096879104, 47891096903679,
		3600	ERASE, 47891096903680, 47891096903680,
		3601	STORE, 47891096903680, 47891096920063,
		3602	STORE, 47891096903680, 47891096932351,
		3603	ERASE, 47891096879104, 47891096879104,
		3604	STORE, 47891096879104, 47891096895487,
		3605	STORE, 47891096895488, 47891096903679,
		3606	ERASE, 47891095064576, 47891095064576,
		3607	STORE, 47891095064576, 47891095068671,
		3608	STORE, 47891095068672, 47891095072767,
		3609	ERASE, 94443354841088, 94443354841088,
		3610	STORE, 94443354841088, 94443354857471,
		3611	STORE, 94443354857472, 94443354861567,
		3612	ERASE, 139741700198400, 139741700198400,
		3613	STORE, 139741700198400, 139741700202495,
		3614	STORE, 139741700202496, 139741700206591,
		3615	ERASE, 47891094958080, 47891094958080,
		3616	STORE, 94443360825344, 94443360960511,
		3617	STORE, 140737488347136, 140737488351231,
		3618	STORE, 140722961661952, 140737488351231,
		3619	ERASE, 140722961661952, 140722961661952,
		3620	STORE, 140722961661952, 140722961666047,
		3621	STORE, 94878388944896, 94878389657599,
		3622	ERASE, 94878388944896, 94878388944896,
		3623	STORE, 94878388944896, 94878388994047,
		3624	STORE, 94878388994048, 94878389657599,
		3625	ERASE, 94878388994048, 94878388994048,
		3626	STORE, 94878388994048, 94878389538815,
		3627	STORE, 94878389538816, 94878389637119,
		3628	STORE, 94878389637120, 94878389657599,
		3629	STORE, 140210690056192, 140210690228223,
		3630	ERASE, 140210690056192, 140210690056192,
		3631	STORE, 140210690056192, 140210690060287,
		3632	STORE, 140210690060288, 140210690228223,
		3633	ERASE, 140210690060288, 140210690060288,
		3634	STORE, 140210690060288, 140210690183167,
		3635	STORE, 140210690183168, 140210690215935,
		3636	STORE, 140210690215936, 140210690224127,
		3637	STORE, 140210690224128, 140210690228223,
		3638	STORE, 140722963148800, 140722963152895,
		3639	STORE, 140722963136512, 140722963148799,
		3640	STORE, 47422104940544, 47422104948735,
		3641	STORE, 47422104948736, 47422104956927,
		3642	STORE, 47422104956928, 47422105063423,
		3643	STORE, 47422104973312, 47422105063423,
		3644	STORE, 47422104956928, 47422104973311,
		3645	ERASE, 47422104973312, 47422104973312,
		3646	STORE, 47422104973312, 47422105047039,
		3647	STORE, 47422105047040, 47422105063423,
		3648	STORE, 47422105026560, 47422105047039,
		3649	STORE, 47422104973312, 47422105026559,
		3650	ERASE, 47422104973312, 47422104973312,
		3651	STORE, 47422104973312, 47422105026559,
		3652	STORE, 47422105042944, 47422105047039,
		3653	STORE, 47422105026560, 47422105042943,
		3654	ERASE, 47422105026560, 47422105026560,
		3655	STORE, 47422105026560, 47422105042943,
		3656	STORE, 47422105055232, 47422105063423,
		3657	STORE, 47422105047040, 47422105055231,
		3658	ERASE, 47422105047040, 47422105047040,
		3659	STORE, 47422105047040, 47422105055231,
		3660	ERASE, 47422105055232, 47422105055232,
		3661	STORE, 47422105055232, 47422105063423,
		3662	STORE, 47422105063424, 47422106902527,
		3663	STORE, 47422105202688, 47422106902527,
		3664	STORE, 47422105063424, 47422105202687,
		3665	ERASE, 47422105202688, 47422105202688,
		3666	STORE, 47422105202688, 47422106861567,
		3667	STORE, 47422106861568, 47422106902527,
		3668	STORE, 47422106546176, 47422106861567,
		3669	STORE, 47422105202688, 47422106546175,
		3670	ERASE, 47422105202688, 47422105202688,
		3671	STORE, 47422105202688, 47422106546175,
		3672	STORE, 47422106857472, 47422106861567,
		3673	STORE, 47422106546176, 47422106857471,
		3674	ERASE, 47422106546176, 47422106546176,
		3675	STORE, 47422106546176, 47422106857471,
		3676	STORE, 47422106886144, 47422106902527,
		3677	STORE, 47422106861568, 47422106886143,
		3678	ERASE, 47422106861568, 47422106861568,
		3679	STORE, 47422106861568, 47422106886143,
		3680	ERASE, 47422106886144, 47422106886144,
		3681	STORE, 47422106886144, 47422106902527,
		3682	STORE, 47422106886144, 47422106914815,
		3683	ERASE, 47422106861568, 47422106861568,
		3684	STORE, 47422106861568, 47422106877951,
		3685	STORE, 47422106877952, 47422106886143,
		3686	ERASE, 47422105047040, 47422105047040,
		3687	STORE, 47422105047040, 47422105051135,
		3688	STORE, 47422105051136, 47422105055231,
		3689	ERASE, 94878389637120, 94878389637120,
		3690	STORE, 94878389637120, 94878389653503,
		3691	STORE, 94878389653504, 94878389657599,
		3692	ERASE, 140210690215936, 140210690215936,
		3693	STORE, 140210690215936, 140210690220031,
		3694	STORE, 140210690220032, 140210690224127,
		3695	ERASE, 47422104940544, 47422104940544,
		3696	STORE, 140737488347136, 140737488351231,
		3697	STORE, 140727690309632, 140737488351231,
		3698	ERASE, 140727690309632, 140727690309632,
		3699	STORE, 140727690309632, 140727690313727,
		3700	STORE, 94121892208640, 94121892921343,
		3701	ERASE, 94121892208640, 94121892208640,
		3702	STORE, 94121892208640, 94121892257791,
		3703	STORE, 94121892257792, 94121892921343,
		3704	ERASE, 94121892257792, 94121892257792,
		3705	STORE, 94121892257792, 94121892802559,
		3706	STORE, 94121892802560, 94121892900863,
		3707	STORE, 94121892900864, 94121892921343,
		3708	STORE, 140662438326272, 140662438498303,
		3709	ERASE, 140662438326272, 140662438326272,
		3710	STORE, 140662438326272, 140662438330367,
		3711	STORE, 140662438330368, 140662438498303,
		3712	ERASE, 140662438330368, 140662438330368,
		3713	STORE, 140662438330368, 140662438453247,
		3714	STORE, 140662438453248, 140662438486015,
		3715	STORE, 140662438486016, 140662438494207,
		3716	STORE, 140662438494208, 140662438498303,
		3717	STORE, 140727690379264, 140727690383359,
		3718	STORE, 140727690366976, 140727690379263,
		3719	STORE, 46970356670464, 46970356678655,
		3720	STORE, 46970356678656, 46970356686847,
		3721	STORE, 46970356686848, 46970356793343,
		3722	STORE, 46970356703232, 46970356793343,
		3723	STORE, 46970356686848, 46970356703231,
		3724	ERASE, 46970356703232, 46970356703232,
		3725	STORE, 46970356703232, 46970356776959,
		3726	STORE, 46970356776960, 46970356793343,
		3727	STORE, 46970356756480, 46970356776959,
		3728	STORE, 46970356703232, 46970356756479,
		3729	ERASE, 46970356703232, 46970356703232,
		3730	STORE, 46970356703232, 46970356756479,
		3731	STORE, 46970356772864, 46970356776959,
		3732	STORE, 46970356756480, 46970356772863,
		3733	ERASE, 46970356756480, 46970356756480,
		3734	STORE, 46970356756480, 46970356772863,
		3735	STORE, 46970356785152, 46970356793343,
		3736	STORE, 46970356776960, 46970356785151,
		3737	ERASE, 46970356776960, 46970356776960,
		3738	STORE, 46970356776960, 46970356785151,
		3739	ERASE, 46970356785152, 46970356785152,
		3740	STORE, 46970356785152, 46970356793343,
		3741	STORE, 46970356793344, 46970358632447,
		3742	STORE, 46970356932608, 46970358632447,
		3743	STORE, 46970356793344, 46970356932607,
		3744	ERASE, 46970356932608, 46970356932608,
		3745	STORE, 46970356932608, 46970358591487,
		3746	STORE, 46970358591488, 46970358632447,
		3747	STORE, 46970358276096, 46970358591487,
		3748	STORE, 46970356932608, 46970358276095,
		3749	ERASE, 46970356932608, 46970356932608,
		3750	STORE, 46970356932608, 46970358276095,
		3751	STORE, 46970358587392, 46970358591487,
		3752	STORE, 46970358276096, 46970358587391,
		3753	ERASE, 46970358276096, 46970358276096,
		3754	STORE, 46970358276096, 46970358587391,
		3755	STORE, 46970358616064, 46970358632447,
		3756	STORE, 46970358591488, 46970358616063,
		3757	ERASE, 46970358591488, 46970358591488,
		3758	STORE, 46970358591488, 46970358616063,
		3759	ERASE, 46970358616064, 46970358616064,
		3760	STORE, 46970358616064, 46970358632447,
		3761	STORE, 46970358616064, 46970358644735,
		3762	ERASE, 46970358591488, 46970358591488,
		3763	STORE, 46970358591488, 46970358607871,
		3764	STORE, 46970358607872, 46970358616063,
		3765	ERASE, 46970356776960, 46970356776960,
		3766	STORE, 46970356776960, 46970356781055,
		3767	STORE, 46970356781056, 46970356785151,
		3768	ERASE, 94121892900864, 94121892900864,
		3769	STORE, 94121892900864, 94121892917247,
		3770	STORE, 94121892917248, 94121892921343,
		3771	ERASE, 140662438486016, 140662438486016,
		3772	STORE, 140662438486016, 140662438490111,
		3773	STORE, 140662438490112, 140662438494207,
		3774	ERASE, 46970356670464, 46970356670464,
		3775	STORE, 94121898610688, 94121898745855,
		3776	STORE, 140737488347136, 140737488351231,
		3777	STORE, 140737189351424, 140737488351231,
		3778	ERASE, 140737189351424, 140737189351424,
		3779	STORE, 140737189351424, 140737189355519,
		3780	STORE, 93847948832768, 93847949545471,
		3781	ERASE, 93847948832768, 93847948832768,
		3782	STORE, 93847948832768, 93847948881919,
		3783	STORE, 93847948881920, 93847949545471,
		3784	ERASE, 93847948881920, 93847948881920,
		3785	STORE, 93847948881920, 93847949426687,
		3786	STORE, 93847949426688, 93847949524991,
		3787	STORE, 93847949524992, 93847949545471,
		3788	STORE, 139698989985792, 139698990157823,
		3789	ERASE, 139698989985792, 139698989985792,
		3790	STORE, 139698989985792, 139698989989887,
		3791	STORE, 139698989989888, 139698990157823,
		3792	ERASE, 139698989989888, 139698989989888,
		3793	STORE, 139698989989888, 139698990112767,
		3794	STORE, 139698990112768, 139698990145535,
		3795	STORE, 139698990145536, 139698990153727,
		3796	STORE, 139698990153728, 139698990157823,
		3797	STORE, 140737189744640, 140737189748735,
		3798	STORE, 140737189732352, 140737189744639,
		3799	STORE, 47933805010944, 47933805019135,
		3800	STORE, 47933805019136, 47933805027327,
		3801	STORE, 47933805027328, 47933805133823,
		3802	STORE, 47933805043712, 47933805133823,
		3803	STORE, 47933805027328, 47933805043711,
		3804	ERASE, 47933805043712, 47933805043712,
		3805	STORE, 47933805043712, 47933805117439,
		3806	STORE, 47933805117440, 47933805133823,
		3807	STORE, 47933805096960, 47933805117439,
		3808	STORE, 47933805043712, 47933805096959,
		3809	ERASE, 47933805043712, 47933805043712,
		3810	STORE, 47933805043712, 47933805096959,
		3811	STORE, 47933805113344, 47933805117439,
		3812	STORE, 47933805096960, 47933805113343,
		3813	ERASE, 47933805096960, 47933805096960,
		3814	STORE, 47933805096960, 47933805113343,
		3815	STORE, 47933805125632, 47933805133823,
		3816	STORE, 47933805117440, 47933805125631,
		3817	ERASE, 47933805117440, 47933805117440,
		3818	STORE, 47933805117440, 47933805125631,
		3819	ERASE, 47933805125632, 47933805125632,
		3820	STORE, 47933805125632, 47933805133823,
		3821	STORE, 47933805133824, 47933806972927,
		3822	STORE, 47933805273088, 47933806972927,
		3823	STORE, 47933805133824, 47933805273087,
		3824	ERASE, 47933805273088, 47933805273088,
		3825	STORE, 47933805273088, 47933806931967,
		3826	STORE, 47933806931968, 47933806972927,
		3827	STORE, 47933806616576, 47933806931967,
		3828	STORE, 47933805273088, 47933806616575,
		3829	ERASE, 47933805273088, 47933805273088,
		3830	STORE, 47933805273088, 47933806616575,
		3831	STORE, 47933806927872, 47933806931967,
		3832	STORE, 47933806616576, 47933806927871,
		3833	ERASE, 47933806616576, 47933806616576,
		3834	STORE, 47933806616576, 47933806927871,
		3835	STORE, 47933806956544, 47933806972927,
		3836	STORE, 47933806931968, 47933806956543,
		3837	ERASE, 47933806931968, 47933806931968,
		3838	STORE, 47933806931968, 47933806956543,
		3839	ERASE, 47933806956544, 47933806956544,
		3840	STORE, 47933806956544, 47933806972927,
		3841	STORE, 47933806956544, 47933806985215,
		3842	ERASE, 47933806931968, 47933806931968,
		3843	STORE, 47933806931968, 47933806948351,
		3844	STORE, 47933806948352, 47933806956543,
		3845	ERASE, 47933805117440, 47933805117440,
		3846	STORE, 47933805117440, 47933805121535,
		3847	STORE, 47933805121536, 47933805125631,
		3848	ERASE, 93847949524992, 93847949524992,
		3849	STORE, 93847949524992, 93847949541375,
		3850	STORE, 93847949541376, 93847949545471,
		3851	ERASE, 139698990145536, 139698990145536,
		3852	STORE, 139698990145536, 139698990149631,
		3853	STORE, 139698990149632, 139698990153727,
		3854	ERASE, 47933805010944, 47933805010944,
		3855	STORE, 140737488347136, 140737488351231,
		3856	STORE, 140725553991680, 140737488351231,
		3857	ERASE, 140725553991680, 140725553991680,
		3858	STORE, 140725553991680, 140725553995775,
		3859	STORE, 93980056248320, 93980056961023,
		3860	ERASE, 93980056248320, 93980056248320,
		3861	STORE, 93980056248320, 93980056297471,
		3862	STORE, 93980056297472, 93980056961023,
		3863	ERASE, 93980056297472, 93980056297472,
		3864	STORE, 93980056297472, 93980056842239,
		3865	STORE, 93980056842240, 93980056940543,
		3866	STORE, 93980056940544, 93980056961023,
		3867	STORE, 140146588971008, 140146589143039,
		3868	ERASE, 140146588971008, 140146588971008,
		3869	STORE, 140146588971008, 140146588975103,
		3870	STORE, 140146588975104, 140146589143039,
		3871	ERASE, 140146588975104, 140146588975104,
		3872	STORE, 140146588975104, 140146589097983,
		3873	STORE, 140146589097984, 140146589130751,
		3874	STORE, 140146589130752, 140146589138943,
		3875	STORE, 140146589138944, 140146589143039,
		3876	STORE, 140725554860032, 140725554864127,
		3877	STORE, 140725554847744, 140725554860031,
		3878	STORE, 47486206025728, 47486206033919,
		3879	STORE, 47486206033920, 47486206042111,
		3880	STORE, 47486206042112, 47486206148607,
		3881	STORE, 47486206058496, 47486206148607,
		3882	STORE, 47486206042112, 47486206058495,
		3883	ERASE, 47486206058496, 47486206058496,
		3884	STORE, 47486206058496, 47486206132223,
		3885	STORE, 47486206132224, 47486206148607,
		3886	STORE, 47486206111744, 47486206132223,
		3887	STORE, 47486206058496, 47486206111743,
		3888	ERASE, 47486206058496, 47486206058496,
		3889	STORE, 47486206058496, 47486206111743,
		3890	STORE, 47486206128128, 47486206132223,
		3891	STORE, 47486206111744, 47486206128127,
		3892	ERASE, 47486206111744, 47486206111744,
		3893	STORE, 47486206111744, 47486206128127,
		3894	STORE, 47486206140416, 47486206148607,
		3895	STORE, 47486206132224, 47486206140415,
		3896	ERASE, 47486206132224, 47486206132224,
		3897	STORE, 47486206132224, 47486206140415,
		3898	ERASE, 47486206140416, 47486206140416,
		3899	STORE, 47486206140416, 47486206148607,
		3900	STORE, 47486206148608, 47486207987711,
		3901	STORE, 47486206287872, 47486207987711,
		3902	STORE, 47486206148608, 47486206287871,
		3903	ERASE, 47486206287872, 47486206287872,
		3904	STORE, 47486206287872, 47486207946751,
		3905	STORE, 47486207946752, 47486207987711,
		3906	STORE, 47486207631360, 47486207946751,
		3907	STORE, 47486206287872, 47486207631359,
		3908	ERASE, 47486206287872, 47486206287872,
		3909	STORE, 47486206287872, 47486207631359,
		3910	STORE, 47486207942656, 47486207946751,
		3911	STORE, 47486207631360, 47486207942655,
		3912	ERASE, 47486207631360, 47486207631360,
		3913	STORE, 47486207631360, 47486207942655,
		3914	STORE, 47486207971328, 47486207987711,
		3915	STORE, 47486207946752, 47486207971327,
		3916	ERASE, 47486207946752, 47486207946752,
		3917	STORE, 47486207946752, 47486207971327,
		3918	ERASE, 47486207971328, 47486207971328,
		3919	STORE, 47486207971328, 47486207987711,
		3920	STORE, 47486207971328, 47486207999999,
		3921	ERASE, 47486207946752, 47486207946752,
		3922	STORE, 47486207946752, 47486207963135,
		3923	STORE, 47486207963136, 47486207971327,
		3924	ERASE, 47486206132224, 47486206132224,
		3925	STORE, 47486206132224, 47486206136319,
		3926	STORE, 47486206136320, 47486206140415,
		3927	ERASE, 93980056940544, 93980056940544,
		3928	STORE, 93980056940544, 93980056956927,
		3929	STORE, 93980056956928, 93980056961023,
		3930	ERASE, 140146589130752, 140146589130752,
		3931	STORE, 140146589130752, 140146589134847,
		3932	STORE, 140146589134848, 140146589138943,
		3933	ERASE, 47486206025728, 47486206025728,
		3934	STORE, 93980070006784, 93980070141951,
		3935	STORE, 140737488347136, 140737488351231,
		3936	STORE, 140727334776832, 140737488351231,
		3937	ERASE, 140727334776832, 140727334776832,
		3938	STORE, 140727334776832, 140727334780927,
		3939	STORE, 94049747247104, 94049747959807,
		3940	ERASE, 94049747247104, 94049747247104,
		3941	STORE, 94049747247104, 94049747296255,
		3942	STORE, 94049747296256, 94049747959807,
		3943	ERASE, 94049747296256, 94049747296256,
		3944	STORE, 94049747296256, 94049747841023,
		3945	STORE, 94049747841024, 94049747939327,
		3946	STORE, 94049747939328, 94049747959807,
		3947	STORE, 140227307216896, 140227307388927,
		3948	ERASE, 140227307216896, 140227307216896,
		3949	STORE, 140227307216896, 140227307220991,
		3950	STORE, 140227307220992, 140227307388927,
		3951	ERASE, 140227307220992, 140227307220992,
		3952	STORE, 140227307220992, 140227307343871,
		3953	STORE, 140227307343872, 140227307376639,
		3954	STORE, 140227307376640, 140227307384831,
		3955	STORE, 140227307384832, 140227307388927,
		3956	STORE, 140727335337984, 140727335342079,
		3957	STORE, 140727335325696, 140727335337983,
		3958	STORE, 47405487779840, 47405487788031,
		3959	STORE, 47405487788032, 47405487796223,
		3960	STORE, 47405487796224, 47405487902719,
		3961	STORE, 47405487812608, 47405487902719,
		3962	STORE, 47405487796224, 47405487812607,
		3963	ERASE, 47405487812608, 47405487812608,
		3964	STORE, 47405487812608, 47405487886335,
		3965	STORE, 47405487886336, 47405487902719,
		3966	STORE, 47405487865856, 47405487886335,
		3967	STORE, 47405487812608, 47405487865855,
		3968	ERASE, 47405487812608, 47405487812608,
		3969	STORE, 47405487812608, 47405487865855,
		3970	STORE, 47405487882240, 47405487886335,
		3971	STORE, 47405487865856, 47405487882239,
		3972	ERASE, 47405487865856, 47405487865856,
		3973	STORE, 47405487865856, 47405487882239,
		3974	STORE, 47405487894528, 47405487902719,
		3975	STORE, 47405487886336, 47405487894527,
		3976	ERASE, 47405487886336, 47405487886336,
		3977	STORE, 47405487886336, 47405487894527,
		3978	ERASE, 47405487894528, 47405487894528,
		3979	STORE, 47405487894528, 47405487902719,
		3980	STORE, 47405487902720, 47405489741823,
		3981	STORE, 47405488041984, 47405489741823,
		3982	STORE, 47405487902720, 47405488041983,
		3983	ERASE, 47405488041984, 47405488041984,
		3984	STORE, 47405488041984, 47405489700863,
		3985	STORE, 47405489700864, 47405489741823,
		3986	STORE, 47405489385472, 47405489700863,
		3987	STORE, 47405488041984, 47405489385471,
		3988	ERASE, 47405488041984, 47405488041984,
		3989	STORE, 47405488041984, 47405489385471,
		3990	STORE, 47405489696768, 47405489700863,
		3991	STORE, 47405489385472, 47405489696767,
		3992	ERASE, 47405489385472, 47405489385472,
		3993	STORE, 47405489385472, 47405489696767,
		3994	STORE, 47405489725440, 47405489741823,
		3995	STORE, 47405489700864, 47405489725439,
		3996	ERASE, 47405489700864, 47405489700864,
		3997	STORE, 47405489700864, 47405489725439,
		3998	ERASE, 47405489725440, 47405489725440,
		3999	STORE, 47405489725440, 47405489741823,
		4000	STORE, 47405489725440, 47405489754111,
		4001	ERASE, 47405489700864, 47405489700864,
		4002	STORE, 47405489700864, 47405489717247,
		4003	STORE, 47405489717248, 47405489725439,
		4004	ERASE, 47405487886336, 47405487886336,
		4005	STORE, 47405487886336, 47405487890431,
		4006	STORE, 47405487890432, 47405487894527,
		4007	ERASE, 94049747939328, 94049747939328,
		4008	STORE, 94049747939328, 94049747955711,
		4009	STORE, 94049747955712, 94049747959807,
		4010	ERASE, 140227307376640, 140227307376640,
		4011	STORE, 140227307376640, 140227307380735,
		4012	STORE, 140227307380736, 140227307384831,
		4013	ERASE, 47405487779840, 47405487779840,
		4014	STORE, 94049758810112, 94049758945279,
		4015	STORE, 140737488347136, 140737488351231,
		4016	STORE, 140727079718912, 140737488351231,
		4017	ERASE, 140727079718912, 140727079718912,
		4018	STORE, 140727079718912, 140727079723007,
		4019	STORE, 94250996527104, 94250997239807,
		4020	ERASE, 94250996527104, 94250996527104,
		4021	STORE, 94250996527104, 94250996576255,
		4022	STORE, 94250996576256, 94250997239807,
		4023	ERASE, 94250996576256, 94250996576256,
		4024	STORE, 94250996576256, 94250997121023,
		4025	STORE, 94250997121024, 94250997219327,
		4026	STORE, 94250997219328, 94250997239807,
		4027	STORE, 140060022587392, 140060022759423,
		4028	ERASE, 140060022587392, 140060022587392,
		4029	STORE, 140060022587392, 140060022591487,
		4030	STORE, 140060022591488, 140060022759423,
		4031	ERASE, 140060022591488, 140060022591488,
		4032	STORE, 140060022591488, 140060022714367,
		4033	STORE, 140060022714368, 140060022747135,
		4034	STORE, 140060022747136, 140060022755327,
		4035	STORE, 140060022755328, 140060022759423,
		4036	STORE, 140727079788544, 140727079792639,
		4037	STORE, 140727079776256, 140727079788543,
		4038	/* this next one caused issues when lowering the efficiency */
		4039	STORE, 47572772409344, 47572772417535,
		4040	STORE, 47572772417536, 47572772425727,
		4041	STORE, 47572772425728, 47572772532223,
		4042	STORE, 47572772442112, 47572772532223,
		4043	STORE, 47572772425728, 47572772442111,
		4044	ERASE, 47572772442112, 47572772442112,
		4045	STORE, 47572772442112, 47572772515839,
		4046	STORE, 47572772515840, 47572772532223,
		4047	STORE, 47572772495360, 47572772515839,
		4048	STORE, 47572772442112, 47572772495359,
		4049	ERASE, 47572772442112, 47572772442112,
		4050	STORE, 47572772442112, 47572772495359,
		4051	STORE, 47572772511744, 47572772515839,
		4052	STORE, 47572772495360, 47572772511743,
		4053	ERASE, 47572772495360, 47572772495360,
		4054	STORE, 47572772495360, 47572772511743,
		4055	STORE, 47572772524032, 47572772532223,
		4056	STORE, 47572772515840, 47572772524031,
		4057	ERASE, 47572772515840, 47572772515840,
		4058	STORE, 47572772515840, 47572772524031,
		4059	ERASE, 47572772524032, 47572772524032,
		4060	STORE, 47572772524032, 47572772532223,
		4061	STORE, 47572772532224, 47572774371327,
		4062	STORE, 47572772671488, 47572774371327,
		4063	STORE, 47572772532224, 47572772671487,
		4064	ERASE, 47572772671488, 47572772671488,
		4065	STORE, 47572772671488, 47572774330367,
		4066	STORE, 47572774330368, 47572774371327,
		4067	STORE, 47572774014976, 47572774330367,
		4068	STORE, 47572772671488, 47572774014975,
		4069	ERASE, 47572772671488, 47572772671488,
		4070	STORE, 47572772671488, 47572774014975,
		4071	STORE, 47572774326272, 47572774330367,
		4072	STORE, 47572774014976, 47572774326271,
		4073	ERASE, 47572774014976, 47572774014976,
		4074	STORE, 47572774014976, 47572774326271,
		4075	STORE, 47572774354944, 47572774371327,
		4076	STORE, 47572774330368, 47572774354943,
		4077	ERASE, 47572774330368, 47572774330368,
		4078	STORE, 47572774330368, 47572774354943,
		4079	ERASE, 47572774354944, 47572774354944,
		4080	STORE, 47572774354944, 47572774371327,
		4081	STORE, 47572774354944, 47572774383615,
		4082	ERASE, 47572774330368, 47572774330368,
		4083	STORE, 47572774330368, 47572774346751,
		4084	STORE, 47572774346752, 47572774354943,
		4085	ERASE, 47572772515840, 47572772515840,
		4086	STORE, 47572772515840, 47572772519935,
		4087	STORE, 47572772519936, 47572772524031,
		4088	ERASE, 94250997219328, 94250997219328,
		4089	STORE, 94250997219328, 94250997235711,
		4090	STORE, 94250997235712, 94250997239807,
		4091	ERASE, 140060022747136, 140060022747136,
		4092	STORE, 140060022747136, 140060022751231,
		4093	STORE, 140060022751232, 140060022755327,
		4094	ERASE, 47572772409344, 47572772409344,
		4095	STORE, 94251018305536, 94251018440703,
		4096	STORE, 140737488347136, 140737488351231,
		4097	STORE, 140730012389376, 140737488351231,
		4098	ERASE, 140730012389376, 140730012389376,
		4099	STORE, 140730012389376, 140730012393471,
		4100	STORE, 94382607675392, 94382607695871,
		4101	ERASE, 94382607675392, 94382607675392,
		4102	STORE, 94382607675392, 94382607679487,
		4103	STORE, 94382607679488, 94382607695871,
		4104	ERASE, 94382607679488, 94382607679488,
		4105	STORE, 94382607679488, 94382607683583,
		4106	STORE, 94382607683584, 94382607687679,
		4107	STORE, 94382607687680, 94382607695871,
		4108	STORE, 140252451454976, 140252451627007,
		4109	ERASE, 140252451454976, 140252451454976,
		4110	STORE, 140252451454976, 140252451459071,
		4111	STORE, 140252451459072, 140252451627007,
		4112	ERASE, 140252451459072, 140252451459072,
		4113	STORE, 140252451459072, 140252451581951,
		4114	STORE, 140252451581952, 140252451614719,
		4115	STORE, 140252451614720, 140252451622911,
		4116	STORE, 140252451622912, 140252451627007,
		4117	STORE, 140730013548544, 140730013552639,
		4118	STORE, 140730013536256, 140730013548543,
		4119	STORE, 47380343541760, 47380343549951,
		4120	STORE, 47380343549952, 47380343558143,
		4121	STORE, 47380343558144, 47380345397247,
		4122	STORE, 47380343697408, 47380345397247,
		4123	STORE, 47380343558144, 47380343697407,
		4124	ERASE, 47380343697408, 47380343697408,
		4125	STORE, 47380343697408, 47380345356287,
		4126	STORE, 47380345356288, 47380345397247,
		4127	STORE, 47380345040896, 47380345356287,
		4128	STORE, 47380343697408, 47380345040895,
		4129	ERASE, 47380343697408, 47380343697408,
		4130	STORE, 47380343697408, 47380345040895,
		4131	STORE, 47380345352192, 47380345356287,
		4132	STORE, 47380345040896, 47380345352191,
		4133	ERASE, 47380345040896, 47380345040896,
		4134	STORE, 47380345040896, 47380345352191,
		4135	STORE, 47380345380864, 47380345397247,
		4136	STORE, 47380345356288, 47380345380863,
		4137	ERASE, 47380345356288, 47380345356288,
		4138	STORE, 47380345356288, 47380345380863,
		4139	ERASE, 47380345380864, 47380345380864,
		4140	STORE, 47380345380864, 47380345397247,
		4141	ERASE, 47380345356288, 47380345356288,
		4142	STORE, 47380345356288, 47380345372671,
		4143	STORE, 47380345372672, 47380345380863,
		4144	ERASE, 94382607687680, 94382607687680,
		4145	STORE, 94382607687680, 94382607691775,
		4146	STORE, 94382607691776, 94382607695871,
		4147	ERASE, 140252451614720, 140252451614720,
		4148	STORE, 140252451614720, 140252451618815,
		4149	STORE, 140252451618816, 140252451622911,
		4150	ERASE, 47380343541760, 47380343541760,
		4151	STORE, 94382626803712, 94382626938879,
		4152	STORE, 140737488347136, 140737488351231,
		4153	STORE, 140730900271104, 140737488351231,
		4154	ERASE, 140730900271104, 140730900271104,
		4155	STORE, 140730900271104, 140730900275199,
		4156	STORE, 93855478120448, 93855478337535,
		4157	ERASE, 93855478120448, 93855478120448,
		4158	STORE, 93855478120448, 93855478198271,
		4159	STORE, 93855478198272, 93855478337535,
		4160	ERASE, 93855478198272, 93855478198272,
		4161	STORE, 93855478198272, 93855478243327,
		4162	STORE, 93855478243328, 93855478288383,
		4163	STORE, 93855478288384, 93855478337535,
		4164	STORE, 140092686573568, 140092686745599,
		4165	ERASE, 140092686573568, 140092686573568,
		4166	STORE, 140092686573568, 140092686577663,
		4167	STORE, 140092686577664, 140092686745599,
		4168	ERASE, 140092686577664, 140092686577664,
		4169	STORE, 140092686577664, 140092686700543,
		4170	STORE, 140092686700544, 140092686733311,
		4171	STORE, 140092686733312, 140092686741503,
		4172	STORE, 140092686741504, 140092686745599,
		4173	STORE, 140730900537344, 140730900541439,
		4174	STORE, 140730900525056, 140730900537343,
		4175	STORE, 47540108423168, 47540108431359,
		4176	STORE, 47540108431360, 47540108439551,
		4177	STORE, 47540108439552, 47540110278655,
		4178	STORE, 47540108578816, 47540110278655,
		4179	STORE, 47540108439552, 47540108578815,
		4180	ERASE, 47540108578816, 47540108578816,
		4181	STORE, 47540108578816, 47540110237695,
		4182	STORE, 47540110237696, 47540110278655,
		4183	STORE, 47540109922304, 47540110237695,
		4184	STORE, 47540108578816, 47540109922303,
		4185	ERASE, 47540108578816, 47540108578816,
		4186	STORE, 47540108578816, 47540109922303,
		4187	STORE, 47540110233600, 47540110237695,
		4188	STORE, 47540109922304, 47540110233599,
		4189	ERASE, 47540109922304, 47540109922304,
		4190	STORE, 47540109922304, 47540110233599,
		4191	STORE, 47540110262272, 47540110278655,
		4192	STORE, 47540110237696, 47540110262271,
		4193	ERASE, 47540110237696, 47540110237696,
		4194	STORE, 47540110237696, 47540110262271,
		4195	ERASE, 47540110262272, 47540110262272,
		4196	STORE, 47540110262272, 47540110278655,
		4197	ERASE, 47540110237696, 47540110237696,
		4198	STORE, 47540110237696, 47540110254079,
		4199	STORE, 47540110254080, 47540110262271,
		4200	ERASE, 93855478288384, 93855478288384,
		4201	STORE, 93855478288384, 93855478333439,
		4202	STORE, 93855478333440, 93855478337535,
		4203	ERASE, 140092686733312, 140092686733312,
		4204	STORE, 140092686733312, 140092686737407,
		4205	STORE, 140092686737408, 140092686741503,
		4206	ERASE, 47540108423168, 47540108423168,
		4207	STORE, 93855492222976, 93855492358143,
		4208	STORE, 93855492222976, 93855492493311,
		4209	STORE, 140737488347136, 140737488351231,
		4210	STORE, 140733498146816, 140737488351231,
		4211	ERASE, 140733498146816, 140733498146816,
		4212	STORE, 140733498146816, 140733498150911,
		4213	STORE, 94170739654656, 94170740367359,
		4214	ERASE, 94170739654656, 94170739654656,
		4215	STORE, 94170739654656, 94170739703807,
		4216	STORE, 94170739703808, 94170740367359,
		4217	ERASE, 94170739703808, 94170739703808,
		4218	STORE, 94170739703808, 94170740248575,
		4219	STORE, 94170740248576, 94170740346879,
		4220	STORE, 94170740346880, 94170740367359,
		4221	STORE, 140024788877312, 140024789049343,
		4222	ERASE, 140024788877312, 140024788877312,
		4223	STORE, 140024788877312, 140024788881407,
		4224	STORE, 140024788881408, 140024789049343,
		4225	ERASE, 140024788881408, 140024788881408,
		4226	STORE, 140024788881408, 140024789004287,
		4227	STORE, 140024789004288, 140024789037055,
		4228	STORE, 140024789037056, 140024789045247,
		4229	STORE, 140024789045248, 140024789049343,
		4230	STORE, 140733499023360, 140733499027455,
		4231	STORE, 140733499011072, 140733499023359,
		4232	STORE, 47608006119424, 47608006127615,
		4233	STORE, 47608006127616, 47608006135807,
		4234	STORE, 47608006135808, 47608006242303,
		4235	STORE, 47608006152192, 47608006242303,
		4236	STORE, 47608006135808, 47608006152191,
		4237	ERASE, 47608006152192, 47608006152192,
		4238	STORE, 47608006152192, 47608006225919,
		4239	STORE, 47608006225920, 47608006242303,
		4240	STORE, 47608006205440, 47608006225919,
		4241	STORE, 47608006152192, 47608006205439,
		4242	ERASE, 47608006152192, 47608006152192,
		4243	STORE, 47608006152192, 47608006205439,
		4244	STORE, 47608006221824, 47608006225919,
		4245	STORE, 47608006205440, 47608006221823,
		4246	ERASE, 47608006205440, 47608006205440,
		4247	STORE, 47608006205440, 47608006221823,
		4248	STORE, 47608006234112, 47608006242303,
		4249	STORE, 47608006225920, 47608006234111,
		4250	ERASE, 47608006225920, 47608006225920,
		4251	STORE, 47608006225920, 47608006234111,
		4252	ERASE, 47608006234112, 47608006234112,
		4253	STORE, 47608006234112, 47608006242303,
		4254	STORE, 47608006242304, 47608008081407,
		4255	STORE, 47608006381568, 47608008081407,
		4256	STORE, 47608006242304, 47608006381567,
		4257	ERASE, 47608006381568, 47608006381568,
		4258	STORE, 47608006381568, 47608008040447,
		4259	STORE, 47608008040448, 47608008081407,
		4260	STORE, 47608007725056, 47608008040447,
		4261	STORE, 47608006381568, 47608007725055,
		4262	ERASE, 47608006381568, 47608006381568,
		4263	STORE, 47608006381568, 47608007725055,
		4264	STORE, 47608008036352, 47608008040447,
		4265	STORE, 47608007725056, 47608008036351,
		4266	ERASE, 47608007725056, 47608007725056,
		4267	STORE, 47608007725056, 47608008036351,
		4268	STORE, 47608008065024, 47608008081407,
		4269	STORE, 47608008040448, 47608008065023,
		4270	ERASE, 47608008040448, 47608008040448,
		4271	STORE, 47608008040448, 47608008065023,
		4272	ERASE, 47608008065024, 47608008065024,
		4273	STORE, 47608008065024, 47608008081407,
		4274	STORE, 47608008065024, 47608008093695,
		4275	ERASE, 47608008040448, 47608008040448,
		4276	STORE, 47608008040448, 47608008056831,
		4277	STORE, 47608008056832, 47608008065023,
		4278	ERASE, 47608006225920, 47608006225920,
		4279	STORE, 47608006225920, 47608006230015,
		4280	STORE, 47608006230016, 47608006234111,
		4281	ERASE, 94170740346880, 94170740346880,
		4282	STORE, 94170740346880, 94170740363263,
		4283	STORE, 94170740363264, 94170740367359,
		4284	ERASE, 140024789037056, 140024789037056,
		4285	STORE, 140024789037056, 140024789041151,
		4286	STORE, 140024789041152, 140024789045247,
		4287	ERASE, 47608006119424, 47608006119424,
		4288	STORE, 140737488347136, 140737488351231,
		4289	STORE, 140730264326144, 140737488351231,
		4290	ERASE, 140730264326144, 140730264326144,
		4291	STORE, 140730264326144, 140730264330239,
		4292	STORE, 94653216407552, 94653217120255,
		4293	ERASE, 94653216407552, 94653216407552,
		4294	STORE, 94653216407552, 94653216456703,
		4295	STORE, 94653216456704, 94653217120255,
		4296	ERASE, 94653216456704, 94653216456704,
		4297	STORE, 94653216456704, 94653217001471,
		4298	STORE, 94653217001472, 94653217099775,
		4299	STORE, 94653217099776, 94653217120255,
		4300	STORE, 140103617011712, 140103617183743,
		4301	ERASE, 140103617011712, 140103617011712,
		4302	STORE, 140103617011712, 140103617015807,
		4303	STORE, 140103617015808, 140103617183743,
		4304	ERASE, 140103617015808, 140103617015808,
		4305	STORE, 140103617015808, 140103617138687,
		4306	STORE, 140103617138688, 140103617171455,
		4307	STORE, 140103617171456, 140103617179647,
		4308	STORE, 140103617179648, 140103617183743,
		4309	STORE, 140730265427968, 140730265432063,
		4310	STORE, 140730265415680, 140730265427967,
		4311	STORE, 47529177985024, 47529177993215,
		4312	STORE, 47529177993216, 47529178001407,
		4313	STORE, 47529178001408, 47529178107903,
		4314	STORE, 47529178017792, 47529178107903,
		4315	STORE, 47529178001408, 47529178017791,
		4316	ERASE, 47529178017792, 47529178017792,
		4317	STORE, 47529178017792, 47529178091519,
		4318	STORE, 47529178091520, 47529178107903,
		4319	STORE, 47529178071040, 47529178091519,
		4320	STORE, 47529178017792, 47529178071039,
		4321	ERASE, 47529178017792, 47529178017792,
		4322	STORE, 47529178017792, 47529178071039,
		4323	STORE, 47529178087424, 47529178091519,
		4324	STORE, 47529178071040, 47529178087423,
		4325	ERASE, 47529178071040, 47529178071040,
		4326	STORE, 47529178071040, 47529178087423,
		4327	STORE, 47529178099712, 47529178107903,
		4328	STORE, 47529178091520, 47529178099711,
		4329	ERASE, 47529178091520, 47529178091520,
		4330	STORE, 47529178091520, 47529178099711,
		4331	ERASE, 47529178099712, 47529178099712,
		4332	STORE, 47529178099712, 47529178107903,
		4333	STORE, 47529178107904, 47529179947007,
		4334	STORE, 47529178247168, 47529179947007,
		4335	STORE, 47529178107904, 47529178247167,
		4336	ERASE, 47529178247168, 47529178247168,
		4337	STORE, 47529178247168, 47529179906047,
		4338	STORE, 47529179906048, 47529179947007,
		4339	STORE, 47529179590656, 47529179906047,
		4340	STORE, 47529178247168, 47529179590655,
		4341	ERASE, 47529178247168, 47529178247168,
		4342	STORE, 47529178247168, 47529179590655,
		4343	STORE, 47529179901952, 47529179906047,
		4344	STORE, 47529179590656, 47529179901951,
		4345	ERASE, 47529179590656, 47529179590656,
		4346	STORE, 47529179590656, 47529179901951,
		4347	STORE, 47529179930624, 47529179947007,
		4348	STORE, 47529179906048, 47529179930623,
		4349	ERASE, 47529179906048, 47529179906048,
		4350	STORE, 47529179906048, 47529179930623,
		4351	ERASE, 47529179930624, 47529179930624,
		4352	STORE, 47529179930624, 47529179947007,
		4353	STORE, 47529179930624, 47529179959295,
		4354	ERASE, 47529179906048, 47529179906048,
		4355	STORE, 47529179906048, 47529179922431,
		4356	STORE, 47529179922432, 47529179930623,
		4357	ERASE, 47529178091520, 47529178091520,
		4358	STORE, 47529178091520, 47529178095615,
		4359	STORE, 47529178095616, 47529178099711,
		4360	ERASE, 94653217099776, 94653217099776,
		4361	STORE, 94653217099776, 94653217116159,
		4362	STORE, 94653217116160, 94653217120255,
		4363	ERASE, 140103617171456, 140103617171456,
		4364	STORE, 140103617171456, 140103617175551,
		4365	STORE, 140103617175552, 140103617179647,
		4366	ERASE, 47529177985024, 47529177985024,
		4367	STORE, 94653241135104, 94653241270271,
		4368	STORE, 140737488347136, 140737488351231,
		4369	STORE, 140736284549120, 140737488351231,
		4370	ERASE, 140736284549120, 140736284549120,
		4371	STORE, 140736284549120, 140736284553215,
		4372	STORE, 93963663822848, 93963664506879,
		4373	ERASE, 93963663822848, 93963663822848,
		4374	STORE, 93963663822848, 93963663884287,
		4375	STORE, 93963663884288, 93963664506879,
		4376	ERASE, 93963663884288, 93963663884288,
		4377	STORE, 93963663884288, 93963664240639,
		4378	STORE, 93963664240640, 93963664379903,
		4379	STORE, 93963664379904, 93963664506879,
		4380	STORE, 140450188439552, 140450188611583,
		4381	ERASE, 140450188439552, 140450188439552,
		4382	STORE, 140450188439552, 140450188443647,
		4383	STORE, 140450188443648, 140450188611583,
		4384	ERASE, 140450188443648, 140450188443648,
		4385	STORE, 140450188443648, 140450188566527,
		4386	STORE, 140450188566528, 140450188599295,
		4387	STORE, 140450188599296, 140450188607487,
		4388	STORE, 140450188607488, 140450188611583,
		4389	STORE, 140736284577792, 140736284581887,
		4390	STORE, 140736284565504, 140736284577791,
		4391	STORE, 47182606557184, 47182606565375,
		4392	STORE, 47182606565376, 47182606573567,
		4393	STORE, 47182606573568, 47182608412671,
		4394	STORE, 47182606712832, 47182608412671,
		4395	STORE, 47182606573568, 47182606712831,
		4396	ERASE, 47182606712832, 47182606712832,
		4397	STORE, 47182606712832, 47182608371711,
		4398	STORE, 47182608371712, 47182608412671,
		4399	STORE, 47182608056320, 47182608371711,
		4400	STORE, 47182606712832, 47182608056319,
		4401	ERASE, 47182606712832, 47182606712832,
		4402	STORE, 47182606712832, 47182608056319,
		4403	STORE, 47182608367616, 47182608371711,
		4404	STORE, 47182608056320, 47182608367615,
		4405	ERASE, 47182608056320, 47182608056320,
		4406	STORE, 47182608056320, 47182608367615,
		4407	STORE, 47182608396288, 47182608412671,
		4408	STORE, 47182608371712, 47182608396287,
		4409	ERASE, 47182608371712, 47182608371712,
		4410	STORE, 47182608371712, 47182608396287,
		4411	ERASE, 47182608396288, 47182608396288,
		4412	STORE, 47182608396288, 47182608412671,
		4413	STORE, 47182608412672, 47182608523263,
		4414	STORE, 47182608429056, 47182608523263,
		4415	STORE, 47182608412672, 47182608429055,
		4416	ERASE, 47182608429056, 47182608429056,
		4417	STORE, 47182608429056, 47182608515071,
		4418	STORE, 47182608515072, 47182608523263,
		4419	STORE, 47182608490496, 47182608515071,
		4420	STORE, 47182608429056, 47182608490495,
		4421	ERASE, 47182608429056, 47182608429056,
		4422	STORE, 47182608429056, 47182608490495,
		4423	STORE, 47182608510976, 47182608515071,
		4424	STORE, 47182608490496, 47182608510975,
		4425	ERASE, 47182608490496, 47182608490496,
		4426	STORE, 47182608490496, 47182608510975,
		4427	ERASE, 47182608515072, 47182608515072,
		4428	STORE, 47182608515072, 47182608523263,
		4429	STORE, 47182608523264, 47182608568319,
		4430	ERASE, 47182608523264, 47182608523264,
		4431	STORE, 47182608523264, 47182608531455,
		4432	STORE, 47182608531456, 47182608568319,
		4433	STORE, 47182608551936, 47182608568319,
		4434	STORE, 47182608531456, 47182608551935,
		4435	ERASE, 47182608531456, 47182608531456,
		4436	STORE, 47182608531456, 47182608551935,
		4437	STORE, 47182608560128, 47182608568319,
		4438	STORE, 47182608551936, 47182608560127,
		4439	ERASE, 47182608551936, 47182608551936,
		4440	STORE, 47182608551936, 47182608568319,
		4441	ERASE, 47182608551936, 47182608551936,
		4442	STORE, 47182608551936, 47182608560127,
		4443	STORE, 47182608560128, 47182608568319,
		4444	ERASE, 47182608560128, 47182608560128,
		4445	STORE, 47182608560128, 47182608568319,
		4446	STORE, 47182608568320, 47182608916479,
		4447	STORE, 47182608609280, 47182608916479,
		4448	STORE, 47182608568320, 47182608609279,
		4449	ERASE, 47182608609280, 47182608609280,
		4450	STORE, 47182608609280, 47182608891903,
		4451	STORE, 47182608891904, 47182608916479,
		4452	STORE, 47182608822272, 47182608891903,
		4453	STORE, 47182608609280, 47182608822271,
		4454	ERASE, 47182608609280, 47182608609280,
		4455	STORE, 47182608609280, 47182608822271,
		4456	STORE, 47182608887808, 47182608891903,
		4457	STORE, 47182608822272, 47182608887807,
		4458	ERASE, 47182608822272, 47182608822272,
		4459	STORE, 47182608822272, 47182608887807,
		4460	ERASE, 47182608891904, 47182608891904,
		4461	STORE, 47182608891904, 47182608916479,
		4462	STORE, 47182608916480, 47182611177471,
		4463	STORE, 47182609068032, 47182611177471,
		4464	STORE, 47182608916480, 47182609068031,
		4465	ERASE, 47182609068032, 47182609068032,
		4466	STORE, 47182609068032, 47182611161087,
		4467	STORE, 47182611161088, 47182611177471,
		4468	STORE, 47182611169280, 47182611177471,
		4469	STORE, 47182611161088, 47182611169279,
		4470	ERASE, 47182611161088, 47182611161088,
		4471	STORE, 47182611161088, 47182611169279,
		4472	ERASE, 47182611169280, 47182611169280,
		4473	STORE, 47182611169280, 47182611177471,
		4474	STORE, 47182611177472, 47182611312639,
		4475	ERASE, 47182611177472, 47182611177472,
		4476	STORE, 47182611177472, 47182611202047,
		4477	STORE, 47182611202048, 47182611312639,
		4478	STORE, 47182611263488, 47182611312639,
		4479	STORE, 47182611202048, 47182611263487,
		4480	ERASE, 47182611202048, 47182611202048,
		4481	STORE, 47182611202048, 47182611263487,
		4482	STORE, 47182611288064, 47182611312639,
		4483	STORE, 47182611263488, 47182611288063,
		4484	ERASE, 47182611263488, 47182611263488,
		4485	STORE, 47182611263488, 47182611312639,
		4486	ERASE, 47182611263488, 47182611263488,
		4487	STORE, 47182611263488, 47182611288063,
		4488	STORE, 47182611288064, 47182611312639,
		4489	STORE, 47182611296256, 47182611312639,
		4490	STORE, 47182611288064, 47182611296255,
		4491	ERASE, 47182611288064, 47182611288064,
		4492	STORE, 47182611288064, 47182611296255,
		4493	ERASE, 47182611296256, 47182611296256,
		4494	STORE, 47182611296256, 47182611312639,
		4495	STORE, 47182611296256, 47182611320831,
		4496	STORE, 47182611320832, 47182611484671,
		4497	ERASE, 47182611320832, 47182611320832,
		4498	STORE, 47182611320832, 47182611333119,
		4499	STORE, 47182611333120, 47182611484671,
		4500	STORE, 47182611431424, 47182611484671,
		4501	STORE, 47182611333120, 47182611431423,
		4502	ERASE, 47182611333120, 47182611333120,
		4503	STORE, 47182611333120, 47182611431423,
		4504	STORE, 47182611476480, 47182611484671,
		4505	STORE, 47182611431424, 47182611476479,
		4506	ERASE, 47182611431424, 47182611431424,
		4507	STORE, 47182611431424, 47182611484671,
		4508	ERASE, 47182611431424, 47182611431424,
		4509	STORE, 47182611431424, 47182611476479,
		4510	STORE, 47182611476480, 47182611484671,
		4511	ERASE, 47182611476480, 47182611476480,
		4512	STORE, 47182611476480, 47182611484671,
		4513	STORE, 47182611484672, 47182612082687,
		4514	STORE, 47182611603456, 47182612082687,
		4515	STORE, 47182611484672, 47182611603455,
		4516	ERASE, 47182611603456, 47182611603456,
		4517	STORE, 47182611603456, 47182612029439,
		4518	STORE, 47182612029440, 47182612082687,
		4519	STORE, 47182611918848, 47182612029439,
		4520	STORE, 47182611603456, 47182611918847,
		4521	ERASE, 47182611603456, 47182611603456,
		4522	STORE, 47182611603456, 47182611918847,
		4523	STORE, 47182612025344, 47182612029439,
		4524	STORE, 47182611918848, 47182612025343,
		4525	ERASE, 47182611918848, 47182611918848,
		4526	STORE, 47182611918848, 47182612025343,
		4527	ERASE, 47182612029440, 47182612029440,
		4528	STORE, 47182612029440, 47182612082687,
		4529	STORE, 47182612082688, 47182615134207,
		4530	STORE, 47182612627456, 47182615134207,
		4531	STORE, 47182612082688, 47182612627455,
		4532	ERASE, 47182612627456, 47182612627456,
		4533	STORE, 47182612627456, 47182614913023,
		4534	STORE, 47182614913024, 47182615134207,
		4535	STORE, 47182614323200, 47182614913023,
		4536	STORE, 47182612627456, 47182614323199,
		4537	ERASE, 47182612627456, 47182612627456,
		4538	STORE, 47182612627456, 47182614323199,
		4539	STORE, 47182614908928, 47182614913023,
		4540	STORE, 47182614323200, 47182614908927,
		4541	ERASE, 47182614323200, 47182614323200,
		4542	STORE, 47182614323200, 47182614908927,
		4543	STORE, 47182615117824, 47182615134207,
		4544	STORE, 47182614913024, 47182615117823,
		4545	ERASE, 47182614913024, 47182614913024,
		4546	STORE, 47182614913024, 47182615117823,
		4547	ERASE, 47182615117824, 47182615117824,
		4548	STORE, 47182615117824, 47182615134207,
		4549	STORE, 47182615134208, 47182615166975,
		4550	ERASE, 47182615134208, 47182615134208,
		4551	STORE, 47182615134208, 47182615142399,
		4552	STORE, 47182615142400, 47182615166975,
		4553	STORE, 47182615154688, 47182615166975,
		4554	STORE, 47182615142400, 47182615154687,
		4555	ERASE, 47182615142400, 47182615142400,
		4556	STORE, 47182615142400, 47182615154687,
		4557	STORE, 47182615158784, 47182615166975,
		4558	STORE, 47182615154688, 47182615158783,
		4559	ERASE, 47182615154688, 47182615154688,
		4560	STORE, 47182615154688, 47182615166975,
		4561	ERASE, 47182615154688, 47182615154688,
		4562	STORE, 47182615154688, 47182615158783,
		4563	STORE, 47182615158784, 47182615166975,
		4564	ERASE, 47182615158784, 47182615158784,
		4565	STORE, 47182615158784, 47182615166975,
		4566	STORE, 47182615166976, 47182615203839,
		4567	ERASE, 47182615166976, 47182615166976,
		4568	STORE, 47182615166976, 47182615175167,
		4569	STORE, 47182615175168, 47182615203839,
		4570	STORE, 47182615191552, 47182615203839,
		4571	STORE, 47182615175168, 47182615191551,
		4572	ERASE, 47182615175168, 47182615175168,
		4573	STORE, 47182615175168, 47182615191551,
		4574	STORE, 47182615195648, 47182615203839,
		4575	STORE, 47182615191552, 47182615195647,
		4576	ERASE, 47182615191552, 47182615191552,
		4577	STORE, 47182615191552, 47182615203839,
		4578	ERASE, 47182615191552, 47182615191552,
		4579	STORE, 47182615191552, 47182615195647,
		4580	STORE, 47182615195648, 47182615203839,
		4581	ERASE, 47182615195648, 47182615195648,
		4582	STORE, 47182615195648, 47182615203839,
		4583	STORE, 47182615203840, 47182615678975,
		4584	ERASE, 47182615203840, 47182615203840,
		4585	STORE, 47182615203840, 47182615212031,
		4586	STORE, 47182615212032, 47182615678975,
		4587	STORE, 47182615547904, 47182615678975,
		4588	STORE, 47182615212032, 47182615547903,
		4589	ERASE, 47182615212032, 47182615212032,
		4590	STORE, 47182615212032, 47182615547903,
		4591	STORE, 47182615670784, 47182615678975,
		4592	STORE, 47182615547904, 47182615670783,
		4593	ERASE, 47182615547904, 47182615547904,
		4594	STORE, 47182615547904, 47182615678975,
		4595	ERASE, 47182615547904, 47182615547904,
		4596	STORE, 47182615547904, 47182615670783,
		4597	STORE, 47182615670784, 47182615678975,
		4598	ERASE, 47182615670784, 47182615670784,
		4599	STORE, 47182615670784, 47182615678975,
		4600	STORE, 47182615678976, 47182615687167,
		4601	STORE, 47182615687168, 47182615707647,
		4602	ERASE, 47182615687168, 47182615687168,
		4603	STORE, 47182615687168, 47182615691263,
		4604	STORE, 47182615691264, 47182615707647,
		4605	STORE, 47182615695360, 47182615707647,
		4606	STORE, 47182615691264, 47182615695359,
		4607	ERASE, 47182615691264, 47182615691264,
		4608	STORE, 47182615691264, 47182615695359,
		4609	STORE, 47182615699456, 47182615707647,
		4610	STORE, 47182615695360, 47182615699455,
		4611	ERASE, 47182615695360, 47182615695360,
		4612	STORE, 47182615695360, 47182615707647,
		4613	ERASE, 47182615695360, 47182615695360,
		4614	STORE, 47182615695360, 47182615699455,
		4615	STORE, 47182615699456, 47182615707647,
		4616	ERASE, 47182615699456, 47182615699456,
		4617	STORE, 47182615699456, 47182615707647,
		4618	STORE, 47182615707648, 47182615715839,
		4619	ERASE, 47182608371712, 47182608371712,
		4620	STORE, 47182608371712, 47182608388095,
		4621	STORE, 47182608388096, 47182608396287,
		4622	ERASE, 47182615699456, 47182615699456,
		4623	STORE, 47182615699456, 47182615703551,
		4624	STORE, 47182615703552, 47182615707647,
		4625	ERASE, 47182611288064, 47182611288064,
		4626	STORE, 47182611288064, 47182611292159,
		4627	STORE, 47182611292160, 47182611296255,
		4628	ERASE, 47182615670784, 47182615670784,
		4629	STORE, 47182615670784, 47182615674879,
		4630	STORE, 47182615674880, 47182615678975,
		4631	ERASE, 47182615195648, 47182615195648,
		4632	STORE, 47182615195648, 47182615199743,
		4633	STORE, 47182615199744, 47182615203839,
		4634	ERASE, 47182615158784, 47182615158784,
		4635	STORE, 47182615158784, 47182615162879,
		4636	STORE, 47182615162880, 47182615166975,
		4637	ERASE, 47182614913024, 47182614913024,
		4638	STORE, 47182614913024, 47182615109631,
		4639	STORE, 47182615109632, 47182615117823,
		4640	ERASE, 47182612029440, 47182612029440,
		4641	STORE, 47182612029440, 47182612066303,
		4642	STORE, 47182612066304, 47182612082687,
		4643	ERASE, 47182611476480, 47182611476480,
		4644	STORE, 47182611476480, 47182611480575,
		4645	STORE, 47182611480576, 47182611484671,
		4646	ERASE, 47182611161088, 47182611161088,
		4647	STORE, 47182611161088, 47182611165183,
		4648	STORE, 47182611165184, 47182611169279,
		4649	ERASE, 47182608891904, 47182608891904,
		4650	STORE, 47182608891904, 47182608912383,
		4651	STORE, 47182608912384, 47182608916479,
		4652	ERASE, 47182608560128, 47182608560128,
		4653	STORE, 47182608560128, 47182608564223,
		4654	STORE, 47182608564224, 47182608568319,
		4655	ERASE, 47182608515072, 47182608515072,
		4656	STORE, 47182608515072, 47182608519167,
		4657	STORE, 47182608519168, 47182608523263,
		4658	ERASE, 93963664379904, 93963664379904,
		4659	STORE, 93963664379904, 93963664502783,
		4660	STORE, 93963664502784, 93963664506879,
		4661	ERASE, 140450188599296, 140450188599296,
		4662	STORE, 140450188599296, 140450188603391,
		4663	STORE, 140450188603392, 140450188607487,
		4664	ERASE, 47182606557184, 47182606557184,
		4665	STORE, 93963694723072, 93963694858239,
		4666	STORE, 140737488347136, 140737488351231,
		4667	STORE, 140730313261056, 140737488351231,
		4668	ERASE, 140730313261056, 140730313261056,
		4669	STORE, 140730313261056, 140730313265151,
		4670	STORE, 94386579017728, 94386579697663,
		4671	ERASE, 94386579017728, 94386579017728,
		4672	STORE, 94386579017728, 94386579083263,
		4673	STORE, 94386579083264, 94386579697663,
		4674	ERASE, 94386579083264, 94386579083264,
		4675	STORE, 94386579083264, 94386579431423,
		4676	STORE, 94386579431424, 94386579570687,
		4677	STORE, 94386579570688, 94386579697663,
		4678	STORE, 140124810838016, 140124811010047,
		4679	ERASE, 140124810838016, 140124810838016,
		4680	STORE, 140124810838016, 140124810842111,
		4681	STORE, 140124810842112, 140124811010047,
		4682	ERASE, 140124810842112, 140124810842112,
		4683	STORE, 140124810842112, 140124810964991,
		4684	STORE, 140124810964992, 140124810997759,
		4685	STORE, 140124810997760, 140124811005951,
		4686	STORE, 140124811005952, 140124811010047,
		4687	STORE, 140730313601024, 140730313605119,
		4688	STORE, 140730313588736, 140730313601023,
		4689	STORE, 47507984158720, 47507984166911,
		4690	STORE, 47507984166912, 47507984175103,
		4691	STORE, 47507984175104, 47507986014207,
		4692	STORE, 47507984314368, 47507986014207,
		4693	STORE, 47507984175104, 47507984314367,
		4694	ERASE, 47507984314368, 47507984314368,
		4695	STORE, 47507984314368, 47507985973247,
		4696	STORE, 47507985973248, 47507986014207,

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tools/testing/selftests/bpf/verifier/ref_tracking.c+36−0

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tools/testing/selftests/net/io_uring_zerocopy_tx.sh+1−1

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tools/testing/selftests/net/udpgro.sh+2−2

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tools/testing/selftests/net/udpgro_bench.sh+1−1

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tools/testing/selftests/net/udpgro_frglist.sh+1−1

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tools/testing/selftests/netfilter/rpath.sh+8−6

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@@ -183,7 +183,7 @@ static int idxd_setup_wqs(struct idxd_device *idxd) · 182 unmodified lines
183	init_completion(&wq->wq_dead);	183	init_completion(&wq->wq_dead);
184	init_completion(&wq->wq_resurrect);	184	init_completion(&wq->wq_resurrect);
185	wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;	185	wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
186	wq->max_batch_size = WQ_DEFAULT_MAX_BATCH;	186	idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
187	wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;	187	wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
188	wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));	188	wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
189	if (!wq->wqcfg) {	189	if (!wq->wqcfg) {
@@ -418,7 +418,7 @@ static void idxd_read_caps(struct idxd_device *idxd) · 228 unmodified lines
418		418
419	idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;	419	idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
420	dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);	420	dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
421	idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift;	421	idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift);
422	dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);	422	dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
423	if (idxd->hw.gen_cap.config_en)	423	if (idxd->hw.gen_cap.config_en)
424	set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);	424	set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);

@@ -54,14 +54,14 @@ · 53 unmodified lines
54	#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team	54	#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
55	#define PPSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version	55	#define PPSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
56	#define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version	56	#define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version
57	#define PPSMC_MSG_EnableGfxOff 0x04 ///< Enable GFXOFF	57	#define PPSMC_MSG_SPARE0 0x04 ///< SPARE
58	#define PPSMC_MSG_DisableGfxOff 0x05 ///< Disable GFXOFF	58	#define PPSMC_MSG_SPARE1 0x05 ///< SPARE
59	#define PPSMC_MSG_PowerDownVcn 0x06 ///< Power down VCN	59	#define PPSMC_MSG_PowerDownVcn 0x06 ///< Power down VCN
60	#define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by default	60	#define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by default
61	#define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless display	61	#define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless display
62	#define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz	62	#define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
63	#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Needs update	63	#define PPSMC_MSG_SPARE2 0x0A ///< SPARE
64	#define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF	64	#define PPSMC_MSG_SPARE3 0x0B ///< SPARE
65	#define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload	65	#define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
66	#define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer	66	#define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer
67	#define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer	67	#define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer
@@ -73,8 +73,7 @@ · 5 unmodified lines
73	#define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK	73	#define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
74	#define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)	74	#define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)
75		75
76		76	#define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
77	#define PPSMC_MSG_EnableGfxImu 0x16 ///< Needs update
78		77
79	#define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency	78	#define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
80	#define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency	79	#define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
@@ -102,8 +101,8 @@ · 21 unmodified lines
102	#define PPSMC_MSG_SetHardMinIspxclkByFreq 0x2C ///< Set HardMin by frequency for ISPXCLK	101	#define PPSMC_MSG_SetHardMinIspxclkByFreq 0x2C ///< Set HardMin by frequency for ISPXCLK
103	#define PPSMC_MSG_PowerDownUmsch 0x2D ///< Power down VCN.UMSCH (aka VSCH) scheduler	102	#define PPSMC_MSG_PowerDownUmsch 0x2D ///< Power down VCN.UMSCH (aka VSCH) scheduler
104	#define PPSMC_MSG_PowerUpUmsch 0x2E ///< Power up VCN.UMSCH (aka VSCH) scheduler	103	#define PPSMC_MSG_PowerUpUmsch 0x2E ///< Power up VCN.UMSCH (aka VSCH) scheduler
105	#define PPSMC_Message_IspStutterOn_MmhubPgDis 0x2F ///< ISP StutterOn mmHub PgDis	104	#define PPSMC_MSG_IspStutterOn_MmhubPgDis 0x2F ///< ISP StutterOn mmHub PgDis
106	#define PPSMC_Message_IspStutterOff_MmhubPgEn 0x30 ///< ISP StufferOff mmHub PgEn	105	#define PPSMC_MSG_IspStutterOff_MmhubPgEn 0x30 ///< ISP StufferOff mmHub PgEn
107		106
108	#define PPSMC_Message_Count 0x31 ///< Total number of PPSMC messages	107	#define PPSMC_Message_Count 0x31 ///< Total number of PPSMC messages
109	/** @}*/	108	/** @}*/