In some benchmarks and some CPU architectures, writing the CQE on a full cache line size improves performance by saving memory access operations (read-modify-write) relative to partial cache line change. This patch lets the user to configure the device to pad the CQE up to 128B in case its content is less than 128B. Currently the driver supports only padding for a CQE size of 128B.
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| @@ -206,6 +206,7 @@ struct mlx5_ib_striding_rq_caps { · 205 unmodified lines | |||
| 206 | enum mlx5_ib_query_dev_resp_flags { | 206 | enum mlx5_ib_query_dev_resp_flags { |
| 207 | /* Support 128B CQE compression */ | 207 | /* Support 128B CQE compression */ |
| 208 | MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, | 208 | MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, |
| 209 | MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, | ||
| 209 | }; | 210 | }; |
| 210 | 211 | ||
| 211 | struct mlx5_ib_query_device_resp { | 212 | struct mlx5_ib_query_device_resp { |
| @@ -221,13 +222,17 @@ struct mlx5_ib_query_device_resp { · 9 unmodified lines | |||
| 221 | struct mlx5_ib_striding_rq_caps striding_rq_caps; | 222 | struct mlx5_ib_striding_rq_caps striding_rq_caps; |
| 222 | }; | 223 | }; |
| 223 | 224 | ||
| 225 | enum mlx5_ib_create_cq_flags { | ||
| 226 | MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, | ||
| 227 | }; | ||
| 228 | |||
| 224 | struct mlx5_ib_create_cq { | 229 | struct mlx5_ib_create_cq { |
| 225 | __u64 buf_addr; | 230 | __u64 buf_addr; |
| 226 | __u64 db_addr; | 231 | __u64 db_addr; |
| 227 | __u32 cqe_size; | 232 | __u32 cqe_size; |
| 228 | __u8 cqe_comp_en; | 233 | __u8 cqe_comp_en; |
| 229 | __u8 cqe_comp_res_format; | 234 | __u8 cqe_comp_res_format; |
| 230 | __u16 reserved; /* explicit padding (optional on i386) */ | 235 | __u16 flags; |
| 231 | }; | 236 | }; |
| 232 | 237 | ||
| 233 | struct mlx5_ib_create_cq_resp { | 238 | struct mlx5_ib_create_cq_resp { |