Since the default DMA ops for arm64 are non-coherent, mark the X-Gene controller explicitly as dma-coherent to avoid additional cache maintenance.
Unified · Split
| @@ -24,6 +24,7 @@ Required properties: · 23 unmodified lines | |||
| 24 | * "sata-phy" for the SATA 6.0Gbps PHY | 24 | * "sata-phy" for the SATA 6.0Gbps PHY |
| 25 | 25 | ||
| 26 | Optional properties: | 26 | Optional properties: |
| 27 | - dma-coherent : Present if dma operations are coherent | ||
| 27 | - status : Shall be "ok" if enabled or "disabled" if disabled. | 28 | - status : Shall be "ok" if enabled or "disabled" if disabled. |
| 28 | Default is "ok". | 29 | Default is "ok". |
| 29 | 30 | ||
| @@ -55,6 +56,7 @@ Example: · 25 unmodified lines | |||
| 55 | <0x0 0x1f22e000 0x0 0x1000>, | 56 | <0x0 0x1f22e000 0x0 0x1000>, |
| 56 | <0x0 0x1f227000 0x0 0x1000>; | 57 | <0x0 0x1f227000 0x0 0x1000>; |
| 57 | interrupts = <0x0 0x87 0x4>; | 58 | interrupts = <0x0 0x87 0x4>; |
| 59 | dma-coherent; | ||
| 58 | status = "ok"; | 60 | status = "ok"; |
| 59 | clocks = <&sataclk 0>; | 61 | clocks = <&sataclk 0>; |
| 60 | phys = <&phy2 0>; | 62 | phys = <&phy2 0>; |
| @@ -69,6 +71,7 @@ Example: · 8 unmodified lines | |||
| 69 | <0x0 0x1f23e000 0x0 0x1000>, | 71 | <0x0 0x1f23e000 0x0 0x1000>, |
| 70 | <0x0 0x1f237000 0x0 0x1000>; | 72 | <0x0 0x1f237000 0x0 0x1000>; |
| 71 | interrupts = <0x0 0x88 0x4>; | 73 | interrupts = <0x0 0x88 0x4>; |
| 74 | dma-coherent; | ||
| 72 | status = "ok"; | 75 | status = "ok"; |
| 73 | clocks = <&sataclk 0>; | 76 | clocks = <&sataclk 0>; |
| 74 | phys = <&phy3 0>; | 77 | phys = <&phy3 0>; |
| @@ -307,6 +307,7 @@ · 306 unmodified lines | |||
| 307 | <0x0 0x1f21e000 0x0 0x1000>, | 307 | <0x0 0x1f21e000 0x0 0x1000>, |
| 308 | <0x0 0x1f217000 0x0 0x1000>; | 308 | <0x0 0x1f217000 0x0 0x1000>; |
| 309 | interrupts = <0x0 0x86 0x4>; | 309 | interrupts = <0x0 0x86 0x4>; |
| 310 | dma-coherent; | ||
| 310 | status = "disabled"; | 311 | status = "disabled"; |
| 311 | clocks = <&sata01clk 0>; | 312 | clocks = <&sata01clk 0>; |
| 312 | phys = <&phy1 0>; | 313 | phys = <&phy1 0>; |
| @@ -321,6 +322,7 @@ · 8 unmodified lines | |||
| 321 | <0x0 0x1f22e000 0x0 0x1000>, | 322 | <0x0 0x1f22e000 0x0 0x1000>, |
| 322 | <0x0 0x1f227000 0x0 0x1000>; | 323 | <0x0 0x1f227000 0x0 0x1000>; |
| 323 | interrupts = <0x0 0x87 0x4>; | 324 | interrupts = <0x0 0x87 0x4>; |
| 325 | dma-coherent; | ||
| 324 | status = "ok"; | 326 | status = "ok"; |
| 325 | clocks = <&sata23clk 0>; | 327 | clocks = <&sata23clk 0>; |
| 326 | phys = <&phy2 0>; | 328 | phys = <&phy2 0>; |
| @@ -334,6 +336,7 @@ · 7 unmodified lines | |||
| 334 | <0x0 0x1f23d000 0x0 0x1000>, | 336 | <0x0 0x1f23d000 0x0 0x1000>, |
| 335 | <0x0 0x1f23e000 0x0 0x1000>; | 337 | <0x0 0x1f23e000 0x0 0x1000>; |
| 336 | interrupts = <0x0 0x88 0x4>; | 338 | interrupts = <0x0 0x88 0x4>; |
| 339 | dma-coherent; | ||
| 337 | status = "ok"; | 340 | status = "ok"; |
| 338 | clocks = <&sata45clk 0>; | 341 | clocks = <&sata45clk 0>; |
| 339 | phys = <&phy3 0>; | 342 | phys = <&phy3 0>; |