Pull RDMA subsystem updates from Jason Gunthorpe: "Overall this cycle did not have any major excitement, and did not require any shared branch with netdev. Lots of driver updates, particularly of the scale-up and performance variety. The largest body of core work was Parav's patches fixing and restructing some of the core code to make way for future RDMA containerization. Summary: - misc small driver fixups to bnxt_re/hfi1/qib/hns/ocrdma/rdmavt/vmw_pvrdma/nes - several major feature adds to bnxt_re driver: SRIOV VF RoCE support, HugePages support, extended hardware stats support, and SRQ support - a notable number of fixes to the i40iw driver from debugging scale up testing - more work to enable the new hip08 chip in the hns driver - misc small ULP fixups to srp/srpt//ipoib - preparation for srp initiator and target to support the RDMA-CM protocol for connections - add RDMA-CM support to srp initiator, srp target is still a WIP - fixes for a couple of places where ipoib could spam the dmesg log - fix encode/decode of FDR/EDR data rates in the core - many patches from Parav with ongoing work to clean up inconsistencies and bugs in RoCE support around the rdma_cm - mlx5 driver support for the userspace features 'thread domain', 'wallclock timestamps' and 'DV Direct Connected transport'. Support for the firmware dual port rocee capability - core support for more than 32 rdma devices in the char dev allocation - kernel doc updates from Randy Dunlap - new netlink uAPI for inspecting RDMA objects similar in spirit to 'ss' - one minor change to the kobject code acked by Greg KH" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (259 commits) RDMA/nldev: Provide detailed QP information RDMA/nldev: Provide global resource utilization RDMA/core: Add resource tracking for create and destroy PDs RDMA/core: Add resource tracking for create and destroy CQs RDMA/core: Add resource tracking for create and destroy QPs RDMA/restrack: Add general infrastructure to track RDMA resources RDMA/core: Save kernel caller name when creating PD and CQ objects RDMA/core: Use the MODNAME instead of the function name for pd callers RDMA: Move enum ib_cq_creation_flags to uapi headers IB/rxe: Change RDMA_RXE kconfig to use select IB/qib: remove qib_keys.c IB/mthca: remove mthca_user.h RDMA/cm: Fix access to uninitialized variable RDMA/cma: Use existing netif_is_bond_master function IB/core: Avoid SGID attributes query while converting GID from OPA to IB RDMA/mlx5: Avoid memory leak in case of XRCD dealloc failure IB/umad: Fix use of unprotected device pointer IB/iser: Combine substrings for three messages IB/iser: Delete an unnecessary variable initialisation in iser_send_data_out() IB/iser: Delete an error message for a failed memory allocation in iser_send_data_out() ...
Showing the changes to include/uapi (6 of 187 files). Show all
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| @@ -82,6 +82,15 @@ struct bnxt_re_qp_resp { · 81 unmodified lines | ||
| 82 | 82 | __u32 rsvd; |
| 83 | 83 | }; |
| 84 | 84 | |
| 85 | +struct bnxt_re_srq_req { | |
| 86 | + __u64 srqva; | |
| 87 | + __u64 srq_handle; | |
| 88 | +}; | |
| 89 | + | |
| 90 | +struct bnxt_re_srq_resp { | |
| 91 | + __u32 srqid; | |
| 92 | +}; | |
| 93 | + | |
| 85 | 94 | enum bnxt_re_shpg_offt { |
| 86 | 95 | BNXT_RE_BEG_RESV_OFFT = 0x00, |
| 87 | 96 | BNXT_RE_AVID_OFFT = 0x10, |
| @@ -402,13 +402,18 @@ struct ib_uverbs_create_cq { · 401 unmodified lines | ||
| 402 | 402 | __u64 driver_data[0]; |
| 403 | 403 | }; |
| 404 | 404 | |
| 405 | +enum ib_uverbs_ex_create_cq_flags { | |
| 406 | + IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION = 1 << 0, | |
| 407 | + IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN = 1 << 1, | |
| 408 | +}; | |
| 409 | + | |
| 405 | 410 | struct ib_uverbs_ex_create_cq { |
| 406 | 411 | __u64 user_handle; |
| 407 | 412 | __u32 cqe; |
| 408 | 413 | __u32 comp_vector; |
| 409 | 414 | __s32 comp_channel; |
| 410 | 415 | __u32 comp_mask; |
| 411 | − __u32 flags; | |
| 416 | + __u32 flags; /* bitmask of ib_uverbs_ex_create_cq_flags */ | |
| 412 | 417 | __u32 reserved; |
| 413 | 418 | }; |
| 414 | 419 | |
| @@ -449,7 +454,7 @@ struct ib_uverbs_wc { · 34 unmodified lines | ||
| 449 | 454 | __u32 vendor_err; |
| 450 | 455 | __u32 byte_len; |
| 451 | 456 | union { |
| 452 | − __u32 imm_data; | |
| 457 | + __be32 imm_data; | |
| 453 | 458 | __u32 invalidate_rkey; |
| 454 | 459 | } ex; |
| 455 | 460 | __u32 qp_num; |
| @@ -765,7 +770,7 @@ struct ib_uverbs_send_wr { · 309 unmodified lines | ||
| 765 | 770 | __u32 opcode; |
| 766 | 771 | __u32 send_flags; |
| 767 | 772 | union { |
| 768 | − __u32 imm_data; | |
| 773 | + __be32 imm_data; | |
| 769 | 774 | __u32 invalidate_rkey; |
| 770 | 775 | } ex; |
| 771 | 776 | union { |
| @@ -97,8 +97,8 @@ struct mlx4_ib_create_srq_resp { · 96 unmodified lines | ||
| 97 | 97 | }; |
| 98 | 98 | |
| 99 | 99 | struct mlx4_ib_create_qp_rss { |
| 100 | − __u64 rx_hash_fields_mask; | |
| 101 | − __u8 rx_hash_function; | |
| 100 | + __u64 rx_hash_fields_mask; /* Use enum mlx4_ib_rx_hash_fields */ | |
| 101 | + __u8 rx_hash_function; /* Use enum mlx4_ib_rx_hash_function_flags */ | |
| 102 | 102 | __u8 reserved[7]; |
| 103 | 103 | __u8 rx_hash_key[40]; |
| 104 | 104 | __u32 comp_mask; |
| @@ -152,7 +152,8 @@ enum mlx4_ib_rx_hash_fields { · 47 unmodified lines | ||
| 152 | 152 | MLX4_IB_RX_HASH_SRC_PORT_TCP = 1 << 4, |
| 153 | 153 | MLX4_IB_RX_HASH_DST_PORT_TCP = 1 << 5, |
| 154 | 154 | MLX4_IB_RX_HASH_SRC_PORT_UDP = 1 << 6, |
| 155 | − MLX4_IB_RX_HASH_DST_PORT_UDP = 1 << 7 | |
| 155 | + MLX4_IB_RX_HASH_DST_PORT_UDP = 1 << 7, | |
| 156 | + MLX4_IB_RX_HASH_INNER = 1ULL << 31, | |
| 156 | 157 | }; |
| 157 | 158 | |
| 158 | 159 | #endif /* MLX4_ABI_USER_H */ |
| @@ -41,6 +41,9 @@ enum { · 40 unmodified lines | ||
| 41 | 41 | MLX5_QP_FLAG_SIGNATURE = 1 << 0, |
| 42 | 42 | MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, |
| 43 | 43 | MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, |
| 44 | + MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, | |
| 45 | + MLX5_QP_FLAG_TYPE_DCT = 1 << 4, | |
| 46 | + MLX5_QP_FLAG_TYPE_DCI = 1 << 5, | |
| 44 | 47 | }; |
| 45 | 48 | |
| 46 | 49 | enum { |
| @@ -121,10 +124,12 @@ struct mlx5_ib_alloc_ucontext_resp { · 74 unmodified lines | ||
| 121 | 124 | __u8 cqe_version; |
| 122 | 125 | __u8 cmds_supp_uhw; |
| 123 | 126 | __u8 eth_min_inline; |
| 124 | − __u8 reserved2; | |
| 127 | + __u8 clock_info_versions; | |
| 125 | 128 | __u64 hca_core_clock_offset; |
| 126 | 129 | __u32 log_uar_size; |
| 127 | 130 | __u32 num_uars_per_page; |
| 131 | + __u32 num_dyn_bfregs; | |
| 132 | + __u32 reserved3; | |
| 128 | 133 | }; |
| 129 | 134 | |
| 130 | 135 | struct mlx5_ib_alloc_pd_resp { |
| @@ -280,8 +285,11 @@ struct mlx5_ib_create_qp { · 149 unmodified lines | ||
| 280 | 285 | __u32 rq_wqe_shift; |
| 281 | 286 | __u32 flags; |
| 282 | 287 | __u32 uidx; |
| 283 | − __u32 reserved0; | |
| 284 | − __u64 sq_buf_addr; | |
| 288 | + __u32 bfreg_index; | |
| 289 | + union { | |
| 290 | + __u64 sq_buf_addr; | |
| 291 | + __u64 access_key; | |
| 292 | + }; | |
| 285 | 293 | }; |
| 286 | 294 | |
| 287 | 295 | /* RX Hash function flags */ |
| @@ -307,7 +315,7 @@ enum mlx5_rx_hash_fields { · 19 unmodified lines | ||
| 307 | 315 | MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, |
| 308 | 316 | MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, |
| 309 | 317 | /* Save bits for future fields */ |
| 310 | − MLX5_RX_HASH_INNER = 1 << 31 | |
| 318 | + MLX5_RX_HASH_INNER = (1UL << 31), | |
| 311 | 319 | }; |
| 312 | 320 | |
| 313 | 321 | struct mlx5_ib_create_qp_rss { |
| @@ -354,6 +362,11 @@ struct mlx5_ib_create_ah_resp { · 40 unmodified lines | ||
| 354 | 362 | __u8 reserved[6]; |
| 355 | 363 | }; |
| 356 | 364 | |
| 365 | +struct mlx5_ib_modify_qp_resp { | |
| 366 | + __u32 response_length; | |
| 367 | + __u32 dctn; | |
| 368 | +}; | |
| 369 | + | |
| 357 | 370 | struct mlx5_ib_create_wq_resp { |
| 358 | 371 | __u32 response_length; |
| 359 | 372 | __u32 reserved; |
| @@ -368,4 +381,36 @@ struct mlx5_ib_modify_wq { · 8 unmodified lines | ||
| 368 | 381 | __u32 comp_mask; |
| 369 | 382 | __u32 reserved; |
| 370 | 383 | }; |
| 384 | + | |
| 385 | +struct mlx5_ib_clock_info { | |
| 386 | + __u32 sign; | |
| 387 | + __u32 resv; | |
| 388 | + __u64 nsec; | |
| 389 | + __u64 cycles; | |
| 390 | + __u64 frac; | |
| 391 | + __u32 mult; | |
| 392 | + __u32 shift; | |
| 393 | + __u64 mask; | |
| 394 | + __u64 overflow_period; | |
| 395 | +}; | |
| 396 | + | |
| 397 | +enum mlx5_ib_mmap_cmd { | |
| 398 | + MLX5_IB_MMAP_REGULAR_PAGE = 0, | |
| 399 | + MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, | |
| 400 | + MLX5_IB_MMAP_WC_PAGE = 2, | |
| 401 | + MLX5_IB_MMAP_NC_PAGE = 3, | |
| 402 | + /* 5 is chosen in order to be compatible with old versions of libmlx5 */ | |
| 403 | + MLX5_IB_MMAP_CORE_CLOCK = 5, | |
| 404 | + MLX5_IB_MMAP_ALLOC_WC = 6, | |
| 405 | + MLX5_IB_MMAP_CLOCK_INFO = 7, | |
| 406 | +}; | |
| 407 | + | |
| 408 | +enum { | |
| 409 | + MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, | |
| 410 | +}; | |
| 411 | + | |
| 412 | +/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ | |
| 413 | +enum { | |
| 414 | + MLX5_IB_CLOCK_INFO_V1 = 0, | |
| 415 | +}; | |
| 371 | 416 | #endif /* MLX5_ABI_USER_H */ |
| @@ -236,6 +236,10 @@ enum rdma_nldev_command { · 235 unmodified lines | ||
| 236 | 236 | RDMA_NLDEV_CMD_PORT_NEW, |
| 237 | 237 | RDMA_NLDEV_CMD_PORT_DEL, |
| 238 | 238 | |
| 239 | + RDMA_NLDEV_CMD_RES_GET, /* can dump */ | |
| 240 | + | |
| 241 | + RDMA_NLDEV_CMD_RES_QP_GET, /* can dump */ | |
| 242 | + | |
| 239 | 243 | RDMA_NLDEV_NUM_OPS |
| 240 | 244 | }; |
| 241 | 245 | |
| @@ -303,6 +307,51 @@ enum rdma_nldev_attr { · 61 unmodified lines | ||
| 303 | 307 | |
| 304 | 308 | RDMA_NLDEV_ATTR_DEV_NODE_TYPE, /* u8 */ |
| 305 | 309 | |
| 310 | + RDMA_NLDEV_ATTR_RES_SUMMARY, /* nested table */ | |
| 311 | + RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY, /* nested table */ | |
| 312 | + RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_NAME, /* string */ | |
| 313 | + RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_CURR, /* u64 */ | |
| 314 | + | |
| 315 | + RDMA_NLDEV_ATTR_RES_QP, /* nested table */ | |
| 316 | + RDMA_NLDEV_ATTR_RES_QP_ENTRY, /* nested table */ | |
| 317 | + /* | |
| 318 | + * Local QPN | |
| 319 | + */ | |
| 320 | + RDMA_NLDEV_ATTR_RES_LQPN, /* u32 */ | |
| 321 | + /* | |
| 322 | + * Remote QPN, | |
| 323 | + * Applicable for RC and UC only IBTA 11.2.5.3 QUERY QUEUE PAIR | |
| 324 | + */ | |
| 325 | + RDMA_NLDEV_ATTR_RES_RQPN, /* u32 */ | |
| 326 | + /* | |
| 327 | + * Receive Queue PSN, | |
| 328 | + * Applicable for RC and UC only 11.2.5.3 QUERY QUEUE PAIR | |
| 329 | + */ | |
| 330 | + RDMA_NLDEV_ATTR_RES_RQ_PSN, /* u32 */ | |
| 331 | + /* | |
| 332 | + * Send Queue PSN | |
| 333 | + */ | |
| 334 | + RDMA_NLDEV_ATTR_RES_SQ_PSN, /* u32 */ | |
| 335 | + RDMA_NLDEV_ATTR_RES_PATH_MIG_STATE, /* u8 */ | |
| 336 | + /* | |
| 337 | + * QP types as visible to RDMA/core, the reserved QPT | |
| 338 | + * are not exported through this interface. | |
| 339 | + */ | |
| 340 | + RDMA_NLDEV_ATTR_RES_TYPE, /* u8 */ | |
| 341 | + RDMA_NLDEV_ATTR_RES_STATE, /* u8 */ | |
| 342 | + /* | |
| 343 | + * Process ID which created object, | |
| 344 | + * in case of kernel origin, PID won't exist. | |
| 345 | + */ | |
| 346 | + RDMA_NLDEV_ATTR_RES_PID, /* u32 */ | |
| 347 | + /* | |
| 348 | + * The name of process created following resource. | |
| 349 | + * It will exist only for kernel objects. | |
| 350 | + * For user created objects, the user is supposed | |
| 351 | + * to read /proc/PID/comm file. | |
| 352 | + */ | |
| 353 | + RDMA_NLDEV_ATTR_RES_KERN_NAME, /* string */ | |
| 354 | + | |
| 306 | 355 | RDMA_NLDEV_ATTR_MAX |
| 307 | 356 | }; |
| 308 | 357 | #endif /* _UAPI_RDMA_NETLINK_H */ |
| @@ -52,12 +52,14 @@ · 51 unmodified lines | ||
| 52 | 52 | #define PVRDMA_UVERBS_ABI_VERSION 3 /* ABI Version. */ |
| 53 | 53 | #define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF /* Bottom 24 bits. */ |
| 54 | 54 | #define PVRDMA_UAR_QP_OFFSET 0 /* QP doorbell. */ |
| 55 | −#define PVRDMA_UAR_QP_SEND BIT(30) /* Send bit. */ | |
| 56 | −#define PVRDMA_UAR_QP_RECV BIT(31) /* Recv bit. */ | |
| 55 | +#define PVRDMA_UAR_QP_SEND (1 << 30) /* Send bit. */ | |
| 56 | +#define PVRDMA_UAR_QP_RECV (1 << 31) /* Recv bit. */ | |
| 57 | 57 | #define PVRDMA_UAR_CQ_OFFSET 4 /* CQ doorbell. */ |
| 58 | −#define PVRDMA_UAR_CQ_ARM_SOL BIT(29) /* Arm solicited bit. */ | |
| 59 | −#define PVRDMA_UAR_CQ_ARM BIT(30) /* Arm bit. */ | |
| 60 | −#define PVRDMA_UAR_CQ_POLL BIT(31) /* Poll bit. */ | |
| 58 | +#define PVRDMA_UAR_CQ_ARM_SOL (1 << 29) /* Arm solicited bit. */ | |
| 59 | +#define PVRDMA_UAR_CQ_ARM (1 << 30) /* Arm bit. */ | |
| 60 | +#define PVRDMA_UAR_CQ_POLL (1 << 31) /* Poll bit. */ | |
| 61 | +#define PVRDMA_UAR_SRQ_OFFSET 8 /* SRQ doorbell. */ | |
| 62 | +#define PVRDMA_UAR_SRQ_RECV (1 << 30) /* Recv bit. */ | |
| 61 | 63 | |
| 62 | 64 | enum pvrdma_wr_opcode { |
| 63 | 65 | PVRDMA_WR_RDMA_WRITE, |