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drm/amd: define new gfx12 uapi flags

define new gfx12 uapi flags

Aurabindo Pillai committed 2 years ago

Commit 7d09d801 parent 7ceb94e1 file · +13 −1Browse files

Showing the changes to include/uapi (1 of 1 file). Show all

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include/uapi/drm/amdgpu_drm.h+13−1
@@ -392,7 +392,7 @@ struct drm_amdgpu_gem_userptr { · 391 unmodified lines
392#define AMDGPU_TILING_NUM_BANKS_SHIFT 21392#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
393#define AMDGPU_TILING_NUM_BANKS_MASK 0x3393#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
394 394
395/* GFX9 and later: */395/* GFX9 - GFX11: */
396#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0396#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
397#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f397#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
398#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5398#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
@@ -406,6 +406,17 @@ struct drm_amdgpu_gem_userptr { · 7 unmodified lines
406#define AMDGPU_TILING_SCANOUT_SHIFT 63406#define AMDGPU_TILING_SCANOUT_SHIFT 63
407#define AMDGPU_TILING_SCANOUT_MASK 0x1407#define AMDGPU_TILING_SCANOUT_MASK 0x1
408 408
409/* GFX12 and later: */
410#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0
411#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7
412/* These are DCC recompression setting for memory management: */
413#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
414#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
415#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5
416#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
417#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8
418#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
419
409/* Set/Get helpers for tiling flags. */420/* Set/Get helpers for tiling flags. */
410#define AMDGPU_TILING_SET(field, value) \421#define AMDGPU_TILING_SET(field, value) \
411 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)422 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
@@ -1268,6 +1279,7 @@ struct drm_amdgpu_info_gpuvm_fault { · 856 unmodified lines
1268#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */1279#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
1269#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */1280#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
1270#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */1281#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
1282#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
1271 1283
1272#if defined(__cplusplus)1284#if defined(__cplusplus)
1273}1285}