AMD IOMMU Extended Feature (EFR) and Extended Feature 2 (EFR2) registers specify features supported by each IOMMU hardware instance. The IOMMU driver checks each feature-specific bits before enabling each feature at run time. For IOMMUFD, the hypervisor passes the raw value of amd_iommu_efr and amd_iommu_efr2 to VMM via iommufd IOMMU_DEVICE_GET_HW_INFO ioctl.
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| @@ -623,6 +623,32 @@ struct iommu_hw_info_tegra241_cmdqv { · 622 unmodified lines | ||
| 623 | 623 | __u8 __reserved; |
| 624 | 624 | }; |
| 625 | 625 | |
| 626 | +/** | |
| 627 | + * struct iommu_hw_info_amd - AMD IOMMU device info | |
| 628 | + * | |
| 629 | + * @efr : Value of AMD IOMMU Extended Feature Register (EFR) | |
| 630 | + * @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2) | |
| 631 | + * | |
| 632 | + * Please See description of these registers in the following sections of | |
| 633 | + * the AMD I/O Virtualization Technology (IOMMU) Specification. | |
| 634 | + * (https://docs.amd.com/v/u/en-US/48882_3.10_PUB) | |
| 635 | + * | |
| 636 | + * - MMIO Offset 0030h IOMMU Extended Feature Register | |
| 637 | + * - MMIO Offset 01A0h IOMMU Extended Feature 2 Register | |
| 638 | + * | |
| 639 | + * Note: The EFR and EFR2 are raw values reported by hardware. | |
| 640 | + * VMM is responsible to determine the appropriate flags to be exposed to | |
| 641 | + * the VM since cetertain features are not currently supported by the kernel | |
| 642 | + * for HW-vIOMMU. | |
| 643 | + * | |
| 644 | + * Current VMM-allowed list of feature flags are: | |
| 645 | + * - EFR[GTSup, GASup, GioSup, PPRSup, EPHSup, GATS, GLX, PASmax] | |
| 646 | + */ | |
| 647 | +struct iommu_hw_info_amd { | |
| 648 | + __aligned_u64 efr; | |
| 649 | + __aligned_u64 efr2; | |
| 650 | +}; | |
| 651 | + | |
| 626 | 652 | /** |
| 627 | 653 | * enum iommu_hw_info_type - IOMMU Hardware Info Types |
| 628 | 654 | * @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware |
| @@ -632,6 +658,7 @@ struct iommu_hw_info_tegra241_cmdqv { · 3 unmodified lines | ||
| 632 | 658 | * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type |
| 633 | 659 | * @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM |
| 634 | 660 | * SMMUv3) info type |
| 661 | + * @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type | |
| 635 | 662 | */ |
| 636 | 663 | enum iommu_hw_info_type { |
| 637 | 664 | IOMMU_HW_INFO_TYPE_NONE = 0, |
| @@ -639,6 +666,7 @@ enum iommu_hw_info_type { · 1 unmodified line | ||
| 639 | 666 | IOMMU_HW_INFO_TYPE_INTEL_VTD = 1, |
| 640 | 667 | IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2, |
| 641 | 668 | IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3, |
| 669 | + IOMMU_HW_INFO_TYPE_AMD = 4, | |
| 642 | 670 | }; |
| 643 | 671 | |
| 644 | 672 | /** |