None of these registers is relevant for the userspace API.
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| @@ -366,24 +366,6 @@ · 365 unmodified lines | |||
| 366 | #define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ | 366 | #define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ |
| 367 | #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ | 367 | #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ |
| 368 | 368 | ||
| 369 | /* | ||
| 370 | * These are definitions for the Exar XR17V35X and XR17(C|D)15X | ||
| 371 | */ | ||
| 372 | #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ | ||
| 373 | #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ | ||
| 374 | #define UART_EXAR_DVID 0x8d /* Device identification */ | ||
| 375 | |||
| 376 | #define UART_EXAR_FCTR 0x08 /* Feature Control Register */ | ||
| 377 | #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */ | ||
| 378 | #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */ | ||
| 379 | #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ | ||
| 380 | #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ | ||
| 381 | #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ | ||
| 382 | #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ | ||
| 383 | |||
| 384 | #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ | ||
| 385 | #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ | ||
| 386 | |||
| 387 | /* | 369 | /* |
| 388 | * These are definitions for the Altera ALTR_16550_F32/F64/F128 | 370 | * These are definitions for the Altera ALTR_16550_F32/F64/F128 |
| 389 | * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs). | 371 | * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs). |