lael-labs/linux

Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml+9−0

@@ -24,6 +24,15 @@ properties: · 23 unmodified lines
24	maxItems: 1	24	maxItems: 1
25	description: virtual channel number of a DSI peripheral	25	description: virtual channel number of a DSI peripheral
26		26
		27	clock-names:
		28	const: refclk
		29
		30	clocks:
		31	maxItems: 1
		32	description: \|
		33	Optional external clock connected to REF_CLK input.
		34	The clock rate must be in 10..154 MHz range.
		35
27	enable-gpios:	36	enable-gpios:
28	description: Bridge EN pin, chip is reset when EN is low.	37	description: Bridge EN pin, chip is reset when EN is low.
29		38

Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml+5−0

   clock-names:
     maxItems: 2
+  resets:
+    maxItems: 1
   ports:
     $ref: /schemas/graph.yaml#/properties/ports
   - reg
   - clocks
   - clock-names
+  - resets
   - interrupts
   - ports
         clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
         clock-names = "iahb", "isfr";
         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+        resets = <&cpg 729>;
         ports {
             #address-cells = <1>;

Documentation/devicetree/bindings/display/ingenic,lcd.yaml+2−0

@@ -17,6 +17,8 @@ properties: · 16 unmodified lines
17	enum:	17	enum:
18	- ingenic,jz4740-lcd	18	- ingenic,jz4740-lcd
19	- ingenic,jz4725b-lcd	19	- ingenic,jz4725b-lcd
		20	- ingenic,jz4760-lcd
		21	- ingenic,jz4760b-lcd
20	- ingenic,jz4770-lcd	22	- ingenic,jz4770-lcd
21	- ingenic,jz4780-lcd	23	- ingenic,jz4780-lcd
22		24

Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml+116−0

@@ -0,0 +1,116 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: MediaTek Display Port Controller
	8
	9	maintainers:
	10	- Chun-Kuang Hu <chunkuang.hu@kernel.org>
	11	- Jitao shi <jitao.shi@mediatek.com>
	12
	13	description: \|
	14	MediaTek DP and eDP are different hardwares and there are some features
	15	which are not supported for eDP. For example, audio is not supported for
	16	eDP. Therefore, we need to use two different compatibles to describe them.
	17	In addition, We just need to enable the power domain of DP, so the clock
	18	of DP is generated by itself and we are not using other PLL to generate
	19	clocks.
	20
	21	properties:
	22	compatible:
	23	enum:
	24	- mediatek,mt8195-dp-tx
	25	- mediatek,mt8195-edp-tx
	26
	27	reg:
	28	maxItems: 1
	29
	30	nvmem-cells:
	31	maxItems: 1
	32	description: efuse data for display port calibration
	33
	34	nvmem-cell-names:
	35	const: dp_calibration_data
	36
	37	power-domains:
	38	maxItems: 1
	39
	40	interrupts:
	41	maxItems: 1
	42
	43	ports:
	44	$ref: /schemas/graph.yaml#/properties/ports
	45	properties:
	46	port@0:
	47	$ref: /schemas/graph.yaml#/properties/port
	48	description: Input endpoint of the controller, usually dp_intf
	49
	50	port@1:
	51	$ref: /schemas/graph.yaml#/$defs/port-base
	52	unevaluatedProperties: false
	53	description: Output endpoint of the controller
	54	properties:
	55	endpoint:
	56	$ref: /schemas/media/video-interfaces.yaml#
	57	unevaluatedProperties: false
	58	properties:
	59	data-lanes:
	60	description: \|
	61	number of lanes supported by the hardware.
	62	The possible values:
	63	0 - For 1 lane enabled in IP.
	64	0 1 - For 2 lanes enabled in IP.
	65	0 1 2 3 - For 4 lanes enabled in IP.
	66	minItems: 1
	67	maxItems: 4
	68	required:
	69	- data-lanes
	70
	71	required:
	72	- port@0
	73	- port@1
	74
	75	max-linkrate-mhz:
	76	enum: [ 1620, 2700, 5400, 8100 ]
	77	description: maximum link rate supported by the hardware.
	78
	79	required:
	80	- compatible
	81	- reg
	82	- interrupts
	83	- ports
	84	- max-linkrate-mhz
	85
	86	additionalProperties: false
	87
	88	examples:
	89	- \|
	90	#include <dt-bindings/interrupt-controller/arm-gic.h>
	91	#include <dt-bindings/power/mt8195-power.h>
	92	dptx@1c600000 {
	93	compatible = "mediatek,mt8195-dp-tx";
	94	reg = <0x1c600000 0x8000>;
	95	power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
	96	interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
	97	max-linkrate-mhz = <8100>;
	98
	99	ports {
	100	#address-cells = <1>;
	101	#size-cells = <0>;
	102
	103	port@0 {
	104	reg = <0>;
	105	dptx_in: endpoint {
	106	remote-endpoint = <&dp_intf0_out>;
	107	};
	108	};
	109	port@1 {
	110	reg = <1>;
	111	dptx_out: endpoint {
	112	data-lanes = <0 1 2 3>;
	113	};
	114	};
	115	};
	116	};

Documentation/devicetree/bindings/display/msm/dp-controller.yaml+41−6

       - qcom,sm8350-dp
   reg:
+    minItems: 4
     items:
       - description: ahb register block
       - description: aux register block
   operating-points-v2:
     maxItems: 1
+  opp-table: true
   power-domains:
     maxItems: 1
+  aux-bus:
+    $ref: /schemas/display/dp-aux-bus.yaml#
+  data-lanes:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 4
+    items:
+      maximum: 3
   "#sound-dai-cells":
     const: 0
-  vdda-0p9-supply: true
+  vdda-0p9-supply:
-  vdda-1p2-supply: true
+    deprecated: true
+  vdda-1p2-supply:
+    deprecated: true
   ports:
     $ref: /schemas/graph.yaml#/properties/ports
   - clock-names
   - phys
   - phy-names
-  - "#sound-dai-cells"
   - power-domains
   - ports
+allOf:
+  # AUX BUS does not exist on DP controllers
+  # Audio output also is present only on DP output
+  # p1 regions is present on DP, but not on eDP
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc7280-edp
+              - qcom,sc8180x-edp
+    then:
+      properties:
+        "#sound-dai-cells": false
+        reg:
+          maxItems: 4
+    else:
+      properties:
+        aux-bus: false
+        reg:
+          minItems: 5
+      required:
+        - "#sound-dai-cells"
 additionalProperties: false
 examples:
         power-domains = <&rpmhpd SC7180_CX>;
-        vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
-        vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>;
         ports {
             #address-cells = <1>;
             #size-cells = <0>;

Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml+4−0

   "^display-controller@[0-9a-f]+$":
     type: object
     description: Node containing the properties of DPU.
+    additionalProperties: false
     properties:
       compatible:
         maxItems: 1
       operating-points-v2: true
+      opp-table:
+        type: object
       ports:
         $ref: /schemas/graph.yaml#/properties/ports
         description: |

Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml+3−0

   "^display-controller@[0-9a-f]+$":
     type: object
     description: Node containing the properties of DPU.
+    additionalProperties: false
     properties:
       compatible:
         maxItems: 1
       operating-points-v2: true
+      opp-table:
+        type: object
       ports:
         $ref: /schemas/graph.yaml#/properties/ports

Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml+3−0

   "^display-controller@[0-9a-f]+$":
     type: object
     description: Node containing the properties of DPU.
+    additionalProperties: false
     properties:
       compatible:
         maxItems: 1
       operating-points-v2: true
+      opp-table:
+        type: object
       ports:
         $ref: /schemas/graph.yaml#/properties/ports

Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml+3−0

   "^display-controller@[0-9a-f]+$":
     type: object
     description: Node containing the properties of DPU.
+    additionalProperties: false
     properties:
       compatible:
         maxItems: 1
       operating-points-v2: true
+      opp-table:
+        type: object
       ports:
         $ref: /schemas/graph.yaml#/properties/ports

Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml+4−0

   "^display-controller@[0-9a-f]+$":
     type: object
     description: Node containing the properties of DPU.
+    additionalProperties: false
     properties:
       compatible:
         maxItems: 1
       operating-points-v2: true
+      opp-table:
+        type: object
       ports:
         $ref: /schemas/graph.yaml#/properties/ports
         description: |

Documentation/devicetree/bindings/display/msm/gmu.yaml+146−20

@@ -20,35 +20,24 @@ description: \| · 19 unmodified lines
20	properties:	20	properties:
21	compatible:	21	compatible:
22	items:	22	items:
23	- enum:	23	- pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
24	- qcom,adreno-gmu-630.2
25	- const: qcom,adreno-gmu	24	- const: qcom,adreno-gmu
26		25
27	reg:	26	reg:
28	items:	27	minItems: 3
29	- description: Core GMU registers	28	maxItems: 4
30	- description: GMU PDC registers
31	- description: GMU PDC sequence registers
32		29
33	reg-names:	30	reg-names:
34	items:	31	minItems: 3
35	- const: gmu	32	maxItems: 4
36	- const: gmu_pdc
37	- const: gmu_pdc_seq
38		33
39	clocks:	34	clocks:
40	items:	35	minItems: 4
41	- description: GMU clock	36	maxItems: 7
42	- description: GPU CX clock
43	- description: GPU AXI clock
44	- description: GPU MEMNOC clock
45		37
46	clock-names:	38	clock-names:
47	items:	39	minItems: 4
48	- const: gmu	40	maxItems: 7
49	- const: cxo
50	- const: axi
51	- const: memnoc
52		41
53	interrupts:	42	interrupts:
54	items:	43	items:
@@ -76,6 +65,9 @@ properties: · 21 unmodified lines
76		65
77	operating-points-v2: true	66	operating-points-v2: true
78		67
		68	opp-table:
		69	type: object
		70
79	required:	71	required:
80	- compatible	72	- compatible
81	- reg	73	- reg
@@ -91,6 +83,140 @@ required: · 9 unmodified lines
91		83
92	additionalProperties: false	84	additionalProperties: false
93		85
		86	allOf:
		87	- if:
		88	properties:
		89	compatible:
		90	contains:
		91	enum:
		92	- qcom,adreno-gmu-618.0
		93	- qcom,adreno-gmu-630.2
		94	then:
		95	properties:
		96	reg:
		97	items:
		98	- description: Core GMU registers
		99	- description: GMU PDC registers
		100	- description: GMU PDC sequence registers
		101	reg-names:
		102	items:
		103	- const: gmu
		104	- const: gmu_pdc
		105	- const: gmu_pdc_seq
		106	clocks:
		107	items:
		108	- description: GMU clock
		109	- description: GPU CX clock
		110	- description: GPU AXI clock
		111	- description: GPU MEMNOC clock
		112	clock-names:
		113	items:
		114	- const: gmu
		115	- const: cxo
		116	- const: axi
		117	- const: memnoc
		118
		119	- if:
		120	properties:
		121	compatible:
		122	contains:
		123	enum:
		124	- qcom,adreno-gmu-635.0
		125	then:
		126	properties:
		127	reg:
		128	items:
		129	- description: Core GMU registers
		130	- description: Resource controller registers
		131	- description: GMU PDC registers
		132	reg-names:
		133	items:
		134	- const: gmu
		135	- const: rscc
		136	- const: gmu_pdc
		137	clocks:
		138	items:
		139	- description: GMU clock
		140	- description: GPU CX clock
		141	- description: GPU AXI clock
		142	- description: GPU MEMNOC clock
		143	- description: GPU AHB clock
		144	- description: GPU HUB CX clock
		145	- description: GPU SMMU vote clock
		146	clock-names:
		147	items:
		148	- const: gmu
		149	- const: cxo
		150	- const: axi
		151	- const: memnoc
		152	- const: ahb
		153	- const: hub
		154	- const: smmu_vote
		155
		156	- if:
		157	properties:
		158	compatible:
		159	contains:
		160	enum:
		161	- qcom,adreno-gmu-640.1
		162	then:
		163	properties:
		164	reg:
		165	items:
		166	- description: Core GMU registers
		167	- description: GMU PDC registers
		168	- description: GMU PDC sequence registers
		169	reg-names:
		170	items:
		171	- const: gmu
		172	- const: gmu_pdc
		173	- const: gmu_pdc_seq
		174
		175	- if:
		176	properties:
		177	compatible:
		178	contains:
		179	enum:
		180	- qcom,adreno-gmu-650.2
		181	then:
		182	properties:
		183	reg:
		184	items:
		185	- description: Core GMU registers
		186	- description: Resource controller registers
		187	- description: GMU PDC registers
		188	- description: GMU PDC sequence registers
		189	reg-names:
		190	items:
		191	- const: gmu
		192	- const: rscc
		193	- const: gmu_pdc
		194	- const: gmu_pdc_seq
		195
		196	- if:
		197	properties:
		198	compatible:
		199	contains:
		200	enum:
		201	- qcom,adreno-gmu-640.1
		202	- qcom,adreno-gmu-650.2
		203	then:
		204	properties:
		205	clocks:
		206	items:
		207	- description: GPU AHB clock
		208	- description: GMU clock
		209	- description: GPU CX clock
		210	- description: GPU AXI clock
		211	- description: GPU MEMNOC clock
		212	clock-names:
		213	items:
		214	- const: ahb
		215	- const: gmu
		216	- const: cxo
		217	- const: axi
		218	- const: memnoc
		219
94	examples:	220	examples:
95	- \|	221	- \|
96	#include <dt-bindings/clock/qcom,gpucc-sdm845.h>	222	#include <dt-bindings/clock/qcom,gpucc-sdm845.h>

Documentation/devicetree/bindings/display/msm/gpu.yaml+2−1

@@ -58,7 +58,8 @@ properties: · 57 unmodified lines
58	- const: ocmem	58	- const: ocmem
59		59
60	iommus:	60	iommus:
61	maxItems: 1	61	minItems: 1
		62	maxItems: 64
62		63
63	sram:	64	sram:
64	$ref: /schemas/types.yaml#/definitions/phandle-array	65	$ref: /schemas/types.yaml#/definitions/phandle-array

Documentation/devicetree/bindings/display/msm/mdp4.yaml+1−1

@@ -36,7 +36,7 @@ properties: · 35 unmodified lines
36	maxItems: 1	36	maxItems: 1
37		37
38	iommus:	38	iommus:
39	maxItems: 1	39	maxItems: 4
40		40
41	ports:	41	ports:
42	$ref: /schemas/graph.yaml#/properties/ports	42	$ref: /schemas/graph.yaml#/properties/ports

Documentation/devicetree/bindings/display/panel/panel-simple.yaml+4−0

       - mitsubishi,aa070mc01-ca1
         # Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module
       - multi-inno,mi0700s4t-6
+        # Multi-Inno Technology Co.,Ltd MI0800FT-9 8" 800x600 TFT Resistive Touch Module
+      - multi-inno,mi0800ft-9
         # Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod.
       - multi-inno,mi1010ait-1cp
         # NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
       - samsung,atna33xc20
         # Samsung 12.2" (2560x1600 pixels) TFT LCD panel
       - samsung,lsn122dl01-c01
+        # Samsung Electronics 10.1" WXGA (1280x800) TFT LCD panel
+      - samsung,ltl101al01
         # Samsung Electronics 10.1" WSVGA TFT LCD panel
       - samsung,ltn101nt05
         # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel

Documentation/devicetree/bindings/display/panel/sitronix,st7701.yaml+4−0

   Techstar TS8550B is 480x854, 2-lane MIPI DSI LCD panel which has
   inbuilt ST7701 chip.
+  Densitron DMT028VGHMCMI-1A is 480x640, 2-lane MIPI DSI LCD panel
+  which has built-in ST7701 chip.
 allOf:
   - $ref: panel-common.yaml#
   compatible:
     items:
       - enum:
+          - densitron,dmt028vghmcmi-1a
           - techstar,ts8550b
       - const: sitronix,st7701

Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt+1−0

@@ -8,6 +8,7 @@ Required properties: · 7 unmodified lines
8	"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"	8	"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"	9	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"	10	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
		11	"rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"
11	- reg: Represent the physical address range of the controller.	12	- reg: Represent the physical address range of the controller.
12	- interrupts: Represent the controller's interrupt to the CPU(s).	13	- interrupts: Represent the controller's interrupt to the CPU(s).
13	- clocks, clock-names: Phandles to the controller's pll reference	14	- clocks, clock-names: Phandles to the controller's pll reference

Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml+12−3

       - const: hdmi_phy
   clocks:
-    maxItems: 2
+    minItems: 2
+    maxItems: 3
   clock-names:
+    minItems: 2
     items:
       - const: iface
       - const: ref
+      - const: xo
   power-domains:
     maxItems: 1
   vddio-supply:
     description: phandle to VDD I/O supply regulator
+  '#clock-cells':
+    const: 0
   '#phy-cells':
     const: 0
                   "hdmi_phy";
       clocks = <&mmcc 116>,
-               <&gcc 214>;
+               <&gcc 214>,
+               <&xo_board>;
       clock-names = "iface",
-                    "ref";
+                    "ref",
+                    "xo";
+      #clock-cells = <0>;
       #phy-cells = <0>;
       vddio-supply = <&vreg_l12a_1p8>;

Documentation/gpu/amdgpu/apu-asic-info-table.csv+8−0

@@ -0,0 +1,8 @@
	1	Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version
	2	Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3
	3	Ryzen 3000 series / AMD Ryzen Embedded V1/R1 with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
	4	Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2
	5	Ryzen 3000 series / AMD Ryzen Embedded V1/R1 with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
	6	SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1
	7	Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1
	8	Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3

Documentation/gpu/amdgpu/dgpu-asic-info-table.csv+24−0

@@ -0,0 +1,24 @@
	1	Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version
	2	AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --, 6, --, --
	3	AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
	4	AMD Radeon R7 (TM\|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, --
	5	AMD Radeon (TM) (HD\|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --
	6	AMD Radeon (TM\|R7\|R9\|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --
	7	AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE 2 / UVD 4.2, 1
	8	AMD Radeon (R9\|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1
	9	AMD Radeon (TM) R(5\|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2
	10	AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3
	11	AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
	12	Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
	13	Radeon (TM) (RX\|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
	14	Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series, POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
	15	Radeon (RX\|TM) (PRO\|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0
	16	AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD 7.2.0, 4.2.0
	17	MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2
	18	MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0
	19	AMD Radeon (RX\|Pro) 5600(M\|XT) /5700 (M\|XT\|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
	20	AMD Radeon (Pro) 5300 /5500XTB/5500(XT\|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2
	21	AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0
	22	AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2
	23	AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
	24	AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5

Documentation/gpu/amdgpu/display/dc-glossary.rst+1−1

@@ -170,7 +170,7 @@ consider asking in the amdgfx and update this page. · 169 unmodified lines
170	MC	170	MC
171	Memory Controller	171	Memory Controller
172		172
173	MPC	173	MPC/MPCC
174	Multiple pipes and plane combine	174	Multiple pipes and plane combine
175		175
176	MPO	176	MPO

Documentation/gpu/amdgpu/display/dcn-overview.rst+59−0

@@ -124,6 +124,65 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would · 123 unmodified lines
124	also apply a regamma function to introduce the gamma removed earlier back.	124	also apply a regamma function to introduce the gamma removed earlier back.
125	Eventually, we output data in integer format at DIO.	125	Eventually, we output data in integer format at DIO.
126		126
		127	AMD Hardware Pipeline
		128	---------------------
		129
		130	When discussing graphics on Linux, the pipeline term can sometimes be
		131	overloaded with multiple meanings, so it is important to define what we mean
		132	when we say pipeline. In the DCN driver, we use the term **hardware
		133	pipeline or pipeline or just pipe** as an abstraction to indicate a
		134	sequence of DCN blocks instantiated to address some specific configuration. DC
		135	core treats DCN blocks as individual resources, meaning we can build a pipeline
		136	by taking resources for all individual hardware blocks to compose one pipeline.
		137	In actuality, we can't connect an arbitrary block from one pipe to a block from
		138	another pipe; they are routed linearly, except for DSC, which can be
		139	arbitrarily assigned as needed. We have this pipeline concept for trying to
		140	optimize bandwidth utilization.
		141
		142	.. kernel-figure:: pipeline_4k_no_split.svg
		143
		144	Additionally, let's take a look at parts of the DTN log (see
		145	'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
		146	this log can help us to see part of this pipeline behavior in real-time::
		147
		148	HUBP: format addr_hi width height ...
		149	[ 0]: 8h 81h 3840 2160
		150	[ 1]: 0h 0h 0 0
		151	[ 2]: 0h 0h 0 0
		152	[ 3]: 0h 0h 0 0
		153	[ 4]: 0h 0h 0 0
		154	...
		155	MPCC: OPP DPP ...
		156	[ 0]: 0h 0h ...
		157
		158	The first thing to notice from the diagram and DTN log it is the fact that we
		159	have different clock domains for each part of the DCN blocks. In this example,
		160	we have just a single pipeline where the data flows from DCHUB to DIO, as
		161	we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and
		162	we can split this single pipe differently, as described in the below diagram:
		163
		164	.. kernel-figure:: pipeline_4k_split.svg
		165
		166	Now, if we inspect the DTN log again we can see some interesting changes::
		167
		168	HUBP: format addr_hi width height ...
		169	[ 0]: 8h 81h 1920 2160 ...
		170	...
		171	[ 4]: 0h 0h 0 0 ...
		172	[ 5]: 8h 81h 1920 2160 ...
		173	...
		174	MPCC: OPP DPP ...
		175	[ 0]: 0h 0h ...
		176	[ 5]: 0h 5h ...
		177
		178	From the above example, we now split the display pipeline into two vertical
		179	parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
		180	clock frequency in the DPP part. This is not only useful for saving power but
		181	also to better handle the required throughput. The idea to keep in mind here is
		182	that the pipe configuration can vary a lot according to the display
		183	configuration, and it is the DML's responsibility to set up all required
		184	configuration parameters for multiple scenarios supported by our hardware.
		185
127	Global Sync	186	Global Sync
128	-----------	187	-----------
129		188

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	834	style="font-size:18.6667px">color space matrix</tspan></text>
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	1043	style="font-size:18.6667px">DCN 2.0</tspan></text>
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	1054	style="font-size:18.6667px">DC Interface</tspan></text>
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	1065	style="font-size:18.6667px">DRM Interface</tspan></text>
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	1086	style="font-size:18.6667px">CNVC</tspan></text>
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	1097	style="font-size:18.6667px">Input CSC</tspan></text>
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	1108	style="font-size:18.6667px;text-align:center;text-anchor:middle">DeGamma</tspan><tspan
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	1113	id="tspan233797">RAM and ROM</tspan><tspan
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	1117	style="font-size:10.6667px;text-align:center;text-anchor:middle"
	1118	id="tspan242597">(sRGB, BT2020</tspan></text>
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	1129	style="font-size:18.6667px">HDR Multiply</tspan></text>
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	1135	id="text64469-9-6"><tspan
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	1140	style="font-size:18.6667px">Gamut Remap</tspan></text>
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	1151	style="font-size:18.6667px;text-align:center;text-anchor:middle">Shaper LUT</tspan><tspan
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	1155	style="font-size:18.6667px;text-align:center;text-anchor:middle"
	1156	id="tspan222533">RAM</tspan></text>
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	1167	style="font-size:18.6667px;text-align:center;text-anchor:middle">3D LUT</tspan><tspan
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	1172	id="tspan221121">RAM</tspan></text>
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	1228	style="font-size:18.6667px">Gamut Remap</tspan></text>
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	1239	style="font-size:18.6667px;text-align:center;text-anchor:middle">Shaper LUT</tspan><tspan
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	1255	style="font-size:18.6667px;text-align:center;text-anchor:middle">3D LUT</tspan><tspan
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	1304	style="font-size:18.6667px;text-align:center;text-anchor:middle">Shaper LUT</tspan><tspan
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	1306	x="408.74442"
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	1313	x="407.1257"
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	1316	sodipodi:role="line"
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	1318	x="407.1257"
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	1320	style="font-size:18.6667px;text-align:center;text-anchor:middle">3D LUT</tspan><tspan
	1321	sodipodi:role="line"
	1322	x="407.1257"
	1323	y="1443.5769"
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	1326	<text
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	1329	x="408.64996"
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	1332	sodipodi:role="line"
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	1334	x="408.64996"
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	1336	style="font-size:18.6667px;text-align:center;text-anchor:middle">Gamma</tspan><tspan
	1337	sodipodi:role="line"
	1338	x="408.64996"
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Documentation/gpu/amdgpu/display/display-manager.rst+141−0

@@ -40,3 +40,144 @@ Atomic Implementation · 39 unmodified lines
40		40
41	.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c	41	.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
42	:functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail	42	:functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
		43
		44	Color Management Properties
		45	===========================
		46
		47	.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
		48	:doc: overview
		49
		50	.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
		51	:internal:
		52
		53
		54	DC Color Capabilities between DCN generations
		55	---------------------------------------------
		56
		57	DRM/KMS framework defines three CRTC color correction properties: degamma,
		58	color transformation matrix (CTM) and gamma, and two properties for degamma and
		59	gamma LUT sizes. AMD DC programs some of the color correction features
		60	pre-blending but DRM/KMS has not per-plane color correction properties.
		61
		62	In general, the DRM CRTC color properties are programmed to DC, as follows:
		63	CRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is
		64	programmed after blending, it is mapped to DPP hw blocks (pre-blending). Other
		65	color caps available in the hw is not currently exposed by DRM interface and
		66	are bypassed.
		67
		68	.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
		69	:doc: color-management-caps
		70
		71	.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
		72	:internal:
		73
		74	The color pipeline has undergone major changes between DCN hardware
		75	generations. What's possible to do before and after blending depends on
		76	hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families
		77	schemas.
		78
		79	DCN 2.0 family color caps and mapping
		80
		81	.. kernel-figure:: dcn2_cm_drm_current.svg
		82
		83	DCN 3.0 family color caps and mapping
		84
		85	.. kernel-figure:: dcn3_cm_drm_current.svg
		86
		87	Blend Mode Properties
		88	=====================
		89
		90	Pixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to
		91	describes how pixels from a foreground plane (fg) are composited with the
		92	background plane (bg). Here, we present main concepts of DRM blend mode to help
		93	to understand how this property is mapped to AMD DC interface. See more about
		94	this DRM property and the alpha blending equations in :ref:`DRM Plane
		95	Composition Properties <plane_composition_properties>`.
		96
		97	Basically, a blend mode sets the alpha blending equation for plane
		98	composition that fits the mode in which the alpha channel affects the state of
		99	pixel color values and, therefore, the resulted pixel color. For
		100	example, consider the following elements of the alpha blending equation:
		101
		102	- fg.rgb: Each of the RGB component values from the foreground's pixel.
		103	- fg.alpha: Alpha component value from the foreground's pixel.
		104	- bg.rgb: Each of the RGB component values from the background.
		105	- plane_alpha: Plane alpha value set by the plane "alpha" property, see
		106	more in :ref:`DRM Plane Composition Properties <plane_composition_properties>`.
		107
		108	in the basic alpha blending equation::
		109
		110	out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb
		111
		112	the alpha channel value of each pixel in a plane is ignored and only the plane
		113	alpha affects the resulted pixel color values.
		114
		115	DRM has three blend mode to define the blend formula in the plane composition:
		116
		117	* None: Blend formula that ignores the pixel alpha.
		118
		119	* Pre-multiplied: Blend formula that assumes the pixel color values in a
		120	plane was already pre-multiplied by its own alpha channel before storage.
		121
		122	* Coverage: Blend formula that assumes the pixel color values were not
		123	pre-multiplied with the alpha channel values.
		124
		125	and pre-multiplied is the default pixel blend mode, that means, when no blend
		126	mode property is created or defined, DRM considers the plane's pixels has
		127	pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test
		128	provides a set of subtests to verify plane alpha and blend mode properties.
		129
		130	The DRM blend mode and its elements are then mapped by AMDGPU display manager
		131	(DM) to program the blending configuration of the Multiple Pipe/Plane Combined
		132	(MPC), as follows:
		133
		134	.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
		135	:doc: mpc-overview
		136
		137	.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
		138	:functions: mpcc_blnd_cfg
		139
		140	Therefore, the blending configuration for a single MPCC instance on the MPC
		141	tree is defined by :c:type:`mpcc_blnd_cfg`, where
		142	:c:type:`pre_multiplied_alpha` is the alpha pre-multiplied mode flag used to
		143	set :c:type:`MPCC_ALPHA_MULTIPLIED_MODE`. It controls whether alpha is
		144	multiplied (true/false), being only true for DRM pre-multiplied blend mode.
		145	:c:type:`mpcc_alpha_blend_mode` defines the alpha blend mode regarding pixel
		146	alpha and plane alpha values. It sets one of the three modes for
		147	:c:type:`MPCC_ALPHA_BLND_MODE`, as described below.
		148
		149	.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
		150	:functions: mpcc_alpha_blend_mode
		151
		152	DM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM
		153	blend formula, as follows:
		154
		155	* MPC pixel alpha matches DRM fg.alpha as the alpha component value
		156	from the plane's pixel
		157	* MPC global alpha matches DRM plane_alpha when the pixel alpha should
		158	be ignored and, therefore, pixel values are not pre-multiplied
		159	* MPC global gain assumes MPC global alpha value when both *DRM
		160	fg.alpha* and DRM plane_alpha participate in the blend equation
		161
		162	In short, fg.alpha is ignored by selecting
		163	:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha *
		164	fg.alpha) component becomes available by selecting
		165	:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the
		166	:c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are
		167	pre-multiplied by alpha or not.
		168
		169	Blend configuration flow
		170	------------------------
		171
		172	The alpha blending equation is configured from DRM to DC interface by the
		173	following path:
		174
		175	1. When updating a :c:type:`drm_plane_state <drm_plane_state>`, DM calls
		176	:c:type:`fill_blending_from_plane_state()` that maps
		177	:c:type:`drm_plane_state <drm_plane_state>` attributes to
		178	:c:type:`dc_plane_info <dc_plane_info>` struct to be handled in the
		179	OS-agnostic component (DC).
		180
		181	2. On DC interface, :c:type:`struct mpcc_blnd_cfg <mpcc_blnd_cfg>` programs the
		182	MPCC blend configuration considering the :c:type:`dc_plane_info
		183	<dc_plane_info>` input from DPP.

Documentation/gpu/amdgpu/display/index.rst+1−0

@@ -28,4 +28,5 @@ table of content: · 27 unmodified lines
28	display-manager.rst	28	display-manager.rst
29	dc-debug.rst	29	dc-debug.rst
30	dcn-overview.rst	30	dcn-overview.rst
		31	mpo-overview.rst
31	dc-glossary.rst	32	dc-glossary.rst

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Documentation/gpu/amdgpu/display/mpo-overview.rst+242−0

@@ -0,0 +1,242 @@
	1	========================
	2	Multiplane Overlay (MPO)
	3	========================
	4
	5	.. note:: You will get more from this page if you have already read the
	6	'Documentation/gpu/amdgpu/display/dcn-overview.rst'.
	7
	8
	9	Multiplane Overlay (MPO) allows for multiple framebuffers to be composited via
	10	fixed-function hardware in the display controller rather than using graphics or
	11	compute shaders for composition. This can yield some power savings if it means
	12	the graphics/compute pipelines can be put into low-power states. In summary,
	13	MPO can bring the following benefits:
	14
	15	* Decreased GPU and CPU workload - no composition shaders needed, no extra
	16	buffer copy needed, GPU can remain idle.
	17	* Plane independent page flips - No need to be tied to global compositor
	18	page-flip present rate, reduced latency, independent timing.
	19
	20	.. note:: Keep in mind that MPO is all about power-saving; if you want to learn
	21	more about power-save in the display context, check the link:
	22	`Power <https://gitlab.freedesktop.org/pq/color-and-hdr/-/blob/main/doc/power.rst>`__.
	23
	24	Multiplane Overlay is only available using the DRM atomic model. The atomic
	25	model only uses a single userspace IOCTL for configuring the display hardware
	26	(modesetting, page-flipping, etc) - drmModeAtomicCommit. To query hardware
	27	resources and limitations userspace also calls into drmModeGetResources which
	28	reports back the number of planes, CRTCs, and connectors. There are three types
	29	of DRM planes that the driver can register and work with:
	30
	31	* ``DRM_PLANE_TYPE_PRIMARY``: Primary planes represent a "main" plane for a
	32	CRTC, primary planes are the planes operated upon by CRTC modesetting and
	33	flipping operations.
	34	* ``DRM_PLANE_TYPE_CURSOR``: Cursor planes represent a "cursor" plane for a
	35	CRTC. Cursor planes are the planes operated upon by the cursor IOCTLs
	36	* ``DRM_PLANE_TYPE_OVERLAY``: Overlay planes represent all non-primary,
	37	non-cursor planes. Some drivers refer to these types of planes as "sprites"
	38	internally.
	39
	40	To illustrate how it works, let's take a look at a device that exposes the
	41	following planes to userspace:
	42
	43	* 4 Primary planes (1 per CRTC).
	44	* 4 Cursor planes (1 per CRTC).
	45	* 1 Overlay plane (shared among CRTCs).
	46
	47	.. note:: Keep in mind that different ASICs might expose other numbers of
	48	planes.
	49
	50	For this hardware example, we have 4 pipes (if you don't know what AMD pipe
	51	means, look at 'Documentation/gpu/amdgpu/display/dcn-overview.rst', section
	52	"AMD Hardware Pipeline"). Typically most AMD devices operate in a pipe-split
	53	configuration for optimal single display output (e.g., 2 pipes per plane).
	54
	55	A typical MPO configuration from userspace - 1 primary + 1 overlay on a single
	56	display - will see 4 pipes in use, 2 per plane.
	57
	58	At least 1 pipe must be used per plane (primary and overlay), so for this
	59	hypothetical hardware that we are using as an example, we have an absolute
	60	limit of 4 planes across all CRTCs. Atomic commits will be rejected for display
	61	configurations using more than 4 planes. Again, it is important to stress that
	62	every DCN has different restrictions; here, we are just trying to provide the
	63	concept idea.
	64
	65	Plane Restrictions
	66	==================
	67
	68	AMDGPU imposes restrictions on the use of DRM planes in the driver.
	69
	70	Atomic commits will be rejected for commits which do not follow these
	71	restrictions:
	72
	73	* Overlay planes must be in ARGB8888 or XRGB8888 format
	74	* Planes cannot be placed outside of the CRTC destination rectangle
	75	* Planes cannot be downscaled more than 1/4x of their original size
	76	* Planes cannot be upscaled more than 16x of their original size
	77
	78	Not every property is available on every plane:
	79
	80	* Only primary planes have color-space and non-RGB format support
	81	* Only overlay planes have alpha blending support
	82
	83	Cursor Restrictions
	84	===================
	85
	86	Before we start to describe some restrictions around cursor and MPO, see the
	87	below image:
	88
	89	.. kernel-figure:: mpo-cursor.svg
	90
	91	The image on the left side represents how DRM expects the cursor and planes to
	92	be blended. However, AMD hardware handles cursors differently, as you can see
	93	on the right side; basically, our cursor cannot be drawn outside its associated
	94	plane as it is being treated as part of the plane. Another consequence of that
	95	is that cursors inherit the color and scale from the plane.
	96
	97	As a result of the above behavior, do not use legacy API to set up the cursor
	98	plane when working with MPO; otherwise, you might encounter unexpected
	99	behavior.
	100
	101	In short, AMD HW has no dedicated cursor planes. A cursor is attached to
	102	another plane and therefore inherits any scaling or color processing from its
	103	parent plane.
	104
	105	Use Cases
	106	=========
	107
	108	Picture-in-Picture (PIP) playback - Underlay strategy
	109	-----------------------------------------------------
	110
	111	Video playback should be done using the "primary plane as underlay" MPO
	112	strategy. This is a 2 planes configuration:
	113
	114	* 1 YUV DRM Primary Plane (e.g. NV12 Video)
	115	* 1 RGBA DRM Overlay Plane (e.g. ARGB8888 desktop). The compositor should
	116	prepare the framebuffers for the planes as follows:
	117	- The overlay plane contains general desktop UI, video player controls, and video subtitles
	118	- Primary plane contains one or more videos
	119
	120	.. note:: Keep in mind that we could extend this configuration to more planes,
	121	but that is currently not supported by our driver yet (maybe if we have a
	122	userspace request in the future, we can change that).
	123
	124	See below a single-video example:
	125
	126	.. kernel-figure:: single-display-mpo.svg
	127
	128	.. note:: We could extend this behavior to more planes, but that is currently
	129	not supported by our driver.
	130
	131	The video buffer should be used directly for the primary plane. The video can
	132	be scaled and positioned for the desktop using the properties: CRTC_X, CRTC_Y,
	133	CRTC_W, and CRTC_H. The primary plane should also have the color encoding and
	134	color range properties set based on the source content:
	135
	136	* ``COLOR_RANGE``, ``COLOR_ENCODING``
	137
	138	The overlay plane should be the native size of the CRTC. The compositor must
	139	draw a transparent cutout for where the video should be placed on the desktop
	140	(i.e., set the alpha to zero). The primary plane video will be visible through
	141	the underlay. The overlay plane's buffer may remain static while the primary
	142	plane's framebuffer is used for standard double-buffered playback.
	143
	144	The compositor should create a YUV buffer matching the native size of the CRTC.
	145	Each video buffer should be composited onto this YUV buffer for direct YUV
	146	scanout. The primary plane should have the color encoding and color range
	147	properties set based on the source content: ``COLOR_RANGE``,
	148	``COLOR_ENCODING``. However, be mindful that the source color space and
	149	encoding match for each video since it affect the entire plane.
	150
	151	The overlay plane should be the native size of the CRTC. The compositor must
	152	draw a transparent cutout for where each video should be placed on the desktop
	153	(i.e., set the alpha to zero). The primary plane videos will be visible through
	154	the underlay. The overlay plane's buffer may remain static while compositing
	155	operations for video playback will be done on the video buffer.
	156
	157	This kernel interface is validated using IGT GPU Tools. The following tests can
	158	be run to validate positioning, blending, scaling under a variety of sequences
	159	and interactions with operations such as DPMS and S3:
	160
	161	- ``kms_plane@plane-panning-bottom-right-pipe-*-planes``
	162	- ``kms_plane@plane-panning-bottom-right-suspend-pipe-*-``
	163	- ``kms_plane@plane-panning-top-left-pipe-*-``
	164	- ``kms_plane@plane-position-covered-pipe-*-``
	165	- ``kms_plane@plane-position-hole-dpms-pipe-*-``
	166	- ``kms_plane@plane-position-hole-pipe-*-``
	167	- ``kms_plane_multiple@atomic-pipe-*-tiling-``
	168	- ``kms_plane_scaling@pipe-*-plane-scaling``
	169	- ``kms_plane_alpha_blend@pipe-*-alpha-basic``
	170	- ``kms_plane_alpha_blend@pipe-*-alpha-transparant-fb``
	171	- ``kms_plane_alpha_blend@pipe-*-alpha-opaque-fb``
	172	- ``kms_plane_alpha_blend@pipe-*-constant-alpha-min``
	173	- ``kms_plane_alpha_blend@pipe-*-constant-alpha-mid``
	174	- ``kms_plane_alpha_blend@pipe-*-constant-alpha-max``
	175
	176	Multiple Display MPO
	177	--------------------
	178
	179	AMDGPU supports display MPO when using multiple displays; however, this feature
	180	behavior heavily relies on the compositor implementation. Keep in mind that
	181	usespace can define different policies. For example, some OSes can use MPO to
	182	protect the plane that handles the video playback; notice that we don't have
	183	many limitations for a single display. Nonetheless, this manipulation can have
	184	many more restrictions for a multi-display scenario. The below example shows a
	185	video playback in the middle of two displays, and it is up to the compositor to
	186	define a policy on how to handle it:
	187
	188	.. kernel-figure:: multi-display-hdcp-mpo.svg
	189
	190	Let's discuss some of the hardware limitations we have when dealing with
	191	multi-display with MPO.
	192
	193	Limitations
	194	~~~~~~~~~~~
	195
	196	For simplicity's sake, for discussing the hardware limitation, this
	197	documentation supposes an example where we have two displays and video playback
	198	that will be moved around different displays.
	199
	200	* Hardware limitations
	201
	202	From the DCN overview page, each display requires at least one pipe and each
	203	MPO plane needs another pipe. As a result, when the video is in the middle of
	204	the two displays, we need to use 2 pipes. See the example below where we avoid
	205	pipe split:
	206
	207	- 1 display (1 pipe) + MPO (1 pipe), we will use two pipes
	208	- 2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the
	209	middle of both displays needs 2 pipes.
	210	- 3 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.
	211
	212	If we use MPO with multiple displays, the userspace has to decide to enable
	213	multiple MPO by the price of limiting the number of external displays supported
	214	or disable it in favor of multiple displays; it is a policy decision. For
	215	example:
	216
	217	* When ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPO
	218	* When ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO
	219
	220	Let's briefly explore how userspace can handle these two display configurations
	221	on an ASIC that only supports three pipes. We can have:
	222
	223	.. kernel-figure:: multi-display-hdcp-mpo-less-pipe-ex.svg
	224
	225	- Total pipes are 3
	226	- User lights up 2 displays (2 out of 3 pipes are used)
	227	- User launches video (1 pipe used for MPO)
	228	- Now, if the user moves the video in the middle of 2 displays, one part of the
	229	video won't be MPO since we have used 3/3 pipes.
	230
	231	* Scaling limitation
	232
	233	MPO cannot handle scaling less than 0.25 and more than x16. For example:
	234
	235	If 4k video (3840x2160) is playing in windowed mode, the physical size of the
	236	window cannot be smaller than (960x540).
	237
	238	.. note:: These scaling limitations might vary from ASIC to ASIC.
	239
	240	* Size Limitation
	241
	242	The minimum MPO size is 12px.

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Documentation/gpu/amdgpu/driver-misc.rst+17−0

@@ -32,6 +32,23 @@ unique_id · 31 unmodified lines
32	.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c	32	.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
33	:doc: unique_id	33	:doc: unique_id
34		34
		35	Accelerated Processing Units (APU) Info
		36	---------------------------------------
		37
		38	.. csv-table::
		39	:header-rows: 1
		40	:widths: 3, 2, 2, 1, 1, 1
		41	:file: ./apu-asic-info-table.csv
		42
		43	Discrete GPU Info
		44	-----------------
		45
		46	.. csv-table::
		47	:header-rows: 1
		48	:widths: 3, 2, 2, 1, 1, 1
		49	:file: ./dgpu-asic-info-table.csv
		50
		51
35	GPU Memory Usage Information	52	GPU Memory Usage Information
36	============================	53	============================
37		54

Documentation/gpu/amdgpu/thermal.rst+17−1

@@ -72,7 +72,8 @@ card's RLC (RunList Controller) firmware powers off the gfx engine · 71 unmodified lines
72	dynamically when there is no workload on gfx or compute pipes. GFXOFF is on by	72	dynamically when there is no workload on gfx or compute pipes. GFXOFF is on by
73	default on supported GPUs.	73	default on supported GPUs.
74		74
75	Userspace can interact with GFXOFF through a debugfs interface:	75	Userspace can interact with GFXOFF through a debugfs interface (all values in
		76	`uint32_t`, unless otherwise noted):
76		77
77	``amdgpu_gfxoff``	78	``amdgpu_gfxoff``
78	-----------------	79	-----------------
@@ -104,3 +105,18 @@ Read it to check current GFXOFF's status of a GPU:: · 25 unmodified lines
104	If GFXOFF is enabled, the value will be transitioning around [0, 3], always	105	If GFXOFF is enabled, the value will be transitioning around [0, 3], always
105	getting into 0 when possible. When it's disabled, it's always at 2. Returns	106	getting into 0 when possible. When it's disabled, it's always at 2. Returns
106	``-EINVAL`` if it's not supported.	107	``-EINVAL`` if it's not supported.
		108
		109	``amdgpu_gfxoff_count``
		110	-----------------------
		111
		112	Read it to get the total GFXOFF entry count at the time of query since system
		113	power-up. The value is an `uint64_t` type, however, due to firmware limitations,
		114	it can currently overflow as an `uint32_t`. Only supported in vangogh
		115
		116	``amdgpu_gfxoff_residency``
		117	---------------------------
		118
		119	Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop. Read it to
		120	get average GFXOFF residency % multiplied by 100 during the last logging
		121	interval. E.g. a value of 7854 means 78.54% of the time in the last logging
		122	interval the GPU was in GFXOFF mode. Only supported in vangogh

Documentation/gpu/drm-kms-helpers.rst+4−4

@@ -122,13 +122,13 @@ format Helper Functions Reference · 121 unmodified lines
122	.. kernel-doc:: drivers/gpu/drm/drm_format_helper.c	122	.. kernel-doc:: drivers/gpu/drm/drm_format_helper.c
123	:export:	123	:export:
124		124
125	Framebuffer CMA Helper Functions Reference	125	Framebuffer DMA Helper Functions Reference
126	==========================================	126	==========================================
127		127
128	.. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c	128	.. kernel-doc:: drivers/gpu/drm/drm_fb_dma_helper.c
129	:doc: framebuffer cma helper functions	129	:doc: framebuffer dma helper functions
130		130
131	.. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c	131	.. kernel-doc:: drivers/gpu/drm/drm_fb_dma_helper.c
132	:export:	132	:export:
133		133
134	Framebuffer GEM Helper Reference	134	Framebuffer GEM Helper Reference

Documentation/gpu/drm-kms.rst+2−0

@@ -532,6 +532,8 @@ Standard Plane Properties · 531 unmodified lines
532	.. kernel-doc:: drivers/gpu/drm/drm_plane.c	532	.. kernel-doc:: drivers/gpu/drm/drm_plane.c
533	:doc: standard plane properties	533	:doc: standard plane properties
534		534
		535	.. _plane_composition_properties:
		536
535	Plane Composition Properties	537	Plane Composition Properties
536	----------------------------	538	----------------------------
537		539

Documentation/gpu/drm-mm.rst+8−8

@@ -300,12 +300,12 @@ Drivers that want to map the GEM object upfront instead of handling page · 299 unmodified lines
300	faults can implement their own mmap file operation handler.	300	faults can implement their own mmap file operation handler.
301		301
302	For platforms without MMU the GEM core provides a helper method	302	For platforms without MMU the GEM core provides a helper method
303	drm_gem_cma_get_unmapped_area(). The mmap() routines will call this to get a	303	drm_gem_dma_get_unmapped_area(). The mmap() routines will call this to get a
304	proposed address for the mapping.	304	proposed address for the mapping.
305		305
306	To use drm_gem_cma_get_unmapped_area(), drivers must fill the struct	306	To use drm_gem_dma_get_unmapped_area(), drivers must fill the struct
307	:c:type:`struct file_operations <file_operations>` get_unmapped_area field with	307	:c:type:`struct file_operations <file_operations>` get_unmapped_area field with
308	a pointer on drm_gem_cma_get_unmapped_area().	308	a pointer on drm_gem_dma_get_unmapped_area().
309		309
310	More detailed information about get_unmapped_area can be found in	310	More detailed information about get_unmapped_area can be found in
311	Documentation/admin-guide/mm/nommu-mmap.rst	311	Documentation/admin-guide/mm/nommu-mmap.rst
@@ -355,16 +355,16 @@ GEM Function Reference · 43 unmodified lines
355	.. kernel-doc:: drivers/gpu/drm/drm_gem.c	355	.. kernel-doc:: drivers/gpu/drm/drm_gem.c
356	:export:	356	:export:
357		357
358	GEM CMA Helper Functions Reference	358	GEM DMA Helper Functions Reference
359	----------------------------------	359	----------------------------------
360		360
361	.. kernel-doc:: drivers/gpu/drm/drm_gem_cma_helper.c	361	.. kernel-doc:: drivers/gpu/drm/drm_gem_dma_helper.c
362	:doc: cma helpers	362	:doc: dma helpers
363		363
364	.. kernel-doc:: include/drm/drm_gem_cma_helper.h	364	.. kernel-doc:: include/drm/drm_gem_dma_helper.h
365	:internal:	365	:internal:
366		366
367	.. kernel-doc:: drivers/gpu/drm/drm_gem_cma_helper.c	367	.. kernel-doc:: drivers/gpu/drm/drm_gem_dma_helper.c
368	:export:	368	:export:
369		369
370	GEM SHMEM Helper Function Reference	370	GEM SHMEM Helper Function Reference

Documentation/gpu/todo.rst+0−36

@@ -322,18 +322,6 @@ Contact: Daniel Vetter, Noralf Tronnes · 321 unmodified lines
322		322
323	Level: Advanced	323	Level: Advanced
324		324
325	idr_init_base()
326	---------------
327
328	DRM core&drivers uses a lot of idr (integer lookup directories) for mapping
329	userspace IDs to internal objects, and in most places ID=0 means NULL and hence
330	is never used. Switching to idr_init_base() for these would make the idr more
331	efficient.
332
333	Contact: Daniel Vetter
334
335	Level: Starter
336
337	struct drm_gem_object_funcs	325	struct drm_gem_object_funcs
338	---------------------------	326	---------------------------
339		327
@@ -343,19 +331,6 @@ converted, except for struct drm_driver.gem_prime_mmap. · 3 unmodified lines
343		331
344	Level: Intermediate	332	Level: Intermediate
345		333
346	Rename CMA helpers to DMA helpers
347	---------------------------------
348
349	CMA (standing for contiguous memory allocator) is really a bit an accident of
350	what these were used for first, a much better name would be DMA helpers. In the
351	text these should even be called coherent DMA memory helpers (so maybe CDM, but
352	no one knows what that means) since underneath they just use dma_alloc_coherent.
353
354	Contact: Laurent Pinchart, Daniel Vetter
355
356	Level: Intermediate (mostly because it is a huge tasks without good partial
357	milestones, not technically itself that challenging)
358
359	connector register/unregister fixes	334	connector register/unregister fixes
360	-----------------------------------	335	-----------------------------------
361		336
@@ -617,17 +592,6 @@ Contact: Javier Martinez Canillas <javierm@redhat.com> · 255 unmodified lines
617		592
618	Level: Intermediate	593	Level: Intermediate
619		594
620	Convert Kernel Selftests (kselftest) to KUnit tests when appropriate
621	--------------------------------------------------------------------
622
623	Many of the `Kselftest <https://www.kernel.org/doc/html/latest/dev-tools/kselftest.html>`_
624	tests in DRM could be converted to Kunit tests instead, since that framework
625	is more suitable for unit testing.
626
627	Contact: Javier Martinez Canillas <javierm@redhat.com>
628
629	Level: Starter
630
631	Enable trinity for DRM	595	Enable trinity for DRM
632	----------------------	596	----------------------
633		597

Documentation/gpu/vkms.rst+1−6

 There's lots of plane features we could add support for:
-- Clearing primary plane: clear primary plane before plane composition (at the
-  start) for correctness of pixel blend ops. It also guarantees alpha channel
-  is cleared in the target buffer for stable crc. [Good to get started]
 - ARGB format on primary plane: blend the primary plane into background with
   translucent alpha.
-- Support when the primary plane isn't exactly matching the output size: blend
+- Add background color KMS property[Good to get started].
-  the primary plane into the black background.
 - Full alpha blending on all planes.

MAINTAINERS+5−0

@@ -6431,6 +6431,11 @@ S: Maintained · 6430 unmodified lines
6431	F: Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml	6431	F: Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml
6432	F: drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c	6432	F: drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
6433		6433
		6434	DRM DRIVER FOR GENERIC EDP PANELS
		6435	R: Douglas Anderson <dianders@chromium.org>
		6436	F: Documentation/devicetree/bindings/display/panel/panel-edp.yaml
		6437	F: drivers/gpu/drm/panel/panel-edp.c
		6438
6434	DRM DRIVER FOR GENERIC USB DISPLAY	6439	DRM DRIVER FOR GENERIC USB DISPLAY
6435	M: Noralf Trønnes <noralf@tronnes.org>	6440	M: Noralf Trønnes <noralf@tronnes.org>
6436	S: Maintained	6441	S: Maintained

drivers/dma-buf/dma-fence.c+13−9

 			       &dma_fence_stub_ops,
 			       &dma_fence_stub_lock,
 			       0, 0);
+		set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
+			&dma_fence_stub.flags);
 		dma_fence_signal_locked(&dma_fence_stub);
 	}
 	spin_unlock(&dma_fence_stub_lock);
 		       &dma_fence_stub_ops,
 		       &dma_fence_stub_lock,
 		       0, 0);
+	set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
+		&dma_fence_stub.flags);
 	dma_fence_signal(fence);
 	return fence;
 	__dma_fence_might_wait();
+	dma_fence_enable_sw_signaling(fence);
 	trace_dma_fence_wait_start(fence);
 	if (fence->ops->wait)
 		ret = fence->ops->wait(fence, intr, timeout);
 {
 	unsigned long flags;
-	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
-		return;
 	spin_lock_irqsave(fence->lock, flags);
 	__dma_fence_enable_signaling(fence);
 	spin_unlock_irqrestore(fence->lock, flags);
 	unsigned long flags;
 	signed long ret = timeout ? timeout : 1;
-	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
-		return ret;
 	spin_lock_irqsave(fence->lock, flags);
+	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
+		goto out;
 	if (intr && signal_pending(current)) {
 		ret = -ERESTARTSYS;
 		goto out;
 	}
-	if (!__dma_fence_enable_signaling(fence))
-		goto out;
 	if (!timeout) {
 		ret = 0;
 		goto out;

drivers/dma-buf/st-dma-fence-chain.c+4−0

 	if (!chain)
 		err = -ENOMEM;
+	dma_fence_enable_sw_signaling(chain);
 	dma_fence_signal(f);
 	dma_fence_put(f);
 		}
 		fc->tail = fc->chains[i];
+		dma_fence_enable_sw_signaling(fc->chains[i]);
 	}
 	fc->chain_length = i;

drivers/dma-buf/st-dma-fence-unwrap.c+22−0

 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	array = mock_array(1, f);
 	if (!array)
 		return -ENOMEM;
 	if (!f1)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f1);
 	f2 = mock_fence();
 	if (!f2) {
 		dma_fence_put(f1);
 		return -ENOMEM;
 	}
+	dma_fence_enable_sw_signaling(f2);
 	array = mock_array(2, f1, f2);
 	if (!array)
 		return -ENOMEM;
 	if (!f1)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f1);
 	f2 = mock_fence();
 	if (!f2) {
 		dma_fence_put(f1);
 		return -ENOMEM;
 	}
+	dma_fence_enable_sw_signaling(f2);
 	chain = mock_chain(f1, f2);
 	if (!chain)
 		return -ENOMEM;
 	if (!f1)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f1);
 	f2 = mock_fence();
 	if (!f2) {
 		dma_fence_put(f1);
 		return -ENOMEM;
 	}
+	dma_fence_enable_sw_signaling(f2);
 	array = mock_array(2, f1, f2);
 	if (!array)
 		return -ENOMEM;
 	if (!f1)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f1);
 	f2 = mock_fence();
 	if (!f2) {
 		err = -ENOMEM;
 		goto error_put_f1;
 	}
+	dma_fence_enable_sw_signaling(f2);
 	f3 = dma_fence_unwrap_merge(f1, f2);
 	if (!f3) {
 		err = -ENOMEM;
 	if (!f1)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f1);
 	f2 = mock_fence();
 	if (!f2)
 		goto error_put_f1;
+	dma_fence_enable_sw_signaling(f2);
 	f3 = dma_fence_unwrap_merge(f1, f2);
 	if (!f3)
 		goto error_put_f2;

drivers/dma-buf/st-dma-fence.c+16−0

 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	dma_fence_signal(f);
 	dma_fence_put(f);
 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	if (dma_fence_is_signaled(f)) {
 		pr_err("Fence unexpectedly signaled on creation\n");
 		goto err_free;
 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	dma_fence_signal(f);
 	if (!dma_fence_add_callback(f, &cb.cb, simple_callback)) {
 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	if (dma_fence_get_status(f)) {
 		pr_err("Fence unexpectedly has signaled status on creation\n");
 		goto err_free;
 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	dma_fence_set_error(f, -EIO);
 	if (dma_fence_get_status(f)) {
 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	if (dma_fence_wait_timeout(f, false, 0) != -ETIME) {
 		pr_err("Wait reported complete before being signaled\n");
 		goto err_free;
 	if (!wt.f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(wt.f);
 	if (dma_fence_wait_timeout(wt.f, false, 1) != -ETIME) {
 		pr_err("Wait reported complete before being signaled\n");
 		goto err_free;
 			break;
 		}
+		dma_fence_enable_sw_signaling(f1);
 		rcu_assign_pointer(t->fences[t->id], f1);
 		smp_wmb();

drivers/dma-buf/st-dma-resv.c+10−0

 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	dma_fence_signal(f);
 	dma_fence_put(f);
 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	dma_resv_init(&resv);
 	r = dma_resv_lock(&resv, NULL);
 	if (r) {
 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	dma_resv_init(&resv);
 	r = dma_resv_lock(&resv, NULL);
 	if (r) {
 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	dma_resv_init(&resv);
 	r = dma_resv_lock(&resv, NULL);
 	if (r) {
 	if (!f)
 		return -ENOMEM;
+	dma_fence_enable_sw_signaling(f);
 	dma_resv_init(&resv);
 	r = dma_resv_lock(&resv, NULL);
 	if (r) {

drivers/dma-buf/sync_file.c+4−4

@@ -132,7 +132,7 @@ EXPORT_SYMBOL(sync_file_get_fence); · 131 unmodified lines
132	char sync_file_get_name(struct sync_file sync_file, char *buf, int len)	132	char sync_file_get_name(struct sync_file sync_file, char *buf, int len)
133	{	133	{
134	if (sync_file->user_name[0]) {	134	if (sync_file->user_name[0]) {
135	strlcpy(buf, sync_file->user_name, len);	135	strscpy(buf, sync_file->user_name, len);
136	} else {	136	} else {
137	struct dma_fence *fence = sync_file->fence;	137	struct dma_fence *fence = sync_file->fence;
138		138
@@ -172,7 +172,7 @@ static struct sync_file sync_file_merge(const char name, struct sync_file *a, · 33 unmodified lines
172	return NULL;	172	return NULL;
173	}	173	}
174	sync_file->fence = fence;	174	sync_file->fence = fence;
175	strlcpy(sync_file->user_name, name, sizeof(sync_file->user_name));	175	strscpy(sync_file->user_name, name, sizeof(sync_file->user_name));
176	return sync_file;	176	return sync_file;
177	}	177	}
178		178
@@ -262,9 +262,9 @@ err_put_fd: · 83 unmodified lines
262	static int sync_fill_fence_info(struct dma_fence *fence,	262	static int sync_fill_fence_info(struct dma_fence *fence,
263	struct sync_fence_info *info)	263	struct sync_fence_info *info)
264	{	264	{
265	strlcpy(info->obj_name, fence->ops->get_timeline_name(fence),	265	strscpy(info->obj_name, fence->ops->get_timeline_name(fence),
266	sizeof(info->obj_name));	266	sizeof(info->obj_name));
267	strlcpy(info->driver_name, fence->ops->get_driver_name(fence),	267	strscpy(info->driver_name, fence->ops->get_driver_name(fence),
268	sizeof(info->driver_name));	268	sizeof(info->driver_name));
269		269
270	info->status = dma_fence_get_status(fence);	270	info->status = dma_fence_get_status(fence);

drivers/dma-buf/udmabuf.c+6−3

 {
 	struct udmabuf *ubuf = buf->priv;
 	struct device *dev = ubuf->device->this_device;
+	int ret = 0;
 	if (!ubuf->sg) {
 		ubuf->sg = get_sg_table(dev, buf, direction);
-		if (IS_ERR(ubuf->sg))
+		if (IS_ERR(ubuf->sg)) {
-			return PTR_ERR(ubuf->sg);
+			ret = PTR_ERR(ubuf->sg);
+			ubuf->sg = NULL;
+		}
 	} else {
 		dma_sync_sg_for_cpu(dev, ubuf->sg->sgl, ubuf->sg->nents,
 				    direction);
 	}
-	return 0;
+	return ret;
 }
 static int end_cpu_udmabuf(struct dma_buf *buf,

drivers/firmware/sysfb.c+4−0

 		name = "efi-framebuffer";
 	else if (si->orig_video_isVGA == VIDEO_TYPE_VLFB)
 		name = "vesa-framebuffer";
+	else if (si->orig_video_isVGA == VIDEO_TYPE_VGAC)
+		name = "vga-framebuffer";
+	else if (si->orig_video_isVGA == VIDEO_TYPE_EGAC)
+		name = "ega-framebuffer";
 	else
 		name = "platform-framebuffer";

drivers/gpu/drm/Kconfig+6−19

 config DRM_MIPI_DBI
 	tristate
 	depends on DRM
+	select DRM_KMS_HELPER
 config DRM_MIPI_DSI
 	bool
 	  If in doubt, say "N".
-config DRM_DEBUG_SELFTEST
+config DRM_KUNIT_TEST
-	tristate "kselftests for DRM"
+	tristate "KUnit tests for DRM" if !KUNIT_ALL_TESTS
-	depends on DRM
+	depends on DRM && KUNIT
-	depends on DEBUG_KERNEL
 	select PRIME_NUMBERS
 	select DRM_DISPLAY_DP_HELPER
 	select DRM_DISPLAY_HELPER
 	select DRM_KMS_HELPER
 	select DRM_BUDDY
 	select DRM_EXPORT_FOR_TESTS if m
-	default n
-	help
-	  This option provides kernel modules that can be used to run
-	  various selftests on parts of the DRM api. This option is not
-	  useful for distributions or general kernels, but only for kernel
-	  developers working on DRM and associated drivers.
-	  If in doubt, say "N".
-config DRM_KUNIT_TEST
-	tristate "KUnit tests for DRM" if !KUNIT_ALL_TESTS
-	depends on DRM && KUNIT=y
-	select DRM_KMS_HELPER
 	default KUNIT_ALL_TESTS
 	help
 	  This builds unit tests for DRM. This option is not useful for
 	help
 	  Helpers for ttm-based gem objects
-config DRM_GEM_CMA_HELPER
+config DRM_GEM_DMA_HELPER
 	tristate
 	depends on DRM
 	help
-	  Choose this if you need the GEM CMA helper functions
+	  Choose this if you need the GEM DMA helper functions
 config DRM_GEM_SHMEM_HELPER
 	tristate

drivers/gpu/drm/Makefile+3−4

 obj-$(CONFIG_DRM_BUDDY) += drm_buddy.o
-drm_cma_helper-y := drm_gem_cma_helper.o
+drm_dma_helper-y := drm_gem_dma_helper.o
-drm_cma_helper-$(CONFIG_DRM_KMS_HELPER) += drm_fb_cma_helper.o
+drm_dma_helper-$(CONFIG_DRM_KMS_HELPER) += drm_fb_dma_helper.o
-obj-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_cma_helper.o
+obj-$(CONFIG_DRM_GEM_DMA_HELPER) += drm_dma_helper.o
 drm_shmem_helper-y := drm_gem_shmem_helper.o
 obj-$(CONFIG_DRM_GEM_SHMEM_HELPER) += drm_shmem_helper.o
 # Drivers and the rest
 #
-obj-$(CONFIG_DRM_DEBUG_SELFTEST) += selftests/
 obj-$(CONFIG_DRM_KUNIT_TEST) += tests/
 obj-$(CONFIG_DRM_MIPI_DBI) += drm_mipi_dbi.o

drivers/gpu/drm/amd/amdgpu/Makefile+4−3

 	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
 	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \
 	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o \
-	nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o
+	sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o
 # add DF block
 amdgpu-y += \
 	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
 	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \
 	mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o \
-	mmhub_v3_0_1.o
+	mmhub_v3_0_1.o gfxhub_v3_0_3.o
 # add UMC block
 amdgpu-y += \
 	gfx_v9_4_2.o \
 	gfx_v10_0.o \
 	imu_v11_0.o \
-	gfx_v11_0.o
+	gfx_v11_0.o \
+	imu_v11_0_3.o
 # add async DMA block
 amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu.h+9−0

 #define AMDGPU_RESET_VCE			(1 << 13)
 #define AMDGPU_RESET_VCE1			(1 << 14)
+#define AMDGPU_RESET_LEVEL_SOFT_RECOVERY (1 << 0)
+#define AMDGPU_RESET_LEVEL_MODE2 (1 << 1)
 /* max cursor sizes (in pixels) */
 #define CIK_CURSOR_WIDTH 128
 #define CIK_CURSOR_HEIGHT 128
 	u64				fence_context;
 	unsigned			num_rings;
 	struct amdgpu_ring		*rings[AMDGPU_MAX_RINGS];
+	struct dma_fence __rcu		*gang_submit;
 	bool				ib_pool_ready;
 	struct amdgpu_sa_manager	ib_pools[AMDGPU_IB_POOL_MAX];
 	struct amdgpu_sched		gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
 	uint32_t                        scpm_status;
 	struct work_struct		reset_work;
+	uint32_t						amdgpu_reset_level_mask;
+	bool                            job_hang;
 };
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
 				u32 reg);
 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
 				u32 reg, u32 v);
+struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
+					    struct dma_fence *gang);
 /* atpx handler */
 #if defined(CONFIG_VGA_SWITCHEROO)

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c+13−4

@@ -1,3 +1,4 @@
		1	// SPDX-License-Identifier: MIT
1	/*	2	/*
2	* Copyright 2012 Advanced Micro Devices, Inc.	3	* Copyright 2012 Advanced Micro Devices, Inc.
3	*	4	*
@@ -849,6 +850,7 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) · 845 unmodified lines
849	if (amdgpu_device_has_dc_support(adev)) {	850	if (amdgpu_device_has_dc_support(adev)) {
850	#if defined(CONFIG_DRM_AMD_DC)	851	#if defined(CONFIG_DRM_AMD_DC)
851	struct amdgpu_display_manager *dm = &adev->dm;	852	struct amdgpu_display_manager *dm = &adev->dm;
		853
852	if (dm->backlight_dev[0])	854	if (dm->backlight_dev[0])
853	atif->bd = dm->backlight_dev[0];	855	atif->bd = dm->backlight_dev[0];
854	#endif	856	#endif
@@ -863,6 +865,7 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) · 8 unmodified lines
863	if ((enc->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&	865	if ((enc->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
864	enc->enc_priv) {	866	enc->enc_priv) {
865	struct amdgpu_encoder_atom_dig *dig = enc->enc_priv;	867	struct amdgpu_encoder_atom_dig *dig = enc->enc_priv;
		868
866	if (dig->bl_dev) {	869	if (dig->bl_dev) {
867	atif->bd = dig->bl_dev;	870	atif->bd = dig->bl_dev;
868	break;	871	break;
@@ -919,9 +922,9 @@ static bool amdgpu_atif_pci_probe_handle(struct pci_dev *pdev) · 50 unmodified lines
919	return false;	922	return false;
920		923
921	status = acpi_get_handle(dhandle, "ATIF", &atif_handle);	924	status = acpi_get_handle(dhandle, "ATIF", &atif_handle);
922	if (ACPI_FAILURE(status)) {	925	if (ACPI_FAILURE(status))
923	return false;	926	return false;
924	}	927
925	amdgpu_acpi_priv.atif.handle = atif_handle;	928	amdgpu_acpi_priv.atif.handle = atif_handle;
926	acpi_get_name(amdgpu_acpi_priv.atif.handle, ACPI_FULL_PATHNAME, &buffer);	929	acpi_get_name(amdgpu_acpi_priv.atif.handle, ACPI_FULL_PATHNAME, &buffer);
927	DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name);	930	DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name);
@@ -954,9 +957,9 @@ static bool amdgpu_atcs_pci_probe_handle(struct pci_dev *pdev) · 26 unmodified lines
954	return false;	957	return false;
955		958
956	status = acpi_get_handle(dhandle, "ATCS", &atcs_handle);	959	status = acpi_get_handle(dhandle, "ATCS", &atcs_handle);
957	if (ACPI_FAILURE(status)) {	960	if (ACPI_FAILURE(status))
958	return false;	961	return false;
959	}	962
960	amdgpu_acpi_priv.atcs.handle = atcs_handle;	963	amdgpu_acpi_priv.atcs.handle = atcs_handle;
961	acpi_get_name(amdgpu_acpi_priv.atcs.handle, ACPI_FULL_PATHNAME, &buffer);	964	acpi_get_name(amdgpu_acpi_priv.atcs.handle, ACPI_FULL_PATHNAME, &buffer);
962	DRM_DEBUG_DRIVER("Found ATCS handle %s\n", acpi_method_name);	965	DRM_DEBUG_DRIVER("Found ATCS handle %s\n", acpi_method_name);
@@ -1070,6 +1073,12 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) · 107 unmodified lines
1070	(pm_suspend_target_state != PM_SUSPEND_TO_IDLE))	1073	(pm_suspend_target_state != PM_SUSPEND_TO_IDLE))
1071	return false;	1074	return false;
1072		1075
		1076	/*
		1077	* If ACPI_FADT_LOW_POWER_S0 is not set in the FADT, it is generally
		1078	* risky to do any special firmware-related preparations for entering
		1079	* S0ix even though the system is suspending to idle, so return false
		1080	* in that case.
		1081	*/
1073	if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {	1082	if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1074	dev_warn_once(adev->dev,	1083	dev_warn_once(adev->dev,
1075	"Power consumption will be higher as BIOS has not been configured for suspend-to-idle.\n"	1084	"Power consumption will be higher as BIOS has not been configured for suspend-to-idle.\n"

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c+5−5

+// SPDX-License-Identifier: MIT
 /*
  * Copyright 2014 Advanced Micro Devices, Inc.
  *
 						  kfd.reset_work);
 	struct amdgpu_reset_context reset_context;
 	memset(&reset_context, 0, sizeof(reset_context));
 	reset_context.method = AMD_RESET_METHOD_NONE;
 	reset_context.reset_req_dev = adev;
 	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
+	clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
 	amdgpu_device_gpu_recover(adev, NULL, &reset_context);
 }
 	ib->length_dw = ib_len;
 	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
 	job->vmid = vmid;
+	job->num_ibs = 1;
 	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
 {
 	struct ras_err_data err_data = {0, 0, 0, NULL};
-	/* CPU MCA will handle page retirement if connected_to_cpu is 1 */
+	amdgpu_umc_poison_handler(adev, &err_data, reset);
-	if (!adev->gmc.xgmi.connected_to_cpu)
-		amdgpu_umc_poison_handler(adev, &err_data, reset);
-	else if (reset)
-		amdgpu_amdkfd_gpu_reset(adev);
 }
 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c+19−11

+// SPDX-License-Identifier: MIT
 /*
  * Copyright 2014-2018 Advanced Micro Devices, Inc.
  *
 	 */
 	replacement = dma_fence_get_stub();
 	dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
-				replacement, DMA_RESV_USAGE_READ);
+				replacement, DMA_RESV_USAGE_BOOKKEEP);
 	dma_fence_put(replacement);
 	return 0;
 }
 	ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
 	if (ret)
 		goto reserve_shared_fail;
-	amdgpu_bo_fence(vm->root.bo,
+	dma_resv_add_fence(vm->root.bo->tbo.base.resv,
-			&vm->process_info->eviction_fence->base, true);
+			   &vm->process_info->eviction_fence->base,
+			   DMA_RESV_USAGE_BOOKKEEP);
 	amdgpu_bo_unreserve(vm->root.bo);
 	/* Update process info */
 	uint64_t reserved_for_pt =
 		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
 	size_t available;
 	spin_lock(&kfd_mem_limit.mem_limit_lock);
 	available = adev->gmc.real_vram_size
 		- adev->kfd.vram_used_aligned
 	}
 	if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
-		amdgpu_bo_fence(bo,
+		dma_resv_add_fence(bo->tbo.base.resv,
-				&avm->process_info->eviction_fence->base,
+				   &avm->process_info->eviction_fence->base,
-				true);
+				   DMA_RESV_USAGE_BOOKKEEP);
 	ret = unreserve_bo_and_vms(&ctx, false, false);
 	goto out;
 {
 	if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
 		*mem = *adev->gmc.vm_fault_info;
-		mb();
+		mb(); /* make sure read happened */
 		atomic_set(&adev->gmc.vm_fault_info_updated, 0);
 	}
 	return 0;
 		if (mem->bo->tbo.pin_count)
 			continue;
-		amdgpu_bo_fence(mem->bo,
+		dma_resv_add_fence(mem->bo->tbo.base.resv,
-			&process_info->eviction_fence->base, true);
+				   &process_info->eviction_fence->base,
+				   DMA_RESV_USAGE_BOOKKEEP);
 	}
 	/* Attach eviction fence to PD / PT BOs */
 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
 			    vm_list_node) {
 		struct amdgpu_bo *bo = peer_vm->root.bo;
-		amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true);
+		dma_resv_add_fence(bo->tbo.base.resv,
+				   &process_info->eviction_fence->base,
+				   DMA_RESV_USAGE_BOOKKEEP);
 	}
 validate_map_fail:
 	ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
 	if (ret)
 		goto reserve_shared_fail;
-	amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true);
+	dma_resv_add_fence(gws_bo->tbo.base.resv,
+			   &process_info->eviction_fence->base,
+			   DMA_RESV_USAGE_BOOKKEEP);
 	amdgpu_bo_unreserve(gws_bo);
 	mutex_unlock(&(*mem)->process_info->lock);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c+6−1

 						   adev->mode_info.dither_property,
 						   AMDGPU_FMT_DITHER_DISABLE);
-			if (amdgpu_audio != 0)
+			if (amdgpu_audio != 0) {
 				drm_object_attach_property(&amdgpu_connector->base.base,
 							   adev->mode_info.audio_property,
 							   AMDGPU_AUDIO_AUTO);
+				amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
+			}
 			subpixel_order = SubPixelHorizontalRGB;
 			connector->interlace_allowed = true;
 				drm_object_attach_property(&amdgpu_connector->base.base,
 							   adev->mode_info.audio_property,
 							   AMDGPU_AUDIO_AUTO);
+				amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
 			}
 			drm_object_attach_property(&amdgpu_connector->base.base,
 						   adev->mode_info.dither_property,
 				drm_object_attach_property(&amdgpu_connector->base.base,
 							   adev->mode_info.audio_property,
 							   AMDGPU_AUDIO_AUTO);
+				amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
 			}
 			drm_object_attach_property(&amdgpu_connector->base.base,
 						   adev->mode_info.dither_property,
 				drm_object_attach_property(&amdgpu_connector->base.base,
 							   adev->mode_info.audio_property,
 							   AMDGPU_AUDIO_AUTO);
+				amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
 			}
 			drm_object_attach_property(&amdgpu_connector->base.base,
 						   adev->mode_info.dither_property,

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+898−844

@@ -39,9 +39,82 @@ · 38 unmodified lines
39	#include "amdgpu_gem.h"	39	#include "amdgpu_gem.h"
40	#include "amdgpu_ras.h"	40	#include "amdgpu_ras.h"
41		41
42	static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,	42	static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
43	struct drm_amdgpu_cs_chunk_fence *data,	43	struct amdgpu_device *adev,
44	uint32_t *offset)	44	struct drm_file *filp,
		45	union drm_amdgpu_cs *cs)
		46	{
		47	struct amdgpu_fpriv *fpriv = filp->driver_priv;
		48
		49	if (cs->in.num_chunks == 0)
		50	return -EINVAL;
		51
		52	memset(p, 0, sizeof(*p));
		53	p->adev = adev;
		54	p->filp = filp;
		55
		56	p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
		57	if (!p->ctx)
		58	return -EINVAL;
		59
		60	if (atomic_read(&p->ctx->guilty)) {
		61	amdgpu_ctx_put(p->ctx);
		62	return -ECANCELED;
		63	}
		64	return 0;
		65	}
		66
		67	static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p,
		68	struct drm_amdgpu_cs_chunk_ib *chunk_ib)
		69	{
		70	struct drm_sched_entity *entity;
		71	unsigned int i;
		72	int r;
		73
		74	r = amdgpu_ctx_get_entity(p->ctx, chunk_ib->ip_type,
		75	chunk_ib->ip_instance,
		76	chunk_ib->ring, &entity);
		77	if (r)
		78	return r;
		79
		80	/*
		81	* Abort if there is no run queue associated with this entity.
		82	* Possibly because of disabled HW IP.
		83	*/
		84	if (entity->rq == NULL)
		85	return -EINVAL;
		86
		87	/* Check if we can add this IB to some existing job */
		88	for (i = 0; i < p->gang_size; ++i)
		89	if (p->entities[i] == entity)
		90	return i;
		91
		92	/* If not increase the gang size if possible */
		93	if (i == AMDGPU_CS_GANG_SIZE)
		94	return -EINVAL;
		95
		96	p->entities[i] = entity;
		97	p->gang_size = i + 1;
		98	return i;
		99	}
		100
		101	static int amdgpu_cs_p1_ib(struct amdgpu_cs_parser *p,
		102	struct drm_amdgpu_cs_chunk_ib *chunk_ib,
		103	unsigned int *num_ibs)
		104	{
		105	int r;
		106
		107	r = amdgpu_cs_job_idx(p, chunk_ib);
		108	if (r < 0)
		109	return r;
		110
		111	++(num_ibs[r]);
		112	return 0;
		113	}
		114
		115	static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
		116	struct drm_amdgpu_cs_chunk_fence *data,
		117	uint32_t *offset)
45	{	118	{
46	struct drm_gem_object *gobj;	119	struct drm_gem_object *gobj;
47	struct amdgpu_bo *bo;	120	struct amdgpu_bo *bo;
@@ -80,11 +153,11 @@ error_unref: · 32 unmodified lines
80	return r;	153	return r;
81	}	154	}
82		155
83	static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,	156	static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p,
84	struct drm_amdgpu_bo_list_in *data)	157	struct drm_amdgpu_bo_list_in *data)
85	{	158	{
		159	struct drm_amdgpu_bo_list_entry *info;
86	int r;	160	int r;
87	struct drm_amdgpu_bo_list_entry *info = NULL;
88		161
89	r = amdgpu_bo_create_list_entry_array(data, &info);	162	r = amdgpu_bo_create_list_entry_array(data, &info);
90	if (r)	163	if (r)
@@ -104,38 +177,25 @@ error_free: · 13 unmodified lines
104	return r;	177	return r;
105	}	178	}
106		179
107	static int amdgpu_cs_parser_init(struct amdgpu_cs_parser p, union drm_amdgpu_cs cs)	180	/* Copy the data from userspace and go over it the first time */
		181	static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
		182	union drm_amdgpu_cs *cs)
108	{	183	{
109	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;	184	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
		185	unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { };
110	struct amdgpu_vm *vm = &fpriv->vm;	186	struct amdgpu_vm *vm = &fpriv->vm;
111	uint64_t *chunk_array_user;	187	uint64_t *chunk_array_user;
112	uint64_t *chunk_array;	188	uint64_t *chunk_array;
113	unsigned size, num_ibs = 0;
114	uint32_t uf_offset = 0;	189	uint32_t uf_offset = 0;
115	int i;	190	unsigned int size;
116	int ret;	191	int ret;
		192	int i;
117		193
118	if (cs->in.num_chunks == 0)	194	chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t),
119	return -EINVAL;	195	GFP_KERNEL);
120
121	chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
122	if (!chunk_array)	196	if (!chunk_array)
123	return -ENOMEM;	197	return -ENOMEM;
124		198
125	p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
126	if (!p->ctx) {
127	ret = -EINVAL;
128	goto free_chunk;
129	}
130
131	mutex_lock(&p->ctx->lock);
132
133	/* skip guilty context job */
134	if (atomic_read(&p->ctx->guilty) == 1) {
135	ret = -ECANCELED;
136	goto free_chunk;
137	}
138
139	/* get chunks */	199	/* get chunks */
140	chunk_array_user = u64_to_user_ptr(cs->in.chunks);	200	chunk_array_user = u64_to_user_ptr(cs->in.chunks);
141	if (copy_from_user(chunk_array, chunk_array_user,	201	if (copy_from_user(chunk_array, chunk_array_user,
@@ -170,7 +230,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs · 28 unmodified lines
170	size = p->chunks[i].length_dw;	230	size = p->chunks[i].length_dw;
171	cdata = u64_to_user_ptr(user_chunk.chunk_data);	231	cdata = u64_to_user_ptr(user_chunk.chunk_data);
172		232
173	p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);	233	p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t),
		234	GFP_KERNEL);
174	if (p->chunks[i].kdata == NULL) {	235	if (p->chunks[i].kdata == NULL) {
175	ret = -ENOMEM;	236	ret = -ENOMEM;
176	i--;	237	i--;
@@ -182,36 +243,35 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs · 5 unmodified lines
182	goto free_partial_kdata;	243	goto free_partial_kdata;
183	}	244	}
184		245
		246	/* Assume the worst on the following checks */
		247	ret = -EINVAL;
185	switch (p->chunks[i].chunk_id) {	248	switch (p->chunks[i].chunk_id) {
186	case AMDGPU_CHUNK_ID_IB:	249	case AMDGPU_CHUNK_ID_IB:
187	++num_ibs;	250	if (size < sizeof(struct drm_amdgpu_cs_chunk_ib))
		251	goto free_partial_kdata;
		252
		253	ret = amdgpu_cs_p1_ib(p, p->chunks[i].kdata, num_ibs);
		254	if (ret)
		255	goto free_partial_kdata;
188	break;	256	break;
189		257
190	case AMDGPU_CHUNK_ID_FENCE:	258	case AMDGPU_CHUNK_ID_FENCE:
191	size = sizeof(struct drm_amdgpu_cs_chunk_fence);	259	if (size < sizeof(struct drm_amdgpu_cs_chunk_fence))
192	if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
193	ret = -EINVAL;
194	goto free_partial_kdata;	260	goto free_partial_kdata;
195	}
196		261
197	ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,	262	ret = amdgpu_cs_p1_user_fence(p, p->chunks[i].kdata,
198	&uf_offset);	263	&uf_offset);
199	if (ret)	264	if (ret)
200	goto free_partial_kdata;	265	goto free_partial_kdata;
201
202	break;	266	break;
203		267
204	case AMDGPU_CHUNK_ID_BO_HANDLES:	268	case AMDGPU_CHUNK_ID_BO_HANDLES:
205	size = sizeof(struct drm_amdgpu_bo_list_in);	269	if (size < sizeof(struct drm_amdgpu_bo_list_in))
206	if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
207	ret = -EINVAL;
208	goto free_partial_kdata;	270	goto free_partial_kdata;
209	}
210		271
211	ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);	272	ret = amdgpu_cs_p1_bo_handles(p, p->chunks[i].kdata);
212	if (ret)	273	if (ret)
213	goto free_partial_kdata;	274	goto free_partial_kdata;
214
215	break;	275	break;
216		276
217	case AMDGPU_CHUNK_ID_DEPENDENCIES:	277	case AMDGPU_CHUNK_ID_DEPENDENCIES:
@@ -223,22 +283,32 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs · 5 unmodified lines
223	break;	283	break;
224		284
225	default:	285	default:
226	ret = -EINVAL;
227	goto free_partial_kdata;	286	goto free_partial_kdata;
228	}	287	}
229	}	288	}
230		289
231	ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);	290	if (!p->gang_size)
232	if (ret)	291	return -EINVAL;
233	goto free_all_kdata;	292
		293	for (i = 0; i < p->gang_size; ++i) {
		294	ret = amdgpu_job_alloc(p->adev, num_ibs[i], &p->jobs[i], vm);
		295	if (ret)
		296	goto free_all_kdata;
		297
		298	ret = drm_sched_job_init(&p->jobs[i]->base, p->entities[i],
		299	&fpriv->vm);
		300	if (ret)
		301	goto free_all_kdata;
		302	}
		303	p->gang_leader = p->jobs[p->gang_size - 1];
234		304
235	if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {	305	if (p->ctx->vram_lost_counter != p->gang_leader->vram_lost_counter) {
236	ret = -ECANCELED;	306	ret = -ECANCELED;
237	goto free_all_kdata;	307	goto free_all_kdata;
238	}	308	}
239		309
240	if (p->uf_entry.tv.bo)	310	if (p->uf_entry.tv.bo)
241	p->job->uf_addr = uf_offset;	311	p->gang_leader->uf_addr = uf_offset;
242	kvfree(chunk_array);	312	kvfree(chunk_array);
243		313
244	/* Use this opportunity to fill in task info for the vm */	314	/* Use this opportunity to fill in task info for the vm */
@@ -260,943 +330,880 @@ free_chunk: · 15 unmodified lines
260	return ret;	330	return ret;
261	}	331	}
262		332
263	/* Convert microseconds to bytes. */	333	static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p,
264	static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)	334	struct amdgpu_cs_chunk *chunk,
		335	unsigned int *ce_preempt,
		336	unsigned int *de_preempt)
265	{	337	{
266	if (us <= 0 \|\| !adev->mm_stats.log2_max_MBps)	338	struct drm_amdgpu_cs_chunk_ib *chunk_ib = chunk->kdata;
267	return 0;	339	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
		340	struct amdgpu_vm *vm = &fpriv->vm;
		341	struct amdgpu_ring *ring;
		342	struct amdgpu_job *job;
		343	struct amdgpu_ib *ib;
		344	int r;
268		345
269	/* Since accum_us is incremented by a million per second, just	346	r = amdgpu_cs_job_idx(p, chunk_ib);
270	* multiply it by the number of MB/s to get the number of bytes.	347	if (r < 0)
271	*/	348	return r;
272	return us << adev->mm_stats.log2_max_MBps;
273	}
274		349
275	static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)	350	job = p->jobs[r];
276	{	351	ring = amdgpu_job_ring(job);
277	if (!adev->mm_stats.log2_max_MBps)	352	ib = &job->ibs[job->num_ibs++];
278	return 0;
279		353
280	return bytes >> adev->mm_stats.log2_max_MBps;	354	/* MM engine doesn't support user fences */
281	}	355	if (p->uf_entry.tv.bo && ring->funcs->no_user_fence)
		356	return -EINVAL;
282		357
283	/* Returns how many bytes TTM can move right now. If no bytes can be moved,	358	if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
284	* it returns 0. If it returns non-zero, it's OK to move at least one buffer,	359	chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
285	* which means it can go over the threshold once. If that happens, the driver	360	if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
286	* will be in debt and no other buffer migrations can be done until that debt	361	(*ce_preempt)++;
287	* is repaid.	362	else
288	*	363	(*de_preempt)++;
289	* This approach allows moving a buffer of any size (it's important to allow
290	* that).
291	*
292	* The currency is simply time in microseconds and it increases as the clock
293	* ticks. The accumulated microseconds (us) are converted to bytes and
294	* returned.
295	*/
296	static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
297	u64 *max_bytes,
298	u64 *max_vis_bytes)
299	{
300	s64 time_us, increment_us;
301	u64 free_vram, total_vram, used_vram;
302	/* Allow a maximum of 200 accumulated ms. This is basically per-IB
303	* throttling.
304	*
305	* It means that in order to get full max MBps, at least 5 IBs per
306	* second must be submitted and not more than 200ms apart from each
307	* other.
308	*/
309	const s64 us_upper_bound = 200000;
310		364
311	if (!adev->mm_stats.log2_max_MBps) {	365	/* Each GFX command submit allows only 1 IB max
312	*max_bytes = 0;	366	* preemptible for CE & DE */
313	*max_vis_bytes = 0;	367	if (ce_preempt > 1 \|\| de_preempt > 1)
314	return;	368	return -EINVAL;
315	}	369	}
316		370
317	total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);	371	if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
318	used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);	372	job->preamble_status \|= AMDGPU_PREAMBLE_IB_PRESENT;
319	free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
320		373
321	spin_lock(&adev->mm_stats.lock);	374	r = amdgpu_ib_get(p->adev, vm, ring->funcs->parse_cs ?
		375	chunk_ib->ib_bytes : 0,
		376	AMDGPU_IB_POOL_DELAYED, ib);
		377	if (r) {
		378	DRM_ERROR("Failed to get ib !\n");
		379	return r;
		380	}
322		381
323	/* Increase the amount of accumulated us. */	382	ib->gpu_addr = chunk_ib->va_start;
324	time_us = ktime_to_us(ktime_get());	383	ib->length_dw = chunk_ib->ib_bytes / 4;
325	increment_us = time_us - adev->mm_stats.last_update_us;	384	ib->flags = chunk_ib->flags;
326	adev->mm_stats.last_update_us = time_us;	385	return 0;
327	adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,	386	}
328	us_upper_bound);
329		387
330	/* This prevents the short period of low performance when the VRAM	388	static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p,
331	* usage is low and the driver is in debt or doesn't have enough	389	struct amdgpu_cs_chunk *chunk)
332	* accumulated us to fill VRAM quickly.	390	{
333	*	391	struct drm_amdgpu_cs_chunk_dep *deps = chunk->kdata;
334	* The situation can occur in these cases:	392	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
335	* - a lot of VRAM is freed by userspace	393	unsigned num_deps;
336	* - the presence of a big buffer causes a lot of evictions	394	int i, r;
337	* (solution: split buffers into smaller ones)
338	*
339	* If 128 MB or 1/8th of VRAM is free, start filling it now by setting
340	* accum_us to a positive number.
341	*/
342	if (free_vram >= 128 * 1024 * 1024 \|\| free_vram >= total_vram / 8) {
343	s64 min_us;
344		395
345	/* Be more aggressive on dGPUs. Try to fill a portion of free	396	num_deps = chunk->length_dw * 4 /
346	* VRAM now.	397	sizeof(struct drm_amdgpu_cs_chunk_dep);
347	*/
348	if (!(adev->flags & AMD_IS_APU))
349	min_us = bytes_to_us(adev, free_vram / 4);
350	else
351	min_us = 0; /* Reset accum_us on APUs. */
352		398
353	adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);	399	for (i = 0; i < num_deps; ++i) {
354	}	400	struct amdgpu_ctx *ctx;
		401	struct drm_sched_entity *entity;
		402	struct dma_fence *fence;
355		403
356	/* This is set to 0 if the driver is in debt to disallow (optional)	404	ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
357	* buffer moves.	405	if (ctx == NULL)
358	*/	406	return -EINVAL;
359	*max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
360		407
361	/* Do the same for visible VRAM if half of it is free */	408	r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
362	if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {	409	deps[i].ip_instance,
363	u64 total_vis_vram = adev->gmc.visible_vram_size;	410	deps[i].ring, &entity);
364	u64 used_vis_vram =	411	if (r) {
365	amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);	412	amdgpu_ctx_put(ctx);
		413	return r;
		414	}
366		415
367	if (used_vis_vram < total_vis_vram) {	416	fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
368	u64 free_vis_vram = total_vis_vram - used_vis_vram;	417	amdgpu_ctx_put(ctx);
369	adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
370	increment_us, us_upper_bound);
371		418
372	if (free_vis_vram >= total_vis_vram / 2)	419	if (IS_ERR(fence))
373	adev->mm_stats.accum_us_vis =	420	return PTR_ERR(fence);
374	max(bytes_to_us(adev, free_vis_vram / 2),	421	else if (!fence)
375	adev->mm_stats.accum_us_vis);	422	continue;
376	}
377		423
378	*max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);	424	if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
379	} else {	425	struct drm_sched_fence *s_fence;
380	*max_vis_bytes = 0;	426	struct dma_fence *old = fence;
381	}
382		427
383	spin_unlock(&adev->mm_stats.lock);	428	s_fence = to_drm_sched_fence(fence);
384	}	429	fence = dma_fence_get(&s_fence->scheduled);
		430	dma_fence_put(old);
		431	}
385		432
386	/* Report how many bytes have really been moved for the last command	433	r = amdgpu_sync_fence(&p->gang_leader->sync, fence);
387	* submission. This can result in a debt that can stop buffer migrations	434	dma_fence_put(fence);
388	* temporarily.	435	if (r)
389	*/	436	return r;
390	void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,	437	}
391	u64 num_vis_bytes)	438	return 0;
392	{
393	spin_lock(&adev->mm_stats.lock);
394	adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
395	adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
396	spin_unlock(&adev->mm_stats.lock);
397	}	439	}
398		440
399	static int amdgpu_cs_bo_validate(void param, struct amdgpu_bo bo)	441	static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p,
		442	uint32_t handle, u64 point,
		443	u64 flags)
400	{	444	{
401	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);	445	struct dma_fence *fence;
402	struct amdgpu_cs_parser *p = param;
403	struct ttm_operation_ctx ctx = {
404	.interruptible = true,
405	.no_wait_gpu = false,
406	.resv = bo->tbo.base.resv
407	};
408	uint32_t domain;
409	int r;	446	int r;
410		447
411	if (bo->tbo.pin_count)	448	r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
412	return 0;	449	if (r) {
		450	DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
		451	handle, point, r);
		452	return r;
		453	}
413		454
414	/* Don't move this buffer if we have depleted our allowance	455	r = amdgpu_sync_fence(&p->gang_leader->sync, fence);
415	* to move it. Don't move anything if the threshold is zero.	456	dma_fence_put(fence);
416	*/
417	if (p->bytes_moved < p->bytes_moved_threshold &&
418	(!bo->tbo.base.dma_buf \|\|
419	list_empty(&bo->tbo.base.dma_buf->attachments))) {
420	if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
421	(bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
422	/* And don't move a CPU_ACCESS_REQUIRED BO to limited
423	* visible VRAM if we've depleted our allowance to do
424	* that.
425	*/
426	if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
427	domain = bo->preferred_domains;
428	else
429	domain = bo->allowed_domains;
430	} else {
431	domain = bo->preferred_domains;
432	}
433	} else {
434	domain = bo->allowed_domains;
435	}
436
437	retry:
438	amdgpu_bo_placement_from_domain(bo, domain);
439	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
440
441	p->bytes_moved += ctx.bytes_moved;
442	if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
443	amdgpu_bo_in_cpu_visible_vram(bo))
444	p->bytes_moved_vis += ctx.bytes_moved;
445
446	if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
447	domain = bo->allowed_domains;
448	goto retry;
449	}
450		457
451	return r;	458	return r;
452	}	459	}
453		460
454	static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,	461	static int amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser *p,
455	struct list_head *validated)	462	struct amdgpu_cs_chunk *chunk)
456	{	463	{
457	struct ttm_operation_ctx ctx = { true, false };	464	struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
458	struct amdgpu_bo_list_entry *lobj;	465	unsigned num_deps;
459	int r;	466	int i, r;
460
461	list_for_each_entry(lobj, validated, tv.head) {
462	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
463	struct mm_struct *usermm;
464
465	usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
466	if (usermm && usermm != current->mm)
467	return -EPERM;
468
469	if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
470	lobj->user_invalidated && lobj->user_pages) {
471	amdgpu_bo_placement_from_domain(bo,
472	AMDGPU_GEM_DOMAIN_CPU);
473	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
474	if (r)
475	return r;
476
477	amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
478	lobj->user_pages);
479	}
480		467
481	r = amdgpu_cs_bo_validate(p, bo);	468	num_deps = chunk->length_dw * 4 /
		469	sizeof(struct drm_amdgpu_cs_chunk_sem);
		470	for (i = 0; i < num_deps; ++i) {
		471	r = amdgpu_syncobj_lookup_and_add(p, deps[i].handle, 0, 0);
482	if (r)	472	if (r)
483	return r;	473	return r;
484
485	kvfree(lobj->user_pages);
486	lobj->user_pages = NULL;
487	}	474	}
		475
488	return 0;	476	return 0;
489	}	477	}
490		478
491	static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,	479	static int amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser *p,
492	union drm_amdgpu_cs *cs)	480	struct amdgpu_cs_chunk *chunk)
493	{	481	{
494	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;	482	struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
495	struct amdgpu_vm *vm = &fpriv->vm;	483	unsigned num_deps;
496	struct amdgpu_bo_list_entry *e;	484	int i, r;
497	struct list_head duplicates;
498	struct amdgpu_bo *gds;
499	struct amdgpu_bo *gws;
500	struct amdgpu_bo *oa;
501	int r;
502
503	INIT_LIST_HEAD(&p->validated);
504
505	/* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
506	if (cs->in.bo_list_handle) {
507	if (p->bo_list)
508	return -EINVAL;
509		485
510	r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,	486	num_deps = chunk->length_dw * 4 /
511	&p->bo_list);	487	sizeof(struct drm_amdgpu_cs_chunk_syncobj);
512	if (r)	488	for (i = 0; i < num_deps; ++i) {
513	return r;	489	r = amdgpu_syncobj_lookup_and_add(p, syncobj_deps[i].handle,
514	} else if (!p->bo_list) {	490	syncobj_deps[i].point,
515	/* Create a empty bo_list when no handle is provided */	491	syncobj_deps[i].flags);
516	r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
517	&p->bo_list);
518	if (r)	492	if (r)
519	return r;	493	return r;
520	}	494	}
521		495
522	mutex_lock(&p->bo_list->bo_list_mutex);	496	return 0;
523		497	}
524	/* One for TTM and one for the CS job */
525	amdgpu_bo_list_for_each_entry(e, p->bo_list)
526	e->tv.num_shared = 2;
527
528	amdgpu_bo_list_get_list(p->bo_list, &p->validated);
529		498
530	INIT_LIST_HEAD(&duplicates);	499	static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p,
531	amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);	500	struct amdgpu_cs_chunk *chunk)
		501	{
		502	struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
		503	unsigned num_deps;
		504	int i;
532		505
533	if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)	506	num_deps = chunk->length_dw * 4 /
534	list_add(&p->uf_entry.tv.head, &p->validated);	507	sizeof(struct drm_amdgpu_cs_chunk_sem);
535		508
536	/* Get userptr backing pages. If pages are updated after registered	509	if (p->post_deps)
537	* in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do	510	return -EINVAL;
538	* amdgpu_ttm_backend_bind() to flush and invalidate new pages
539	*/
540	amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
541	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
542	bool userpage_invalidated = false;
543	int i;
544		511
545	e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,	512	p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
546	sizeof(struct page *),	513	GFP_KERNEL);
547	GFP_KERNEL \| __GFP_ZERO);	514	p->num_post_deps = 0;
548	if (!e->user_pages) {
549	DRM_ERROR("kvmalloc_array failure\n");
550	r = -ENOMEM;
551	goto out_free_user_pages;
552	}
553		515
554	r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);	516	if (!p->post_deps)
555	if (r) {	517	return -ENOMEM;
556	kvfree(e->user_pages);
557	e->user_pages = NULL;
558	goto out_free_user_pages;
559	}
560		518
561	for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
562	if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
563	userpage_invalidated = true;
564	break;
565	}
566	}
567	e->user_invalidated = userpage_invalidated;
568	}
569		519
570	r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,	520	for (i = 0; i < num_deps; ++i) {
571	&duplicates);	521	p->post_deps[i].syncobj =
572	if (unlikely(r != 0)) {	522	drm_syncobj_find(p->filp, deps[i].handle);
573	if (r != -ERESTARTSYS)	523	if (!p->post_deps[i].syncobj)
574	DRM_ERROR("ttm_eu_reserve_buffers failed.\n");	524	return -EINVAL;
575	goto out_free_user_pages;	525	p->post_deps[i].chain = NULL;
		526	p->post_deps[i].point = 0;
		527	p->num_post_deps++;
576	}	528	}
577		529
578	amdgpu_bo_list_for_each_entry(e, p->bo_list) {	530	return 0;
579	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);	531	}
580
581	e->bo_va = amdgpu_vm_bo_find(vm, bo);
582	}
583		532
584	/* Move fence waiting after getting reservation lock of	533	static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p,
585	* PD root. Then there is no need on a ctx mutex lock.	534	struct amdgpu_cs_chunk *chunk)
586	*/	535	{
587	r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entity);	536	struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
588	if (unlikely(r != 0)) {	537	unsigned num_deps;
589	if (r != -ERESTARTSYS)	538	int i;
590	DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
591	goto error_validate;
592	}
593		539
594	amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,	540	num_deps = chunk->length_dw * 4 /
595	&p->bytes_moved_vis_threshold);	541	sizeof(struct drm_amdgpu_cs_chunk_syncobj);
596	p->bytes_moved = 0;
597	p->bytes_moved_vis = 0;
598		542
599	r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,	543	if (p->post_deps)
600	amdgpu_cs_bo_validate, p);	544	return -EINVAL;
601	if (r) {
602	DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
603	goto error_validate;
604	}
605		545
606	r = amdgpu_cs_list_validate(p, &duplicates);	546	p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
607	if (r)	547	GFP_KERNEL);
608	goto error_validate;	548	p->num_post_deps = 0;
609		549
610	r = amdgpu_cs_list_validate(p, &p->validated);	550	if (!p->post_deps)
611	if (r)	551	return -ENOMEM;
612	goto error_validate;
613		552
614	amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,	553	for (i = 0; i < num_deps; ++i) {
615	p->bytes_moved_vis);	554	struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
616		555
617	gds = p->bo_list->gds_obj;	556	dep->chain = NULL;
618	gws = p->bo_list->gws_obj;	557	if (syncobj_deps[i].point) {
619	oa = p->bo_list->oa_obj;	558	dep->chain = dma_fence_chain_alloc();
		559	if (!dep->chain)
		560	return -ENOMEM;
		561	}
620		562
621	if (gds) {	563	dep->syncobj = drm_syncobj_find(p->filp,
622	p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;	564	syncobj_deps[i].handle);
623	p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;	565	if (!dep->syncobj) {
624	}	566	dma_fence_chain_free(dep->chain);
625	if (gws) {	567	return -EINVAL;
626	p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;	568	}
627	p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;	569	dep->point = syncobj_deps[i].point;
628	}	570	p->num_post_deps++;
629	if (oa) {
630	p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
631	p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
632	}	571	}
633		572
634	if (!r && p->uf_entry.tv.bo) {	573	return 0;
635	struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);	574	}
636		575
637	r = amdgpu_ttm_alloc_gart(&uf->tbo);	576	static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p)
638	p->job->uf_addr += amdgpu_bo_gpu_offset(uf);	577	{
639	}	578	unsigned int ce_preempt = 0, de_preempt = 0;
		579	int i, r;
640		580
641	error_validate:	581	for (i = 0; i < p->nchunks; ++i) {
642	if (r)	582	struct amdgpu_cs_chunk *chunk;
643	ttm_eu_backoff_reservation(&p->ticket, &p->validated);
644		583
645	out_free_user_pages:	584	chunk = &p->chunks[i];
646	if (r) {
647	amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
648	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
649		585
650	if (!e->user_pages)	586	switch (chunk->chunk_id) {
651	continue;	587	case AMDGPU_CHUNK_ID_IB:
652	amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);	588	r = amdgpu_cs_p2_ib(p, chunk, &ce_preempt, &de_preempt);
653	kvfree(e->user_pages);	589	if (r)
654	e->user_pages = NULL;	590	return r;
		591	break;
		592	case AMDGPU_CHUNK_ID_DEPENDENCIES:
		593	case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
		594	r = amdgpu_cs_p2_dependencies(p, chunk);
		595	if (r)
		596	return r;
		597	break;
		598	case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
		599	r = amdgpu_cs_p2_syncobj_in(p, chunk);
		600	if (r)
		601	return r;
		602	break;
		603	case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
		604	r = amdgpu_cs_p2_syncobj_out(p, chunk);
		605	if (r)
		606	return r;
		607	break;
		608	case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
		609	r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk);
		610	if (r)
		611	return r;
		612	break;
		613	case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
		614	r = amdgpu_cs_p2_syncobj_timeline_signal(p, chunk);
		615	if (r)
		616	return r;
		617	break;
655	}	618	}
656	mutex_unlock(&p->bo_list->bo_list_mutex);
657	}	619	}
658	return r;	620
		621	return 0;
659	}	622	}
660		623
661	static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)	624	/* Convert microseconds to bytes. */
		625	static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
662	{	626	{
663	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;	627	if (us <= 0 \|\| !adev->mm_stats.log2_max_MBps)
664	struct amdgpu_bo_list_entry *e;	628	return 0;
665	int r;
666		629
667	list_for_each_entry(e, &p->validated, tv.head) {	630	/* Since accum_us is incremented by a million per second, just
668	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);	631	* multiply it by the number of MB/s to get the number of bytes.
669	struct dma_resv *resv = bo->tbo.base.resv;	632	*/
670	enum amdgpu_sync_mode sync_mode;	633	return us << adev->mm_stats.log2_max_MBps;
		634	}
671		635
672	sync_mode = amdgpu_bo_explicit_sync(bo) ?	636	static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
673	AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;	637	{
674	r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode,	638	if (!adev->mm_stats.log2_max_MBps)
675	&fpriv->vm);	639	return 0;
676	if (r)	640
677	return r;	641	return bytes >> adev->mm_stats.log2_max_MBps;
678	}
679	return 0;
680	}	642	}
681		643
682	/**	644	/* Returns how many bytes TTM can move right now. If no bytes can be moved,
683	* amdgpu_cs_parser_fini() - clean parser states	645	* it returns 0. If it returns non-zero, it's OK to move at least one buffer,
684	* @parser: parser structure holding parsing context.	646	* which means it can go over the threshold once. If that happens, the driver
685	* @error: error number	647	* will be in debt and no other buffer migrations can be done until that debt
686	* @backoff: indicator to backoff the reservation	648	* is repaid.
		649	*
		650	* This approach allows moving a buffer of any size (it's important to allow
		651	* that).
687	*	652	*
688	* If error is set then unvalidate buffer, otherwise just free memory	653	* The currency is simply time in microseconds and it increases as the clock
689	* used by parsing context.	654	* ticks. The accumulated microseconds (us) are converted to bytes and
690	**/	655	* returned.
691	static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,	656	*/
692	bool backoff)	657	static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
		658	u64 *max_bytes,
		659	u64 *max_vis_bytes)
693	{	660	{
694	unsigned i;	661	s64 time_us, increment_us;
		662	u64 free_vram, total_vram, used_vram;
		663	/* Allow a maximum of 200 accumulated ms. This is basically per-IB
		664	* throttling.
		665	*
		666	* It means that in order to get full max MBps, at least 5 IBs per
		667	* second must be submitted and not more than 200ms apart from each
		668	* other.
		669	*/
		670	const s64 us_upper_bound = 200000;
695		671
696	if (error && backoff) {	672	if (!adev->mm_stats.log2_max_MBps) {
697	ttm_eu_backoff_reservation(&parser->ticket,	673	*max_bytes = 0;
698	&parser->validated);	674	*max_vis_bytes = 0;
699	mutex_unlock(&parser->bo_list->bo_list_mutex);	675	return;
700	}	676	}
701		677
702	for (i = 0; i < parser->num_post_deps; i++) {	678	total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
703	drm_syncobj_put(parser->post_deps[i].syncobj);	679	used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
704	kfree(parser->post_deps[i].chain);	680	free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
705	}
706	kfree(parser->post_deps);
707		681
708	dma_fence_put(parser->fence);	682	spin_lock(&adev->mm_stats.lock);
709		683
710	if (parser->ctx) {	684	/* Increase the amount of accumulated us. */
711	mutex_unlock(&parser->ctx->lock);	685	time_us = ktime_to_us(ktime_get());
712	amdgpu_ctx_put(parser->ctx);	686	increment_us = time_us - adev->mm_stats.last_update_us;
		687	adev->mm_stats.last_update_us = time_us;
		688	adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
		689	us_upper_bound);
		690
		691	/* This prevents the short period of low performance when the VRAM
		692	* usage is low and the driver is in debt or doesn't have enough
		693	* accumulated us to fill VRAM quickly.
		694	*
		695	* The situation can occur in these cases:
		696	* - a lot of VRAM is freed by userspace
		697	* - the presence of a big buffer causes a lot of evictions
		698	* (solution: split buffers into smaller ones)
		699	*
		700	* If 128 MB or 1/8th of VRAM is free, start filling it now by setting
		701	* accum_us to a positive number.
		702	*/
		703	if (free_vram >= 128 * 1024 * 1024 \|\| free_vram >= total_vram / 8) {
		704	s64 min_us;
		705
		706	/* Be more aggressive on dGPUs. Try to fill a portion of free
		707	* VRAM now.
		708	*/
		709	if (!(adev->flags & AMD_IS_APU))
		710	min_us = bytes_to_us(adev, free_vram / 4);
		711	else
		712	min_us = 0; /* Reset accum_us on APUs. */
		713
		714	adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
713	}	715	}
714	if (parser->bo_list)
715	amdgpu_bo_list_put(parser->bo_list);
716		716
717	for (i = 0; i < parser->nchunks; i++)	717	/* This is set to 0 if the driver is in debt to disallow (optional)
718	kvfree(parser->chunks[i].kdata);	718	* buffer moves.
719	kvfree(parser->chunks);	719	*/
720	if (parser->job)	720	*max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
721	amdgpu_job_free(parser->job);
722	if (parser->uf_entry.tv.bo) {
723	struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
724		721
725	amdgpu_bo_unref(&uf);	722	/* Do the same for visible VRAM if half of it is free */
		723	if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
		724	u64 total_vis_vram = adev->gmc.visible_vram_size;
		725	u64 used_vis_vram =
		726	amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
		727
		728	if (used_vis_vram < total_vis_vram) {
		729	u64 free_vis_vram = total_vis_vram - used_vis_vram;
		730	adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
		731	increment_us, us_upper_bound);
		732
		733	if (free_vis_vram >= total_vis_vram / 2)
		734	adev->mm_stats.accum_us_vis =
		735	max(bytes_to_us(adev, free_vis_vram / 2),
		736	adev->mm_stats.accum_us_vis);
		737	}
		738
		739	*max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
		740	} else {
		741	*max_vis_bytes = 0;
726	}	742	}
		743
		744	spin_unlock(&adev->mm_stats.lock);
727	}	745	}
728		746
729	static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)	747	/* Report how many bytes have really been moved for the last command
		748	* submission. This can result in a debt that can stop buffer migrations
		749	* temporarily.
		750	*/
		751	void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
		752	u64 num_vis_bytes)
730	{	753	{
731	struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);	754	spin_lock(&adev->mm_stats.lock);
732	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;	755	adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
733	struct amdgpu_device *adev = p->adev;	756	adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
734	struct amdgpu_vm *vm = &fpriv->vm;	757	spin_unlock(&adev->mm_stats.lock);
735	struct amdgpu_bo_list_entry *e;	758	}
736	struct amdgpu_bo_va *bo_va;
737	struct amdgpu_bo *bo;
738	int r;
739		759
740	/* Only for UVD/VCE VM emulation */	760	static int amdgpu_cs_bo_validate(void param, struct amdgpu_bo bo)
741	if (ring->funcs->parse_cs \|\| ring->funcs->patch_cs_in_place) {	761	{
742	unsigned i, j;	762	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
743		763	struct amdgpu_cs_parser *p = param;
744	for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {	764	struct ttm_operation_ctx ctx = {
745	struct drm_amdgpu_cs_chunk_ib *chunk_ib;	765	.interruptible = true,
746	struct amdgpu_bo_va_mapping *m;	766	.no_wait_gpu = false,
747	struct amdgpu_bo *aobj = NULL;	767	.resv = bo->tbo.base.resv
748	struct amdgpu_cs_chunk *chunk;	768	};
749	uint64_t offset, va_start;	769	uint32_t domain;
750	struct amdgpu_ib *ib;	770	int r;
751	uint8_t *kptr;
752
753	chunk = &p->chunks[i];
754	ib = &p->job->ibs[j];
755	chunk_ib = chunk->kdata;
756
757	if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
758	continue;
759		771
760	va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;	772	if (bo->tbo.pin_count)
761	r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);	773	return 0;
762	if (r) {
763	DRM_ERROR("IB va_start is invalid\n");
764	return r;
765	}
766		774
767	if ((va_start + chunk_ib->ib_bytes) >	775	/* Don't move this buffer if we have depleted our allowance
768	(m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {	776	* to move it. Don't move anything if the threshold is zero.
769	DRM_ERROR("IB va_start+ib_bytes is invalid\n");	777	*/
770	return -EINVAL;	778	if (p->bytes_moved < p->bytes_moved_threshold &&
771	}	779	(!bo->tbo.base.dma_buf \|\|
		780	list_empty(&bo->tbo.base.dma_buf->attachments))) {
		781	if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
		782	(bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
		783	/* And don't move a CPU_ACCESS_REQUIRED BO to limited
		784	* visible VRAM if we've depleted our allowance to do
		785	* that.
		786	*/
		787	if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
		788	domain = bo->preferred_domains;
		789	else
		790	domain = bo->allowed_domains;
		791	} else {
		792	domain = bo->preferred_domains;
		793	}
		794	} else {
		795	domain = bo->allowed_domains;
		796	}
772		797
773	/* the IB should be reserved at this point */	798	retry:
774	r = amdgpu_bo_kmap(aobj, (void **)&kptr);	799	amdgpu_bo_placement_from_domain(bo, domain);
775	if (r) {	800	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
776	return r;
777	}
778		801
779	offset = m->start * AMDGPU_GPU_PAGE_SIZE;	802	p->bytes_moved += ctx.bytes_moved;
780	kptr += va_start - offset;	803	if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
781		804	amdgpu_bo_in_cpu_visible_vram(bo))
782	if (ring->funcs->parse_cs) {	805	p->bytes_moved_vis += ctx.bytes_moved;
783	memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
784	amdgpu_bo_kunmap(aobj);
785
786	r = amdgpu_ring_parse_cs(ring, p, p->job, ib);
787	if (r)
788	return r;
789	} else {
790	ib->ptr = (uint32_t *)kptr;
791	r = amdgpu_ring_patch_cs_in_place(ring, p, p->job, ib);
792	amdgpu_bo_kunmap(aobj);
793	if (r)
794	return r;
795	}
796		806
797	j++;	807	if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
798	}	808	domain = bo->allowed_domains;
		809	goto retry;
799	}	810	}
800		811
801	if (!p->job->vm)	812	return r;
802	return amdgpu_cs_sync_rings(p);	813	}
803		814
		815	static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
		816	struct list_head *validated)
		817	{
		818	struct ttm_operation_ctx ctx = { true, false };
		819	struct amdgpu_bo_list_entry *lobj;
		820	int r;
804		821
805	r = amdgpu_vm_clear_freed(adev, vm, NULL);	822	list_for_each_entry(lobj, validated, tv.head) {
806	if (r)	823	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
807	return r;	824	struct mm_struct *usermm;
808		825
809	r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);	826	usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
810	if (r)	827	if (usermm && usermm != current->mm)
811	return r;	828	return -EPERM;
812		829
813	r = amdgpu_sync_fence(&p->job->sync, fpriv->prt_va->last_pt_update);	830	if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
814	if (r)	831	lobj->user_invalidated && lobj->user_pages) {
815	return r;	832	amdgpu_bo_placement_from_domain(bo,
		833	AMDGPU_GEM_DOMAIN_CPU);
		834	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
		835	if (r)
		836	return r;
816		837
817	if (amdgpu_mcbp \|\| amdgpu_sriov_vf(adev)) {	838	amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
818	bo_va = fpriv->csa_va;	839	lobj->user_pages);
819	BUG_ON(!bo_va);	840	}
820	r = amdgpu_vm_bo_update(adev, bo_va, false);
821	if (r)
822	return r;
823		841
824	r = amdgpu_sync_fence(&p->job->sync, bo_va->last_pt_update);	842	r = amdgpu_cs_bo_validate(p, bo);
825	if (r)	843	if (r)
826	return r;	844	return r;
		845
		846	kvfree(lobj->user_pages);
		847	lobj->user_pages = NULL;
827	}	848	}
		849	return 0;
		850	}
828		851
829	amdgpu_bo_list_for_each_entry(e, p->bo_list) {	852	static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
830	/* ignore duplicates */	853	union drm_amdgpu_cs *cs)
831	bo = ttm_to_amdgpu_bo(e->tv.bo);	854	{
832	if (!bo)	855	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
833	continue;	856	struct amdgpu_vm *vm = &fpriv->vm;
		857	struct amdgpu_bo_list_entry *e;
		858	struct list_head duplicates;
		859	unsigned int i;
		860	int r;
834		861
835	bo_va = e->bo_va;	862	INIT_LIST_HEAD(&p->validated);
836	if (bo_va == NULL)
837	continue;
838		863
839	r = amdgpu_vm_bo_update(adev, bo_va, false);	864	/* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
		865	if (cs->in.bo_list_handle) {
		866	if (p->bo_list)
		867	return -EINVAL;
		868
		869	r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
		870	&p->bo_list);
840	if (r)	871	if (r)
841	return r;	872	return r;
842		873	} else if (!p->bo_list) {
843	r = amdgpu_sync_fence(&p->job->sync, bo_va->last_pt_update);	874	/* Create a empty bo_list when no handle is provided */
		875	r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
		876	&p->bo_list);
844	if (r)	877	if (r)
845	return r;	878	return r;
846	}	879	}
847		880
848	r = amdgpu_vm_handle_moved(adev, vm);	881	mutex_lock(&p->bo_list->bo_list_mutex);
849	if (r)
850	return r;
851		882
852	r = amdgpu_vm_update_pdes(adev, vm, false);	883	/* One for TTM and one for the CS job */
853	if (r)	884	amdgpu_bo_list_for_each_entry(e, p->bo_list)
854	return r;	885	e->tv.num_shared = 2;
855		886
856	r = amdgpu_sync_fence(&p->job->sync, vm->last_update);	887	amdgpu_bo_list_get_list(p->bo_list, &p->validated);
857	if (r)
858	return r;
859		888
860	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);	889	INIT_LIST_HEAD(&duplicates);
		890	amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
861		891
862	if (amdgpu_vm_debug) {	892	if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
863	/* Invalidate all BOs to test for userspace bugs */	893	list_add(&p->uf_entry.tv.head, &p->validated);
864	amdgpu_bo_list_for_each_entry(e, p->bo_list) {
865	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
866		894
867	/* ignore duplicates */	895	/* Get userptr backing pages. If pages are updated after registered
868	if (!bo)	896	* in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
869	continue;	897	* amdgpu_ttm_backend_bind() to flush and invalidate new pages
		898	*/
		899	amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
		900	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
		901	bool userpage_invalidated = false;
		902	int i;
870		903
871	amdgpu_vm_bo_invalidate(adev, bo, false);	904	e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
		905	sizeof(struct page *),
		906	GFP_KERNEL \| __GFP_ZERO);
		907	if (!e->user_pages) {
		908	DRM_ERROR("kvmalloc_array failure\n");
		909	r = -ENOMEM;
		910	goto out_free_user_pages;
872	}	911	}
873	}
874
875	return amdgpu_cs_sync_rings(p);
876	}
877
878	static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
879	struct amdgpu_cs_parser *parser)
880	{
881	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
882	struct amdgpu_vm *vm = &fpriv->vm;
883	int r, ce_preempt = 0, de_preempt = 0;
884	struct amdgpu_ring *ring;
885	int i, j;
886
887	for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
888	struct amdgpu_cs_chunk *chunk;
889	struct amdgpu_ib *ib;
890	struct drm_amdgpu_cs_chunk_ib *chunk_ib;
891	struct drm_sched_entity *entity;
892		912
893	chunk = &parser->chunks[i];	913	r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);
894	ib = &parser->job->ibs[j];	914	if (r) {
895	chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;	915	kvfree(e->user_pages);
896		916	e->user_pages = NULL;
897	if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)	917	goto out_free_user_pages;
898	continue;	918	}
899		919
900	if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&	920	for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
901	(amdgpu_mcbp \|\| amdgpu_sriov_vf(adev))) {	921	if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
902	if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {	922	userpage_invalidated = true;
903	if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)	923	break;
904	ce_preempt++;
905	else
906	de_preempt++;
907	}	924	}
908
909	/* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
910	if (ce_preempt > 1 \|\| de_preempt > 1)
911	return -EINVAL;
912	}	925	}
		926	e->user_invalidated = userpage_invalidated;
		927	}
913		928
914	r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,	929	r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
915	chunk_ib->ip_instance, chunk_ib->ring,	930	&duplicates);
916	&entity);	931	if (unlikely(r != 0)) {
917	if (r)	932	if (r != -ERESTARTSYS)
918	return r;	933	DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
919		934	goto out_free_user_pages;
920	if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)	935	}
921	parser->job->preamble_status \|=
922	AMDGPU_PREAMBLE_IB_PRESENT;
923
924	if (parser->entity && parser->entity != entity)
925	return -EINVAL;
926
927	/* Return if there is no run queue associated with this entity.
928	* Possibly because of disabled HW IP*/
929	if (entity->rq == NULL)
930	return -EINVAL;
931
932	parser->entity = entity;
933
934	ring = to_amdgpu_ring(entity->rq->sched);
935	r = amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
936	chunk_ib->ib_bytes : 0,
937	AMDGPU_IB_POOL_DELAYED, ib);
938	if (r) {
939	DRM_ERROR("Failed to get ib !\n");
940	return r;
941	}
942		936
943	ib->gpu_addr = chunk_ib->va_start;	937	amdgpu_bo_list_for_each_entry(e, p->bo_list) {
944	ib->length_dw = chunk_ib->ib_bytes / 4;	938	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
945	ib->flags = chunk_ib->flags;
946		939
947	j++;	940	e->bo_va = amdgpu_vm_bo_find(vm, bo);
948	}	941	}
949		942
950	/* MM engine doesn't support user fences */	943	amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
951	ring = to_amdgpu_ring(parser->entity->rq->sched);	944	&p->bytes_moved_vis_threshold);
952	if (parser->job->uf_addr && ring->funcs->no_user_fence)	945	p->bytes_moved = 0;
953	return -EINVAL;	946	p->bytes_moved_vis = 0;
954		947
955	return 0;	948	r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
956	}	949	amdgpu_cs_bo_validate, p);
		950	if (r) {
		951	DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
		952	goto error_validate;
		953	}
957		954
958	static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,	955	r = amdgpu_cs_list_validate(p, &duplicates);
959	struct amdgpu_cs_chunk *chunk)	956	if (r)
960	{	957	goto error_validate;
961	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
962	unsigned num_deps;
963	int i, r;
964	struct drm_amdgpu_cs_chunk_dep *deps;
965		958
966	deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;	959	r = amdgpu_cs_list_validate(p, &p->validated);
967	num_deps = chunk->length_dw * 4 /	960	if (r)
968	sizeof(struct drm_amdgpu_cs_chunk_dep);	961	goto error_validate;
969		962
970	for (i = 0; i < num_deps; ++i) {	963	if (p->uf_entry.tv.bo) {
971	struct amdgpu_ctx *ctx;	964	struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
972	struct drm_sched_entity *entity;
973	struct dma_fence *fence;
974		965
975	ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);	966	r = amdgpu_ttm_alloc_gart(&uf->tbo);
976	if (ctx == NULL)	967	if (r)
977	return -EINVAL;	968	goto error_validate;
978		969
979	r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,	970	p->gang_leader->uf_addr += amdgpu_bo_gpu_offset(uf);
980	deps[i].ip_instance,	971	}
981	deps[i].ring, &entity);
982	if (r) {
983	amdgpu_ctx_put(ctx);
984	return r;
985	}
986		972
987	fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);	973	amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
988	amdgpu_ctx_put(ctx);	974	p->bytes_moved_vis);
989		975
990	if (IS_ERR(fence))	976	for (i = 0; i < p->gang_size; ++i)
991	return PTR_ERR(fence);	977	amdgpu_job_set_resources(p->jobs[i], p->bo_list->gds_obj,
992	else if (!fence)	978	p->bo_list->gws_obj,
993	continue;	979	p->bo_list->oa_obj);
		980	return 0;
994		981
995	if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {	982	error_validate:
996	struct drm_sched_fence *s_fence;	983	ttm_eu_backoff_reservation(&p->ticket, &p->validated);
997	struct dma_fence *old = fence;
998		984
999	s_fence = to_drm_sched_fence(fence);	985	out_free_user_pages:
1000	fence = dma_fence_get(&s_fence->scheduled);	986	amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1001	dma_fence_put(old);	987	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1002	}
1003		988
1004	r = amdgpu_sync_fence(&p->job->sync, fence);	989	if (!e->user_pages)
1005	dma_fence_put(fence);	990	continue;
1006	if (r)	991	amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1007	return r;	992	kvfree(e->user_pages);
		993	e->user_pages = NULL;
1008	}	994	}
1009	return 0;	995	return r;
1010	}	996	}
1011		997
1012	static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,	998	static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *p)
1013	uint32_t handle, u64 point,
1014	u64 flags)
1015	{	999	{
1016	struct dma_fence *fence;	1000	int i, j;
1017	int r;
1018		1001
1019	r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);	1002	if (!trace_amdgpu_cs_enabled())
1020	if (r) {	1003	return;
1021	DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
1022	handle, point, r);
1023	return r;
1024	}
1025		1004
1026	r = amdgpu_sync_fence(&p->job->sync, fence);	1005	for (i = 0; i < p->gang_size; ++i) {
1027	dma_fence_put(fence);	1006	struct amdgpu_job *job = p->jobs[i];
1028		1007
1029	return r;	1008	for (j = 0; j < job->num_ibs; ++j)
		1009	trace_amdgpu_cs(p, job, &job->ibs[j]);
		1010	}
1030	}	1011	}
1031		1012
1032	static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,	1013	static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,
1033	struct amdgpu_cs_chunk *chunk)	1014	struct amdgpu_job *job)
1034	{	1015	{
1035	struct drm_amdgpu_cs_chunk_sem *deps;	1016	struct amdgpu_ring *ring = amdgpu_job_ring(job);
1036	unsigned num_deps;	1017	unsigned int i;
1037	int i, r;	1018	int r;
1038		1019
1039	deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;	1020	/* Only for UVD/VCE VM emulation */
1040	num_deps = chunk->length_dw * 4 /	1021	if (!ring->funcs->parse_cs && !ring->funcs->patch_cs_in_place)
1041	sizeof(struct drm_amdgpu_cs_chunk_sem);	1022	return 0;
1042	for (i = 0; i < num_deps; ++i) {	1023
1043	r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,	1024	for (i = 0; i < job->num_ibs; ++i) {
1044	0, 0);	1025	struct amdgpu_ib *ib = &job->ibs[i];
1045	if (r)	1026	struct amdgpu_bo_va_mapping *m;
		1027	struct amdgpu_bo *aobj;
		1028	uint64_t va_start;
		1029	uint8_t *kptr;
		1030
		1031	va_start = ib->gpu_addr & AMDGPU_GMC_HOLE_MASK;
		1032	r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
		1033	if (r) {
		1034	DRM_ERROR("IB va_start is invalid\n");
1046	return r;	1035	return r;
		1036	}
		1037
		1038	if ((va_start + ib->length_dw * 4) >
		1039	(m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
		1040	DRM_ERROR("IB va_start+ib_bytes is invalid\n");
		1041	return -EINVAL;
		1042	}
		1043
		1044	/* the IB should be reserved at this point */
		1045	r = amdgpu_bo_kmap(aobj, (void **)&kptr);
		1046	if (r) {
		1047	return r;
		1048	}
		1049
		1050	kptr += va_start - (m->start * AMDGPU_GPU_PAGE_SIZE);
		1051
		1052	if (ring->funcs->parse_cs) {
		1053	memcpy(ib->ptr, kptr, ib->length_dw * 4);
		1054	amdgpu_bo_kunmap(aobj);
		1055
		1056	r = amdgpu_ring_parse_cs(ring, p, job, ib);
		1057	if (r)
		1058	return r;
		1059	} else {
		1060	ib->ptr = (uint32_t *)kptr;
		1061	r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);
		1062	amdgpu_bo_kunmap(aobj);
		1063	if (r)
		1064	return r;
		1065	}
1047	}	1066	}
1048		1067
1049	return 0;	1068	return 0;
1050	}	1069	}
1051		1070
1052		1071	static int amdgpu_cs_patch_jobs(struct amdgpu_cs_parser *p)
1053	static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
1054	struct amdgpu_cs_chunk *chunk)
1055	{	1072	{
1056	struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;	1073	unsigned int i;
1057	unsigned num_deps;	1074	int r;
1058	int i, r;
1059		1075
1060	syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;	1076	for (i = 0; i < p->gang_size; ++i) {
1061	num_deps = chunk->length_dw * 4 /	1077	r = amdgpu_cs_patch_ibs(p, p->jobs[i]);
1062	sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1063	for (i = 0; i < num_deps; ++i) {
1064	r = amdgpu_syncobj_lookup_and_add_to_sync(p,
1065	syncobj_deps[i].handle,
1066	syncobj_deps[i].point,
1067	syncobj_deps[i].flags);
1068	if (r)	1078	if (r)
1069	return r;	1079	return r;
1070	}	1080	}
1071
1072	return 0;	1081	return 0;
1073	}	1082	}
1074		1083
1075	static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,	1084	static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
1076	struct amdgpu_cs_chunk *chunk)
1077	{	1085	{
1078	struct drm_amdgpu_cs_chunk_sem *deps;	1086	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1079	unsigned num_deps;	1087	struct amdgpu_job *job = p->gang_leader;
1080	int i;	1088	struct amdgpu_device *adev = p->adev;
1081		1089	struct amdgpu_vm *vm = &fpriv->vm;
1082	deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;	1090	struct amdgpu_bo_list_entry *e;
1083	num_deps = chunk->length_dw * 4 /	1091	struct amdgpu_bo_va *bo_va;
1084	sizeof(struct drm_amdgpu_cs_chunk_sem);	1092	struct amdgpu_bo *bo;
		1093	unsigned int i;
		1094	int r;
1085		1095
1086	if (p->post_deps)	1096	r = amdgpu_vm_clear_freed(adev, vm, NULL);
1087	return -EINVAL;	1097	if (r)
		1098	return r;
1088		1099
1089	p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),	1100	r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
1090	GFP_KERNEL);	1101	if (r)
1091	p->num_post_deps = 0;	1102	return r;
1092		1103
1093	if (!p->post_deps)	1104	r = amdgpu_sync_fence(&job->sync, fpriv->prt_va->last_pt_update);
1094	return -ENOMEM;	1105	if (r)
		1106	return r;
1095		1107
		1108	if (fpriv->csa_va) {
		1109	bo_va = fpriv->csa_va;
		1110	BUG_ON(!bo_va);
		1111	r = amdgpu_vm_bo_update(adev, bo_va, false);
		1112	if (r)
		1113	return r;
1096		1114
1097	for (i = 0; i < num_deps; ++i) {	1115	r = amdgpu_sync_fence(&job->sync, bo_va->last_pt_update);
1098	p->post_deps[i].syncobj =	1116	if (r)
1099	drm_syncobj_find(p->filp, deps[i].handle);	1117	return r;
1100	if (!p->post_deps[i].syncobj)
1101	return -EINVAL;
1102	p->post_deps[i].chain = NULL;
1103	p->post_deps[i].point = 0;
1104	p->num_post_deps++;
1105	}	1118	}
1106		1119
1107	return 0;	1120	amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1108	}	1121	/* ignore duplicates */
		1122	bo = ttm_to_amdgpu_bo(e->tv.bo);
		1123	if (!bo)
		1124	continue;
1109		1125
		1126	bo_va = e->bo_va;
		1127	if (bo_va == NULL)
		1128	continue;
1110		1129
1111	static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,	1130	r = amdgpu_vm_bo_update(adev, bo_va, false);
1112	struct amdgpu_cs_chunk *chunk)	1131	if (r)
1113	{	1132	return r;
1114	struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1115	unsigned num_deps;
1116	int i;
1117		1133
1118	syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;	1134	r = amdgpu_sync_fence(&job->sync, bo_va->last_pt_update);
1119	num_deps = chunk->length_dw * 4 /	1135	if (r)
1120	sizeof(struct drm_amdgpu_cs_chunk_syncobj);	1136	return r;
		1137	}
1121		1138
1122	if (p->post_deps)	1139	r = amdgpu_vm_handle_moved(adev, vm);
1123	return -EINVAL;	1140	if (r)
		1141	return r;
1124		1142
1125	p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),	1143	r = amdgpu_vm_update_pdes(adev, vm, false);
1126	GFP_KERNEL);	1144	if (r)
1127	p->num_post_deps = 0;	1145	return r;
1128		1146
1129	if (!p->post_deps)	1147	r = amdgpu_sync_fence(&job->sync, vm->last_update);
1130	return -ENOMEM;	1148	if (r)
		1149	return r;
1131		1150
1132	for (i = 0; i < num_deps; ++i) {	1151	for (i = 0; i < p->gang_size; ++i) {
1133	struct amdgpu_cs_post_dep *dep = &p->post_deps[i];	1152	job = p->jobs[i];
1134		1153
1135	dep->chain = NULL;	1154	if (!job->vm)
1136	if (syncobj_deps[i].point) {	1155	continue;
1137	dep->chain = dma_fence_chain_alloc();
1138	if (!dep->chain)
1139	return -ENOMEM;
1140	}
1141		1156
1142	dep->syncobj = drm_syncobj_find(p->filp,	1157	job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
1143	syncobj_deps[i].handle);	1158	}
1144	if (!dep->syncobj) {	1159
1145	dma_fence_chain_free(dep->chain);	1160	if (amdgpu_vm_debug) {
1146	return -EINVAL;	1161	/* Invalidate all BOs to test for userspace bugs */
		1162	amdgpu_bo_list_for_each_entry(e, p->bo_list) {
		1163	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
		1164
		1165	/* ignore duplicates */
		1166	if (!bo)
		1167	continue;
		1168
		1169	amdgpu_vm_bo_invalidate(adev, bo, false);
1147	}	1170	}
1148	dep->point = syncobj_deps[i].point;
1149	p->num_post_deps++;
1150	}	1171	}
1151		1172
1152	return 0;	1173	return 0;
1153	}	1174	}
1154		1175
1155	static int amdgpu_cs_dependencies(struct amdgpu_device *adev,	1176	static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
1156	struct amdgpu_cs_parser *p)
1157	{	1177	{
1158	int i, r;	1178	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1159		1179	struct amdgpu_job *leader = p->gang_leader;
1160	/* TODO: Investigate why we still need the context lock */	1180	struct amdgpu_bo_list_entry *e;
1161	mutex_unlock(&p->ctx->lock);	1181	unsigned int i;
		1182	int r;
1162		1183
1163	for (i = 0; i < p->nchunks; ++i) {	1184	list_for_each_entry(e, &p->validated, tv.head) {
1164	struct amdgpu_cs_chunk *chunk;	1185	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
		1186	struct dma_resv *resv = bo->tbo.base.resv;
		1187	enum amdgpu_sync_mode sync_mode;
1165		1188
1166	chunk = &p->chunks[i];	1189	sync_mode = amdgpu_bo_explicit_sync(bo) ?
		1190	AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
		1191	r = amdgpu_sync_resv(p->adev, &leader->sync, resv, sync_mode,
		1192	&fpriv->vm);
		1193	if (r)
		1194	return r;
		1195	}
1167		1196
1168	switch (chunk->chunk_id) {	1197	for (i = 0; i < p->gang_size - 1; ++i) {
1169	case AMDGPU_CHUNK_ID_DEPENDENCIES:	1198	r = amdgpu_sync_clone(&leader->sync, &p->jobs[i]->sync);
1170	case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:	1199	if (r)
1171	r = amdgpu_cs_process_fence_dep(p, chunk);	1200	return r;
1172	if (r)
1173	goto out;
1174	break;
1175	case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
1176	r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1177	if (r)
1178	goto out;
1179	break;
1180	case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
1181	r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1182	if (r)
1183	goto out;
1184	break;
1185	case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
1186	r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
1187	if (r)
1188	goto out;
1189	break;
1190	case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
1191	r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
1192	if (r)
1193	goto out;
1194	break;
1195	}
1196	}	1201	}
1197		1202
1198	out:	1203	r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entities[p->gang_size - 1]);
1199	mutex_lock(&p->ctx->lock);	1204	if (r && r != -ERESTARTSYS)
		1205	DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
		1206
1200	return r;	1207	return r;
1201	}	1208	}
1202		1209
@@ -1221,20 +1228,28 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, · 18 unmodified lines
1221	union drm_amdgpu_cs *cs)	1228	union drm_amdgpu_cs *cs)
1222	{	1229	{
1223	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;	1230	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1224	struct drm_sched_entity *entity = p->entity;	1231	struct amdgpu_job *leader = p->gang_leader;
1225	struct amdgpu_bo_list_entry *e;	1232	struct amdgpu_bo_list_entry *e;
1226	struct amdgpu_job *job;	1233	unsigned int i;
1227	uint64_t seq;	1234	uint64_t seq;
1228	int r;	1235	int r;
1229		1236
1230	job = p->job;	1237	for (i = 0; i < p->gang_size; ++i)
1231	p->job = NULL;	1238	drm_sched_job_arm(&p->jobs[i]->base);
1232		1239
1233	r = drm_sched_job_init(&job->base, entity, &fpriv->vm);	1240	for (i = 0; i < (p->gang_size - 1); ++i) {
1234	if (r)	1241	struct dma_fence *fence;
1235	goto error_unlock;	1242
		1243	fence = &p->jobs[i]->base.s_fence->scheduled;
		1244	r = amdgpu_sync_fence(&leader->sync, fence);
		1245	if (r)
		1246	goto error_cleanup;
		1247	}
1236		1248
1237	drm_sched_job_arm(&job->base);	1249	if (p->gang_size > 1) {
		1250	for (i = 0; i < p->gang_size; ++i)
		1251	amdgpu_job_set_gang_leader(p->jobs[i], leader);
		1252	}
1238		1253
1239	/* No memory allocation is allowed while holding the notifier lock.	1254	/* No memory allocation is allowed while holding the notifier lock.
1240	* The lock is held until amdgpu_cs_submit is finished and fence is	1255	* The lock is held until amdgpu_cs_submit is finished and fence is
@@ -1245,6 +1260,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, · 4 unmodified lines
1245	/* If userptr are invalidated after amdgpu_cs_parser_bos(), return	1260	/* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1246	* -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.	1261	* -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1247	*/	1262	*/
		1263	r = 0;
1248	amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {	1264	amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1249	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);	1265	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1250		1266
@@ -1252,67 +1268,96 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, · 1 unmodified line
1252	}	1268	}
1253	if (r) {	1269	if (r) {
1254	r = -EAGAIN;	1270	r = -EAGAIN;
1255	goto error_abort;	1271	goto error_unlock;
1256	}	1272	}
1257		1273
1258	p->fence = dma_fence_get(&job->base.s_fence->finished);	1274	p->fence = dma_fence_get(&leader->base.s_fence->finished);
		1275	list_for_each_entry(e, &p->validated, tv.head) {
		1276
		1277	/* Everybody except for the gang leader uses READ */
		1278	for (i = 0; i < (p->gang_size - 1); ++i) {
		1279	dma_resv_add_fence(e->tv.bo->base.resv,
		1280	&p->jobs[i]->base.s_fence->finished,
		1281	DMA_RESV_USAGE_READ);
		1282	}
		1283
		1284	/* The gang leader is remembered as writer */
		1285	e->tv.num_shared = 0;
		1286	}
1259		1287
1260	seq = amdgpu_ctx_add_fence(p->ctx, entity, p->fence);	1288	seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_size - 1],
		1289	p->fence);
1261	amdgpu_cs_post_dependencies(p);	1290	amdgpu_cs_post_dependencies(p);
1262		1291
1263	if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&	1292	if ((leader->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1264	!p->ctx->preamble_presented) {	1293	!p->ctx->preamble_presented) {
1265	job->preamble_status \|= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;	1294	leader->preamble_status \|= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1266	p->ctx->preamble_presented = true;	1295	p->ctx->preamble_presented = true;
1267	}	1296	}
1268		1297
1269	cs->out.handle = seq;	1298	cs->out.handle = seq;
1270	job->uf_sequence = seq;	1299	leader->uf_sequence = seq;
1271		1300
1272	amdgpu_job_free_resources(job);
1273
1274	trace_amdgpu_cs_ioctl(job);
1275	amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);	1301	amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1276	drm_sched_entity_push_job(&job->base);	1302	for (i = 0; i < p->gang_size; ++i) {
		1303	amdgpu_job_free_resources(p->jobs[i]);
		1304	trace_amdgpu_cs_ioctl(p->jobs[i]);
		1305	drm_sched_entity_push_job(&p->jobs[i]->base);
		1306	p->jobs[i] = NULL;
		1307	}
1277		1308
1278	amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);	1309	amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1279
1280	/* Make sure all BOs are remembered as writers */
1281	amdgpu_bo_list_for_each_entry(e, p->bo_list)
1282	e->tv.num_shared = 0;
1283
1284	ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);	1310	ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
		1311
1285	mutex_unlock(&p->adev->notifier_lock);	1312	mutex_unlock(&p->adev->notifier_lock);
1286	mutex_unlock(&p->bo_list->bo_list_mutex);	1313	mutex_unlock(&p->bo_list->bo_list_mutex);
1287
1288	return 0;	1314	return 0;
1289		1315
1290	error_abort:	1316	error_unlock:
1291	drm_sched_job_cleanup(&job->base);
1292	mutex_unlock(&p->adev->notifier_lock);	1317	mutex_unlock(&p->adev->notifier_lock);
1293		1318
1294	error_unlock:	1319	error_cleanup:
1295	amdgpu_job_free(job);	1320	for (i = 0; i < p->gang_size; ++i)
		1321	drm_sched_job_cleanup(&p->jobs[i]->base);
1296	return r;	1322	return r;
1297	}	1323	}
1298		1324
1299	static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser)	1325	/* Cleanup the parser structure */
		1326	static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser)
1300	{	1327	{
1301	int i;	1328	unsigned i;
1302		1329
1303	if (!trace_amdgpu_cs_enabled())	1330	for (i = 0; i < parser->num_post_deps; i++) {
1304	return;	1331	drm_syncobj_put(parser->post_deps[i].syncobj);
		1332	kfree(parser->post_deps[i].chain);
		1333	}
		1334	kfree(parser->post_deps);
		1335
		1336	dma_fence_put(parser->fence);
		1337
		1338	if (parser->ctx)
		1339	amdgpu_ctx_put(parser->ctx);
		1340	if (parser->bo_list)
		1341	amdgpu_bo_list_put(parser->bo_list);
		1342
		1343	for (i = 0; i < parser->nchunks; i++)
		1344	kvfree(parser->chunks[i].kdata);
		1345	kvfree(parser->chunks);
		1346	for (i = 0; i < parser->gang_size; ++i) {
		1347	if (parser->jobs[i])
		1348	amdgpu_job_free(parser->jobs[i]);
		1349	}
		1350	if (parser->uf_entry.tv.bo) {
		1351	struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
1305		1352
1306	for (i = 0; i < parser->job->num_ibs; i++)	1353	amdgpu_bo_unref(&uf);
1307	trace_amdgpu_cs(parser, i);	1354	}
1308	}	1355	}
1309		1356
1310	int amdgpu_cs_ioctl(struct drm_device dev, void data, struct drm_file *filp)	1357	int amdgpu_cs_ioctl(struct drm_device dev, void data, struct drm_file *filp)
1311	{	1358	{
1312	struct amdgpu_device *adev = drm_to_adev(dev);	1359	struct amdgpu_device *adev = drm_to_adev(dev);
1313	union drm_amdgpu_cs *cs = data;	1360	struct amdgpu_cs_parser parser;
1314	struct amdgpu_cs_parser parser = {};
1315	bool reserved_buffers = false;
1316	int r;	1361	int r;
1317		1362
1318	if (amdgpu_ras_intr_triggered())	1363	if (amdgpu_ras_intr_triggered())
@@ -1321,25 +1366,20 @@ int amdgpu_cs_ioctl(struct drm_device dev, void data, struct drm_file *filp) · 2 unmodified lines
1321	if (!adev->accel_working)	1366	if (!adev->accel_working)
1322	return -EBUSY;	1367	return -EBUSY;
1323		1368
1324	parser.adev = adev;	1369	r = amdgpu_cs_parser_init(&parser, adev, filp, data);
1325	parser.filp = filp;
1326
1327	r = amdgpu_cs_parser_init(&parser, data);
1328	if (r) {	1370	if (r) {
1329	if (printk_ratelimit())	1371	if (printk_ratelimit())
1330	DRM_ERROR("Failed to initialize parser %d!\n", r);	1372	DRM_ERROR("Failed to initialize parser %d!\n", r);
1331	goto out;	1373	return r;
1332	}	1374	}
1333		1375
1334	r = amdgpu_cs_ib_fill(adev, &parser);	1376	r = amdgpu_cs_pass1(&parser, data);
1335	if (r)	1377	if (r)
1336	goto out;	1378	goto error_fini;
1337		1379
1338	r = amdgpu_cs_dependencies(adev, &parser);	1380	r = amdgpu_cs_pass2(&parser);
1339	if (r) {	1381	if (r)
1340	DRM_ERROR("Failed in the dependencies handling %d!\n", r);	1382	goto error_fini;
1341	goto out;
1342	}
1343		1383
1344	r = amdgpu_cs_parser_bos(&parser, data);	1384	r = amdgpu_cs_parser_bos(&parser, data);
1345	if (r) {	1385	if (r) {
@@ -1347,22 +1387,36 @@ int amdgpu_cs_ioctl(struct drm_device dev, void data, struct drm_file *filp) · 1 unmodified line
1347	DRM_ERROR("Not enough memory for command submission!\n");	1387	DRM_ERROR("Not enough memory for command submission!\n");
1348	else if (r != -ERESTARTSYS && r != -EAGAIN)	1388	else if (r != -ERESTARTSYS && r != -EAGAIN)
1349	DRM_ERROR("Failed to process the buffer list %d!\n", r);	1389	DRM_ERROR("Failed to process the buffer list %d!\n", r);
1350	goto out;	1390	goto error_fini;
1351	}	1391	}
1352		1392
1353	reserved_buffers = true;	1393	r = amdgpu_cs_patch_jobs(&parser);
		1394	if (r)
		1395	goto error_backoff;
		1396
		1397	r = amdgpu_cs_vm_handling(&parser);
		1398	if (r)
		1399	goto error_backoff;
		1400
		1401	r = amdgpu_cs_sync_rings(&parser);
		1402	if (r)
		1403	goto error_backoff;
1354		1404
1355	trace_amdgpu_cs_ibs(&parser);	1405	trace_amdgpu_cs_ibs(&parser);
1356		1406
1357	r = amdgpu_cs_vm_handling(&parser);	1407	r = amdgpu_cs_submit(&parser, data);
1358	if (r)	1408	if (r)
1359	goto out;	1409	goto error_backoff;
1360		1410
1361	r = amdgpu_cs_submit(&parser, cs);	1411	amdgpu_cs_parser_fini(&parser);
		1412	return 0;
1362		1413
1363	out:	1414	error_backoff:
1364	amdgpu_cs_parser_fini(&parser, r, reserved_buffers);	1415	ttm_eu_backoff_reservation(&parser.ticket, &parser.validated);
		1416	mutex_unlock(&parser.bo_list->bo_list_mutex);
1365		1417
		1418	error_fini:
		1419	amdgpu_cs_parser_fini(&parser);
1366	return r;	1420	return r;
1367	}	1421	}
1368		1422

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h+7−3

 #include "amdgpu_bo_list.h"
 #include "amdgpu_ring.h"
+#define AMDGPU_CS_GANG_SIZE	4
 struct amdgpu_bo_va_mapping;
 struct amdgpu_cs_chunk {
 	unsigned		nchunks;
 	struct amdgpu_cs_chunk	*chunks;
-	/* scheduler job object */
+	/* scheduler job objects */
-	struct amdgpu_job	*job;
+	unsigned int		gang_size;
-	struct drm_sched_entity	*entity;
+	struct drm_sched_entity	*entities[AMDGPU_CS_GANG_SIZE];
+	struct amdgpu_job	*jobs[AMDGPU_CS_GANG_SIZE];
+	struct amdgpu_job	*gang_leader;
 	/* buffer objects */
 	struct ww_acquire_ctx		ticket;

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c+2−4

 	kref_init(&ctx->refcount);
 	ctx->mgr = mgr;
 	spin_lock_init(&ctx->ring_lock);
-	mutex_init(&ctx->lock);
 	ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter);
 	ctx->reset_counter_query = ctx->reset_counter;
 		}
 	}
-	if (drm_dev_enter(&adev->ddev, &idx)) {
+	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 		amdgpu_ctx_set_stable_pstate(ctx, ctx->stable_pstate);
 		drm_dev_exit(idx);
 	}
-	mutex_destroy(&ctx->lock);
 	kfree(ctx);
 }
 	mgr->adev = adev;
 	mutex_init(&mgr->lock);
-	idr_init(&mgr->ctx_handles);
+	idr_init_base(&mgr->ctx_handles, 1);
 	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
 		atomic64_set(&mgr->time_spend[i], 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h+0−1

@@ -53,7 +53,6 @@ struct amdgpu_ctx { · 52 unmodified lines
53	bool preamble_presented;	53	bool preamble_presented;
54	int32_t init_priority;	54	int32_t init_priority;
55	int32_t override_priority;	55	int32_t override_priority;
56	struct mutex lock;
57	atomic_t guilty;	56	atomic_t guilty;
58	unsigned long ras_counter_ce;	57	unsigned long ras_counter_ce;
59	unsigned long ras_counter_ue;	58	unsigned long ras_counter_ue;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c+170−0

@@ -1042,6 +1042,157 @@ err: · 1041 unmodified lines
1042	return r;	1042	return r;
1043	}	1043	}
1044		1044
		1045	/**
		1046	* amdgpu_debugfs_gfxoff_residency_read - Read GFXOFF residency
		1047	*
		1048	* @f: open file handle
		1049	* @buf: User buffer to store read data in
		1050	* @size: Number of bytes to read
		1051	* @pos: Offset to seek to
		1052	*
		1053	* Read the last residency value logged. It doesn't auto update, one needs to
		1054	* stop logging before getting the current value.
		1055	*/
		1056	static ssize_t amdgpu_debugfs_gfxoff_residency_read(struct file f, char __user buf,
		1057	size_t size, loff_t *pos)
		1058	{
		1059	struct amdgpu_device *adev = file_inode(f)->i_private;
		1060	ssize_t result = 0;
		1061	int r;
		1062
		1063	if (size & 0x3 \|\| *pos & 0x3)
		1064	return -EINVAL;
		1065
		1066	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
		1067	if (r < 0) {
		1068	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
		1069	return r;
		1070	}
		1071
		1072	while (size) {
		1073	uint32_t value;
		1074
		1075	r = amdgpu_get_gfx_off_residency(adev, &value);
		1076	if (r)
		1077	goto out;
		1078
		1079	r = put_user(value, (uint32_t *)buf);
		1080	if (r)
		1081	goto out;
		1082
		1083	result += 4;
		1084	buf += 4;
		1085	*pos += 4;
		1086	size -= 4;
		1087	}
		1088
		1089	r = result;
		1090	out:
		1091	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
		1092	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
		1093
		1094	return r;
		1095	}
		1096
		1097	/**
		1098	* amdgpu_debugfs_gfxoff_residency_write - Log GFXOFF Residency
		1099	*
		1100	* @f: open file handle
		1101	* @buf: User buffer to write data from
		1102	* @size: Number of bytes to write
		1103	* @pos: Offset to seek to
		1104	*
		1105	* Write a 32-bit non-zero to start logging; write a 32-bit zero to stop
		1106	*/
		1107	static ssize_t amdgpu_debugfs_gfxoff_residency_write(struct file f, const char __user buf,
		1108	size_t size, loff_t *pos)
		1109	{
		1110	struct amdgpu_device *adev = file_inode(f)->i_private;
		1111	ssize_t result = 0;
		1112	int r;
		1113
		1114	if (size & 0x3 \|\| *pos & 0x3)
		1115	return -EINVAL;
		1116
		1117	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
		1118	if (r < 0) {
		1119	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
		1120	return r;
		1121	}
		1122
		1123	while (size) {
		1124	u32 value;
		1125
		1126	r = get_user(value, (uint32_t *)buf);
		1127	if (r)
		1128	goto out;
		1129
		1130	amdgpu_set_gfx_off_residency(adev, value ? true : false);
		1131
		1132	result += 4;
		1133	buf += 4;
		1134	*pos += 4;
		1135	size -= 4;
		1136	}
		1137
		1138	r = result;
		1139	out:
		1140	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
		1141	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
		1142
		1143	return r;
		1144	}
		1145
		1146
		1147	/**
		1148	* amdgpu_debugfs_gfxoff_count_read - Read GFXOFF entry count
		1149	*
		1150	* @f: open file handle
		1151	* @buf: User buffer to store read data in
		1152	* @size: Number of bytes to read
		1153	* @pos: Offset to seek to
		1154	*/
		1155	static ssize_t amdgpu_debugfs_gfxoff_count_read(struct file f, char __user buf,
		1156	size_t size, loff_t *pos)
		1157	{
		1158	struct amdgpu_device *adev = file_inode(f)->i_private;
		1159	ssize_t result = 0;
		1160	int r;
		1161
		1162	if (size & 0x3 \|\| *pos & 0x3)
		1163	return -EINVAL;
		1164
		1165	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
		1166	if (r < 0) {
		1167	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
		1168	return r;
		1169	}
		1170
		1171	while (size) {
		1172	u64 value = 0;
		1173
		1174	r = amdgpu_get_gfx_off_entrycount(adev, &value);
		1175	if (r)
		1176	goto out;
		1177
		1178	r = put_user(value, (u64 *)buf);
		1179	if (r)
		1180	goto out;
		1181
		1182	result += 4;
		1183	buf += 4;
		1184	*pos += 4;
		1185	size -= 4;
		1186	}
		1187
		1188	r = result;
		1189	out:
		1190	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
		1191	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
		1192
		1193	return r;
		1194	}
		1195
1045	/**	1196	/**
1046	* amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF	1197	* amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF
1047	*	1198	*
@@ -1249,6 +1400,19 @@ static const struct file_operations amdgpu_debugfs_gfxoff_status_fops = { · 201 unmodified lines
1249	.llseek = default_llseek	1400	.llseek = default_llseek
1250	};	1401	};
1251		1402
		1403	static const struct file_operations amdgpu_debugfs_gfxoff_count_fops = {
		1404	.owner = THIS_MODULE,
		1405	.read = amdgpu_debugfs_gfxoff_count_read,
		1406	.llseek = default_llseek
		1407	};
		1408
		1409	static const struct file_operations amdgpu_debugfs_gfxoff_residency_fops = {
		1410	.owner = THIS_MODULE,
		1411	.read = amdgpu_debugfs_gfxoff_residency_read,
		1412	.write = amdgpu_debugfs_gfxoff_residency_write,
		1413	.llseek = default_llseek
		1414	};
		1415
1252	static const struct file_operations *debugfs_regs[] = {	1416	static const struct file_operations *debugfs_regs[] = {
1253	&amdgpu_debugfs_regs_fops,	1417	&amdgpu_debugfs_regs_fops,
1254	&amdgpu_debugfs_regs2_fops,	1418	&amdgpu_debugfs_regs2_fops,
@@ -1261,6 +1425,8 @@ static const struct file_operations *debugfs_regs[] = { · 6 unmodified lines
1261	&amdgpu_debugfs_gpr_fops,	1425	&amdgpu_debugfs_gpr_fops,
1262	&amdgpu_debugfs_gfxoff_fops,	1426	&amdgpu_debugfs_gfxoff_fops,
1263	&amdgpu_debugfs_gfxoff_status_fops,	1427	&amdgpu_debugfs_gfxoff_status_fops,
		1428	&amdgpu_debugfs_gfxoff_count_fops,
		1429	&amdgpu_debugfs_gfxoff_residency_fops,
1264	};	1430	};
1265		1431
1266	static const char *debugfs_regs_names[] = {	1432	static const char *debugfs_regs_names[] = {
@@ -1275,6 +1441,8 @@ static const char *debugfs_regs_names[] = { · 8 unmodified lines
1275	"amdgpu_gpr",	1441	"amdgpu_gpr",
1276	"amdgpu_gfxoff",	1442	"amdgpu_gfxoff",
1277	"amdgpu_gfxoff_status",	1443	"amdgpu_gfxoff_status",
		1444	"amdgpu_gfxoff_count",
		1445	"amdgpu_gfxoff_residency",
1278	};	1446	};
1279		1447
1280	/**	1448	/**
@@ -1786,6 +1954,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) · 505 unmodified lines
1786	return PTR_ERR(ent);	1954	return PTR_ERR(ent);
1787	}	1955	}
1788		1956
		1957	debugfs_create_u32("amdgpu_reset_level", 0600, root, &adev->amdgpu_reset_level_mask);
		1958
1789	/* Register debugfs entries for amdgpu_ttm */	1959	/* Register debugfs entries for amdgpu_ttm */
1790	amdgpu_ttm_debugfs_init(adev);	1960	amdgpu_ttm_debugfs_init(adev);
1791	amdgpu_debugfs_pm_init(adev);	1961	amdgpu_debugfs_pm_init(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+100−22

 	 */
 	if (adev->gmc.xgmi.num_physical_nodes > 1) {
 		if (amdgpu_xgmi_add_device(adev) == 0) {
-			struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
+			if (!amdgpu_sriov_vf(adev)) {
+				struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
-			if (!hive->reset_domain ||
+				if (!hive->reset_domain ||
-			    !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
+				    !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
-				r = -ENOENT;
+					r = -ENOENT;
+					amdgpu_put_xgmi_hive(hive);
+					goto init_failed;
+				}
+				/* Drop the early temporary reset domain we created for device */
+				amdgpu_reset_put_reset_domain(adev->reset_domain);
+				adev->reset_domain = hive->reset_domain;
 				amdgpu_put_xgmi_hive(hive);
-				goto init_failed;
 			}
-			/* Drop the early temporary reset domain we created for device */
-			amdgpu_reset_put_reset_domain(adev->reset_domain);
-			adev->reset_domain = hive->reset_domain;
-			amdgpu_put_xgmi_hive(hive);
 		}
 	}
 	adev->gmc.gart_size = 512 * 1024 * 1024;
 	adev->accel_working = false;
 	adev->num_rings = 0;
+	RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
 	adev->mman.buffer_funcs = NULL;
 	adev->mman.buffer_funcs_ring = NULL;
 	adev->vm_manager.vm_pte_funcs = NULL;
 	INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
 	adev->gfx.gfx_off_req_count = 1;
+	adev->gfx.gfx_off_residency = 0;
+	adev->gfx.gfx_off_entrycount = 0;
 	adev->pm.ac_power = power_supply_is_system_supplied() > 0;
 	atomic_set(&adev->throttling_logging_enabled, 1);
 	amdgpu_gart_dummy_page_fini(adev);
-	if (drm_dev_is_unplugged(adev_to_drm(adev)))
+	amdgpu_device_unmap_mmio(adev);
-		amdgpu_device_unmap_mmio(adev);
 }
 	release_firmware(adev->firmware.gpu_info_fw);
 	adev->firmware.gpu_info_fw = NULL;
 	adev->accel_working = false;
+	dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
 	amdgpu_reset_fini(adev);
  */
 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
 {
-	if (!amdgpu_device_ip_check_soft_reset(adev)) {
-		dev_info(adev->dev, "Timeout, but no hardware hang detected.\n");
-		return false;
-	}
 	if (amdgpu_gpu_recovery == 0)
 		goto disabled;
+	if (!amdgpu_device_ip_check_soft_reset(adev)) {
+		dev_info(adev->dev,"Timeout, but no hardware hang detected.\n");
+		return false;
+	}
 	if (amdgpu_sriov_vf(adev))
 		return true;
 		if (!need_full_reset)
 			need_full_reset = amdgpu_device_ip_need_full_reset(adev);
-		if (!need_full_reset) {
+		if (!need_full_reset && amdgpu_gpu_recovery) {
 			amdgpu_device_ip_pre_soft_reset(adev);
 			r = amdgpu_device_ip_soft_reset(adev);
 			amdgpu_device_ip_post_soft_reset(adev);
 	struct amdgpu_device *tmp_adev = NULL;
 	bool need_full_reset, skip_hw_reset, vram_lost = false;
 	int r = 0;
+	bool gpu_reset_for_dev_remove = 0;
 	/* Try reset handler method first */
 	tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
 		test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
 	skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
+	gpu_reset_for_dev_remove =
+		test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
+			test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
 	/*
 	 * ASIC reset has to be done on all XGMI hive nodes ASAP
 	 * to allow proper links negotiation in FW (within 1 sec)
 		amdgpu_ras_intr_cleared();
 	}
+	/* Since the mode1 reset affects base ip blocks, the
+	 * phase1 ip blocks need to be resumed. Otherwise there
+	 * will be a BIOS signature error and the psp bootloader
+	 * can't load kdb on the next amdgpu install.
+	 */
+	if (gpu_reset_for_dev_remove) {
+		list_for_each_entry(tmp_adev, device_list_handle, reset_list)
+			amdgpu_device_ip_resume_phase1(tmp_adev);
+		goto end;
+	}
 	list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
 		if (need_full_reset) {
 			/* post card */
 			/* set guilty */
 			drm_sched_increase_karma(s_job);
+			amdgpu_reset_prepare_hwcontext(adev, reset_context);
 retry:
 			/* do hw reset */
 			if (amdgpu_sriov_vf(adev)) {
 	bool need_emergency_restart = false;
 	bool audio_suspended = false;
 	int tmp_vram_lost_counter;
+	bool gpu_reset_for_dev_remove = false;
+	gpu_reset_for_dev_remove =
+			test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
+				test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
 	/*
 	 * Special case: RAS triggered and full reset isn't supported
 	reset_context->job = job;
 	reset_context->hive = hive;
 	/*
 	 * Build list of devices to reset.
 	 * In case we are in XGMI hive mode, resort the device list
 	 */
 	INIT_LIST_HEAD(&device_list);
 	if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
-		list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head)
+		list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 			list_add_tail(&tmp_adev->reset_list, &device_list);
+			if (gpu_reset_for_dev_remove && adev->shutdown)
+				tmp_adev->shutdown = true;
+		}
 		if (!list_is_first(&adev->reset_list, &device_list))
 			list_rotate_to_front(&adev->reset_list, &device_list);
 		device_list_handle = &device_list;
 retry:	/* Rest of adevs pre asic reset from XGMI hive. */
 	list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
+		if (gpu_reset_for_dev_remove) {
+			/* Workaroud for ASICs need to disable SMC first */
+			amdgpu_device_smu_fini_early(tmp_adev);
+		}
 		r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
 		/*TODO Should we stop ?*/
 		if (r) {
 			amdgpu_ras_resume(adev);
 	} else {
 		r = amdgpu_do_asic_reset(device_list_handle, reset_context);
-		if (r && r == -EAGAIN)
+		if (r && r == -EAGAIN) {
+			set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags);
+			adev->asic_reset_res = 0;
 			goto retry;
+		}
+		if (!r && gpu_reset_for_dev_remove)
+			goto recover_end;
 	}
 skip_hw_reset:
 		amdgpu_device_unset_mp1_state(tmp_adev);
 	}
+recover_end:
 	tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
 					    reset_list);
 	amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
 		~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
 	resource_size_t aper_limit =
 		adev->gmc.aper_base + adev->gmc.aper_size - 1;
-	bool p2p_access = !adev->gmc.xgmi.connected_to_cpu &&
+	bool p2p_access =
-			  !(pci_p2pdma_distance_many(adev->pdev,
+		!adev->gmc.xgmi.connected_to_cpu &&
-					&peer_adev->dev, 1, true) < 0);
+		!(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
 	return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
 		adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
 	reset_context.reset_req_dev = adev;
 	set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
 	set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
+	set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
 	adev->no_hw_access = true;
 	r = amdgpu_device_pre_asic_reset(adev, &reset_context);
 	(void)RREG32(data);
 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 }
+/**
+ * amdgpu_device_switch_gang - switch to a new gang
+ * @adev: amdgpu_device pointer
+ * @gang: the gang to switch to
+ *
+ * Try to switch to a new gang.
+ * Returns: NULL if we switched to the new gang or a reference to the current
+ * gang leader.
+ */
+struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
+					    struct dma_fence *gang)
+{
+	struct dma_fence *old = NULL;
+	do {
+		dma_fence_put(old);
+		rcu_read_lock();
+		old = dma_fence_get_rcu_safe(&adev->gang_submit);
+		rcu_read_unlock();
+		if (old == gang)
+			break;
+		if (!dma_fence_is_signaled(old))
+			return old;
+	} while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
+			 old, gang) != old);
+	dma_fence_put(old);
+	return NULL;
+}

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+16−3

 		return r;
 	}
-	memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
+	memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
 	release_firmware(fw);
 	return 0;
 	case IP_VERSION(11, 0, 0):
 	case IP_VERSION(11, 0, 1):
 	case IP_VERSION(11, 0, 2):
+	case IP_VERSION(11, 0, 3):
 		amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
 		break;
 	default:
 	case IP_VERSION(11, 0, 0):
 	case IP_VERSION(11, 0, 1):
 	case IP_VERSION(11, 0, 2):
+	case IP_VERSION(11, 0, 3):
 		amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
 		break;
 	default:
 	case IP_VERSION(13, 0, 5):
 	case IP_VERSION(13, 0, 7):
 	case IP_VERSION(13, 0, 8):
+	case IP_VERSION(13, 0, 10):
 		amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
 		break;
 	case IP_VERSION(13, 0, 4):
 	case IP_VERSION(13, 0, 5):
 	case IP_VERSION(13, 0, 7):
 	case IP_VERSION(13, 0, 8):
+	case IP_VERSION(13, 0, 10):
 		amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
 		break;
 	default:
 	case IP_VERSION(11, 0, 0):
 	case IP_VERSION(11, 0, 1):
 	case IP_VERSION(11, 0, 2):
+	case IP_VERSION(11, 0, 3):
 		amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
 		break;
 	default:
 	case IP_VERSION(6, 0, 0):
 	case IP_VERSION(6, 0, 1):
 	case IP_VERSION(6, 0, 2):
+	case IP_VERSION(6, 0, 3):
 		amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
 		break;
 	default:
 		case IP_VERSION(4, 0, 2):
 		case IP_VERSION(4, 0, 4):
 			amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
-			amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
+			if (!amdgpu_sriov_vf(adev))
+				amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
 			break;
 		default:
 			dev_err(adev->dev,
 	case IP_VERSION(11, 0, 0):
 	case IP_VERSION(11, 0, 1):
 	case IP_VERSION(11, 0, 2):
+	case IP_VERSION(11, 0, 3):
 		amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
 		adev->enable_mes = true;
 		adev->enable_mes_kiq = true;
 		break;
 	case IP_VERSION(11, 0, 0):
 	case IP_VERSION(11, 0, 2):
+	case IP_VERSION(11, 0, 3):
 		adev->family = AMDGPU_FAMILY_GC_11_0_0;
 		break;
 	case IP_VERSION(11, 0, 1):
 		break;
 	case IP_VERSION(4, 3, 0):
 	case IP_VERSION(4, 3, 1):
-		adev->nbio.funcs = &nbio_v4_3_funcs;
+		if (amdgpu_sriov_vf(adev))
+			adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
+		else
+			adev->nbio.funcs = &nbio_v4_3_funcs;
 		adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
 		break;
 	case IP_VERSION(7, 7, 0):
 	case IP_VERSION(6, 0, 0):
 	case IP_VERSION(6, 0, 1):
 	case IP_VERSION(6, 0, 2):
+	case IP_VERSION(6, 0, 3):
 		adev->lsdma.funcs = &lsdma_v6_0_funcs;
 		break;
 	default:

drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c+1−1

@@ -58,7 +58,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, · 57 unmodified lines
58	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);	58	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
59	int r;	59	int r;
60		60
61	if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0)	61	if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
62	attach->peer2peer = false;	62	attach->peer2peer = false;
63		63
64	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);	64	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+39−4

@@ -102,9 +102,10 @@ · 101 unmodified lines
102	* - 3.46.0 - To enable hot plug amdgpu tests in libdrm	102	* - 3.46.0 - To enable hot plug amdgpu tests in libdrm
103	* - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags	103	* - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
104	* - 3.48.0 - Add IP discovery version info to HW INFO	104	* - 3.48.0 - Add IP discovery version info to HW INFO
		105	* 3.49.0 - Add gang submit into CS IOCTL
105	*/	106	*/
106	#define KMS_DRIVER_MAJOR 3	107	#define KMS_DRIVER_MAJOR 3
107	#define KMS_DRIVER_MINOR 48	108	#define KMS_DRIVER_MINOR 49
108	#define KMS_DRIVER_PATCHLEVEL 0	109	#define KMS_DRIVER_PATCHLEVEL 0
109		110
110	int amdgpu_vram_limit;	111	int amdgpu_vram_limit;
@@ -2181,15 +2182,46 @@ amdgpu_pci_remove(struct pci_dev *pdev) · 2070 unmodified lines
2181	struct drm_device *dev = pci_get_drvdata(pdev);	2182	struct drm_device *dev = pci_get_drvdata(pdev);
2182	struct amdgpu_device *adev = drm_to_adev(dev);	2183	struct amdgpu_device *adev = drm_to_adev(dev);
2183		2184
2184	drm_dev_unplug(dev);
2185
2186	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {	2185	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2187	pm_runtime_get_sync(dev->dev);	2186	pm_runtime_get_sync(dev->dev);
2188	pm_runtime_forbid(dev->dev);	2187	pm_runtime_forbid(dev->dev);
2189	}	2188	}
2190		2189
		2190	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
		2191	bool need_to_reset_gpu = false;
		2192
		2193	if (adev->gmc.xgmi.num_physical_nodes > 1) {
		2194	struct amdgpu_hive_info *hive;
		2195
		2196	hive = amdgpu_get_xgmi_hive(adev);
		2197	if (hive->device_remove_count == 0)
		2198	need_to_reset_gpu = true;
		2199	hive->device_remove_count++;
		2200	amdgpu_put_xgmi_hive(hive);
		2201	} else {
		2202	need_to_reset_gpu = true;
		2203	}
		2204
		2205	/* Workaround for ASICs need to reset SMU.
		2206	* Called only when the first device is removed.
		2207	*/
		2208	if (need_to_reset_gpu) {
		2209	struct amdgpu_reset_context reset_context;
		2210
		2211	adev->shutdown = true;
		2212	memset(&reset_context, 0, sizeof(reset_context));
		2213	reset_context.method = AMD_RESET_METHOD_NONE;
		2214	reset_context.reset_req_dev = adev;
		2215	set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
		2216	set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags);
		2217	amdgpu_device_gpu_recover(adev, NULL, &reset_context);
		2218	}
		2219	}
		2220
2191	amdgpu_driver_unload_kms(dev);	2221	amdgpu_driver_unload_kms(dev);
2192		2222
		2223	drm_dev_unplug(dev);
		2224
2193	/*	2225	/*
2194	* Flush any in flight DMA operations from device.	2226	* Flush any in flight DMA operations from device.
2195	* Clear the Bus Master Enable bit and then wait on the PCIe Device	2227	* Clear the Bus Master Enable bit and then wait on the PCIe Device
@@ -2563,8 +2595,11 @@ static int amdgpu_pmops_runtime_resume(struct device *dev) · 367 unmodified lines
2563	amdgpu_device_baco_exit(drm_dev);	2595	amdgpu_device_baco_exit(drm_dev);
2564	}	2596	}
2565	ret = amdgpu_device_resume(drm_dev, false);	2597	ret = amdgpu_device_resume(drm_dev, false);
2566	if (ret)	2598	if (ret) {
		2599	if (amdgpu_device_supports_px(drm_dev))
		2600	pci_disable_device(pdev);
2567	return ret;	2601	return ret;
		2602	}
2568		2603
2569	if (amdgpu_device_supports_px(drm_dev))	2604	if (amdgpu_device_supports_px(drm_dev))
2570	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;	2605	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c+180−1

@@ -23,6 +23,7 @@ · 22 unmodified lines
23	*	23	*
24	*/	24	*/
25		25
		26	#include <linux/firmware.h>
26	#include "amdgpu.h"	27	#include "amdgpu.h"
27	#include "amdgpu_gfx.h"	28	#include "amdgpu_gfx.h"
28	#include "amdgpu_rlc.h"	29	#include "amdgpu_rlc.h"
@@ -477,7 +478,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev) · 448 unmodified lines
477	kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],	478	kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
478	RESET_QUEUES, 0, 0);	479	RESET_QUEUES, 0, 0);
479		480
480	if (adev->gfx.kiq.ring.sched.ready)	481	if (adev->gfx.kiq.ring.sched.ready && !adev->job_hang)
481	r = amdgpu_ring_test_helper(kiq_ring);	482	r = amdgpu_ring_test_helper(kiq_ring);
482	spin_unlock(&adev->gfx.kiq.ring_lock);	483	spin_unlock(&adev->gfx.kiq.ring_lock);
483		484
@@ -610,6 +611,45 @@ unlock: · 126 unmodified lines
610	mutex_unlock(&adev->gfx.gfx_off_mutex);	611	mutex_unlock(&adev->gfx.gfx_off_mutex);
611	}	612	}
612		613
		614	int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
		615	{
		616	int r = 0;
		617
		618	mutex_lock(&adev->gfx.gfx_off_mutex);
		619
		620	r = amdgpu_dpm_set_residency_gfxoff(adev, value);
		621
		622	mutex_unlock(&adev->gfx.gfx_off_mutex);
		623
		624	return r;
		625	}
		626
		627	int amdgpu_get_gfx_off_residency(struct amdgpu_device adev, u32 value)
		628	{
		629	int r = 0;
		630
		631	mutex_lock(&adev->gfx.gfx_off_mutex);
		632
		633	r = amdgpu_dpm_get_residency_gfxoff(adev, value);
		634
		635	mutex_unlock(&adev->gfx.gfx_off_mutex);
		636
		637	return r;
		638	}
		639
		640	int amdgpu_get_gfx_off_entrycount(struct amdgpu_device adev, u64 value)
		641	{
		642	int r = 0;
		643
		644	mutex_lock(&adev->gfx.gfx_off_mutex);
		645
		646	r = amdgpu_dpm_get_entrycount_gfxoff(adev, value);
		647
		648	mutex_unlock(&adev->gfx.gfx_off_mutex);
		649
		650	return r;
		651	}
		652
613	int amdgpu_get_gfx_off_status(struct amdgpu_device adev, uint32_t value)	653	int amdgpu_get_gfx_off_status(struct amdgpu_device adev, uint32_t value)
614	{	654	{
615		655
@@ -826,3 +866,142 @@ int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev) · 210 unmodified lines
826	}	866	}
827	return amdgpu_num_kcq;	867	return amdgpu_num_kcq;
828	}	868	}
		869
		870	void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
		871	uint32_t ucode_id)
		872	{
		873	const struct gfx_firmware_header_v1_0 *cp_hdr;
		874	const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
		875	struct amdgpu_firmware_info *info = NULL;
		876	const struct firmware *ucode_fw;
		877	unsigned int fw_size;
		878
		879	switch (ucode_id) {
		880	case AMDGPU_UCODE_ID_CP_PFP:
		881	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
		882	adev->gfx.pfp_fw->data;
		883	adev->gfx.pfp_fw_version =
		884	le32_to_cpu(cp_hdr->header.ucode_version);
		885	adev->gfx.pfp_feature_version =
		886	le32_to_cpu(cp_hdr->ucode_feature_version);
		887	ucode_fw = adev->gfx.pfp_fw;
		888	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
		889	break;
		890	case AMDGPU_UCODE_ID_CP_RS64_PFP:
		891	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
		892	adev->gfx.pfp_fw->data;
		893	adev->gfx.pfp_fw_version =
		894	le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
		895	adev->gfx.pfp_feature_version =
		896	le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
		897	ucode_fw = adev->gfx.pfp_fw;
		898	fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
		899	break;
		900	case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
		901	case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
		902	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
		903	adev->gfx.pfp_fw->data;
		904	ucode_fw = adev->gfx.pfp_fw;
		905	fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
		906	break;
		907	case AMDGPU_UCODE_ID_CP_ME:
		908	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
		909	adev->gfx.me_fw->data;
		910	adev->gfx.me_fw_version =
		911	le32_to_cpu(cp_hdr->header.ucode_version);
		912	adev->gfx.me_feature_version =
		913	le32_to_cpu(cp_hdr->ucode_feature_version);
		914	ucode_fw = adev->gfx.me_fw;
		915	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
		916	break;
		917	case AMDGPU_UCODE_ID_CP_RS64_ME:
		918	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
		919	adev->gfx.me_fw->data;
		920	adev->gfx.me_fw_version =
		921	le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
		922	adev->gfx.me_feature_version =
		923	le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
		924	ucode_fw = adev->gfx.me_fw;
		925	fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
		926	break;
		927	case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
		928	case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
		929	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
		930	adev->gfx.me_fw->data;
		931	ucode_fw = adev->gfx.me_fw;
		932	fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
		933	break;
		934	case AMDGPU_UCODE_ID_CP_CE:
		935	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
		936	adev->gfx.ce_fw->data;
		937	adev->gfx.ce_fw_version =
		938	le32_to_cpu(cp_hdr->header.ucode_version);
		939	adev->gfx.ce_feature_version =
		940	le32_to_cpu(cp_hdr->ucode_feature_version);
		941	ucode_fw = adev->gfx.ce_fw;
		942	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
		943	break;
		944	case AMDGPU_UCODE_ID_CP_MEC1:
		945	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
		946	adev->gfx.mec_fw->data;
		947	adev->gfx.mec_fw_version =
		948	le32_to_cpu(cp_hdr->header.ucode_version);
		949	adev->gfx.mec_feature_version =
		950	le32_to_cpu(cp_hdr->ucode_feature_version);
		951	ucode_fw = adev->gfx.mec_fw;
		952	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
		953	le32_to_cpu(cp_hdr->jt_size) * 4;
		954	break;
		955	case AMDGPU_UCODE_ID_CP_MEC1_JT:
		956	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
		957	adev->gfx.mec_fw->data;
		958	ucode_fw = adev->gfx.mec_fw;
		959	fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
		960	break;
		961	case AMDGPU_UCODE_ID_CP_MEC2:
		962	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
		963	adev->gfx.mec2_fw->data;
		964	adev->gfx.mec2_fw_version =
		965	le32_to_cpu(cp_hdr->header.ucode_version);
		966	adev->gfx.mec2_feature_version =
		967	le32_to_cpu(cp_hdr->ucode_feature_version);
		968	ucode_fw = adev->gfx.mec2_fw;
		969	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
		970	le32_to_cpu(cp_hdr->jt_size) * 4;
		971	break;
		972	case AMDGPU_UCODE_ID_CP_MEC2_JT:
		973	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
		974	adev->gfx.mec2_fw->data;
		975	ucode_fw = adev->gfx.mec2_fw;
		976	fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
		977	break;
		978	case AMDGPU_UCODE_ID_CP_RS64_MEC:
		979	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
		980	adev->gfx.mec_fw->data;
		981	adev->gfx.mec_fw_version =
		982	le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
		983	adev->gfx.mec_feature_version =
		984	le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
		985	ucode_fw = adev->gfx.mec_fw;
		986	fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
		987	break;
		988	case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
		989	case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
		990	case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
		991	case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
		992	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
		993	adev->gfx.mec_fw->data;
		994	ucode_fw = adev->gfx.mec_fw;
		995	fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
		996	break;
		997	default:
		998	break;
		999	}
		1000
		1001	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
		1002	info = &adev->firmware.ucode[ucode_id];
		1003	info->ucode_id = ucode_id;
		1004	info->fw = ucode_fw;
		1005	adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
		1006	}
		1007	}

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h+12−4

 	uint32_t                        srbm_soft_reset;
 	/* gfx off */
-	bool                            gfx_off_state; /* true: enabled, false: disabled */
+	bool                            gfx_off_state;      /* true: enabled, false: disabled */
-	struct mutex                    gfx_off_mutex;
+	struct mutex                    gfx_off_mutex;      /* mutex to change gfxoff state */
-	uint32_t                        gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
+	uint32_t                        gfx_off_req_count;  /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
-	struct delayed_work             gfx_off_delay_work;
+	struct delayed_work             gfx_off_delay_work; /* async work to set gfx block off */
+	uint32_t                        gfx_off_residency;  /* last logged residency */
+	uint64_t                        gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */
 	/* pipe reservation */
 	struct mutex			pipe_reserve_mutex;
 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
+void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
+int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);
+int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);
+int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 		void *err_data,
 		struct amdgpu_iv_entry *entry);
 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
+void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
 #endif

drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h+3−0

 	void (*init)(struct amdgpu_device *adev);
 	int (*get_xgmi_info)(struct amdgpu_device *adev);
 	void (*utcl2_harvest)(struct amdgpu_device *adev);
+	void (*mode2_save_regs)(struct amdgpu_device *adev);
+	void (*mode2_restore_regs)(struct amdgpu_device *adev);
+	void (*halt)(struct amdgpu_device *adev);
 };
 struct amdgpu_gfxhub {

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c+9−39

@@ -572,45 +572,15 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) · 571 unmodified lines
572	void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)	572	void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)
573	{	573	{
574	struct amdgpu_gmc *gmc = &adev->gmc;	574	struct amdgpu_gmc *gmc = &adev->gmc;
575		575	uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
576	switch (adev->ip_versions[GC_HWIP][0]) {	576	bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) \|\|
577	case IP_VERSION(9, 0, 1):	577	gc_ver == IP_VERSION(9, 3, 0) \|\|
578	case IP_VERSION(9, 3, 0):	578	gc_ver == IP_VERSION(9, 4, 0) \|\|
579	case IP_VERSION(9, 4, 0):	579	gc_ver == IP_VERSION(9, 4, 1) \|\|
580	case IP_VERSION(9, 4, 1):	580	gc_ver == IP_VERSION(9, 4, 2) \|\|
581	case IP_VERSION(9, 4, 2):	581	gc_ver >= IP_VERSION(10, 3, 0));
582	case IP_VERSION(10, 3, 3):	582
583	case IP_VERSION(10, 3, 4):	583	gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry;
584	case IP_VERSION(10, 3, 5):
585	case IP_VERSION(10, 3, 6):
586	case IP_VERSION(10, 3, 7):
587	/*
588	* noretry = 0 will cause kfd page fault tests fail
589	* for some ASICs, so set default to 1 for these ASICs.
590	*/
591	if (amdgpu_noretry == -1)
592	gmc->noretry = 1;
593	else
594	gmc->noretry = amdgpu_noretry;
595	break;
596	default:
597	/* Raven currently has issues with noretry
598	* regardless of what we decide for other
599	* asics, we should leave raven with
600	* noretry = 0 until we root cause the
601	* issues.
602	*
603	* default this to 0 for now, but we may want
604	* to change this in the future for certain
605	* GPUs as it can increase performance in
606	* certain cases.
607	*/
608	if (amdgpu_noretry == -1)
609	gmc->noretry = 0;
610	else
611	gmc->noretry = amdgpu_noretry;
612	break;
613	}
614	}	584	}
615		585
616	void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,	586	void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h+26−0

@@ -264,6 +264,32 @@ struct amdgpu_gmc { · 263 unmodified lines
264	u64 mall_size;	264	u64 mall_size;
265	/* number of UMC instances */	265	/* number of UMC instances */
266	int num_umc;	266	int num_umc;
		267	/* mode2 save restore */
		268	u64 VM_L2_CNTL;
		269	u64 VM_L2_CNTL2;
		270	u64 VM_DUMMY_PAGE_FAULT_CNTL;
		271	u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32;
		272	u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32;
		273	u64 VM_L2_PROTECTION_FAULT_CNTL;
		274	u64 VM_L2_PROTECTION_FAULT_CNTL2;
		275	u64 VM_L2_PROTECTION_FAULT_MM_CNTL3;
		276	u64 VM_L2_PROTECTION_FAULT_MM_CNTL4;
		277	u64 VM_L2_PROTECTION_FAULT_ADDR_LO32;
		278	u64 VM_L2_PROTECTION_FAULT_ADDR_HI32;
		279	u64 VM_DEBUG;
		280	u64 VM_L2_MM_GROUP_RT_CLASSES;
		281	u64 VM_L2_BANK_SELECT_RESERVED_CID;
		282	u64 VM_L2_BANK_SELECT_RESERVED_CID2;
		283	u64 VM_L2_CACHE_PARITY_CNTL;
		284	u64 VM_L2_IH_LOG_CNTL;
		285	u64 VM_CONTEXT_CNTL[16];
		286	u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16];
		287	u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16];
		288	u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16];
		289	u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16];
		290	u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16];
		291	u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16];
		292	u64 MC_VM_MX_L1_TLB_CNTL;
267	};	293	};
268		294
269	#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))	295	#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))

drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c+38−0

@@ -204,6 +204,42 @@ void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr) · 203 unmodified lines
204	amdgpu_gart_invalidate_tlb(adev);	204	amdgpu_gart_invalidate_tlb(adev);
205	}	205	}
206		206
		207	/**
		208	* amdgpu_gtt_mgr_intersects - test for intersection
		209	*
		210	* @man: Our manager object
		211	* @res: The resource to test
		212	* @place: The place for the new allocation
		213	* @size: The size of the new allocation
		214	*
		215	* Simplified intersection test, only interesting if we need GART or not.
		216	*/
		217	static bool amdgpu_gtt_mgr_intersects(struct ttm_resource_manager *man,
		218	struct ttm_resource *res,
		219	const struct ttm_place *place,
		220	size_t size)
		221	{
		222	return !place->lpfn \|\| amdgpu_gtt_mgr_has_gart_addr(res);
		223	}
		224
		225	/**
		226	* amdgpu_gtt_mgr_compatible - test for compatibility
		227	*
		228	* @man: Our manager object
		229	* @res: The resource to test
		230	* @place: The place for the new allocation
		231	* @size: The size of the new allocation
		232	*
		233	* Simplified compatibility test.
		234	*/
		235	static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man,
		236	struct ttm_resource *res,
		237	const struct ttm_place *place,
		238	size_t size)
		239	{
		240	return !place->lpfn \|\| amdgpu_gtt_mgr_has_gart_addr(res);
		241	}
		242
207	/**	243	/**
208	* amdgpu_gtt_mgr_debug - dump VRAM table	244	* amdgpu_gtt_mgr_debug - dump VRAM table
209	*	245	*
@@ -225,6 +261,8 @@ static void amdgpu_gtt_mgr_debug(struct ttm_resource_manager *man, · 15 unmodified lines
225	static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func = {	261	static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func = {
226	.alloc = amdgpu_gtt_mgr_new,	262	.alloc = amdgpu_gtt_mgr_new,
227	.free = amdgpu_gtt_mgr_del,	263	.free = amdgpu_gtt_mgr_del,
		264	.intersects = amdgpu_gtt_mgr_intersects,
		265	.compatible = amdgpu_gtt_mgr_compatible,
228	.debug = amdgpu_gtt_mgr_debug	266	.debug = amdgpu_gtt_mgr_debug
229	};	267	};
230		268

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c+47−3

 	}
 	memset(&ti, 0, sizeof(struct amdgpu_task_info));
+	adev->job_hang = true;
 	if (amdgpu_gpu_recovery &&
 	    amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
 		reset_context.method = AMD_RESET_METHOD_NONE;
 		reset_context.reset_req_dev = adev;
 		clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
+		clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
 		r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context);
 		if (r)
 	}
 exit:
+	adev->job_hang = false;
 	drm_dev_exit(idx);
 	return DRM_GPU_SCHED_STAT_NOMINAL;
 }
 	 */
 	(*job)->base.sched = &adev->rings[0]->sched;
 	(*job)->vm = vm;
-	(*job)->num_ibs = num_ibs;
 	amdgpu_sync_create(&(*job)->sync);
 	amdgpu_sync_create(&(*job)->sched_sync);
 	if (r)
 		return r;
+	(*job)->num_ibs = 1;
 	r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
 	if (r)
 		kfree(*job);
 	return r;
 }
+void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
+			      struct amdgpu_bo *gws, struct amdgpu_bo *oa)
+{
+	if (gds) {
+		job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
+		job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
+	}
+	if (gws) {
+		job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
+		job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
+	}
+	if (oa) {
+		job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
+		job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
+	}
+}
 void amdgpu_job_free_resources(struct amdgpu_job *job)
 {
 	struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
 	dma_fence_put(&job->hw_fence);
 }
+void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
+				struct amdgpu_job *leader)
+{
+	struct dma_fence *fence = &leader->base.s_fence->scheduled;
+	WARN_ON(job->gang_submit);
+	/*
+	 * Don't add a reference when we are the gang leader to avoid circle
+	 * dependency.
+	 */
+	if (job != leader)
+		dma_fence_get(fence);
+	job->gang_submit = fence;
+}
 void amdgpu_job_free(struct amdgpu_job *job)
 {
 	amdgpu_job_free_resources(job);
 	amdgpu_sync_free(&job->sync);
 	amdgpu_sync_free(&job->sched_sync);
+	if (job->gang_submit != &job->base.s_fence->scheduled)
+		dma_fence_put(job->gang_submit);
 	if (!job->hw_fence.ops)
 		kfree(job);
 		fence = amdgpu_sync_get_fence(&job->sync);
 	}
+	if (!fence && job->gang_submit)
+		fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
 	return fence;
 }
 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
 {
 	struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
+	struct amdgpu_device *adev = ring->adev;
 	struct dma_fence *fence = NULL, *finished;
 	struct amdgpu_job *job;
 	int r = 0;
 	trace_amdgpu_sched_run_job(job);
-	if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter))
+	/* Skip job if VRAM is lost and never resubmit gangs */
-		dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
+	if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter) ||
+	    (job->job_run_counter && job->gang_submit))
+		dma_fence_set_error(finished, -ECANCELED);
 	if (finished->error < 0) {
 		DRM_INFO("Skip scheduling IBs!\n");

drivers/gpu/drm/amd/amdgpu/amdgpu_job.h+10−0

 	struct amdgpu_sync	sync;
 	struct amdgpu_sync	sched_sync;
 	struct dma_fence	hw_fence;
+	struct dma_fence	*gang_submit;
 	uint32_t		preamble_status;
 	uint32_t                preemption_status;
 	bool                    vm_needs_flush;
 	struct amdgpu_ib	ibs[];
 };
+static inline struct amdgpu_ring *amdgpu_job_ring(struct amdgpu_job *job)
+{
+	return to_amdgpu_ring(job->base.entity->rq->sched);
+}
 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
 		     struct amdgpu_job **job, struct amdgpu_vm *vm);
 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
 		enum amdgpu_ib_pool_type pool, struct amdgpu_job **job);
+void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
+			      struct amdgpu_bo *gws, struct amdgpu_bo *oa);
 void amdgpu_job_free_resources(struct amdgpu_job *job);
+void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
+				struct amdgpu_job *leader);
 void amdgpu_job_free(struct amdgpu_job *job);
 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
 		      void *owner, struct dma_fence **f);

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+49−1

@@ -247,6 +247,14 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, · 246 unmodified lines
247	fw_info->ver = adev->gfx.rlc_srls_fw_version;	247	fw_info->ver = adev->gfx.rlc_srls_fw_version;
248	fw_info->feature = adev->gfx.rlc_srls_feature_version;	248	fw_info->feature = adev->gfx.rlc_srls_feature_version;
249	break;	249	break;
		250	case AMDGPU_INFO_FW_GFX_RLCP:
		251	fw_info->ver = adev->gfx.rlcp_ucode_version;
		252	fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
		253	break;
		254	case AMDGPU_INFO_FW_GFX_RLCV:
		255	fw_info->ver = adev->gfx.rlcv_ucode_version;
		256	fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
		257	break;
250	case AMDGPU_INFO_FW_GFX_MEC:	258	case AMDGPU_INFO_FW_GFX_MEC:
251	if (query_fw->index == 0) {	259	if (query_fw->index == 0) {
252	fw_info->ver = adev->gfx.mec_fw_version;	260	fw_info->ver = adev->gfx.mec_fw_version;
@@ -328,6 +336,14 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, · 75 unmodified lines
328	fw_info->ver = adev->psp.cap_fw_version;	336	fw_info->ver = adev->psp.cap_fw_version;
329	fw_info->feature = adev->psp.cap_feature_version;	337	fw_info->feature = adev->psp.cap_feature_version;
330	break;	338	break;
		339	case AMDGPU_INFO_FW_MES_KIQ:
		340	fw_info->ver = adev->mes.ucode_fw_version[0];
		341	fw_info->feature = 0;
		342	break;
		343	case AMDGPU_INFO_FW_MES:
		344	fw_info->ver = adev->mes.ucode_fw_version[1];
		345	fw_info->feature = 0;
		346	break;
331	default:	347	default:
332	return -EINVAL;	348	return -EINVAL;
333	}	349	}
@@ -1160,7 +1176,7 @@ int amdgpu_driver_open_kms(struct drm_device dev, struct drm_file file_priv) · 826 unmodified lines
1160	}	1176	}
1161		1177
1162	mutex_init(&fpriv->bo_list_lock);	1178	mutex_init(&fpriv->bo_list_lock);
1163	idr_init(&fpriv->bo_list_handles);	1179	idr_init_base(&fpriv->bo_list_handles, 1);
1164		1180
1165	amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);	1181	amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1166		1182
@@ -1469,6 +1485,22 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file m, void unused) · 302 unmodified lines
1469	seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",	1485	seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1470	fw_info.feature, fw_info.ver);	1486	fw_info.feature, fw_info.ver);
1471		1487
		1488	/* RLCP */
		1489	query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
		1490	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
		1491	if (ret)
		1492	return ret;
		1493	seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
		1494	fw_info.feature, fw_info.ver);
		1495
		1496	/* RLCV */
		1497	query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
		1498	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
		1499	if (ret)
		1500	return ret;
		1501	seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
		1502	fw_info.feature, fw_info.ver);
		1503
1472	/* MEC */	1504	/* MEC */
1473	query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;	1505	query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1474	query_fw.index = 0;	1506	query_fw.index = 0;
@@ -1581,6 +1613,22 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file m, void unused) · 106 unmodified lines
1581	fw_info.feature, fw_info.ver);	1613	fw_info.feature, fw_info.ver);
1582	}	1614	}
1583		1615
		1616	/* MES_KIQ */
		1617	query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
		1618	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
		1619	if (ret)
		1620	return ret;
		1621	seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
		1622	fw_info.feature, fw_info.ver);
		1623
		1624	/* MES */
		1625	query_fw.fw_type = AMDGPU_INFO_FW_MES;
		1626	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
		1627	if (ret)
		1628	return ret;
		1629	seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
		1630	fw_info.feature, fw_info.ver);
		1631
1584	seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);	1632	seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1585		1633
1586	return 0;	1634	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h+0−1

@@ -38,7 +38,6 @@ · 37 unmodified lines
38	#include <drm/drm_crtc_helper.h>	38	#include <drm/drm_crtc_helper.h>
39	#include <drm/drm_fb_helper.h>	39	#include <drm/drm_fb_helper.h>
40	#include <drm/drm_framebuffer.h>	40	#include <drm/drm_framebuffer.h>
41	#include <drm/drm_plane_helper.h>
42	#include <drm/drm_probe_helper.h>	41	#include <drm/drm_probe_helper.h>
43	#include <linux/i2c.h>	42	#include <linux/i2c.h>
44	#include <linux/i2c-algo-bit.h>	43	#include <linux/i2c-algo-bit.h>

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+2−2

@@ -591,7 +591,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, · 590 unmodified lines
591	if (!bp->destroy)	591	if (!bp->destroy)
592	bp->destroy = &amdgpu_bo_destroy;	592	bp->destroy = &amdgpu_bo_destroy;
593		593
594	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,	594	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type,
595	&bo->placement, page_align, &ctx, NULL,	595	&bo->placement, page_align, &ctx, NULL,
596	bp->resv, bp->destroy);	596	bp->resv, bp->destroy);
597	if (unlikely(r != 0))	597	if (unlikely(r != 0))
@@ -1309,7 +1309,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) · 711 unmodified lines
1309	if (bo->base.resv == &bo->base._resv)	1309	if (bo->base.resv == &bo->base._resv)
1310	amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);	1310	amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1311		1311
1312	if (bo->resource->mem_type != TTM_PL_VRAM \|\|	1312	if (!bo->resource \|\| bo->resource->mem_type != TTM_PL_VRAM \|\|
1313	!(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) \|\|	1313	!(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) \|\|
1314	adev->in_suspend \|\| adev->shutdown)	1314	adev->in_suspend \|\| adev->shutdown)
1315	return;	1315	return;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+35−17

 	case IP_VERSION(13, 0, 3):
 	case IP_VERSION(13, 0, 5):
 	case IP_VERSION(13, 0, 8):
+	case IP_VERSION(13, 0, 10):
 		psp_v13_0_set_psp_funcs(psp);
 		psp->autoload_supported = true;
 		break;
 	switch (adev->ip_versions[MP0_HWIP][0]) {
 	case IP_VERSION(9, 0, 0):
+		adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 		ret = psp_init_cap_microcode(psp, "vega10");
 		break;
 	case IP_VERSION(11, 0, 9):
+		adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 		ret = psp_init_cap_microcode(psp, "navi12");
 		break;
 	case IP_VERSION(11, 0, 7):
+		adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 		ret = psp_init_cap_microcode(psp, "sienna_cichlid");
 		break;
 	case IP_VERSION(13, 0, 2):
+		adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 		ret = psp_init_cap_microcode(psp, "aldebaran");
 		ret &= psp_init_ta_microcode(psp, "aldebaran");
 		break;
+	case IP_VERSION(13, 0, 0):
+		adev->virt.autoload_ucode_id = 0;
+		break;
+	case IP_VERSION(13, 0, 10):
+		adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
+		break;
 	default:
 		BUG();
 		break;
 	}
 	return ret;
 }
 	kfree(cmd);
 	cmd = NULL;
+	if (psp->km_ring.ring_mem)
+		amdgpu_bo_free_kernel(&adev->firmware.rbuf,
+				      &psp->km_ring.ring_mem_mc_addr,
+				      (void **)&psp->km_ring.ring_mem);
 	amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 			      &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 	amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 	case IP_VERSION(11, 0, 9):
 	case IP_VERSION(11, 0, 7):
 	case IP_VERSION(13, 0, 2):
+	case IP_VERSION(13, 0, 10):
 		return true;
 	default:
 		return false;
 	struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 	psp_prep_tmr_unload_cmd_buf(psp, cmd);
-	DRM_INFO("free PSP TMR buffer\n");
+	dev_info(psp->adev->dev, "free PSP TMR buffer\n");
 	ret = psp_cmd_submit_buf(psp, NULL, cmd,
 				 psp->fence_buf_mc_addr);
 			}
 		}
+		if ((is_psp_fw_valid(psp->ras_drv)) &&
+		    (psp->funcs->bootloader_load_ras_drv != NULL)) {
+			ret = psp_bootloader_load_ras_drv(psp);
+			if (ret) {
+				DRM_ERROR("PSP load ras_drv failed!\n");
+				return ret;
+			}
+		}
 		if ((is_psp_fw_valid(psp->sos)) &&
 		    (psp->funcs->bootloader_load_sos != NULL)) {
 			ret = psp_bootloader_load_sos(psp);
 		return true;
 	if (amdgpu_sriov_vf(psp->adev) &&
-	   (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
+	    amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
-	    || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
-		/*skip ucode loading in SRIOV VF */
 		return true;
 	if (psp->autoload_supported &&
 		/* Start rlc autoload after psp recieved all the gfx firmware */
 		if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
-		    AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
+		    adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
 			ret = psp_rlc_autoload_start(psp);
 			if (ret) {
 				DRM_ERROR("Failed to start rlc autoload\n");
 		psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
 		psp->dbg_drv.start_addr         = ucode_start_addr;
 		break;
+	case PSP_FW_TYPE_PSP_RAS_DRV:
+		psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
+		psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
+		psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
+		psp->ras_drv.start_addr         = ucode_start_addr;
+		break;
 	default:
 		dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
 		break;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h+6−0

 	PSP_BL__LOAD_SOCDRV             = 0xB0000,
 	PSP_BL__LOAD_DBGDRV             = 0xC0000,
 	PSP_BL__LOAD_INTFDRV		= 0xD0000,
+	PSP_BL__LOAD_RASDRV		    = 0xE0000,
 	PSP_BL__DRAM_LONG_TRAIN		= 0x100000,
 	PSP_BL__DRAM_SHORT_TRAIN	= 0x200000,
 	PSP_BL__LOAD_TOS_SPL_TABLE	= 0x10000000,
 	int (*bootloader_load_soc_drv)(struct psp_context *psp);
 	int (*bootloader_load_intf_drv)(struct psp_context *psp);
 	int (*bootloader_load_dbg_drv)(struct psp_context *psp);
+	int (*bootloader_load_ras_drv)(struct psp_context *psp);
 	int (*bootloader_load_sos)(struct psp_context *psp);
 	int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
 	int (*ring_create)(struct psp_context *psp,
 	struct psp_bin_desc		soc_drv;
 	struct psp_bin_desc		intf_drv;
 	struct psp_bin_desc		dbg_drv;
+	struct psp_bin_desc		ras_drv;
 	/* tmr buffer */
 	struct amdgpu_bo		*tmr_bo;
 		((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
 #define psp_bootloader_load_dbg_drv(psp) \
 		((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
+#define psp_bootloader_load_ras_drv(psp) \
+		((psp)->funcs->bootloader_load_ras_drv ? \
+		(psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
 #define psp_bootloader_load_sos(psp) \
 		((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
 #define psp_smu_reload_quirk(psp) \

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c+18−17

@@ -1950,6 +1950,7 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) · 1949 unmodified lines
1950	reset_context.method = AMD_RESET_METHOD_NONE;	1950	reset_context.method = AMD_RESET_METHOD_NONE;
1951	reset_context.reset_req_dev = adev;	1951	reset_context.reset_req_dev = adev;
1952	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);	1952	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
		1953	clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
1953		1954
1954	amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);	1955	amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
1955	}	1956	}
@@ -2719,7 +2720,8 @@ int amdgpu_ras_pre_fini(struct amdgpu_device *adev) · 763 unmodified lines
2719		2720
2720		2721
2721	/* Need disable ras on all IPs here before ip [hw/sw]fini */	2722	/* Need disable ras on all IPs here before ip [hw/sw]fini */
2722	amdgpu_ras_disable_all_features(adev, 0);	2723	if (con->features)
		2724	amdgpu_ras_disable_all_features(adev, 0);
2723	amdgpu_ras_recovery_fini(adev);	2725	amdgpu_ras_recovery_fini(adev);
2724	return 0;	2726	return 0;
2725	}	2727	}
@@ -2832,11 +2834,8 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, · 106 unmodified lines
2832	struct mce m = (struct mce )data;	2834	struct mce m = (struct mce )data;
2833	struct amdgpu_device *adev = NULL;	2835	struct amdgpu_device *adev = NULL;
2834	uint32_t gpu_id = 0;	2836	uint32_t gpu_id = 0;
2835	uint32_t umc_inst = 0;	2837	uint32_t umc_inst = 0, ch_inst = 0;
2836	uint32_t ch_inst, channel_index = 0;
2837	struct ras_err_data err_data = {0, 0, 0, NULL};	2838	struct ras_err_data err_data = {0, 0, 0, NULL};
2838	struct eeprom_table_record err_rec;
2839	uint64_t retired_page;
2840		2839
2841	/*	2840	/*
2842	* If the error was generated in UMC_V2, which belongs to GPU UMCs,	2841	* If the error was generated in UMC_V2, which belongs to GPU UMCs,
@@ -2875,21 +2874,22 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, · 32 unmodified lines
2875	dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",	2874	dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
2876	umc_inst, ch_inst);	2875	umc_inst, ch_inst);
2877		2876
		2877	err_data.err_addr =
		2878	kcalloc(adev->umc.max_ras_err_cnt_per_query,
		2879	sizeof(struct eeprom_table_record), GFP_KERNEL);
		2880	if(!err_data.err_addr) {
		2881	dev_warn(adev->dev, "Failed to alloc memory for "
		2882	"umc error address record in mca notifier!\n");
		2883	return NOTIFY_DONE;
		2884	}
		2885
2878	/*	2886	/*
2879	* Translate UMC channel address to Physical address	2887	* Translate UMC channel address to Physical address
2880	*/	2888	*/
2881	channel_index =	2889	if (adev->umc.ras &&
2882	adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num	2890	adev->umc.ras->convert_ras_error_address)
2883	+ ch_inst];	2891	adev->umc.ras->convert_ras_error_address(adev,
2884		2892	&err_data, 0, ch_inst, umc_inst, m->addr);
2885	retired_page = ADDR_OF_8KB_BLOCK(m->addr) \|
2886	ADDR_OF_256B_BLOCK(channel_index) \|
2887	OFFSET_IN_256B_BLOCK(m->addr);
2888
2889	memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
2890	err_data.err_addr = &err_rec;
2891	amdgpu_umc_fill_error_record(&err_data, m->addr,
2892	retired_page, channel_index, umc_inst);
2893		2893
2894	if (amdgpu_bad_page_threshold != 0) {	2894	if (amdgpu_bad_page_threshold != 0) {
2895	amdgpu_ras_add_bad_pages(adev, err_data.err_addr,	2895	amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
@@ -2897,6 +2897,7 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, · 1 unmodified line
2897	amdgpu_ras_save_bad_pages(adev);	2897	amdgpu_ras_save_bad_pages(adev);
2898	}	2898	}
2899		2899
		2900	kfree(err_data.err_addr);
2900	return NOTIFY_OK;	2901	return NOTIFY_OK;
2901	}	2902	}
2902		2903

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c+10−0

 #define EEPROM_I2C_MADDR_ARCTURUS_D342  0x0
 #define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0
 #define EEPROM_I2C_MADDR_ALDEBARAN      0x0
+#define EEPROM_I2C_MADDR_SMU_13_0_0     (0x54UL << 16)
 /*
  * The 2 macros bellow represent the actual size in bytes that
 		return false;
 	}
+	switch (adev->ip_versions[MP1_HWIP][0]) {
+	case IP_VERSION(13, 0, 0):
+		control->i2c_address = EEPROM_I2C_MADDR_SMU_13_0_0;
+		break;
+	default:
+		break;
+	}
 	return true;
 }

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c+21−0

 #include "amdgpu_reset.h"
 #include "aldebaran.h"
+#include "sienna_cichlid.h"
 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
 			     struct amdgpu_reset_handler *handler)
 {
 	int ret = 0;
+	adev->amdgpu_reset_level_mask = 0x1;
 	switch (adev->ip_versions[MP1_HWIP][0]) {
 	case IP_VERSION(13, 0, 2):
 		ret = aldebaran_reset_init(adev);
 		break;
+	case IP_VERSION(11, 0, 7):
+		ret = sienna_cichlid_reset_init(adev);
+		break;
 	default:
 		break;
 	}
 	case IP_VERSION(13, 0, 2):
 		ret = aldebaran_reset_fini(adev);
 		break;
+	case IP_VERSION(11, 0, 7):
+		ret = sienna_cichlid_reset_fini(adev);
+		break;
 	default:
 		break;
 	}
 {
 	struct amdgpu_reset_handler *reset_handler = NULL;
+	if (!(adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
+		return -ENOSYS;
+	if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags))
+		return -ENOSYS;
 	if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
 		reset_handler = adev->reset_cntl->get_reset_handler(
 			adev->reset_cntl, reset_context);
 	int ret;
 	struct amdgpu_reset_handler *reset_handler = NULL;
+	if (!(adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
+		return -ENOSYS;
+	if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags))
+		return -ENOSYS;
 	if (adev->reset_cntl)
 		reset_handler = adev->reset_cntl->get_reset_handler(
 			adev->reset_cntl, reset_context);

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h+4−1

 	AMDGPU_NEED_FULL_RESET = 0,
 	AMDGPU_SKIP_HW_RESET = 1,
+	AMDGPU_SKIP_MODE2_RESET = 2,
+	AMDGPU_RESET_FOR_DEVICE_REMOVE = 3,
 };
 struct amdgpu_reset_context {
 static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain)
 {
-	kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
+	if (domain)
+		kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
 }
 static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c+3−0

@@ -405,6 +405,9 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, · 404 unmodified lines
405	{	405	{
406	ktime_t deadline = ktime_add_us(ktime_get(), 10000);	406	ktime_t deadline = ktime_add_us(ktime_get(), 10000);
407		407
		408	if (!(ring->adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_SOFT_RECOVERY))
		409	return false;
		410
408	if (amdgpu_sriov_vf(ring->adev) \|\| !ring->funcs->soft_recovery \|\| !fence)	411	if (amdgpu_sriov_vf(ring->adev) \|\| !ring->funcs->soft_recovery \|\| !fence)
409	return false;	412	return false;
410		413

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c+8−0

@@ -359,6 +359,14 @@ static void amdgpu_gfx_rlc_init_microcode_v2_1(struct amdgpu_device *adev) · 358 unmodified lines
359	le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);	359	le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
360		360
361	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {	361	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
		362	if (adev->gfx.rlc.save_restore_list_cntl_size_bytes) {
		363	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
		364	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
		365	info->fw = adev->gfx.rlc_fw;
		366	adev->firmware.fw_size +=
		367	ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
		368	}
		369
362	if (adev->gfx.rlc.save_restore_list_gpm_size_bytes) {	370	if (adev->gfx.rlc.save_restore_list_gpm_size_bytes) {
363	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];	371	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
364	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;	372	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;

drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c+133−0

@@ -21,6 +21,7 @@ · 20 unmodified lines
21	*	21	*
22	*/	22	*/
23		23
		24	#include <linux/firmware.h>
24	#include "amdgpu.h"	25	#include "amdgpu.h"
25	#include "amdgpu_sdma.h"	26	#include "amdgpu_sdma.h"
26	#include "amdgpu_ras.h"	27	#include "amdgpu_ras.h"
@@ -150,3 +151,135 @@ int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev, · 123 unmodified lines
150	amdgpu_ras_interrupt_dispatch(adev, &ih_data);	151	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
151	return 0;	152	return 0;
152	}	153	}
		154
		155	static int amdgpu_sdma_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
		156	{
		157	int err = 0;
		158	uint16_t version_major;
		159	const struct common_firmware_header *header = NULL;
		160	const struct sdma_firmware_header_v1_0 *hdr;
		161	const struct sdma_firmware_header_v2_0 *hdr_v2;
		162
		163	err = amdgpu_ucode_validate(sdma_inst->fw);
		164	if (err)
		165	return err;
		166
		167	header = (const struct common_firmware_header *)
		168	sdma_inst->fw->data;
		169	version_major = le16_to_cpu(header->header_version_major);
		170
		171	switch (version_major) {
		172	case 1:
		173	hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
		174	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
		175	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
		176	break;
		177	case 2:
		178	hdr_v2 = (const struct sdma_firmware_header_v2_0 *)sdma_inst->fw->data;
		179	sdma_inst->fw_version = le32_to_cpu(hdr_v2->header.ucode_version);
		180	sdma_inst->feature_version = le32_to_cpu(hdr_v2->ucode_feature_version);
		181	break;
		182	default:
		183	return -EINVAL;
		184	}
		185
		186	if (sdma_inst->feature_version >= 20)
		187	sdma_inst->burst_nop = true;
		188
		189	return 0;
		190	}
		191
		192	void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev,
		193	bool duplicate)
		194	{
		195	int i;
		196
		197	for (i = 0; i < adev->sdma.num_instances; i++) {
		198	release_firmware(adev->sdma.instance[i].fw);
		199	if (duplicate)
		200	break;
		201	}
		202
		203	memset((void *)adev->sdma.instance, 0,
		204	sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
		205	}
		206
		207	int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,
		208	char *fw_name, u32 instance,
		209	bool duplicate)
		210	{
		211	struct amdgpu_firmware_info *info = NULL;
		212	const struct common_firmware_header *header = NULL;
		213	int err = 0, i;
		214	const struct sdma_firmware_header_v2_0 *sdma_hdr;
		215	uint16_t version_major;
		216
		217	err = request_firmware(&adev->sdma.instance[instance].fw, fw_name, adev->dev);
		218	if (err)
		219	goto out;
		220
		221	header = (const struct common_firmware_header *)
		222	adev->sdma.instance[instance].fw->data;
		223	version_major = le16_to_cpu(header->header_version_major);
		224
		225	if ((duplicate && instance) \|\| (!duplicate && version_major > 1))
		226	return -EINVAL;
		227
		228	err = amdgpu_sdma_init_inst_ctx(&adev->sdma.instance[instance]);
		229	if (err)
		230	goto out;
		231
		232	if (duplicate) {
		233	for (i = 1; i < adev->sdma.num_instances; i++)
		234	memcpy((void *)&adev->sdma.instance[i],
		235	(void *)&adev->sdma.instance[0],
		236	sizeof(struct amdgpu_sdma_instance));
		237	}
		238
		239	if (amdgpu_sriov_vf(adev))
		240	return 0;
		241
		242	DRM_DEBUG("psp_load == '%s'\n",
		243	adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
		244
		245	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
		246	switch (version_major) {
		247	case 1:
		248	for (i = 0; i < adev->sdma.num_instances; i++) {
		249	if (!duplicate && (instance != i))
		250	continue;
		251	else {
		252	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
		253	info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
		254	info->fw = adev->sdma.instance[i].fw;
		255	adev->firmware.fw_size +=
		256	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
		257	}
		258	}
		259	break;
		260	case 2:
		261	sdma_hdr = (const struct sdma_firmware_header_v2_0 *)
		262	adev->sdma.instance[0].fw->data;
		263	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH0];
		264	info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH0;
		265	info->fw = adev->sdma.instance[0].fw;
		266	adev->firmware.fw_size +=
		267	ALIGN(le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes), PAGE_SIZE);
		268	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH1];
		269	info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH1;
		270	info->fw = adev->sdma.instance[0].fw;
		271	adev->firmware.fw_size +=
		272	ALIGN(le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes), PAGE_SIZE);
		273	break;
		274	default:
		275	return -EINVAL;
		276	}
		277	}
		278
		279	out:
		280	if (err) {
		281	DRM_ERROR("SDMA: Failed to init firmware \"%s\"\n", fw_name);
		282	amdgpu_sdma_destroy_inst_ctx(adev, duplicate);
		283	}
		284	return err;
		285	}

drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h+4−0

 int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
 				      struct amdgpu_irq_src *source,
 				      struct amdgpu_iv_entry *entry);
+int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,
+        char *fw_name, u32 instance, bool duplicate);
+void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev,
+        bool duplicate);
 #endif

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c+3−1

+// SPDX-License-Identifier: MIT
 /*
  * Copyright 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
 	struct hlist_node *tmp;
 	struct dma_fence *f;
 	int i;
 	hash_for_each_safe(sync->fences, i, tmp, e, node) {
 		f = e->fence;
 {
 	struct amdgpu_sync_entry *e;
 	struct hlist_node *tmp;
-	unsigned i;
+	unsigned int i;
 	hash_for_each_safe(sync->fences, i, tmp, e, node) {
 		hash_del(&e->node);

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h+7−5

 );
 TRACE_EVENT(amdgpu_cs,
-	    TP_PROTO(struct amdgpu_cs_parser *p, int i),
+	    TP_PROTO(struct amdgpu_cs_parser *p,
-	    TP_ARGS(p, i),
+		     struct amdgpu_job *job,
+		     struct amdgpu_ib *ib),
+	    TP_ARGS(p, job, ib),
 	    TP_STRUCT__entry(
 			     __field(struct amdgpu_bo_list *, bo_list)
 			     __field(u32, ring)
 	    TP_fast_assign(
 			   __entry->bo_list = p->bo_list;
-			   __entry->ring = to_amdgpu_ring(p->entity->rq->sched)->idx;
+			   __entry->ring = to_amdgpu_ring(job->base.sched)->idx;
-			   __entry->dw = p->job->ibs[i].length_dw;
+			   __entry->dw = ib->length_dw;
 			   __entry->fences = amdgpu_fence_count_emitted(
-				to_amdgpu_ring(p->entity->rq->sched));
+				to_amdgpu_ring(job->base.sched));
 			   ),
 	    TP_printk("bo_list=%p, ring=%u, dw=%u, fences=%u",
 		      __entry->bo_list, __entry->ring, __entry->dw,

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+15−33

 	adev = amdgpu_ttm_adev(bo->bdev);
-	if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
+	if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
+			 bo->ttm == NULL)) {
 		ttm_bo_move_null(bo, new_mem);
 		goto out;
 	}
 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
 					    const struct ttm_place *place)
 {
-	unsigned long num_pages = bo->resource->num_pages;
 	struct dma_resv_iter resv_cursor;
-	struct amdgpu_res_cursor cursor;
 	struct dma_fence *f;
+	if (!amdgpu_bo_is_amdgpu_bo(bo))
+		return ttm_bo_eviction_valuable(bo, place);
 	/* Swapout? */
 	if (bo->resource->mem_type == TTM_PL_SYSTEM)
 		return true;
 			return false;
 	}
-	switch (bo->resource->mem_type) {
+	/* Preemptible BOs don't own system resources managed by the
-	case AMDGPU_PL_PREEMPT:
+	 * driver (pages, VRAM, GART space). They point to resources
-		/* Preemptible BOs don't own system resources managed by the
+	 * owned by someone else (e.g. pageable memory in user mode
-		 * driver (pages, VRAM, GART space). They point to resources
+	 * or a DMABuf). They are used in a preemptible context so we
-		 * owned by someone else (e.g. pageable memory in user mode
+	 * can guarantee no deadlocks and good QoS in case of MMU
-		 * or a DMABuf). They are used in a preemptible context so we
+	 * notifiers or DMABuf move notifiers from the resource owner.
-		 * can guarantee no deadlocks and good QoS in case of MMU
+	 */
-		 * notifiers or DMABuf move notifiers from the resource owner.
+	if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
-		 */
 		return false;
-	case TTM_PL_TT:
-		if (amdgpu_bo_is_amdgpu_bo(bo) &&
-		    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
-			return false;
-		return true;
-	case TTM_PL_VRAM:
+	if (bo->resource->mem_type == TTM_PL_TT &&
-		/* Check each drm MM node individually */
+	    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
-		amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
-				 &cursor);
-		while (cursor.remaining) {
-			if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
-			    && !(place->lpfn &&
-				 place->lpfn <= PFN_DOWN(cursor.start)))
-				return true;
-			amdgpu_res_next(&cursor, cursor.size);
-		}
 		return false;
-	default:
-		break;
-	}
 	return ttm_bo_eviction_valuable(bo, place);
 }

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c+118−50

 	} else if (version_major == 2) {
 		const struct rlc_firmware_header_v2_0 *rlc_hdr =
 			container_of(hdr, struct rlc_firmware_header_v2_0, header);
+		const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 =
+			container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
+		const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 =
+			container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1);
+		const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 =
+			container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2);
+		const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 =
+			container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3);
-		DRM_DEBUG("ucode_feature_version: %u\n",
+		switch (version_minor) {
-			  le32_to_cpu(rlc_hdr->ucode_feature_version));
+		case 0:
-		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
+			/* rlc_hdr v2_0 */
-		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
+			DRM_DEBUG("ucode_feature_version: %u\n",
-		DRM_DEBUG("save_and_restore_offset: %u\n",
+				  le32_to_cpu(rlc_hdr->ucode_feature_version));
-			  le32_to_cpu(rlc_hdr->save_and_restore_offset));
+			DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
-		DRM_DEBUG("clear_state_descriptor_offset: %u\n",
+			DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
-			  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
+			DRM_DEBUG("save_and_restore_offset: %u\n",
-		DRM_DEBUG("avail_scratch_ram_locations: %u\n",
+				  le32_to_cpu(rlc_hdr->save_and_restore_offset));
-			  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
+			DRM_DEBUG("clear_state_descriptor_offset: %u\n",
-		DRM_DEBUG("reg_restore_list_size: %u\n",
+				  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
-			  le32_to_cpu(rlc_hdr->reg_restore_list_size));
+			DRM_DEBUG("avail_scratch_ram_locations: %u\n",
-		DRM_DEBUG("reg_list_format_start: %u\n",
+				  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
-			  le32_to_cpu(rlc_hdr->reg_list_format_start));
+			DRM_DEBUG("reg_restore_list_size: %u\n",
-		DRM_DEBUG("reg_list_format_separate_start: %u\n",
+				  le32_to_cpu(rlc_hdr->reg_restore_list_size));
-			  le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
+			DRM_DEBUG("reg_list_format_start: %u\n",
-		DRM_DEBUG("starting_offsets_start: %u\n",
+				  le32_to_cpu(rlc_hdr->reg_list_format_start));
-			  le32_to_cpu(rlc_hdr->starting_offsets_start));
+			DRM_DEBUG("reg_list_format_separate_start: %u\n",
-		DRM_DEBUG("reg_list_format_size_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
-			  le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
+			DRM_DEBUG("starting_offsets_start: %u\n",
-		DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr->starting_offsets_start));
-			  le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
+			DRM_DEBUG("reg_list_format_size_bytes: %u\n",
-		DRM_DEBUG("reg_list_size_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
-			  le32_to_cpu(rlc_hdr->reg_list_size_bytes));
+			DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
-		DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
-			  le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
+			DRM_DEBUG("reg_list_size_bytes: %u\n",
-		DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr->reg_list_size_bytes));
-			  le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
+			DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
-		DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
-			  le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
+			DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
-		DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
-			  le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
+			DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
-		DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
-			  le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
+			DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
-		if (version_minor == 1) {
+				  le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
-			const struct rlc_firmware_header_v2_1 *v2_1 =
+			DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
-				container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
+				  le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
+			break;
+		case 1:
+			/* rlc_hdr v2_1 */
 			DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
-				  le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
+				  le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length));
 			DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver));
 			DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver));
 			DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes));
 			DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes));
 			DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver));
 			DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver));
 			DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes));
 			DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes));
 			DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver));
 			DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver));
 			DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes));
 			DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
-				  le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
+				  le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes));
+			break;
+		case 2:
+			/* rlc_hdr v2_2 */
+			DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes));
+			DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes));
+			DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes));
+			DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes));
+			break;
+		case 3:
+			/* rlc_hdr v2_3 */
+			DRM_DEBUG("rlcp_ucode_version: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version));
+			DRM_DEBUG("rlcp_ucode_feature_version: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version));
+			DRM_DEBUG("rlcp_ucode_size_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes));
+			DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes));
+			DRM_DEBUG("rlcv_ucode_version: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version));
+			DRM_DEBUG("rlcv_ucode_feature_version: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version));
+			DRM_DEBUG("rlcv_ucode_size_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes));
+			DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes));
+			break;
+		case 4:
+			/* rlc_hdr v2_4 */
+			DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n",
+				  le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes));
+			DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes));
+			DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n",
+				  le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes));
+			DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes));
+			DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n",
+				  le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes));
+			DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes));
+			DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n",
+				  le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes));
+			DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes));
+			DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n",
+				  le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes));
+			DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n",
+				  le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes));
+			break;
+		default:
+			DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor);
+			break;
 		}
 	} else {
 		DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h+1−0

@@ -124,6 +124,7 @@ enum psp_fw_type { · 123 unmodified lines
124	PSP_FW_TYPE_PSP_SOC_DRV,	124	PSP_FW_TYPE_PSP_SOC_DRV,
125	PSP_FW_TYPE_PSP_INTF_DRV,	125	PSP_FW_TYPE_PSP_INTF_DRV,
126	PSP_FW_TYPE_PSP_DBG_DRV,	126	PSP_FW_TYPE_PSP_DBG_DRV,
		127	PSP_FW_TYPE_PSP_RAS_DRV,
127	};	128	};
128		129
129	/* version_major=2, version_minor=0 */	130	/* version_major=2, version_minor=0 */

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h+6−0

 #define __AMDGPU_UMC_H__
 #include "amdgpu_ras.h"
+#define UMC_INVALID_ADDR 0x1ULL
 /*
  * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
  * is the index of 4KB block
 	struct amdgpu_ras_block_object ras_block;
 	void (*err_cnt_init)(struct amdgpu_device *adev);
 	bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
+	void (*convert_ras_error_address)(struct amdgpu_device *adev,
+						 struct ras_err_data *err_data,
+						 uint32_t umc_reg_offset, uint32_t ch_inst,
+						 uint32_t umc_inst, uint64_t mca_addr);
 	void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev,
 				      void *ras_error_status);
 	void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h+19−0

 #define AMDGPU_VCN_SW_RING_FLAG		(1 << 9)
 #define AMDGPU_VCN_FW_LOGGING_FLAG	(1 << 10)
 #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
+#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
+#define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14)
 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER	0x00000001
 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER		0x00000001
 #define VCN_CODEC_DISABLE_MASK_HEVC (1 << 2)
 #define VCN_CODEC_DISABLE_MASK_H264 (1 << 3)
+#define AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU (0)
+#define AMDGPU_VCN_SMU_DPM_INTERFACE_APU (1)
 enum fw_queue_mode {
 	FW_QUEUE_RING_RESET = 1,
 	FW_QUEUE_DPG_HOLD_OFF = 2,
 	struct amdgpu_fw_shared_smu_interface_info smu_interface_info;
 };
+struct amdgpu_fw_shared_rb_setup {
+	uint32_t is_rb_enabled_flags;
+	uint32_t rb_addr_lo;
+	uint32_t rb_addr_hi;
+	uint32_t  rb_size;
+	uint32_t  rb4_addr_lo;
+	uint32_t  rb4_addr_hi;
+	uint32_t  rb4_size;
+	uint32_t  reserved[6];
+};
 struct amdgpu_vcn4_fw_shared {
 	uint32_t present_flag_0;
 	uint8_t pad[12];
 	struct amdgpu_fw_shared_unified_queue_struct sq;
 	uint8_t pad1[8];
 	struct amdgpu_fw_shared_fw_logging fw_log;
+	uint8_t pad2[20];
+	struct amdgpu_fw_shared_rb_setup rb_setup;
+	struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;
 };
 struct amdgpu_vcn_fwlog {

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c+56−1

@@ -690,7 +690,6 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev) · 689 unmodified lines
690	}	690	}
691	}	691	}
692		692
693
694	void amdgpu_detect_virtualization(struct amdgpu_device *adev)	693	void amdgpu_detect_virtualization(struct amdgpu_device *adev)
695	{	694	{
696	uint32_t reg;	695	uint32_t reg;
@@ -707,6 +706,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev) · 10 unmodified lines
707	case CHIP_SIENNA_CICHLID:	706	case CHIP_SIENNA_CICHLID:
708	case CHIP_ARCTURUS:	707	case CHIP_ARCTURUS:
709	case CHIP_ALDEBARAN:	708	case CHIP_ALDEBARAN:
		709	case CHIP_IP_DISCOVERY:
710	reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);	710	reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
711	break;	711	break;
712	default: /* other chip doesn't support SRIOV */	712	default: /* other chip doesn't support SRIOV */
@@ -750,6 +750,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev) · 37 unmodified lines
750	case CHIP_NAVI10:	750	case CHIP_NAVI10:
751	case CHIP_NAVI12:	751	case CHIP_NAVI12:
752	case CHIP_SIENNA_CICHLID:	752	case CHIP_SIENNA_CICHLID:
		753	case CHIP_IP_DISCOVERY:
753	nv_set_virt_ops(adev);	754	nv_set_virt_ops(adev);
754	/* try send GPU_INIT_DATA request to host */	755	/* try send GPU_INIT_DATA request to host */
755	amdgpu_virt_request_init_data(adev);	756	amdgpu_virt_request_init_data(adev);
@@ -807,6 +808,60 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad · 51 unmodified lines
807	return mode;	808	return mode;
808	}	809	}
809		810
		811	bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)
		812	{
		813	switch (adev->ip_versions[MP0_HWIP][0]) {
		814	case IP_VERSION(13, 0, 0):
		815	/* no vf autoload, white list */
		816	if (ucode_id == AMDGPU_UCODE_ID_VCN1 \|\|
		817	ucode_id == AMDGPU_UCODE_ID_VCN)
		818	return false;
		819	else
		820	return true;
		821	case IP_VERSION(13, 0, 10):
		822	/* white list */
		823	if (ucode_id == AMDGPU_UCODE_ID_CAP
		824	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP
		825	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME
		826	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC
		827	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK
		828	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK
		829	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK
		830	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK
		831	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK
		832	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK
		833	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK
		834	\|\| ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK
		835	\|\| ucode_id == AMDGPU_UCODE_ID_CP_MES
		836	\|\| ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA
		837	\|\| ucode_id == AMDGPU_UCODE_ID_CP_MES1
		838	\|\| ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA
		839	\|\| ucode_id == AMDGPU_UCODE_ID_VCN1
		840	\|\| ucode_id == AMDGPU_UCODE_ID_VCN)
		841	return false;
		842	else
		843	return true;
		844	default:
		845	/* lagacy black list */
		846	if (ucode_id == AMDGPU_UCODE_ID_SDMA0
		847	\|\| ucode_id == AMDGPU_UCODE_ID_SDMA1
		848	\|\| ucode_id == AMDGPU_UCODE_ID_SDMA2
		849	\|\| ucode_id == AMDGPU_UCODE_ID_SDMA3
		850	\|\| ucode_id == AMDGPU_UCODE_ID_SDMA4
		851	\|\| ucode_id == AMDGPU_UCODE_ID_SDMA5
		852	\|\| ucode_id == AMDGPU_UCODE_ID_SDMA6
		853	\|\| ucode_id == AMDGPU_UCODE_ID_SDMA7
		854	\|\| ucode_id == AMDGPU_UCODE_ID_RLC_G
		855	\|\| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
		856	\|\| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
		857	\|\| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
		858	\|\| ucode_id == AMDGPU_UCODE_ID_SMC)
		859	return true;
		860	else
		861	return false;
		862	}
		863	}
		864
810	void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,	865	void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
811	struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,	866	struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
812	struct amdgpu_video_codec_info *decode, uint32_t decode_array_size)	867	struct amdgpu_video_codec_info *decode, uint32_t decode_array_size)

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h+5−0

 	uint32_t decode_max_frame_pixels;
 	uint32_t encode_max_dimension_pixels;
 	uint32_t encode_max_frame_pixels;
+	/* the ucode id to signal the autoload */
+	uint32_t autoload_ucode_id;
 };
 struct amdgpu_video_codec_info;
 		       u32 acc_flags, u32 hwip);
 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
 		      u32 offset, u32 acc_flags, u32 hwip);
+bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
+			uint32_t ucode_id);
 #endif

drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c+2−2

@@ -282,8 +282,8 @@ static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, · 281 unmodified lines
282	return PTR_ERR(crtc_state);	282	return PTR_ERR(crtc_state);
283		283
284	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,	284	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
285	DRM_PLANE_HELPER_NO_SCALING,	285	DRM_PLANE_NO_SCALING,
286	DRM_PLANE_HELPER_NO_SCALING,	286	DRM_PLANE_NO_SCALING,
287	false, true);	287	false, true);
288	if (ret != 0)	288	if (ret != 0)
289	return ret;	289	return ret;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+67−30

 	struct amdgpu_bo *bo = vm_bo->bo;
 	vm_bo->moved = true;
+	spin_lock(&vm_bo->vm->status_lock);
 	if (bo->tbo.type == ttm_bo_type_kernel)
 		list_move(&vm_bo->vm_status, &vm->evicted);
 	else
 		list_move_tail(&vm_bo->vm_status, &vm->evicted);
+	spin_unlock(&vm_bo->vm->status_lock);
 }
 /**
  * amdgpu_vm_bo_moved - vm_bo is moved
  */
 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
 {
+	spin_lock(&vm_bo->vm->status_lock);
 	list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
+	spin_unlock(&vm_bo->vm->status_lock);
 }
 /**
  */
 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
 {
+	spin_lock(&vm_bo->vm->status_lock);
 	list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
+	spin_unlock(&vm_bo->vm->status_lock);
 	vm_bo->moved = false;
 }
  */
 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
 {
-	spin_lock(&vm_bo->vm->invalidated_lock);
+	spin_lock(&vm_bo->vm->status_lock);
 	list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
-	spin_unlock(&vm_bo->vm->invalidated_lock);
+	spin_unlock(&vm_bo->vm->status_lock);
 }
 /**
  */
 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
 {
-	if (vm_bo->bo->parent)
+	if (vm_bo->bo->parent) {
+		spin_lock(&vm_bo->vm->status_lock);
 		list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
-	else
+		spin_unlock(&vm_bo->vm->status_lock);
+	} else {
 		amdgpu_vm_bo_idle(vm_bo);
+	}
 }
 /**
  */
 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
 {
-	spin_lock(&vm_bo->vm->invalidated_lock);
+	spin_lock(&vm_bo->vm->status_lock);
 	list_move(&vm_bo->vm_status, &vm_bo->vm->done);
-	spin_unlock(&vm_bo->vm->invalidated_lock);
+	spin_unlock(&vm_bo->vm->status_lock);
 }
 /**
 			      int (*validate)(void *p, struct amdgpu_bo *bo),
 			      void *param)
 {
-	struct amdgpu_vm_bo_base *bo_base, *tmp;
+	struct amdgpu_vm_bo_base *bo_base;
+	struct amdgpu_bo *shadow;
+	struct amdgpu_bo *bo;
 	int r;
-	list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
+	spin_lock(&vm->status_lock);
-		struct amdgpu_bo *bo = bo_base->bo;
+	while (!list_empty(&vm->evicted)) {
-		struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
+		bo_base = list_first_entry(&vm->evicted,
+					   struct amdgpu_vm_bo_base,
+					   vm_status);
+		spin_unlock(&vm->status_lock);
+		bo = bo_base->bo;
+		shadow = amdgpu_bo_shadowed(bo);
 		r = validate(param, bo);
 		if (r)
 			vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
 			amdgpu_vm_bo_relocated(bo_base);
 		}
+		spin_lock(&vm->status_lock);
 	}
+	spin_unlock(&vm->status_lock);
 	amdgpu_vm_eviction_lock(vm);
 	vm->evicting = false;
  */
 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
 {
+	bool empty;
 	bool ret;
 	amdgpu_vm_eviction_lock(vm);
 	ret = !vm->evicting;
 	amdgpu_vm_eviction_unlock(vm);
-	return ret && list_empty(&vm->evicted);
+	spin_lock(&vm->status_lock);
+	empty = list_empty(&vm->evicted);
+	spin_unlock(&vm->status_lock);
+	return ret && empty;
 }
 /**
 	struct amdgpu_vm_update_params params;
 	struct amdgpu_vm_bo_base *entry;
 	bool flush_tlb_needed = false;
+	LIST_HEAD(relocated);
 	int r, idx;
-	if (list_empty(&vm->relocated))
+	spin_lock(&vm->status_lock);
+	list_splice_init(&vm->relocated, &relocated);
+	spin_unlock(&vm->status_lock);
+	if (list_empty(&relocated))
 		return 0;
 	if (!drm_dev_enter(adev_to_drm(adev), &idx))
 	if (r)
 		goto error;
-	list_for_each_entry(entry, &vm->relocated, vm_status) {
+	list_for_each_entry(entry, &relocated, vm_status) {
 		/* vm_flush_needed after updating moved PDEs */
 		flush_tlb_needed |= entry->moved;
 	if (flush_tlb_needed)
 		atomic64_inc(&vm->tlb_seq);
-	while (!list_empty(&vm->relocated)) {
+	while (!list_empty(&relocated)) {
-		entry = list_first_entry(&vm->relocated,
+		entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
-					 struct amdgpu_vm_bo_base,
 					 vm_status);
 		amdgpu_vm_bo_idle(entry);
 	}
 {
 	struct amdgpu_bo_va *bo_va, *tmp;
+	spin_lock(&vm->status_lock);
 	list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
 		if (!bo_va->base.bo)
 			continue;
 		amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
 				gtt_mem, cpu_mem);
 	}
-	spin_lock(&vm->invalidated_lock);
 	list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
 		if (!bo_va->base.bo)
 			continue;
 		amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
 				gtt_mem, cpu_mem);
 	}
-	spin_unlock(&vm->invalidated_lock);
+	spin_unlock(&vm->status_lock);
 }
 /**
  * amdgpu_vm_bo_update - update all BO mappings in the vm page table
 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
 			   struct amdgpu_vm *vm)
 {
-	struct amdgpu_bo_va *bo_va, *tmp;
+	struct amdgpu_bo_va *bo_va;
 	struct dma_resv *resv;
 	bool clear;
 	int r;
-	list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
+	spin_lock(&vm->status_lock);
+	while (!list_empty(&vm->moved)) {
+		bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
+					 base.vm_status);
+		spin_unlock(&vm->status_lock);
 		/* Per VM BOs never need to bo cleared in the page tables */
 		r = amdgpu_vm_bo_update(adev, bo_va, false);
 		if (r)
 			return r;
+		spin_lock(&vm->status_lock);
 	}
-	spin_lock(&vm->invalidated_lock);
 	while (!list_empty(&vm->invalidated)) {
 		bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
 					 base.vm_status);
 		resv = bo_va->base.bo->tbo.base.resv;
-		spin_unlock(&vm->invalidated_lock);
+		spin_unlock(&vm->status_lock);
 		/* Try to reserve the BO to avoid clearing its ptes */
 		if (!amdgpu_vm_debug && dma_resv_trylock(resv))
 		if (!clear)
 			dma_resv_unlock(resv);
-		spin_lock(&vm->invalidated_lock);
+		spin_lock(&vm->status_lock);
 	}
-	spin_unlock(&vm->invalidated_lock);
+	spin_unlock(&vm->status_lock);
 	return 0;
 }
 	if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
 	    !bo_va->base.moved) {
-		list_move(&bo_va->base.vm_status, &vm->moved);
+		amdgpu_vm_bo_moved(&bo_va->base);
 	}
 	trace_amdgpu_vm_bo_map(bo_va, mapping);
 }
 		}
 	}
-	spin_lock(&vm->invalidated_lock);
+	spin_lock(&vm->status_lock);
 	list_del(&bo_va->base.vm_status);
-	spin_unlock(&vm->invalidated_lock);
+	spin_unlock(&vm->status_lock);
 	list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
 		list_del(&mapping->list);
 	INIT_LIST_HEAD(&vm->moved);
 	INIT_LIST_HEAD(&vm->idle);
 	INIT_LIST_HEAD(&vm->invalidated);
-	spin_lock_init(&vm->invalidated_lock);
+	spin_lock_init(&vm->status_lock);
 	INIT_LIST_HEAD(&vm->freed);
 	INIT_LIST_HEAD(&vm->done);
+	INIT_LIST_HEAD(&vm->pt_freed);
+	INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
 	/* create scheduler entities for page table updates */
 	r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
 	amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
+	flush_work(&vm->pt_free_work);
 	root = amdgpu_bo_ref(vm->root.bo);
 	amdgpu_bo_reserve(root, true);
 	amdgpu_vm_set_pasid(adev, vm, 0);
 	unsigned int total_done_objs = 0;
 	unsigned int id = 0;
+	spin_lock(&vm->status_lock);
 	seq_puts(m, "\tIdle BOs:\n");
 	list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
 		if (!bo_va->base.bo)
 	id = 0;
 	seq_puts(m, "\tInvalidated BOs:\n");
-	spin_lock(&vm->invalidated_lock);
 	list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
 		if (!bo_va->base.bo)
 			continue;
 			continue;
 		total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
 	}
-	spin_unlock(&vm->invalidated_lock);
+	spin_unlock(&vm->status_lock);
 	total_done_objs = id;
 	seq_printf(m, "\tTotal idle size:        %12lld\tobjs:\t%d\n", total_idle,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+8−1

 	bool			evicting;
 	unsigned int		saved_flags;
+	/* Lock to protect vm_bo add/del/move on all lists of vm */
+	spinlock_t		status_lock;
 	/* BOs who needs a validation */
 	struct list_head	evicted;
 	/* regular invalidated BOs, but not yet updated in the PT */
 	struct list_head	invalidated;
-	spinlock_t		invalidated_lock;
 	/* BO mappings freed, but not yet updated in the PT */
 	struct list_head	freed;
 	/* BOs which are invalidated, has been updated in the PTs */
 	struct list_head        done;
+	/* PT BOs scheduled to free and fill with zero if vm_resv is not hold */
+	struct list_head	pt_freed;
+	struct work_struct	pt_free_work;
 	/* contains the page directory */
 	struct amdgpu_vm_bo_base     root;
 	struct dma_fence	*last_update;
 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
 			  uint64_t start, uint64_t end,
 			  uint64_t dst, uint64_t flags);
+void amdgpu_vm_pt_free_work(struct work_struct *work);
 #if defined(CONFIG_DEBUG_FS)
 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c+41−3

@@ -637,10 +637,34 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry) · 636 unmodified lines
637	}	637	}
638	ttm_bo_set_bulk_move(&entry->bo->tbo, NULL);	638	ttm_bo_set_bulk_move(&entry->bo->tbo, NULL);
639	entry->bo->vm_bo = NULL;	639	entry->bo->vm_bo = NULL;
		640
		641	spin_lock(&entry->vm->status_lock);
640	list_del(&entry->vm_status);	642	list_del(&entry->vm_status);
		643	spin_unlock(&entry->vm->status_lock);
641	amdgpu_bo_unref(&entry->bo);	644	amdgpu_bo_unref(&entry->bo);
642	}	645	}
643		646
		647	void amdgpu_vm_pt_free_work(struct work_struct *work)
		648	{
		649	struct amdgpu_vm_bo_base entry, next;
		650	struct amdgpu_vm *vm;
		651	LIST_HEAD(pt_freed);
		652
		653	vm = container_of(work, struct amdgpu_vm, pt_free_work);
		654
		655	spin_lock(&vm->status_lock);
		656	list_splice_init(&vm->pt_freed, &pt_freed);
		657	spin_unlock(&vm->status_lock);
		658
		659	/* flush_work in amdgpu_vm_fini ensure vm->root.bo is valid. */
		660	amdgpu_bo_reserve(vm->root.bo, true);
		661
		662	list_for_each_entry_safe(entry, next, &pt_freed, vm_status)
		663	amdgpu_vm_pt_free(entry);
		664
		665	amdgpu_bo_unreserve(vm->root.bo);
		666	}
		667
644	/**	668	/**
645	* amdgpu_vm_pt_free_dfs - free PD/PT levels	669	* amdgpu_vm_pt_free_dfs - free PD/PT levels
646	*	670	*
@@ -652,11 +676,24 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry) · 5 unmodified lines
652	*/	676	*/
653	static void amdgpu_vm_pt_free_dfs(struct amdgpu_device *adev,	677	static void amdgpu_vm_pt_free_dfs(struct amdgpu_device *adev,
654	struct amdgpu_vm *vm,	678	struct amdgpu_vm *vm,
655	struct amdgpu_vm_pt_cursor *start)	679	struct amdgpu_vm_pt_cursor *start,
		680	bool unlocked)
656	{	681	{
657	struct amdgpu_vm_pt_cursor cursor;	682	struct amdgpu_vm_pt_cursor cursor;
658	struct amdgpu_vm_bo_base *entry;	683	struct amdgpu_vm_bo_base *entry;
659		684
		685	if (unlocked) {
		686	spin_lock(&vm->status_lock);
		687	for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
		688	list_move(&entry->vm_status, &vm->pt_freed);
		689
		690	if (start)
		691	list_move(&start->entry->vm_status, &vm->pt_freed);
		692	spin_unlock(&vm->status_lock);
		693	schedule_work(&vm->pt_free_work);
		694	return;
		695	}
		696
660	for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)	697	for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
661	amdgpu_vm_pt_free(entry);	698	amdgpu_vm_pt_free(entry);
662		699
@@ -673,7 +710,7 @@ static void amdgpu_vm_pt_free_dfs(struct amdgpu_device *adev, · 10 unmodified lines
673	*/	710	*/
674	void amdgpu_vm_pt_free_root(struct amdgpu_device adev, struct amdgpu_vm vm)	711	void amdgpu_vm_pt_free_root(struct amdgpu_device adev, struct amdgpu_vm vm)
675	{	712	{
676	amdgpu_vm_pt_free_dfs(adev, vm, NULL);	713	amdgpu_vm_pt_free_dfs(adev, vm, NULL, false);
677	}	714	}
678		715
679	/**	716	/**
@@ -966,7 +1003,8 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, · 286 unmodified lines
966	if (cursor.entry->bo) {	1003	if (cursor.entry->bo) {
967	params->table_freed = true;	1004	params->table_freed = true;
968	amdgpu_vm_pt_free_dfs(adev, params->vm,	1005	amdgpu_vm_pt_free_dfs(adev, params->vm,
969	&cursor);	1006	&cursor,
		1007	params->unlocked);
970	}	1008	}
971	amdgpu_vm_pt_next(adev, &cursor);	1009	amdgpu_vm_pt_next(adev, &cursor);
972	}	1010	}

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c+8−4

 		swap(p->vm->last_unlocked, tmp);
 		dma_fence_put(tmp);
 	} else {
-		amdgpu_bo_fence(p->vm->root.bo, f, true);
+		dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f,
+				   DMA_RESV_USAGE_BOOKKEEP);
 	}
 	if (fence && !p->immediate)
 	int r;
 	/* Wait for PD/PT moves to be completed */
-	dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
+	dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL);
-				DMA_RESV_USAGE_KERNEL, fence) {
+	dma_resv_for_each_fence_unlocked(&cursor, fence) {
 		r = amdgpu_sync_fence(&p->job->sync, fence);
-		if (r)
+		if (r) {
+			dma_resv_iter_end(&cursor);
 			return r;
+		}
 	}
+	dma_resv_iter_end(&cursor);
 	do {
 		ndw = p->num_dw_left;

drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c+68−0

@@ -720,6 +720,72 @@ uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr) · 719 unmodified lines
720	return atomic64_read(&mgr->vis_usage);	720	return atomic64_read(&mgr->vis_usage);
721	}	721	}
722		722
		723	/**
		724	* amdgpu_vram_mgr_intersects - test each drm buddy block for intersection
		725	*
		726	* @man: TTM memory type manager
		727	* @res: The resource to test
		728	* @place: The place to test against
		729	* @size: Size of the new allocation
		730	*
		731	* Test each drm buddy block for intersection for eviction decision.
		732	*/
		733	static bool amdgpu_vram_mgr_intersects(struct ttm_resource_manager *man,
		734	struct ttm_resource *res,
		735	const struct ttm_place *place,
		736	size_t size)
		737	{
		738	struct amdgpu_vram_mgr_resource *mgr = to_amdgpu_vram_mgr_resource(res);
		739	struct drm_buddy_block *block;
		740
		741	/* Check each drm buddy block individually */
		742	list_for_each_entry(block, &mgr->blocks, link) {
		743	unsigned long fpfn =
		744	amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT;
		745	unsigned long lpfn = fpfn +
		746	(amdgpu_vram_mgr_block_size(block) >> PAGE_SHIFT);
		747
		748	if (place->fpfn < lpfn &&
		749	(!place->lpfn \|\| place->lpfn > fpfn))
		750	return true;
		751	}
		752
		753	return false;
		754	}
		755
		756	/**
		757	* amdgpu_vram_mgr_compatible - test each drm buddy block for compatibility
		758	*
		759	* @man: TTM memory type manager
		760	* @res: The resource to test
		761	* @place: The place to test against
		762	* @size: Size of the new allocation
		763	*
		764	* Test each drm buddy block for placement compatibility.
		765	*/
		766	static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man,
		767	struct ttm_resource *res,
		768	const struct ttm_place *place,
		769	size_t size)
		770	{
		771	struct amdgpu_vram_mgr_resource *mgr = to_amdgpu_vram_mgr_resource(res);
		772	struct drm_buddy_block *block;
		773
		774	/* Check each drm buddy block individually */
		775	list_for_each_entry(block, &mgr->blocks, link) {
		776	unsigned long fpfn =
		777	amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT;
		778	unsigned long lpfn = fpfn +
		779	(amdgpu_vram_mgr_block_size(block) >> PAGE_SHIFT);
		780
		781	if (fpfn < place->fpfn \|\|
		782	(place->lpfn && lpfn > place->lpfn))
		783	return false;
		784	}
		785
		786	return true;
		787	}
		788
723	/**	789	/**
724	* amdgpu_vram_mgr_debug - dump VRAM table	790	* amdgpu_vram_mgr_debug - dump VRAM table
725	*	791	*
@@ -753,6 +819,8 @@ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man, · 27 unmodified lines
753	static const struct ttm_resource_manager_func amdgpu_vram_mgr_func = {	819	static const struct ttm_resource_manager_func amdgpu_vram_mgr_func = {
754	.alloc = amdgpu_vram_mgr_new,	820	.alloc = amdgpu_vram_mgr_new,
755	.free = amdgpu_vram_mgr_del,	821	.free = amdgpu_vram_mgr_del,
		822	.intersects = amdgpu_vram_mgr_intersects,
		823	.compatible = amdgpu_vram_mgr_compatible,
756	.debug = amdgpu_vram_mgr_debug	824	.debug = amdgpu_vram_mgr_debug
757	};	825	};
758		826

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c+18−6

 		goto pro_end;
 	}
+	/**
+	 * Only init hive->reset_domain for none SRIOV configuration. For SRIOV,
+	 * Host driver decide how to reset the GPU either through FLR or chain reset.
+	 * Guest side will get individual notifications from the host for the FLR
+	 * if necessary.
+	 */
+	if (!amdgpu_sriov_vf(adev)) {
 	/**
 	 * Avoid recreating reset domain when hive is reconstructed for the case
-	 * of reset the devices in the XGMI hive during probe for SRIOV
+	 * of reset the devices in the XGMI hive during probe for passthrough GPU
 	 * See https://www.spinics.net/lists/amd-gfx/msg58836.html
 	 */
-	if (adev->reset_domain->type != XGMI_HIVE) {
+		if (adev->reset_domain->type != XGMI_HIVE) {
-		hive->reset_domain = amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive");
+			hive->reset_domain =
+				amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive");
 			if (!hive->reset_domain) {
 				dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n");
 				ret = -ENOMEM;
 				hive = NULL;
 				goto pro_end;
 			}
-	} else {
+		} else {
-		amdgpu_reset_get_reset_domain(adev->reset_domain);
+			amdgpu_reset_get_reset_domain(adev->reset_domain);
-		hive->reset_domain = adev->reset_domain;
+			hive->reset_domain = adev->reset_domain;
+		}
 	}
 	hive->hive_id = adev->gmc.xgmi.hive_id;
 {
 	int ret;
+	if (amdgpu_sriov_vf(adev))
+		return 0;
 	/* Each psp need to set the latest topology */
 	ret = psp_xgmi_set_topology_info(&adev->psp,
 					 atomic_read(&hive->number_devices),

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h+1−0

@@ -43,6 +43,7 @@ struct amdgpu_hive_info { · 42 unmodified lines
43	} pstate;	43	} pstate;
44		44
45	struct amdgpu_reset_domain *reset_domain;	45	struct amdgpu_reset_domain *reset_domain;
		46	uint32_t device_remove_count;
46	};	47	};
47		48
48	struct amdgpu_pcs_ras_field {	49	struct amdgpu_pcs_ras_field {

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+24−267

@@ -3943,56 +3943,6 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) · 3942 unmodified lines
3943	DRM_WARN_ONCE("CP firmware version too old, please update!");	3943	DRM_WARN_ONCE("CP firmware version too old, please update!");
3944	}	3944	}
3945		3945
3946
3947	static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3948	{
3949	const struct rlc_firmware_header_v2_1 *rlc_hdr;
3950
3951	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3952	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3953	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3954	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3955	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3956	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3957	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3958	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3959	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3960	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3961	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3962	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3963	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3964	adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3965	le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3966	}
3967
3968	static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3969	{
3970	const struct rlc_firmware_header_v2_2 *rlc_hdr;
3971
3972	rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3973	adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3974	adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3975	adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3976	adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3977	}
3978
3979	static void gfx_v10_0_init_tap_delays_microcode(struct amdgpu_device *adev)
3980	{
3981	const struct rlc_firmware_header_v2_4 *rlc_hdr;
3982
3983	rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;
3984	adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);
3985	adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);
3986	adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);
3987	adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);
3988	adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);
3989	adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);
3990	adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);
3991	adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);
3992	adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);
3993	adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);
3994	}
3995
3996	static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)	3946	static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3997	{	3947	{
3998	bool ret = false;	3948	bool ret = false;
@@ -4028,12 +3978,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 29 unmodified lines
4028	char fw_name[40];	3978	char fw_name[40];
4029	char *wks = "";	3979	char *wks = "";
4030	int err;	3980	int err;
4031	struct amdgpu_firmware_info *info = NULL;
4032	const struct common_firmware_header *header = NULL;
4033	const struct gfx_firmware_header_v1_0 *cp_hdr;
4034	const struct rlc_firmware_header_v2_0 *rlc_hdr;	3981	const struct rlc_firmware_header_v2_0 *rlc_hdr;
4035	unsigned int *tmp = NULL;
4036	unsigned int i = 0;
4037	uint16_t version_major;	3982	uint16_t version_major;
4038	uint16_t version_minor;	3983	uint16_t version_minor;
4039		3984
@@ -4091,9 +4036,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 51 unmodified lines
4091	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);	4036	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4092	if (err)	4037	if (err)
4093	goto out;	4038	goto out;
4094	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;	4039	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4095	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4096	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4097		4040
4098	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);	4041	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4099	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);	4042	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
@@ -4102,9 +4045,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 2 unmodified lines
4102	err = amdgpu_ucode_validate(adev->gfx.me_fw);	4045	err = amdgpu_ucode_validate(adev->gfx.me_fw);
4103	if (err)	4046	if (err)
4104	goto out;	4047	goto out;
4105	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;	4048	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4106	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4107	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4108		4049
4109	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);	4050	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4110	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);	4051	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
@@ -4113,69 +4054,27 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 2 unmodified lines
4113	err = amdgpu_ucode_validate(adev->gfx.ce_fw);	4054	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4114	if (err)	4055	if (err)
4115	goto out;	4056	goto out;
4116	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;	4057	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4117	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4118	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4119		4058
4120	if (!amdgpu_sriov_vf(adev)) {	4059	if (!amdgpu_sriov_vf(adev)) {
4121	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);	4060	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4122	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);	4061	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4123	if (err)	4062	if (err)
4124	goto out;	4063	goto out;
		4064	/* don't check this. There are apparently firmwares in the wild with
		4065	* incorrect size in the header
		4066	*/
4125	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);	4067	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
		4068	if (err)
		4069	dev_dbg(adev->dev,
		4070	"gfx10: amdgpu_ucode_validate() failed \"%s\"\n",
		4071	fw_name);
4126	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;	4072	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4127	version_major = le16_to_cpu(rlc_hdr->header.header_version_major);	4073	version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4128	version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);	4074	version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4129		4075	err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4130	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);	4076	if (err)
4131	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4132	adev->gfx.rlc.save_and_restore_offset =
4133	le32_to_cpu(rlc_hdr->save_and_restore_offset);
4134	adev->gfx.rlc.clear_state_descriptor_offset =
4135	le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4136	adev->gfx.rlc.avail_scratch_ram_locations =
4137	le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4138	adev->gfx.rlc.reg_restore_list_size =
4139	le32_to_cpu(rlc_hdr->reg_restore_list_size);
4140	adev->gfx.rlc.reg_list_format_start =
4141	le32_to_cpu(rlc_hdr->reg_list_format_start);
4142	adev->gfx.rlc.reg_list_format_separate_start =
4143	le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4144	adev->gfx.rlc.starting_offsets_start =
4145	le32_to_cpu(rlc_hdr->starting_offsets_start);
4146	adev->gfx.rlc.reg_list_format_size_bytes =
4147	le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4148	adev->gfx.rlc.reg_list_size_bytes =
4149	le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4150	adev->gfx.rlc.register_list_format =
4151	kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4152	adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4153	if (!adev->gfx.rlc.register_list_format) {
4154	err = -ENOMEM;
4155	goto out;	4077	goto out;
4156	}
4157
4158	tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4159	le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4160	for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4161	adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4162
4163	adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4164
4165	tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4166	le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4167	for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4168	adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4169
4170	if (version_major == 2) {
4171	if (version_minor >= 1)
4172	gfx_v10_0_init_rlc_ext_microcode(adev);
4173	if (version_minor >= 2)
4174	gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4175	if (version_minor == 4) {
4176	gfx_v10_0_init_tap_delays_microcode(adev);
4177	}
4178	}
4179	}	4078	}
4180		4079
4181	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);	4080	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
@@ -4185,9 +4084,8 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 3 unmodified lines
4185	err = amdgpu_ucode_validate(adev->gfx.mec_fw);	4084	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4186	if (err)	4085	if (err)
4187	goto out;	4086	goto out;
4188	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;	4087	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4189	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);	4088	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4190	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4191		4089
4192	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);	4090	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4193	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);	4091	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
@@ -4195,164 +4093,18 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 1 unmodified line
4195	err = amdgpu_ucode_validate(adev->gfx.mec2_fw);	4093	err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4196	if (err)	4094	if (err)
4197	goto out;	4095	goto out;
4198	cp_hdr = (const struct gfx_firmware_header_v1_0 *)	4096	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4199	adev->gfx.mec2_fw->data;	4097	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4200	adev->gfx.mec2_fw_version =
4201	le32_to_cpu(cp_hdr->header.ucode_version);
4202	adev->gfx.mec2_feature_version =
4203	le32_to_cpu(cp_hdr->ucode_feature_version);
4204	} else {	4098	} else {
4205	err = 0;	4099	err = 0;
4206	adev->gfx.mec2_fw = NULL;	4100	adev->gfx.mec2_fw = NULL;
4207	}	4101	}
4208		4102
4209	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4210	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4211	info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4212	info->fw = adev->gfx.pfp_fw;
4213	header = (const struct common_firmware_header *)info->fw->data;
4214	adev->firmware.fw_size +=
4215	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4216
4217	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4218	info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4219	info->fw = adev->gfx.me_fw;
4220	header = (const struct common_firmware_header *)info->fw->data;
4221	adev->firmware.fw_size +=
4222	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4223
4224	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4225	info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4226	info->fw = adev->gfx.ce_fw;
4227	header = (const struct common_firmware_header *)info->fw->data;
4228	adev->firmware.fw_size +=
4229	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4230
4231	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4232	info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4233	info->fw = adev->gfx.rlc_fw;
4234	if (info->fw) {
4235	header = (const struct common_firmware_header *)info->fw->data;
4236	adev->firmware.fw_size +=
4237	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4238	}
4239	if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4240	adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4241	adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4242	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4243	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4244	info->fw = adev->gfx.rlc_fw;
4245	adev->firmware.fw_size +=
4246	ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4247
4248	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4249	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4250	info->fw = adev->gfx.rlc_fw;
4251	adev->firmware.fw_size +=
4252	ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4253
4254	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4255	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4256	info->fw = adev->gfx.rlc_fw;
4257	adev->firmware.fw_size +=
4258	ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4259
4260	if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4261	adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4262	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4263	info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4264	info->fw = adev->gfx.rlc_fw;
4265	adev->firmware.fw_size +=
4266	ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4267
4268	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4269	info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4270	info->fw = adev->gfx.rlc_fw;
4271	adev->firmware.fw_size +=
4272	ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4273	}
4274
4275	}
4276
4277	if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {
4278	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];
4279	info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;
4280	info->fw = adev->gfx.rlc_fw;
4281	adev->firmware.fw_size +=
4282	ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);
4283	}
4284
4285	if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {
4286	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];
4287	info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;
4288	info->fw = adev->gfx.rlc_fw;
4289	adev->firmware.fw_size +=
4290	ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);
4291	}
4292
4293	if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {
4294	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];
4295	info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;
4296	info->fw = adev->gfx.rlc_fw;
4297	adev->firmware.fw_size +=
4298	ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);
4299	}
4300
4301	if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {
4302	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];
4303	info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;
4304	info->fw = adev->gfx.rlc_fw;
4305	adev->firmware.fw_size +=
4306	ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);
4307	}
4308
4309	if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {
4310	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];
4311	info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;
4312	info->fw = adev->gfx.rlc_fw;
4313	adev->firmware.fw_size +=
4314	ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);
4315	}
4316
4317	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4318	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4319	info->fw = adev->gfx.mec_fw;
4320	header = (const struct common_firmware_header *)info->fw->data;
4321	cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4322	adev->firmware.fw_size +=
4323	ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4324	le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4325
4326	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4327	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4328	info->fw = adev->gfx.mec_fw;
4329	adev->firmware.fw_size +=
4330	ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4331
4332	if (adev->gfx.mec2_fw) {
4333	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4334	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4335	info->fw = adev->gfx.mec2_fw;
4336	header = (const struct common_firmware_header *)info->fw->data;
4337	cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4338	adev->firmware.fw_size +=
4339	ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4340	le32_to_cpu(cp_hdr->jt_size) * 4,
4341	PAGE_SIZE);
4342	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4343	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4344	info->fw = adev->gfx.mec2_fw;
4345	adev->firmware.fw_size +=
4346	ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4347	PAGE_SIZE);
4348	}
4349	}
4350
4351	gfx_v10_0_check_fw_write_wait(adev);	4103	gfx_v10_0_check_fw_write_wait(adev);
4352	out:	4104	out:
4353	if (err) {	4105	if (err) {
4354	dev_err(adev->dev,	4106	dev_err(adev->dev,
4355	"gfx10: Failed to load firmware \"%s\"\n",	4107	"gfx10: Failed to init firmware \"%s\"\n",
4356	fw_name);	4108	fw_name);
4357	release_firmware(adev->gfx.pfp_fw);	4109	release_firmware(adev->gfx.pfp_fw);
4358	adev->gfx.pfp_fw = NULL;	4110	adev->gfx.pfp_fw = NULL;
@@ -5981,6 +5733,9 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) · 1622 unmodified lines
5981	WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);	5733	WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5982	}	5734	}
5983		5735
		5736	if (adev->job_hang && !enable)
		5737	return 0;
		5738
5984	for (i = 0; i < adev->usec_timeout; i++) {	5739	for (i = 0; i < adev->usec_timeout; i++) {
5985	if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)	5740	if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5986	break;	5741	break;
@@ -7579,8 +7334,10 @@ static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) · 1592 unmodified lines
7579	for (i = 0; i < adev->gfx.num_gfx_rings; i++)	7334	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7580	kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],	7335	kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7581	PREEMPT_QUEUES, 0, 0);	7336	PREEMPT_QUEUES, 0, 0);
7582		7337	if (!adev->job_hang)
7583	return amdgpu_ring_test_helper(kiq_ring);	7338	return amdgpu_ring_test_helper(kiq_ring);
		7339	else
		7340	return 0;
7584	}	7341	}
7585	#endif	7342	#endif
7586		7343

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c+37−180

@@ -73,21 +73,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); · 72 unmodified lines
73	MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin");	73	MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin");
74	MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin");	74	MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin");
75	MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin");	75	MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin");
76		76	MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin");
77	static const struct soc15_reg_golden golden_settings_gc_11_0[] =	77	MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin");
78	{	78	MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin");
79	/* Pending on emulation bring up */	79	MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin");
80	};
81
82	static const struct soc15_reg_golden golden_settings_gc_11_0_0[] =
83	{
84	/* Pending on emulation bring up */
85	};
86
87	static const struct soc15_reg_golden golden_settings_gc_rlc_spm_11_0[] =
88	{
89	/* Pending on emulation bring up */
90	};
91		80
92	static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =	81	static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
93	{	82	{
@@ -269,34 +258,10 @@ static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) · 175 unmodified lines
269	adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs;	258	adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs;
270	}	259	}
271		260
272	static void gfx_v11_0_init_spm_golden_registers(struct amdgpu_device *adev)
273	{
274	switch (adev->ip_versions[GC_HWIP][0]) {
275	case IP_VERSION(11, 0, 0):
276	soc15_program_register_sequence(adev,
277	golden_settings_gc_rlc_spm_11_0,
278	(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_11_0));
279	break;
280	default:
281	break;
282	}
283	}
284
285	static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)	261	static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
286	{	262	{
287	switch (adev->ip_versions[GC_HWIP][0]) {	263	switch (adev->ip_versions[GC_HWIP][0]) {
288	case IP_VERSION(11, 0, 0):
289	soc15_program_register_sequence(adev,
290	golden_settings_gc_11_0,
291	(const u32)ARRAY_SIZE(golden_settings_gc_11_0));
292	soc15_program_register_sequence(adev,
293	golden_settings_gc_11_0_0,
294	(const u32)ARRAY_SIZE(golden_settings_gc_11_0_0));
295	break;
296	case IP_VERSION(11, 0, 1):	264	case IP_VERSION(11, 0, 1):
297	soc15_program_register_sequence(adev,
298	golden_settings_gc_11_0,
299	(const u32)ARRAY_SIZE(golden_settings_gc_11_0));
300	soc15_program_register_sequence(adev,	265	soc15_program_register_sequence(adev,
301	golden_settings_gc_11_0_1,	266	golden_settings_gc_11_0_1,
302	(const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));	267	(const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
@@ -304,7 +269,6 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) · 1 unmodified line
304	default:	269	default:
305	break;	270	break;
306	}	271	}
307	gfx_v11_0_init_spm_golden_registers(adev);
308	}	272	}
309		273
310	static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,	274	static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
@@ -479,10 +443,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) · 168 unmodified lines
479	char fw_name[40];	443	char fw_name[40];
480	char ucode_prefix[30];	444	char ucode_prefix[30];
481	int err;	445	int err;
482	struct amdgpu_firmware_info *info = NULL;
483	const struct common_firmware_header *header = NULL;
484	const struct gfx_firmware_header_v1_0 *cp_hdr;
485	const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
486	const struct rlc_firmware_header_v2_0 *rlc_hdr;	446	const struct rlc_firmware_header_v2_0 *rlc_hdr;
487	uint16_t version_major;	447	uint16_t version_major;
488	uint16_t version_minor;	448	uint16_t version_minor;
@@ -504,14 +464,11 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) · 15 unmodified lines
504	adev->gfx.pfp_fw->data, 2, 0);	464	adev->gfx.pfp_fw->data, 2, 0);
505	if (adev->gfx.rs64_enable) {	465	if (adev->gfx.rs64_enable) {
506	dev_info(adev->dev, "CP RS64 enable\n");	466	dev_info(adev->dev, "CP RS64 enable\n");
507	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data;	467	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
508	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version);	468	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
509	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);	469	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK);
510
511	} else {	470	} else {
512	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;	471	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
513	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
514	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
515	}	472	}
516		473
517	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix);	474	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix);
@@ -522,14 +479,11 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) · 4 unmodified lines
522	if (err)	479	if (err)
523	goto out;	480	goto out;
524	if (adev->gfx.rs64_enable) {	481	if (adev->gfx.rs64_enable) {
525	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data;	482	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
526	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version);	483	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
527	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);	484	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK);
528
529	} else {	485	} else {
530	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;	486	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
531	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
532	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
533	}	487	}
534		488
535	if (!amdgpu_sriov_vf(adev)) {	489	if (!amdgpu_sriov_vf(adev)) {
@@ -556,136 +510,23 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) · 20 unmodified lines
556	if (err)	510	if (err)
557	goto out;	511	goto out;
558	if (adev->gfx.rs64_enable) {	512	if (adev->gfx.rs64_enable) {
559	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;	513	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
560	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version);	514	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
561	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);	515	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
562		516	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK);
		517	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK);
563	} else {	518	} else {
564	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;	519	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
565	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);	520	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
566	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
567	}	521	}
568		522
569	/* only one MEC for gfx 11.0.0. */	523	/* only one MEC for gfx 11.0.0. */
570	adev->gfx.mec2_fw = NULL;	524	adev->gfx.mec2_fw = NULL;
571		525
572	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
573	if (adev->gfx.rs64_enable) {
574	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data;
575	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP];
576	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP;
577	info->fw = adev->gfx.pfp_fw;
578	header = (const struct common_firmware_header *)info->fw->data;
579	adev->firmware.fw_size +=
580	ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE);
581
582	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK];
583	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK;
584	info->fw = adev->gfx.pfp_fw;
585	header = (const struct common_firmware_header *)info->fw->data;
586	adev->firmware.fw_size +=
587	ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE);
588
589	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK];
590	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK;
591	info->fw = adev->gfx.pfp_fw;
592	header = (const struct common_firmware_header *)info->fw->data;
593	adev->firmware.fw_size +=
594	ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE);
595
596	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data;
597	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME];
598	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME;
599	info->fw = adev->gfx.me_fw;
600	header = (const struct common_firmware_header *)info->fw->data;
601	adev->firmware.fw_size +=
602	ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE);
603
604	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK];
605	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK;
606	info->fw = adev->gfx.me_fw;
607	header = (const struct common_firmware_header *)info->fw->data;
608	adev->firmware.fw_size +=
609	ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE);
610
611	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK];
612	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK;
613	info->fw = adev->gfx.me_fw;
614	header = (const struct common_firmware_header *)info->fw->data;
615	adev->firmware.fw_size +=
616	ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE);
617
618	cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
619	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC];
620	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC;
621	info->fw = adev->gfx.mec_fw;
622	header = (const struct common_firmware_header *)info->fw->data;
623	adev->firmware.fw_size +=
624	ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE);
625
626	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK];
627	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK;
628	info->fw = adev->gfx.mec_fw;
629	header = (const struct common_firmware_header *)info->fw->data;
630	adev->firmware.fw_size +=
631	ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE);
632
633	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK];
634	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK;
635	info->fw = adev->gfx.mec_fw;
636	header = (const struct common_firmware_header *)info->fw->data;
637	adev->firmware.fw_size +=
638	ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE);
639
640	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK];
641	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK;
642	info->fw = adev->gfx.mec_fw;
643	header = (const struct common_firmware_header *)info->fw->data;
644	adev->firmware.fw_size +=
645	ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE);
646
647	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK];
648	info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK;
649	info->fw = adev->gfx.mec_fw;
650	header = (const struct common_firmware_header *)info->fw->data;
651	adev->firmware.fw_size +=
652	ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE);
653	} else {
654	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
655	info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
656	info->fw = adev->gfx.pfp_fw;
657	header = (const struct common_firmware_header *)info->fw->data;
658	adev->firmware.fw_size +=
659	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
660
661	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
662	info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
663	info->fw = adev->gfx.me_fw;
664	header = (const struct common_firmware_header *)info->fw->data;
665	adev->firmware.fw_size +=
666	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
667
668	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
669	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
670	info->fw = adev->gfx.mec_fw;
671	header = (const struct common_firmware_header *)info->fw->data;
672	cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
673	adev->firmware.fw_size +=
674	ALIGN(le32_to_cpu(header->ucode_size_bytes) -
675	le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
676
677	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
678	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
679	info->fw = adev->gfx.mec_fw;
680	adev->firmware.fw_size +=
681	ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
682	}
683	}
684
685	out:	526	out:
686	if (err) {	527	if (err) {
687	dev_err(adev->dev,	528	dev_err(adev->dev,
688	"gfx11: Failed to load firmware \"%s\"\n",	529	"gfx11: Failed to init firmware \"%s\"\n",
689	fw_name);	530	fw_name);
690	release_firmware(adev->gfx.pfp_fw);	531	release_firmware(adev->gfx.pfp_fw);
691	adev->gfx.pfp_fw = NULL;	532	adev->gfx.pfp_fw = NULL;
@@ -997,7 +838,6 @@ static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { · 305 unmodified lines
997	.read_wave_sgprs = &gfx_v11_0_read_wave_sgprs,	838	.read_wave_sgprs = &gfx_v11_0_read_wave_sgprs,
998	.read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,	839	.read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
999	.select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,	840	.select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
1000	.init_spm_golden = &gfx_v11_0_init_spm_golden_registers,
1001	.update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,	841	.update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
1002	};	842	};
1003		843
@@ -1008,6 +848,7 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) · 4 unmodified lines
1008	switch (adev->ip_versions[GC_HWIP][0]) {	848	switch (adev->ip_versions[GC_HWIP][0]) {
1009	case IP_VERSION(11, 0, 0):	849	case IP_VERSION(11, 0, 0):
1010	case IP_VERSION(11, 0, 2):	850	case IP_VERSION(11, 0, 2):
		851	case IP_VERSION(11, 0, 3):
1011	adev->gfx.config.max_hw_contexts = 8;	852	adev->gfx.config.max_hw_contexts = 8;
1012	adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;	853	adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1013	adev->gfx.config.sc_prim_fifo_size_backend = 0x100;	854	adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -1443,6 +1284,7 @@ static int gfx_v11_0_sw_init(void *handle) · 429 unmodified lines
1443	case IP_VERSION(11, 0, 0):	1284	case IP_VERSION(11, 0, 0):
1444	case IP_VERSION(11, 0, 1):	1285	case IP_VERSION(11, 0, 1):
1445	case IP_VERSION(11, 0, 2):	1286	case IP_VERSION(11, 0, 2):
		1287	case IP_VERSION(11, 0, 3):
1446	adev->gfx.me.num_me = 1;	1288	adev->gfx.me.num_me = 1;
1447	adev->gfx.me.num_pipe_per_me = 1;	1289	adev->gfx.me.num_pipe_per_me = 1;
1448	adev->gfx.me.num_queue_per_pipe = 1;	1290	adev->gfx.me.num_queue_per_pipe = 1;
@@ -2617,6 +2459,21 @@ static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) · 1168 unmodified lines
2617	mec_hdr->ucode_start_addr_hi >> 2);	2459	mec_hdr->ucode_start_addr_hi >> 2);
2618	}	2460	}
2619	soc21_grbm_select(adev, 0, 0, 0, 0);	2461	soc21_grbm_select(adev, 0, 0, 0, 0);
		2462
		2463	/* reset mec pipe */
		2464	tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
		2465	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
		2466	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
		2467	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
		2468	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
		2469	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
		2470
		2471	/* clear mec pipe reset */
		2472	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
		2473	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
		2474	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
		2475	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
		2476	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2620	}	2477	}
2621		2478
2622	static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)	2479	static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+25−193

@@ -126,6 +126,8 @@ MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); · 125 unmodified lines
126	MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin");	126	MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin");
127	MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin");	127	MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin");
128	MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin");	128	MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin");
		129	MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin");
		130	MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin");
129		131
130	#define mmTCP_CHAN_STEER_0_ARCT 0x0b03	132	#define mmTCP_CHAN_STEER_0_ARCT 0x0b03
131	#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0	133	#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0
@@ -1089,27 +1091,6 @@ static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) · 957 unmodified lines
1089	kfree(adev->gfx.rlc.register_list_format);	1091	kfree(adev->gfx.rlc.register_list_format);
1090	}	1092	}
1091		1093
1092	static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
1093	{
1094	const struct rlc_firmware_header_v2_1 *rlc_hdr;
1095
1096	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
1097	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
1098	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
1099	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
1100	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
1101	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
1102	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
1103	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
1104	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
1105	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
1106	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
1107	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
1108	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
1109	adev->gfx.rlc.reg_list_format_direct_reg_list_length =
1110	le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
1111	}
1112
1113	static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)	1094	static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
1114	{	1095	{
1115	adev->gfx.me_fw_write_wait = false;	1096	adev->gfx.me_fw_write_wait = false;
@@ -1271,9 +1252,6 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, · 155 unmodified lines
1271	{	1252	{
1272	char fw_name[30];	1253	char fw_name[30];
1273	int err;	1254	int err;
1274	struct amdgpu_firmware_info *info = NULL;
1275	const struct common_firmware_header *header = NULL;
1276	const struct gfx_firmware_header_v1_0 *cp_hdr;
1277		1255
1278	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);	1256	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1279	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);	1257	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
@@ -1282,9 +1260,7 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, · 2 unmodified lines
1282	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);	1260	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1283	if (err)	1261	if (err)
1284	goto out;	1262	goto out;
1285	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;	1263	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
1286	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1287	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1288		1264
1289	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);	1265	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1290	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);	1266	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
@@ -1293,9 +1269,7 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, · 2 unmodified lines
1293	err = amdgpu_ucode_validate(adev->gfx.me_fw);	1269	err = amdgpu_ucode_validate(adev->gfx.me_fw);
1294	if (err)	1270	if (err)
1295	goto out;	1271	goto out;
1296	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;	1272	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
1297	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1298	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1299		1273
1300	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);	1274	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1301	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);	1275	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
@@ -1304,37 +1278,12 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, · 2 unmodified lines
1304	err = amdgpu_ucode_validate(adev->gfx.ce_fw);	1278	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1305	if (err)	1279	if (err)
1306	goto out;	1280	goto out;
1307	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;	1281	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
1308	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1309	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1310
1311	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1312	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1313	info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1314	info->fw = adev->gfx.pfp_fw;
1315	header = (const struct common_firmware_header *)info->fw->data;
1316	adev->firmware.fw_size +=
1317	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1318
1319	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1320	info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1321	info->fw = adev->gfx.me_fw;
1322	header = (const struct common_firmware_header *)info->fw->data;
1323	adev->firmware.fw_size +=
1324	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1325
1326	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1327	info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1328	info->fw = adev->gfx.ce_fw;
1329	header = (const struct common_firmware_header *)info->fw->data;
1330	adev->firmware.fw_size +=
1331	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1332	}
1333		1282
1334	out:	1283	out:
1335	if (err) {	1284	if (err) {
1336	dev_err(adev->dev,	1285	dev_err(adev->dev,
1337	"gfx9: Failed to load firmware \"%s\"\n",	1286	"gfx9: Failed to init firmware \"%s\"\n",
1338	fw_name);	1287	fw_name);
1339	release_firmware(adev->gfx.pfp_fw);	1288	release_firmware(adev->gfx.pfp_fw);
1340	adev->gfx.pfp_fw = NULL;	1289	adev->gfx.pfp_fw = NULL;
@@ -1351,11 +1300,7 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, · 10 unmodified lines
1351	{	1300	{
1352	char fw_name[30];	1301	char fw_name[30];
1353	int err;	1302	int err;
1354	struct amdgpu_firmware_info *info = NULL;
1355	const struct common_firmware_header *header = NULL;
1356	const struct rlc_firmware_header_v2_0 *rlc_hdr;	1303	const struct rlc_firmware_header_v2_0 *rlc_hdr;
1357	unsigned int *tmp = NULL;
1358	unsigned int i = 0;
1359	uint16_t version_major;	1304	uint16_t version_major;
1360	uint16_t version_minor;	1305	uint16_t version_minor;
1361	uint32_t smu_version;	1306	uint32_t smu_version;
@@ -1384,92 +1329,17 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, · 22 unmodified lines
1384	if (err)	1329	if (err)
1385	goto out;	1330	goto out;
1386	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);	1331	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
		1332	if (err)
		1333	goto out;
1387	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;	1334	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1388		1335
1389	version_major = le16_to_cpu(rlc_hdr->header.header_version_major);	1336	version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1390	version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);	1337	version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1391	if (version_major == 2 && version_minor == 1)	1338	err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
1392	adev->gfx.rlc.is_rlc_v2_1 = true;
1393
1394	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1395	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1396	adev->gfx.rlc.save_and_restore_offset =
1397	le32_to_cpu(rlc_hdr->save_and_restore_offset);
1398	adev->gfx.rlc.clear_state_descriptor_offset =
1399	le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1400	adev->gfx.rlc.avail_scratch_ram_locations =
1401	le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1402	adev->gfx.rlc.reg_restore_list_size =
1403	le32_to_cpu(rlc_hdr->reg_restore_list_size);
1404	adev->gfx.rlc.reg_list_format_start =
1405	le32_to_cpu(rlc_hdr->reg_list_format_start);
1406	adev->gfx.rlc.reg_list_format_separate_start =
1407	le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1408	adev->gfx.rlc.starting_offsets_start =
1409	le32_to_cpu(rlc_hdr->starting_offsets_start);
1410	adev->gfx.rlc.reg_list_format_size_bytes =
1411	le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1412	adev->gfx.rlc.reg_list_size_bytes =
1413	le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1414	adev->gfx.rlc.register_list_format =
1415	kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1416	adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1417	if (!adev->gfx.rlc.register_list_format) {
1418	err = -ENOMEM;
1419	goto out;
1420	}
1421
1422	tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1423	le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1424	for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1425	adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1426
1427	adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1428
1429	tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1430	le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1431	for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1432	adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1433
1434	if (adev->gfx.rlc.is_rlc_v2_1)
1435	gfx_v9_0_init_rlc_ext_microcode(adev);
1436
1437	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1438	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1439	info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1440	info->fw = adev->gfx.rlc_fw;
1441	header = (const struct common_firmware_header *)info->fw->data;
1442	adev->firmware.fw_size +=
1443	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1444
1445	if (adev->gfx.rlc.is_rlc_v2_1 &&
1446	adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
1447	adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
1448	adev->gfx.rlc.save_restore_list_srm_size_bytes) {
1449	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
1450	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
1451	info->fw = adev->gfx.rlc_fw;
1452	adev->firmware.fw_size +=
1453	ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
1454
1455	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
1456	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
1457	info->fw = adev->gfx.rlc_fw;
1458	adev->firmware.fw_size +=
1459	ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
1460
1461	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
1462	info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
1463	info->fw = adev->gfx.rlc_fw;
1464	adev->firmware.fw_size +=
1465	ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
1466	}
1467	}
1468
1469	out:	1339	out:
1470	if (err) {	1340	if (err) {
1471	dev_err(adev->dev,	1341	dev_err(adev->dev,
1472	"gfx9: Failed to load firmware \"%s\"\n",	1342	"gfx9: Failed to init firmware \"%s\"\n",
1473	fw_name);	1343	fw_name);
1474	release_firmware(adev->gfx.rlc_fw);	1344	release_firmware(adev->gfx.rlc_fw);
1475	adev->gfx.rlc_fw = NULL;	1345	adev->gfx.rlc_fw = NULL;
@@ -1492,35 +1362,34 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, · 16 unmodified lines
1492	{	1362	{
1493	char fw_name[30];	1363	char fw_name[30];
1494	int err;	1364	int err;
1495	struct amdgpu_firmware_info *info = NULL;
1496	const struct common_firmware_header *header = NULL;
1497	const struct gfx_firmware_header_v1_0 *cp_hdr;
1498		1365
1499	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);	1366	if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN))
		1367	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name);
		1368	else
		1369	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
		1370
1500	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);	1371	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1501	if (err)	1372	if (err)
1502	goto out;	1373	goto out;
1503	err = amdgpu_ucode_validate(adev->gfx.mec_fw);	1374	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1504	if (err)	1375	if (err)
1505	goto out;	1376	goto out;
1506	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;	1377	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
1507	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);	1378	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
1508	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1509
1510		1379
1511	if (gfx_v9_0_load_mec2_fw_bin_support(adev)) {	1380	if (gfx_v9_0_load_mec2_fw_bin_support(adev)) {
1512	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);	1381	if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN))
		1382	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name);
		1383	else
		1384	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
		1385
1513	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);	1386	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1514	if (!err) {	1387	if (!err) {
1515	err = amdgpu_ucode_validate(adev->gfx.mec2_fw);	1388	err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1516	if (err)	1389	if (err)
1517	goto out;	1390	goto out;
1518	cp_hdr = (const struct gfx_firmware_header_v1_0 *)	1391	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
1519	adev->gfx.mec2_fw->data;	1392	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
1520	adev->gfx.mec2_fw_version =
1521	le32_to_cpu(cp_hdr->header.ucode_version);
1522	adev->gfx.mec2_feature_version =
1523	le32_to_cpu(cp_hdr->ucode_feature_version);
1524	} else {	1393	} else {
1525	err = 0;	1394	err = 0;
1526	adev->gfx.mec2_fw = NULL;	1395	adev->gfx.mec2_fw = NULL;
@@ -1530,49 +1399,12 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, · 3 unmodified lines
1530	adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;	1399	adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
1531	}	1400	}
1532		1401
1533	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1534	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1535	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1536	info->fw = adev->gfx.mec_fw;
1537	header = (const struct common_firmware_header *)info->fw->data;
1538	cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
1539	adev->firmware.fw_size +=
1540	ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
1541
1542	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
1543	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
1544	info->fw = adev->gfx.mec_fw;
1545	adev->firmware.fw_size +=
1546	ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
1547
1548	if (adev->gfx.mec2_fw) {
1549	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1550	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1551	info->fw = adev->gfx.mec2_fw;
1552	header = (const struct common_firmware_header *)info->fw->data;
1553	cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
1554	adev->firmware.fw_size +=
1555	ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
1556
1557	/* TODO: Determine if MEC2 JT FW loading can be removed
1558	for all GFX V9 asic and above */
1559	if (gfx_v9_0_load_mec2_fw_bin_support(adev)) {
1560	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
1561	info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
1562	info->fw = adev->gfx.mec2_fw;
1563	adev->firmware.fw_size +=
1564	ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
1565	PAGE_SIZE);
1566	}
1567	}
1568	}
1569
1570	out:	1402	out:
1571	gfx_v9_0_check_if_need_gfxoff(adev);	1403	gfx_v9_0_check_if_need_gfxoff(adev);
1572	gfx_v9_0_check_fw_write_wait(adev);	1404	gfx_v9_0_check_fw_write_wait(adev);
1573	if (err) {	1405	if (err) {
1574	dev_err(adev->dev,	1406	dev_err(adev->dev,
1575	"gfx9: Failed to load firmware \"%s\"\n",	1407	"gfx9: Failed to init firmware \"%s\"\n",
1576	fw_name);	1408	fw_name);
1577	release_firmware(adev->gfx.mec_fw);	1409	release_firmware(adev->gfx.mec_fw);
1578	adev->gfx.mec_fw = NULL;	1410	adev->gfx.mec_fw = NULL;

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c+108−0

@@ -576,6 +576,111 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev) · 575 unmodified lines
576	}	576	}
577	}	577	}
578		578
		579	static void gfxhub_v2_1_save_regs(struct amdgpu_device *adev)
		580	{
		581	int i;
		582	adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
		583	adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
		584	adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL);
		585	adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32);
		586	adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32);
		587	adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
		588	adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2);
		589	adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3);
		590	adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4);
		591	adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32);
		592	adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32);
		593	adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG);
		594	adev->gmc.VM_L2_MM_GROUP_RT_CLASSES = RREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES);
		595	adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID);
		596	adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2 = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2);
		597	adev->gmc.VM_L2_CACHE_PARITY_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL);
		598	adev->gmc.VM_L2_IH_LOG_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL);
		599
		600	for (i = 0; i <= 15; i++) {
		601	adev->gmc.VM_CONTEXT_CNTL[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i);
		602	adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2);
		603	adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2);
		604	adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2);
		605	adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2);
		606	adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2);
		607	adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2);
		608	}
		609
		610	adev->gmc.MC_VM_MX_L1_TLB_CNTL = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
		611	}
		612
		613	static void gfxhub_v2_1_restore_regs(struct amdgpu_device *adev)
		614	{
		615	int i;
		616	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, adev->gmc.VM_L2_CNTL);
		617	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, adev->gmc.VM_L2_CNTL2);
		618	WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL, adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL);
		619	WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32);
		620	WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32);
		621	WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL);
		622	WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2);
		623	WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3);
		624	WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4);
		625	WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32);
		626	WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32);
		627	WREG32_SOC15(GC, 0, mmGCVM_DEBUG, adev->gmc.VM_DEBUG);
		628	WREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES, adev->gmc.VM_L2_MM_GROUP_RT_CLASSES);
		629	WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID);
		630	WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2);
		631	WREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL, adev->gmc.VM_L2_CACHE_PARITY_CNTL);
		632	WREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL, adev->gmc.VM_L2_IH_LOG_CNTL);
		633
		634	for (i = 0; i <= 15; i++) {
		635	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, adev->gmc.VM_CONTEXT_CNTL[i]);
		636	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i]);
		637	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i]);
		638	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i]);
		639	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i]);
		640	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i]);
		641	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i]);
		642	}
		643
		644	WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, adev->gmc.vram_start >> 24);
		645	WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, adev->gmc.vram_end >> 24);
		646	WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, adev->gmc.MC_VM_MX_L1_TLB_CNTL);
		647	}
		648
		649	static void gfxhub_v2_1_halt(struct amdgpu_device *adev)
		650	{
		651	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
		652	int i;
		653	uint32_t tmp;
		654	int time = 1000;
		655
		656	gfxhub_v2_1_set_fault_enable_default(adev, false);
		657
		658	for (i = 0; i <= 14; i++) {
		659	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
		660	i * hub->ctx_addr_distance, ~0);
		661	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
		662	i * hub->ctx_addr_distance, ~0);
		663	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
		664	i * hub->ctx_addr_distance,
		665	0);
		666	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
		667	i * hub->ctx_addr_distance,
		668	0);
		669	}
		670	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
		671	while ((tmp & (GRBM_STATUS2__EA_BUSY_MASK \|
		672	GRBM_STATUS2__EA_LINK_BUSY_MASK)) != 0 &&
		673	time) {
		674	udelay(100);
		675	time--;
		676	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
		677	}
		678
		679	if (!time) {
		680	DRM_WARN("failed to wait for GRBM(EA) idle\n");
		681	}
		682	}
		683
579	const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {	684	const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
580	.get_fb_location = gfxhub_v2_1_get_fb_location,	685	.get_fb_location = gfxhub_v2_1_get_fb_location,
581	.get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,	686	.get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,
@@ -586,4 +691,7 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { · 4 unmodified lines
586	.init = gfxhub_v2_1_init,	691	.init = gfxhub_v2_1_init,
587	.get_xgmi_info = gfxhub_v2_1_get_xgmi_info,	692	.get_xgmi_info = gfxhub_v2_1_get_xgmi_info,
588	.utcl2_harvest = gfxhub_v2_1_utcl2_harvest,	693	.utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
		694	.mode2_save_regs = gfxhub_v2_1_save_regs,
		695	.mode2_restore_regs = gfxhub_v2_1_restore_regs,
		696	.halt = gfxhub_v2_1_halt,
589	};	697	};

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c+511−0

@@ -0,0 +1,511 @@
	1	/*
	2	* Copyright 2022 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#include "amdgpu.h"
	25	#include "gfxhub_v3_0_3.h"
	26
	27	#include "gc/gc_11_0_3_offset.h"
	28	#include "gc/gc_11_0_3_sh_mask.h"
	29	#include "navi10_enum.h"
	30	#include "soc15_common.h"
	31
	32	#define regGCVM_L2_CNTL3_DEFAULT 0x80100007
	33	#define regGCVM_L2_CNTL4_DEFAULT 0x000000c1
	34	#define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0
	35
	36	static const char *gfxhub_client_ids[] = {
	37	"CB/DB",
	38	"Reserved",
	39	"GE1",
	40	"GE2",
	41	"CPF",
	42	"CPC",
	43	"CPG",
	44	"RLC",
	45	"TCP",
	46	"SQC (inst)",
	47	"SQC (data)",
	48	"SQG",
	49	"Reserved",
	50	"SDMA0",
	51	"SDMA1",
	52	"GCR",
	53	"SDMA2",
	54	"SDMA3",
	55	};
	56
	57	static uint32_t gfxhub_v3_0_3_get_invalidate_req(unsigned int vmid,
	58	uint32_t flush_type)
	59	{
	60	u32 req = 0;
	61
	62	/* invalidate using legacy mode on vmid*/
	63	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
	64	PER_VMID_INVALIDATE_REQ, 1 << vmid);
	65	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
	66	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
	67	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
	68	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
	69	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
	70	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
	71	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
	72	CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
	73
	74	return req;
	75	}
	76
	77	static void
	78	gfxhub_v3_0_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
	79	uint32_t status)
	80	{
	81	u32 cid = REG_GET_FIELD(status,
	82	GCVM_L2_PROTECTION_FAULT_STATUS, CID);
	83
	84	dev_err(adev->dev,
	85	"GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
	86	status);
	87	dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
	88	cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
	89	cid);
	90	dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
	91	REG_GET_FIELD(status,
	92	GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
	93	dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
	94	REG_GET_FIELD(status,
	95	GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
	96	dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
	97	REG_GET_FIELD(status,
	98	GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
	99	dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
	100	REG_GET_FIELD(status,
	101	GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
	102	dev_err(adev->dev, "\t RW: 0x%lx\n",
	103	REG_GET_FIELD(status,
	104	GCVM_L2_PROTECTION_FAULT_STATUS, RW));
	105	}
	106
	107	static u64 gfxhub_v3_0_3_get_fb_location(struct amdgpu_device *adev)
	108	{
	109	u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);
	110
	111	base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
	112	base <<= 24;
	113
	114	return base;
	115	}
	116
	117	static u64 gfxhub_v3_0_3_get_mc_fb_offset(struct amdgpu_device *adev)
	118	{
	119	return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;
	120	}
	121
	122	static void gfxhub_v3_0_3_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
	123	uint64_t page_table_base)
	124	{
	125	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
	126
	127	WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
	128	hub->ctx_addr_distance * vmid,
	129	lower_32_bits(page_table_base));
	130
	131	WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
	132	hub->ctx_addr_distance * vmid,
	133	upper_32_bits(page_table_base));
	134	}
	135
	136	static void gfxhub_v3_0_3_init_gart_aperture_regs(struct amdgpu_device *adev)
	137	{
	138	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
	139
	140	gfxhub_v3_0_3_setup_vm_pt_regs(adev, 0, pt_base);
	141
	142	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
	143	(u32)(adev->gmc.gart_start >> 12));
	144	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
	145	(u32)(adev->gmc.gart_start >> 44));
	146
	147	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
	148	(u32)(adev->gmc.gart_end >> 12));
	149	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
	150	(u32)(adev->gmc.gart_end >> 44));
	151	}
	152
	153	static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev)
	154	{
	155	uint64_t value;
	156
	157	/* Disable AGP. */
	158	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
	159	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0);
	160	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FFFFFF);
	161
	162	/* Program the system aperture low logical page number. */
	163	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
	164	adev->gmc.vram_start >> 18);
	165	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
	166	adev->gmc.vram_end >> 18);
	167
	168	/* Set default page address. */
	169	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
	170	+ adev->vm_manager.vram_base_offset;
	171	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
	172	(u32)(value >> 12));
	173	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
	174	(u32)(value >> 44));
	175
	176	/* Program "protection fault". */
	177	WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
	178	(u32)(adev->dummy_page_addr >> 12));
	179	WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
	180	(u32)((u64)adev->dummy_page_addr >> 44));
	181
	182	WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
	183	ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
	184	}
	185
	186
	187	static void gfxhub_v3_0_3_init_tlb_regs(struct amdgpu_device *adev)
	188	{
	189	uint32_t tmp;
	190
	191	/* Setup TLB control */
	192	tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
	193
	194	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
	195	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
	196	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
	197	ENABLE_ADVANCED_DRIVER_MODEL, 1);
	198	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
	199	SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
	200	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
	201	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
	202	MTYPE, MTYPE_UC); /* UC, uncached */
	203
	204	WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
	205	}
	206
	207	static void gfxhub_v3_0_3_init_cache_regs(struct amdgpu_device *adev)
	208	{
	209	uint32_t tmp;
	210
	211	/* These registers are not accessible to VF-SRIOV.
	212	* The PF will program them instead.
	213	*/
	214	if (amdgpu_sriov_vf(adev))
	215	return;
	216
	217	/* Setup L2 cache */
	218	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
	219	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
	220	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
	221	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
	222	ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
	223	/* XXX for emulation, Refer to closed source code.*/
	224	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
	225	L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
	226	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
	227	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
	228	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
	229	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
	230
	231	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
	232	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
	233	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
	234	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
	235
	236	tmp = regGCVM_L2_CNTL3_DEFAULT;
	237	if (adev->gmc.translate_further) {
	238	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
	239	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
	240	L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
	241	} else {
	242	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
	243	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
	244	L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
	245	}
	246	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
	247
	248	tmp = regGCVM_L2_CNTL4_DEFAULT;
	249	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
	250	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
	251	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
	252
	253	tmp = regGCVM_L2_CNTL5_DEFAULT;
	254	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
	255	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
	256	}
	257
	258	static void gfxhub_v3_0_3_enable_system_domain(struct amdgpu_device *adev)
	259	{
	260	uint32_t tmp;
	261
	262	tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
	263	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
	264	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
	265	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
	266	RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
	267	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
	268	}
	269
	270	static void gfxhub_v3_0_3_disable_identity_aperture(struct amdgpu_device *adev)
	271	{
	272	/* These registers are not accessible to VF-SRIOV.
	273	* The PF will program them instead.
	274	*/
	275	if (amdgpu_sriov_vf(adev))
	276	return;
	277
	278	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
	279	0xFFFFFFFF);
	280	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
	281	0x0000000F);
	282
	283	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
	284	0);
	285	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
	286	0);
	287
	288	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
	289	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
	290
	291	}
	292
	293	static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev)
	294	{
	295	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
	296	int i;
	297	uint32_t tmp;
	298
	299	for (i = 0; i <= 14; i++) {
	300	tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
	301	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
	302	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
	303	adev->vm_manager.num_level);
	304	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
	305	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	306	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
	307	DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	308	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
	309	PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	310	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
	311	VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	312	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
	313	READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	314	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
	315	WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	316	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
	317	EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	318	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
	319	PAGE_TABLE_BLOCK_SIZE,
	320	adev->vm_manager.block_size - 9);
	321	/* Send no-retry XNACK on fault to suppress VM fault storm. */
	322	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
	323	RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
	324	!amdgpu_noretry);
	325	WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL,
	326	i * hub->ctx_distance, tmp);
	327	WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
	328	i * hub->ctx_addr_distance, 0);
	329	WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
	330	i * hub->ctx_addr_distance, 0);
	331	WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
	332	i * hub->ctx_addr_distance,
	333	lower_32_bits(adev->vm_manager.max_pfn - 1));
	334	WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
	335	i * hub->ctx_addr_distance,
	336	upper_32_bits(adev->vm_manager.max_pfn - 1));
	337	}
	338
	339	hub->vm_cntx_cntl = tmp;
	340	}
	341
	342	static void gfxhub_v3_0_3_program_invalidation(struct amdgpu_device *adev)
	343	{
	344	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
	345	unsigned i;
	346
	347	for (i = 0 ; i < 18; ++i) {
	348	WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
	349	i * hub->eng_addr_distance, 0xffffffff);
	350	WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
	351	i * hub->eng_addr_distance, 0x1f);
	352	}
	353	}
	354
	355	static int gfxhub_v3_0_3_gart_enable(struct amdgpu_device *adev)
	356	{
	357	if (amdgpu_sriov_vf(adev)) {
	358	/*
	359	* GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
	360	* VF copy registers so vbios post doesn't program them, for
	361	* SRIOV driver need to program them
	362	*/
	363	WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE,
	364	adev->gmc.vram_start >> 24);
	365	WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP,
	366	adev->gmc.vram_end >> 24);
	367	}
	368
	369	/* GART Enable. */
	370	gfxhub_v3_0_3_init_gart_aperture_regs(adev);
	371	gfxhub_v3_0_3_init_system_aperture_regs(adev);
	372	gfxhub_v3_0_3_init_tlb_regs(adev);
	373	gfxhub_v3_0_3_init_cache_regs(adev);
	374
	375	gfxhub_v3_0_3_enable_system_domain(adev);
	376	gfxhub_v3_0_3_disable_identity_aperture(adev);
	377	gfxhub_v3_0_3_setup_vmid_config(adev);
	378	gfxhub_v3_0_3_program_invalidation(adev);
	379
	380	return 0;
	381	}
	382
	383	static void gfxhub_v3_0_3_gart_disable(struct amdgpu_device *adev)
	384	{
	385	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
	386	u32 tmp;
	387	u32 i;
	388
	389	/* Disable all tables */
	390	for (i = 0; i < 16; i++)
	391	WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL,
	392	i * hub->ctx_distance, 0);
	393
	394	/* Setup TLB control */
	395	tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
	396	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
	397	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
	398	ENABLE_ADVANCED_DRIVER_MODEL, 0);
	399	WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
	400
	401	/* Setup L2 cache */
	402	WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
	403	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0);
	404	}
	405
	406	/**
	407	* gfxhub_v3_0_3_set_fault_enable_default - update GART/VM fault handling
	408	*
	409	* @adev: amdgpu_device pointer
	410	* @value: true redirects VM faults to the default page
	411	*/
	412	static void gfxhub_v3_0_3_set_fault_enable_default(struct amdgpu_device *adev,
	413	bool value)
	414	{
	415	u32 tmp;
	416
	417	/* These registers are not accessible to VF-SRIOV.
	418	* The PF will program them instead.
	419	*/
	420	if (amdgpu_sriov_vf(adev))
	421	return;
	422
	423	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
	424	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	425	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	426	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	427	PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	428	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	429	PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	430	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	431	PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	432	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	433	TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
	434	value);
	435	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	436	NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	437	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	438	DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	439	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	440	VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	441	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	442	READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	443	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	444	WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	445	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	446	EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	447	if (!value) {
	448	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	449	CRASH_ON_NO_RETRY_FAULT, 1);
	450	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
	451	CRASH_ON_RETRY_FAULT, 1);
	452	}
	453	WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
	454	}
	455
	456	static const struct amdgpu_vmhub_funcs gfxhub_v3_0_3_vmhub_funcs = {
	457	.print_l2_protection_fault_status = gfxhub_v3_0_3_print_l2_protection_fault_status,
	458	.get_invalidate_req = gfxhub_v3_0_3_get_invalidate_req,
	459	};
	460
	461	static void gfxhub_v3_0_3_init(struct amdgpu_device *adev)
	462	{
	463	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
	464
	465	hub->ctx0_ptb_addr_lo32 =
	466	SOC15_REG_OFFSET(GC, 0,
	467	regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
	468	hub->ctx0_ptb_addr_hi32 =
	469	SOC15_REG_OFFSET(GC, 0,
	470	regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
	471	hub->vm_inv_eng0_sem =
	472	SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);
	473	hub->vm_inv_eng0_req =
	474	SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);
	475	hub->vm_inv_eng0_ack =
	476	SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);
	477	hub->vm_context0_cntl =
	478	SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);
	479	hub->vm_l2_pro_fault_status =
	480	SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS);
	481	hub->vm_l2_pro_fault_cntl =
	482	SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
	483
	484	hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL;
	485	hub->ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
	486	regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
	487	hub->eng_distance = regGCVM_INVALIDATE_ENG1_REQ -
	488	regGCVM_INVALIDATE_ENG0_REQ;
	489	hub->eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
	490	regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
	491
	492	hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK \|
	493	GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK \|
	494	GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK \|
	495	GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK \|
	496	GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK \|
	497	GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK \|
	498	GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
	499
	500	hub->vmhub_funcs = &gfxhub_v3_0_3_vmhub_funcs;
	501	}
	502
	503	const struct amdgpu_gfxhub_funcs gfxhub_v3_0_3_funcs = {
	504	.get_fb_location = gfxhub_v3_0_3_get_fb_location,
	505	.get_mc_fb_offset = gfxhub_v3_0_3_get_mc_fb_offset,
	506	.setup_vm_pt_regs = gfxhub_v3_0_3_setup_vm_pt_regs,
	507	.gart_enable = gfxhub_v3_0_3_gart_enable,
	508	.gart_disable = gfxhub_v3_0_3_gart_disable,
	509	.set_fault_enable_default = gfxhub_v3_0_3_set_fault_enable_default,
	510	.init = gfxhub_v3_0_3_init,
	511	};

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.h+29−0

@@ -0,0 +1,29 @@
	1	/*
	2	* Copyright 2022 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __GFXHUB_V3_0_3_H__
	25	#define __GFXHUB_V3_0_3_H__
	26
	27	extern const struct amdgpu_gfxhub_funcs gfxhub_v3_0_3_funcs;
	28
	29	#endif

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c+16−3

 #include "soc15_common.h"
 #include "nbio_v4_3.h"
 #include "gfxhub_v3_0.h"
+#include "gfxhub_v3_0_3.h"
 #include "mmhub_v3_0.h"
 #include "mmhub_v3_0_1.h"
 #include "mmhub_v3_0_2.h"
 	/* Issue additional private vm invalidation to MMHUB */
 	if ((vmhub != AMDGPU_GFXHUB_0) &&
-	    (hub->vm_l2_bank_select_reserved_cid2)) {
+	    (hub->vm_l2_bank_select_reserved_cid2) &&
+		!amdgpu_sriov_vf(adev)) {
 		inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
 		/* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */
 		inv_req |= (1 << 25);
 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 {
-	adev->gfxhub.funcs = &gfxhub_v3_0_funcs;
+	switch (adev->ip_versions[GC_HWIP][0]) {
+	case IP_VERSION(11, 0, 3):
+		adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs;
+		break;
+	default:
+		adev->gfxhub.funcs = &gfxhub_v3_0_funcs;
+		break;
+	}
 }
 static int gmc_v11_0_early_init(void *handle)
 	amdgpu_gmc_gart_location(adev, mc);
 	/* base offset of vram pages */
-	adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);
+	if (amdgpu_sriov_vf(adev))
+		adev->vm_manager.vram_base_offset = 0;
+	else
+		adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);
 }
 /**
 	case IP_VERSION(11, 0, 0):
 	case IP_VERSION(11, 0, 1):
 	case IP_VERSION(11, 0, 2):
+	case IP_VERSION(11, 0, 3):
 		adev->num_vmhubs = 2;
 		/*
 		 * To fulfill 4-level page support,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c+23−3

@@ -105,7 +105,13 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev, · 104 unmodified lines
105	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,	105	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
106	RB_USED_INT_THRESHOLD, threshold);	106	RB_USED_INT_THRESHOLD, threshold);
107		107
108	WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl);	108	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
		109	if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
		110	return;
		111	} else {
		112	WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl);
		113	}
		114
109	WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl);	115	WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl);
110	}	116	}
111		117
@@ -132,7 +138,13 @@ static int ih_v6_0_toggle_ring_interrupts(struct amdgpu_device *adev, · 20 unmodified lines
132	/* enable_intr field is only valid in ring0 */	138	/* enable_intr field is only valid in ring0 */
133	if (ih == &adev->irq.ih)	139	if (ih == &adev->irq.ih)
134	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));	140	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
135	WREG32(ih_regs->ih_rb_cntl, tmp);	141
		142	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
		143	if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
		144	return -ETIMEDOUT;
		145	} else {
		146	WREG32(ih_regs->ih_rb_cntl, tmp);
		147	}
136		148
137	if (enable) {	149	if (enable) {
138	ih->enabled = true;	150	ih->enabled = true;
@@ -242,7 +254,15 @@ static int ih_v6_0_enable_ring(struct amdgpu_device *adev, · 103 unmodified lines
242	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);	254	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
243	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);	255	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
244	}	256	}
245	WREG32(ih_regs->ih_rb_cntl, tmp);	257
		258	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
		259	if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
		260	DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
		261	return -ETIMEDOUT;
		262	}
		263	} else {
		264	WREG32(ih_regs->ih_rb_cntl, tmp);
		265	}
246		266
247	if (ih == &adev->irq.ih) {	267	if (ih == &adev->irq.ih) {
248	/* set the ih ring 0 writeback address whether it's enabled or not */	268	/* set the ih ring 0 writeback address whether it's enabled or not */

drivers/gpu/drm/amd/amdgpu/imu_v11_0.c+6−0

 #include "amdgpu_imu.h"
 #include "amdgpu_dpm.h"
+#include "imu_v11_0_3.h"
 #include "gc/gc_11_0_0_offset.h"
 #include "gc/gc_11_0_0_sh_mask.h"
 MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_0_1_imu.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_0_2_imu.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_3_imu.bin");
 static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
 {
 		program_imu_rlc_ram(adev, imu_rlc_ram_golden_11_0_2,
 				(const u32)ARRAY_SIZE(imu_rlc_ram_golden_11_0_2));
 		break;
+	case IP_VERSION(11, 0, 3):
+		imu_v11_0_3_program_rlc_ram(adev);
+		break;
 	default:
 		BUG();
 		break;

drivers/gpu/drm/amd/amdgpu/imu_v11_0_3.c+145−0

@@ -0,0 +1,145 @@
	1	/*
	2	* Copyright 2022 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "amdgpu.h"
	24	#include "amdgpu_imu.h"
	25	#include "imu_v11_0_3.h"
	26
	27	#include "gc/gc_11_0_3_offset.h"
	28	#include "gc/gc_11_0_3_sh_mask.h"
	29
	30	static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11_0_3[] = {
	31	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000),
	32	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000),
	33	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000),
	34	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
	35	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS, 0x003f3fff, 0xe0000000),
	36	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000),
	37	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000),
	38	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000),
	39	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000),
	40	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000),
	41	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC, 0x00000017, 0xe0000000),
	42	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_ENABLE, 0x00000001, 0xe0000000),
	43	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_CREDITS, 0x003f3fbf, 0xe0000000),
	44	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE0, 0x10200800, 0xe0000000),
	45	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE1, 0x00000088, 0xe0000000),
	46	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE0, 0x1d041040, 0xe0000000),
	47	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE1, 0x80000000, 0xe0000000),
	48	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_IO_PRIORITY, 0x88888888, 0xe0000000),
	49	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MAM_CTRL, 0x0000d800, 0xe0000000),
	50	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ARB_FINAL, 0x000007ff, 0xe0000000),
	51	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_DRAM_PAGE_BURST, 0x20080200, 0xe0000000),
	52	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ENABLE, 0x00000001, 0xe0000000),
	53	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
	54	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000),
	55	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0x000fffff, 0xe0000000),
	56	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MISC, 0x0c48bff0, 0xe0000000),
	57	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SA_UNIT_DISABLE, 0x00fffc01, 0xe0000000),
	58	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_PRIM_CONFIG, 0x000fffe1, 0xe0000000),
	59	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0xffffff01, 0xe0000000),
	60	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0x40000000),
	61	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0x42000000),
	62	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x44000000),
	63	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x46000000),
	64	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x48000000),
	65	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x4A000000),
	66	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCGTS_TCC_DISABLE, 0x00000001, 0x00000000),
	67	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_RATE_CONFIG, 0x00000001, 0x00000000),
	68	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_EDC_CONFIG, 0x00000001, 0x00000000),
	69	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0xe0000000),
	70	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0xe0000000),
	71	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0xe0000000),
	72	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0xe0000000),
	73	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x000005ff, 0xe0000000),
	74	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0xe0000000),
	75	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x000065ff, 0xe0000000),
	76	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000),
	77	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0xe0000000),
	78	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000),
	79	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0xe0000000),
	80	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x00000fff, 0xe0000000),
	81	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000),
	82	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000551, 0xe0000000),
	83	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
	84	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0xe0000000),
	85	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
	86	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0xe0000000),
	87	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000),
	88	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000),
	89	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000001, 0xe0000000),
	90	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000),
	91	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000444, 0xe0000000),
	92	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x54105410, 0xe0000000),
	93	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_2, 0x76323276, 0xe0000000),
	94	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000244, 0xe0000000),
	95	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCUTCL2_HARVEST_BYPASS_GROUPS, 0x00000006, 0xe0000000),
	96	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000),
	97	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0xe0000000),
	98	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000),
	99	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000),
	100	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
	101	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0xe0000000),
	102	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0xe0000000),
	103	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0xe0000000),
	104	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0xe0000000),
	105	};
	106
	107	static void program_rlc_ram_register_setting(struct amdgpu_device *adev,
	108	const struct imu_rlc_ram_golden *regs,
	109	const u32 array_size)
	110	{
	111	const struct imu_rlc_ram_golden *entry;
	112	u32 reg, data;
	113	int i;
	114
	115	for (i = 0; i < array_size; ++i) {
	116	entry = &regs[i];
	117	reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
	118	reg \|= entry->addr_mask;
	119
	120	data = entry->data;
	121	if (entry->reg == regGCMC_VM_AGP_BASE)
	122	data = 0x00ffffff;
	123	else if (entry->reg == regGCMC_VM_AGP_TOP)
	124	data = 0x0;
	125	else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE)
	126	data = adev->gmc.vram_start >> 24;
	127	else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP)
	128	data = adev->gmc.vram_end >> 24;
	129
	130	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);
	131	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg);
	132	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data);
	133	}
	134	//Indicate the latest entry
	135	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);
	136	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0);
	137	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0);
	138	}
	139
	140	void imu_v11_0_3_program_rlc_ram(struct amdgpu_device *adev)
	141	{
	142	program_rlc_ram_register_setting(adev,
	143	imu_rlc_ram_golden_11_0_3,
	144	(const u32)ARRAY_SIZE(imu_rlc_ram_golden_11_0_3));
	145	}

drivers/gpu/drm/amd/amdgpu/imu_v11_0_3.h+29−0

@@ -0,0 +1,29 @@
	1	/*
	2	* Copyright 2022 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __IMU_V11_0_3_H__
	25	#define __IMU_V11_0_3_H__
	26
	27	void imu_v11_0_3_program_rlc_ram(struct amdgpu_device *adev);
	28
	29	#endif

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c+11−0

 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
 static int mes_v11_0_hw_fini(void *handle);
 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
 	mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 	mes_add_queue_pkt.gds_size = input->queue_size;
+	if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) &&
+		  (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) &&
+		  (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3))))
+		mes_add_queue_pkt.trap_en = 1;
+	/* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
+	mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
+	mes_add_queue_pkt.gds_size = input->queue_size;
 	return mes_v11_0_submit_pkt_and_poll_completion(mes,
 			&mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 			offsetof(union MESAPI__ADD_QUEUE, api_status));

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c+5−5

 	uint64_t value;
 	uint32_t tmp;
-	/* Disable AGP. */
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
-	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF);
 	if (!amdgpu_sriov_vf(adev)) {
 		/*
 		 * the new L1 policy will block SRIOV guest from writing
 		 * these regs, and they will be programed at host.
 		 * so skip programing these regs.
 		 */
+		/* Disable AGP. */
+		WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
+		WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
+		WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF);
 		/* Program the system aperture low logical page number. */
 		WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 			     adev->gmc.vram_start >> 18);

drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h+140−0

@@ -0,0 +1,140 @@
	1	/*
	2	* Copyright 2022 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __MMSCH_V4_0_H__
	25	#define __MMSCH_V4_0_H__
	26
	27	#include "amdgpu_vcn.h"
	28
	29	#define MMSCH_VERSION_MAJOR 4
	30	#define MMSCH_VERSION_MINOR 0
	31	#define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 \| MMSCH_VERSION_MINOR)
	32
	33	#define RB_ENABLED (1 << 0)
	34	#define RB4_ENABLED (1 << 1)
	35	#define MMSCH_DOORBELL_OFFSET 0x8
	36
	37	#define MMSCH_VF_ENGINE_STATUS__PASS 0x1
	38
	39	#define MMSCH_VF_MAILBOX_RESP__OK 0x1
	40	#define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2
	41
	42	enum mmsch_v4_0_command_type {
	43	MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
	44	MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
	45	MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
	46	MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
	47	MMSCH_COMMAND__END = 0xf
	48	};
	49
	50	struct mmsch_v4_0_table_info {
	51	uint32_t init_status;
	52	uint32_t table_offset;
	53	uint32_t table_size;
	54	};
	55
	56	struct mmsch_v4_0_init_header {
	57	uint32_t version;
	58	uint32_t total_size;
	59	struct mmsch_v4_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES];
	60	struct mmsch_v4_0_table_info jpegdec;
	61	};
	62
	63	struct mmsch_v4_0_cmd_direct_reg_header {
	64	uint32_t reg_offset : 28;
	65	uint32_t command_type : 4;
	66	};
	67
	68	struct mmsch_v4_0_cmd_indirect_reg_header {
	69	uint32_t reg_offset : 20;
	70	uint32_t reg_idx_space : 8;
	71	uint32_t command_type : 4;
	72	};
	73
	74	struct mmsch_v4_0_cmd_direct_write {
	75	struct mmsch_v4_0_cmd_direct_reg_header cmd_header;
	76	uint32_t reg_value;
	77	};
	78
	79	struct mmsch_v4_0_cmd_direct_read_modify_write {
	80	struct mmsch_v4_0_cmd_direct_reg_header cmd_header;
	81	uint32_t write_data;
	82	uint32_t mask_value;
	83	};
	84
	85	struct mmsch_v4_0_cmd_direct_polling {
	86	struct mmsch_v4_0_cmd_direct_reg_header cmd_header;
	87	uint32_t mask_value;
	88	uint32_t wait_value;
	89	};
	90
	91	struct mmsch_v4_0_cmd_end {
	92	struct mmsch_v4_0_cmd_direct_reg_header cmd_header;
	93	};
	94
	95	struct mmsch_v4_0_cmd_indirect_write {
	96	struct mmsch_v4_0_cmd_indirect_reg_header cmd_header;
	97	uint32_t reg_value;
	98	};
	99
	100	#define MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
	101	size = sizeof(struct mmsch_v4_0_cmd_direct_read_modify_write); \
	102	size_dw = size / 4; \
	103	direct_rd_mod_wt.cmd_header.reg_offset = reg; \
	104	direct_rd_mod_wt.mask_value = mask; \
	105	direct_rd_mod_wt.write_data = data; \
	106	memcpy((void *)table_loc, &direct_rd_mod_wt, size); \
	107	table_loc += size_dw; \
	108	table_size += size_dw; \
	109	}
	110
	111	#define MMSCH_V4_0_INSERT_DIRECT_WT(reg, value) { \
	112	size = sizeof(struct mmsch_v4_0_cmd_direct_write); \
	113	size_dw = size / 4; \
	114	direct_wt.cmd_header.reg_offset = reg; \
	115	direct_wt.reg_value = value; \
	116	memcpy((void *)table_loc, &direct_wt, size); \
	117	table_loc += size_dw; \
	118	table_size += size_dw; \
	119	}
	120
	121	#define MMSCH_V4_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
	122	size = sizeof(struct mmsch_v4_0_cmd_direct_polling); \
	123	size_dw = size / 4; \
	124	direct_poll.cmd_header.reg_offset = reg; \
	125	direct_poll.mask_value = mask; \
	126	direct_poll.wait_value = wait; \
	127	memcpy((void *)table_loc, &direct_poll, size); \
	128	table_loc += size_dw; \
	129	table_size += size_dw; \
	130	}
	131
	132	#define MMSCH_V4_0_INSERT_END() { \
	133	size = sizeof(struct mmsch_v4_0_cmd_end); \
	134	size_dw = size / 4; \
	135	memcpy((void *)table_loc, &end, size); \
	136	table_loc += size_dw; \
	137	table_size += size_dw; \
	138	}
	139
	140	#endif

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c+1−0

@@ -290,6 +290,7 @@ flr_done: · 289 unmodified lines
290	reset_context.method = AMD_RESET_METHOD_NONE;	290	reset_context.method = AMD_RESET_METHOD_NONE;
291	reset_context.reset_req_dev = adev;	291	reset_context.reset_req_dev = adev;
292	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);	292	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
		293	clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
293		294
294	amdgpu_device_gpu_recover(adev, NULL, &reset_context);	295	amdgpu_device_gpu_recover(adev, NULL, &reset_context);
295	}	296	}

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c+1−0

@@ -317,6 +317,7 @@ flr_done: · 316 unmodified lines
317	reset_context.method = AMD_RESET_METHOD_NONE;	317	reset_context.method = AMD_RESET_METHOD_NONE;
318	reset_context.reset_req_dev = adev;	318	reset_context.reset_req_dev = adev;
319	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);	319	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
		320	clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
320		321
321	amdgpu_device_gpu_recover(adev, NULL, &reset_context);	322	amdgpu_device_gpu_recover(adev, NULL, &reset_context);
322	}	323	}

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c+1−0

@@ -529,6 +529,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work) · 528 unmodified lines
529	reset_context.method = AMD_RESET_METHOD_NONE;	529	reset_context.method = AMD_RESET_METHOD_NONE;
530	reset_context.reset_req_dev = adev;	530	reset_context.reset_req_dev = adev;
531	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);	531	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
		532	clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
532		533
533	amdgpu_device_gpu_recover(adev, NULL, &reset_context);	534	amdgpu_device_gpu_recover(adev, NULL, &reset_context);
534	}	535	}

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c+44−0

@@ -488,3 +488,47 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = { · 487 unmodified lines
488	.get_rom_offset = nbio_v4_3_get_rom_offset,	488	.get_rom_offset = nbio_v4_3_get_rom_offset,
489	.program_aspm = nbio_v4_3_program_aspm,	489	.program_aspm = nbio_v4_3_program_aspm,
490	};	490	};
		491
		492
		493	static void nbio_v4_3_sriov_ih_doorbell_range(struct amdgpu_device *adev,
		494	bool use_doorbell, int doorbell_index)
		495	{
		496	}
		497
		498	static void nbio_v4_3_sriov_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
		499	bool use_doorbell, int doorbell_index,
		500	int doorbell_size)
		501	{
		502	}
		503
		504	static void nbio_v4_3_sriov_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
		505	int doorbell_index, int instance)
		506	{
		507	}
		508
		509	static void nbio_v4_3_sriov_gc_doorbell_init(struct amdgpu_device *adev)
		510	{
		511	}
		512
		513	const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs = {
		514	.get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
		515	.get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
		516	.get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset,
		517	.get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset,
		518	.get_rev_id = nbio_v4_3_get_rev_id,
		519	.mc_access_enable = nbio_v4_3_mc_access_enable,
		520	.get_memsize = nbio_v4_3_get_memsize,
		521	.sdma_doorbell_range = nbio_v4_3_sriov_sdma_doorbell_range,
		522	.vcn_doorbell_range = nbio_v4_3_sriov_vcn_doorbell_range,
		523	.gc_doorbell_init = nbio_v4_3_sriov_gc_doorbell_init,
		524	.enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture,
		525	.enable_doorbell_selfring_aperture = nbio_v4_3_enable_doorbell_selfring_aperture,
		526	.ih_doorbell_range = nbio_v4_3_sriov_ih_doorbell_range,
		527	.update_medium_grain_clock_gating = nbio_v4_3_update_medium_grain_clock_gating,
		528	.update_medium_grain_light_sleep = nbio_v4_3_update_medium_grain_light_sleep,
		529	.get_clockgating_state = nbio_v4_3_get_clockgating_state,
		530	.ih_control = nbio_v4_3_ih_control,
		531	.init_registers = nbio_v4_3_init_registers,
		532	.remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
		533	.get_rom_offset = nbio_v4_3_get_rom_offset,
		534	};

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h+1−0

@@ -28,5 +28,6 @@ · 27 unmodified lines
28		28
29	extern const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg;	29	extern const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg;
30	extern const struct amdgpu_nbio_funcs nbio_v4_3_funcs;	30	extern const struct amdgpu_nbio_funcs nbio_v4_3_funcs;
		31	extern const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs;
31		32
32	#endif	33	#endif

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c+9−0

 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
+MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
 /* For large FW files the time to complete can be very long */
 #define USBC_PD_POLLING_LIMIT_S 240
 		break;
 	case IP_VERSION(13, 0, 0):
 	case IP_VERSION(13, 0, 7):
+	case IP_VERSION(13, 0, 10):
 		err = psp_init_sos_microcode(psp, chip_name);
 		if (err)
 			return err;
 	return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 }
+static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
+{
+	return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
+}
 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 {
 	int ret;
 	.bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 	.bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 	.bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
+	.bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
 	.bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 	.ring_init = psp_v13_0_ring_init,
 	.ring_create = psp_v13_0_ring_create,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c+19−91

@@ -561,44 +561,6 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) · 560 unmodified lines
561	}	561	}
562	}	562	}
563		563
564	static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
565	{
566	int err = 0;
567	const struct sdma_firmware_header_v1_0 *hdr;
568
569	err = amdgpu_ucode_validate(sdma_inst->fw);
570	if (err)
571	return err;
572
573	hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
574	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
575	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
576
577	if (sdma_inst->feature_version >= 20)
578	sdma_inst->burst_nop = true;
579
580	return 0;
581	}
582
583	static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
584	{
585	int i;
586
587	for (i = 0; i < adev->sdma.num_instances; i++) {
588	release_firmware(adev->sdma.instance[i].fw);
589	adev->sdma.instance[i].fw = NULL;
590
591	/* arcturus shares the same FW memory across
592	all SDMA isntances */
593	if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) \|\|
594	adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
595	break;
596	}
597
598	memset((void *)adev->sdma.instance, 0,
599	sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
600	}
601
602	/**	564	/**
603	* sdma_v4_0_init_microcode - load ucode images from disk	565	* sdma_v4_0_init_microcode - load ucode images from disk
604	*	566	*
@@ -615,9 +577,7 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) · 10 unmodified lines
615	{	577	{
616	const char *chip_name;	578	const char *chip_name;
617	char fw_name[30];	579	char fw_name[30];
618	int err = 0, i;	580	int ret, i;
619	struct amdgpu_firmware_info *info = NULL;
620	const struct common_firmware_header *header = NULL;
621		581
622	DRM_DEBUG("\n");	582	DRM_DEBUG("\n");
623		583
@@ -656,58 +616,25 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) · 32 unmodified lines
656	BUG();	616	BUG();
657	}	617	}
658		618
659	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);	619	for (i = 0; i < adev->sdma.num_instances; i++) {
660		620	if (i == 0)
661	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);	621	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
662	if (err)	622	else
663	goto out;	623	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
664
665	err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
666	if (err)
667	goto out;
668
669	for (i = 1; i < adev->sdma.num_instances; i++) {
670	if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) \|\|	624	if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) \|\|
671	adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {	625	adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
672	/* Acturus & Aldebaran will leverage the same FW memory	626	/* Acturus & Aldebaran will leverage the same FW memory
673	for every SDMA instance */	627	for every SDMA instance */
674	memcpy((void *)&adev->sdma.instance[i],	628	ret = amdgpu_sdma_init_microcode(adev, fw_name, 0, true);
675	(void *)&adev->sdma.instance[0],	629	break;
676	sizeof(struct amdgpu_sdma_instance));	630	} else {
677	}	631	ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false);
678	else {	632	if (ret)
679	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);	633	return ret;
680
681	err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
682	if (err)
683	goto out;
684
685	err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
686	if (err)
687	goto out;
688	}
689	}
690
691	DRM_DEBUG("psp_load == '%s'\n",
692	adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
693
694	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
695	for (i = 0; i < adev->sdma.num_instances; i++) {
696	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
697	info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
698	info->fw = adev->sdma.instance[i].fw;
699	header = (const struct common_firmware_header *)info->fw->data;
700	adev->firmware.fw_size +=
701	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
702	}	634	}
703	}	635	}
704		636
705	out:	637	return ret;
706	if (err) {
707	DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
708	sdma_v4_0_destroy_inst_ctx(adev);
709	}
710	return err;
711	}	638	}
712		639
713	/**	640	/**
@@ -2000,14 +1927,17 @@ static int sdma_v4_0_sw_fini(void *handle) · 1286 unmodified lines
2000	amdgpu_ring_fini(&adev->sdma.instance[i].page);	1927	amdgpu_ring_fini(&adev->sdma.instance[i].page);
2001	}	1928	}
2002		1929
2003	sdma_v4_0_destroy_inst_ctx(adev);	1930	if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0) \|\|
		1931	adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
		1932	amdgpu_sdma_destroy_inst_ctx(adev, true);
		1933	else
		1934	amdgpu_sdma_destroy_inst_ctx(adev, false);
2004		1935
2005	return 0;	1936	return 0;
2006	}	1937	}
2007		1938
2008	static int sdma_v4_0_hw_init(void *handle)	1939	static int sdma_v4_0_hw_init(void *handle)
2009	{	1940	{
2010	int r;
2011	struct amdgpu_device adev = (struct amdgpu_device )handle;	1941	struct amdgpu_device adev = (struct amdgpu_device )handle;
2012		1942
2013	if (adev->flags & AMD_IS_APU)	1943	if (adev->flags & AMD_IS_APU)
@@ -2016,9 +1946,7 @@ static int sdma_v4_0_hw_init(void *handle) · 2 unmodified lines
2016	if (!amdgpu_sriov_vf(adev))	1946	if (!amdgpu_sriov_vf(adev))
2017	sdma_v4_0_init_golden_registers(adev);	1947	sdma_v4_0_init_golden_registers(adev);
2018		1948
2019	r = sdma_v4_0_start(adev);	1949	return sdma_v4_0_start(adev);
2020
2021	return r;
2022	}	1950	}
2023		1951
2024	static int sdma_v4_0_hw_fini(void *handle)	1952	static int sdma_v4_0_hw_fini(void *handle)

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c+9−40

@@ -240,10 +240,7 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) · 239 unmodified lines
240	{	240	{
241	const char *chip_name;	241	const char *chip_name;
242	char fw_name[40];	242	char fw_name[40];
243	int err = 0, i;	243	int ret, i;
244	struct amdgpu_firmware_info *info = NULL;
245	const struct common_firmware_header *header = NULL;
246	const struct sdma_firmware_header_v1_0 *hdr;
247		244
248	if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))	245	if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
249	return 0;	246	return 0;
@@ -272,38 +269,12 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) · 22 unmodified lines
272	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);	269	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
273	else	270	else
274	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);	271	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
275	err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);	272	ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false);
276	if (err)	273	if (ret)
277	goto out;	274	return ret;
278	err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
279	if (err)
280	goto out;
281	hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
282	adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
283	adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
284	if (adev->sdma.instance[i].feature_version >= 20)
285	adev->sdma.instance[i].burst_nop = true;
286	DRM_DEBUG("psp_load == '%s'\n",
287	adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
288
289	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
290	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
291	info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
292	info->fw = adev->sdma.instance[i].fw;
293	header = (const struct common_firmware_header *)info->fw->data;
294	adev->firmware.fw_size +=
295	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
296	}
297	}
298	out:
299	if (err) {
300	DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
301	for (i = 0; i < adev->sdma.num_instances; i++) {
302	release_firmware(adev->sdma.instance[i].fw);
303	adev->sdma.instance[i].fw = NULL;
304	}
305	}	275	}
306	return err;	276
		277	return ret;
307	}	278	}
308		279
309	static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)	280	static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
@@ -1465,12 +1436,10 @@ static int sdma_v5_0_sw_fini(void *handle) · 1155 unmodified lines
1465	struct amdgpu_device adev = (struct amdgpu_device )handle;	1436	struct amdgpu_device adev = (struct amdgpu_device )handle;
1466	int i;	1437	int i;
1467		1438
1468	for (i = 0; i < adev->sdma.num_instances; i++) {	1439	for (i = 0; i < adev->sdma.num_instances; i++)
1469	release_firmware(adev->sdma.instance[i].fw);
1470	adev->sdma.instance[i].fw = NULL;
1471
1472	amdgpu_ring_fini(&adev->sdma.instance[i].ring);	1440	amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1473	}	1441
		1442	amdgpu_sdma_destroy_inst_ctx(adev, false);
1474		1443
1475	return 0;	1444	return 0;
1476	}	1445	}

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c+3−71

@@ -89,33 +89,6 @@ static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3 · 88 unmodified lines
89	return base + internal_offset;	89	return base + internal_offset;
90	}	90	}
91		91
92	static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
93	{
94	int err = 0;
95	const struct sdma_firmware_header_v1_0 *hdr;
96
97	err = amdgpu_ucode_validate(sdma_inst->fw);
98	if (err)
99	return err;
100
101	hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
102	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
103	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
104
105	if (sdma_inst->feature_version >= 20)
106	sdma_inst->burst_nop = true;
107
108	return 0;
109	}
110
111	static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
112	{
113	release_firmware(adev->sdma.instance[0].fw);
114
115	memset((void *)adev->sdma.instance, 0,
116	sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
117	}
118
119	/**	92	/**
120	* sdma_v5_2_init_microcode - load ucode images from disk	93	* sdma_v5_2_init_microcode - load ucode images from disk
121	*	94	*
@@ -132,9 +105,6 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) · 10 unmodified lines
132	{	105	{
133	const char *chip_name;	106	const char *chip_name;
134	char fw_name[40];	107	char fw_name[40];
135	int err = 0, i;
136	struct amdgpu_firmware_info *info = NULL;
137	const struct common_firmware_header *header = NULL;
138		108
139	DRM_DEBUG("\n");	109	DRM_DEBUG("\n");
140		110
@@ -169,42 +139,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) · 28 unmodified lines
169		139
170	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);	140	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
171		141
172	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);	142	return amdgpu_sdma_init_microcode(adev, fw_name, 0, true);
173	if (err)
174	goto out;
175
176	err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
177	if (err)
178	goto out;
179
180	for (i = 1; i < adev->sdma.num_instances; i++)
181	memcpy((void *)&adev->sdma.instance[i],
182	(void *)&adev->sdma.instance[0],
183	sizeof(struct amdgpu_sdma_instance));
184
185	if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
186	return 0;
187
188	DRM_DEBUG("psp_load == '%s'\n",
189	adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
190
191	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
192	for (i = 0; i < adev->sdma.num_instances; i++) {
193	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
194	info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
195	info->fw = adev->sdma.instance[i].fw;
196	header = (const struct common_firmware_header *)info->fw->data;
197	adev->firmware.fw_size +=
198	ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
199	}
200	}
201
202	out:
203	if (err) {
204	DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
205	sdma_v5_2_destroy_inst_ctx(adev);
206	}
207	return err;
208	}	143	}
209		144
210	static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)	145	static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
@@ -1406,19 +1341,16 @@ static int sdma_v5_2_sw_fini(void *handle) · 1195 unmodified lines
1406	for (i = 0; i < adev->sdma.num_instances; i++)	1341	for (i = 0; i < adev->sdma.num_instances; i++)
1407	amdgpu_ring_fini(&adev->sdma.instance[i].ring);	1342	amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1408		1343
1409	sdma_v5_2_destroy_inst_ctx(adev);	1344	amdgpu_sdma_destroy_inst_ctx(adev, true);
1410		1345
1411	return 0;	1346	return 0;
1412	}	1347	}
1413		1348
1414	static int sdma_v5_2_hw_init(void *handle)	1349	static int sdma_v5_2_hw_init(void *handle)
1415	{	1350	{
1416	int r;
1417	struct amdgpu_device adev = (struct amdgpu_device )handle;	1351	struct amdgpu_device adev = (struct amdgpu_device )handle;
1418		1352
1419	r = sdma_v5_2_start(adev);	1353	return sdma_v5_2_start(adev);
1420
1421	return r;
1422	}	1354	}
1423		1355
1424	static int sdma_v5_2_hw_fini(void *handle)	1356	static int sdma_v5_2_hw_fini(void *handle)

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c+10−77

@@ -47,6 +47,7 @@ · 46 unmodified lines
47	MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");	47	MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
48	MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");	48	MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
49	MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");	49	MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
		50	MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
50		51
51	#define SDMA1_REG_OFFSET 0x600	52	#define SDMA1_REG_OFFSET 0x600
52	#define SDMA0_HYP_DEC_REG_START 0x5880	53	#define SDMA0_HYP_DEC_REG_START 0x5880
@@ -77,33 +78,6 @@ static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3 · 24 unmodified lines
77	return base + internal_offset;	78	return base + internal_offset;
78	}	79	}
79		80
80	static int sdma_v6_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
81	{
82	int err = 0;
83	const struct sdma_firmware_header_v2_0 *hdr;
84
85	err = amdgpu_ucode_validate(sdma_inst->fw);
86	if (err)
87	return err;
88
89	hdr = (const struct sdma_firmware_header_v2_0 *)sdma_inst->fw->data;
90	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
91	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
92
93	if (sdma_inst->feature_version >= 20)
94	sdma_inst->burst_nop = true;
95
96	return 0;
97	}
98
99	static void sdma_v6_0_destroy_inst_ctx(struct amdgpu_device *adev)
100	{
101	release_firmware(adev->sdma.instance[0].fw);
102
103	memset((void*)adev->sdma.instance, 0,
104	sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
105	}
106
107	/**	81	/**
108	* sdma_v6_0_init_microcode - load ucode images from disk	82	* sdma_v6_0_init_microcode - load ucode images from disk
109	*	83	*
@@ -113,16 +87,10 @@ static void sdma_v6_0_destroy_inst_ctx(struct amdgpu_device *adev) · 3 unmodified lines
113	* the driver (not loaded into hw).	87	* the driver (not loaded into hw).
114	* Returns 0 on success, error on failure.	88	* Returns 0 on success, error on failure.
115	*/	89	*/
116
117	// emulation only, won't work on real chip
118	// sdma 6.0.0 real chip need to use PSP to load firmware
119	static int sdma_v6_0_init_microcode(struct amdgpu_device *adev)	90	static int sdma_v6_0_init_microcode(struct amdgpu_device *adev)
120	{	91	{
121	char fw_name[30];	92	char fw_name[30];
122	char ucode_prefix[30];	93	char ucode_prefix[30];
123	int err = 0, i;
124	struct amdgpu_firmware_info *info = NULL;
125	const struct sdma_firmware_header_v2_0 *sdma_hdr;
126		94
127	DRM_DEBUG("\n");	95	DRM_DEBUG("\n");
128		96
@@ -130,43 +98,7 @@ static int sdma_v6_0_init_microcode(struct amdgpu_device *adev) · 1 unmodified line
130		98
131	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);	99	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
132		100
133	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);	101	return amdgpu_sdma_init_microcode(adev, fw_name, 0, true);
134	if (err)
135	goto out;
136
137	err = sdma_v6_0_init_inst_ctx(&adev->sdma.instance[0]);
138	if (err)
139	goto out;
140
141	for (i = 1; i < adev->sdma.num_instances; i++) {
142	memcpy((void*)&adev->sdma.instance[i],
143	(void*)&adev->sdma.instance[0],
144	sizeof(struct amdgpu_sdma_instance));
145	}
146
147	DRM_DEBUG("psp_load == '%s'\n",
148	adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
149
150	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
151	sdma_hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
152	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH0];
153	info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH0;
154	info->fw = adev->sdma.instance[0].fw;
155	adev->firmware.fw_size +=
156	ALIGN(le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes), PAGE_SIZE);
157	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH1];
158	info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH1;
159	info->fw = adev->sdma.instance[0].fw;
160	adev->firmware.fw_size +=
161	ALIGN(le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes), PAGE_SIZE);
162	}
163
164	out:
165	if (err) {
166	DRM_ERROR("sdma_v6_0: Failed to load firmware \"%s\"\n", fw_name);
167	sdma_v6_0_destroy_inst_ctx(adev);
168	}
169	return err;
170	}	102	}
171		103
172	static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring)	104	static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring)
@@ -559,7 +491,8 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) · 386 unmodified lines
559	for (i = 0; i < adev->sdma.num_instances; i++) {	491	for (i = 0; i < adev->sdma.num_instances; i++) {
560	ring = &adev->sdma.instance[i].ring;	492	ring = &adev->sdma.instance[i].ring;
561		493
562	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);	494	if (!amdgpu_sriov_vf(adev))
		495	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
563		496
564	/* Set ring buffer size in dwords */	497	/* Set ring buffer size in dwords */
565	rb_bufsz = order_base_2(ring->ring_size / 4);	498	rb_bufsz = order_base_2(ring->ring_size / 4);
@@ -593,7 +526,10 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) · 27 unmodified lines
593	lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);	526	lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
594		527
595	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);	528	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
596	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);	529	if (amdgpu_sriov_vf(adev))
		530	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);
		531	else
		532	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
597	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);	533	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
598		534
599	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);	535	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
@@ -1365,19 +1301,16 @@ static int sdma_v6_0_sw_fini(void *handle) · 765 unmodified lines
1365	for (i = 0; i < adev->sdma.num_instances; i++)	1301	for (i = 0; i < adev->sdma.num_instances; i++)
1366	amdgpu_ring_fini(&adev->sdma.instance[i].ring);	1302	amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1367		1303
1368	sdma_v6_0_destroy_inst_ctx(adev);	1304	amdgpu_sdma_destroy_inst_ctx(adev, true);
1369		1305
1370	return 0;	1306	return 0;
1371	}	1307	}
1372		1308
1373	static int sdma_v6_0_hw_init(void *handle)	1309	static int sdma_v6_0_hw_init(void *handle)
1374	{	1310	{
1375	int r;
1376	struct amdgpu_device adev = (struct amdgpu_device )handle;	1311	struct amdgpu_device adev = (struct amdgpu_device )handle;
1377		1312
1378	r = sdma_v6_0_start(adev);	1313	return sdma_v6_0_start(adev);
1379
1380	return r;
1381	}	1314	}
1382		1315
1383	static int sdma_v6_0_hw_fini(void *handle)	1316	static int sdma_v6_0_hw_fini(void *handle)

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c+303−0

@@ -0,0 +1,303 @@
	1	/*
	2	* Copyright 2021 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#include "sienna_cichlid.h"
	25	#include "amdgpu_reset.h"
	26	#include "amdgpu_amdkfd.h"
	27	#include "amdgpu_dpm.h"
	28	#include "amdgpu_job.h"
	29	#include "amdgpu_ring.h"
	30	#include "amdgpu_ras.h"
	31	#include "amdgpu_psp.h"
	32	#include "amdgpu_xgmi.h"
	33
	34	static struct amdgpu_reset_handler *
	35	sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
	36	struct amdgpu_reset_context *reset_context)
	37	{
	38	struct amdgpu_reset_handler *handler;
	39	struct amdgpu_device adev = (struct amdgpu_device )reset_ctl->handle;
	40
	41	if (reset_context->method != AMD_RESET_METHOD_NONE) {
	42	list_for_each_entry(handler, &reset_ctl->reset_handlers,
	43	handler_list) {
	44	if (handler->reset_method == reset_context->method)
	45	return handler;
	46	}
	47	} else {
	48	list_for_each_entry(handler, &reset_ctl->reset_handlers,
	49	handler_list) {
	50	if (handler->reset_method == AMD_RESET_METHOD_MODE2 &&
	51	adev->pm.fw_version >= 0x3a5500 &&
	52	!amdgpu_sriov_vf(adev)) {
	53	reset_context->method = AMD_RESET_METHOD_MODE2;
	54	return handler;
	55	}
	56	}
	57	}
	58
	59	return NULL;
	60	}
	61
	62	static int sienna_cichlid_mode2_suspend_ip(struct amdgpu_device *adev)
	63	{
	64	int r, i;
	65
	66	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
	67	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
	68
	69	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
	70	if (!(adev->ip_blocks[i].version->type ==
	71	AMD_IP_BLOCK_TYPE_GFX \|\|
	72	adev->ip_blocks[i].version->type ==
	73	AMD_IP_BLOCK_TYPE_SDMA))
	74	continue;
	75
	76	r = adev->ip_blocks[i].version->funcs->suspend(adev);
	77
	78	if (r) {
	79	dev_err(adev->dev,
	80	"suspend of IP block <%s> failed %d\n",
	81	adev->ip_blocks[i].version->funcs->name, r);
	82	return r;
	83	}
	84	adev->ip_blocks[i].status.hw = false;
	85	}
	86
	87	return r;
	88	}
	89
	90	static int
	91	sienna_cichlid_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
	92	struct amdgpu_reset_context *reset_context)
	93	{
	94	int r = 0;
	95	struct amdgpu_device adev = (struct amdgpu_device )reset_ctl->handle;
	96
	97	if (!amdgpu_sriov_vf(adev)) {
	98	if (adev->gfxhub.funcs->mode2_save_regs)
	99	adev->gfxhub.funcs->mode2_save_regs(adev);
	100	if (adev->gfxhub.funcs->halt)
	101	adev->gfxhub.funcs->halt(adev);
	102	r = sienna_cichlid_mode2_suspend_ip(adev);
	103	}
	104
	105	return r;
	106	}
	107
	108	static void sienna_cichlid_async_reset(struct work_struct *work)
	109	{
	110	struct amdgpu_reset_handler *handler;
	111	struct amdgpu_reset_control *reset_ctl =
	112	container_of(work, struct amdgpu_reset_control, reset_work);
	113	struct amdgpu_device adev = (struct amdgpu_device )reset_ctl->handle;
	114
	115	list_for_each_entry(handler, &reset_ctl->reset_handlers,
	116	handler_list) {
	117	if (handler->reset_method == reset_ctl->active_reset) {
	118	dev_dbg(adev->dev, "Resetting device\n");
	119	handler->do_reset(adev);
	120	break;
	121	}
	122	}
	123	}
	124
	125	static int sienna_cichlid_mode2_reset(struct amdgpu_device *adev)
	126	{
	127	/* disable BM */
	128	pci_clear_master(adev->pdev);
	129	return amdgpu_dpm_mode2_reset(adev);
	130	}
	131
	132	static int
	133	sienna_cichlid_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
	134	struct amdgpu_reset_context *reset_context)
	135	{
	136	struct amdgpu_device adev = (struct amdgpu_device )reset_ctl->handle;
	137	int r;
	138
	139	r = sienna_cichlid_mode2_reset(adev);
	140	if (r) {
	141	dev_err(adev->dev,
	142	"ASIC reset failed with error, %d ", r);
	143	}
	144	return r;
	145	}
	146
	147	static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev)
	148	{
	149	int i, r;
	150	struct psp_context *psp = &adev->psp;
	151
	152	r = psp_rlc_autoload_start(psp);
	153	if (r) {
	154	dev_err(adev->dev, "Failed to start rlc autoload\n");
	155	return r;
	156	}
	157
	158	/* Reinit GFXHUB */
	159	if (adev->gfxhub.funcs->mode2_restore_regs)
	160	adev->gfxhub.funcs->mode2_restore_regs(adev);
	161	adev->gfxhub.funcs->init(adev);
	162	r = adev->gfxhub.funcs->gart_enable(adev);
	163	if (r) {
	164	dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
	165	return r;
	166	}
	167
	168	for (i = 0; i < adev->num_ip_blocks; i++) {
	169	if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
	170	r = adev->ip_blocks[i].version->funcs->resume(adev);
	171	if (r) {
	172	dev_err(adev->dev,
	173	"resume of IP block <%s> failed %d\n",
	174	adev->ip_blocks[i].version->funcs->name, r);
	175	return r;
	176	}
	177
	178	adev->ip_blocks[i].status.hw = true;
	179	}
	180	}
	181
	182	for (i = 0; i < adev->num_ip_blocks; i++) {
	183	if (!(adev->ip_blocks[i].version->type ==
	184	AMD_IP_BLOCK_TYPE_GFX \|\|
	185	adev->ip_blocks[i].version->type ==
	186	AMD_IP_BLOCK_TYPE_SDMA))
	187	continue;
	188	r = adev->ip_blocks[i].version->funcs->resume(adev);
	189	if (r) {
	190	dev_err(adev->dev,
	191	"resume of IP block <%s> failed %d\n",
	192	adev->ip_blocks[i].version->funcs->name, r);
	193	return r;
	194	}
	195
	196	adev->ip_blocks[i].status.hw = true;
	197	}
	198
	199	for (i = 0; i < adev->num_ip_blocks; i++) {
	200	if (!(adev->ip_blocks[i].version->type ==
	201	AMD_IP_BLOCK_TYPE_GFX \|\|
	202	adev->ip_blocks[i].version->type ==
	203	AMD_IP_BLOCK_TYPE_SDMA))
	204	continue;
	205
	206	if (adev->ip_blocks[i].version->funcs->late_init) {
	207	r = adev->ip_blocks[i].version->funcs->late_init(
	208	(void *)adev);
	209	if (r) {
	210	dev_err(adev->dev,
	211	"late_init of IP block <%s> failed %d after reset\n",
	212	adev->ip_blocks[i].version->funcs->name,
	213	r);
	214	return r;
	215	}
	216	}
	217	adev->ip_blocks[i].status.late_initialized = true;
	218	}
	219
	220	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
	221	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
	222
	223	return r;
	224	}
	225
	226	static int
	227	sienna_cichlid_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
	228	struct amdgpu_reset_context *reset_context)
	229	{
	230	int r;
	231	struct amdgpu_device tmp_adev = (struct amdgpu_device )reset_ctl->handle;
	232
	233	dev_info(tmp_adev->dev,
	234	"GPU reset succeeded, trying to resume\n");
	235	r = sienna_cichlid_mode2_restore_ip(tmp_adev);
	236	if (r)
	237	goto end;
	238
	239	/*
	240	* Add this ASIC as tracked as reset was already
	241	* complete successfully.
	242	*/
	243	amdgpu_register_gpu_instance(tmp_adev);
	244
	245	/* Resume RAS */
	246	amdgpu_ras_resume(tmp_adev);
	247
	248	amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
	249
	250	r = amdgpu_ib_ring_tests(tmp_adev);
	251	if (r) {
	252	dev_err(tmp_adev->dev,
	253	"ib ring test failed (%d).\n", r);
	254	r = -EAGAIN;
	255	goto end;
	256	}
	257
	258	end:
	259	if (r)
	260	return -EAGAIN;
	261	else
	262	return r;
	263	}
	264
	265	static struct amdgpu_reset_handler sienna_cichlid_mode2_handler = {
	266	.reset_method = AMD_RESET_METHOD_MODE2,
	267	.prepare_env = NULL,
	268	.prepare_hwcontext = sienna_cichlid_mode2_prepare_hwcontext,
	269	.perform_reset = sienna_cichlid_mode2_perform_reset,
	270	.restore_hwcontext = sienna_cichlid_mode2_restore_hwcontext,
	271	.restore_env = NULL,
	272	.do_reset = sienna_cichlid_mode2_reset,
	273	};
	274
	275	int sienna_cichlid_reset_init(struct amdgpu_device *adev)
	276	{
	277	struct amdgpu_reset_control *reset_ctl;
	278
	279	reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
	280	if (!reset_ctl)
	281	return -ENOMEM;
	282
	283	reset_ctl->handle = adev;
	284	reset_ctl->async_reset = sienna_cichlid_async_reset;
	285	reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
	286	reset_ctl->get_reset_handler = sienna_cichlid_get_reset_handler;
	287
	288	INIT_LIST_HEAD(&reset_ctl->reset_handlers);
	289	INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
	290	/* Only mode2 is handled through reset control now */
	291	amdgpu_reset_add_handler(reset_ctl, &sienna_cichlid_mode2_handler);
	292
	293	adev->reset_cntl = reset_ctl;
	294
	295	return 0;
	296	}
	297
	298	int sienna_cichlid_reset_fini(struct amdgpu_device *adev)
	299	{
	300	kfree(adev->reset_cntl);
	301	adev->reset_cntl = NULL;
	302	return 0;
	303	}

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.hrenamed from drivers/gpu/drm/amd/display/dc/inc/dml_wrapper.h+6−8

 /*
- * Copyright 2015 Advanced Micro Devices, Inc.
+ * Copyright 2021 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: AMD
- *
  */
-#ifndef DML_WRAPPER_H_
+#ifndef __SIENNA_CICHLID_H__
-#define DML_WRAPPER_H_
+#define __SIENNA_CICHLID_H__
-#include "dc.h"
+#include "amdgpu.h"
-#include "dml/display_mode_vba.h"
-bool dml_validate(struct dc *dc, struct dc_state *context, bool fast_validate);
+int sienna_cichlid_reset_init(struct amdgpu_device *adev);
+int sienna_cichlid_reset_fini(struct amdgpu_device *adev);
 #endif

drivers/gpu/drm/amd/amdgpu/soc21.c+18−1

 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
-	WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL), grbm_gfx_cntl);
+	WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
 }
 static void soc21_vga_set_state(struct amdgpu_device *adev, bool state)
 			AMD_PG_SUPPORT_JPEG |
 			AMD_PG_SUPPORT_ATHUB |
 			AMD_PG_SUPPORT_MMHUB;
+		if (amdgpu_sriov_vf(adev)) {
+			adev->cg_flags = 0;
+			adev->pg_flags = 0;
+		}
 		adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
 		break;
 	case IP_VERSION(11, 0, 2):
 			AMD_PG_SUPPORT_JPEG;
 		adev->external_rev_id = adev->rev_id + 0x1;
 		break;
+	case IP_VERSION(11, 0, 3):
+		adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
+			AMD_CG_SUPPORT_JPEG_MGCG;
+		adev->pg_flags = AMD_PG_SUPPORT_VCN |
+			AMD_PG_SUPPORT_VCN_DPG |
+			AMD_PG_SUPPORT_JPEG;
+		if (amdgpu_sriov_vf(adev)) {
+			/* hypervisor control CG and PG enablement */
+			adev->cg_flags = 0;
+			adev->pg_flags = 0;
+		}
+		adev->external_rev_id = adev->rev_id + 0x20;
+		break;
 	default:
 		/* FIXME: not supported yet */
 		return -EINVAL;

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c+33−25

@@ -452,41 +452,47 @@ static void umc_v6_7_query_ras_error_count(struct amdgpu_device *adev, · 451 unmodified lines
452		452
453	static void umc_v6_7_query_error_address(struct amdgpu_device *adev,	453	static void umc_v6_7_query_error_address(struct amdgpu_device *adev,
454	struct ras_err_data *err_data,	454	struct ras_err_data *err_data,
455	uint32_t umc_reg_offset,	455	uint32_t umc_reg_offset, uint32_t ch_inst,
456	uint32_t ch_inst,	456	uint32_t umc_inst, uint64_t mca_addr)
457	uint32_t umc_inst)
458	{	457	{
459	uint32_t mc_umc_status_addr;	458	uint32_t mc_umc_status_addr;
460	uint32_t channel_index;	459	uint32_t channel_index;
461	uint64_t mc_umc_status, mc_umc_addrt0;	460	uint64_t mc_umc_status = 0, mc_umc_addrt0;
462	uint64_t err_addr, soc_pa, retired_page, column;	461	uint64_t err_addr, soc_pa, retired_page, column;
463		462
464	mc_umc_status_addr =	463	if (mca_addr == UMC_INVALID_ADDR) {
465	SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);	464	mc_umc_status_addr =
466	mc_umc_addrt0 =	465	SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
467	SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);	466	mc_umc_addrt0 =
		467	SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
468		468
469	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);	469	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
470		470
471	if (mc_umc_status == 0)	471	if (mc_umc_status == 0)
472	return;	472	return;
473		473
474	if (!err_data->err_addr) {	474	if (!err_data->err_addr) {
475	/* clear umc status */	475	/* clear umc status */
476	WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);	476	WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
477	return;	477	return;
		478	}
478	}	479	}
479		480
480	channel_index =	481	channel_index =
481	adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];	482	adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
482		483
483	/* calculate error address if ue/ce error is detected */	484	/* calculate error address if ue/ce error is detected */
484	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&	485	if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
485	(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 \|\|	486	(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 \|\|
486	REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {	487	REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) \|\|
487		488	mca_addr != UMC_INVALID_ADDR) {
488	err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);	489	if (mca_addr == UMC_INVALID_ADDR) {
489	err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);	490	err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
		491	err_addr =
		492	REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
		493	} else {
		494	err_addr = mca_addr;
		495	}
490		496
491	/* translate umc channel address to soc pa, 3 parts are included */	497	/* translate umc channel address to soc pa, 3 parts are included */
492	soc_pa = ADDR_OF_8KB_BLOCK(err_addr) \|	498	soc_pa = ADDR_OF_8KB_BLOCK(err_addr) \|
@@ -501,7 +507,8 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, · 8 unmodified lines
501		507
502	/* we only save ue error information currently, ce is skipped */	508	/* we only save ue error information currently, ce is skipped */
503	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)	509	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
504	== 1) {	510	== 1 \|\|
		511	mca_addr != UMC_INVALID_ADDR) {
505	/* loop for all possibilities of [C4 C3 C2] */	512	/* loop for all possibilities of [C4 C3 C2] */
506	for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {	513	for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {
507	retired_page = soc_pa \| (column << UMC_V6_7_PA_C2_BIT);	514	retired_page = soc_pa \| (column << UMC_V6_7_PA_C2_BIT);
@@ -519,7 +526,8 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, · 11 unmodified lines
519	}	526	}
520		527
521	/* clear umc status */	528	/* clear umc status */
522	WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);	529	if (mca_addr == UMC_INVALID_ADDR)
		530	WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
523	}	531	}
524		532
525	static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev,	533	static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev,
@@ -540,9 +548,8 @@ static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev, · 14 unmodified lines
540	ch_inst);	548	ch_inst);
541	umc_v6_7_query_error_address(adev,	549	umc_v6_7_query_error_address(adev,
542	err_data,	550	err_data,
543	umc_reg_offset,	551	umc_reg_offset, ch_inst,
544	ch_inst,	552	umc_inst, UMC_INVALID_ADDR);
545	umc_inst);
546	}	553	}
547	}	554	}
548		555
@@ -583,4 +590,5 @@ struct amdgpu_umc_ras umc_v6_7_ras = { · 34 unmodified lines
583	.query_ras_poison_mode = umc_v6_7_query_ras_poison_mode,	590	.query_ras_poison_mode = umc_v6_7_query_ras_poison_mode,
584	.ecc_info_query_ras_error_count = umc_v6_7_ecc_info_query_ras_error_count,	591	.ecc_info_query_ras_error_count = umc_v6_7_ecc_info_query_ras_error_count,
585	.ecc_info_query_ras_error_address = umc_v6_7_ecc_info_query_ras_error_address,	592	.ecc_info_query_ras_error_address = umc_v6_7_ecc_info_query_ras_error_address,
		593	.convert_ras_error_address = umc_v6_7_query_error_address,
586	};	594	};

drivers/gpu/drm/amd/amdgpu/umc_v8_10.c+3−9

 						   uint32_t umc_reg_offset,
 						   unsigned long *error_count)
 {
-	uint32_t ecc_err_cnt, ecc_err_cnt_addr;
 	uint64_t mc_umc_status;
 	uint32_t mc_umc_status_addr;
 	/* UMC 8_10 registers */
-	ecc_err_cnt_addr =
-		SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt);
 	mc_umc_status_addr =
 		SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
-	ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
+	/* Rely on MCUMC_STATUS for correctable error counter
-	*error_count +=
+	 * MCUMC_STATUS is a 64 bit register
-		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) -
+	 */
-		 UMC_V8_10_CE_CNT_INIT);
-	/* Check for SRAM correctable error, MCUMC_STATUS is a 64 bit register */
 	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
 	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c+10−7

 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 };
-static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p)
+static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p,
+				struct amdgpu_job *job)
 {
 	struct drm_gpu_scheduler **scheds;
 	/* The create msg must be in the first IB submitted */
-	if (atomic_read(&p->entity->fence_seq))
+	if (atomic_read(&job->base.entity->fence_seq))
 		return -EINVAL;
 	scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
 		[AMDGPU_RING_PRIO_DEFAULT].sched;
-	drm_sched_entity_modify_sched(p->entity, scheds, 1);
+	drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
 	return 0;
 }
-static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
+static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
+			    uint64_t addr)
 {
 	struct ttm_operation_ctx ctx = { false, false };
 	struct amdgpu_bo_va_mapping *map;
 		if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
 			continue;
-		r = vcn_v3_0_limit_sched(p);
+		r = vcn_v3_0_limit_sched(p, job);
 		if (r)
 			goto out;
 	}
 					   struct amdgpu_job *job,
 					   struct amdgpu_ib *ib)
 {
-	struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
+	struct amdgpu_ring *ring = amdgpu_job_ring(job);
 	uint32_t msg_lo = 0, msg_hi = 0;
 	unsigned i;
 	int r;
 			msg_hi = val;
 		} else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) &&
 			   val == 0) {
-			r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo);
+			r = vcn_v3_0_dec_msg(p, job,
+					     ((u64)msg_hi) << 32 | msg_lo);
 			if (r)
 				return r;
 		}

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c+312−31

@@ -30,6 +30,7 @@ · 29 unmodified lines
30	#include "soc15d.h"	30	#include "soc15d.h"
31	#include "soc15_hw_ip.h"	31	#include "soc15_hw_ip.h"
32	#include "vcn_v2_0.h"	32	#include "vcn_v2_0.h"
		33	#include "mmsch_v4_0.h"
33		34
34	#include "vcn/vcn_4_0_0_offset.h"	35	#include "vcn/vcn_4_0_0_offset.h"
35	#include "vcn/vcn_4_0_0_sh_mask.h"	36	#include "vcn/vcn_4_0_0_sh_mask.h"
@@ -45,6 +46,8 @@ · 9 unmodified lines
45	#define VCN_VID_SOC_ADDRESS_2_0 0x1fb00	46	#define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
46	#define VCN1_VID_SOC_ADDRESS_3_0 0x48300	47	#define VCN1_VID_SOC_ADDRESS_3_0 0x48300
47		48
		49	#define VCN_HARVEST_MMSCH 0
		50
48	#define RDECODE_MSG_CREATE 0x00000000	51	#define RDECODE_MSG_CREATE 0x00000000
49	#define RDECODE_MESSAGE_CREATE 0x00000001	52	#define RDECODE_MESSAGE_CREATE 0x00000001
50		53
@@ -53,12 +56,14 @@ static int amdgpu_ih_clientid_vcns[] = { · 2 unmodified lines
53	SOC15_IH_CLIENTID_VCN1	56	SOC15_IH_CLIENTID_VCN1
54	};	57	};
55		58
		59	static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
56	static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);	60	static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
57	static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);	61	static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
58	static int vcn_v4_0_set_powergating_state(void *handle,	62	static int vcn_v4_0_set_powergating_state(void *handle,
59	enum amd_powergating_state state);	63	enum amd_powergating_state state);
60	static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,	64	static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
61	int inst_idx, struct dpg_pause_state *new_state);	65	int inst_idx, struct dpg_pause_state *new_state);
		66	static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
62		67
63	/**	68	/**
64	* vcn_v4_0_early_init - set function pointers	69	* vcn_v4_0_early_init - set function pointers
@@ -71,6 +76,9 @@ static int vcn_v4_0_early_init(void *handle) · 6 unmodified lines
71	{	76	{
72	struct amdgpu_device adev = (struct amdgpu_device )handle;	77	struct amdgpu_device adev = (struct amdgpu_device )handle;
73		78
		79	if (amdgpu_sriov_vf(adev))
		80	adev->vcn.harvest_config = VCN_HARVEST_MMSCH;
		81
74	/* re-use enc ring as unified ring */	82	/* re-use enc ring as unified ring */
75	adev->vcn.num_enc_rings = 1;	83	adev->vcn.num_enc_rings = 1;
76		84
@@ -92,6 +100,7 @@ static int vcn_v4_0_sw_init(void *handle) · 15 unmodified lines
92	struct amdgpu_ring *ring;	100	struct amdgpu_ring *ring;
93	struct amdgpu_device adev = (struct amdgpu_device )handle;	101	struct amdgpu_device adev = (struct amdgpu_device )handle;
94	int i, r;	102	int i, r;
		103	int vcn_doorbell_index = 0;
95		104
96	r = amdgpu_vcn_sw_init(adev);	105	r = amdgpu_vcn_sw_init(adev);
97	if (r)	106	if (r)
@@ -103,6 +112,12 @@ static int vcn_v4_0_sw_init(void *handle) · 5 unmodified lines
103	if (r)	112	if (r)
104	return r;	113	return r;
105		114
		115	if (amdgpu_sriov_vf(adev)) {
		116	vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 - MMSCH_DOORBELL_OFFSET;
		117	/* get DWORD offset */
		118	vcn_doorbell_index = vcn_doorbell_index << 1;
		119	}
		120
106	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {	121	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
107	volatile struct amdgpu_vcn4_fw_shared *fw_shared;	122	volatile struct amdgpu_vcn4_fw_shared *fw_shared;
108		123
@@ -119,7 +134,10 @@ static int vcn_v4_0_sw_init(void *handle) · 10 unmodified lines
119		134
120	ring = &adev->vcn.inst[i].ring_enc[0];	135	ring = &adev->vcn.inst[i].ring_enc[0];
121	ring->use_doorbell = true;	136	ring->use_doorbell = true;
122	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;	137	if (amdgpu_sriov_vf(adev))
		138	ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1;
		139	else
		140	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
123		141
124	sprintf(ring->name, "vcn_unified_%d", i);	142	sprintf(ring->name, "vcn_unified_%d", i);
125		143
@@ -132,10 +150,23 @@ static int vcn_v4_0_sw_init(void *handle) · 6 unmodified lines
132	fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);	150	fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
133	fw_shared->sq.is_enabled = 1;	151	fw_shared->sq.is_enabled = 1;
134		152
		153	fw_shared->present_flag_0 \|= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
		154	fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
		155	AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
		156
		157	if (amdgpu_sriov_vf(adev))
		158	fw_shared->present_flag_0 \|= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
		159
135	if (amdgpu_vcnfw_log)	160	if (amdgpu_vcnfw_log)
136	amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);	161	amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
137	}	162	}
138		163
		164	if (amdgpu_sriov_vf(adev)) {
		165	r = amdgpu_virt_alloc_mm_table(adev);
		166	if (r)
		167	return r;
		168	}
		169
139	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)	170	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
140	adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;	171	adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
141		172
@@ -169,6 +200,9 @@ static int vcn_v4_0_sw_fini(void *handle) · 27 unmodified lines
169	drm_dev_exit(idx);	200	drm_dev_exit(idx);
170	}	201	}
171		202
		203	if (amdgpu_sriov_vf(adev))
		204	amdgpu_virt_free_mm_table(adev);
		205
172	r = amdgpu_vcn_suspend(adev);	206	r = amdgpu_vcn_suspend(adev);
173	if (r)	207	if (r)
174	return r;	208	return r;
@@ -191,18 +225,42 @@ static int vcn_v4_0_hw_init(void *handle) · 16 unmodified lines
191	struct amdgpu_ring *ring;	225	struct amdgpu_ring *ring;
192	int i, r;	226	int i, r;
193		227
194	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {	228	if (amdgpu_sriov_vf(adev)) {
195	if (adev->vcn.harvest_config & (1 << i))	229	r = vcn_v4_0_start_sriov(adev);
196	continue;	230	if (r)
		231	goto done;
197		232
198	ring = &adev->vcn.inst[i].ring_enc[0];	233	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
		234	if (adev->vcn.harvest_config & (1 << i))
		235	continue;
199		236
200	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,	237	ring = &adev->vcn.inst[i].ring_enc[0];
201	((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);	238	if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
		239	ring->sched.ready = false;
		240	ring->no_scheduler = true;
		241	dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
		242	} else {
		243	ring->wptr = 0;
		244	ring->wptr_old = 0;
		245	vcn_v4_0_unified_ring_set_wptr(ring);
		246	ring->sched.ready = true;
		247	}
		248	}
		249	} else {
		250	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
		251	if (adev->vcn.harvest_config & (1 << i))
		252	continue;
202		253
203	r = amdgpu_ring_test_helper(ring);	254	ring = &adev->vcn.inst[i].ring_enc[0];
204	if (r)	255
205	goto done;	256	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
		257	((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
		258
		259	r = amdgpu_ring_test_helper(ring);
		260	if (r)
		261	goto done;
		262
		263	}
206	}	264	}
207		265
208	done:	266	done:
@@ -230,12 +288,14 @@ static int vcn_v4_0_hw_fini(void *handle) · 21 unmodified lines
230	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {	288	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
231	if (adev->vcn.harvest_config & (1 << i))	289	if (adev->vcn.harvest_config & (1 << i))
232	continue;	290	continue;
233		291	if (!amdgpu_sriov_vf(adev)) {
234	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) \|\|	292	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) \|\|
235	(adev->vcn.cur_state != AMD_PG_STATE_GATE &&	293	(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
236	RREG32_SOC15(VCN, i, regUVD_STATUS))) {	294	RREG32_SOC15(VCN, i, regUVD_STATUS))) {
237	vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);	295	vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
		296	}
238	}	297	}
		298
239	}	299	}
240		300
241	return 0;	301	return 0;
@@ -1107,6 +1167,214 @@ static int vcn_v4_0_start(struct amdgpu_device *adev) · 865 unmodified lines
1107	return 0;	1167	return 0;
1108	}	1168	}
1109		1169
		1170	static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
		1171	{
		1172	int i;
		1173	struct amdgpu_ring *ring_enc;
		1174	uint64_t cache_addr;
		1175	uint64_t rb_enc_addr;
		1176	uint64_t ctx_addr;
		1177	uint32_t param, resp, expected;
		1178	uint32_t offset, cache_size;
		1179	uint32_t tmp, timeout;
		1180
		1181	struct amdgpu_mm_table *table = &adev->virt.mm_table;
		1182	uint32_t *table_loc;
		1183	uint32_t table_size;
		1184	uint32_t size, size_dw;
		1185	uint32_t init_status;
		1186	uint32_t enabled_vcn;
		1187
		1188	struct mmsch_v4_0_cmd_direct_write
		1189	direct_wt = { {0} };
		1190	struct mmsch_v4_0_cmd_direct_read_modify_write
		1191	direct_rd_mod_wt = { {0} };
		1192	struct mmsch_v4_0_cmd_end end = { {0} };
		1193	struct mmsch_v4_0_init_header header;
		1194
		1195	volatile struct amdgpu_vcn4_fw_shared *fw_shared;
		1196	volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
		1197
		1198	direct_wt.cmd_header.command_type =
		1199	MMSCH_COMMAND__DIRECT_REG_WRITE;
		1200	direct_rd_mod_wt.cmd_header.command_type =
		1201	MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
		1202	end.cmd_header.command_type =
		1203	MMSCH_COMMAND__END;
		1204
		1205	header.version = MMSCH_VERSION;
		1206	header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2;
		1207	for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
		1208	header.inst[i].init_status = 0;
		1209	header.inst[i].table_offset = 0;
		1210	header.inst[i].table_size = 0;
		1211	}
		1212
		1213	table_loc = (uint32_t *)table->cpu_addr;
		1214	table_loc += header.total_size;
		1215	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
		1216	if (adev->vcn.harvest_config & (1 << i))
		1217	continue;
		1218
		1219	table_size = 0;
		1220
		1221	MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
		1222	regUVD_STATUS),
		1223	~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
		1224
		1225	cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
		1226
		1227	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
		1228	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1229	regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
		1230	adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
		1231	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1232	regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
		1233	adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
		1234	offset = 0;
		1235	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1236	regUVD_VCPU_CACHE_OFFSET0),
		1237	0);
		1238	} else {
		1239	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1240	regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
		1241	lower_32_bits(adev->vcn.inst[i].gpu_addr));
		1242	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1243	regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
		1244	upper_32_bits(adev->vcn.inst[i].gpu_addr));
		1245	offset = cache_size;
		1246	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1247	regUVD_VCPU_CACHE_OFFSET0),
		1248	AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
		1249	}
		1250
		1251	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1252	regUVD_VCPU_CACHE_SIZE0),
		1253	cache_size);
		1254
		1255	cache_addr = adev->vcn.inst[i].gpu_addr + offset;
		1256	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1257	regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
		1258	lower_32_bits(cache_addr));
		1259	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1260	regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
		1261	upper_32_bits(cache_addr));
		1262	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1263	regUVD_VCPU_CACHE_OFFSET1),
		1264	0);
		1265	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1266	regUVD_VCPU_CACHE_SIZE1),
		1267	AMDGPU_VCN_STACK_SIZE);
		1268
		1269	cache_addr = adev->vcn.inst[i].gpu_addr + offset +
		1270	AMDGPU_VCN_STACK_SIZE;
		1271	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1272	regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
		1273	lower_32_bits(cache_addr));
		1274	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1275	regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
		1276	upper_32_bits(cache_addr));
		1277	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1278	regUVD_VCPU_CACHE_OFFSET2),
		1279	0);
		1280	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1281	regUVD_VCPU_CACHE_SIZE2),
		1282	AMDGPU_VCN_CONTEXT_SIZE);
		1283
		1284	fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
		1285	rb_setup = &fw_shared->rb_setup;
		1286
		1287	ring_enc = &adev->vcn.inst[i].ring_enc[0];
		1288	ring_enc->wptr = 0;
		1289	rb_enc_addr = ring_enc->gpu_addr;
		1290
		1291	rb_setup->is_rb_enabled_flags \|= RB_ENABLED;
		1292	rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
		1293	rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
		1294	rb_setup->rb_size = ring_enc->ring_size / 4;
		1295	fw_shared->present_flag_0 \|= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
		1296
		1297	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1298	regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
		1299	lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
		1300	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1301	regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
		1302	upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
		1303	MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
		1304	regUVD_VCPU_NONCACHE_SIZE0),
		1305	AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
		1306
		1307	/* add end packet */
		1308	MMSCH_V4_0_INSERT_END();
		1309
		1310	/* refine header */
		1311	header.inst[i].init_status = 0;
		1312	header.inst[i].table_offset = header.total_size;
		1313	header.inst[i].table_size = table_size;
		1314	header.total_size += table_size;
		1315	}
		1316
		1317	/* Update init table header in memory */
		1318	size = sizeof(struct mmsch_v4_0_init_header);
		1319	table_loc = (uint32_t *)table->cpu_addr;
		1320	memcpy((void *)table_loc, &header, size);
		1321
		1322	/* message MMSCH (in VCN[0]) to initialize this client
		1323	* 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
		1324	* of memory descriptor location
		1325	*/
		1326	ctx_addr = table->gpu_addr;
		1327	WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
		1328	WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
		1329
		1330	/* 2, update vmid of descriptor */
		1331	tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
		1332	tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
		1333	/* use domain0 for MM scheduler */
		1334	tmp \|= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
		1335	WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
		1336
		1337	/* 3, notify mmsch about the size of this descriptor */
		1338	size = header.total_size;
		1339	WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size);
		1340
		1341	/* 4, set resp to zero */
		1342	WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0);
		1343
		1344	/* 5, kick off the initialization and wait until
		1345	* MMSCH_VF_MAILBOX_RESP becomes non-zero
		1346	*/
		1347	param = 0x00000001;
		1348	WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param);
		1349	tmp = 0;
		1350	timeout = 1000;
		1351	resp = 0;
		1352	expected = MMSCH_VF_MAILBOX_RESP__OK;
		1353	while (resp != expected) {
		1354	resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);
		1355	if (resp != 0)
		1356	break;
		1357
		1358	udelay(10);
		1359	tmp = tmp + 10;
		1360	if (tmp >= timeout) {
		1361	DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
		1362	" waiting for regMMSCH_VF_MAILBOX_RESP "\
		1363	"(expected=0x%08x, readback=0x%08x)\n",
		1364	tmp, expected, resp);
		1365	return -EBUSY;
		1366	}
		1367	}
		1368	enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
		1369	init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status;
		1370	if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
		1371	&& init_status != MMSCH_VF_ENGINE_STATUS__PASS)
		1372	DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
		1373	"status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
		1374
		1375	return 0;
		1376	}
		1377
1110	/**	1378	/**
1111	* vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode	1379	* vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode
1112	*	1380	*
@@ -1327,21 +1595,23 @@ static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) · 214 unmodified lines
1327	}	1595	}
1328	}	1596	}
1329		1597
1330	static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p)	1598	static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
		1599	struct amdgpu_job *job)
1331	{	1600	{
1332	struct drm_gpu_scheduler **scheds;	1601	struct drm_gpu_scheduler **scheds;
1333		1602
1334	/* The create msg must be in the first IB submitted */	1603	/* The create msg must be in the first IB submitted */
1335	if (atomic_read(&p->entity->fence_seq))	1604	if (atomic_read(&job->base.entity->fence_seq))
1336	return -EINVAL;	1605	return -EINVAL;
1337		1606
1338	scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]	1607	scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
1339	[AMDGPU_RING_PRIO_0].sched;	1608	[AMDGPU_RING_PRIO_0].sched;
1340	drm_sched_entity_modify_sched(p->entity, scheds, 1);	1609	drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
1341	return 0;	1610	return 0;
1342	}	1611	}
1343		1612
1344	static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)	1613	static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser p, struct amdgpu_job job,
		1614	uint64_t addr)
1345	{	1615	{
1346	struct ttm_operation_ctx ctx = { false, false };	1616	struct ttm_operation_ctx ctx = { false, false };
1347	struct amdgpu_bo_va_mapping *map;	1617	struct amdgpu_bo_va_mapping *map;
@@ -1412,7 +1682,7 @@ static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) · 64 unmodified lines
1412	if (create[0] == 0x7 \|\| create[0] == 0x10 \|\| create[0] == 0x11)	1682	if (create[0] == 0x7 \|\| create[0] == 0x10 \|\| create[0] == 0x11)
1413	continue;	1683	continue;
1414		1684
1415	r = vcn_v4_0_limit_sched(p);	1685	r = vcn_v4_0_limit_sched(p, job);
1416	if (r)	1686	if (r)
1417	goto out;	1687	goto out;
1418	}	1688	}
@@ -1425,32 +1695,34 @@ out: · 6 unmodified lines
1425	#define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003)	1695	#define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003)
1426		1696
1427	static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,	1697	static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1428	struct amdgpu_job *job,	1698	struct amdgpu_job *job,
1429	struct amdgpu_ib *ib)	1699	struct amdgpu_ib *ib)
1430	{	1700	{
1431	struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);	1701	struct amdgpu_ring *ring = amdgpu_job_ring(job);
1432	struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;	1702	struct amdgpu_vcn_decode_buffer *decode_buffer;
		1703	uint64_t addr;
1433	uint32_t val;	1704	uint32_t val;
1434	int r = 0;
1435		1705
1436	/* The first instance can decode anything */	1706	/* The first instance can decode anything */
1437	if (!ring->me)	1707	if (!ring->me)
1438	return r;	1708	return 0;
1439		1709
1440	/* unified queue ib header has 8 double words. */	1710	/* unified queue ib header has 8 double words. */
1441	if (ib->length_dw < 8)	1711	if (ib->length_dw < 8)
1442	return r;	1712	return 0;
1443		1713
1444	val = amdgpu_ib_get_value(ib, 6); //RADEON_VCN_ENGINE_TYPE	1714	val = amdgpu_ib_get_value(ib, 6); //RADEON_VCN_ENGINE_TYPE
		1715	if (val != RADEON_VCN_ENGINE_TYPE_DECODE)
		1716	return 0;
1445		1717
1446	if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {	1718	decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[10];
1447	decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[10];
1448		1719
1449	if (decode_buffer->valid_buf_flag & 0x1)	1720	if (!(decode_buffer->valid_buf_flag & 0x1))
1450	r = vcn_v4_0_dec_msg(p, ((u64)decode_buffer->msg_buffer_address_hi) << 32 \|	1721	return 0;
1451	decode_buffer->msg_buffer_address_lo);	1722
1452	}	1723	addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 \|
1453	return r;	1724	decode_buffer->msg_buffer_address_lo;
		1725	return vcn_v4_0_dec_msg(p, job, addr);
1454	}	1726	}
1455		1727
1456	static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {	1728	static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
@@ -1596,6 +1868,15 @@ static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_sta · 139 unmodified lines
1596	struct amdgpu_device adev = (struct amdgpu_device )handle;	1868	struct amdgpu_device adev = (struct amdgpu_device )handle;
1597	int ret;	1869	int ret;
1598		1870
		1871	/* for SRIOV, guest should not control VCN Power-gating
		1872	* MMSCH FW should control Power-gating and clock-gating
		1873	* guest should avoid touching CGC and PG
		1874	*/
		1875	if (amdgpu_sriov_vf(adev)) {
		1876	adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
		1877	return 0;
		1878	}
		1879
1599	if(state == adev->vcn.cur_state)	1880	if(state == adev->vcn.cur_state)
1600	return 0;	1881	return 0;
1601		1882

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h+387−384

@@ -742,7 +742,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { · 741 unmodified lines
742	0xbf88fffe, 0x877aff7f,	742	0xbf88fffe, 0x877aff7f,
743	0x04000000, 0x8f7a857a,	743	0x04000000, 0x8f7a857a,
744	0x886d7a6d, 0xb97b02dc,	744	0x886d7a6d, 0xb97b02dc,
745	0x8f7b997b, 0xb97a2a05,	745	0x8f7b997b, 0xb97a3a05,
746	0x807a817a, 0xbf0d997b,	746	0x807a817a, 0xbf0d997b,
747	0xbf850002, 0x8f7a897a,	747	0xbf850002, 0x8f7a897a,
748	0xbf820001, 0x8f7a8a7a,	748	0xbf820001, 0x8f7a8a7a,
@@ -819,7 +819,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { · 70 unmodified lines
819	0xbefe037c, 0xbefc0370,	819	0xbefe037c, 0xbefc0370,
820	0xf4611c7a, 0xf8000000,	820	0xf4611c7a, 0xf8000000,
821	0x80708470, 0xbefc037e,	821	0x80708470, 0xbefc037e,
822	0xb9702a05, 0x80708170,	822	0xb9703a05, 0x80708170,
823	0xbf0d9973, 0xbf850002,	823	0xbf0d9973, 0xbf850002,
824	0x8f708970, 0xbf820001,	824	0x8f708970, 0xbf820001,
825	0x8f708a70, 0xb97a1e06,	825	0x8f708a70, 0xb97a1e06,
@@ -1069,7 +1069,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { · 243 unmodified lines
1069	0xb9f9f816, 0x876f7bff,	1069	0xb9f9f816, 0x876f7bff,
1070	0xfffff800, 0x906f8b6f,	1070	0xfffff800, 0x906f8b6f,
1071	0xb9efa2c3, 0xb9f3f801,	1071	0xb9efa2c3, 0xb9f3f801,
1072	0xb96e2a05, 0x806e816e,	1072	0xb96e3a05, 0x806e816e,
1073	0xbf0d9972, 0xbf850002,	1073	0xbf0d9972, 0xbf850002,
1074	0x8f6e896e, 0xbf820001,	1074	0x8f6e896e, 0xbf820001,
1075	0x8f6e8a6e, 0xb96f1e06,	1075	0x8f6e8a6e, 0xb96f1e06,
@@ -2114,7 +2114,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 1038 unmodified lines
2114	0x007a0000, 0x7e000280,	2114	0x007a0000, 0x7e000280,
2115	0xbefe037a, 0xbeff037b,	2115	0xbefe037a, 0xbeff037b,
2116	0xb97b02dc, 0x8f7b997b,	2116	0xb97b02dc, 0x8f7b997b,
2117	0xb97a2a05, 0x807a817a,	2117	0xb97a3a05, 0x807a817a,
2118	0xbf0d997b, 0xbf850002,	2118	0xbf0d997b, 0xbf850002,
2119	0x8f7a897a, 0xbf820001,	2119	0x8f7a897a, 0xbf820001,
2120	0x8f7a8a7a, 0xb97b1e06,	2120	0x8f7a8a7a, 0xb97b1e06,
@@ -2157,7 +2157,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 36 unmodified lines
2157	0x01000000, 0xe0704100,	2157	0x01000000, 0xe0704100,
2158	0x705d0100, 0xe0704200,	2158	0x705d0100, 0xe0704200,
2159	0x705d0200, 0xe0704300,	2159	0x705d0200, 0xe0704300,
2160	0x705d0300, 0xb9702a05,	2160	0x705d0300, 0xb9703a05,
2161	0x80708170, 0xbf0d9973,	2161	0x80708170, 0xbf0d9973,
2162	0xbf850002, 0x8f708970,	2162	0xbf850002, 0x8f708970,
2163	0xbf820001, 0x8f708a70,	2163	0xbf820001, 0x8f708a70,
@@ -2189,7 +2189,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 25 unmodified lines
2189	0xbefe03ff, 0x0000ffff,	2189	0xbefe03ff, 0x0000ffff,
2190	0xbeff0380, 0xe0704000,	2190	0xbeff0380, 0xe0704000,
2191	0x705d0200, 0xbefe03c1,	2191	0x705d0200, 0xbefe03c1,
2192	0xb9702a05, 0x80708170,	2192	0xb9703a05, 0x80708170,
2193	0xbf0d9973, 0xbf850002,	2193	0xbf0d9973, 0xbf850002,
2194	0x8f708970, 0xbf820001,	2194	0x8f708970, 0xbf820001,
2195	0x8f708a70, 0xb97a1e06,	2195	0x8f708a70, 0xb97a1e06,
@@ -2475,7 +2475,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 279 unmodified lines
2475	0xb9ef4803, 0x876f7bff,	2475	0xb9ef4803, 0x876f7bff,
2476	0xfffff800, 0x906f8b6f,	2476	0xfffff800, 0x906f8b6f,
2477	0xb9efa2c3, 0xb9f3f801,	2477	0xb9efa2c3, 0xb9f3f801,
2478	0xb96e2a05, 0x806e816e,	2478	0xb96e3a05, 0x806e816e,
2479	0xbf0d9972, 0xbf850002,	2479	0xbf0d9972, 0xbf850002,
2480	0x8f6e896e, 0xbf820001,	2480	0x8f6e896e, 0xbf820001,
2481	0x8f6e8a6e, 0xb96f1e06,	2481	0x8f6e8a6e, 0xb96f1e06,
@@ -2494,438 +2494,441 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { · 12 unmodified lines
2494	0xbf9f0000, 0xbf9f0000,	2494	0xbf9f0000, 0xbf9f0000,
2495	0xbf9f0000, 0x00000000,	2495	0xbf9f0000, 0x00000000,
2496	};	2496	};
2497
2498	static const uint32_t cwsr_trap_gfx11_hex[] = {	2497	static const uint32_t cwsr_trap_gfx11_hex[] = {
2499	0xbfa00001, 0xbfa0021b,	2498	0xbfa00001, 0xbfa0021e,
2500	0xb0804006, 0xb8f8f802,	2499	0xb0804006, 0xb8f8f802,
2501	0x91788678, 0xb8fbf803,	2500	0x9178ff78, 0x00020006,
2502	0x8b6eff78, 0x00002000,	2501	0xb8fbf803, 0xbf0d9f6d,
2503	0xbfa10009, 0x8b6eff6d,	2502	0xbfa20006, 0x8b6eff78,
2504	0x00ff0000, 0xbfa2001e,	2503	0x00002000, 0xbfa10009,
2505	0x8b6eff7b, 0x00000400,
2506	0xbfa20041, 0xbf830010,
2507	0xb8fbf803, 0xbfa0fffa,
2508	0x8b6eff7b, 0x00000900,
2509	0xbfa20015, 0x8b6eff7b,
2510	0x000071ff, 0xbfa10008,
2511	0x8b6fff7b, 0x00007080,
2512	0xbfa10001, 0xbeee1287,
2513	0xb8eff801, 0x846e8c6e,
2514	0x8b6e6f6e, 0xbfa2000a,
2515	0x8b6eff6d, 0x00ff0000,	2504	0x8b6eff6d, 0x00ff0000,
2516	0xbfa20007, 0xb8eef801,	2505	0xbfa2001e, 0x8b6eff7b,
2517	0x8b6eff6e, 0x00000800,	2506	0x00000400, 0xbfa20041,
2518	0xbfa20003, 0x8b6eff7b,	2507	0xbf830010, 0xb8fbf803,
2519	0x00000400, 0xbfa20026,	2508	0xbfa0fffa, 0x8b6eff7b,
2520	0xbefa4d82, 0xbf89fc07,	2509	0x00000900, 0xbfa20015,
2521	0x84fa887a, 0xf4005bbd,	2510	0x8b6eff7b, 0x000071ff,
2522	0xf8000010, 0xbf89fc07,	2511	0xbfa10008, 0x8b6fff7b,
2523	0x846e976e, 0x9177ff77,	2512	0x00007080, 0xbfa10001,
2524	0x00800000, 0x8c776e77,	2513	0xbeee1287, 0xb8eff801,
2525	0xf4045bbd, 0xf8000000,	2514	0x846e8c6e, 0x8b6e6f6e,
2526	0xbf89fc07, 0xf4045ebd,	2515	0xbfa2000a, 0x8b6eff6d,
2527	0xf8000008, 0xbf89fc07,	2516	0x00ff0000, 0xbfa20007,
2528	0x8bee6e6e, 0xbfa10001,	2517	0xb8eef801, 0x8b6eff6e,
2529	0xbe80486e, 0x8b6eff6d,	2518	0x00000800, 0xbfa20003,
2530	0x01ff0000, 0xbfa20005,	2519	0x8b6eff7b, 0x00000400,
2531	0x8c78ff78, 0x00002000,	2520	0xbfa20026, 0xbefa4d82,
2532	0x80ec886c, 0x82ed806d,	2521	0xbf89fc07, 0x84fa887a,
2533	0xbfa00005, 0x8b6eff6d,	2522	0xf4005bbd, 0xf8000010,
2534	0x01000000, 0xbfa20002,	2523	0xbf89fc07, 0x846e976e,
2535	0x806c846c, 0x826d806d,	2524	0x9177ff77, 0x00800000,
2536	0x8b6dff6d, 0x0000ffff,	2525	0x8c776e77, 0xf4045bbd,
2537	0x8bfe7e7e, 0x8bea6a6a,	2526	0xf8000000, 0xbf89fc07,
2538	0xb978f802, 0xbe804a6c,	2527	0xf4045ebd, 0xf8000008,
2539	0x8b6dff6d, 0x0000ffff,	2528	0xbf89fc07, 0x8bee6e6e,
2540	0xbefa0080, 0xb97a0283,	2529	0xbfa10001, 0xbe80486e,
2541	0xbeee007e, 0xbeef007f,	2530	0x8b6eff6d, 0x01ff0000,
2542	0xbefe0180, 0xbefe4d84,	2531	0xbfa20005, 0x8c78ff78,
2543	0xbf89fc07, 0x8b7aff7f,	2532	0x00002000, 0x80ec886c,
2544	0x04000000, 0x847a857a,	2533	0x82ed806d, 0xbfa00005,
2545	0x8c6d7a6d, 0xbefa007e,	2534	0x8b6eff6d, 0x01000000,
2546	0x8b7bff7f, 0x0000ffff,	2535	0xbfa20002, 0x806c846c,
2547	0xbefe00c1, 0xbeff00c1,	2536	0x826d806d, 0x8b6dff6d,
2548	0xdca6c000, 0x007a0000,	2537	0x0000ffff, 0x8bfe7e7e,
2549	0x7e000280, 0xbefe007a,	2538	0x8bea6a6a, 0xb978f802,
2550	0xbeff007b, 0xb8fb02dc,	2539	0xbe804a6c, 0x8b6dff6d,
2551	0x847b997b, 0xb8fa3b05,	2540	0x0000ffff, 0xbefa0080,
2552	0x807a817a, 0xbf0d997b,	2541	0xb97a0283, 0xbeee007e,
2553	0xbfa20002, 0x847a897a,	2542	0xbeef007f, 0xbefe0180,
2554	0xbfa00001, 0x847a8a7a,	2543	0xbefe4d84, 0xbf89fc07,
2555	0xb8fb1e06, 0x847b8a7b,	2544	0x8b7aff7f, 0x04000000,
2556	0x807a7b7a, 0x8b7bff7f,	2545	0x847a857a, 0x8c6d7a6d,
2557	0x0000ffff, 0x807aff7a,	2546	0xbefa007e, 0x8b7bff7f,
2558	0x00000200, 0x807a7e7a,	2547	0x0000ffff, 0xbefe00c1,
2559	0x827b807b, 0xd7610000,	2548	0xbeff00c1, 0xdca6c000,
2560	0x00010870, 0xd7610000,	2549	0x007a0000, 0x7e000280,
2561	0x00010a71, 0xd7610000,
2562	0x00010c72, 0xd7610000,
2563	0x00010e73, 0xd7610000,
2564	0x00011074, 0xd7610000,
2565	0x00011275, 0xd7610000,
2566	0x00011476, 0xd7610000,
2567	0x00011677, 0xd7610000,
2568	0x00011a79, 0xd7610000,
2569	0x00011c7e, 0xd7610000,
2570	0x00011e7f, 0xbefe00ff,
2571	0x00003fff, 0xbeff0080,
2572	0xdca6c040, 0x007a0000,
2573	0xd760007a, 0x00011d00,
2574	0xd760007b, 0x00011f00,
2575	0xbefe007a, 0xbeff007b,	2550	0xbefe007a, 0xbeff007b,
2576	0xbef4007e, 0x8b75ff7f,	2551	0xb8fb02dc, 0x847b997b,
2577	0x0000ffff, 0x8c75ff75,	2552	0xb8fa3b05, 0x807a817a,
2578	0x00040000, 0xbef60080,	2553	0xbf0d997b, 0xbfa20002,
2579	0xbef700ff, 0x10807fac,	2554	0x847a897a, 0xbfa00001,
2580	0xbef1007d, 0xbef00080,	2555	0x847a8a7a, 0xb8fb1e06,
2581	0xb8f302dc, 0x84739973,	2556	0x847b8a7b, 0x807a7b7a,
2582	0xbefe00c1, 0x857d9973,	2557	0x8b7bff7f, 0x0000ffff,
2583	0x8b7d817d, 0xbf06817d,	2558	0x807aff7a, 0x00000200,
2584	0xbfa20002, 0xbeff0080,	2559	0x807a7e7a, 0x827b807b,
2585	0xbfa00002, 0xbeff00c1,	2560	0xd7610000, 0x00010870,
2586	0xbfa00009, 0xbef600ff,	2561	0xd7610000, 0x00010a71,
2587	0x01000000, 0xe0685080,	2562	0xd7610000, 0x00010c72,
2588	0x701d0100, 0xe0685100,	2563	0xd7610000, 0x00010e73,
2589	0x701d0200, 0xe0685180,	2564	0xd7610000, 0x00011074,
2590	0x701d0300, 0xbfa00008,	2565	0xd7610000, 0x00011275,
		2566	0xd7610000, 0x00011476,
		2567	0xd7610000, 0x00011677,
		2568	0xd7610000, 0x00011a79,
		2569	0xd7610000, 0x00011c7e,
		2570	0xd7610000, 0x00011e7f,
		2571	0xbefe00ff, 0x00003fff,
		2572	0xbeff0080, 0xdca6c040,
		2573	0x007a0000, 0xd760007a,
		2574	0x00011d00, 0xd760007b,
		2575	0x00011f00, 0xbefe007a,
		2576	0xbeff007b, 0xbef4007e,
		2577	0x8b75ff7f, 0x0000ffff,
		2578	0x8c75ff75, 0x00040000,
		2579	0xbef60080, 0xbef700ff,
		2580	0x10807fac, 0xbef1007d,
		2581	0xbef00080, 0xb8f302dc,
		2582	0x84739973, 0xbefe00c1,
		2583	0x857d9973, 0x8b7d817d,
		2584	0xbf06817d, 0xbfa20002,
		2585	0xbeff0080, 0xbfa00002,
		2586	0xbeff00c1, 0xbfa00009,
2591	0xbef600ff, 0x01000000,	2587	0xbef600ff, 0x01000000,
2592	0xe0685100, 0x701d0100,	2588	0xe0685080, 0x701d0100,
2593	0xe0685200, 0x701d0200,	2589	0xe0685100, 0x701d0200,
2594	0xe0685300, 0x701d0300,	2590	0xe0685180, 0x701d0300,
		2591	0xbfa00008, 0xbef600ff,
		2592	0x01000000, 0xe0685100,
		2593	0x701d0100, 0xe0685200,
		2594	0x701d0200, 0xe0685300,
		2595	0x701d0300, 0xb8f03b05,
		2596	0x80708170, 0xbf0d9973,
		2597	0xbfa20002, 0x84708970,
		2598	0xbfa00001, 0x84708a70,
		2599	0xb8fa1e06, 0x847a8a7a,
		2600	0x80707a70, 0x8070ff70,
		2601	0x00000200, 0xbef600ff,
		2602	0x01000000, 0x7e000280,
		2603	0x7e020280, 0x7e040280,
		2604	0xbefd0080, 0xd7610002,
		2605	0x0000fa71, 0x807d817d,
		2606	0xd7610002, 0x0000fa6c,
		2607	0x807d817d, 0x917aff6d,
		2608	0x80000000, 0xd7610002,
		2609	0x0000fa7a, 0x807d817d,
		2610	0xd7610002, 0x0000fa6e,
		2611	0x807d817d, 0xd7610002,
		2612	0x0000fa6f, 0x807d817d,
		2613	0xd7610002, 0x0000fa78,
		2614	0x807d817d, 0xb8faf803,
		2615	0xd7610002, 0x0000fa7a,
		2616	0x807d817d, 0xd7610002,
		2617	0x0000fa7b, 0x807d817d,
		2618	0xb8f1f801, 0xd7610002,
		2619	0x0000fa71, 0x807d817d,
		2620	0xb8f1f814, 0xd7610002,
		2621	0x0000fa71, 0x807d817d,
		2622	0xb8f1f815, 0xd7610002,
		2623	0x0000fa71, 0x807d817d,
		2624	0xbefe00ff, 0x0000ffff,
		2625	0xbeff0080, 0xe0685000,
		2626	0x701d0200, 0xbefe00c1,
2595	0xb8f03b05, 0x80708170,	2627	0xb8f03b05, 0x80708170,
2596	0xbf0d9973, 0xbfa20002,	2628	0xbf0d9973, 0xbfa20002,
2597	0x84708970, 0xbfa00001,	2629	0x84708970, 0xbfa00001,
2598	0x84708a70, 0xb8fa1e06,	2630	0x84708a70, 0xb8fa1e06,
2599	0x847a8a7a, 0x80707a70,	2631	0x847a8a7a, 0x80707a70,
2600	0x8070ff70, 0x00000200,
2601	0xbef600ff, 0x01000000,	2632	0xbef600ff, 0x01000000,
2602	0x7e000280, 0x7e020280,	2633	0xbef90080, 0xbefd0080,
2603	0x7e040280, 0xbefd0080,	2634	0xbf800000, 0xbe804100,
2604	0xd7610002, 0x0000fa71,	2635	0xbe824102, 0xbe844104,
2605	0x807d817d, 0xd7610002,	2636	0xbe864106, 0xbe884108,
2606	0x0000fa6c, 0x807d817d,	2637	0xbe8a410a, 0xbe8c410c,
2607	0x917aff6d, 0x80000000,	2638	0xbe8e410e, 0xd7610002,
2608	0xd7610002, 0x0000fa7a,	2639	0x0000f200, 0x80798179,
2609	0x807d817d, 0xd7610002,	2640	0xd7610002, 0x0000f201,
2610	0x0000fa6e, 0x807d817d,
2611	0xd7610002, 0x0000fa6f,
2612	0x807d817d, 0xd7610002,
2613	0x0000fa78, 0x807d817d,
2614	0xb8faf803, 0xd7610002,
2615	0x0000fa7a, 0x807d817d,
2616	0xd7610002, 0x0000fa7b,
2617	0x807d817d, 0xb8f1f801,
2618	0xd7610002, 0x0000fa71,
2619	0x807d817d, 0xb8f1f814,
2620	0xd7610002, 0x0000fa71,
2621	0x807d817d, 0xb8f1f815,
2622	0xd7610002, 0x0000fa71,
2623	0x807d817d, 0xbefe00ff,
2624	0x0000ffff, 0xbeff0080,
2625	0xe0685000, 0x701d0200,
2626	0xbefe00c1, 0xb8f03b05,
2627	0x80708170, 0xbf0d9973,
2628	0xbfa20002, 0x84708970,
2629	0xbfa00001, 0x84708a70,
2630	0xb8fa1e06, 0x847a8a7a,
2631	0x80707a70, 0xbef600ff,
2632	0x01000000, 0xbef90080,
2633	0xbefd0080, 0xbf800000,
2634	0xbe804100, 0xbe824102,
2635	0xbe844104, 0xbe864106,
2636	0xbe884108, 0xbe8a410a,
2637	0xbe8c410c, 0xbe8e410e,
2638	0xd7610002, 0x0000f200,
2639	0x80798179, 0xd7610002,
2640	0x0000f201, 0x80798179,
2641	0xd7610002, 0x0000f202,
2642	0x80798179, 0xd7610002,
2643	0x0000f203, 0x80798179,
2644	0xd7610002, 0x0000f204,
2645	0x80798179, 0xd7610002,	2641	0x80798179, 0xd7610002,
2646	0x0000f205, 0x80798179,	2642	0x0000f202, 0x80798179,
2647	0xd7610002, 0x0000f206,	2643	0xd7610002, 0x0000f203,
2648	0x80798179, 0xd7610002,	2644	0x80798179, 0xd7610002,
2649	0x0000f207, 0x80798179,	2645	0x0000f204, 0x80798179,
2650	0xd7610002, 0x0000f208,	2646	0xd7610002, 0x0000f205,
2651	0x80798179, 0xd7610002,	2647	0x80798179, 0xd7610002,
2652	0x0000f209, 0x80798179,	2648	0x0000f206, 0x80798179,
2653	0xd7610002, 0x0000f20a,	2649	0xd7610002, 0x0000f207,
2654	0x80798179, 0xd7610002,	2650	0x80798179, 0xd7610002,
2655	0x0000f20b, 0x80798179,	2651	0x0000f208, 0x80798179,
2656	0xd7610002, 0x0000f20c,	2652	0xd7610002, 0x0000f209,
2657	0x80798179, 0xd7610002,	2653	0x80798179, 0xd7610002,
2658	0x0000f20d, 0x80798179,	2654	0x0000f20a, 0x80798179,
2659	0xd7610002, 0x0000f20e,	2655	0xd7610002, 0x0000f20b,
2660	0x80798179, 0xd7610002,	2656	0x80798179, 0xd7610002,
2661	0x0000f20f, 0x80798179,	2657	0x0000f20c, 0x80798179,
2662	0xbf06a079, 0xbfa10006,	2658	0xd7610002, 0x0000f20d,
2663	0xe0685000, 0x701d0200,
2664	0x8070ff70, 0x00000080,
2665	0xbef90080, 0x7e040280,
2666	0x807d907d, 0xbf0aff7d,
2667	0x00000060, 0xbfa2ffbc,
2668	0xbe804100, 0xbe824102,
2669	0xbe844104, 0xbe864106,
2670	0xbe884108, 0xbe8a410a,
2671	0xd7610002, 0x0000f200,
2672	0x80798179, 0xd7610002,	2659	0x80798179, 0xd7610002,
2673	0x0000f201, 0x80798179,	2660	0x0000f20e, 0x80798179,
2674	0xd7610002, 0x0000f202,	2661	0xd7610002, 0x0000f20f,
		2662	0x80798179, 0xbf06a079,
		2663	0xbfa10006, 0xe0685000,
		2664	0x701d0200, 0x8070ff70,
		2665	0x00000080, 0xbef90080,
		2666	0x7e040280, 0x807d907d,
		2667	0xbf0aff7d, 0x00000060,
		2668	0xbfa2ffbc, 0xbe804100,
		2669	0xbe824102, 0xbe844104,
		2670	0xbe864106, 0xbe884108,
		2671	0xbe8a410a, 0xd7610002,
		2672	0x0000f200, 0x80798179,
		2673	0xd7610002, 0x0000f201,
2675	0x80798179, 0xd7610002,	2674	0x80798179, 0xd7610002,
2676	0x0000f203, 0x80798179,	2675	0x0000f202, 0x80798179,
2677	0xd7610002, 0x0000f204,	2676	0xd7610002, 0x0000f203,
2678	0x80798179, 0xd7610002,	2677	0x80798179, 0xd7610002,
2679	0x0000f205, 0x80798179,	2678	0x0000f204, 0x80798179,
2680	0xd7610002, 0x0000f206,	2679	0xd7610002, 0x0000f205,
2681	0x80798179, 0xd7610002,	2680	0x80798179, 0xd7610002,
2682	0x0000f207, 0x80798179,	2681	0x0000f206, 0x80798179,
2683	0xd7610002, 0x0000f208,	2682	0xd7610002, 0x0000f207,
2684	0x80798179, 0xd7610002,	2683	0x80798179, 0xd7610002,
2685	0x0000f209, 0x80798179,	2684	0x0000f208, 0x80798179,
2686	0xd7610002, 0x0000f20a,	2685	0xd7610002, 0x0000f209,
2687	0x80798179, 0xd7610002,	2686	0x80798179, 0xd7610002,
2688	0x0000f20b, 0x80798179,	2687	0x0000f20a, 0x80798179,
2689	0xe0685000, 0x701d0200,	2688	0xd7610002, 0x0000f20b,
		2689	0x80798179, 0xe0685000,
		2690	0x701d0200, 0xbefe00c1,
		2691	0x857d9973, 0x8b7d817d,
		2692	0xbf06817d, 0xbfa20002,
		2693	0xbeff0080, 0xbfa00001,
		2694	0xbeff00c1, 0xb8fb4306,
		2695	0x8b7bc17b, 0xbfa10044,
		2696	0xbfbd0000, 0x8b7aff6d,
		2697	0x80000000, 0xbfa10040,
		2698	0x847b867b, 0x847b827b,
		2699	0xbef6007b, 0xb8f03b05,
		2700	0x80708170, 0xbf0d9973,
		2701	0xbfa20002, 0x84708970,
		2702	0xbfa00001, 0x84708a70,
		2703	0xb8fa1e06, 0x847a8a7a,
		2704	0x80707a70, 0x8070ff70,
		2705	0x00000200, 0x8070ff70,
		2706	0x00000080, 0xbef600ff,
		2707	0x01000000, 0xd71f0000,
		2708	0x000100c1, 0xd7200000,
		2709	0x000200c1, 0x16000084,
		2710	0x857d9973, 0x8b7d817d,
		2711	0xbf06817d, 0xbefd0080,
		2712	0xbfa20012, 0xbe8300ff,
		2713	0x00000080, 0xbf800000,
		2714	0xbf800000, 0xbf800000,
		2715	0xd8d80000, 0x01000000,
		2716	0xbf890000, 0xe0685000,
		2717	0x701d0100, 0x807d037d,
		2718	0x80700370, 0xd5250000,
		2719	0x0001ff00, 0x00000080,
		2720	0xbf0a7b7d, 0xbfa2fff4,
		2721	0xbfa00011, 0xbe8300ff,
		2722	0x00000100, 0xbf800000,
		2723	0xbf800000, 0xbf800000,
		2724	0xd8d80000, 0x01000000,
		2725	0xbf890000, 0xe0685000,
		2726	0x701d0100, 0x807d037d,
		2727	0x80700370, 0xd5250000,
		2728	0x0001ff00, 0x00000100,
		2729	0xbf0a7b7d, 0xbfa2fff4,
2690	0xbefe00c1, 0x857d9973,	2730	0xbefe00c1, 0x857d9973,
2691	0x8b7d817d, 0xbf06817d,	2731	0x8b7d817d, 0xbf06817d,
2692	0xbfa20002, 0xbeff0080,	2732	0xbfa20004, 0xbef000ff,
2693	0xbfa00001, 0xbeff00c1,	2733	0x00000200, 0xbeff0080,
2694	0xb8fb4306, 0x8b7bc17b,	2734	0xbfa00003, 0xbef000ff,
2695	0xbfa10044, 0xbfbd0000,	2735	0x00000400, 0xbeff00c1,
2696	0x8b7aff6d, 0x80000000,	2736	0xb8fb3b05, 0x807b817b,
2697	0xbfa10040, 0x847b867b,	2737	0x847b827b, 0x857d9973,
2698	0x847b827b, 0xbef6007b,
2699	0xb8f03b05, 0x80708170,
2700	0xbf0d9973, 0xbfa20002,
2701	0x84708970, 0xbfa00001,
2702	0x84708a70, 0xb8fa1e06,
2703	0x847a8a7a, 0x80707a70,
2704	0x8070ff70, 0x00000200,
2705	0x8070ff70, 0x00000080,
2706	0xbef600ff, 0x01000000,
2707	0xd71f0000, 0x000100c1,
2708	0xd7200000, 0x000200c1,
2709	0x16000084, 0x857d9973,
2710	0x8b7d817d, 0xbf06817d,	2738	0x8b7d817d, 0xbf06817d,
2711	0xbefd0080, 0xbfa20012,	2739	0xbfa20017, 0xbef600ff,
2712	0xbe8300ff, 0x00000080,	2740	0x01000000, 0xbefd0084,
2713	0xbf800000, 0xbf800000,	2741	0xbf0a7b7d, 0xbfa10037,
2714	0xbf800000, 0xd8d80000,	2742	0x7e008700, 0x7e028701,
2715	0x01000000, 0xbf890000,	2743	0x7e048702, 0x7e068703,
2716	0xe0685000, 0x701d0100,	2744	0xe0685000, 0x701d0000,
2717	0x807d037d, 0x80700370,	2745	0xe0685080, 0x701d0100,
2718	0xd5250000, 0x0001ff00,	2746	0xe0685100, 0x701d0200,
2719	0x00000080, 0xbf0a7b7d,	2747	0xe0685180, 0x701d0300,
2720	0xbfa2fff4, 0xbfa00011,	2748	0x807d847d, 0x8070ff70,
2721	0xbe8300ff, 0x00000100,	2749	0x00000200, 0xbf0a7b7d,
2722	0xbf800000, 0xbf800000,	2750	0xbfa2ffef, 0xbfa00025,
2723	0xbf800000, 0xd8d80000,
2724	0x01000000, 0xbf890000,
2725	0xe0685000, 0x701d0100,
2726	0x807d037d, 0x80700370,
2727	0xd5250000, 0x0001ff00,
2728	0x00000100, 0xbf0a7b7d,
2729	0xbfa2fff4, 0xbefe00c1,
2730	0x857d9973, 0x8b7d817d,
2731	0xbf06817d, 0xbfa20004,
2732	0xbef000ff, 0x00000200,
2733	0xbeff0080, 0xbfa00003,
2734	0xbef000ff, 0x00000400,
2735	0xbeff00c1, 0xb8fb3b05,
2736	0x807b817b, 0x847b827b,
2737	0x857d9973, 0x8b7d817d,
2738	0xbf06817d, 0xbfa20017,
2739	0xbef600ff, 0x01000000,	2751	0xbef600ff, 0x01000000,
2740	0xbefd0084, 0xbf0a7b7d,	2752	0xbefd0084, 0xbf0a7b7d,
2741	0xbfa10037, 0x7e008700,	2753	0xbfa10011, 0x7e008700,
2742	0x7e028701, 0x7e048702,	2754	0x7e028701, 0x7e048702,
2743	0x7e068703, 0xe0685000,	2755	0x7e068703, 0xe0685000,
2744	0x701d0000, 0xe0685080,	2756	0x701d0000, 0xe0685100,
2745	0x701d0100, 0xe0685100,	2757	0x701d0100, 0xe0685200,
2746	0x701d0200, 0xe0685180,	2758	0x701d0200, 0xe0685300,
2747	0x701d0300, 0x807d847d,	2759	0x701d0300, 0x807d847d,
2748	0x8070ff70, 0x00000200,	2760	0x8070ff70, 0x00000400,
2749	0xbf0a7b7d, 0xbfa2ffef,	2761	0xbf0a7b7d, 0xbfa2ffef,
2750	0xbfa00025, 0xbef600ff,	2762	0xb8fb1e06, 0x8b7bc17b,
2751	0x01000000, 0xbefd0084,	2763	0xbfa1000c, 0x847b837b,
2752	0xbf0a7b7d, 0xbfa10011,	2764	0x807b7d7b, 0xbefe00c1,
2753	0x7e008700, 0x7e028701,	2765	0xbeff0080, 0x7e008700,
2754	0x7e048702, 0x7e068703,
2755	0xe0685000, 0x701d0000,	2766	0xe0685000, 0x701d0000,
2756	0xe0685100, 0x701d0100,	2767	0x807d817d, 0x8070ff70,
2757	0xe0685200, 0x701d0200,	2768	0x00000080, 0xbf0a7b7d,
2758	0xe0685300, 0x701d0300,	2769	0xbfa2fff8, 0xbfa00146,
2759	0x807d847d, 0x8070ff70,	2770	0xbef4007e, 0x8b75ff7f,
2760	0x00000400, 0xbf0a7b7d,	2771	0x0000ffff, 0x8c75ff75,
2761	0xbfa2ffef, 0xb8fb1e06,	2772	0x00040000, 0xbef60080,
2762	0x8b7bc17b, 0xbfa1000c,	2773	0xbef700ff, 0x10807fac,
2763	0x847b837b, 0x807b7d7b,	2774	0xb8f202dc, 0x84729972,
2764	0xbefe00c1, 0xbeff0080,	2775	0x8b6eff7f, 0x04000000,
2765	0x7e008700, 0xe0685000,	2776	0xbfa1003a, 0xbefe00c1,
2766	0x701d0000, 0x807d817d,	2777	0x857d9972, 0x8b7d817d,
2767	0x8070ff70, 0x00000080,	2778	0xbf06817d, 0xbfa20002,
2768	0xbf0a7b7d, 0xbfa2fff8,	2779	0xbeff0080, 0xbfa00001,
2769	0xbfa00141, 0xbef4007e,	2780	0xbeff00c1, 0xb8ef4306,
2770	0x8b75ff7f, 0x0000ffff,	2781	0x8b6fc16f, 0xbfa1002f,
2771	0x8c75ff75, 0x00040000,	2782	0x846f866f, 0x846f826f,
2772	0xbef60080, 0xbef700ff,	2783	0xbef6006f, 0xb8f83b05,
2773	0x10807fac, 0xb8f202dc,	2784	0x80788178, 0xbf0d9972,
2774	0x84729972, 0x8b6eff7f,	2785	0xbfa20002, 0x84788978,
2775	0x04000000, 0xbfa1003a,	2786	0xbfa00001, 0x84788a78,
		2787	0xb8ee1e06, 0x846e8a6e,
		2788	0x80786e78, 0x8078ff78,
		2789	0x00000200, 0x8078ff78,
		2790	0x00000080, 0xbef600ff,
		2791	0x01000000, 0x857d9972,
		2792	0x8b7d817d, 0xbf06817d,
		2793	0xbefd0080, 0xbfa2000c,
		2794	0xe0500000, 0x781d0000,
		2795	0xbf8903f7, 0xdac00000,
		2796	0x00000000, 0x807dff7d,
		2797	0x00000080, 0x8078ff78,
		2798	0x00000080, 0xbf0a6f7d,
		2799	0xbfa2fff5, 0xbfa0000b,
		2800	0xe0500000, 0x781d0000,
		2801	0xbf8903f7, 0xdac00000,
		2802	0x00000000, 0x807dff7d,
		2803	0x00000100, 0x8078ff78,
		2804	0x00000100, 0xbf0a6f7d,
		2805	0xbfa2fff5, 0xbef80080,
2776	0xbefe00c1, 0x857d9972,	2806	0xbefe00c1, 0x857d9972,
2777	0x8b7d817d, 0xbf06817d,	2807	0x8b7d817d, 0xbf06817d,
2778	0xbfa20002, 0xbeff0080,	2808	0xbfa20002, 0xbeff0080,
2779	0xbfa00001, 0xbeff00c1,	2809	0xbfa00001, 0xbeff00c1,
2780	0xb8ef4306, 0x8b6fc16f,	2810	0xb8ef3b05, 0x806f816f,
2781	0xbfa1002f, 0x846f866f,	2811	0x846f826f, 0x857d9972,
2782	0x846f826f, 0xbef6006f,	2812	0x8b7d817d, 0xbf06817d,
2783	0xb8f83b05, 0x80788178,	2813	0xbfa20024, 0xbef600ff,
2784	0xbf0d9972, 0xbfa20002,	2814	0x01000000, 0xbeee0078,
2785	0x84788978, 0xbfa00001,
2786	0x84788a78, 0xb8ee1e06,
2787	0x846e8a6e, 0x80786e78,
2788	0x8078ff78, 0x00000200,	2815	0x8078ff78, 0x00000200,
2789	0x8078ff78, 0x00000080,	2816	0xbefd0084, 0xbf0a6f7d,
2790	0xbef600ff, 0x01000000,	2817	0xbfa10050, 0xe0505000,
2791	0x857d9972, 0x8b7d817d,	2818	0x781d0000, 0xe0505080,
2792	0xbf06817d, 0xbefd0080,	2819	0x781d0100, 0xe0505100,
2793	0xbfa2000c, 0xe0500000,	2820	0x781d0200, 0xe0505180,
2794	0x781d0000, 0xbf8903f7,	2821	0x781d0300, 0xbf8903f7,
2795	0xdac00000, 0x00000000,	2822	0x7e008500, 0x7e028501,
2796	0x807dff7d, 0x00000080,	2823	0x7e048502, 0x7e068503,
2797	0x8078ff78, 0x00000080,	2824	0x807d847d, 0x8078ff78,
2798	0xbf0a6f7d, 0xbfa2fff5,	2825	0x00000200, 0xbf0a6f7d,
2799	0xbfa0000b, 0xe0500000,	2826	0xbfa2ffee, 0xe0505000,
2800	0x781d0000, 0xbf8903f7,	2827	0x6e1d0000, 0xe0505080,
2801	0xdac00000, 0x00000000,	2828	0x6e1d0100, 0xe0505100,
2802	0x807dff7d, 0x00000100,	2829	0x6e1d0200, 0xe0505180,
2803	0x8078ff78, 0x00000100,	2830	0x6e1d0300, 0xbf8903f7,
2804	0xbf0a6f7d, 0xbfa2fff5,	2831	0xbfa00034, 0xbef600ff,
2805	0xbef80080, 0xbefe00c1,	2832	0x01000000, 0xbeee0078,
2806	0x857d9972, 0x8b7d817d,	2833	0x8078ff78, 0x00000400,
2807	0xbf06817d, 0xbfa20002,	2834	0xbefd0084, 0xbf0a6f7d,
2808	0xbeff0080, 0xbfa00001,	2835	0xbfa10012, 0xe0505000,
2809	0xbeff00c1, 0xb8ef3b05,	2836	0x781d0000, 0xe0505100,
2810	0x806f816f, 0x846f826f,	2837	0x781d0100, 0xe0505200,
2811	0x857d9972, 0x8b7d817d,	2838	0x781d0200, 0xe0505300,
2812	0xbf06817d, 0xbfa20024,	2839	0x781d0300, 0xbf8903f7,
2813	0xbef600ff, 0x01000000,	2840	0x7e008500, 0x7e028501,
2814	0xbeee0078, 0x8078ff78,	2841	0x7e048502, 0x7e068503,
2815	0x00000200, 0xbefd0084,	2842	0x807d847d, 0x8078ff78,
2816	0xbf0a6f7d, 0xbfa10050,	2843	0x00000400, 0xbf0a6f7d,
		2844	0xbfa2ffee, 0xb8ef1e06,
		2845	0x8b6fc16f, 0xbfa1000e,
		2846	0x846f836f, 0x806f7d6f,
		2847	0xbefe00c1, 0xbeff0080,
2817	0xe0505000, 0x781d0000,	2848	0xe0505000, 0x781d0000,
2818	0xe0505080, 0x781d0100,
2819	0xe0505100, 0x781d0200,
2820	0xe0505180, 0x781d0300,
2821	0xbf8903f7, 0x7e008500,	2849	0xbf8903f7, 0x7e008500,
2822	0x7e028501, 0x7e048502,	2850	0x807d817d, 0x8078ff78,
2823	0x7e068503, 0x807d847d,	2851	0x00000080, 0xbf0a6f7d,
2824	0x8078ff78, 0x00000200,	2852	0xbfa2fff7, 0xbeff00c1,
2825	0xbf0a6f7d, 0xbfa2ffee,
2826	0xe0505000, 0x6e1d0000,	2853	0xe0505000, 0x6e1d0000,
2827	0xe0505080, 0x6e1d0100,	2854	0xe0505100, 0x6e1d0100,
2828	0xe0505100, 0x6e1d0200,	2855	0xe0505200, 0x6e1d0200,
2829	0xe0505180, 0x6e1d0300,	2856	0xe0505300, 0x6e1d0300,
2830	0xbf8903f7, 0xbfa00034,	2857	0xbf8903f7, 0xb8f83b05,
2831	0xbef600ff, 0x01000000,	2858	0x80788178, 0xbf0d9972,
2832	0xbeee0078, 0x8078ff78,	2859	0xbfa20002, 0x84788978,
2833	0x00000400, 0xbefd0084,	2860	0xbfa00001, 0x84788a78,
2834	0xbf0a6f7d, 0xbfa10012,	2861	0xb8ee1e06, 0x846e8a6e,
2835	0xe0505000, 0x781d0000,	2862	0x80786e78, 0x8078ff78,
2836	0xe0505100, 0x781d0100,	2863	0x00000200, 0x80f8ff78,
2837	0xe0505200, 0x781d0200,	2864	0x00000050, 0xbef600ff,
2838	0xe0505300, 0x781d0300,	2865	0x01000000, 0xbefd00ff,
2839	0xbf8903f7, 0x7e008500,	2866	0x0000006c, 0x80f89078,
2840	0x7e028501, 0x7e048502,	2867	0xf428403a, 0xf0000000,
2841	0x7e068503, 0x807d847d,	2868	0xbf89fc07, 0x80fd847d,
2842	0x8078ff78, 0x00000400,	2869	0xbf800000, 0xbe804300,
2843	0xbf0a6f7d, 0xbfa2ffee,	2870	0xbe824302, 0x80f8a078,
2844	0xb8ef1e06, 0x8b6fc16f,	2871	0xf42c403a, 0xf0000000,
2845	0xbfa1000e, 0x846f836f,	2872	0xbf89fc07, 0x80fd887d,
2846	0x806f7d6f, 0xbefe00c1,	2873	0xbf800000, 0xbe804300,
2847	0xbeff0080, 0xe0505000,	2874	0xbe824302, 0xbe844304,
2848	0x781d0000, 0xbf8903f7,	2875	0xbe864306, 0x80f8c078,
2849	0x7e008500, 0x807d817d,	2876	0xf430403a, 0xf0000000,
2850	0x8078ff78, 0x00000080,	2877	0xbf89fc07, 0x80fd907d,
2851	0xbf0a6f7d, 0xbfa2fff7,	2878	0xbf800000, 0xbe804300,
2852	0xbeff00c1, 0xe0505000,	2879	0xbe824302, 0xbe844304,
2853	0x6e1d0000, 0xe0505100,	2880	0xbe864306, 0xbe884308,
2854	0x6e1d0100, 0xe0505200,	2881	0xbe8a430a, 0xbe8c430c,
2855	0x6e1d0200, 0xe0505300,	2882	0xbe8e430e, 0xbf06807d,
2856	0x6e1d0300, 0xbf8903f7,	2883	0xbfa1fff0, 0xb980f801,
		2884	0x00000000, 0xbfbd0000,
2857	0xb8f83b05, 0x80788178,	2885	0xb8f83b05, 0x80788178,
2858	0xbf0d9972, 0xbfa20002,	2886	0xbf0d9972, 0xbfa20002,
2859	0x84788978, 0xbfa00001,	2887	0x84788978, 0xbfa00001,
2860	0x84788a78, 0xb8ee1e06,	2888	0x84788a78, 0xb8ee1e06,
2861	0x846e8a6e, 0x80786e78,	2889	0x846e8a6e, 0x80786e78,
2862	0x8078ff78, 0x00000200,	2890	0x8078ff78, 0x00000200,
2863	0x80f8ff78, 0x00000050,
2864	0xbef600ff, 0x01000000,	2891	0xbef600ff, 0x01000000,
2865	0xbefd00ff, 0x0000006c,	2892	0xf4205bfa, 0xf0000000,
2866	0x80f89078, 0xf428403a,	2893	0x80788478, 0xf4205b3a,
2867	0xf0000000, 0xbf89fc07,
2868	0x80fd847d, 0xbf800000,
2869	0xbe804300, 0xbe824302,
2870	0x80f8a078, 0xf42c403a,
2871	0xf0000000, 0xbf89fc07,
2872	0x80fd887d, 0xbf800000,
2873	0xbe804300, 0xbe824302,
2874	0xbe844304, 0xbe864306,
2875	0x80f8c078, 0xf430403a,
2876	0xf0000000, 0xbf89fc07,
2877	0x80fd907d, 0xbf800000,
2878	0xbe804300, 0xbe824302,
2879	0xbe844304, 0xbe864306,
2880	0xbe884308, 0xbe8a430a,
2881	0xbe8c430c, 0xbe8e430e,
2882	0xbf06807d, 0xbfa1fff0,
2883	0xb980f801, 0x00000000,
2884	0xbfbd0000, 0xb8f83b05,
2885	0x80788178, 0xbf0d9972,
2886	0xbfa20002, 0x84788978,
2887	0xbfa00001, 0x84788a78,
2888	0xb8ee1e06, 0x846e8a6e,
2889	0x80786e78, 0x8078ff78,
2890	0x00000200, 0xbef600ff,
2891	0x01000000, 0xf4205bfa,
2892	0xf0000000, 0x80788478,	2894	0xf0000000, 0x80788478,
2893	0xf4205b3a, 0xf0000000,	2895	0xf4205b7a, 0xf0000000,
2894	0x80788478, 0xf4205b7a,	2896	0x80788478, 0xf4205c3a,
2895	0xf0000000, 0x80788478,	2897	0xf0000000, 0x80788478,
2896	0xf4205c3a, 0xf0000000,	2898	0xf4205c7a, 0xf0000000,
2897	0x80788478, 0xf4205c7a,	2899	0x80788478, 0xf4205eba,
2898	0xf0000000, 0x80788478,	2900	0xf0000000, 0x80788478,
2899	0xf4205eba, 0xf0000000,	2901	0xf4205efa, 0xf0000000,
2900	0x80788478, 0xf4205efa,	2902	0x80788478, 0xf4205e7a,
2901	0xf0000000, 0x80788478,	2903	0xf0000000, 0x80788478,
2902	0xf4205e7a, 0xf0000000,	2904	0xf4205cfa, 0xf0000000,
2903	0x80788478, 0xf4205cfa,	2905	0x80788478, 0xf4205bba,
2904	0xf0000000, 0x80788478,	2906	0xf0000000, 0x80788478,
		2907	0xbf89fc07, 0xb96ef814,
2905	0xf4205bba, 0xf0000000,	2908	0xf4205bba, 0xf0000000,
2906	0x80788478, 0xbf89fc07,	2909	0x80788478, 0xbf89fc07,
2907	0xb96ef814, 0xf4205bba,	2910	0xb96ef815, 0xbefd006f,
2908	0xf0000000, 0x80788478,	2911	0xbefe0070, 0xbeff0071,
2909	0xbf89fc07, 0xb96ef815,	2912	0x8b6f7bff, 0x000003ff,
2910	0xbefd006f, 0xbefe0070,	2913	0xb96f4803, 0x8b6f7bff,
2911	0xbeff0071, 0x8b6f7bff,	2914	0xfffff800, 0x856f8b6f,
2912	0x000003ff, 0xb96f4803,	2915	0xb96fa2c3, 0xb973f801,
2913	0x8b6f7bff, 0xfffff800,	2916	0xb8ee3b05, 0x806e816e,
2914	0x856f8b6f, 0xb96fa2c3,	2917	0xbf0d9972, 0xbfa20002,
2915	0xb973f801, 0xb8ee3b05,	2918	0x846e896e, 0xbfa00001,
2916	0x806e816e, 0xbf0d9972,	2919	0x846e8a6e, 0xb8ef1e06,
2917	0xbfa20002, 0x846e896e,	2920	0x846f8a6f, 0x806e6f6e,
2918	0xbfa00001, 0x846e8a6e,	2921	0x806eff6e, 0x00000200,
2919	0xb8ef1e06, 0x846f8a6f,	2922	0x806e746e, 0x826f8075,
2920	0x806e6f6e, 0x806eff6e,	2923	0x8b6fff6f, 0x0000ffff,
2921	0x00000200, 0x806e746e,	2924	0xf4085c37, 0xf8000050,
2922	0x826f8075, 0x8b6fff6f,	2925	0xf4085d37, 0xf8000060,
2923	0x0000ffff, 0xf4085c37,	2926	0xf4005e77, 0xf8000074,
2924	0xf8000050, 0xf4085d37,	2927	0xbf89fc07, 0x8b6dff6d,
2925	0xf8000060, 0xf4005e77,	2928	0x0000ffff, 0x8bfe7e7e,
2926	0xf8000074, 0xbf89fc07,	2929	0x8bea6a6a, 0xb8eef802,
2927	0x8b6dff6d, 0x0000ffff,	2930	0xbf0d866e, 0xbfa20002,
2928	0x8bfe7e7e, 0x8bea6a6a,	2931	0xb97af802, 0xbe80486c,
2929	0xb97af802, 0xbe804a6c,	2932	0xb97af802, 0xbe804a6c,
2930	0xbfb00000, 0xbf9f0000,	2933	0xbfb00000, 0xbf9f0000,
2931	0xbf9f0000, 0xbf9f0000,	2934	0xbf9f0000, 0xbf9f0000,

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm+21−0

 #define HAVE_XNACK (ASIC_FAMILY < CHIP_SIENNA_CICHLID)
 #define HAVE_SENDMSG_RTN (ASIC_FAMILY >= CHIP_PLUM_BONITO)
 #define HAVE_BUFFER_LDS_LOAD (ASIC_FAMILY < CHIP_PLUM_BONITO)
+#define SW_SA_TRAP (ASIC_FAMILY >= CHIP_PLUM_BONITO)
 var SINGLE_STEP_MISSED_WORKAROUND		= 1	//workaround for lost MODE.DEBUG_EN exception when SAVECTX raised
 var SQ_WAVE_STATUS_SPI_PRIO_MASK		= 0x00000006
 var SQ_WAVE_STATUS_HALT_MASK			= 0x2000
 var SQ_WAVE_STATUS_ECC_ERR_MASK			= 0x20000
+var SQ_WAVE_STATUS_TRAP_EN_SHIFT		= 6
 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT		= 12
 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9
 	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+#if SW_SA_TRAP
+	// If ttmp1[31] is set then trap may occur early.
+	// Spin wait until SAVECTX exception is raised.
+	s_bitcmp1_b32	s_save_pc_hi, 31
+	s_cbranch_scc1  L_CHECK_SAVE
+#endif
 	s_and_b32       ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK
 	s_cbranch_scc0	L_NOT_HALTED
 	s_and_b32	s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff		//pc[47:32] //Do it here in order not to affect STATUS
 	s_and_b64	exec, exec, exec					// Restore STATUS.EXECZ, not writable by s_setreg_b32
 	s_and_b64	vcc, vcc, vcc						// Restore STATUS.VCCZ, not writable by s_setreg_b32
+#if SW_SA_TRAP
+	// If traps are enabled then return to the shader with PRIV=0.
+	// Otherwise retain PRIV=1 for subsequent context save requests.
+	s_getreg_b32	s_restore_tmp, hwreg(HW_REG_STATUS)
+	s_bitcmp1_b32	s_restore_tmp, SQ_WAVE_STATUS_TRAP_EN_SHIFT
+	s_cbranch_scc1	L_RETURN_WITHOUT_PRIV
 	s_setreg_b32	hwreg(HW_REG_STATUS), s_restore_status			// SCC is included, which is changed by previous salu
+	s_setpc_b64	[s_restore_pc_lo, s_restore_pc_hi]
+L_RETURN_WITHOUT_PRIV:
+#endif
+	s_setreg_b32	hwreg(HW_REG_STATUS), s_restore_status			// SCC is included, which is changed by previous salu
 	s_rfe_b64	s_restore_pc_lo						//Return to the main shader program and resume execution
 L_END_PGM:

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c+41−13

@@ -327,6 +327,12 @@ static int kfd_ioctl_create_queue(struct file filep, struct kfd_process p, · 326 unmodified lines
327	goto err_bind_process;	327	goto err_bind_process;
328	}	328	}
329		329
		330	if (!pdd->doorbell_index &&
		331	kfd_alloc_process_doorbells(dev, &pdd->doorbell_index) < 0) {
		332	err = -ENOMEM;
		333	goto err_alloc_doorbells;
		334	}
		335
330	/* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work	336	/* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
331	* on unmapped queues for usermode queue oversubscription (no aggregated doorbell)	337	* on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
332	*/	338	*/
@@ -404,6 +410,7 @@ err_create_queue: · 71 unmodified lines
404	if (wptr_bo)	410	if (wptr_bo)
405	amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo);	411	amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo);
406	err_wptr_map_gart:	412	err_wptr_map_gart:
		413	err_alloc_doorbells:
407	err_bind_process:	414	err_bind_process:
408	err_pdd:	415	err_pdd:
409	mutex_unlock(&p->mutex);	416	mutex_unlock(&p->mutex);
@@ -869,14 +876,11 @@ static int kfd_ioctl_wait_events(struct file filp, struct kfd_process p, · 459 unmodified lines
869	void *data)	876	void *data)
870	{	877	{
871	struct kfd_ioctl_wait_events_args *args = data;	878	struct kfd_ioctl_wait_events_args *args = data;
872	int err;
873		879
874	err = kfd_wait_on_events(p, args->num_events,	880	return kfd_wait_on_events(p, args->num_events,
875	(void __user *)args->events_ptr,	881	(void __user *)args->events_ptr,
876	(args->wait_for_all != 0),	882	(args->wait_for_all != 0),
877	&args->timeout, &args->wait_result);	883	&args->timeout, &args->wait_result);
878
879	return err;
880	}	884	}
881	static int kfd_ioctl_set_scratch_backing_va(struct file *filep,	885	static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
882	struct kfd_process p, void data)	886	struct kfd_process p, void data)
@@ -1092,6 +1096,10 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, · 209 unmodified lines
1092	goto err_unlock;	1096	goto err_unlock;
1093	}	1097	}
1094	offset = kfd_get_process_doorbells(pdd);	1098	offset = kfd_get_process_doorbells(pdd);
		1099	if (!offset) {
		1100	err = -ENOMEM;
		1101	goto err_unlock;
		1102	}
1095	} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {	1103	} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1096	if (args->size != PAGE_SIZE) {	1104	if (args->size != PAGE_SIZE) {
1097	err = -EINVAL;	1105	err = -EINVAL;
@@ -1576,6 +1584,8 @@ static int kfd_ioctl_smi_events(struct file *filep, · 478 unmodified lines
1576	return kfd_smi_event_open(pdd->dev, &args->anon_fd);	1584	return kfd_smi_event_open(pdd->dev, &args->anon_fd);
1577	}	1585	}
1578		1586
		1587	#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
		1588
1579	static int kfd_ioctl_set_xnack_mode(struct file *filep,	1589	static int kfd_ioctl_set_xnack_mode(struct file *filep,
1580	struct kfd_process p, void data)	1590	struct kfd_process p, void data)
1581	{	1591	{
@@ -1586,22 +1596,29 @@ static int kfd_ioctl_set_xnack_mode(struct file *filep, · 4 unmodified lines
1586	if (args->xnack_enabled >= 0) {	1596	if (args->xnack_enabled >= 0) {
1587	if (!list_empty(&p->pqm.queues)) {	1597	if (!list_empty(&p->pqm.queues)) {
1588	pr_debug("Process has user queues running\n");	1598	pr_debug("Process has user queues running\n");
1589	mutex_unlock(&p->mutex);	1599	r = -EBUSY;
1590	return -EBUSY;	1600	goto out_unlock;
1591	}	1601	}
1592	if (args->xnack_enabled && !kfd_process_xnack_mode(p, true))	1602
		1603	if (p->xnack_enabled == args->xnack_enabled)
		1604	goto out_unlock;
		1605
		1606	if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) {
1593	r = -EPERM;	1607	r = -EPERM;
1594	else	1608	goto out_unlock;
1595	p->xnack_enabled = args->xnack_enabled;	1609	}
		1610
		1611	r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled);
1596	} else {	1612	} else {
1597	args->xnack_enabled = p->xnack_enabled;	1613	args->xnack_enabled = p->xnack_enabled;
1598	}	1614	}
		1615
		1616	out_unlock:
1599	mutex_unlock(&p->mutex);	1617	mutex_unlock(&p->mutex);
1600		1618
1601	return r;	1619	return r;
1602	}	1620	}
1603		1621
1604	#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1605	static int kfd_ioctl_svm(struct file filep, struct kfd_process p, void *data)	1622	static int kfd_ioctl_svm(struct file filep, struct kfd_process p, void *data)
1606	{	1623	{
1607	struct kfd_ioctl_svm_args *args = data;	1624	struct kfd_ioctl_svm_args *args = data;
@@ -1621,6 +1638,11 @@ static int kfd_ioctl_svm(struct file filep, struct kfd_process p, void *data) · 13 unmodified lines
1621	return r;	1638	return r;
1622	}	1639	}
1623	#else	1640	#else
		1641	static int kfd_ioctl_set_xnack_mode(struct file *filep,
		1642	struct kfd_process p, void data)
		1643	{
		1644	return -EPERM;
		1645	}
1624	static int kfd_ioctl_svm(struct file filep, struct kfd_process p, void *data)	1646	static int kfd_ioctl_svm(struct file filep, struct kfd_process p, void *data)
1625	{	1647	{
1626	return -EPERM;	1648	return -EPERM;
@@ -2145,6 +2167,12 @@ static int criu_restore_devices(struct kfd_process *p, · 518 unmodified lines
2145	ret = PTR_ERR(pdd);	2167	ret = PTR_ERR(pdd);
2146	goto exit;	2168	goto exit;
2147	}	2169	}
		2170
		2171	if (!pdd->doorbell_index &&
		2172	kfd_alloc_process_doorbells(pdd->dev, &pdd->doorbell_index) < 0) {
		2173	ret = -ENOMEM;
		2174	goto exit;
		2175	}
2148	}	2176	}
2149		2177
2150	/*	2178	/*
@@ -2173,6 +2201,8 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, · 22 unmodified lines
2173	return -EINVAL;	2201	return -EINVAL;
2174		2202
2175	offset = kfd_get_process_doorbells(pdd);	2203	offset = kfd_get_process_doorbells(pdd);
		2204	if (!offset)
		2205	return -ENOMEM;
2176	} else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {	2206	} else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2177	/* MMIO BOs need remapped bus address */	2207	/* MMIO BOs need remapped bus address */
2178	if (bo_bucket->size != PAGE_SIZE) {	2208	if (bo_bucket->size != PAGE_SIZE) {
@@ -2847,7 +2877,6 @@ static int kfd_mmio_mmap(struct kfd_dev dev, struct kfd_process process, · 668 unmodified lines
2847	struct vm_area_struct *vma)	2877	struct vm_area_struct *vma)
2848	{	2878	{
2849	phys_addr_t address;	2879	phys_addr_t address;
2850	int ret;
2851		2880
2852	if (vma->vm_end - vma->vm_start != PAGE_SIZE)	2881	if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2853	return -EINVAL;	2882	return -EINVAL;
@@ -2867,12 +2896,11 @@ static int kfd_mmio_mmap(struct kfd_dev dev, struct kfd_process process, · 13 unmodified lines
2867	process->pasid, (unsigned long long) vma->vm_start,	2896	process->pasid, (unsigned long long) vma->vm_start,
2868	address, vma->vm_flags, PAGE_SIZE);	2897	address, vma->vm_flags, PAGE_SIZE);
2869		2898
2870	ret = io_remap_pfn_range(vma,	2899	return io_remap_pfn_range(vma,
2871	vma->vm_start,	2900	vma->vm_start,
2872	address >> PAGE_SHIFT,	2901	address >> PAGE_SHIFT,
2873	PAGE_SIZE,	2902	PAGE_SIZE,
2874	vma->vm_page_prot);	2903	vma->vm_page_prot);
2875	return ret;
2876	}	2904	}
2877		2905
2878		2906

drivers/gpu/drm/amd/amdkfd/kfd_crat.c+2−1

 		case IP_VERSION(11, 0, 0):
 		case IP_VERSION(11, 0, 1):
 		case IP_VERSION(11, 0, 2):
+		case IP_VERSION(11, 0, 3):
 			pcache_info = cache_info;
 			num_of_cache_types =
 				kfd_fill_gpu_cache_info_from_gfx_config(kdev, pcache_info);
 	/* Fill in Subtype: IO_LINKS
 	 *  Only direct links are added here which is Link from GPU to
-	 *  to its NUMA node. Indirect links are added by userspace.
+	 *  its NUMA node. Indirect links are added by userspace.
 	 */
 	sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
 		cache_mem_filled);

drivers/gpu/drm/amd/amdkfd/kfd_device.c+8−0

 	case IP_VERSION(6, 0, 0):
 	case IP_VERSION(6, 0, 1):
 	case IP_VERSION(6, 0, 2):
+	case IP_VERSION(6, 0, 3):
 		kfd->device_info.num_sdma_queues_per_engine = 8;
 		break;
 	default:
 	switch (sdma_version) {
 	case IP_VERSION(6, 0, 0):
 	case IP_VERSION(6, 0, 2):
+	case IP_VERSION(6, 0, 3):
 		/* Reserve 1 for paging and 1 for gfx */
 		kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
 		/* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */
 	case IP_VERSION(11, 0, 0):
 	case IP_VERSION(11, 0, 1):
 	case IP_VERSION(11, 0, 2):
+	case IP_VERSION(11, 0, 3):
 		kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
 		break;
 	default:
 			gfx_target_version = 110002;
 			f2g = &gfx_v11_kfd2kgd;
 			break;
+		case IP_VERSION(11, 0, 3):
+			/* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */
+			gfx_target_version = 110001;
+			f2g = &gfx_v11_kfd2kgd;
+			break;
 		default:
 			break;
 		}

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+21−24

 			dqm->dev->kfd2kgd->init_interrupts(dqm->dev->adev, i);
 }
+static void init_sdma_bitmaps(struct device_queue_manager *dqm)
+{
+	unsigned int num_sdma_queues =
+		min_t(unsigned int, sizeof(dqm->sdma_bitmap)*8,
+		      get_num_sdma_queues(dqm));
+	unsigned int num_xgmi_sdma_queues =
+		min_t(unsigned int, sizeof(dqm->xgmi_sdma_bitmap)*8,
+		      get_num_xgmi_sdma_queues(dqm));
+	if (num_sdma_queues)
+		dqm->sdma_bitmap = GENMASK_ULL(num_sdma_queues-1, 0);
+	if (num_xgmi_sdma_queues)
+		dqm->xgmi_sdma_bitmap = GENMASK_ULL(num_xgmi_sdma_queues-1, 0);
+	dqm->sdma_bitmap &= ~get_reserved_sdma_queues_bitmap(dqm);
+	pr_info("sdma_bitmap: %llx\n", dqm->sdma_bitmap);
+}
 static int initialize_nocpsch(struct device_queue_manager *dqm)
 {
 	int pipe, queue;
 	memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
-	dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
+	init_sdma_bitmaps(dqm);
-	dqm->sdma_bitmap &= ~(get_reserved_sdma_queues_bitmap(dqm));
-	pr_info("sdma_bitmap: %llx\n", dqm->sdma_bitmap);
-	dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
 	return 0;
 }
 static int initialize_cpsch(struct device_queue_manager *dqm)
 {
-	uint64_t num_sdma_queues;
-	uint64_t num_xgmi_sdma_queues;
 	pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
 	mutex_init(&dqm->lock_hidden);
 	dqm->active_cp_queue_count = 0;
 	dqm->gws_queue_count = 0;
 	dqm->active_runlist = false;
-	num_sdma_queues = get_num_sdma_queues(dqm);
-	if (num_sdma_queues >= BITS_PER_TYPE(dqm->sdma_bitmap))
-		dqm->sdma_bitmap = ULLONG_MAX;
-	else
-		dqm->sdma_bitmap = (BIT_ULL(num_sdma_queues) - 1);
-	dqm->sdma_bitmap &= ~(get_reserved_sdma_queues_bitmap(dqm));
-	pr_info("sdma_bitmap: %llx\n", dqm->sdma_bitmap);
-	num_xgmi_sdma_queues = get_num_xgmi_sdma_queues(dqm);
-	if (num_xgmi_sdma_queues >= BITS_PER_TYPE(dqm->xgmi_sdma_bitmap))
-		dqm->xgmi_sdma_bitmap = ULLONG_MAX;
-	else
-		dqm->xgmi_sdma_bitmap = (BIT_ULL(num_xgmi_sdma_queues) - 1);
 	INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
+	init_sdma_bitmaps(dqm);
 	return 0;
 }

drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c+12−0

 	/* Calculate physical address of doorbell */
 	address = kfd_get_process_doorbells(pdd);
+	if (!address)
+		return -ENOMEM;
 	vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
 				VM_DONTDUMP | VM_PFNMAP;
 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd)
 {
+	if (!pdd->doorbell_index) {
+		int r = kfd_alloc_process_doorbells(pdd->dev,
+						    &pdd->doorbell_index);
+		if (r)
+			return 0;
+	}
 	return pdd->dev->doorbell_base +
 		pdd->doorbell_index * kfd_doorbell_process_slice(pdd->dev);
 }
 	if (r > 0)
 		*doorbell_index = r;
+	if (r < 0)
+		pr_err("Failed to allocate process doorbells\n");
 	return r;
 }

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c+36−21

@@ -322,12 +322,13 @@ svm_migrate_copy_to_vram(struct amdgpu_device adev, struct svm_range prange, · 321 unmodified lines
322	for (i = j = 0; i < npages; i++) {	322	for (i = j = 0; i < npages; i++) {
323	struct page *spage;	323	struct page *spage;
324		324
		325	dst[i] = cursor.start + (j << PAGE_SHIFT);
		326	migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]);
		327	svm_migrate_get_vram_page(prange, migrate->dst[i]);
		328	migrate->dst[i] = migrate_pfn(migrate->dst[i]);
		329
325	spage = migrate_pfn_to_page(migrate->src[i]);	330	spage = migrate_pfn_to_page(migrate->src[i]);
326	if (spage && !is_zone_device_page(spage)) {	331	if (spage && !is_zone_device_page(spage)) {
327	dst[i] = cursor.start + (j << PAGE_SHIFT);
328	migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]);
329	svm_migrate_get_vram_page(prange, migrate->dst[i]);
330	migrate->dst[i] = migrate_pfn(migrate->dst[i]);
331	src[i] = dma_map_page(dev, spage, 0, PAGE_SIZE,	332	src[i] = dma_map_page(dev, spage, 0, PAGE_SIZE,
332	DMA_TO_DEVICE);	333	DMA_TO_DEVICE);
333	r = dma_mapping_error(dev, src[i]);	334	r = dma_mapping_error(dev, src[i]);
@@ -522,9 +523,6 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc, · 188 unmodified lines
522	pr_debug("svms 0x%p [0x%lx 0x%lx] to gpu 0x%x\n", prange->svms,	523	pr_debug("svms 0x%p [0x%lx 0x%lx] to gpu 0x%x\n", prange->svms,
523	prange->start, prange->last, best_loc);	524	prange->start, prange->last, best_loc);
524		525
525	/* FIXME: workaround for page locking bug with invalid pages */
526	svm_range_prefault(prange, mm, SVM_ADEV_PGMAP_OWNER(adev));
527
528	start = prange->start << PAGE_SHIFT;	526	start = prange->start << PAGE_SHIFT;
529	end = (prange->last + 1) << PAGE_SHIFT;	527	end = (prange->last + 1) << PAGE_SHIFT;
530		528
@@ -886,7 +884,7 @@ svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc, · 355 unmodified lines
886	static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)	884	static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)
887	{	885	{
888	unsigned long addr = vmf->address;	886	unsigned long addr = vmf->address;
889	struct vm_area_struct *vma;	887	struct svm_range_bo *svm_bo;
890	enum svm_work_list_ops op;	888	enum svm_work_list_ops op;
891	struct svm_range *parent;	889	struct svm_range *parent;
892	struct svm_range *prange;	890	struct svm_range *prange;
@@ -894,29 +892,42 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf) · 1 unmodified line
894	struct mm_struct *mm;	892	struct mm_struct *mm;
895	int r = 0;	893	int r = 0;
896		894
897	vma = vmf->vma;	895	svm_bo = vmf->page->zone_device_data;
898	mm = vma->vm_mm;	896	if (!svm_bo) {
		897	pr_debug("failed get device page at addr 0x%lx\n", addr);
		898	return VM_FAULT_SIGBUS;
		899	}
		900	if (!mmget_not_zero(svm_bo->eviction_fence->mm)) {
		901	pr_debug("addr 0x%lx of process mm is destroyed\n", addr);
		902	return VM_FAULT_SIGBUS;
		903	}
		904
		905	mm = svm_bo->eviction_fence->mm;
		906	if (mm != vmf->vma->vm_mm)
		907	pr_debug("addr 0x%lx is COW mapping in child process\n", addr);
899		908
900	p = kfd_lookup_process_by_mm(vma->vm_mm);	909	p = kfd_lookup_process_by_mm(mm);
901	if (!p) {	910	if (!p) {
902	pr_debug("failed find process at fault address 0x%lx\n", addr);	911	pr_debug("failed find process at fault address 0x%lx\n", addr);
903	return VM_FAULT_SIGBUS;	912	r = VM_FAULT_SIGBUS;
		913	goto out_mmput;
904	}	914	}
905	if (READ_ONCE(p->svms.faulting_task) == current) {	915	if (READ_ONCE(p->svms.faulting_task) == current) {
906	pr_debug("skipping ram migration\n");	916	pr_debug("skipping ram migration\n");
907	kfd_unref_process(p);	917	r = 0;
908	return 0;	918	goto out_unref_process;
909	}	919	}
910	addr >>= PAGE_SHIFT;	920
911	pr_debug("CPU page fault svms 0x%p address 0x%lx\n", &p->svms, addr);	921	pr_debug("CPU page fault svms 0x%p address 0x%lx\n", &p->svms, addr);
		922	addr >>= PAGE_SHIFT;
912		923
913	mutex_lock(&p->svms.lock);	924	mutex_lock(&p->svms.lock);
914		925
915	prange = svm_range_from_addr(&p->svms, addr, &parent);	926	prange = svm_range_from_addr(&p->svms, addr, &parent);
916	if (!prange) {	927	if (!prange) {
917	pr_debug("cannot find svm range at 0x%lx\n", addr);	928	pr_debug("failed get range svms 0x%p addr 0x%lx\n", &p->svms, addr);
918	r = -EFAULT;	929	r = -EFAULT;
919	goto out;	930	goto out_unlock_svms;
920	}	931	}
921		932
922	mutex_lock(&parent->migrate_mutex);	933	mutex_lock(&parent->migrate_mutex);
@@ -938,10 +949,11 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf) · 15 unmodified lines
938	goto out_unlock_prange;	949	goto out_unlock_prange;
939	}	950	}
940		951
941	r = svm_migrate_vram_to_ram(prange, mm, KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU);	952	r = svm_migrate_vram_to_ram(prange, vmf->vma->vm_mm,
		953	KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU);
942	if (r)	954	if (r)
943	pr_debug("failed %d migrate 0x%p [0x%lx 0x%lx] to ram\n", r,	955	pr_debug("failed %d migrate svms 0x%p range 0x%p [0x%lx 0x%lx]\n",
944	prange, prange->start, prange->last);	956	r, prange->svms, prange, prange->start, prange->last);
945		957
946	/* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */	958	/* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */
947	if (p->xnack_enabled && parent == prange)	959	if (p->xnack_enabled && parent == prange)
@@ -955,9 +967,12 @@ out_unlock_prange: · 7 unmodified lines
955	if (prange != parent)	967	if (prange != parent)
956	mutex_unlock(&prange->migrate_mutex);	968	mutex_unlock(&prange->migrate_mutex);
957	mutex_unlock(&parent->migrate_mutex);	969	mutex_unlock(&parent->migrate_mutex);
958	out:	970	out_unlock_svms:
959	mutex_unlock(&p->svms.lock);	971	mutex_unlock(&p->svms.lock);
		972	out_unref_process:
960	kfd_unref_process(p);	973	kfd_unref_process(p);
		974	out_mmput:
		975	mmput(mm);
961		976
962	pr_debug("CPU fault svms 0x%p address 0x%lx done\n", &p->svms, addr);	977	pr_debug("CPU fault svms 0x%p address 0x%lx done\n", &p->svms, addr);
963		978

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c+12−73

 	return r;
 }
-static int hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd,
-			    uint32_t pipe_id, uint32_t queue_id,
-			    struct queue_properties *p, struct mm_struct *mms)
-{
-	return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, mqd, pipe_id,
-					      queue_id, p->doorbell_off);
-}
 static void update_mqd(struct mqd_manager *mm, void *mqd,
 		       struct queue_properties *q,
 		       struct mqd_update_info *minfo)
 	return m->queue_doorbell_id0;
 }
-static int destroy_mqd(struct mqd_manager *mm, void *mqd,
-		       enum kfd_preempt_type type,
-		       unsigned int timeout, uint32_t pipe_id,
-		       uint32_t queue_id)
-{
-	return mm->dev->kfd2kgd->hqd_destroy
-		(mm->dev->adev, mqd, type, timeout,
-		 pipe_id, queue_id);
-}
-static void free_mqd(struct mqd_manager *mm, void *mqd,
-			struct kfd_mem_obj *mqd_mem_obj)
-{
-	kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
-}
-static bool is_occupied(struct mqd_manager *mm, void *mqd,
-			uint64_t queue_address,	uint32_t pipe_id,
-			uint32_t queue_id)
-{
-	return mm->dev->kfd2kgd->hqd_is_occupied(
-		mm->dev->adev, queue_address,
-		pipe_id, queue_id);
-}
 static int get_wave_state(struct mqd_manager *mm, void *mqd,
 			  void __user *ctl_stack,
 			  u32 *ctl_stack_used_size,
 	mm->update_mqd(mm, m, q, NULL);
 }
-static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
-		uint32_t pipe_id, uint32_t queue_id,
-		struct queue_properties *p, struct mm_struct *mms)
-{
-	return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->adev, mqd,
-					       (uint32_t __user *)p->write_ptr,
-					       mms);
-}
 #define SDMA_RLC_DUMMY_DEFAULT 0xf
 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
 	q->is_active = QUEUE_IS_ACTIVE(*q);
 }
-/*
- *  * preempt type here is ignored because there is only one way
- *  * to preempt sdma queue
- */
-static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
-		enum kfd_preempt_type type,
-		unsigned int timeout, uint32_t pipe_id,
-		uint32_t queue_id)
-{
-	return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->adev, mqd, timeout);
-}
-static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
-		uint64_t queue_address, uint32_t pipe_id,
-		uint32_t queue_id)
-{
-	return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->adev, mqd);
-}
 #if defined(CONFIG_DEBUG_FS)
 static int debugfs_show_mqd(struct seq_file *m, void *data)
 		pr_debug("%s@%i\n", __func__, __LINE__);
 		mqd->allocate_mqd = allocate_mqd;
 		mqd->init_mqd = init_mqd;
-		mqd->free_mqd = free_mqd;
+		mqd->free_mqd = kfd_free_mqd_cp;
 		mqd->load_mqd = load_mqd;
 		mqd->update_mqd = update_mqd;
-		mqd->destroy_mqd = destroy_mqd;
+		mqd->destroy_mqd = kfd_destroy_mqd_cp;
-		mqd->is_occupied = is_occupied;
+		mqd->is_occupied = kfd_is_occupied_cp;
 		mqd->mqd_size = sizeof(struct v11_compute_mqd);
 		mqd->get_wave_state = get_wave_state;
 #if defined(CONFIG_DEBUG_FS)
 		mqd->allocate_mqd = allocate_hiq_mqd;
 		mqd->init_mqd = init_mqd_hiq;
 		mqd->free_mqd = free_mqd_hiq_sdma;
-		mqd->load_mqd = hiq_load_mqd_kiq;
+		mqd->load_mqd = kfd_hiq_load_mqd_kiq;
 		mqd->update_mqd = update_mqd;
-		mqd->destroy_mqd = destroy_mqd;
+		mqd->destroy_mqd = kfd_destroy_mqd_cp;
-		mqd->is_occupied = is_occupied;
+		mqd->is_occupied = kfd_is_occupied_cp;
 		mqd->mqd_size = sizeof(struct v11_compute_mqd);
 #if defined(CONFIG_DEBUG_FS)
 		mqd->debugfs_show_mqd = debugfs_show_mqd;
 	case KFD_MQD_TYPE_DIQ:
 		mqd->allocate_mqd = allocate_mqd;
 		mqd->init_mqd = init_mqd_hiq;
-		mqd->free_mqd = free_mqd;
+		mqd->free_mqd = kfd_free_mqd_cp;
 		mqd->load_mqd = load_mqd;
 		mqd->update_mqd = update_mqd;
-		mqd->destroy_mqd = destroy_mqd;
+		mqd->destroy_mqd = kfd_destroy_mqd_cp;
-		mqd->is_occupied = is_occupied;
+		mqd->is_occupied = kfd_is_occupied_cp;
 		mqd->mqd_size = sizeof(struct v11_compute_mqd);
 #if defined(CONFIG_DEBUG_FS)
 		mqd->debugfs_show_mqd = debugfs_show_mqd;
 		mqd->allocate_mqd = allocate_sdma_mqd;
 		mqd->init_mqd = init_mqd_sdma;
 		mqd->free_mqd = free_mqd_hiq_sdma;
-		mqd->load_mqd = load_mqd_sdma;
+		mqd->load_mqd = kfd_load_mqd_sdma;
 		mqd->update_mqd = update_mqd_sdma;
-		mqd->destroy_mqd = destroy_mqd_sdma;
+		mqd->destroy_mqd = kfd_destroy_mqd_sdma;
-		mqd->is_occupied = is_occupied_sdma;
+		mqd->is_occupied = kfd_is_occupied_sdma;
 		mqd->mqd_size = sizeof(struct v11_sdma_mqd);
 #if defined(CONFIG_DEBUG_FS)
 		mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;

drivers/gpu/drm/amd/amdkfd/kfd_process.c+0−5

 	if (!pdd)
 		return NULL;
-	if (kfd_alloc_process_doorbells(dev, &pdd->doorbell_index) < 0) {
-		pr_err("Failed to alloc doorbell for pdd\n");
-		goto err_free_pdd;
-	}
 	if (init_doorbell_bitmap(&pdd->qpd, dev)) {
 		pr_err("Failed to init doorbell for process\n");
 		goto err_free_pdd;

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c+7−0

@@ -857,6 +857,13 @@ int kfd_criu_restore_queue(struct kfd_process *p, · 856 unmodified lines
857	ret = -EINVAL;	857	ret = -EINVAL;
858	goto exit;	858	goto exit;
859	}	859	}
		860
		861	if (!pdd->doorbell_index &&
		862	kfd_alloc_process_doorbells(pdd->dev, &pdd->doorbell_index) < 0) {
		863	ret = -ENOMEM;
		864	goto exit;
		865	}
		866
860	/* data stored in this order: mqd, ctl_stack */	867	/* data stored in this order: mqd, ctl_stack */
861	mqd = q_extra_data;	868	mqd = q_extra_data;
862	ctl_stack = mqd + q_data->mqd_size;	869	ctl_stack = mqd + q_data->mqd_size;

drivers/gpu/drm/amd/amdkfd/kfd_svm.c+59−23

@@ -278,7 +278,7 @@ static void svm_range_free(struct svm_range *prange, bool update_mem_usage) · 277 unmodified lines
278	svm_range_free_dma_mappings(prange);	278	svm_range_free_dma_mappings(prange);
279		279
280	if (update_mem_usage && !p->xnack_enabled) {	280	if (update_mem_usage && !p->xnack_enabled) {
281	pr_debug("unreserve mem limit: %lld\n", size);	281	pr_debug("unreserve prange 0x%p size: 0x%llx\n", prange, size);
282	amdgpu_amdkfd_unreserve_mem_limit(NULL, size,	282	amdgpu_amdkfd_unreserve_mem_limit(NULL, size,
283	KFD_IOC_ALLOC_MEM_FLAGS_USERPTR);	283	KFD_IOC_ALLOC_MEM_FLAGS_USERPTR);
284	}	284	}
@@ -2956,6 +2956,64 @@ out: · 2671 unmodified lines
2956	return r;	2956	return r;
2957	}	2957	}
2958		2958
		2959	int
		2960	svm_range_switch_xnack_reserve_mem(struct kfd_process *p, bool xnack_enabled)
		2961	{
		2962	struct svm_range prange, pchild;
		2963	uint64_t reserved_size = 0;
		2964	uint64_t size;
		2965	int r = 0;
		2966
		2967	pr_debug("switching xnack from %d to %d\n", p->xnack_enabled, xnack_enabled);
		2968
		2969	mutex_lock(&p->svms.lock);
		2970
		2971	list_for_each_entry(prange, &p->svms.list, list) {
		2972	svm_range_lock(prange);
		2973	list_for_each_entry(pchild, &prange->child_list, child_list) {
		2974	size = (pchild->last - pchild->start + 1) << PAGE_SHIFT;
		2975	if (xnack_enabled) {
		2976	amdgpu_amdkfd_unreserve_mem_limit(NULL, size,
		2977	KFD_IOC_ALLOC_MEM_FLAGS_USERPTR);
		2978	} else {
		2979	r = amdgpu_amdkfd_reserve_mem_limit(NULL, size,
		2980	KFD_IOC_ALLOC_MEM_FLAGS_USERPTR);
		2981	if (r)
		2982	goto out_unlock;
		2983	reserved_size += size;
		2984	}
		2985	}
		2986
		2987	size = (prange->last - prange->start + 1) << PAGE_SHIFT;
		2988	if (xnack_enabled) {
		2989	amdgpu_amdkfd_unreserve_mem_limit(NULL, size,
		2990	KFD_IOC_ALLOC_MEM_FLAGS_USERPTR);
		2991	} else {
		2992	r = amdgpu_amdkfd_reserve_mem_limit(NULL, size,
		2993	KFD_IOC_ALLOC_MEM_FLAGS_USERPTR);
		2994	if (r)
		2995	goto out_unlock;
		2996	reserved_size += size;
		2997	}
		2998	out_unlock:
		2999	svm_range_unlock(prange);
		3000	if (r)
		3001	break;
		3002	}
		3003
		3004	if (r)
		3005	amdgpu_amdkfd_unreserve_mem_limit(NULL, reserved_size,
		3006	KFD_IOC_ALLOC_MEM_FLAGS_USERPTR);
		3007	else
		3008	/* Change xnack mode must be inside svms lock, to avoid race with
		3009	* svm_range_deferred_list_work unreserve memory in parallel.
		3010	*/
		3011	p->xnack_enabled = xnack_enabled;
		3012
		3013	mutex_unlock(&p->svms.lock);
		3014	return r;
		3015	}
		3016
2959	void svm_range_list_fini(struct kfd_process *p)	3017	void svm_range_list_fini(struct kfd_process *p)
2960	{	3018	{
2961	struct svm_range *prange;	3019	struct svm_range *prange;
@@ -3181,28 +3239,6 @@ out: · 219 unmodified lines
3181	return best_loc;	3239	return best_loc;
3182	}	3240	}
3183		3241
3184	/* FIXME: This is a workaround for page locking bug when some pages are
3185	* invalid during migration to VRAM
3186	*/
3187	void svm_range_prefault(struct svm_range prange, struct mm_struct mm,
3188	void *owner)
3189	{
3190	struct hmm_range *hmm_range;
3191	int r;
3192
3193	if (prange->validated_once)
3194	return;
3195
3196	r = amdgpu_hmm_range_get_pages(&prange->notifier, mm, NULL,
3197	prange->start << PAGE_SHIFT,
3198	prange->npages, &hmm_range,
3199	false, true, owner);
3200	if (!r) {
3201	amdgpu_hmm_range_get_pages_done(hmm_range);
3202	prange->validated_once = true;
3203	}
3204	}
3205
3206	/* svm_range_trigger_migration - start page migration if prefetch loc changed	3242	/* svm_range_trigger_migration - start page migration if prefetch loc changed
3207	* @mm: current process mm_struct	3243	* @mm: current process mm_struct
3208	* @prange: svm range structure	3244	* @prange: svm range structure

drivers/gpu/drm/amd/amdkfd/kfd_svm.h+1−2

 void svm_range_dma_unmap(struct device *dev, dma_addr_t *dma_addr,
 			 unsigned long offset, unsigned long npages);
 void svm_range_free_dma_mappings(struct svm_range *prange);
-void svm_range_prefault(struct svm_range *prange, struct mm_struct *mm,
-			void *owner);
 int svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges,
 		       uint64_t *svm_priv_data_size);
 int kfd_criu_checkpoint_svm(struct kfd_process *p,
 void svm_range_bo_unref_async(struct svm_range_bo *svm_bo);
 void svm_range_set_max_pages(struct amdgpu_device *adev);
+int svm_range_switch_xnack_reserve_mem(struct kfd_process *p, bool xnack_enabled);
 #else

drivers/gpu/drm/amd/display/Kconfig+0−2

 	bool "AMD DC support for Southern Islands ASICs"
 	depends on DRM_AMDGPU_SI
 	depends on DRM_AMD_DC
-	default n
 	help
 	  Choose this option to enable new AMD DC support for SI asics
 	  by default. This includes Tahiti, Pitcairn, Cape Verde, Oland.
 config DRM_AMD_SECURE_DISPLAY
         bool "Enable secure display support"
-        default n
         depends on DEBUG_FS
         depends on DRM_AMD_DC_DCN
         help

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+54−96

@@ -88,6 +88,7 @@ · 87 unmodified lines
88	#include <drm/drm_vblank.h>	88	#include <drm/drm_vblank.h>
89	#include <drm/drm_audio_component.h>	89	#include <drm/drm_audio_component.h>
90	#include <drm/drm_gem_atomic_helper.h>	90	#include <drm/drm_gem_atomic_helper.h>
		91	#include <drm/drm_plane_helper.h>
91		92
92	#include <acpi/video.h>	93	#include <acpi/video.h>
93		94
@@ -99,8 +100,6 @@ · 5 unmodified lines
99	#include "soc15_common.h"	100	#include "soc15_common.h"
100	#include "vega10_ip_offset.h"	101	#include "vega10_ip_offset.h"
101		102
102	#include "soc15_common.h"
103
104	#include "gc/gc_11_0_0_offset.h"	103	#include "gc/gc_11_0_0_offset.h"
105	#include "gc/gc_11_0_0_sh_mask.h"	104	#include "gc/gc_11_0_0_sh_mask.h"
106		105
@@ -1297,13 +1296,21 @@ static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct · 1190 unmodified lines
1297		1296
1298	if (hpd_rx_offload_wq[i].wq == NULL) {	1297	if (hpd_rx_offload_wq[i].wq == NULL) {
1299	DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");	1298	DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1300	return NULL;	1299	goto out_err;
1301	}	1300	}
1302		1301
1303	spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);	1302	spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1304	}	1303	}
1305		1304
1306	return hpd_rx_offload_wq;	1305	return hpd_rx_offload_wq;
		1306
		1307	out_err:
		1308	for (i = 0; i < max_caps; i++) {
		1309	if (hpd_rx_offload_wq[i].wq)
		1310	destroy_workqueue(hpd_rx_offload_wq[i].wq);
		1311	}
		1312	kfree(hpd_rx_offload_wq);
		1313	return NULL;
1307	}	1314	}
1308		1315
1309	struct amdgpu_stutter_quirk {	1316	struct amdgpu_stutter_quirk {
@@ -1531,7 +1538,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) · 221 unmodified lines
1531		1538
1532	if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {	1539	if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1533	adev->dm.dc->debug.disable_dsc = true;	1540	adev->dm.dc->debug.disable_dsc = true;
1534	adev->dm.dc->debug.disable_dsc_edp = true;
1535	}	1541	}
1536		1542
1537	if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)	1543	if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
@@ -2809,20 +2815,18 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { · 1271 unmodified lines
2809	};	2815	};
2810		2816
2811	static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {	2817	static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2812	.atomic_commit_tail = amdgpu_dm_atomic_commit_tail	2818	.atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
		2819	.atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2813	};	2820	};
2814		2821
2815	static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)	2822	static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2816	{	2823	{
2817	u32 max_avg, min_cll, max, min, q, r;
2818	struct amdgpu_dm_backlight_caps *caps;	2824	struct amdgpu_dm_backlight_caps *caps;
2819	struct amdgpu_display_manager *dm;	2825	struct amdgpu_display_manager *dm;
2820	struct drm_connector *conn_base;	2826	struct drm_connector *conn_base;
2821	struct amdgpu_device *adev;	2827	struct amdgpu_device *adev;
2822	struct dc_link *link = NULL;	2828	struct dc_link *link = NULL;
2823	static const u8 pre_computed_values[] = {	2829	struct drm_luminance_range_info *luminance_range;
2824	50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
2825	71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};
2826	int i;	2830	int i;
2827		2831
2828	if (!aconnector \|\| !aconnector->dc_link)	2832	if (!aconnector \|\| !aconnector->dc_link)
@@ -2844,8 +2848,6 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) · 15 unmodified lines
2844	caps = &dm->backlight_caps[i];	2848	caps = &dm->backlight_caps[i];
2845	caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;	2849	caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2846	caps->aux_support = false;	2850	caps->aux_support = false;
2847	max_avg = conn_base->hdr_sink_metadata.hdmi_type1.max_fall;
2848	min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
2849		2851
2850	if (caps->ext_caps->bits.oled == 1 /*\|\|	2852	if (caps->ext_caps->bits.oled == 1 /*\|\|
2851	caps->ext_caps->bits.sdr_aux_backlight_control == 1 \|\|	2853	caps->ext_caps->bits.sdr_aux_backlight_control == 1 \|\|
@@ -2857,31 +2859,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) · 5 unmodified lines
2857	else if (amdgpu_backlight == 1)	2859	else if (amdgpu_backlight == 1)
2858	caps->aux_support = true;	2860	caps->aux_support = true;
2859		2861
2860	/* From the specification (CTA-861-G), for calculating the maximum	2862	luminance_range = &conn_base->display_info.luminance_range;
2861	* luminance we need to use:	2863	caps->aux_min_input_signal = luminance_range->min_luminance;
2862	* Luminance = 502*(CV/32)	2864	caps->aux_max_input_signal = luminance_range->max_luminance;
2863	* Where CV is a one-byte value.
2864	* For calculating this expression we may need float point precision;
2865	* to avoid this complexity level, we take advantage that CV is divided
2866	* by a constant. From the Euclids division algorithm, we know that CV
2867	* can be written as: CV = 32*q + r. Next, we replace CV in the
2868	* Luminance expression and get 50(2q)(2**(r/32)), hence we just
2869	* need to pre-compute the value of r/32. For pre-computing the values
2870	* We just used the following Ruby line:
2871	* (0...32).each {\|cv\| puts (502*(cv/32.0)).round}
2872	* The results of the above expressions can be verified at
2873	* pre_computed_values.
2874	*/
2875	q = max_avg >> 5;
2876	r = max_avg % 32;
2877	max = (1 << q) * pre_computed_values[r];
2878
2879	// min luminance: maxLum * (CV/255)^2 / 100
2880	q = DIV_ROUND_CLOSEST(min_cll, 255);
2881	min = max * DIV_ROUND_CLOSEST((q * q), 100);
2882
2883	caps->aux_max_input_signal = max;
2884	caps->aux_min_input_signal = min;
2885	}	2865	}
2886		2866
2887	void amdgpu_dm_update_connector_after_detect(	2867	void amdgpu_dm_update_connector_after_detect(
@@ -5638,7 +5618,8 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, · 2750 unmodified lines
5638	dc_dsc_policy_set_enable_dsc_when_not_needed(	5618	dc_dsc_policy_set_enable_dsc_when_not_needed(
5639	aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);	5619	aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5640		5620
5641	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && !dc->debug.disable_dsc_edp &&	5621	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
		5622	!aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5642	dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {	5623	dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5643		5624
5644	apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);	5625	apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
@@ -6330,10 +6311,17 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, · 685 unmodified lines
6330	drm_atomic_get_old_connector_state(state, conn);	6311	drm_atomic_get_old_connector_state(state, conn);
6331	struct drm_crtc *crtc = new_con_state->crtc;	6312	struct drm_crtc *crtc = new_con_state->crtc;
6332	struct drm_crtc_state *new_crtc_state;	6313	struct drm_crtc_state *new_crtc_state;
		6314	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6333	int ret;	6315	int ret;
6334		6316
6335	trace_amdgpu_dm_connector_atomic_check(new_con_state);	6317	trace_amdgpu_dm_connector_atomic_check(new_con_state);
6336		6318
		6319	if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
		6320	ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
		6321	if (ret < 0)
		6322	return ret;
		6323	}
		6324
6337	if (!crtc)	6325	if (!crtc)
6338	return 0;	6326	return 0;
6339		6327
@@ -6417,6 +6405,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, · 77 unmodified lines
6417	const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;	6405	const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6418	struct drm_dp_mst_topology_mgr *mst_mgr;	6406	struct drm_dp_mst_topology_mgr *mst_mgr;
6419	struct drm_dp_mst_port *mst_port;	6407	struct drm_dp_mst_port *mst_port;
		6408	struct drm_dp_mst_topology_state *mst_state;
6420	enum dc_color_depth color_depth;	6409	enum dc_color_depth color_depth;
6421	int clock, bpp = 0;	6410	int clock, bpp = 0;
6422	bool is_y420 = false;	6411	bool is_y420 = false;
@@ -6430,6 +6419,13 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, · 7 unmodified lines
6430	if (!crtc_state->connectors_changed && !crtc_state->mode_changed)	6419	if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6431	return 0;	6420	return 0;
6432		6421
		6422	mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
		6423	if (IS_ERR(mst_state))
		6424	return PTR_ERR(mst_state);
		6425
		6426	if (!mst_state->pbn_div)
		6427	mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_port->dc_link);
		6428
6433	if (!state->duplicated) {	6429	if (!state->duplicated) {
6434	int max_bpc = conn_state->max_requested_bpc;	6430	int max_bpc = conn_state->max_requested_bpc;
6435	is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&	6431	is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
@@ -6441,11 +6437,10 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, · 5 unmodified lines
6441	clock = adjusted_mode->clock;	6437	clock = adjusted_mode->clock;
6442	dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);	6438	dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6443	}	6439	}
6444	dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,	6440
6445	mst_mgr,	6441	dm_new_connector_state->vcpi_slots =
6446	mst_port,	6442	drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6447	dm_new_connector_state->pbn,	6443	dm_new_connector_state->pbn);
6448	dm_mst_get_pbn_divider(aconnector->dc_link));
6449	if (dm_new_connector_state->vcpi_slots < 0) {	6444	if (dm_new_connector_state->vcpi_slots < 0) {
6450	DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);	6445	DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6451	return dm_new_connector_state->vcpi_slots;	6446	return dm_new_connector_state->vcpi_slots;
@@ -6515,18 +6510,12 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, · 63 unmodified lines
6515	dm_conn_state->pbn = pbn;	6510	dm_conn_state->pbn = pbn;
6516	dm_conn_state->vcpi_slots = slot_num;	6511	dm_conn_state->vcpi_slots = slot_num;
6517		6512
6518	drm_dp_mst_atomic_enable_dsc(state,	6513	drm_dp_mst_atomic_enable_dsc(state, aconnector->port, dm_conn_state->pbn,
6519	aconnector->port,
6520	dm_conn_state->pbn,
6521	0,
6522	false);	6514	false);
6523	continue;	6515	continue;
6524	}	6516	}
6525		6517
6526	vcpi = drm_dp_mst_atomic_enable_dsc(state,	6518	vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, pbn, true);
6527	aconnector->port,
6528	pbn, pbn_div,
6529	true);
6530	if (vcpi < 0)	6519	if (vcpi < 0)
6531	return vcpi;	6520	return vcpi;
6532		6521
@@ -7396,11 +7385,6 @@ static void update_freesync_state_on_stream( · 863 unmodified lines
7396	&vrr_infopacket,	7385	&vrr_infopacket,
7397	pack_sdp_v1_3);	7386	pack_sdp_v1_3);
7398		7387
7399	new_crtc_state->freesync_timing_changed \|=
7400	(memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
7401	&vrr_params.adjust,
7402	sizeof(vrr_params.adjust)) != 0);
7403
7404	new_crtc_state->freesync_vrr_info_changed \|=	7388	new_crtc_state->freesync_vrr_info_changed \|=
7405	(memcmp(&new_crtc_state->vrr_infopacket,	7389	(memcmp(&new_crtc_state->vrr_infopacket,
7406	&vrr_infopacket,	7390	&vrr_infopacket,
@@ -7409,7 +7393,6 @@ static void update_freesync_state_on_stream( · 2 unmodified lines
7409	acrtc->dm_irq_params.vrr_params = vrr_params;	7393	acrtc->dm_irq_params.vrr_params = vrr_params;
7410	new_crtc_state->vrr_infopacket = vrr_infopacket;	7394	new_crtc_state->vrr_infopacket = vrr_infopacket;
7411		7395
7412	new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust;
7413	new_stream->vrr_infopacket = vrr_infopacket;	7396	new_stream->vrr_infopacket = vrr_infopacket;
7414		7397
7415	if (new_crtc_state->freesync_vrr_info_changed)	7398	if (new_crtc_state->freesync_vrr_info_changed)
@@ -7472,10 +7455,6 @@ static void update_stream_irq_parameters( · 56 unmodified lines
7472	new_stream,	7455	new_stream,
7473	&config, &vrr_params);	7456	&config, &vrr_params);
7474		7457
7475	new_crtc_state->freesync_timing_changed \|=
7476	(memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
7477	&vrr_params.adjust, sizeof(vrr_params.adjust)) != 0);
7478
7479	new_crtc_state->freesync_config = config;	7458	new_crtc_state->freesync_config = config;
7480	/* Copy state for access from DM IRQ handler */	7459	/* Copy state for access from DM IRQ handler */
7481	acrtc->dm_irq_params.freesync_config = config;	7460	acrtc->dm_irq_params.freesync_config = config;
@@ -8001,6 +7980,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 519 unmodified lines
8001	DRM_ERROR("Waiting for fences timed out!");	7980	DRM_ERROR("Waiting for fences timed out!");
8002		7981
8003	drm_atomic_helper_update_legacy_modeset_state(dev, state);	7982	drm_atomic_helper_update_legacy_modeset_state(dev, state);
		7983	drm_dp_mst_atomic_wait_for_dependencies(state);
8004		7984
8005	dm_state = dm_atomic_get_new_state(state);	7985	dm_state = dm_atomic_get_new_state(state);
8006	if (dm_state && dm_state->context) {	7986	if (dm_state && dm_state->context) {
@@ -8399,7 +8379,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 392 unmodified lines
8399	dc_release_state(dc_state_temp);	8379	dc_release_state(dc_state_temp);
8400	}	8380	}
8401		8381
8402
8403	static int dm_force_atomic_commit(struct drm_connector *connector)	8382	static int dm_force_atomic_commit(struct drm_connector *connector)
8404	{	8383	{
8405	int ret = 0;	8384	int ret = 0;
@@ -9330,6 +9309,7 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm · 924 unmodified lines
9330		9309
9331	/**	9310	/**
9332	* amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.	9311	* amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
		9312	*
9333	* @dev: The DRM device	9313	* @dev: The DRM device
9334	* @state: The atomic state to commit	9314	* @state: The atomic state to commit
9335	*	9315	*
@@ -9370,8 +9350,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 34 unmodified lines
9370	struct dm_crtc_state dm_old_crtc_state, dm_new_crtc_state;	9350	struct dm_crtc_state dm_old_crtc_state, dm_new_crtc_state;
9371	#if defined(CONFIG_DRM_AMD_DC_DCN)	9351	#if defined(CONFIG_DRM_AMD_DC_DCN)
9372	struct dsc_mst_fairness_vars vars[MAX_PIPES];	9352	struct dsc_mst_fairness_vars vars[MAX_PIPES];
9373	struct drm_dp_mst_topology_state *mst_state;
9374	struct drm_dp_mst_topology_mgr *mgr;
9375	#endif	9353	#endif
9376		9354
9377	trace_amdgpu_dm_atomic_check_begin(state);	9355	trace_amdgpu_dm_atomic_check_begin(state);
@@ -9388,9 +9366,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 10 unmodified lines
9388	struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);	9366	struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9389		9367
9390	/* Skip connectors that are disabled or part of modeset already. */	9368	/* Skip connectors that are disabled or part of modeset already. */
9391	if (!old_con_state->crtc && !new_con_state->crtc)
9392	continue;
9393
9394	if (!new_con_state->crtc)	9369	if (!new_con_state->crtc)
9395	continue;	9370	continue;
9396		9371
@@ -9618,33 +9593,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 221 unmodified lines
9618	lock_and_validation_needed = true;	9593	lock_and_validation_needed = true;
9619	}	9594	}
9620		9595
9621	#if defined(CONFIG_DRM_AMD_DC_DCN)
9622	/* set the slot info for each mst_state based on the link encoding format */
9623	for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
9624	struct amdgpu_dm_connector *aconnector;
9625	struct drm_connector *connector;
9626	struct drm_connector_list_iter iter;
9627	u8 link_coding_cap;
9628
9629	if (!mgr->mst_state )
9630	continue;
9631
9632	drm_connector_list_iter_begin(dev, &iter);
9633	drm_for_each_connector_iter(connector, &iter) {
9634	int id = connector->index;
9635
9636	if (id == mst_state->mgr->conn_base_id) {
9637	aconnector = to_amdgpu_dm_connector(connector);
9638	link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
9639	drm_dp_mst_update_slots(mst_state, link_coding_cap);
9640
9641	break;
9642	}
9643	}
9644	drm_connector_list_iter_end(&iter);
9645
9646	}
9647	#endif
9648	/**	9596	/**
9649	* Streams and planes are reset when there are changes that affect	9597	* Streams and planes are reset when there are changes that affect
9650	* bandwidth. Anything that affects bandwidth needs to go through	9598	* bandwidth. Anything that affects bandwidth needs to go through
@@ -9952,8 +9900,19 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, · 301 unmodified lines
9952	return valid_vsdb_found ? i : -ENODEV;	9900	return valid_vsdb_found ? i : -ENODEV;
9953	}	9901	}
9954		9902
		9903	/**
		9904	* amdgpu_dm_update_freesync_caps - Update Freesync capabilities
		9905	*
		9906	* @connector: Connector to query.
		9907	* @edid: EDID from monitor
		9908	*
		9909	* Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
		9910	* track of some of the display information in the internal data struct used by
		9911	* amdgpu_dm. This function checks which type of connector we need to set the
		9912	* FreeSync parameters.
		9913	*/
9955	void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,	9914	void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
9956	struct edid *edid)	9915	struct edid *edid)
9957	{	9916	{
9958	int i = 0;	9917	int i = 0;
9959	struct detailed_timing *timing;	9918	struct detailed_timing *timing;
@@ -9966,8 +9925,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, · 6 unmodified lines
9966		9925
9967	struct drm_device *dev = connector->dev;	9926	struct drm_device *dev = connector->dev;
9968	struct amdgpu_device *adev = drm_to_adev(dev);	9927	struct amdgpu_device *adev = drm_to_adev(dev);
9969	bool freesync_capable = false;
9970	struct amdgpu_hdmi_vsdb_info vsdb_info = {0};	9928	struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
		9929	bool freesync_capable = false;
9971		9930
9972	if (!connector->state) {	9931	if (!connector->state) {
9973	DRM_ERROR("%s - Connector has no state", __func__);	9932	DRM_ERROR("%s - Connector has no state", __func__);
@@ -9996,7 +9955,6 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, · 22 unmodified lines
9996	if (!adev->dm.freesync_module)	9955	if (!adev->dm.freesync_module)
9997	goto update;	9956	goto update;
9998		9957
9999
10000	if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT	9958	if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10001	\|\| sink->sink_signal == SIGNAL_TYPE_EDP) {	9959	\|\| sink->sink_signal == SIGNAL_TYPE_EDP) {
10002	bool edid_check_required = false;	9960	bool edid_check_required = false;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h+41−6

@@ -598,6 +598,10 @@ struct amdgpu_dm_connector { · 597 unmodified lines
598	* The 'current' sink is in dc_link->sink. */	598	* The 'current' sink is in dc_link->sink. */
599	struct dc_sink *dc_sink;	599	struct dc_sink *dc_sink;
600	struct dc_link *dc_link;	600	struct dc_link *dc_link;
		601
		602	/**
		603	* @dc_em_sink: Reference to the emulated (virtual) sink.
		604	*/
601	struct dc_sink *dc_em_sink;	605	struct dc_sink *dc_em_sink;
602		606
603	/* DM only */	607	/* DM only */
@@ -610,7 +614,16 @@ struct amdgpu_dm_connector { · 6 unmodified lines
610	struct amdgpu_i2c_adapter *i2c;	614	struct amdgpu_i2c_adapter *i2c;
611		615
612	/* Monitor range limits */	616	/* Monitor range limits */
613	int min_vfreq ;	617	/**
		618	* @min_vfreq: Minimal frequency supported by the display in Hz. This
		619	* value is set to zero when there is no FreeSync support.
		620	*/
		621	int min_vfreq;
		622
		623	/**
		624	* @max_vfreq: Maximum frequency supported by the display in Hz. This
		625	* value is set to zero when there is no FreeSync support.
		626	*/
614	int max_vfreq ;	627	int max_vfreq ;
615	int pixel_clock_mhz;	628	int pixel_clock_mhz;
616		629
@@ -668,7 +681,6 @@ struct dm_crtc_state { · 51 unmodified lines
668		681
669	int crc_skip_count;	682	int crc_skip_count;
670		683
671	bool freesync_timing_changed;
672	bool freesync_vrr_info_changed;	684	bool freesync_vrr_info_changed;
673		685
674	bool dsc_force_changed;	686	bool dsc_force_changed;
@@ -705,11 +717,34 @@ struct dm_connector_state { · 30 unmodified lines
705	uint64_t pbn;	717	uint64_t pbn;
706	};	718	};
707		719
		720	/**
		721	* struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info
		722	*
		723	* AMDGPU supports FreeSync over HDMI by using the VSDB section, and this
		724	* struct is useful to keep track of the display-specific information about
		725	* FreeSync.
		726	*/
708	struct amdgpu_hdmi_vsdb_info {	727	struct amdgpu_hdmi_vsdb_info {
709	unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */	728	/**
710	bool freesync_supported; /* FreeSync Supported */	729	* @amd_vsdb_version: Vendor Specific Data Block Version, should be
711	unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */	730	* used to determine which Vendor Specific InfoFrame (VSIF) to send.
712	unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */	731	*/
		732	unsigned int amd_vsdb_version;
		733
		734	/**
		735	* @freesync_supported: FreeSync Supported.
		736	*/
		737	bool freesync_supported;
		738
		739	/**
		740	* @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz.
		741	*/
		742	unsigned int min_refresh_rate_hz;
		743
		744	/**
		745	* @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz
		746	*/
		747	unsigned int max_refresh_rate_hz;
713	};	748	};
714		749
715		750

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c+81−28

 #include "modules/color/color_gamma.h"
 #include "basics/conversion.h"
-/*
+/**
+ * DOC: overview
+ *
  * The DC interface to HW gives us the following color management blocks
  * per pipe (surface):
  *
 #define MAX_DRM_LUT_VALUE 0xFFFF
-/*
+/**
- * Initialize the color module.
+ * amdgpu_dm_init_color_mod - Initialize the color module.
  *
  * We're not using the full color module, only certain components.
  * Only call setup functions for components that we need.
 	setup_x_points_distribution();
 }
-/* Extracts the DRM lut and lut size from a blob. */
+/**
+ * __extract_blob_lut - Extracts the DRM lut and lut size from a blob.
+ * @blob: DRM color mgmt property blob
+ * @size: lut size
+ *
+ * Returns:
+ * DRM LUT or NULL
+ */
 static const struct drm_color_lut *
 __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
 {
 	return blob ? (struct drm_color_lut *)blob->data : NULL;
 }
-/*
+/**
- * Return true if the given lut is a linear mapping of values, i.e. it acts
+ * __is_lut_linear - check if the given lut is a linear mapping of values
- * like a bypass LUT.
+ * @lut: given lut to check values
+ * @size: lut size
  *
  * It is considered linear if the lut represents:
- * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in
+ * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0,
- *                                           [0, MAX_COLOR_LUT_ENTRIES)
+ * MAX_COLOR_LUT_ENTRIES)
+ *
+ * Returns:
+ * True if the given lut is a linear mapping of values, i.e. it acts like a
+ * bypass LUT. Otherwise, false.
  */
 static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
 {
 	return true;
 }
-/*
+/**
- * Convert the drm_color_lut to dc_gamma. The conversion depends on the size
+ * __drm_lut_to_dc_gamma - convert the drm_color_lut to dc_gamma.
- * of the lut - whether or not it's legacy.
+ * @lut: DRM lookup table for color conversion
+ * @gamma: DC gamma to set entries
+ * @is_legacy: legacy or atomic gamma
+ *
+ * The conversion depends on the size of the lut - whether or not it's legacy.
  */
 static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
 				  struct dc_gamma *gamma, bool is_legacy)
 	}
 }
-/*
+/**
- * Converts a DRM CTM to a DC CSC float matrix.
+ * __drm_ctm_to_dc_matrix - converts a DRM CTM to a DC CSC float matrix
+ * @ctm: DRM color transformation matrix
+ * @matrix: DC CSC float matrix
+ *
  * The matrix needs to be a 3x4 (12 entry) matrix.
  */
 static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
 	}
 }
-/* Calculates the legacy transfer function - only for sRGB input space. */
+/**
+ * __set_legacy_tf - Calculates the legacy transfer function
+ * @func: transfer function
+ * @lut: lookup table that defines the color space
+ * @lut_size: size of respective lut
+ * @has_rom: if ROM can be used for hardcoded curve
+ *
+ * Only for sRGB input space
+ *
+ * Returns:
+ * 0 in case of success, -ENOMEM if fails
+ */
 static int __set_legacy_tf(struct dc_transfer_func *func,
 			   const struct drm_color_lut *lut, uint32_t lut_size,
 			   bool has_rom)
 	return res ? 0 : -ENOMEM;
 }
-/* Calculates the output transfer function based on expected input space. */
+/**
+ * __set_output_tf - calculates the output transfer function based on expected input space.
+ * @func: transfer function
+ * @lut: lookup table that defines the color space
+ * @lut_size: size of respective lut
+ * @has_rom: if ROM can be used for hardcoded curve
+ *
+ * Returns:
+ * 0 in case of success. -ENOMEM if fails.
+ */
 static int __set_output_tf(struct dc_transfer_func *func,
 			   const struct drm_color_lut *lut, uint32_t lut_size,
 			   bool has_rom)
 	return res ? 0 : -ENOMEM;
 }
-/* Caculates the input transfer function based on expected input space. */
+/**
+ * __set_input_tf - calculates the input transfer function based on expected
+ * input space.
+ * @func: transfer function
+ * @lut: lookup table that defines the color space
+ * @lut_size: size of respective lut.
+ *
+ * Returns:
+ * 0 in case of success. -ENOMEM if fails.
+ */
 static int __set_input_tf(struct dc_transfer_func *func,
 			  const struct drm_color_lut *lut, uint32_t lut_size)
 {
 }
 /**
- * amdgpu_dm_verify_lut_sizes
+ * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes
  * @crtc_state: the DRM CRTC state
  *
- * Verifies that the Degamma and Gamma LUTs attached to the |crtc_state| are of
+ * Verifies that the Degamma and Gamma LUTs attached to the &crtc_state
- * the expected size.
+ * are of the expected size.
  *
- * Returns 0 on success.
+ * Returns:
+ * 0 on success. -EINVAL if any lut sizes are invalid.
  */
 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
 {
  * of the HW blocks as long as the CRTC CTM always comes before the
  * CRTC RGM and after the CRTC DGM.
  *
- * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
+ * - The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
- * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
+ * - The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
- * The CRTC CTM will be placed in the gamut remap block if it is non-linear.
+ * - The CRTC CTM will be placed in the gamut remap block if it is non-linear.
  *
  * The RGM block is typically more fully featured and accurate across
  * all ASICs - DCE can't support a custom non-linear CRTC DGM.
  * management at once we have to either restrict the usage of CRTC properties
  * or blend adjustments together.
  *
- * Returns 0 on success.
+ * Returns:
+ * 0 on success. Error code if setup fails.
  */
 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
 {
 		if (r)
 			return r;
 	} else if (has_regamma) {
-		/* CRTC RGM goes into RGM LUT. */
+		/* If atomic regamma, CRTC RGM goes into RGM LUT. */
 		stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
 		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
  *
  * Update the underlying dc_stream_state's input transfer function (ITF) in
  * preparation for hardware commit. The transfer function used depends on
- * the prepartion done on the stream for color management.
+ * the preparation done on the stream for color management.
  *
- * Returns 0 on success.
+ * Returns:
+ * 0 on success. -ENOMEM if mem allocation fails.
  */
 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
 				      struct dc_plane_state *dc_plane_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c+104−77

@@ -27,6 +27,7 @@ · 26 unmodified lines
27	#include <linux/acpi.h>	27	#include <linux/acpi.h>
28	#include <linux/i2c.h>	28	#include <linux/i2c.h>
29		29
		30	#include <drm/drm_atomic.h>
30	#include <drm/drm_probe_helper.h>	31	#include <drm/drm_probe_helper.h>
31	#include <drm/amdgpu_drm.h>	32	#include <drm/amdgpu_drm.h>
32	#include <drm/drm_edid.h>	33	#include <drm/drm_edid.h>
@@ -153,41 +154,28 @@ enum dc_edid_status dm_helpers_parse_edid_caps( · 120 unmodified lines
153	return result;	154	return result;
154	}	155	}
155		156
156	static void get_payload_table(	157	static void
157	struct amdgpu_dm_connector *aconnector,	158	fill_dc_mst_payload_table_from_drm(struct drm_dp_mst_topology_state *mst_state,
158	struct dp_mst_stream_allocation_table *proposed_table)	159	struct amdgpu_dm_connector *aconnector,
		160	struct dc_dp_mst_stream_allocation_table *table)
159	{	161	{
160	int i;	162	struct dc_dp_mst_stream_allocation_table new_table = { 0 };
161	struct drm_dp_mst_topology_mgr *mst_mgr =	163	struct dc_dp_mst_stream_allocation *sa;
162	&aconnector->mst_port->mst_mgr;	164	struct drm_dp_mst_atomic_payload *payload;
163		165
164	mutex_lock(&mst_mgr->payload_lock);	166	/* Fill payload info*/
165		167	list_for_each_entry(payload, &mst_state->payloads, next) {
166	proposed_table->stream_count = 0;	168	if (payload->delete)
167		169	continue;
168	/* number of active streams */	170
169	for (i = 0; i < mst_mgr->max_payloads; i++) {	171	sa = &new_table.stream_allocations[new_table.stream_count];
170	if (mst_mgr->payloads[i].num_slots == 0)	172	sa->slot_count = payload->time_slots;
171	break; /* end of vcp_id table */	173	sa->vcp_id = payload->vcpi;
172		174	new_table.stream_count++;
173	ASSERT(mst_mgr->payloads[i].payload_state !=
174	DP_PAYLOAD_DELETE_LOCAL);
175
176	if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL \|\|
177	mst_mgr->payloads[i].payload_state ==
178	DP_PAYLOAD_REMOTE) {
179
180	struct dp_mst_stream_allocation *sa =
181	&proposed_table->stream_allocations[
182	proposed_table->stream_count];
183
184	sa->slot_count = mst_mgr->payloads[i].num_slots;
185	sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
186	proposed_table->stream_count++;
187	}
188	}	175	}
189		176
190	mutex_unlock(&mst_mgr->payload_lock);	177	/* Overwrite the old table */
		178	*table = new_table;
191	}	179	}
192		180
193	void dm_helpers_dp_update_branch_info(	181	void dm_helpers_dp_update_branch_info(
@@ -201,15 +189,13 @@ void dm_helpers_dp_update_branch_info( · 7 unmodified lines
201	bool dm_helpers_dp_mst_write_payload_allocation_table(	189	bool dm_helpers_dp_mst_write_payload_allocation_table(
202	struct dc_context *ctx,	190	struct dc_context *ctx,
203	const struct dc_stream_state *stream,	191	const struct dc_stream_state *stream,
204	struct dp_mst_stream_allocation_table *proposed_table,	192	struct dc_dp_mst_stream_allocation_table *proposed_table,
205	bool enable)	193	bool enable)
206	{	194	{
207	struct amdgpu_dm_connector *aconnector;	195	struct amdgpu_dm_connector *aconnector;
208	struct dm_connector_state *dm_conn_state;	196	struct drm_dp_mst_topology_state *mst_state;
		197	struct drm_dp_mst_atomic_payload *payload;
209	struct drm_dp_mst_topology_mgr *mst_mgr;	198	struct drm_dp_mst_topology_mgr *mst_mgr;
210	struct drm_dp_mst_port *mst_port;
211	bool ret;
212	u8 link_coding_cap = DP_8b_10b_ENCODING;
213		199
214	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;	200	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
215	/* Accessing the connector state is required for vcpi_slots allocation	201	/* Accessing the connector state is required for vcpi_slots allocation
@@ -220,40 +206,21 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( · 4 unmodified lines
220	if (!aconnector \|\| !aconnector->mst_port)	206	if (!aconnector \|\| !aconnector->mst_port)
221	return false;	207	return false;
222		208
223	dm_conn_state = to_dm_connector_state(aconnector->base.state);
224
225	mst_mgr = &aconnector->mst_port->mst_mgr;	209	mst_mgr = &aconnector->mst_port->mst_mgr;
226		210	mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
227	if (!mst_mgr->mst_state)
228	return false;
229
230	mst_port = aconnector->port;
231
232	#if defined(CONFIG_DRM_AMD_DC_DCN)
233	link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
234	#endif
235
236	if (enable) {
237
238	ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port,
239	dm_conn_state->pbn,
240	dm_conn_state->vcpi_slots);
241	if (!ret)
242	return false;
243
244	} else {
245	drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
246	}
247		211
248	/* It's OK for this to fail */	212	/* It's OK for this to fail */
249	drm_dp_update_payload_part1(mst_mgr, (link_coding_cap == DP_CAP_ANSI_128B132B) ? 0:1);	213	payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->port);
		214	if (enable)
		215	drm_dp_add_payload_part1(mst_mgr, mst_state, payload);
		216	else
		217	drm_dp_remove_payload(mst_mgr, mst_state, payload);
250		218
251	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or	219	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
252	* AUX message. The sequence is slot 1-63 allocated sequence for each	220	* AUX message. The sequence is slot 1-63 allocated sequence for each
253	* stream. AMD ASIC stream slot allocation should follow the same	221	* stream. AMD ASIC stream slot allocation should follow the same
254	* sequence. copy DRM MST allocation to dc */	222	* sequence. copy DRM MST allocation to dc */
255		223	fill_dc_mst_payload_table_from_drm(mst_state, aconnector, proposed_table);
256	get_payload_table(aconnector, proposed_table);
257		224
258	return true;	225	return true;
259	}	226	}
@@ -310,8 +277,9 @@ bool dm_helpers_dp_mst_send_payload_allocation( · 50 unmodified lines
310	bool enable)	277	bool enable)
311	{	278	{
312	struct amdgpu_dm_connector *aconnector;	279	struct amdgpu_dm_connector *aconnector;
		280	struct drm_dp_mst_topology_state *mst_state;
313	struct drm_dp_mst_topology_mgr *mst_mgr;	281	struct drm_dp_mst_topology_mgr *mst_mgr;
314	struct drm_dp_mst_port *mst_port;	282	struct drm_dp_mst_atomic_payload *payload;
315	enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;	283	enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
316	enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;	284	enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
317		285
@@ -320,19 +288,16 @@ bool dm_helpers_dp_mst_send_payload_allocation( · 2 unmodified lines
320	if (!aconnector \|\| !aconnector->mst_port)	288	if (!aconnector \|\| !aconnector->mst_port)
321	return false;	289	return false;
322		290
323	mst_port = aconnector->port;
324
325	mst_mgr = &aconnector->mst_port->mst_mgr;	291	mst_mgr = &aconnector->mst_port->mst_mgr;
		292	mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
326		293
327	if (!mst_mgr->mst_state)	294	payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->port);
328	return false;
329
330	if (!enable) {	295	if (!enable) {
331	set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;	296	set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
332	clr_flag = MST_ALLOCATE_NEW_PAYLOAD;	297	clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
333	}	298	}
334		299
335	if (drm_dp_update_payload_part2(mst_mgr)) {	300	if (enable && drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload)) {
336	amdgpu_dm_set_mst_status(&aconnector->mst_status,	301	amdgpu_dm_set_mst_status(&aconnector->mst_status,
337	set_flag, false);	302	set_flag, false);
338	} else {	303	} else {
@@ -342,9 +307,6 @@ bool dm_helpers_dp_mst_send_payload_allocation( · 3 unmodified lines
342	clr_flag, false);	307	clr_flag, false);
343	}	308	}
344		309
345	if (!enable)
346	drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
347
348	return true;	310	return true;
349	}	311	}
350		312
@@ -729,8 +691,14 @@ bool dm_helpers_dp_write_dsc_enable( · 378 unmodified lines
729	const struct dc_stream_state *stream,	691	const struct dc_stream_state *stream,
730	bool enable)	692	bool enable)
731	{	693	{
732	uint8_t enable_dsc = enable ? 1 : 0;	694	static const uint8_t DSC_DISABLE;
		695	static const uint8_t DSC_DECODING = 0x01;
		696	static const uint8_t DSC_PASSTHROUGH = 0x02;
		697
733	struct amdgpu_dm_connector *aconnector;	698	struct amdgpu_dm_connector *aconnector;
		699	struct drm_dp_mst_port *port;
		700	uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
		701	uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
734	uint8_t ret = 0;	702	uint8_t ret = 0;
735		703
736	if (!stream)	704	if (!stream)
@@ -750,8 +718,39 @@ bool dm_helpers_dp_write_dsc_enable( · 13 unmodified lines
750	aconnector->dsc_aux, stream, enable_dsc);	718	aconnector->dsc_aux, stream, enable_dsc);
751	#endif	719	#endif
752		720
753	ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1);	721	port = aconnector->port;
754	DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable");	722
		723	if (enable) {
		724	if (port->passthrough_aux) {
		725	ret = drm_dp_dpcd_write(port->passthrough_aux,
		726	DP_DSC_ENABLE,
		727	&enable_passthrough, 1);
		728	DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
		729	ret);
		730	}
		731
		732	ret = drm_dp_dpcd_write(aconnector->dsc_aux,
		733	DP_DSC_ENABLE, &enable_dsc, 1);
		734	DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n",
		735	(port->passthrough_aux) ? "remote RX" :
		736	"virtual dpcd",
		737	ret);
		738	} else {
		739	ret = drm_dp_dpcd_write(aconnector->dsc_aux,
		740	DP_DSC_ENABLE, &enable_dsc, 1);
		741	DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n",
		742	(port->passthrough_aux) ? "remote RX" :
		743	"virtual dpcd",
		744	ret);
		745
		746	if (port->passthrough_aux) {
		747	ret = drm_dp_dpcd_write(port->passthrough_aux,
		748	DP_DSC_ENABLE,
		749	&enable_passthrough, 1);
		750	DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
		751	ret);
		752	}
		753	}
755	}	754	}
756		755
757	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT \|\| stream->signal == SIGNAL_TYPE_EDP) {	756	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT \|\| stream->signal == SIGNAL_TYPE_EDP) {
@@ -768,7 +767,7 @@ bool dm_helpers_dp_write_dsc_enable( · 10 unmodified lines
768	#endif	767	#endif
769	}	768	}
770		769
771	return (ret > 0);	770	return ret;
772	}	771	}
773		772
774	bool dm_helpers_is_dp_sink_present(struct dc_link *link)	773	bool dm_helpers_is_dp_sink_present(struct dc_link *link)
@@ -879,6 +878,34 @@ void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigne · 104 unmodified lines
879	//amdgpu_device_gpu_recover(dc_context->driver-context, NULL);	878	//amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
880	}	879	}
881		880
		881	void dm_helpers_init_panel_settings(
		882	struct dc_context *ctx,
		883	struct dc_panel_config *panel_config,
		884	struct dc_sink *sink)
		885	{
		886	// Extra Panel Power Sequence
		887	panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
		888	panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
		889	panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
		890	panel_config->pps.extra_post_t7_ms = 0;
		891	panel_config->pps.extra_pre_t11_ms = 0;
		892	panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
		893	panel_config->pps.extra_post_OUI_ms = 0;
		894	// Feature DSC
		895	panel_config->dsc.disable_dsc_edp = false;
		896	panel_config->dsc.force_dsc_edp_policy = 0;
		897	}
		898
		899	void dm_helpers_override_panel_settings(
		900	struct dc_context *ctx,
		901	struct dc_panel_config *panel_config)
		902	{
		903	// Feature DSC
		904	if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
		905	panel_config->dsc.disable_dsc_edp = true;
		906	}
		907	}
		908
882	void *dm_helpers_allocate_gpu_mem(	909	void *dm_helpers_allocate_gpu_mem(
883	struct dc_context *ctx,	910	struct dc_context *ctx,
884	enum dc_gpu_mem_alloc_type type,	911	enum dc_gpu_mem_alloc_type type,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+123−86

@@ -36,6 +36,7 @@ · 35 unmodified lines
36	#include "dm_helpers.h"	36	#include "dm_helpers.h"
37		37
38	#include "dc_link_ddc.h"	38	#include "dc_link_ddc.h"
		39	#include "dc_link_dp.h"
39	#include "ddc_service_types.h"	40	#include "ddc_service_types.h"
40	#include "dpcd_defs.h"	41	#include "dpcd_defs.h"
41		42
@@ -447,34 +448,13 @@ dm_dp_mst_detect(struct drm_connector *connector, · 405 unmodified lines
447	}	448	}
448		449
449	static int dm_dp_mst_atomic_check(struct drm_connector *connector,	450	static int dm_dp_mst_atomic_check(struct drm_connector *connector,
450	struct drm_atomic_state *state)	451	struct drm_atomic_state *state)
451	{	452	{
452	struct drm_connector_state *new_conn_state =
453	drm_atomic_get_new_connector_state(state, connector);
454	struct drm_connector_state *old_conn_state =
455	drm_atomic_get_old_connector_state(state, connector);
456	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);	453	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
457	struct drm_crtc_state *new_crtc_state;	454	struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_port->mst_mgr;
458	struct drm_dp_mst_topology_mgr *mst_mgr;	455	struct drm_dp_mst_port *mst_port = aconnector->port;
459	struct drm_dp_mst_port *mst_port;
460		456
461	mst_port = aconnector->port;	457	return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
462	mst_mgr = &aconnector->mst_port->mst_mgr;
463
464	if (!old_conn_state->crtc)
465	return 0;
466
467	if (new_conn_state->crtc) {
468	new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
469	if (!new_crtc_state \|\|
470	!drm_atomic_crtc_needs_modeset(new_crtc_state) \|\|
471	new_crtc_state->enable)
472	return 0;
473	}
474
475	return drm_dp_atomic_release_vcpi_slots(state,
476	mst_mgr,
477	mst_port);
478	}	458	}
479		459
480	static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {	460	static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
@@ -618,15 +598,8 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, · 137 unmodified lines
618		598
619	dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);	599	dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
620	aconnector->mst_mgr.cbs = &dm_mst_cbs;	600	aconnector->mst_mgr.cbs = &dm_mst_cbs;
621	drm_dp_mst_topology_mgr_init(	601	drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
622	&aconnector->mst_mgr,
623	adev_to_drm(dm->adev),
624	&aconnector->dm_dp_aux.aux,
625	16,
626	4,
627	max_link_enc_cap.lane_count,
628	drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate),
629	aconnector->connector_id);

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drivers/gpu/drm/arm/hdlcd_crtc.c+5−6

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drivers/gpu/drm/arm/hdlcd_drv.c+28−49

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drivers/gpu/drm/armada/armada_crtc.c+0−1

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drivers/gpu/drm/armada/armada_overlay.c+1−7

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drivers/gpu/drm/ast/ast_tables.h+7−0

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drivers/gpu/drm/atmel-hlcdc/Kconfig+1−1

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drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c+3−3

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drivers/gpu/drm/bridge/adv7511/adv7511.h+1−4

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drivers/gpu/drm/bridge/adv7511/adv7511_cec.c+2−2

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drivers/gpu/drm/bridge/analogix/anx7625.c+32−6

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drivers/gpu/drm/bridge/analogix/anx7625.h+6−0

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drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c+2−1

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drivers/gpu/drm/bridge/chipone-icn6211.c+38−10

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drivers/gpu/drm/bridge/ite-it6505.c+18−9

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drivers/gpu/drm/bridge/lontium-lt8912b.c+17−9

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drivers/gpu/drm/bridge/lontium-lt9611.c+2−1

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drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c+3−1

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drivers/gpu/drm/bridge/parade-ps8640.c+7−2

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drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c+3−3

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drivers/gpu/drm/bridge/tc358767.c+40−50

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drivers/gpu/drm/bridge/ti-sn65dsi86.c+96−23

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drivers/gpu/drm/display/drm_dp_helper.c+33−10

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drivers/gpu/drm/display/drm_dp_mst_topology.c+518−631

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drivers/gpu/drm/drm_aperture.c+5−5

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drivers/gpu/drm/drm_client.c+2−2

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drivers/gpu/drm/drm_color_mgmt.c+1−1

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drivers/gpu/drm/drm_encoder.c+64−11

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drivers/gpu/drm/drm_fb_dma_helper.crenamed from drivers/gpu/drm/drm_fb_cma_helper.c+36−31

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drivers/gpu/drm/drm_file.c+1−142

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drivers/gpu/drm/drm_gem.c+170−0

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drivers/gpu/drm/drm_gem_dma_helper.crenamed from drivers/gpu/drm/drm_gem_cma_helper.c+151−151

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drivers/gpu/drm/drm_panel_orientation_quirks.c+18−0

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drivers/gpu/drm/drm_simple_kms_helper.c+2−3

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drivers/gpu/drm/exynos/exynos_drm_plane.c+0−1

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drivers/gpu/drm/exynos/exynos_hdmi.c+3−3

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drivers/gpu/drm/exynos/exynos_mixer.c+1−1

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drivers/gpu/drm/fsl-dcu/Kconfig+1−1

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drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c+6−12

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drivers/gpu/drm/gma500/backlight.c+68−34

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drivers/gpu/drm/gma500/cdv_device.c+9−41

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drivers/gpu/drm/gma500/cdv_intel_dp.c+1−1

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drivers/gpu/drm/gma500/gma_display.h+0−2

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drivers/gpu/drm/gma500/oaktrail_crtc.c+1−1

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drivers/gpu/drm/gma500/oaktrail_device.c+5−60

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drivers/gpu/drm/gma500/oaktrail_lvds.c+0−1

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drivers/gpu/drm/gma500/psb_device.c+4−69

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drivers/gpu/drm/gma500/psb_intel_display.c+0−2

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drivers/gpu/drm/gma500/psb_intel_drv.h+0−5

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drivers/gpu/drm/gma500/psb_intel_sdvo.c+41−21

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drivers/gpu/drm/gma500/psb_irq.c+7−8

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drivers/gpu/drm/gud/gud_pipe.c+21−13

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drivers/gpu/drm/hisilicon/kirin/Kconfig+1−1

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drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c+7−8

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drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c+1−2

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drivers/gpu/drm/hyperv/hyperv_drm_modeset.c+4−5

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drivers/gpu/drm/i915/Makefile+3−1

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drivers/gpu/drm/i915/display/g4x_dp.c+2−2

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drivers/gpu/drm/i915/display/hsw_ips.c+1−1

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drivers/gpu/drm/i915/display/i9xx_plane.c+3−4

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drivers/gpu/drm/i915/display/icl_dsi.c+7−10

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drivers/gpu/drm/i915/display/intel_atomic.c+4−5

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drivers/gpu/drm/i915/display/intel_atomic_plane.c+1−2

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drivers/gpu/drm/i915/display/intel_audio.c+51−51

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drivers/gpu/drm/i915/display/intel_backlight.c+22−20

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drivers/gpu/drm/i915/display/intel_backlight_regs.h+124−0

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drivers/gpu/drm/i915/display/intel_bios.c+204−171

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drivers/gpu/drm/i915/display/intel_bios.h+1−0

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drivers/gpu/drm/i915/display/intel_bw.c+103−35

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drivers/gpu/drm/i915/display/intel_cdclk.c+150−143

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drivers/gpu/drm/i915/display/intel_cdclk.h+2−2

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drivers/gpu/drm/i915/display/intel_color.c+18−17

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drivers/gpu/drm/i915/display/intel_connector.c+4−4

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drivers/gpu/drm/i915/display/intel_crt.c+7−6

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drivers/gpu/drm/i915/display/intel_crtc.c+0−1

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drivers/gpu/drm/i915/display/intel_crtc_state_dump.c+5−4

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drivers/gpu/drm/i915/display/intel_cursor.c+3−4

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drivers/gpu/drm/i915/display/intel_ddi.c+45−44

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drivers/gpu/drm/i915/display/intel_display.c+171−210

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drivers/gpu/drm/i915/display/intel_display.h+4−4

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drivers/gpu/drm/i915/display/intel_display_core.h+418−0

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drivers/gpu/drm/i915/display/intel_display_debugfs.c+49−98

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drivers/gpu/drm/i915/display/intel_display_power.c+80−73

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drivers/gpu/drm/i915/display/intel_display_power_map.c+116−3

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drivers/gpu/drm/i915/display/intel_display_power_well.c+87−42

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drivers/gpu/drm/i915/display/intel_display_power_well.h+10−6

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drivers/gpu/drm/i915/display/intel_display_types.h+3−2

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drivers/gpu/drm/i915/display/intel_dmc.c+108−34

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drivers/gpu/drm/i915/display/intel_dmc.h+1−0

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drivers/gpu/drm/i915/display/intel_dmc_regs.h+2−0

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drivers/gpu/drm/i915/display/intel_dp.c+82−39

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drivers/gpu/drm/i915/display/intel_dp_aux.c+54−3

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drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c+13−2

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drivers/gpu/drm/i915/display/intel_dp_hdcp.c+1−0

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drivers/gpu/drm/i915/display/intel_dp_link_training.c+36−47

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drivers/gpu/drm/i915/display/intel_dp_mst.c+39−66

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drivers/gpu/drm/i915/display/intel_dpio_phy.c+1−1

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drivers/gpu/drm/i915/display/intel_dpll.c+82−29

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drivers/gpu/drm/i915/display/intel_dpll_mgr.c+178−148

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drivers/gpu/drm/i915/display/intel_dsb.c+30−0

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drivers/gpu/drm/i915/display/intel_dsb.h+0−28

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drivers/gpu/drm/i915/display/intel_dsi.c+1−1

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drivers/gpu/drm/i915/display/intel_dsi.h+0−3

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drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c+8−6

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drivers/gpu/drm/i915/display/intel_dvo_dev.h+2−2

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drivers/gpu/drm/i915/display/intel_fb.c+9−9

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drivers/gpu/drm/i915/display/intel_fb_pin.c+2−2

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drivers/gpu/drm/i915/display/intel_fb_pin.h+2−2

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drivers/gpu/drm/i915/display/intel_fbc.c+12−6

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drivers/gpu/drm/i915/display/intel_fbc.h+1−0

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drivers/gpu/drm/i915/display/intel_fbdev.c+24−16

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drivers/gpu/drm/i915/display/intel_fdi.c+10−10

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drivers/gpu/drm/i915/display/intel_frontbuffer.c+29−27

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drivers/gpu/drm/i915/display/intel_frontbuffer.h+18−0

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drivers/gpu/drm/i915/display/intel_gmbus.c+153−137

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drivers/gpu/drm/i915/display/intel_gmbus.h+1−0

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drivers/gpu/drm/i915/display/intel_gmbus_regs.h+81−0

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drivers/gpu/drm/i915/display/intel_hdcp.c+93−70

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drivers/gpu/drm/i915/display/intel_hdcp_regs.h+270−0

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drivers/gpu/drm/i915/display/intel_hdmi.c+11−1

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drivers/gpu/drm/i915/display/intel_hotplug.c+58−58

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drivers/gpu/drm/i915/display/intel_lpe_audio.c+24−23

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drivers/gpu/drm/i915/display/intel_lvds.c+2−2

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drivers/gpu/drm/i915/display/intel_modeset_setup.c+8−7

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drivers/gpu/drm/i915/display/intel_modeset_verify.c+4−4

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drivers/gpu/drm/i915/display/intel_opregion.c+21−21

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drivers/gpu/drm/i915/display/intel_overlay.c+8−8

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drivers/gpu/drm/i915/display/intel_panel.c+24−21

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drivers/gpu/drm/i915/display/intel_panel.h+3−0

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drivers/gpu/drm/i915/display/intel_pch_refclk.c+13−3

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drivers/gpu/drm/i915/display/intel_pch_refclk.h+1−0

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drivers/gpu/drm/i915/display/intel_plane_initial.c+1−1

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