This patch intorduces new UAPI/IOCTL for usermode graphics queue. The userspace app will fill this structure and request the graphics driver to add a graphics work queue for it. The output of this UAPI is a queue id. This UAPI maps the queue into GPU, so the graphics app can start submitting work to the queue as soon as the call returns. V2: Addressed review comments from Alex and Christian - Make the doorbell offset's comment clearer - Change the output parameter name to queue_id V3: Integration with doorbell manager V4: - Updated the UAPI doc (Pierre-Eric) - Created a Union for engine specific MQDs (Alex) - Added Christian's R-B V5: - Add variables for GDS and CSA in MQD structure (Alex) - Make MQD data a ptr-size pair instead of union (Alex) V9: - renamed struct drm_amdgpu_userq_mqd_gfx_v11 to struct drm_amdgpu_userq_mqd as its being used for SDMA and compute queues as well V10: - keeping the drm_amdgpu_userq_mqd IP independent, moving the _gfx_v11 objects in a separate structure in other patch. (Alex)
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| @@ -54,6 +54,7 @@ extern "C" { · 53 unmodified lines | |||
| 54 | #define DRM_AMDGPU_VM 0x13 | 54 | #define DRM_AMDGPU_VM 0x13 |
| 55 | #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 | 55 | #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 |
| 56 | #define DRM_AMDGPU_SCHED 0x15 | 56 | #define DRM_AMDGPU_SCHED 0x15 |
| 57 | #define DRM_AMDGPU_USERQ 0x16 | ||
| 57 | 58 | ||
| 58 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | 59 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) |
| 59 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | 60 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) |
| @@ -71,6 +72,7 @@ extern "C" { · 11 unmodified lines | |||
| 71 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) | 72 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) |
| 72 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) | 73 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) |
| 73 | #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) | 74 | #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) |
| 75 | #define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) | ||
| 74 | 76 | ||
| 75 | /** | 77 | /** |
| 76 | * DOC: memory domains | 78 | * DOC: memory domains |
| @@ -319,6 +321,94 @@ union drm_amdgpu_ctx { · 242 unmodified lines | |||
| 319 | union drm_amdgpu_ctx_out out; | 321 | union drm_amdgpu_ctx_out out; |
| 320 | }; | 322 | }; |
| 321 | 323 | ||
| 324 | /* user queue IOCTL */ | ||
| 325 | #define AMDGPU_USERQ_OP_CREATE 1 | ||
| 326 | #define AMDGPU_USERQ_OP_FREE 2 | ||
| 327 | |||
| 328 | /* Flag to indicate secure buffer related workload, unused for now */ | ||
| 329 | #define AMDGPU_USERQ_MQD_FLAGS_SECURE (1 << 0) | ||
| 330 | /* Flag to indicate AQL workload, unused for now */ | ||
| 331 | #define AMDGPU_USERQ_MQD_FLAGS_AQL (1 << 1) | ||
| 332 | |||
| 333 | /* | ||
| 334 | * MQD (memory queue descriptor) is a set of parameters which allow | ||
| 335 | * the GPU to uniquely define and identify a usermode queue. This | ||
| 336 | * structure defines the MQD for GFX-V11 IP ver 0. | ||
| 337 | */ | ||
| 338 | struct drm_amdgpu_userq_in { | ||
| 339 | /** AMDGPU_USERQ_OP_* */ | ||
| 340 | __u32 op; | ||
| 341 | /** Queue handle for USERQ_OP_FREE */ | ||
| 342 | __u32 queue_id; | ||
| 343 | /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */ | ||
| 344 | __u32 ip_type; | ||
| 345 | /** | ||
| 346 | * @flags: flags to indicate special function for queue like secure | ||
| 347 | * buffer (TMZ). Unused for now. | ||
| 348 | */ | ||
| 349 | __u32 flags; | ||
| 350 | /** | ||
| 351 | * @doorbell_handle: the handle of doorbell GEM object | ||
| 352 | * associated to this client. | ||
| 353 | */ | ||
| 354 | __u32 doorbell_handle; | ||
| 355 | /** | ||
| 356 | * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo. | ||
| 357 | * Kernel will generate absolute doorbell offset using doorbell_handle | ||
| 358 | * and doorbell_offset in the doorbell bo. | ||
| 359 | */ | ||
| 360 | __u32 doorbell_offset; | ||
| 361 | |||
| 362 | /** | ||
| 363 | * @queue_va: Virtual address of the GPU memory which holds the queue | ||
| 364 | * object. The queue holds the workload packets. | ||
| 365 | */ | ||
| 366 | __u64 queue_va; | ||
| 367 | /** | ||
| 368 | * @queue_size: Size of the queue in bytes, this needs to be 256-byte | ||
| 369 | * aligned. | ||
| 370 | */ | ||
| 371 | __u64 queue_size; | ||
| 372 | /** | ||
| 373 | * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR. | ||
| 374 | * This object must be at least 8 byte in size and aligned to 8-byte offset. | ||
| 375 | */ | ||
| 376 | __u64 rptr_va; | ||
| 377 | /** | ||
| 378 | * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR. | ||
| 379 | * This object must be at least 8 byte in size and aligned to 8-byte offset. | ||
| 380 | * | ||
| 381 | * Queue, RPTR and WPTR can come from the same object, as long as the size | ||
| 382 | * and alignment related requirements are met. | ||
| 383 | */ | ||
| 384 | __u64 wptr_va; | ||
| 385 | /** | ||
| 386 | * @mqd: Queue descriptor for USERQ_OP_CREATE | ||
| 387 | * MQD data can be of different size for different GPU IP/engine and | ||
| 388 | * their respective versions/revisions, so this points to a __u64 * | ||
| 389 | * which holds MQD of this usermode queue. | ||
| 390 | */ | ||
| 391 | __u64 mqd; | ||
| 392 | /** | ||
| 393 | * @size: size of MQD data in bytes, it must match the MQD structure | ||
| 394 | * size of the respective engine/revision defined in UAPI for ex, for | ||
| 395 | * gfx_v11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx_v11). | ||
| 396 | */ | ||
| 397 | __u64 mqd_size; | ||
| 398 | }; | ||
| 399 | |||
| 400 | struct drm_amdgpu_userq_out { | ||
| 401 | /** Queue handle */ | ||
| 402 | __u32 queue_id; | ||
| 403 | /** Flags */ | ||
| 404 | __u32 flags; | ||
| 405 | }; | ||
| 406 | |||
| 407 | union drm_amdgpu_userq { | ||
| 408 | struct drm_amdgpu_userq_in in; | ||
| 409 | struct drm_amdgpu_userq_out out; | ||
| 410 | }; | ||
| 411 | |||
| 322 | /* vm ioctl */ | 412 | /* vm ioctl */ |
| 323 | #define AMDGPU_VM_OP_RESERVE_VMID 1 | 413 | #define AMDGPU_VM_OP_RESERVE_VMID 1 |
| 324 | #define AMDGPU_VM_OP_UNRESERVE_VMID 2 | 414 | #define AMDGPU_VM_OP_UNRESERVE_VMID 2 |