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riscv: dts: fu740: fix cache-controller interrupts

The order of interrupt numbers is incorrect. The order for FU740 is: DirError, DataError, DataFail, DirFail From SiFive FU740-C000 Manual: 19 - L2 Cache DirError 20 - L2 Cache DirFail 21 - L2 Cache DataError 22 - L2 Cache DataFail

David Abdurachmanov committed 5 years ago

Commit 7ede12b1 parent 3a027641 file · +1 −1Browse files

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arch/riscv/boot/dts/sifive/fu740-c000.dtsi+1−1
@@ -273,7 +273,7 @@ · 272 unmodified lines
273 cache-size = <2097152>;273 cache-size = <2097152>;
274 cache-unified;274 cache-unified;
275 interrupt-parent = <&plic0>;275 interrupt-parent = <&plic0>;
276 interrupts = <19 20 21 22>;276 interrupts = <19 21 22 20>;
277 reg = <0x0 0x2010000 0x0 0x1000>;277 reg = <0x0 0x2010000 0x0 0x1000>;
278 };278 };
279 gpio: gpio@10060000 {279 gpio: gpio@10060000 {

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