Add new netlink attribute to allow user space configuration of reference sync pin pairs, where both pins are used to provide one clock signal consisting of both: base frequency and sync signal.
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| @@ -249,6 +249,7 @@ enum dpll_a_pin { · 248 unmodified lines | |||
| 249 | DPLL_A_PIN_ESYNC_FREQUENCY, | 249 | DPLL_A_PIN_ESYNC_FREQUENCY, |
| 250 | DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED, | 250 | DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED, |
| 251 | DPLL_A_PIN_ESYNC_PULSE, | 251 | DPLL_A_PIN_ESYNC_PULSE, |
| 252 | DPLL_A_PIN_REFERENCE_SYNC, | ||
| 252 | 253 | ||
| 253 | __DPLL_A_PIN_MAX, | 254 | __DPLL_A_PIN_MAX, |
| 254 | DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1) | 255 | DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1) |