Reformat register field definitions in the style used elsewhere and align comments with names used in the spec. No functional change intended.
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| @@ -995,19 +995,19 @@ · 994 unmodified lines | |||
| 995 | #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ | 995 | #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ |
| 996 | #define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ | 996 | #define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ |
| 997 | 997 | ||
| 998 | /* L1 PM Substates */ | 998 | /* ASPM L1 PM Substates */ |
| 999 | #define PCI_L1SS_CAP 4 /* capability register */ | 999 | #define PCI_L1SS_CAP 0x04 /* Capabilities Register */ |
| 1000 | #define PCI_L1SS_CAP_PCIPM_L1_2 1 /* PCI PM L1.2 Support */ | 1000 | #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */ |
| 1001 | #define PCI_L1SS_CAP_PCIPM_L1_1 2 /* PCI PM L1.1 Support */ | 1001 | #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */ |
| 1002 | #define PCI_L1SS_CAP_ASPM_L1_2 4 /* ASPM L1.2 Support */ | 1002 | #define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */ |
| 1003 | #define PCI_L1SS_CAP_ASPM_L1_1 8 /* ASPM L1.1 Support */ | 1003 | #define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */ |
| 1004 | #define PCI_L1SS_CAP_L1_PM_SS 16 /* L1 PM Substates Support */ | 1004 | #define PCI_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */ |
| 1005 | #define PCI_L1SS_CTL1 8 /* Control Register 1 */ | 1005 | #define PCI_L1SS_CTL1 0x08 /* Control 1 Register */ |
| 1006 | #define PCI_L1SS_CTL1_PCIPM_L1_2 1 /* PCI PM L1.2 Enable */ | 1006 | #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */ |
| 1007 | #define PCI_L1SS_CTL1_PCIPM_L1_1 2 /* PCI PM L1.1 Support */ | 1007 | #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */ |
| 1008 | #define PCI_L1SS_CTL1_ASPM_L1_2 4 /* ASPM L1.2 Support */ | 1008 | #define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */ |
| 1009 | #define PCI_L1SS_CTL1_ASPM_L1_1 8 /* ASPM L1.1 Support */ | 1009 | #define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */ |
| 1010 | #define PCI_L1SS_CTL1_L1SS_MASK 0x0000000F | 1010 | #define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f |
| 1011 | #define PCI_L1SS_CTL2 0xC /* Control Register 2 */ | 1011 | #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ |
| 1012 | 1012 | ||
| 1013 | #endif /* LINUX_PCI_REGS_H */ | 1013 | #endif /* LINUX_PCI_REGS_H */ |