To make the code a bit more readable, let's move the OSI specific initialization out of the psci_dt_cpu_init_idle() and into a separate function.
Unified · Split
| @@ -160,6 +160,29 @@ int __init psci_dt_parse_state_node(struct device_node *np, u32 *state) · 159 unmodified lines | ||
| 160 | 160 | return 0; |
| 161 | 161 | } |
| 162 | 162 | |
| 163 | +static int __init psci_dt_cpu_init_topology(struct cpuidle_driver *drv, | |
| 164 | + struct psci_cpuidle_data *data, | |
| 165 | + unsigned int state_count, int cpu) | |
| 166 | +{ | |
| 167 | + /* Currently limit the hierarchical topology to be used in OSI mode. */ | |
| 168 | + if (!psci_has_osi_support()) | |
| 169 | + return 0; | |
| 170 | + | |
| 171 | + data->dev = psci_dt_attach_cpu(cpu); | |
| 172 | + if (IS_ERR_OR_NULL(data->dev)) | |
| 173 | + return PTR_ERR_OR_ZERO(data->dev); | |
| 174 | + | |
| 175 | + /* | |
| 176 | + * Using the deepest state for the CPU to trigger a potential selection | |
| 177 | + * of a shared state for the domain, assumes the domain states are all | |
| 178 | + * deeper states. | |
| 179 | + */ | |
| 180 | + drv->states[state_count - 1].enter = psci_enter_domain_idle_state; | |
| 181 | + psci_cpuidle_use_cpuhp = true; | |
| 182 | + | |
| 183 | + return 0; | |
| 184 | +} | |
| 185 | + | |
| 163 | 186 | static int __init psci_dt_cpu_init_idle(struct cpuidle_driver *drv, |
| 164 | 187 | struct device_node *cpu_node, |
| 165 | 188 | unsigned int state_count, int cpu) |
| @@ -193,25 +216,10 @@ static int __init psci_dt_cpu_init_idle(struct cpuidle_driver *drv, · 27 unmodified lines | ||
| 193 | 216 | goto free_mem; |
| 194 | 217 | } |
| 195 | 218 | |
| 196 | − /* Currently limit the hierarchical topology to be used in OSI mode. */ | |
| 197 | − if (psci_has_osi_support()) { | |
| 198 | − data->dev = psci_dt_attach_cpu(cpu); | |
| 199 | − if (IS_ERR(data->dev)) { | |
| 200 | − ret = PTR_ERR(data->dev); | |
| 201 | − goto free_mem; | |
| 202 | − } | |
| 203 | − | |
| 204 | − /* | |
| 205 | − * Using the deepest state for the CPU to trigger a potential | |
| 206 | − * selection of a shared state for the domain, assumes the | |
| 207 | − * domain states are all deeper states. | |
| 208 | − */ | |
| 209 | − if (data->dev) { | |
| 210 | − drv->states[state_count - 1].enter = | |
| 211 | − psci_enter_domain_idle_state; | |
| 212 | − psci_cpuidle_use_cpuhp = true; | |
| 213 | − } | |
| 214 | − } | |
| 219 | + /* Initialize optional data, used for the hierarchical topology. */ | |
| 220 | + ret = psci_dt_cpu_init_topology(drv, data, state_count, cpu); | |
| 221 | + if (ret < 0) | |
| 222 | + goto free_mem; | |
| 215 | 223 | |
| 216 | 224 | /* Idle states parsed correctly, store them in the per-cpu struct. */ |
| 217 | 225 | data->psci_states = psci_states; |