History

Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

This series provides some low level updates for mlx5 driver needed for both rdma and netdev trees. 1) Termination flow steering table bits and hardware definitions. 2) Introduce the core dump HW access registers definitions. 3) Refactor and cleans-up VF representors functions handlers. 4) Renames host_params bits to function_changed bits and add the support for eswitch functions change event in the eswitch general case. (for both legacy and switchdev modes). 5) Potential error pointer dereference in error handling

Saeed Mahameed committed 7 years ago

Commit 7fe4d432 parents b4b12b0 869311519 files · +179 −126Browse files

Showing the changes to include/linux (5 of 19 files). Show all

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5 files
  1. include/linux/mlx5/device.h +1 −1
  2. include/linux/mlx5/driver.h +1 −0
  3. include/linux/mlx5/eswitch.h +11 −9
  4. include/linux/mlx5/fs.h +1 −0
  5. include/linux/mlx5/mlx5_ifc.h +26 −7
include/linux/mlx5/device.h+1−1
@@ -342,7 +342,7 @@ enum mlx5_event { · 341 unmodified lines
342 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,342 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
343 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,343 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
344 344
345 MLX5_EVENT_TYPE_HOST_PARAMS_CHANGE = 0xe,345 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
346 346
347 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,347 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
348 348
include/linux/mlx5/driver.h+1−0
@@ -107,6 +107,7 @@ enum { · 106 unmodified lines
107 MLX5_REG_FPGA_CAP = 0x4022,107 MLX5_REG_FPGA_CAP = 0x4022,
108 MLX5_REG_FPGA_CTRL = 0x4023,108 MLX5_REG_FPGA_CTRL = 0x4023,
109 MLX5_REG_FPGA_ACCESS_REG = 0x4024,109 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
110 MLX5_REG_CORE_DUMP = 0x402e,
110 MLX5_REG_PCAP = 0x5001,111 MLX5_REG_PCAP = 0x5001,
111 MLX5_REG_PMTU = 0x5003,112 MLX5_REG_PMTU = 0x5003,
112 MLX5_REG_PTYS = 0x5004,113 MLX5_REG_PTYS = 0x5004,
include/linux/mlx5/eswitch.h+11−9
@@ -29,17 +29,19 @@ enum { · 28 unmodified lines
29};29};
30 30
31struct mlx5_eswitch_rep;31struct mlx5_eswitch_rep;
32struct mlx5_eswitch_rep_if {32struct mlx5_eswitch_rep_ops {
33 int (*load)(struct mlx5_core_dev *dev,33 int (*load)(struct mlx5_core_dev *dev, struct mlx5_eswitch_rep *rep);
34 struct mlx5_eswitch_rep *rep);34 void (*unload)(struct mlx5_eswitch_rep *rep);
35 void (*unload)(struct mlx5_eswitch_rep *rep);35 void *(*get_proto_dev)(struct mlx5_eswitch_rep *rep);
36 void *(*get_proto_dev)(struct mlx5_eswitch_rep *rep);36};
37 void *priv;37
38 atomic_t state;38struct mlx5_eswitch_rep_data {
39 void *priv;
40 atomic_t state;
39};41};
40 42
41struct mlx5_eswitch_rep {43struct mlx5_eswitch_rep {
42 struct mlx5_eswitch_rep_if rep_if[NUM_REP_TYPES];44 struct mlx5_eswitch_rep_data rep_data[NUM_REP_TYPES];
43 u16 vport;45 u16 vport;
44 u8 hw_id[ETH_ALEN];46 u8 hw_id[ETH_ALEN];
45 u16 vlan;47 u16 vlan;
@@ -47,7 +49,7 @@ struct mlx5_eswitch_rep { · 1 unmodified line
47};49};
48 50
49void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,51void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
50 struct mlx5_eswitch_rep_if *rep_if,52 const struct mlx5_eswitch_rep_ops *ops,
51 u8 rep_type);53 u8 rep_type);
52void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type);54void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type);
53void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,55void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
include/linux/mlx5/fs.h+1−0
@@ -47,6 +47,7 @@ enum { · 46 unmodified lines
47enum {47enum {
48 MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT = BIT(0),48 MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT = BIT(0),
49 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1),49 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP = BIT(1),
50 MLX5_FLOW_TABLE_TERMINATION = BIT(2),
50};51};
51 52
52#define LEFTOVERS_RULE_NUM 253#define LEFTOVERS_RULE_NUM 2
include/linux/mlx5/mlx5_ifc.h+26−7
@@ -155,7 +155,7 @@ enum { · 154 unmodified lines
155 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,155 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
156 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,156 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
157 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,157 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
158 MLX5_CMD_OP_QUERY_HOST_PARAMS = 0x740,158 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
159 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,159 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
160 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,160 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
161 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,161 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
@@ -382,7 +382,8 @@ struct mlx5_ifc_flow_table_prop_layout_bits { · 220 unmodified lines
382 u8 reformat_and_modify_action[0x1];382 u8 reformat_and_modify_action[0x1];
383 u8 reserved_at_15[0x2];383 u8 reserved_at_15[0x2];
384 u8 table_miss_action_domain[0x1];384 u8 table_miss_action_domain[0x1];
385 u8 reserved_at_18[0x8];385 u8 termination_table[0x1];
386 u8 reserved_at_19[0x7];
386 u8 reserved_at_20[0x2];387 u8 reserved_at_20[0x2];
387 u8 log_max_ft_size[0x6];388 u8 log_max_ft_size[0x6];
388 u8 log_max_modify_header_context[0x8];389 u8 log_max_modify_header_context[0x8];
@@ -664,7 +665,9 @@ struct mlx5_ifc_e_switch_cap_bits { · 275 unmodified lines
664 u8 vport_svlan_insert[0x1];665 u8 vport_svlan_insert[0x1];
665 u8 vport_cvlan_insert_if_not_exist[0x1];666 u8 vport_cvlan_insert_if_not_exist[0x1];
666 u8 vport_cvlan_insert_overwrite[0x1];667 u8 vport_cvlan_insert_overwrite[0x1];
667 u8 reserved_at_5[0x16];668 u8 reserved_at_5[0x14];
669 u8 esw_functions_changed[0x1];
670 u8 reserved_at_1a[0x1];
668 u8 ecpf_vport_exists[0x1];671 u8 ecpf_vport_exists[0x1];
669 u8 counter_eswitch_affinity[0x1];672 u8 counter_eswitch_affinity[0x1];
670 u8 merged_eswitch[0x1];673 u8 merged_eswitch[0x1];
@@ -715,7 +718,9 @@ struct mlx5_ifc_qos_cap_bits { · 44 unmodified lines
715};718};
716 719
717struct mlx5_ifc_debug_cap_bits {720struct mlx5_ifc_debug_cap_bits {
718 u8 reserved_at_0[0x20];721 u8 core_dump_general[0x1];
722 u8 core_dump_qp[0x1];
723 u8 reserved_at_2[0x1e];
719 724
720 u8 reserved_at_20[0x2];725 u8 reserved_at_20[0x2];
721 u8 stall_detect[0x1];726 u8 stall_detect[0x1];
@@ -2531,6 +2536,7 @@ union mlx5_ifc_hca_cap_union_bits { · 1809 unmodified lines
2531 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;2536 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2532 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;2537 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2533 struct mlx5_ifc_qos_cap_bits qos_cap;2538 struct mlx5_ifc_qos_cap_bits qos_cap;
2539 struct mlx5_ifc_debug_cap_bits debug_cap;
2534 struct mlx5_ifc_fpga_cap_bits fpga_cap;2540 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2535 u8 reserved_at_0[0x8000];2541 u8 reserved_at_0[0x8000];
2536};2542};
@@ -7236,7 +7242,8 @@ struct mlx5_ifc_create_flow_table_out_bits { · 4699 unmodified lines
7236struct mlx5_ifc_flow_table_context_bits {7242struct mlx5_ifc_flow_table_context_bits {
7237 u8 reformat_en[0x1];7243 u8 reformat_en[0x1];
7238 u8 decap_en[0x1];7244 u8 decap_en[0x1];
7239 u8 reserved_at_2[0x2];7245 u8 reserved_at_2[0x1];
7246 u8 termination_table[0x1];
7240 u8 table_miss_action[0x4];7247 u8 table_miss_action[0x4];
7241 u8 level[0x8];7248 u8 level[0x8];
7242 u8 reserved_at_10[0x8];7249 u8 reserved_at_10[0x8];
@@ -8546,6 +8553,18 @@ struct mlx5_ifc_qcam_reg_bits { · 1303 unmodified lines
8546 u8 reserved_at_1c0[0x80];8553 u8 reserved_at_1c0[0x80];
8547};8554};
8548 8555
8556struct mlx5_ifc_core_dump_reg_bits {
8557 u8 reserved_at_0[0x18];
8558 u8 core_dump_type[0x8];
8559
8560 u8 reserved_at_20[0x30];
8561 u8 vhca_id[0x10];
8562
8563 u8 reserved_at_60[0x8];
8564 u8 qpn[0x18];
8565 u8 reserved_at_80[0x180];
8566};
8567
8549struct mlx5_ifc_pcap_reg_bits {8568struct mlx5_ifc_pcap_reg_bits {
8550 u8 reserved_at_0[0x8];8569 u8 reserved_at_0[0x8];
8551 u8 local_port[0x8];8570 u8 local_port[0x8];
@@ -9704,7 +9723,7 @@ struct mlx5_ifc_host_params_context_bits { · 1152 unmodified lines
9704 u8 reserved_at_80[0x180];9723 u8 reserved_at_80[0x180];
9705};9724};
9706 9725
9707struct mlx5_ifc_query_host_params_in_bits {9726struct mlx5_ifc_query_esw_functions_in_bits {
9708 u8 opcode[0x10];9727 u8 opcode[0x10];
9709 u8 reserved_at_10[0x10];9728 u8 reserved_at_10[0x10];
9710 9729
@@ -9714,7 +9733,7 @@ struct mlx5_ifc_query_host_params_in_bits { · 3 unmodified lines
9714 u8 reserved_at_40[0x40];9733 u8 reserved_at_40[0x40];
9715};9734};
9716 9735
9717struct mlx5_ifc_query_host_params_out_bits {9736struct mlx5_ifc_query_esw_functions_out_bits {
9718 u8 status[0x8];9737 u8 status[0x8];
9719 u8 reserved_at_8[0x18];9738 u8 reserved_at_8[0x18];
9720 9739

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