History

Merge tag 'mips_6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer: "Cleanups and fixes" * tag 'mips_6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: pci-legacy: Override pci_address_to_pio MIPS: Loongson64: env: Use str_on_off() helper in prom_lefi_init_env() MIPS: migrate to generic rule for built-in DTBs mips: fix shmctl/semctl/msgctl syscall for o32 mips/math-emu: fix emulation of the prefx instruction MIPS: Loongson: Add comments for interface_info MIPS: Loongson64: remove ROM Size unit in boardinfo MIPS: traps: Use str_enabled_disabled() in parity_protection_init() MIPS: ftrace: Declare ftrace_get_parent_ra_addr() as static Revert "MIPS: csrc-r4k: Select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT" MIPS: Fix the wrong format specifier MIPS: Add a blank line after __HEAD MIPS: kernel: Rename read/write_c0_ecc to read/writec0_errctl

Linus Torvalds committed 1 year ago

Commit 805ba042 parents 816cef9 df1b8d625 files · +52 −71Browse files

Unified · Split

25 files
  1. arch/mips/Kconfig +2 −1
  2. arch/mips/Makefile +0 −3
  3. arch/mips/boot/dts/Makefile +0 −2
  4. arch/mips/boot/dts/brcm/Makefile +0 −2
  5. arch/mips/boot/dts/cavium-octeon/Makefile +0 −2
  6. arch/mips/boot/dts/ingenic/Makefile +0 −2
  7. arch/mips/boot/dts/lantiq/Makefile +0 −2
  8. arch/mips/boot/dts/loongson/Makefile +0 −2
  9. arch/mips/boot/dts/mscc/Makefile +0 −3
  10. arch/mips/boot/dts/mti/Makefile +0 −2
  11. arch/mips/boot/dts/pic32/Makefile +0 −2
  12. arch/mips/boot/dts/ralink/Makefile +0 −2
  13. arch/mips/include/asm/mach-loongson64/boot_param.h +4 −4
  14. arch/mips/include/asm/mipsregs.h +2 −2
  15. arch/mips/kernel/cevt-bcm1480.c +1 −1
  16. arch/mips/kernel/ftrace.c +1 −1
  17. arch/mips/kernel/head.S +1 −0
  18. arch/mips/kernel/mips-mt.c +3 −4
  19. arch/mips/kernel/spram.c +0 −4
  20. arch/mips/kernel/syscalls/syscall_o32.tbl +3 −3
  21. arch/mips/kernel/traps.c +24 −23
  22. arch/mips/loongson64/boardinfo.c +0 −2
  23. arch/mips/loongson64/env.c +2 −1
  24. arch/mips/math-emu/cp1emu.c +1 −1
  25. arch/mips/pci/pci-legacy.c +8 −0
arch/mips/Kconfig+2−1
@@ -29,10 +29,12 @@ config MIPS · 28 unmodified lines
29 select ARCH_WANT_IPC_PARSE_VERSION29 select ARCH_WANT_IPC_PARSE_VERSION
30 select ARCH_WANT_LD_ORPHAN_WARN30 select ARCH_WANT_LD_ORPHAN_WARN
31 select BUILDTIME_TABLE_SORT31 select BUILDTIME_TABLE_SORT
32 select BUILTIN_DTB_ALL if BUILTIN_DTB
32 select CLONE_BACKWARDS33 select CLONE_BACKWARDS
33 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)34 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
34 select CPU_PM if CPU_IDLE || SUSPEND35 select CPU_PM if CPU_IDLE || SUSPEND
35 select GENERIC_ATOMIC64 if !64BIT36 select GENERIC_ATOMIC64 if !64BIT
37 select GENERIC_BUILTIN_DTB if BUILTIN_DTB
36 select GENERIC_CMOS_UPDATE38 select GENERIC_CMOS_UPDATE
37 select GENERIC_CPU_AUTOPROBE39 select GENERIC_CPU_AUTOPROBE
38 select GENERIC_GETTIMEOFDAY40 select GENERIC_GETTIMEOFDAY
@@ -1084,7 +1086,6 @@ config CSRC_IOASIC · 1045 unmodified lines
1084 1086
1085config CSRC_R4K1087config CSRC_R4K
1086 select CLOCKSOURCE_WATCHDOG if CPU_FREQ1088 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
1087 select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT
1088 bool1089 bool
1089 1090
1090config CSRC_SB12501091config CSRC_SB1250
arch/mips/Makefile+0−3
@@ -423,9 +423,6 @@ endif · 422 unmodified lines
423 423
424CLEAN_FILES += vmlinux.32 vmlinux.64424CLEAN_FILES += vmlinux.32 vmlinux.64
425 425
426# device-trees
427core-y += arch/mips/boot/dts/
428
429archprepare:426archprepare:
430ifdef CONFIG_MIPS32_N32427ifdef CONFIG_MIPS32_N32
431 @$(kecho) ' Checking missing-syscalls for N32'428 @$(kecho) ' Checking missing-syscalls for N32'
arch/mips/boot/dts/Makefile+0−2
@@ -16,5 +16,3 @@ subdir-$(CONFIG_ATH79) += qca · 15 unmodified lines
16subdir-$(CONFIG_RALINK) += ralink16subdir-$(CONFIG_RALINK) += ralink
17subdir-$(CONFIG_MACH_REALTEK_RTL) += realtek17subdir-$(CONFIG_MACH_REALTEK_RTL) += realtek
18subdir-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += xilfpga18subdir-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += xilfpga
19
20obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
arch/mips/boot/dts/brcm/Makefile+0−2
@@ -33,5 +33,3 @@ dtb-$(CONFIG_DT_NONE) += \ · 32 unmodified lines
33 bcm97420c.dtb \33 bcm97420c.dtb \
34 bcm97425svmb.dtb \34 bcm97425svmb.dtb \
35 bcm97435svmb.dtb35 bcm97435svmb.dtb
36
37obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
arch/mips/boot/dts/cavium-octeon/Makefile+0−2
@@ -1,4 +1,2 @@
1# SPDX-License-Identifier: GPL-2.01# SPDX-License-Identifier: GPL-2.0
2dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb2dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb
3
4obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
arch/mips/boot/dts/ingenic/Makefile+0−2
@@ -5,5 +5,3 @@ dtb-$(CONFIG_JZ4770_GCW0) += gcw0.dtb · 4 unmodified lines
5dtb-$(CONFIG_JZ4780_CI20) += ci20.dtb5dtb-$(CONFIG_JZ4780_CI20) += ci20.dtb
6dtb-$(CONFIG_X1000_CU1000_NEO) += cu1000-neo.dtb6dtb-$(CONFIG_X1000_CU1000_NEO) += cu1000-neo.dtb
7dtb-$(CONFIG_X1830_CU1830_NEO) += cu1830-neo.dtb7dtb-$(CONFIG_X1830_CU1830_NEO) += cu1830-neo.dtb
8
9obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
arch/mips/boot/dts/lantiq/Makefile+0−2
@@ -1,4 +1,2 @@
1# SPDX-License-Identifier: GPL-2.01# SPDX-License-Identifier: GPL-2.0
2dtb-$(CONFIG_DT_EASY50712) += danube_easy50712.dtb2dtb-$(CONFIG_DT_EASY50712) += danube_easy50712.dtb
3
4obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
arch/mips/boot/dts/loongson/Makefile+0−2
@@ -5,5 +5,3 @@ dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb · 4 unmodified lines
5dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb5dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
6dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb6dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
7dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb7dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb
8
9obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
arch/mips/boot/dts/mscc/Makefile+0−3
@@ -8,6 +8,3 @@ dtb-$(CONFIG_SOC_VCOREIII) += \ · 7 unmodified lines
8 ocelot_pcb123.dtb \8 ocelot_pcb123.dtb \
9 serval_pcb105.dtb \9 serval_pcb105.dtb \
10 serval_pcb106.dtb10 serval_pcb106.dtb
11
12
13obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
arch/mips/boot/dts/mti/Makefile+0−2
@@ -1,5 +1,3 @@
1# SPDX-License-Identifier: GPL-2.01# SPDX-License-Identifier: GPL-2.0
2dtb-$(CONFIG_MIPS_MALTA) += malta.dtb2dtb-$(CONFIG_MIPS_MALTA) += malta.dtb
3dtb-$(CONFIG_LEGACY_BOARD_SEAD3) += sead3.dtb3dtb-$(CONFIG_LEGACY_BOARD_SEAD3) += sead3.dtb
4
5obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
arch/mips/boot/dts/pic32/Makefile+0−2
@@ -3,5 +3,3 @@ dtb-$(CONFIG_DTB_PIC32_MZDA_SK) += pic32mzda_sk.dtb · 2 unmodified lines
3 3
4dtb-$(CONFIG_DTB_PIC32_NONE) += \4dtb-$(CONFIG_DTB_PIC32_NONE) += \
5 pic32mzda_sk.dtb5 pic32mzda_sk.dtb
6
7obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
arch/mips/boot/dts/ralink/Makefile+0−2
@@ -10,5 +10,3 @@ dtb-$(CONFIG_SOC_MT7621) += \ · 9 unmodified lines
10 mt7621-gnubee-gb-pc1.dtb \10 mt7621-gnubee-gb-pc1.dtb \
11 mt7621-gnubee-gb-pc2.dtb \11 mt7621-gnubee-gb-pc2.dtb \
12 mt7621-tplink-hc220-g5-v1.dtb12 mt7621-tplink-hc220-g5-v1.dtb
13
14obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
arch/mips/include/asm/mach-loongson64/boot_param.h+4−4
@@ -128,10 +128,10 @@ struct irq_source_routing_table { · 127 unmodified lines
128} __packed;128} __packed;
129 129
130struct interface_info {130struct interface_info {
131 u16 vers; /* version of the specificition */131 u16 vers; /* version of the specification */
132 u16 size;132 u16 size; /* size of this interface */
133 u8 flag;133 u8 flag; /* used or unused */
134 char description[64];134 char description[64]; /* description for each change */
135} __packed;135} __packed;
136 136
137#define MAX_RESOURCE_NUMBER 128137#define MAX_RESOURCE_NUMBER 128
arch/mips/include/asm/mipsregs.h+2−2
@@ -2039,8 +2039,8 @@ do { \ · 2038 unmodified lines
2039#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)2039#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
2040#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)2040#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
2041 2041
2042#define read_c0_ecc() __read_32bit_c0_register($26, 0)2042#define read_c0_errctl() __read_32bit_c0_register($26, 0)
2043#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)2043#define write_c0_errctl(val) __write_32bit_c0_register($26, 0, val)
2044 2044
2045#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)2045#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
2046#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)2046#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
arch/mips/kernel/cevt-bcm1480.c+1−1
@@ -103,7 +103,7 @@ void sb1480_clockevent_init(void) · 102 unmodified lines
103 103
104 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */104 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
105 105
106 sprintf(name, "bcm1480-counter-%d", cpu);106 sprintf(name, "bcm1480-counter-%u", cpu);
107 cd->name = name;107 cd->name = name;
108 cd->features = CLOCK_EVT_FEAT_PERIODIC |108 cd->features = CLOCK_EVT_FEAT_PERIODIC |
109 CLOCK_EVT_FEAT_ONESHOT;109 CLOCK_EVT_FEAT_ONESHOT;
arch/mips/kernel/ftrace.c+1−1
@@ -248,7 +248,7 @@ int ftrace_disable_ftrace_graph_caller(void) · 247 unmodified lines
248#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */248#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */
249#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */249#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */
250 250
251unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long251static unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long
252 old_parent_ra, unsigned long parent_ra_addr, unsigned long fp)252 old_parent_ra, unsigned long parent_ra_addr, unsigned long fp)
253{253{
254 unsigned long sp, ip, tmp;254 unsigned long sp, ip, tmp;
arch/mips/kernel/head.S+1−0
@@ -60,6 +60,7 @@ · 59 unmodified lines
60 .endm60 .endm
61 61
62 __HEAD62 __HEAD
63
63#ifndef CONFIG_NO_EXCEPT_FILL64#ifndef CONFIG_NO_EXCEPT_FILL
64 /*65 /*
65 * Reserved space for exception handlers.66 * Reserved space for exception handlers.
arch/mips/kernel/mips-mt.c+3−4
@@ -122,9 +122,8 @@ void mips_mt_set_cpuoptions(void) · 121 unmodified lines
122 unsigned long ectlval;122 unsigned long ectlval;
123 unsigned long itcblkgrn;123 unsigned long itcblkgrn;
124 124
125 /* ErrCtl register is known as "ecc" to Linux */125 ectlval = read_c0_errctl();
126 ectlval = read_c0_ecc();126 write_c0_errctl(ectlval | (0x1 << 26));
127 write_c0_ecc(ectlval | (0x1 << 26));
128 ehb();127 ehb();
129#define INDEX_0 (0x80000000)128#define INDEX_0 (0x80000000)
130#define INDEX_8 (0x80000008)129#define INDEX_8 (0x80000008)
@@ -145,7 +144,7 @@ void mips_mt_set_cpuoptions(void) · 14 unmodified lines
145 ehb();144 ehb();
146 /* Write out to ITU with CACHE op */145 /* Write out to ITU with CACHE op */
147 cache_op(Index_Store_Tag_D, INDEX_0);146 cache_op(Index_Store_Tag_D, INDEX_0);
148 write_c0_ecc(ectlval);147 write_c0_errctl(ectlval);
149 ehb();148 ehb();
150 printk("Mapped %ld ITC cells starting at 0x%08x\n",149 printk("Mapped %ld ITC cells starting at 0x%08x\n",
151 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);150 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
arch/mips/kernel/spram.c+0−4
@@ -26,10 +26,6 @@ · 25 unmodified lines
26 26
27#define ERRCTL_SPRAM (1 << 28)27#define ERRCTL_SPRAM (1 << 28)
28 28
29/* errctl access */
30#define read_c0_errctl(x) read_c0_ecc(x)
31#define write_c0_errctl(x) write_c0_ecc(x)
32
33/*29/*
34 * Different semantics to the set_c0_* function built by __BUILD_SET_C030 * Different semantics to the set_c0_* function built by __BUILD_SET_C0
35 */31 */
arch/mips/kernel/syscalls/syscall_o32.tbl+3−3
@@ -382,15 +382,15 @@ · 381 unmodified lines
382368 o32 io_pgetevents sys_io_pgetevents_time32 compat_sys_io_pgetevents382368 o32 io_pgetevents sys_io_pgetevents_time32 compat_sys_io_pgetevents
383# room for arch specific calls383# room for arch specific calls
384393 o32 semget sys_semget384393 o32 semget sys_semget
385394 o32 semctl sys_semctl compat_sys_semctl385394 o32 semctl sys_old_semctl compat_sys_old_semctl
386395 o32 shmget sys_shmget386395 o32 shmget sys_shmget
387396 o32 shmctl sys_shmctl compat_sys_shmctl387396 o32 shmctl sys_old_shmctl compat_sys_old_shmctl
388397 o32 shmat sys_shmat compat_sys_shmat388397 o32 shmat sys_shmat compat_sys_shmat
389398 o32 shmdt sys_shmdt389398 o32 shmdt sys_shmdt
390399 o32 msgget sys_msgget390399 o32 msgget sys_msgget
391400 o32 msgsnd sys_msgsnd compat_sys_msgsnd391400 o32 msgsnd sys_msgsnd compat_sys_msgsnd
392401 o32 msgrcv sys_msgrcv compat_sys_msgrcv392401 o32 msgrcv sys_msgrcv compat_sys_msgrcv
393402 o32 msgctl sys_msgctl compat_sys_msgctl393402 o32 msgctl sys_old_msgctl compat_sys_old_msgctl
394403 o32 clock_gettime64 sys_clock_gettime sys_clock_gettime394403 o32 clock_gettime64 sys_clock_gettime sys_clock_gettime
395404 o32 clock_settime64 sys_clock_settime sys_clock_settime395404 o32 clock_settime64 sys_clock_settime sys_clock_settime
396405 o32 clock_adjtime64 sys_clock_adjtime sys_clock_adjtime396405 o32 clock_adjtime64 sys_clock_adjtime sys_clock_adjtime
arch/mips/kernel/traps.c+24−23
@@ -38,6 +38,7 @@ · 37 unmodified lines
38#include <linux/kdb.h>38#include <linux/kdb.h>
39#include <linux/irq.h>39#include <linux/irq.h>
40#include <linux/perf_event.h>40#include <linux/perf_event.h>
41#include <linux/string_choices.h>
41 42
42#include <asm/addrspace.h>43#include <asm/addrspace.h>
43#include <asm/bootinfo.h>44#include <asm/bootinfo.h>
@@ -1705,10 +1706,10 @@ static inline __init void parity_protection_init(void) · 1661 unmodified lines
1705 l2parity &= l1parity;1706 l2parity &= l1parity;
1706 1707
1707 /* Probe L1 ECC support */1708 /* Probe L1 ECC support */
1708 cp0_ectl = read_c0_ecc();1709 cp0_ectl = read_c0_errctl();
1709 write_c0_ecc(cp0_ectl | ERRCTL_PE);1710 write_c0_errctl(cp0_ectl | ERRCTL_PE);
1710 back_to_back_c0_hazard();1711 back_to_back_c0_hazard();
1711 cp0_ectl = read_c0_ecc();1712 cp0_ectl = read_c0_errctl();
1712 1713
1713 /* Probe L2 ECC support */1714 /* Probe L2 ECC support */
1714 gcr_ectl = read_gcr_err_control();1715 gcr_ectl = read_gcr_err_control();
@@ -1727,9 +1728,9 @@ static inline __init void parity_protection_init(void) · 12 unmodified lines
1727 cp0_ectl |= ERRCTL_PE;1728 cp0_ectl |= ERRCTL_PE;
1728 else1729 else
1729 cp0_ectl &= ~ERRCTL_PE;1730 cp0_ectl &= ~ERRCTL_PE;
1730 write_c0_ecc(cp0_ectl);1731 write_c0_errctl(cp0_ectl);
1731 back_to_back_c0_hazard();1732 back_to_back_c0_hazard();
1732 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);1733 WARN_ON(!!(read_c0_errctl() & ERRCTL_PE) != l1parity);
1733 1734
1734 /* Configure L2 ECC checking */1735 /* Configure L2 ECC checking */
1735 if (l2parity)1736 if (l2parity)
@@ -1741,8 +1742,8 @@ static inline __init void parity_protection_init(void) · 5 unmodified lines
1741 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;1742 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1742 WARN_ON(!!gcr_ectl != l2parity);1743 WARN_ON(!!gcr_ectl != l2parity);
1743 1744
1744 pr_info("Cache parity protection %sabled\n",1745 pr_info("Cache parity protection %s\n",
1745 l1parity ? "en" : "dis");1746 str_enabled_disabled(l1parity));
1746 return;1747 return;
1747 }1748 }
1748 1749
@@ -1761,18 +1762,18 @@ static inline __init void parity_protection_init(void) · 12 unmodified lines
1761 unsigned long errctl;1762 unsigned long errctl;
1762 unsigned int l1parity_present, l2parity_present;1763 unsigned int l1parity_present, l2parity_present;
1763 1764
1764 errctl = read_c0_ecc();1765 errctl = read_c0_errctl();
1765 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);1766 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1766 1767
1767 /* probe L1 parity support */1768 /* probe L1 parity support */
1768 write_c0_ecc(errctl | ERRCTL_PE);1769 write_c0_errctl(errctl | ERRCTL_PE);
1769 back_to_back_c0_hazard();1770 back_to_back_c0_hazard();
1770 l1parity_present = (read_c0_ecc() & ERRCTL_PE);1771 l1parity_present = (read_c0_errctl() & ERRCTL_PE);
1771 1772
1772 /* probe L2 parity support */1773 /* probe L2 parity support */
1773 write_c0_ecc(errctl|ERRCTL_L2P);1774 write_c0_errctl(errctl|ERRCTL_L2P);
1774 back_to_back_c0_hazard();1775 back_to_back_c0_hazard();
1775 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);1776 l2parity_present = (read_c0_errctl() & ERRCTL_L2P);
1776 1777
1777 if (l1parity_present && l2parity_present) {1778 if (l1parity_present && l2parity_present) {
1778 if (l1parity)1779 if (l1parity)
@@ -1791,20 +1792,20 @@ static inline __init void parity_protection_init(void) · 12 unmodified lines
1791 1792
1792 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);1793 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1793 1794
1794 write_c0_ecc(errctl);1795 write_c0_errctl(errctl);
1795 back_to_back_c0_hazard();1796 back_to_back_c0_hazard();
1796 errctl = read_c0_ecc();1797 errctl = read_c0_errctl();
1797 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);1798 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1798 1799
1799 if (l1parity_present)1800 if (l1parity_present)
1800 printk(KERN_INFO "Cache parity protection %sabled\n",1801 pr_info("Cache parity protection %s\n",
1801 (errctl & ERRCTL_PE) ? "en" : "dis");1802 str_enabled_disabled(errctl & ERRCTL_PE));
1802 1803
1803 if (l2parity_present) {1804 if (l2parity_present) {
1804 if (l1parity_present && l1parity)1805 if (l1parity_present && l1parity)
1805 errctl ^= ERRCTL_L2P;1806 errctl ^= ERRCTL_L2P;
1806 printk(KERN_INFO "L2 cache parity protection %sabled\n",1807 pr_info("L2 cache parity protection %s\n",
1807 (errctl & ERRCTL_L2P) ? "en" : "dis");1808 str_enabled_disabled(errctl & ERRCTL_L2P));
1808 }1809 }
1809 }1810 }
1810 break;1811 break;
@@ -1812,11 +1813,11 @@ static inline __init void parity_protection_init(void) · 1 unmodified line
1812 case CPU_5KC:1813 case CPU_5KC:
1813 case CPU_5KE:1814 case CPU_5KE:
1814 case CPU_LOONGSON32:1815 case CPU_LOONGSON32:
1815 write_c0_ecc(0x80000000);1816 write_c0_errctl(0x80000000);
1816 back_to_back_c0_hazard();1817 back_to_back_c0_hazard();
1817 /* Set the PE bit (bit 31) in the c0_errctl register. */1818 /* Set the PE bit (bit 31) in the c0_errctl register. */
1818 printk(KERN_INFO "Cache parity protection %sabled\n",1819 pr_info("Cache parity protection %s\n",
1819 (read_c0_ecc() & 0x80000000) ? "en" : "dis");1820 str_enabled_disabled(read_c0_errctl() & 0x80000000));
1820 break;1821 break;
1821 case CPU_20KC:1822 case CPU_20KC:
1822 case CPU_25KF:1823 case CPU_25KF:
@@ -1887,8 +1888,8 @@ asmlinkage void do_ftlb(void) · 64 unmodified lines
1887 if ((cpu_has_mips_r2_r6) &&1888 if ((cpu_has_mips_r2_r6) &&
1888 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||1889 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1889 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {1890 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1890 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",1891 pr_err("FTLB error exception, cp0_errctl=0x%08x:\n",
1891 read_c0_ecc());1892 read_c0_errctl());
1892 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());1893 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1893 reg_val = read_c0_cacheerr();1894 reg_val = read_c0_cacheerr();
1894 pr_err("c0_cacheerr == %08x\n", reg_val);1895 pr_err("c0_cacheerr == %08x\n", reg_val);
arch/mips/loongson64/boardinfo.c+0−2
@@ -21,13 +21,11 @@ static ssize_t boardinfo_show(struct kobject *kobj, · 20 unmodified lines
21 "BIOS Info\n"21 "BIOS Info\n"
22 "Vendor\t\t\t: %s\n"22 "Vendor\t\t\t: %s\n"
23 "Version\t\t\t: %s\n"23 "Version\t\t\t: %s\n"
24 "ROM Size\t\t: %d KB\n"
25 "Release Date\t\t: %s\n",24 "Release Date\t\t: %s\n",
26 strsep(&tmp_board_manufacturer, "-"),25 strsep(&tmp_board_manufacturer, "-"),
27 eboard->name,26 eboard->name,
28 strsep(&tmp_bios_vendor, "-"),27 strsep(&tmp_bios_vendor, "-"),
29 einter->description,28 einter->description,
30 einter->size,
31 especial->special_name);29 especial->special_name);
32}30}
33static struct kobj_attribute boardinfo_attr = __ATTR(boardinfo, 0444,31static struct kobj_attribute boardinfo_attr = __ATTR(boardinfo, 0444,
arch/mips/loongson64/env.c+2−1
@@ -17,6 +17,7 @@ · 16 unmodified lines
17#include <linux/dma-map-ops.h>17#include <linux/dma-map-ops.h>
18#include <linux/export.h>18#include <linux/export.h>
19#include <linux/pci_ids.h>19#include <linux/pci_ids.h>
20#include <linux/string_choices.h>
20#include <asm/bootinfo.h>21#include <asm/bootinfo.h>
21#include <loongson.h>22#include <loongson.h>
22#include <boot_param.h>23#include <boot_param.h>
@@ -162,7 +163,7 @@ void __init prom_lefi_init_env(void) · 139 unmodified lines
162 dma_default_coherent = !eirq_source->dma_noncoherent;163 dma_default_coherent = !eirq_source->dma_noncoherent;
163 }164 }
164 165
165 pr_info("Firmware: Coherent DMA: %s\n", dma_default_coherent ? "on" : "off");166 pr_info("Firmware: Coherent DMA: %s\n", str_on_off(dma_default_coherent));
166 167
167 loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm;168 loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm;
168 loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;169 loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;
arch/mips/math-emu/cp1emu.c+1−1
@@ -1660,7 +1660,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, · 1659 unmodified lines
1660 break;1660 break;
1661 }1661 }
1662 1662
1663 case 0x3:1663 case 0x7:
1664 if (MIPSInst_FUNC(ir) != pfetch_op)1664 if (MIPSInst_FUNC(ir) != pfetch_op)
1665 return SIGILL;1665 return SIGILL;
1666 1666
arch/mips/pci/pci-legacy.c+8−0
@@ -29,6 +29,14 @@ static LIST_HEAD(controllers); · 28 unmodified lines
29 29
30static int pci_initialized;30static int pci_initialized;
31 31
32unsigned long pci_address_to_pio(phys_addr_t address)
33{
34 if (address > IO_SPACE_LIMIT)
35 return (unsigned long)-1;
36
37 return (unsigned long) address;
38}
39
32/*40/*
33 * We need to avoid collisions with `mirrored' VGA ports41 * We need to avoid collisions with `mirrored' VGA ports
34 * and other strange ISA hardware, so we always want the42 * and other strange ISA hardware, so we always want the

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